DAGCombiner.cpp revision 704e1a0f044614e6d2da236380c890fa5f2d1e03
1//===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run 11// both before and after the DAG is legalized. 12// 13// This pass is not a substitute for the LLVM IR instcombine pass. This pass is 14// primarily intended to handle simplification opportunities that are implicit 15// in the LLVM IR and exposed by the various codegen lowering phases. 16// 17//===----------------------------------------------------------------------===// 18 19#define DEBUG_TYPE "dagcombine" 20#include "llvm/CodeGen/SelectionDAG.h" 21#include "llvm/DerivedTypes.h" 22#include "llvm/LLVMContext.h" 23#include "llvm/CodeGen/MachineFunction.h" 24#include "llvm/CodeGen/MachineFrameInfo.h" 25#include "llvm/Analysis/AliasAnalysis.h" 26#include "llvm/Target/TargetData.h" 27#include "llvm/Target/TargetLowering.h" 28#include "llvm/Target/TargetMachine.h" 29#include "llvm/Target/TargetOptions.h" 30#include "llvm/ADT/SmallPtrSet.h" 31#include "llvm/ADT/Statistic.h" 32#include "llvm/Support/CommandLine.h" 33#include "llvm/Support/Debug.h" 34#include "llvm/Support/ErrorHandling.h" 35#include "llvm/Support/MathExtras.h" 36#include "llvm/Support/raw_ostream.h" 37#include <algorithm> 38using namespace llvm; 39 40STATISTIC(NodesCombined , "Number of dag nodes combined"); 41STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created"); 42STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created"); 43STATISTIC(OpsNarrowed , "Number of load/op/store narrowed"); 44STATISTIC(LdStFP2Int , "Number of fp load/store pairs transformed to int"); 45 46namespace { 47 static cl::opt<bool> 48 CombinerAA("combiner-alias-analysis", cl::Hidden, 49 cl::desc("Turn on alias analysis during testing")); 50 51 static cl::opt<bool> 52 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden, 53 cl::desc("Include global information in alias analysis")); 54 55//------------------------------ DAGCombiner ---------------------------------// 56 57 class DAGCombiner { 58 SelectionDAG &DAG; 59 const TargetLowering &TLI; 60 CombineLevel Level; 61 CodeGenOpt::Level OptLevel; 62 bool LegalOperations; 63 bool LegalTypes; 64 65 // Worklist of all of the nodes that need to be simplified. 66 std::vector<SDNode*> WorkList; 67 68 // AA - Used for DAG load/store alias analysis. 69 AliasAnalysis &AA; 70 71 /// AddUsersToWorkList - When an instruction is simplified, add all users of 72 /// the instruction to the work lists because they might get more simplified 73 /// now. 74 /// 75 void AddUsersToWorkList(SDNode *N) { 76 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 77 UI != UE; ++UI) 78 AddToWorkList(*UI); 79 } 80 81 /// visit - call the node-specific routine that knows how to fold each 82 /// particular type of node. 83 SDValue visit(SDNode *N); 84 85 public: 86 /// AddToWorkList - Add to the work list making sure it's instance is at the 87 /// the back (next to be processed.) 88 void AddToWorkList(SDNode *N) { 89 removeFromWorkList(N); 90 WorkList.push_back(N); 91 } 92 93 /// removeFromWorkList - remove all instances of N from the worklist. 94 /// 95 void removeFromWorkList(SDNode *N) { 96 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N), 97 WorkList.end()); 98 } 99 100 SDValue CombineTo(SDNode *N, const SDValue *To, unsigned NumTo, 101 bool AddTo = true); 102 103 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true) { 104 return CombineTo(N, &Res, 1, AddTo); 105 } 106 107 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, 108 bool AddTo = true) { 109 SDValue To[] = { Res0, Res1 }; 110 return CombineTo(N, To, 2, AddTo); 111 } 112 113 void CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO); 114 115 private: 116 117 /// SimplifyDemandedBits - Check the specified integer node value to see if 118 /// it can be simplified or if things it uses can be simplified by bit 119 /// propagation. If so, return true. 120 bool SimplifyDemandedBits(SDValue Op) { 121 unsigned BitWidth = Op.getValueType().getScalarType().getSizeInBits(); 122 APInt Demanded = APInt::getAllOnesValue(BitWidth); 123 return SimplifyDemandedBits(Op, Demanded); 124 } 125 126 bool SimplifyDemandedBits(SDValue Op, const APInt &Demanded); 127 128 bool CombineToPreIndexedLoadStore(SDNode *N); 129 bool CombineToPostIndexedLoadStore(SDNode *N); 130 131 void ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad); 132 SDValue PromoteOperand(SDValue Op, EVT PVT, bool &Replace); 133 SDValue SExtPromoteOperand(SDValue Op, EVT PVT); 134 SDValue ZExtPromoteOperand(SDValue Op, EVT PVT); 135 SDValue PromoteIntBinOp(SDValue Op); 136 SDValue PromoteIntShiftOp(SDValue Op); 137 SDValue PromoteExtend(SDValue Op); 138 bool PromoteLoad(SDValue Op); 139 140 void ExtendSetCCUses(SmallVector<SDNode*, 4> SetCCs, 141 SDValue Trunc, SDValue ExtLoad, DebugLoc DL, 142 ISD::NodeType ExtType); 143 144 /// combine - call the node-specific routine that knows how to fold each 145 /// particular type of node. If that doesn't do anything, try the 146 /// target-specific DAG combines. 147 SDValue combine(SDNode *N); 148 149 // Visitation implementation - Implement dag node combining for different 150 // node types. The semantics are as follows: 151 // Return Value: 152 // SDValue.getNode() == 0 - No change was made 153 // SDValue.getNode() == N - N was replaced, is dead and has been handled. 154 // otherwise - N should be replaced by the returned Operand. 155 // 156 SDValue visitTokenFactor(SDNode *N); 157 SDValue visitMERGE_VALUES(SDNode *N); 158 SDValue visitADD(SDNode *N); 159 SDValue visitSUB(SDNode *N); 160 SDValue visitADDC(SDNode *N); 161 SDValue visitSUBC(SDNode *N); 162 SDValue visitADDE(SDNode *N); 163 SDValue visitSUBE(SDNode *N); 164 SDValue visitMUL(SDNode *N); 165 SDValue visitSDIV(SDNode *N); 166 SDValue visitUDIV(SDNode *N); 167 SDValue visitSREM(SDNode *N); 168 SDValue visitUREM(SDNode *N); 169 SDValue visitMULHU(SDNode *N); 170 SDValue visitMULHS(SDNode *N); 171 SDValue visitSMUL_LOHI(SDNode *N); 172 SDValue visitUMUL_LOHI(SDNode *N); 173 SDValue visitSMULO(SDNode *N); 174 SDValue visitUMULO(SDNode *N); 175 SDValue visitSDIVREM(SDNode *N); 176 SDValue visitUDIVREM(SDNode *N); 177 SDValue visitAND(SDNode *N); 178 SDValue visitOR(SDNode *N); 179 SDValue visitXOR(SDNode *N); 180 SDValue SimplifyVBinOp(SDNode *N); 181 SDValue visitSHL(SDNode *N); 182 SDValue visitSRA(SDNode *N); 183 SDValue visitSRL(SDNode *N); 184 SDValue visitCTLZ(SDNode *N); 185 SDValue visitCTLZ_ZERO_UNDEF(SDNode *N); 186 SDValue visitCTTZ(SDNode *N); 187 SDValue visitCTTZ_ZERO_UNDEF(SDNode *N); 188 SDValue visitCTPOP(SDNode *N); 189 SDValue visitSELECT(SDNode *N); 190 SDValue visitSELECT_CC(SDNode *N); 191 SDValue visitSETCC(SDNode *N); 192 SDValue visitSIGN_EXTEND(SDNode *N); 193 SDValue visitZERO_EXTEND(SDNode *N); 194 SDValue visitANY_EXTEND(SDNode *N); 195 SDValue visitSIGN_EXTEND_INREG(SDNode *N); 196 SDValue visitTRUNCATE(SDNode *N); 197 SDValue visitBITCAST(SDNode *N); 198 SDValue visitBUILD_PAIR(SDNode *N); 199 SDValue visitFADD(SDNode *N); 200 SDValue visitFSUB(SDNode *N); 201 SDValue visitFMUL(SDNode *N); 202 SDValue visitFDIV(SDNode *N); 203 SDValue visitFREM(SDNode *N); 204 SDValue visitFCOPYSIGN(SDNode *N); 205 SDValue visitSINT_TO_FP(SDNode *N); 206 SDValue visitUINT_TO_FP(SDNode *N); 207 SDValue visitFP_TO_SINT(SDNode *N); 208 SDValue visitFP_TO_UINT(SDNode *N); 209 SDValue visitFP_ROUND(SDNode *N); 210 SDValue visitFP_ROUND_INREG(SDNode *N); 211 SDValue visitFP_EXTEND(SDNode *N); 212 SDValue visitFNEG(SDNode *N); 213 SDValue visitFABS(SDNode *N); 214 SDValue visitBRCOND(SDNode *N); 215 SDValue visitBR_CC(SDNode *N); 216 SDValue visitLOAD(SDNode *N); 217 SDValue visitSTORE(SDNode *N); 218 SDValue visitINSERT_VECTOR_ELT(SDNode *N); 219 SDValue visitEXTRACT_VECTOR_ELT(SDNode *N); 220 SDValue visitBUILD_VECTOR(SDNode *N); 221 SDValue visitCONCAT_VECTORS(SDNode *N); 222 SDValue visitEXTRACT_SUBVECTOR(SDNode *N); 223 SDValue visitVECTOR_SHUFFLE(SDNode *N); 224 SDValue visitMEMBARRIER(SDNode *N); 225 226 SDValue XformToShuffleWithZero(SDNode *N); 227 SDValue ReassociateOps(unsigned Opc, DebugLoc DL, SDValue LHS, SDValue RHS); 228 229 SDValue visitShiftByConstant(SDNode *N, unsigned Amt); 230 231 bool SimplifySelectOps(SDNode *SELECT, SDValue LHS, SDValue RHS); 232 SDValue SimplifyBinOpWithSameOpcodeHands(SDNode *N); 233 SDValue SimplifySelect(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2); 234 SDValue SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2, 235 SDValue N3, ISD::CondCode CC, 236 bool NotExtCompare = false); 237 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond, 238 DebugLoc DL, bool foldBooleans = true); 239 SDValue SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 240 unsigned HiOp); 241 SDValue CombineConsecutiveLoads(SDNode *N, EVT VT); 242 SDValue ConstantFoldBITCASTofBUILD_VECTOR(SDNode *, EVT); 243 SDValue BuildSDIV(SDNode *N); 244 SDValue BuildUDIV(SDNode *N); 245 SDValue MatchBSwapHWordLow(SDNode *N, SDValue N0, SDValue N1, 246 bool DemandHighBits = true); 247 SDValue MatchBSwapHWord(SDNode *N, SDValue N0, SDValue N1); 248 SDNode *MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL); 249 SDValue ReduceLoadWidth(SDNode *N); 250 SDValue ReduceLoadOpStoreWidth(SDNode *N); 251 SDValue TransformFPLoadStorePair(SDNode *N); 252 253 SDValue GetDemandedBits(SDValue V, const APInt &Mask); 254 255 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 256 /// looking for aliasing nodes and adding them to the Aliases vector. 257 void GatherAllAliases(SDNode *N, SDValue OriginalChain, 258 SmallVector<SDValue, 8> &Aliases); 259 260 /// isAlias - Return true if there is any possibility that the two addresses 261 /// overlap. 262 bool isAlias(SDValue Ptr1, int64_t Size1, 263 const Value *SrcValue1, int SrcValueOffset1, 264 unsigned SrcValueAlign1, 265 const MDNode *TBAAInfo1, 266 SDValue Ptr2, int64_t Size2, 267 const Value *SrcValue2, int SrcValueOffset2, 268 unsigned SrcValueAlign2, 269 const MDNode *TBAAInfo2) const; 270 271 /// FindAliasInfo - Extracts the relevant alias information from the memory 272 /// node. Returns true if the operand was a load. 273 bool FindAliasInfo(SDNode *N, 274 SDValue &Ptr, int64_t &Size, 275 const Value *&SrcValue, int &SrcValueOffset, 276 unsigned &SrcValueAlignment, 277 const MDNode *&TBAAInfo) const; 278 279 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, 280 /// looking for a better chain (aliasing node.) 281 SDValue FindBetterChain(SDNode *N, SDValue Chain); 282 283 public: 284 DAGCombiner(SelectionDAG &D, AliasAnalysis &A, CodeGenOpt::Level OL) 285 : DAG(D), TLI(D.getTargetLoweringInfo()), Level(BeforeLegalizeTypes), 286 OptLevel(OL), LegalOperations(false), LegalTypes(false), AA(A) {} 287 288 /// Run - runs the dag combiner on all nodes in the work list 289 void Run(CombineLevel AtLevel); 290 291 SelectionDAG &getDAG() const { return DAG; } 292 293 /// getShiftAmountTy - Returns a type large enough to hold any valid 294 /// shift amount - before type legalization these can be huge. 295 EVT getShiftAmountTy(EVT LHSTy) { 296 return LegalTypes ? TLI.getShiftAmountTy(LHSTy) : TLI.getPointerTy(); 297 } 298 299 /// isTypeLegal - This method returns true if we are running before type 300 /// legalization or if the specified VT is legal. 301 bool isTypeLegal(const EVT &VT) { 302 if (!LegalTypes) return true; 303 return TLI.isTypeLegal(VT); 304 } 305 }; 306} 307 308 309namespace { 310/// WorkListRemover - This class is a DAGUpdateListener that removes any deleted 311/// nodes from the worklist. 312class WorkListRemover : public SelectionDAG::DAGUpdateListener { 313 DAGCombiner &DC; 314public: 315 explicit WorkListRemover(DAGCombiner &dc) : DC(dc) {} 316 317 virtual void NodeDeleted(SDNode *N, SDNode *E) { 318 DC.removeFromWorkList(N); 319 } 320 321 virtual void NodeUpdated(SDNode *N) { 322 // Ignore updates. 323 } 324}; 325} 326 327//===----------------------------------------------------------------------===// 328// TargetLowering::DAGCombinerInfo implementation 329//===----------------------------------------------------------------------===// 330 331void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) { 332 ((DAGCombiner*)DC)->AddToWorkList(N); 333} 334 335void TargetLowering::DAGCombinerInfo::RemoveFromWorklist(SDNode *N) { 336 ((DAGCombiner*)DC)->removeFromWorkList(N); 337} 338 339SDValue TargetLowering::DAGCombinerInfo:: 340CombineTo(SDNode *N, const std::vector<SDValue> &To, bool AddTo) { 341 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size(), AddTo); 342} 343 344SDValue TargetLowering::DAGCombinerInfo:: 345CombineTo(SDNode *N, SDValue Res, bool AddTo) { 346 return ((DAGCombiner*)DC)->CombineTo(N, Res, AddTo); 347} 348 349 350SDValue TargetLowering::DAGCombinerInfo:: 351CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo) { 352 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1, AddTo); 353} 354 355void TargetLowering::DAGCombinerInfo:: 356CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) { 357 return ((DAGCombiner*)DC)->CommitTargetLoweringOpt(TLO); 358} 359 360//===----------------------------------------------------------------------===// 361// Helper Functions 362//===----------------------------------------------------------------------===// 363 364/// isNegatibleForFree - Return 1 if we can compute the negated form of the 365/// specified expression for the same cost as the expression itself, or 2 if we 366/// can compute the negated form more cheaply than the expression itself. 367static char isNegatibleForFree(SDValue Op, bool LegalOperations, 368 const TargetOptions *Options, 369 unsigned Depth = 0) { 370 // No compile time optimizations on this type. 371 if (Op.getValueType() == MVT::ppcf128) 372 return 0; 373 374 // fneg is removable even if it has multiple uses. 375 if (Op.getOpcode() == ISD::FNEG) return 2; 376 377 // Don't allow anything with multiple uses. 378 if (!Op.hasOneUse()) return 0; 379 380 // Don't recurse exponentially. 381 if (Depth > 6) return 0; 382 383 switch (Op.getOpcode()) { 384 default: return false; 385 case ISD::ConstantFP: 386 // Don't invert constant FP values after legalize. The negated constant 387 // isn't necessarily legal. 388 return LegalOperations ? 0 : 1; 389 case ISD::FADD: 390 // FIXME: determine better conditions for this xform. 391 if (!Options->UnsafeFPMath) return 0; 392 393 // fold (fsub (fadd A, B)) -> (fsub (fneg A), B) 394 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, Options, 395 Depth + 1)) 396 return V; 397 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A) 398 return isNegatibleForFree(Op.getOperand(1), LegalOperations, Options, 399 Depth + 1); 400 case ISD::FSUB: 401 // We can't turn -(A-B) into B-A when we honor signed zeros. 402 if (!Options->UnsafeFPMath) return 0; 403 404 // fold (fneg (fsub A, B)) -> (fsub B, A) 405 return 1; 406 407 case ISD::FMUL: 408 case ISD::FDIV: 409 if (Options->HonorSignDependentRoundingFPMath()) return 0; 410 411 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) or (fmul X, (fneg Y)) 412 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, Options, 413 Depth + 1)) 414 return V; 415 416 return isNegatibleForFree(Op.getOperand(1), LegalOperations, Options, 417 Depth + 1); 418 419 case ISD::FP_EXTEND: 420 case ISD::FP_ROUND: 421 case ISD::FSIN: 422 return isNegatibleForFree(Op.getOperand(0), LegalOperations, Options, 423 Depth + 1); 424 } 425} 426 427/// GetNegatedExpression - If isNegatibleForFree returns true, this function 428/// returns the newly negated expression. 429static SDValue GetNegatedExpression(SDValue Op, SelectionDAG &DAG, 430 bool LegalOperations, unsigned Depth = 0) { 431 // fneg is removable even if it has multiple uses. 432 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0); 433 434 // Don't allow anything with multiple uses. 435 assert(Op.hasOneUse() && "Unknown reuse!"); 436 437 assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree"); 438 switch (Op.getOpcode()) { 439 default: llvm_unreachable("Unknown code"); 440 case ISD::ConstantFP: { 441 APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF(); 442 V.changeSign(); 443 return DAG.getConstantFP(V, Op.getValueType()); 444 } 445 case ISD::FADD: 446 // FIXME: determine better conditions for this xform. 447 assert(DAG.getTarget().Options.UnsafeFPMath); 448 449 // fold (fneg (fadd A, B)) -> (fsub (fneg A), B) 450 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, 451 &DAG.getTarget().Options, Depth+1)) 452 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 453 GetNegatedExpression(Op.getOperand(0), DAG, 454 LegalOperations, Depth+1), 455 Op.getOperand(1)); 456 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A) 457 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 458 GetNegatedExpression(Op.getOperand(1), DAG, 459 LegalOperations, Depth+1), 460 Op.getOperand(0)); 461 case ISD::FSUB: 462 // We can't turn -(A-B) into B-A when we honor signed zeros. 463 assert(DAG.getTarget().Options.UnsafeFPMath); 464 465 // fold (fneg (fsub 0, B)) -> B 466 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(Op.getOperand(0))) 467 if (N0CFP->getValueAPF().isZero()) 468 return Op.getOperand(1); 469 470 // fold (fneg (fsub A, B)) -> (fsub B, A) 471 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 472 Op.getOperand(1), Op.getOperand(0)); 473 474 case ISD::FMUL: 475 case ISD::FDIV: 476 assert(!DAG.getTarget().Options.HonorSignDependentRoundingFPMath()); 477 478 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) 479 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, 480 &DAG.getTarget().Options, Depth+1)) 481 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 482 GetNegatedExpression(Op.getOperand(0), DAG, 483 LegalOperations, Depth+1), 484 Op.getOperand(1)); 485 486 // fold (fneg (fmul X, Y)) -> (fmul X, (fneg Y)) 487 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 488 Op.getOperand(0), 489 GetNegatedExpression(Op.getOperand(1), DAG, 490 LegalOperations, Depth+1)); 491 492 case ISD::FP_EXTEND: 493 case ISD::FSIN: 494 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 495 GetNegatedExpression(Op.getOperand(0), DAG, 496 LegalOperations, Depth+1)); 497 case ISD::FP_ROUND: 498 return DAG.getNode(ISD::FP_ROUND, Op.getDebugLoc(), Op.getValueType(), 499 GetNegatedExpression(Op.getOperand(0), DAG, 500 LegalOperations, Depth+1), 501 Op.getOperand(1)); 502 } 503} 504 505 506// isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc 507// that selects between the values 1 and 0, making it equivalent to a setcc. 508// Also, set the incoming LHS, RHS, and CC references to the appropriate 509// nodes based on the type of node we are checking. This simplifies life a 510// bit for the callers. 511static bool isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS, 512 SDValue &CC) { 513 if (N.getOpcode() == ISD::SETCC) { 514 LHS = N.getOperand(0); 515 RHS = N.getOperand(1); 516 CC = N.getOperand(2); 517 return true; 518 } 519 if (N.getOpcode() == ISD::SELECT_CC && 520 N.getOperand(2).getOpcode() == ISD::Constant && 521 N.getOperand(3).getOpcode() == ISD::Constant && 522 cast<ConstantSDNode>(N.getOperand(2))->getAPIntValue() == 1 && 523 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) { 524 LHS = N.getOperand(0); 525 RHS = N.getOperand(1); 526 CC = N.getOperand(4); 527 return true; 528 } 529 return false; 530} 531 532// isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only 533// one use. If this is true, it allows the users to invert the operation for 534// free when it is profitable to do so. 535static bool isOneUseSetCC(SDValue N) { 536 SDValue N0, N1, N2; 537 if (isSetCCEquivalent(N, N0, N1, N2) && N.getNode()->hasOneUse()) 538 return true; 539 return false; 540} 541 542SDValue DAGCombiner::ReassociateOps(unsigned Opc, DebugLoc DL, 543 SDValue N0, SDValue N1) { 544 EVT VT = N0.getValueType(); 545 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) { 546 if (isa<ConstantSDNode>(N1)) { 547 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2)) 548 SDValue OpNode = 549 DAG.FoldConstantArithmetic(Opc, VT, 550 cast<ConstantSDNode>(N0.getOperand(1)), 551 cast<ConstantSDNode>(N1)); 552 return DAG.getNode(Opc, DL, VT, N0.getOperand(0), OpNode); 553 } 554 if (N0.hasOneUse()) { 555 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use 556 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT, 557 N0.getOperand(0), N1); 558 AddToWorkList(OpNode.getNode()); 559 return DAG.getNode(Opc, DL, VT, OpNode, N0.getOperand(1)); 560 } 561 } 562 563 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) { 564 if (isa<ConstantSDNode>(N0)) { 565 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2)) 566 SDValue OpNode = 567 DAG.FoldConstantArithmetic(Opc, VT, 568 cast<ConstantSDNode>(N1.getOperand(1)), 569 cast<ConstantSDNode>(N0)); 570 return DAG.getNode(Opc, DL, VT, N1.getOperand(0), OpNode); 571 } 572 if (N1.hasOneUse()) { 573 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use 574 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT, 575 N1.getOperand(0), N0); 576 AddToWorkList(OpNode.getNode()); 577 return DAG.getNode(Opc, DL, VT, OpNode, N1.getOperand(1)); 578 } 579 } 580 581 return SDValue(); 582} 583 584SDValue DAGCombiner::CombineTo(SDNode *N, const SDValue *To, unsigned NumTo, 585 bool AddTo) { 586 assert(N->getNumValues() == NumTo && "Broken CombineTo call!"); 587 ++NodesCombined; 588 DEBUG(dbgs() << "\nReplacing.1 "; 589 N->dump(&DAG); 590 dbgs() << "\nWith: "; 591 To[0].getNode()->dump(&DAG); 592 dbgs() << " and " << NumTo-1 << " other values\n"; 593 for (unsigned i = 0, e = NumTo; i != e; ++i) 594 assert((!To[i].getNode() || 595 N->getValueType(i) == To[i].getValueType()) && 596 "Cannot combine value to value of different type!")); 597 WorkListRemover DeadNodes(*this); 598 DAG.ReplaceAllUsesWith(N, To, &DeadNodes); 599 600 if (AddTo) { 601 // Push the new nodes and any users onto the worklist 602 for (unsigned i = 0, e = NumTo; i != e; ++i) { 603 if (To[i].getNode()) { 604 AddToWorkList(To[i].getNode()); 605 AddUsersToWorkList(To[i].getNode()); 606 } 607 } 608 } 609 610 // Finally, if the node is now dead, remove it from the graph. The node 611 // may not be dead if the replacement process recursively simplified to 612 // something else needing this node. 613 if (N->use_empty()) { 614 // Nodes can be reintroduced into the worklist. Make sure we do not 615 // process a node that has been replaced. 616 removeFromWorkList(N); 617 618 // Finally, since the node is now dead, remove it from the graph. 619 DAG.DeleteNode(N); 620 } 621 return SDValue(N, 0); 622} 623 624void DAGCombiner:: 625CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) { 626 // Replace all uses. If any nodes become isomorphic to other nodes and 627 // are deleted, make sure to remove them from our worklist. 628 WorkListRemover DeadNodes(*this); 629 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &DeadNodes); 630 631 // Push the new node and any (possibly new) users onto the worklist. 632 AddToWorkList(TLO.New.getNode()); 633 AddUsersToWorkList(TLO.New.getNode()); 634 635 // Finally, if the node is now dead, remove it from the graph. The node 636 // may not be dead if the replacement process recursively simplified to 637 // something else needing this node. 638 if (TLO.Old.getNode()->use_empty()) { 639 removeFromWorkList(TLO.Old.getNode()); 640 641 // If the operands of this node are only used by the node, they will now 642 // be dead. Make sure to visit them first to delete dead nodes early. 643 for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands(); i != e; ++i) 644 if (TLO.Old.getNode()->getOperand(i).getNode()->hasOneUse()) 645 AddToWorkList(TLO.Old.getNode()->getOperand(i).getNode()); 646 647 DAG.DeleteNode(TLO.Old.getNode()); 648 } 649} 650 651/// SimplifyDemandedBits - Check the specified integer node value to see if 652/// it can be simplified or if things it uses can be simplified by bit 653/// propagation. If so, return true. 654bool DAGCombiner::SimplifyDemandedBits(SDValue Op, const APInt &Demanded) { 655 TargetLowering::TargetLoweringOpt TLO(DAG, LegalTypes, LegalOperations); 656 APInt KnownZero, KnownOne; 657 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO)) 658 return false; 659 660 // Revisit the node. 661 AddToWorkList(Op.getNode()); 662 663 // Replace the old value with the new one. 664 ++NodesCombined; 665 DEBUG(dbgs() << "\nReplacing.2 "; 666 TLO.Old.getNode()->dump(&DAG); 667 dbgs() << "\nWith: "; 668 TLO.New.getNode()->dump(&DAG); 669 dbgs() << '\n'); 670 671 CommitTargetLoweringOpt(TLO); 672 return true; 673} 674 675void DAGCombiner::ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad) { 676 DebugLoc dl = Load->getDebugLoc(); 677 EVT VT = Load->getValueType(0); 678 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, VT, SDValue(ExtLoad, 0)); 679 680 DEBUG(dbgs() << "\nReplacing.9 "; 681 Load->dump(&DAG); 682 dbgs() << "\nWith: "; 683 Trunc.getNode()->dump(&DAG); 684 dbgs() << '\n'); 685 WorkListRemover DeadNodes(*this); 686 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 0), Trunc, &DeadNodes); 687 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 1), SDValue(ExtLoad, 1), 688 &DeadNodes); 689 removeFromWorkList(Load); 690 DAG.DeleteNode(Load); 691 AddToWorkList(Trunc.getNode()); 692} 693 694SDValue DAGCombiner::PromoteOperand(SDValue Op, EVT PVT, bool &Replace) { 695 Replace = false; 696 DebugLoc dl = Op.getDebugLoc(); 697 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Op)) { 698 EVT MemVT = LD->getMemoryVT(); 699 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD) 700 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT) ? ISD::ZEXTLOAD 701 : ISD::EXTLOAD) 702 : LD->getExtensionType(); 703 Replace = true; 704 return DAG.getExtLoad(ExtType, dl, PVT, 705 LD->getChain(), LD->getBasePtr(), 706 LD->getPointerInfo(), 707 MemVT, LD->isVolatile(), 708 LD->isNonTemporal(), LD->getAlignment()); 709 } 710 711 unsigned Opc = Op.getOpcode(); 712 switch (Opc) { 713 default: break; 714 case ISD::AssertSext: 715 return DAG.getNode(ISD::AssertSext, dl, PVT, 716 SExtPromoteOperand(Op.getOperand(0), PVT), 717 Op.getOperand(1)); 718 case ISD::AssertZext: 719 return DAG.getNode(ISD::AssertZext, dl, PVT, 720 ZExtPromoteOperand(Op.getOperand(0), PVT), 721 Op.getOperand(1)); 722 case ISD::Constant: { 723 unsigned ExtOpc = 724 Op.getValueType().isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; 725 return DAG.getNode(ExtOpc, dl, PVT, Op); 726 } 727 } 728 729 if (!TLI.isOperationLegal(ISD::ANY_EXTEND, PVT)) 730 return SDValue(); 731 return DAG.getNode(ISD::ANY_EXTEND, dl, PVT, Op); 732} 733 734SDValue DAGCombiner::SExtPromoteOperand(SDValue Op, EVT PVT) { 735 if (!TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, PVT)) 736 return SDValue(); 737 EVT OldVT = Op.getValueType(); 738 DebugLoc dl = Op.getDebugLoc(); 739 bool Replace = false; 740 SDValue NewOp = PromoteOperand(Op, PVT, Replace); 741 if (NewOp.getNode() == 0) 742 return SDValue(); 743 AddToWorkList(NewOp.getNode()); 744 745 if (Replace) 746 ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode()); 747 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NewOp.getValueType(), NewOp, 748 DAG.getValueType(OldVT)); 749} 750 751SDValue DAGCombiner::ZExtPromoteOperand(SDValue Op, EVT PVT) { 752 EVT OldVT = Op.getValueType(); 753 DebugLoc dl = Op.getDebugLoc(); 754 bool Replace = false; 755 SDValue NewOp = PromoteOperand(Op, PVT, Replace); 756 if (NewOp.getNode() == 0) 757 return SDValue(); 758 AddToWorkList(NewOp.getNode()); 759 760 if (Replace) 761 ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode()); 762 return DAG.getZeroExtendInReg(NewOp, dl, OldVT); 763} 764 765/// PromoteIntBinOp - Promote the specified integer binary operation if the 766/// target indicates it is beneficial. e.g. On x86, it's usually better to 767/// promote i16 operations to i32 since i16 instructions are longer. 768SDValue DAGCombiner::PromoteIntBinOp(SDValue Op) { 769 if (!LegalOperations) 770 return SDValue(); 771 772 EVT VT = Op.getValueType(); 773 if (VT.isVector() || !VT.isInteger()) 774 return SDValue(); 775 776 // If operation type is 'undesirable', e.g. i16 on x86, consider 777 // promoting it. 778 unsigned Opc = Op.getOpcode(); 779 if (TLI.isTypeDesirableForOp(Opc, VT)) 780 return SDValue(); 781 782 EVT PVT = VT; 783 // Consult target whether it is a good idea to promote this operation and 784 // what's the right type to promote it to. 785 if (TLI.IsDesirableToPromoteOp(Op, PVT)) { 786 assert(PVT != VT && "Don't know what type to promote to!"); 787 788 bool Replace0 = false; 789 SDValue N0 = Op.getOperand(0); 790 SDValue NN0 = PromoteOperand(N0, PVT, Replace0); 791 if (NN0.getNode() == 0) 792 return SDValue(); 793 794 bool Replace1 = false; 795 SDValue N1 = Op.getOperand(1); 796 SDValue NN1; 797 if (N0 == N1) 798 NN1 = NN0; 799 else { 800 NN1 = PromoteOperand(N1, PVT, Replace1); 801 if (NN1.getNode() == 0) 802 return SDValue(); 803 } 804 805 AddToWorkList(NN0.getNode()); 806 if (NN1.getNode()) 807 AddToWorkList(NN1.getNode()); 808 809 if (Replace0) 810 ReplaceLoadWithPromotedLoad(N0.getNode(), NN0.getNode()); 811 if (Replace1) 812 ReplaceLoadWithPromotedLoad(N1.getNode(), NN1.getNode()); 813 814 DEBUG(dbgs() << "\nPromoting "; 815 Op.getNode()->dump(&DAG)); 816 DebugLoc dl = Op.getDebugLoc(); 817 return DAG.getNode(ISD::TRUNCATE, dl, VT, 818 DAG.getNode(Opc, dl, PVT, NN0, NN1)); 819 } 820 return SDValue(); 821} 822 823/// PromoteIntShiftOp - Promote the specified integer shift operation if the 824/// target indicates it is beneficial. e.g. On x86, it's usually better to 825/// promote i16 operations to i32 since i16 instructions are longer. 826SDValue DAGCombiner::PromoteIntShiftOp(SDValue Op) { 827 if (!LegalOperations) 828 return SDValue(); 829 830 EVT VT = Op.getValueType(); 831 if (VT.isVector() || !VT.isInteger()) 832 return SDValue(); 833 834 // If operation type is 'undesirable', e.g. i16 on x86, consider 835 // promoting it. 836 unsigned Opc = Op.getOpcode(); 837 if (TLI.isTypeDesirableForOp(Opc, VT)) 838 return SDValue(); 839 840 EVT PVT = VT; 841 // Consult target whether it is a good idea to promote this operation and 842 // what's the right type to promote it to. 843 if (TLI.IsDesirableToPromoteOp(Op, PVT)) { 844 assert(PVT != VT && "Don't know what type to promote to!"); 845 846 bool Replace = false; 847 SDValue N0 = Op.getOperand(0); 848 if (Opc == ISD::SRA) 849 N0 = SExtPromoteOperand(Op.getOperand(0), PVT); 850 else if (Opc == ISD::SRL) 851 N0 = ZExtPromoteOperand(Op.getOperand(0), PVT); 852 else 853 N0 = PromoteOperand(N0, PVT, Replace); 854 if (N0.getNode() == 0) 855 return SDValue(); 856 857 AddToWorkList(N0.getNode()); 858 if (Replace) 859 ReplaceLoadWithPromotedLoad(Op.getOperand(0).getNode(), N0.getNode()); 860 861 DEBUG(dbgs() << "\nPromoting "; 862 Op.getNode()->dump(&DAG)); 863 DebugLoc dl = Op.getDebugLoc(); 864 return DAG.getNode(ISD::TRUNCATE, dl, VT, 865 DAG.getNode(Opc, dl, PVT, N0, Op.getOperand(1))); 866 } 867 return SDValue(); 868} 869 870SDValue DAGCombiner::PromoteExtend(SDValue Op) { 871 if (!LegalOperations) 872 return SDValue(); 873 874 EVT VT = Op.getValueType(); 875 if (VT.isVector() || !VT.isInteger()) 876 return SDValue(); 877 878 // If operation type is 'undesirable', e.g. i16 on x86, consider 879 // promoting it. 880 unsigned Opc = Op.getOpcode(); 881 if (TLI.isTypeDesirableForOp(Opc, VT)) 882 return SDValue(); 883 884 EVT PVT = VT; 885 // Consult target whether it is a good idea to promote this operation and 886 // what's the right type to promote it to. 887 if (TLI.IsDesirableToPromoteOp(Op, PVT)) { 888 assert(PVT != VT && "Don't know what type to promote to!"); 889 // fold (aext (aext x)) -> (aext x) 890 // fold (aext (zext x)) -> (zext x) 891 // fold (aext (sext x)) -> (sext x) 892 DEBUG(dbgs() << "\nPromoting "; 893 Op.getNode()->dump(&DAG)); 894 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), VT, Op.getOperand(0)); 895 } 896 return SDValue(); 897} 898 899bool DAGCombiner::PromoteLoad(SDValue Op) { 900 if (!LegalOperations) 901 return false; 902 903 EVT VT = Op.getValueType(); 904 if (VT.isVector() || !VT.isInteger()) 905 return false; 906 907 // If operation type is 'undesirable', e.g. i16 on x86, consider 908 // promoting it. 909 unsigned Opc = Op.getOpcode(); 910 if (TLI.isTypeDesirableForOp(Opc, VT)) 911 return false; 912 913 EVT PVT = VT; 914 // Consult target whether it is a good idea to promote this operation and 915 // what's the right type to promote it to. 916 if (TLI.IsDesirableToPromoteOp(Op, PVT)) { 917 assert(PVT != VT && "Don't know what type to promote to!"); 918 919 DebugLoc dl = Op.getDebugLoc(); 920 SDNode *N = Op.getNode(); 921 LoadSDNode *LD = cast<LoadSDNode>(N); 922 EVT MemVT = LD->getMemoryVT(); 923 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD) 924 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT) ? ISD::ZEXTLOAD 925 : ISD::EXTLOAD) 926 : LD->getExtensionType(); 927 SDValue NewLD = DAG.getExtLoad(ExtType, dl, PVT, 928 LD->getChain(), LD->getBasePtr(), 929 LD->getPointerInfo(), 930 MemVT, LD->isVolatile(), 931 LD->isNonTemporal(), LD->getAlignment()); 932 SDValue Result = DAG.getNode(ISD::TRUNCATE, dl, VT, NewLD); 933 934 DEBUG(dbgs() << "\nPromoting "; 935 N->dump(&DAG); 936 dbgs() << "\nTo: "; 937 Result.getNode()->dump(&DAG); 938 dbgs() << '\n'); 939 WorkListRemover DeadNodes(*this); 940 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result, &DeadNodes); 941 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), NewLD.getValue(1), &DeadNodes); 942 removeFromWorkList(N); 943 DAG.DeleteNode(N); 944 AddToWorkList(Result.getNode()); 945 return true; 946 } 947 return false; 948} 949 950 951//===----------------------------------------------------------------------===// 952// Main DAG Combiner implementation 953//===----------------------------------------------------------------------===// 954 955void DAGCombiner::Run(CombineLevel AtLevel) { 956 // set the instance variables, so that the various visit routines may use it. 957 Level = AtLevel; 958 LegalOperations = Level >= AfterLegalizeVectorOps; 959 LegalTypes = Level >= AfterLegalizeTypes; 960 961 // Add all the dag nodes to the worklist. 962 WorkList.reserve(DAG.allnodes_size()); 963 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 964 E = DAG.allnodes_end(); I != E; ++I) 965 WorkList.push_back(I); 966 967 // Create a dummy node (which is not added to allnodes), that adds a reference 968 // to the root node, preventing it from being deleted, and tracking any 969 // changes of the root. 970 HandleSDNode Dummy(DAG.getRoot()); 971 972 // The root of the dag may dangle to deleted nodes until the dag combiner is 973 // done. Set it to null to avoid confusion. 974 DAG.setRoot(SDValue()); 975 976 // while the worklist isn't empty, inspect the node on the end of it and 977 // try and combine it. 978 while (!WorkList.empty()) { 979 SDNode *N = WorkList.back(); 980 WorkList.pop_back(); 981 982 // If N has no uses, it is dead. Make sure to revisit all N's operands once 983 // N is deleted from the DAG, since they too may now be dead or may have a 984 // reduced number of uses, allowing other xforms. 985 if (N->use_empty() && N != &Dummy) { 986 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 987 AddToWorkList(N->getOperand(i).getNode()); 988 989 DAG.DeleteNode(N); 990 continue; 991 } 992 993 SDValue RV = combine(N); 994 995 if (RV.getNode() == 0) 996 continue; 997 998 ++NodesCombined; 999 1000 // If we get back the same node we passed in, rather than a new node or 1001 // zero, we know that the node must have defined multiple values and 1002 // CombineTo was used. Since CombineTo takes care of the worklist 1003 // mechanics for us, we have no work to do in this case. 1004 if (RV.getNode() == N) 1005 continue; 1006 1007 assert(N->getOpcode() != ISD::DELETED_NODE && 1008 RV.getNode()->getOpcode() != ISD::DELETED_NODE && 1009 "Node was deleted but visit returned new node!"); 1010 1011 DEBUG(dbgs() << "\nReplacing.3 "; 1012 N->dump(&DAG); 1013 dbgs() << "\nWith: "; 1014 RV.getNode()->dump(&DAG); 1015 dbgs() << '\n'); 1016 1017 // Transfer debug value. 1018 DAG.TransferDbgValues(SDValue(N, 0), RV); 1019 WorkListRemover DeadNodes(*this); 1020 if (N->getNumValues() == RV.getNode()->getNumValues()) 1021 DAG.ReplaceAllUsesWith(N, RV.getNode(), &DeadNodes); 1022 else { 1023 assert(N->getValueType(0) == RV.getValueType() && 1024 N->getNumValues() == 1 && "Type mismatch"); 1025 SDValue OpV = RV; 1026 DAG.ReplaceAllUsesWith(N, &OpV, &DeadNodes); 1027 } 1028 1029 // Push the new node and any users onto the worklist 1030 AddToWorkList(RV.getNode()); 1031 AddUsersToWorkList(RV.getNode()); 1032 1033 // Add any uses of the old node to the worklist in case this node is the 1034 // last one that uses them. They may become dead after this node is 1035 // deleted. 1036 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 1037 AddToWorkList(N->getOperand(i).getNode()); 1038 1039 // Finally, if the node is now dead, remove it from the graph. The node 1040 // may not be dead if the replacement process recursively simplified to 1041 // something else needing this node. 1042 if (N->use_empty()) { 1043 // Nodes can be reintroduced into the worklist. Make sure we do not 1044 // process a node that has been replaced. 1045 removeFromWorkList(N); 1046 1047 // Finally, since the node is now dead, remove it from the graph. 1048 DAG.DeleteNode(N); 1049 } 1050 } 1051 1052 // If the root changed (e.g. it was a dead load, update the root). 1053 DAG.setRoot(Dummy.getValue()); 1054} 1055 1056SDValue DAGCombiner::visit(SDNode *N) { 1057 switch (N->getOpcode()) { 1058 default: break; 1059 case ISD::TokenFactor: return visitTokenFactor(N); 1060 case ISD::MERGE_VALUES: return visitMERGE_VALUES(N); 1061 case ISD::ADD: return visitADD(N); 1062 case ISD::SUB: return visitSUB(N); 1063 case ISD::ADDC: return visitADDC(N); 1064 case ISD::SUBC: return visitSUBC(N); 1065 case ISD::ADDE: return visitADDE(N); 1066 case ISD::SUBE: return visitSUBE(N); 1067 case ISD::MUL: return visitMUL(N); 1068 case ISD::SDIV: return visitSDIV(N); 1069 case ISD::UDIV: return visitUDIV(N); 1070 case ISD::SREM: return visitSREM(N); 1071 case ISD::UREM: return visitUREM(N); 1072 case ISD::MULHU: return visitMULHU(N); 1073 case ISD::MULHS: return visitMULHS(N); 1074 case ISD::SMUL_LOHI: return visitSMUL_LOHI(N); 1075 case ISD::UMUL_LOHI: return visitUMUL_LOHI(N); 1076 case ISD::SMULO: return visitSMULO(N); 1077 case ISD::UMULO: return visitUMULO(N); 1078 case ISD::SDIVREM: return visitSDIVREM(N); 1079 case ISD::UDIVREM: return visitUDIVREM(N); 1080 case ISD::AND: return visitAND(N); 1081 case ISD::OR: return visitOR(N); 1082 case ISD::XOR: return visitXOR(N); 1083 case ISD::SHL: return visitSHL(N); 1084 case ISD::SRA: return visitSRA(N); 1085 case ISD::SRL: return visitSRL(N); 1086 case ISD::CTLZ: return visitCTLZ(N); 1087 case ISD::CTLZ_ZERO_UNDEF: return visitCTLZ_ZERO_UNDEF(N); 1088 case ISD::CTTZ: return visitCTTZ(N); 1089 case ISD::CTTZ_ZERO_UNDEF: return visitCTTZ_ZERO_UNDEF(N); 1090 case ISD::CTPOP: return visitCTPOP(N); 1091 case ISD::SELECT: return visitSELECT(N); 1092 case ISD::SELECT_CC: return visitSELECT_CC(N); 1093 case ISD::SETCC: return visitSETCC(N); 1094 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N); 1095 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N); 1096 case ISD::ANY_EXTEND: return visitANY_EXTEND(N); 1097 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N); 1098 case ISD::TRUNCATE: return visitTRUNCATE(N); 1099 case ISD::BITCAST: return visitBITCAST(N); 1100 case ISD::BUILD_PAIR: return visitBUILD_PAIR(N); 1101 case ISD::FADD: return visitFADD(N); 1102 case ISD::FSUB: return visitFSUB(N); 1103 case ISD::FMUL: return visitFMUL(N); 1104 case ISD::FDIV: return visitFDIV(N); 1105 case ISD::FREM: return visitFREM(N); 1106 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N); 1107 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N); 1108 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N); 1109 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N); 1110 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N); 1111 case ISD::FP_ROUND: return visitFP_ROUND(N); 1112 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N); 1113 case ISD::FP_EXTEND: return visitFP_EXTEND(N); 1114 case ISD::FNEG: return visitFNEG(N); 1115 case ISD::FABS: return visitFABS(N); 1116 case ISD::BRCOND: return visitBRCOND(N); 1117 case ISD::BR_CC: return visitBR_CC(N); 1118 case ISD::LOAD: return visitLOAD(N); 1119 case ISD::STORE: return visitSTORE(N); 1120 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N); 1121 case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N); 1122 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N); 1123 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N); 1124 case ISD::EXTRACT_SUBVECTOR: return visitEXTRACT_SUBVECTOR(N); 1125 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N); 1126 case ISD::MEMBARRIER: return visitMEMBARRIER(N); 1127 } 1128 return SDValue(); 1129} 1130 1131SDValue DAGCombiner::combine(SDNode *N) { 1132 SDValue RV = visit(N); 1133 1134 // If nothing happened, try a target-specific DAG combine. 1135 if (RV.getNode() == 0) { 1136 assert(N->getOpcode() != ISD::DELETED_NODE && 1137 "Node was deleted but visit returned NULL!"); 1138 1139 if (N->getOpcode() >= ISD::BUILTIN_OP_END || 1140 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) { 1141 1142 // Expose the DAG combiner to the target combiner impls. 1143 TargetLowering::DAGCombinerInfo 1144 DagCombineInfo(DAG, !LegalTypes, !LegalOperations, false, this); 1145 1146 RV = TLI.PerformDAGCombine(N, DagCombineInfo); 1147 } 1148 } 1149 1150 // If nothing happened still, try promoting the operation. 1151 if (RV.getNode() == 0) { 1152 switch (N->getOpcode()) { 1153 default: break; 1154 case ISD::ADD: 1155 case ISD::SUB: 1156 case ISD::MUL: 1157 case ISD::AND: 1158 case ISD::OR: 1159 case ISD::XOR: 1160 RV = PromoteIntBinOp(SDValue(N, 0)); 1161 break; 1162 case ISD::SHL: 1163 case ISD::SRA: 1164 case ISD::SRL: 1165 RV = PromoteIntShiftOp(SDValue(N, 0)); 1166 break; 1167 case ISD::SIGN_EXTEND: 1168 case ISD::ZERO_EXTEND: 1169 case ISD::ANY_EXTEND: 1170 RV = PromoteExtend(SDValue(N, 0)); 1171 break; 1172 case ISD::LOAD: 1173 if (PromoteLoad(SDValue(N, 0))) 1174 RV = SDValue(N, 0); 1175 break; 1176 } 1177 } 1178 1179 // If N is a commutative binary node, try commuting it to enable more 1180 // sdisel CSE. 1181 if (RV.getNode() == 0 && 1182 SelectionDAG::isCommutativeBinOp(N->getOpcode()) && 1183 N->getNumValues() == 1) { 1184 SDValue N0 = N->getOperand(0); 1185 SDValue N1 = N->getOperand(1); 1186 1187 // Constant operands are canonicalized to RHS. 1188 if (isa<ConstantSDNode>(N0) || !isa<ConstantSDNode>(N1)) { 1189 SDValue Ops[] = { N1, N0 }; 1190 SDNode *CSENode = DAG.getNodeIfExists(N->getOpcode(), N->getVTList(), 1191 Ops, 2); 1192 if (CSENode) 1193 return SDValue(CSENode, 0); 1194 } 1195 } 1196 1197 return RV; 1198} 1199 1200/// getInputChainForNode - Given a node, return its input chain if it has one, 1201/// otherwise return a null sd operand. 1202static SDValue getInputChainForNode(SDNode *N) { 1203 if (unsigned NumOps = N->getNumOperands()) { 1204 if (N->getOperand(0).getValueType() == MVT::Other) 1205 return N->getOperand(0); 1206 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other) 1207 return N->getOperand(NumOps-1); 1208 for (unsigned i = 1; i < NumOps-1; ++i) 1209 if (N->getOperand(i).getValueType() == MVT::Other) 1210 return N->getOperand(i); 1211 } 1212 return SDValue(); 1213} 1214 1215SDValue DAGCombiner::visitTokenFactor(SDNode *N) { 1216 // If N has two operands, where one has an input chain equal to the other, 1217 // the 'other' chain is redundant. 1218 if (N->getNumOperands() == 2) { 1219 if (getInputChainForNode(N->getOperand(0).getNode()) == N->getOperand(1)) 1220 return N->getOperand(0); 1221 if (getInputChainForNode(N->getOperand(1).getNode()) == N->getOperand(0)) 1222 return N->getOperand(1); 1223 } 1224 1225 SmallVector<SDNode *, 8> TFs; // List of token factors to visit. 1226 SmallVector<SDValue, 8> Ops; // Ops for replacing token factor. 1227 SmallPtrSet<SDNode*, 16> SeenOps; 1228 bool Changed = false; // If we should replace this token factor. 1229 1230 // Start out with this token factor. 1231 TFs.push_back(N); 1232 1233 // Iterate through token factors. The TFs grows when new token factors are 1234 // encountered. 1235 for (unsigned i = 0; i < TFs.size(); ++i) { 1236 SDNode *TF = TFs[i]; 1237 1238 // Check each of the operands. 1239 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) { 1240 SDValue Op = TF->getOperand(i); 1241 1242 switch (Op.getOpcode()) { 1243 case ISD::EntryToken: 1244 // Entry tokens don't need to be added to the list. They are 1245 // rededundant. 1246 Changed = true; 1247 break; 1248 1249 case ISD::TokenFactor: 1250 if (Op.hasOneUse() && 1251 std::find(TFs.begin(), TFs.end(), Op.getNode()) == TFs.end()) { 1252 // Queue up for processing. 1253 TFs.push_back(Op.getNode()); 1254 // Clean up in case the token factor is removed. 1255 AddToWorkList(Op.getNode()); 1256 Changed = true; 1257 break; 1258 } 1259 // Fall thru 1260 1261 default: 1262 // Only add if it isn't already in the list. 1263 if (SeenOps.insert(Op.getNode())) 1264 Ops.push_back(Op); 1265 else 1266 Changed = true; 1267 break; 1268 } 1269 } 1270 } 1271 1272 SDValue Result; 1273 1274 // If we've change things around then replace token factor. 1275 if (Changed) { 1276 if (Ops.empty()) { 1277 // The entry token is the only possible outcome. 1278 Result = DAG.getEntryNode(); 1279 } else { 1280 // New and improved token factor. 1281 Result = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 1282 MVT::Other, &Ops[0], Ops.size()); 1283 } 1284 1285 // Don't add users to work list. 1286 return CombineTo(N, Result, false); 1287 } 1288 1289 return Result; 1290} 1291 1292/// MERGE_VALUES can always be eliminated. 1293SDValue DAGCombiner::visitMERGE_VALUES(SDNode *N) { 1294 WorkListRemover DeadNodes(*this); 1295 // Replacing results may cause a different MERGE_VALUES to suddenly 1296 // be CSE'd with N, and carry its uses with it. Iterate until no 1297 // uses remain, to ensure that the node can be safely deleted. 1298 do { 1299 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 1300 DAG.ReplaceAllUsesOfValueWith(SDValue(N, i), N->getOperand(i), 1301 &DeadNodes); 1302 } while (!N->use_empty()); 1303 removeFromWorkList(N); 1304 DAG.DeleteNode(N); 1305 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1306} 1307 1308static 1309SDValue combineShlAddConstant(DebugLoc DL, SDValue N0, SDValue N1, 1310 SelectionDAG &DAG) { 1311 EVT VT = N0.getValueType(); 1312 SDValue N00 = N0.getOperand(0); 1313 SDValue N01 = N0.getOperand(1); 1314 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01); 1315 1316 if (N01C && N00.getOpcode() == ISD::ADD && N00.getNode()->hasOneUse() && 1317 isa<ConstantSDNode>(N00.getOperand(1))) { 1318 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 1319 N0 = DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, 1320 DAG.getNode(ISD::SHL, N00.getDebugLoc(), VT, 1321 N00.getOperand(0), N01), 1322 DAG.getNode(ISD::SHL, N01.getDebugLoc(), VT, 1323 N00.getOperand(1), N01)); 1324 return DAG.getNode(ISD::ADD, DL, VT, N0, N1); 1325 } 1326 1327 return SDValue(); 1328} 1329 1330SDValue DAGCombiner::visitADD(SDNode *N) { 1331 SDValue N0 = N->getOperand(0); 1332 SDValue N1 = N->getOperand(1); 1333 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1334 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1335 EVT VT = N0.getValueType(); 1336 1337 // fold vector ops 1338 if (VT.isVector()) { 1339 SDValue FoldedVOp = SimplifyVBinOp(N); 1340 if (FoldedVOp.getNode()) return FoldedVOp; 1341 } 1342 1343 // fold (add x, undef) -> undef 1344 if (N0.getOpcode() == ISD::UNDEF) 1345 return N0; 1346 if (N1.getOpcode() == ISD::UNDEF) 1347 return N1; 1348 // fold (add c1, c2) -> c1+c2 1349 if (N0C && N1C) 1350 return DAG.FoldConstantArithmetic(ISD::ADD, VT, N0C, N1C); 1351 // canonicalize constant to RHS 1352 if (N0C && !N1C) 1353 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0); 1354 // fold (add x, 0) -> x 1355 if (N1C && N1C->isNullValue()) 1356 return N0; 1357 // fold (add Sym, c) -> Sym+c 1358 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0)) 1359 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA) && N1C && 1360 GA->getOpcode() == ISD::GlobalAddress) 1361 return DAG.getGlobalAddress(GA->getGlobal(), N1C->getDebugLoc(), VT, 1362 GA->getOffset() + 1363 (uint64_t)N1C->getSExtValue()); 1364 // fold ((c1-A)+c2) -> (c1+c2)-A 1365 if (N1C && N0.getOpcode() == ISD::SUB) 1366 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0))) 1367 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1368 DAG.getConstant(N1C->getAPIntValue()+ 1369 N0C->getAPIntValue(), VT), 1370 N0.getOperand(1)); 1371 // reassociate add 1372 SDValue RADD = ReassociateOps(ISD::ADD, N->getDebugLoc(), N0, N1); 1373 if (RADD.getNode() != 0) 1374 return RADD; 1375 // fold ((0-A) + B) -> B-A 1376 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) && 1377 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue()) 1378 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1, N0.getOperand(1)); 1379 // fold (A + (0-B)) -> A-B 1380 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) && 1381 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue()) 1382 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, N1.getOperand(1)); 1383 // fold (A+(B-A)) -> B 1384 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1)) 1385 return N1.getOperand(0); 1386 // fold ((B-A)+A) -> B 1387 if (N0.getOpcode() == ISD::SUB && N1 == N0.getOperand(1)) 1388 return N0.getOperand(0); 1389 // fold (A+(B-(A+C))) to (B-C) 1390 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD && 1391 N0 == N1.getOperand(1).getOperand(0)) 1392 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0), 1393 N1.getOperand(1).getOperand(1)); 1394 // fold (A+(B-(C+A))) to (B-C) 1395 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD && 1396 N0 == N1.getOperand(1).getOperand(1)) 1397 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0), 1398 N1.getOperand(1).getOperand(0)); 1399 // fold (A+((B-A)+or-C)) to (B+or-C) 1400 if ((N1.getOpcode() == ISD::SUB || N1.getOpcode() == ISD::ADD) && 1401 N1.getOperand(0).getOpcode() == ISD::SUB && 1402 N0 == N1.getOperand(0).getOperand(1)) 1403 return DAG.getNode(N1.getOpcode(), N->getDebugLoc(), VT, 1404 N1.getOperand(0).getOperand(0), N1.getOperand(1)); 1405 1406 // fold (A-B)+(C-D) to (A+C)-(B+D) when A or C is constant 1407 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB) { 1408 SDValue N00 = N0.getOperand(0); 1409 SDValue N01 = N0.getOperand(1); 1410 SDValue N10 = N1.getOperand(0); 1411 SDValue N11 = N1.getOperand(1); 1412 1413 if (isa<ConstantSDNode>(N00) || isa<ConstantSDNode>(N10)) 1414 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1415 DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, N00, N10), 1416 DAG.getNode(ISD::ADD, N1.getDebugLoc(), VT, N01, N11)); 1417 } 1418 1419 if (!VT.isVector() && SimplifyDemandedBits(SDValue(N, 0))) 1420 return SDValue(N, 0); 1421 1422 // fold (a+b) -> (a|b) iff a and b share no bits. 1423 if (VT.isInteger() && !VT.isVector()) { 1424 APInt LHSZero, LHSOne; 1425 APInt RHSZero, RHSOne; 1426 APInt Mask = APInt::getAllOnesValue(VT.getScalarType().getSizeInBits()); 1427 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 1428 1429 if (LHSZero.getBoolValue()) { 1430 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 1431 1432 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1433 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1434 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 1435 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 1436 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1); 1437 } 1438 } 1439 1440 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 1441 if (N0.getOpcode() == ISD::SHL && N0.getNode()->hasOneUse()) { 1442 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N0, N1, DAG); 1443 if (Result.getNode()) return Result; 1444 } 1445 if (N1.getOpcode() == ISD::SHL && N1.getNode()->hasOneUse()) { 1446 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N1, N0, DAG); 1447 if (Result.getNode()) return Result; 1448 } 1449 1450 // fold (add x, shl(0 - y, n)) -> sub(x, shl(y, n)) 1451 if (N1.getOpcode() == ISD::SHL && 1452 N1.getOperand(0).getOpcode() == ISD::SUB) 1453 if (ConstantSDNode *C = 1454 dyn_cast<ConstantSDNode>(N1.getOperand(0).getOperand(0))) 1455 if (C->getAPIntValue() == 0) 1456 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, 1457 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1458 N1.getOperand(0).getOperand(1), 1459 N1.getOperand(1))); 1460 if (N0.getOpcode() == ISD::SHL && 1461 N0.getOperand(0).getOpcode() == ISD::SUB) 1462 if (ConstantSDNode *C = 1463 dyn_cast<ConstantSDNode>(N0.getOperand(0).getOperand(0))) 1464 if (C->getAPIntValue() == 0) 1465 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1, 1466 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1467 N0.getOperand(0).getOperand(1), 1468 N0.getOperand(1))); 1469 1470 if (N1.getOpcode() == ISD::AND) { 1471 SDValue AndOp0 = N1.getOperand(0); 1472 ConstantSDNode *AndOp1 = dyn_cast<ConstantSDNode>(N1->getOperand(1)); 1473 unsigned NumSignBits = DAG.ComputeNumSignBits(AndOp0); 1474 unsigned DestBits = VT.getScalarType().getSizeInBits(); 1475 1476 // (add z, (and (sbbl x, x), 1)) -> (sub z, (sbbl x, x)) 1477 // and similar xforms where the inner op is either ~0 or 0. 1478 if (NumSignBits == DestBits && AndOp1 && AndOp1->isOne()) { 1479 DebugLoc DL = N->getDebugLoc(); 1480 return DAG.getNode(ISD::SUB, DL, VT, N->getOperand(0), AndOp0); 1481 } 1482 } 1483 1484 // add (sext i1), X -> sub X, (zext i1) 1485 if (N0.getOpcode() == ISD::SIGN_EXTEND && 1486 N0.getOperand(0).getValueType() == MVT::i1 && 1487 !TLI.isOperationLegal(ISD::SIGN_EXTEND, MVT::i1)) { 1488 DebugLoc DL = N->getDebugLoc(); 1489 SDValue ZExt = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0)); 1490 return DAG.getNode(ISD::SUB, DL, VT, N1, ZExt); 1491 } 1492 1493 return SDValue(); 1494} 1495 1496SDValue DAGCombiner::visitADDC(SDNode *N) { 1497 SDValue N0 = N->getOperand(0); 1498 SDValue N1 = N->getOperand(1); 1499 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1500 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1501 EVT VT = N0.getValueType(); 1502 1503 // If the flag result is dead, turn this into an ADD. 1504 if (!N->hasAnyUseOfValue(1)) 1505 return CombineTo(N, DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, N1), 1506 DAG.getNode(ISD::CARRY_FALSE, 1507 N->getDebugLoc(), MVT::Glue)); 1508 1509 // canonicalize constant to RHS. 1510 if (N0C && !N1C) 1511 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0); 1512 1513 // fold (addc x, 0) -> x + no carry out 1514 if (N1C && N1C->isNullValue()) 1515 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, 1516 N->getDebugLoc(), MVT::Glue)); 1517 1518 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits. 1519 APInt LHSZero, LHSOne; 1520 APInt RHSZero, RHSOne; 1521 APInt Mask = APInt::getAllOnesValue(VT.getScalarType().getSizeInBits()); 1522 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 1523 1524 if (LHSZero.getBoolValue()) { 1525 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 1526 1527 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1528 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1529 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 1530 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 1531 return CombineTo(N, DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1), 1532 DAG.getNode(ISD::CARRY_FALSE, 1533 N->getDebugLoc(), MVT::Glue)); 1534 } 1535 1536 return SDValue(); 1537} 1538 1539SDValue DAGCombiner::visitADDE(SDNode *N) { 1540 SDValue N0 = N->getOperand(0); 1541 SDValue N1 = N->getOperand(1); 1542 SDValue CarryIn = N->getOperand(2); 1543 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1544 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1545 1546 // canonicalize constant to RHS 1547 if (N0C && !N1C) 1548 return DAG.getNode(ISD::ADDE, N->getDebugLoc(), N->getVTList(), 1549 N1, N0, CarryIn); 1550 1551 // fold (adde x, y, false) -> (addc x, y) 1552 if (CarryIn.getOpcode() == ISD::CARRY_FALSE) 1553 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N0, N1); 1554 1555 return SDValue(); 1556} 1557 1558// Since it may not be valid to emit a fold to zero for vector initializers 1559// check if we can before folding. 1560static SDValue tryFoldToZero(DebugLoc DL, const TargetLowering &TLI, EVT VT, 1561 SelectionDAG &DAG, bool LegalOperations) { 1562 if (!VT.isVector()) { 1563 return DAG.getConstant(0, VT); 1564 } 1565 if (!LegalOperations || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) { 1566 // Produce a vector of zeros. 1567 SDValue El = DAG.getConstant(0, VT.getVectorElementType()); 1568 std::vector<SDValue> Ops(VT.getVectorNumElements(), El); 1569 return DAG.getNode(ISD::BUILD_VECTOR, DL, VT, 1570 &Ops[0], Ops.size()); 1571 } 1572 return SDValue(); 1573} 1574 1575SDValue DAGCombiner::visitSUB(SDNode *N) { 1576 SDValue N0 = N->getOperand(0); 1577 SDValue N1 = N->getOperand(1); 1578 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1579 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1580 ConstantSDNode *N1C1 = N1.getOpcode() != ISD::ADD ? 0 : 1581 dyn_cast<ConstantSDNode>(N1.getOperand(1).getNode()); 1582 EVT VT = N0.getValueType(); 1583 1584 // fold vector ops 1585 if (VT.isVector()) { 1586 SDValue FoldedVOp = SimplifyVBinOp(N); 1587 if (FoldedVOp.getNode()) return FoldedVOp; 1588 } 1589 1590 // fold (sub x, x) -> 0 1591 // FIXME: Refactor this and xor and other similar operations together. 1592 if (N0 == N1) 1593 return tryFoldToZero(N->getDebugLoc(), TLI, VT, DAG, LegalOperations); 1594 // fold (sub c1, c2) -> c1-c2 1595 if (N0C && N1C) 1596 return DAG.FoldConstantArithmetic(ISD::SUB, VT, N0C, N1C); 1597 // fold (sub x, c) -> (add x, -c) 1598 if (N1C) 1599 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, 1600 DAG.getConstant(-N1C->getAPIntValue(), VT)); 1601 // Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1) 1602 if (N0C && N0C->isAllOnesValue()) 1603 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0); 1604 // fold A-(A-B) -> B 1605 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(0)) 1606 return N1.getOperand(1); 1607 // fold (A+B)-A -> B 1608 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1) 1609 return N0.getOperand(1); 1610 // fold (A+B)-B -> A 1611 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1) 1612 return N0.getOperand(0); 1613 // fold C2-(A+C1) -> (C2-C1)-A 1614 if (N1.getOpcode() == ISD::ADD && N0C && N1C1) { 1615 SDValue NewC = DAG.getConstant((N0C->getAPIntValue() - N1C1->getAPIntValue()), VT); 1616 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, NewC, 1617 N1.getOperand(0)); 1618 } 1619 // fold ((A+(B+or-C))-B) -> A+or-C 1620 if (N0.getOpcode() == ISD::ADD && 1621 (N0.getOperand(1).getOpcode() == ISD::SUB || 1622 N0.getOperand(1).getOpcode() == ISD::ADD) && 1623 N0.getOperand(1).getOperand(0) == N1) 1624 return DAG.getNode(N0.getOperand(1).getOpcode(), N->getDebugLoc(), VT, 1625 N0.getOperand(0), N0.getOperand(1).getOperand(1)); 1626 // fold ((A+(C+B))-B) -> A+C 1627 if (N0.getOpcode() == ISD::ADD && 1628 N0.getOperand(1).getOpcode() == ISD::ADD && 1629 N0.getOperand(1).getOperand(1) == N1) 1630 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, 1631 N0.getOperand(0), N0.getOperand(1).getOperand(0)); 1632 // fold ((A-(B-C))-C) -> A-B 1633 if (N0.getOpcode() == ISD::SUB && 1634 N0.getOperand(1).getOpcode() == ISD::SUB && 1635 N0.getOperand(1).getOperand(1) == N1) 1636 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1637 N0.getOperand(0), N0.getOperand(1).getOperand(0)); 1638 1639 // If either operand of a sub is undef, the result is undef 1640 if (N0.getOpcode() == ISD::UNDEF) 1641 return N0; 1642 if (N1.getOpcode() == ISD::UNDEF) 1643 return N1; 1644 1645 // If the relocation model supports it, consider symbol offsets. 1646 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0)) 1647 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA)) { 1648 // fold (sub Sym, c) -> Sym-c 1649 if (N1C && GA->getOpcode() == ISD::GlobalAddress) 1650 return DAG.getGlobalAddress(GA->getGlobal(), N1C->getDebugLoc(), VT, 1651 GA->getOffset() - 1652 (uint64_t)N1C->getSExtValue()); 1653 // fold (sub Sym+c1, Sym+c2) -> c1-c2 1654 if (GlobalAddressSDNode *GB = dyn_cast<GlobalAddressSDNode>(N1)) 1655 if (GA->getGlobal() == GB->getGlobal()) 1656 return DAG.getConstant((uint64_t)GA->getOffset() - GB->getOffset(), 1657 VT); 1658 } 1659 1660 return SDValue(); 1661} 1662 1663SDValue DAGCombiner::visitSUBC(SDNode *N) { 1664 SDValue N0 = N->getOperand(0); 1665 SDValue N1 = N->getOperand(1); 1666 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1667 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1668 EVT VT = N0.getValueType(); 1669 1670 // If the flag result is dead, turn this into an SUB. 1671 if (!N->hasAnyUseOfValue(1)) 1672 return CombineTo(N, DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, N1), 1673 DAG.getNode(ISD::CARRY_FALSE, N->getDebugLoc(), 1674 MVT::Glue)); 1675 1676 // fold (subc x, x) -> 0 + no borrow 1677 if (N0 == N1) 1678 return CombineTo(N, DAG.getConstant(0, VT), 1679 DAG.getNode(ISD::CARRY_FALSE, N->getDebugLoc(), 1680 MVT::Glue)); 1681 1682 // fold (subc x, 0) -> x + no borrow 1683 if (N1C && N1C->isNullValue()) 1684 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, N->getDebugLoc(), 1685 MVT::Glue)); 1686 1687 // Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1) + no borrow 1688 if (N0C && N0C->isAllOnesValue()) 1689 return CombineTo(N, DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0), 1690 DAG.getNode(ISD::CARRY_FALSE, N->getDebugLoc(), 1691 MVT::Glue)); 1692 1693 return SDValue(); 1694} 1695 1696SDValue DAGCombiner::visitSUBE(SDNode *N) { 1697 SDValue N0 = N->getOperand(0); 1698 SDValue N1 = N->getOperand(1); 1699 SDValue CarryIn = N->getOperand(2); 1700 1701 // fold (sube x, y, false) -> (subc x, y) 1702 if (CarryIn.getOpcode() == ISD::CARRY_FALSE) 1703 return DAG.getNode(ISD::SUBC, N->getDebugLoc(), N->getVTList(), N0, N1); 1704 1705 return SDValue(); 1706} 1707 1708SDValue DAGCombiner::visitMUL(SDNode *N) { 1709 SDValue N0 = N->getOperand(0); 1710 SDValue N1 = N->getOperand(1); 1711 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1712 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1713 EVT VT = N0.getValueType(); 1714 1715 // fold vector ops 1716 if (VT.isVector()) { 1717 SDValue FoldedVOp = SimplifyVBinOp(N); 1718 if (FoldedVOp.getNode()) return FoldedVOp; 1719 } 1720 1721 // fold (mul x, undef) -> 0 1722 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1723 return DAG.getConstant(0, VT); 1724 // fold (mul c1, c2) -> c1*c2 1725 if (N0C && N1C) 1726 return DAG.FoldConstantArithmetic(ISD::MUL, VT, N0C, N1C); 1727 // canonicalize constant to RHS 1728 if (N0C && !N1C) 1729 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, N1, N0); 1730 // fold (mul x, 0) -> 0 1731 if (N1C && N1C->isNullValue()) 1732 return N1; 1733 // fold (mul x, -1) -> 0-x 1734 if (N1C && N1C->isAllOnesValue()) 1735 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1736 DAG.getConstant(0, VT), N0); 1737 // fold (mul x, (1 << c)) -> x << c 1738 if (N1C && N1C->getAPIntValue().isPowerOf2()) 1739 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 1740 DAG.getConstant(N1C->getAPIntValue().logBase2(), 1741 getShiftAmountTy(N0.getValueType()))); 1742 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c 1743 if (N1C && (-N1C->getAPIntValue()).isPowerOf2()) { 1744 unsigned Log2Val = (-N1C->getAPIntValue()).logBase2(); 1745 // FIXME: If the input is something that is easily negated (e.g. a 1746 // single-use add), we should put the negate there. 1747 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1748 DAG.getConstant(0, VT), 1749 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 1750 DAG.getConstant(Log2Val, 1751 getShiftAmountTy(N0.getValueType())))); 1752 } 1753 // (mul (shl X, c1), c2) -> (mul X, c2 << c1) 1754 if (N1C && N0.getOpcode() == ISD::SHL && 1755 isa<ConstantSDNode>(N0.getOperand(1))) { 1756 SDValue C3 = DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1757 N1, N0.getOperand(1)); 1758 AddToWorkList(C3.getNode()); 1759 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1760 N0.getOperand(0), C3); 1761 } 1762 1763 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one 1764 // use. 1765 { 1766 SDValue Sh(0,0), Y(0,0); 1767 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)). 1768 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) && 1769 N0.getNode()->hasOneUse()) { 1770 Sh = N0; Y = N1; 1771 } else if (N1.getOpcode() == ISD::SHL && 1772 isa<ConstantSDNode>(N1.getOperand(1)) && 1773 N1.getNode()->hasOneUse()) { 1774 Sh = N1; Y = N0; 1775 } 1776 1777 if (Sh.getNode()) { 1778 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1779 Sh.getOperand(0), Y); 1780 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1781 Mul, Sh.getOperand(1)); 1782 } 1783 } 1784 1785 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2) 1786 if (N1C && N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse() && 1787 isa<ConstantSDNode>(N0.getOperand(1))) 1788 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, 1789 DAG.getNode(ISD::MUL, N0.getDebugLoc(), VT, 1790 N0.getOperand(0), N1), 1791 DAG.getNode(ISD::MUL, N1.getDebugLoc(), VT, 1792 N0.getOperand(1), N1)); 1793 1794 // reassociate mul 1795 SDValue RMUL = ReassociateOps(ISD::MUL, N->getDebugLoc(), N0, N1); 1796 if (RMUL.getNode() != 0) 1797 return RMUL; 1798 1799 return SDValue(); 1800} 1801 1802SDValue DAGCombiner::visitSDIV(SDNode *N) { 1803 SDValue N0 = N->getOperand(0); 1804 SDValue N1 = N->getOperand(1); 1805 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1806 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1807 EVT VT = N->getValueType(0); 1808 1809 // fold vector ops 1810 if (VT.isVector()) { 1811 SDValue FoldedVOp = SimplifyVBinOp(N); 1812 if (FoldedVOp.getNode()) return FoldedVOp; 1813 } 1814 1815 // fold (sdiv c1, c2) -> c1/c2 1816 if (N0C && N1C && !N1C->isNullValue()) 1817 return DAG.FoldConstantArithmetic(ISD::SDIV, VT, N0C, N1C); 1818 // fold (sdiv X, 1) -> X 1819 if (N1C && N1C->getAPIntValue() == 1LL) 1820 return N0; 1821 // fold (sdiv X, -1) -> 0-X 1822 if (N1C && N1C->isAllOnesValue()) 1823 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1824 DAG.getConstant(0, VT), N0); 1825 // If we know the sign bits of both operands are zero, strength reduce to a 1826 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2 1827 if (!VT.isVector()) { 1828 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 1829 return DAG.getNode(ISD::UDIV, N->getDebugLoc(), N1.getValueType(), 1830 N0, N1); 1831 } 1832 // fold (sdiv X, pow2) -> simple ops after legalize 1833 if (N1C && !N1C->isNullValue() && 1834 (N1C->getAPIntValue().isPowerOf2() || 1835 (-N1C->getAPIntValue()).isPowerOf2())) { 1836 // If dividing by powers of two is cheap, then don't perform the following 1837 // fold. 1838 if (TLI.isPow2DivCheap()) 1839 return SDValue(); 1840 1841 unsigned lg2 = N1C->getAPIntValue().countTrailingZeros(); 1842 1843 // Splat the sign bit into the register 1844 SDValue SGN = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0, 1845 DAG.getConstant(VT.getSizeInBits()-1, 1846 getShiftAmountTy(N0.getValueType()))); 1847 AddToWorkList(SGN.getNode()); 1848 1849 // Add (N0 < 0) ? abs2 - 1 : 0; 1850 SDValue SRL = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, SGN, 1851 DAG.getConstant(VT.getSizeInBits() - lg2, 1852 getShiftAmountTy(SGN.getValueType()))); 1853 SDValue ADD = DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, SRL); 1854 AddToWorkList(SRL.getNode()); 1855 AddToWorkList(ADD.getNode()); // Divide by pow2 1856 SDValue SRA = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, ADD, 1857 DAG.getConstant(lg2, getShiftAmountTy(ADD.getValueType()))); 1858 1859 // If we're dividing by a positive value, we're done. Otherwise, we must 1860 // negate the result. 1861 if (N1C->getAPIntValue().isNonNegative()) 1862 return SRA; 1863 1864 AddToWorkList(SRA.getNode()); 1865 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1866 DAG.getConstant(0, VT), SRA); 1867 } 1868 1869 // if integer divide is expensive and we satisfy the requirements, emit an 1870 // alternate sequence. 1871 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) { 1872 SDValue Op = BuildSDIV(N); 1873 if (Op.getNode()) return Op; 1874 } 1875 1876 // undef / X -> 0 1877 if (N0.getOpcode() == ISD::UNDEF) 1878 return DAG.getConstant(0, VT); 1879 // X / undef -> undef 1880 if (N1.getOpcode() == ISD::UNDEF) 1881 return N1; 1882 1883 return SDValue(); 1884} 1885 1886SDValue DAGCombiner::visitUDIV(SDNode *N) { 1887 SDValue N0 = N->getOperand(0); 1888 SDValue N1 = N->getOperand(1); 1889 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1890 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1891 EVT VT = N->getValueType(0); 1892 1893 // fold vector ops 1894 if (VT.isVector()) { 1895 SDValue FoldedVOp = SimplifyVBinOp(N); 1896 if (FoldedVOp.getNode()) return FoldedVOp; 1897 } 1898 1899 // fold (udiv c1, c2) -> c1/c2 1900 if (N0C && N1C && !N1C->isNullValue()) 1901 return DAG.FoldConstantArithmetic(ISD::UDIV, VT, N0C, N1C); 1902 // fold (udiv x, (1 << c)) -> x >>u c 1903 if (N1C && N1C->getAPIntValue().isPowerOf2()) 1904 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, 1905 DAG.getConstant(N1C->getAPIntValue().logBase2(), 1906 getShiftAmountTy(N0.getValueType()))); 1907 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2 1908 if (N1.getOpcode() == ISD::SHL) { 1909 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1910 if (SHC->getAPIntValue().isPowerOf2()) { 1911 EVT ADDVT = N1.getOperand(1).getValueType(); 1912 SDValue Add = DAG.getNode(ISD::ADD, N->getDebugLoc(), ADDVT, 1913 N1.getOperand(1), 1914 DAG.getConstant(SHC->getAPIntValue() 1915 .logBase2(), 1916 ADDVT)); 1917 AddToWorkList(Add.getNode()); 1918 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, Add); 1919 } 1920 } 1921 } 1922 // fold (udiv x, c) -> alternate 1923 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) { 1924 SDValue Op = BuildUDIV(N); 1925 if (Op.getNode()) return Op; 1926 } 1927 1928 // undef / X -> 0 1929 if (N0.getOpcode() == ISD::UNDEF) 1930 return DAG.getConstant(0, VT); 1931 // X / undef -> undef 1932 if (N1.getOpcode() == ISD::UNDEF) 1933 return N1; 1934 1935 return SDValue(); 1936} 1937 1938SDValue DAGCombiner::visitSREM(SDNode *N) { 1939 SDValue N0 = N->getOperand(0); 1940 SDValue N1 = N->getOperand(1); 1941 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1942 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1943 EVT VT = N->getValueType(0); 1944 1945 // fold (srem c1, c2) -> c1%c2 1946 if (N0C && N1C && !N1C->isNullValue()) 1947 return DAG.FoldConstantArithmetic(ISD::SREM, VT, N0C, N1C); 1948 // If we know the sign bits of both operands are zero, strength reduce to a 1949 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15 1950 if (!VT.isVector()) { 1951 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 1952 return DAG.getNode(ISD::UREM, N->getDebugLoc(), VT, N0, N1); 1953 } 1954 1955 // If X/C can be simplified by the division-by-constant logic, lower 1956 // X%C to the equivalent of X-X/C*C. 1957 if (N1C && !N1C->isNullValue()) { 1958 SDValue Div = DAG.getNode(ISD::SDIV, N->getDebugLoc(), VT, N0, N1); 1959 AddToWorkList(Div.getNode()); 1960 SDValue OptimizedDiv = combine(Div.getNode()); 1961 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) { 1962 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1963 OptimizedDiv, N1); 1964 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul); 1965 AddToWorkList(Mul.getNode()); 1966 return Sub; 1967 } 1968 } 1969 1970 // undef % X -> 0 1971 if (N0.getOpcode() == ISD::UNDEF) 1972 return DAG.getConstant(0, VT); 1973 // X % undef -> undef 1974 if (N1.getOpcode() == ISD::UNDEF) 1975 return N1; 1976 1977 return SDValue(); 1978} 1979 1980SDValue DAGCombiner::visitUREM(SDNode *N) { 1981 SDValue N0 = N->getOperand(0); 1982 SDValue N1 = N->getOperand(1); 1983 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1984 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1985 EVT VT = N->getValueType(0); 1986 1987 // fold (urem c1, c2) -> c1%c2 1988 if (N0C && N1C && !N1C->isNullValue()) 1989 return DAG.FoldConstantArithmetic(ISD::UREM, VT, N0C, N1C); 1990 // fold (urem x, pow2) -> (and x, pow2-1) 1991 if (N1C && !N1C->isNullValue() && N1C->getAPIntValue().isPowerOf2()) 1992 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, 1993 DAG.getConstant(N1C->getAPIntValue()-1,VT)); 1994 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1)) 1995 if (N1.getOpcode() == ISD::SHL) { 1996 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1997 if (SHC->getAPIntValue().isPowerOf2()) { 1998 SDValue Add = 1999 DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, 2000 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), 2001 VT)); 2002 AddToWorkList(Add.getNode()); 2003 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, Add); 2004 } 2005 } 2006 } 2007 2008 // If X/C can be simplified by the division-by-constant logic, lower 2009 // X%C to the equivalent of X-X/C*C. 2010 if (N1C && !N1C->isNullValue()) { 2011 SDValue Div = DAG.getNode(ISD::UDIV, N->getDebugLoc(), VT, N0, N1); 2012 AddToWorkList(Div.getNode()); 2013 SDValue OptimizedDiv = combine(Div.getNode()); 2014 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) { 2015 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 2016 OptimizedDiv, N1); 2017 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul); 2018 AddToWorkList(Mul.getNode()); 2019 return Sub; 2020 } 2021 } 2022 2023 // undef % X -> 0 2024 if (N0.getOpcode() == ISD::UNDEF) 2025 return DAG.getConstant(0, VT); 2026 // X % undef -> undef 2027 if (N1.getOpcode() == ISD::UNDEF) 2028 return N1; 2029 2030 return SDValue(); 2031} 2032 2033SDValue DAGCombiner::visitMULHS(SDNode *N) { 2034 SDValue N0 = N->getOperand(0); 2035 SDValue N1 = N->getOperand(1); 2036 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2037 EVT VT = N->getValueType(0); 2038 DebugLoc DL = N->getDebugLoc(); 2039 2040 // fold (mulhs x, 0) -> 0 2041 if (N1C && N1C->isNullValue()) 2042 return N1; 2043 // fold (mulhs x, 1) -> (sra x, size(x)-1) 2044 if (N1C && N1C->getAPIntValue() == 1) 2045 return DAG.getNode(ISD::SRA, N->getDebugLoc(), N0.getValueType(), N0, 2046 DAG.getConstant(N0.getValueType().getSizeInBits() - 1, 2047 getShiftAmountTy(N0.getValueType()))); 2048 // fold (mulhs x, undef) -> 0 2049 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 2050 return DAG.getConstant(0, VT); 2051 2052 // If the type twice as wide is legal, transform the mulhs to a wider multiply 2053 // plus a shift. 2054 if (VT.isSimple() && !VT.isVector()) { 2055 MVT Simple = VT.getSimpleVT(); 2056 unsigned SimpleSize = Simple.getSizeInBits(); 2057 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2); 2058 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { 2059 N0 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N0); 2060 N1 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N1); 2061 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1); 2062 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1, 2063 DAG.getConstant(SimpleSize, getShiftAmountTy(N1.getValueType()))); 2064 return DAG.getNode(ISD::TRUNCATE, DL, VT, N1); 2065 } 2066 } 2067 2068 return SDValue(); 2069} 2070 2071SDValue DAGCombiner::visitMULHU(SDNode *N) { 2072 SDValue N0 = N->getOperand(0); 2073 SDValue N1 = N->getOperand(1); 2074 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2075 EVT VT = N->getValueType(0); 2076 DebugLoc DL = N->getDebugLoc(); 2077 2078 // fold (mulhu x, 0) -> 0 2079 if (N1C && N1C->isNullValue()) 2080 return N1; 2081 // fold (mulhu x, 1) -> 0 2082 if (N1C && N1C->getAPIntValue() == 1) 2083 return DAG.getConstant(0, N0.getValueType()); 2084 // fold (mulhu x, undef) -> 0 2085 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 2086 return DAG.getConstant(0, VT); 2087 2088 // If the type twice as wide is legal, transform the mulhu to a wider multiply 2089 // plus a shift. 2090 if (VT.isSimple() && !VT.isVector()) { 2091 MVT Simple = VT.getSimpleVT(); 2092 unsigned SimpleSize = Simple.getSizeInBits(); 2093 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2); 2094 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { 2095 N0 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N0); 2096 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N1); 2097 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1); 2098 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1, 2099 DAG.getConstant(SimpleSize, getShiftAmountTy(N1.getValueType()))); 2100 return DAG.getNode(ISD::TRUNCATE, DL, VT, N1); 2101 } 2102 } 2103 2104 return SDValue(); 2105} 2106 2107/// SimplifyNodeWithTwoResults - Perform optimizations common to nodes that 2108/// compute two values. LoOp and HiOp give the opcodes for the two computations 2109/// that are being performed. Return true if a simplification was made. 2110/// 2111SDValue DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 2112 unsigned HiOp) { 2113 // If the high half is not needed, just compute the low half. 2114 bool HiExists = N->hasAnyUseOfValue(1); 2115 if (!HiExists && 2116 (!LegalOperations || 2117 TLI.isOperationLegal(LoOp, N->getValueType(0)))) { 2118 SDValue Res = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0), 2119 N->op_begin(), N->getNumOperands()); 2120 return CombineTo(N, Res, Res); 2121 } 2122 2123 // If the low half is not needed, just compute the high half. 2124 bool LoExists = N->hasAnyUseOfValue(0); 2125 if (!LoExists && 2126 (!LegalOperations || 2127 TLI.isOperationLegal(HiOp, N->getValueType(1)))) { 2128 SDValue Res = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1), 2129 N->op_begin(), N->getNumOperands()); 2130 return CombineTo(N, Res, Res); 2131 } 2132 2133 // If both halves are used, return as it is. 2134 if (LoExists && HiExists) 2135 return SDValue(); 2136 2137 // If the two computed results can be simplified separately, separate them. 2138 if (LoExists) { 2139 SDValue Lo = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0), 2140 N->op_begin(), N->getNumOperands()); 2141 AddToWorkList(Lo.getNode()); 2142 SDValue LoOpt = combine(Lo.getNode()); 2143 if (LoOpt.getNode() && LoOpt.getNode() != Lo.getNode() && 2144 (!LegalOperations || 2145 TLI.isOperationLegal(LoOpt.getOpcode(), LoOpt.getValueType()))) 2146 return CombineTo(N, LoOpt, LoOpt); 2147 } 2148 2149 if (HiExists) { 2150 SDValue Hi = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1), 2151 N->op_begin(), N->getNumOperands()); 2152 AddToWorkList(Hi.getNode()); 2153 SDValue HiOpt = combine(Hi.getNode()); 2154 if (HiOpt.getNode() && HiOpt != Hi && 2155 (!LegalOperations || 2156 TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType()))) 2157 return CombineTo(N, HiOpt, HiOpt); 2158 } 2159 2160 return SDValue(); 2161} 2162 2163SDValue DAGCombiner::visitSMUL_LOHI(SDNode *N) { 2164 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS); 2165 if (Res.getNode()) return Res; 2166 2167 EVT VT = N->getValueType(0); 2168 DebugLoc DL = N->getDebugLoc(); 2169 2170 // If the type twice as wide is legal, transform the mulhu to a wider multiply 2171 // plus a shift. 2172 if (VT.isSimple() && !VT.isVector()) { 2173 MVT Simple = VT.getSimpleVT(); 2174 unsigned SimpleSize = Simple.getSizeInBits(); 2175 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2); 2176 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { 2177 SDValue Lo = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(0)); 2178 SDValue Hi = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(1)); 2179 Lo = DAG.getNode(ISD::MUL, DL, NewVT, Lo, Hi); 2180 // Compute the high part as N1. 2181 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo, 2182 DAG.getConstant(SimpleSize, getShiftAmountTy(Lo.getValueType()))); 2183 Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi); 2184 // Compute the low part as N0. 2185 Lo = DAG.getNode(ISD::TRUNCATE, DL, VT, Lo); 2186 return CombineTo(N, Lo, Hi); 2187 } 2188 } 2189 2190 return SDValue(); 2191} 2192 2193SDValue DAGCombiner::visitUMUL_LOHI(SDNode *N) { 2194 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU); 2195 if (Res.getNode()) return Res; 2196 2197 EVT VT = N->getValueType(0); 2198 DebugLoc DL = N->getDebugLoc(); 2199 2200 // If the type twice as wide is legal, transform the mulhu to a wider multiply 2201 // plus a shift. 2202 if (VT.isSimple() && !VT.isVector()) { 2203 MVT Simple = VT.getSimpleVT(); 2204 unsigned SimpleSize = Simple.getSizeInBits(); 2205 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2); 2206 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { 2207 SDValue Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(0)); 2208 SDValue Hi = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(1)); 2209 Lo = DAG.getNode(ISD::MUL, DL, NewVT, Lo, Hi); 2210 // Compute the high part as N1. 2211 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo, 2212 DAG.getConstant(SimpleSize, getShiftAmountTy(Lo.getValueType()))); 2213 Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi); 2214 // Compute the low part as N0. 2215 Lo = DAG.getNode(ISD::TRUNCATE, DL, VT, Lo); 2216 return CombineTo(N, Lo, Hi); 2217 } 2218 } 2219 2220 return SDValue(); 2221} 2222 2223SDValue DAGCombiner::visitSMULO(SDNode *N) { 2224 // (smulo x, 2) -> (saddo x, x) 2225 if (ConstantSDNode *C2 = dyn_cast<ConstantSDNode>(N->getOperand(1))) 2226 if (C2->getAPIntValue() == 2) 2227 return DAG.getNode(ISD::SADDO, N->getDebugLoc(), N->getVTList(), 2228 N->getOperand(0), N->getOperand(0)); 2229 2230 return SDValue(); 2231} 2232 2233SDValue DAGCombiner::visitUMULO(SDNode *N) { 2234 // (umulo x, 2) -> (uaddo x, x) 2235 if (ConstantSDNode *C2 = dyn_cast<ConstantSDNode>(N->getOperand(1))) 2236 if (C2->getAPIntValue() == 2) 2237 return DAG.getNode(ISD::UADDO, N->getDebugLoc(), N->getVTList(), 2238 N->getOperand(0), N->getOperand(0)); 2239 2240 return SDValue(); 2241} 2242 2243SDValue DAGCombiner::visitSDIVREM(SDNode *N) { 2244 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM); 2245 if (Res.getNode()) return Res; 2246 2247 return SDValue(); 2248} 2249 2250SDValue DAGCombiner::visitUDIVREM(SDNode *N) { 2251 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM); 2252 if (Res.getNode()) return Res; 2253 2254 return SDValue(); 2255} 2256 2257/// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with 2258/// two operands of the same opcode, try to simplify it. 2259SDValue DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) { 2260 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1); 2261 EVT VT = N0.getValueType(); 2262 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!"); 2263 2264 // Bail early if none of these transforms apply. 2265 if (N0.getNode()->getNumOperands() == 0) return SDValue(); 2266 2267 // For each of OP in AND/OR/XOR: 2268 // fold (OP (zext x), (zext y)) -> (zext (OP x, y)) 2269 // fold (OP (sext x), (sext y)) -> (sext (OP x, y)) 2270 // fold (OP (aext x), (aext y)) -> (aext (OP x, y)) 2271 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y)) (if trunc isn't free) 2272 // 2273 // do not sink logical op inside of a vector extend, since it may combine 2274 // into a vsetcc. 2275 EVT Op0VT = N0.getOperand(0).getValueType(); 2276 if ((N0.getOpcode() == ISD::ZERO_EXTEND || 2277 N0.getOpcode() == ISD::SIGN_EXTEND || 2278 // Avoid infinite looping with PromoteIntBinOp. 2279 (N0.getOpcode() == ISD::ANY_EXTEND && 2280 (!LegalTypes || TLI.isTypeDesirableForOp(N->getOpcode(), Op0VT))) || 2281 (N0.getOpcode() == ISD::TRUNCATE && 2282 (!TLI.isZExtFree(VT, Op0VT) || 2283 !TLI.isTruncateFree(Op0VT, VT)) && 2284 TLI.isTypeLegal(Op0VT))) && 2285 !VT.isVector() && 2286 Op0VT == N1.getOperand(0).getValueType() && 2287 (!LegalOperations || TLI.isOperationLegal(N->getOpcode(), Op0VT))) { 2288 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(), 2289 N0.getOperand(0).getValueType(), 2290 N0.getOperand(0), N1.getOperand(0)); 2291 AddToWorkList(ORNode.getNode()); 2292 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, ORNode); 2293 } 2294 2295 // For each of OP in SHL/SRL/SRA/AND... 2296 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z) 2297 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z) 2298 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z) 2299 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL || 2300 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) && 2301 N0.getOperand(1) == N1.getOperand(1)) { 2302 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(), 2303 N0.getOperand(0).getValueType(), 2304 N0.getOperand(0), N1.getOperand(0)); 2305 AddToWorkList(ORNode.getNode()); 2306 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, 2307 ORNode, N0.getOperand(1)); 2308 } 2309 2310 return SDValue(); 2311} 2312 2313SDValue DAGCombiner::visitAND(SDNode *N) { 2314 SDValue N0 = N->getOperand(0); 2315 SDValue N1 = N->getOperand(1); 2316 SDValue LL, LR, RL, RR, CC0, CC1; 2317 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2318 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2319 EVT VT = N1.getValueType(); 2320 unsigned BitWidth = VT.getScalarType().getSizeInBits(); 2321 2322 // fold vector ops 2323 if (VT.isVector()) { 2324 SDValue FoldedVOp = SimplifyVBinOp(N); 2325 if (FoldedVOp.getNode()) return FoldedVOp; 2326 } 2327 2328 // fold (and x, undef) -> 0 2329 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 2330 return DAG.getConstant(0, VT); 2331 // fold (and c1, c2) -> c1&c2 2332 if (N0C && N1C) 2333 return DAG.FoldConstantArithmetic(ISD::AND, VT, N0C, N1C); 2334 // canonicalize constant to RHS 2335 if (N0C && !N1C) 2336 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N1, N0); 2337 // fold (and x, -1) -> x 2338 if (N1C && N1C->isAllOnesValue()) 2339 return N0; 2340 // if (and x, c) is known to be zero, return 0 2341 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0), 2342 APInt::getAllOnesValue(BitWidth))) 2343 return DAG.getConstant(0, VT); 2344 // reassociate and 2345 SDValue RAND = ReassociateOps(ISD::AND, N->getDebugLoc(), N0, N1); 2346 if (RAND.getNode() != 0) 2347 return RAND; 2348 // fold (and (or x, C), D) -> D if (C & D) == D 2349 if (N1C && N0.getOpcode() == ISD::OR) 2350 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 2351 if ((ORI->getAPIntValue() & N1C->getAPIntValue()) == N1C->getAPIntValue()) 2352 return N1; 2353 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits. 2354 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 2355 SDValue N0Op0 = N0.getOperand(0); 2356 APInt Mask = ~N1C->getAPIntValue(); 2357 Mask = Mask.trunc(N0Op0.getValueSizeInBits()); 2358 if (DAG.MaskedValueIsZero(N0Op0, Mask)) { 2359 SDValue Zext = DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), 2360 N0.getValueType(), N0Op0); 2361 2362 // Replace uses of the AND with uses of the Zero extend node. 2363 CombineTo(N, Zext); 2364 2365 // We actually want to replace all uses of the any_extend with the 2366 // zero_extend, to avoid duplicating things. This will later cause this 2367 // AND to be folded. 2368 CombineTo(N0.getNode(), Zext); 2369 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2370 } 2371 } 2372 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y)) 2373 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 2374 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 2375 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 2376 2377 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 2378 LL.getValueType().isInteger()) { 2379 // fold (and (seteq X, 0), (seteq Y, 0)) -> (seteq (or X, Y), 0) 2380 if (cast<ConstantSDNode>(LR)->isNullValue() && Op1 == ISD::SETEQ) { 2381 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(), 2382 LR.getValueType(), LL, RL); 2383 AddToWorkList(ORNode.getNode()); 2384 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 2385 } 2386 // fold (and (seteq X, -1), (seteq Y, -1)) -> (seteq (and X, Y), -1) 2387 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) { 2388 SDValue ANDNode = DAG.getNode(ISD::AND, N0.getDebugLoc(), 2389 LR.getValueType(), LL, RL); 2390 AddToWorkList(ANDNode.getNode()); 2391 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1); 2392 } 2393 // fold (and (setgt X, -1), (setgt Y, -1)) -> (setgt (or X, Y), -1) 2394 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) { 2395 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(), 2396 LR.getValueType(), LL, RL); 2397 AddToWorkList(ORNode.getNode()); 2398 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 2399 } 2400 } 2401 // canonicalize equivalent to ll == rl 2402 if (LL == RR && LR == RL) { 2403 Op1 = ISD::getSetCCSwappedOperands(Op1); 2404 std::swap(RL, RR); 2405 } 2406 if (LL == RL && LR == RR) { 2407 bool isInteger = LL.getValueType().isInteger(); 2408 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger); 2409 if (Result != ISD::SETCC_INVALID && 2410 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType()))) 2411 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(), 2412 LL, LR, Result); 2413 } 2414 } 2415 2416 // Simplify: (and (op x...), (op y...)) -> (op (and x, y)) 2417 if (N0.getOpcode() == N1.getOpcode()) { 2418 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 2419 if (Tmp.getNode()) return Tmp; 2420 } 2421 2422 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1) 2423 // fold (and (sra)) -> (and (srl)) when possible. 2424 if (!VT.isVector() && 2425 SimplifyDemandedBits(SDValue(N, 0))) 2426 return SDValue(N, 0); 2427 2428 // fold (zext_inreg (extload x)) -> (zextload x) 2429 if (ISD::isEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode())) { 2430 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2431 EVT MemVT = LN0->getMemoryVT(); 2432 // If we zero all the possible extended bits, then we can turn this into 2433 // a zextload if we are running before legalize or the operation is legal. 2434 unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits(); 2435 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 2436 BitWidth - MemVT.getScalarType().getSizeInBits())) && 2437 ((!LegalOperations && !LN0->isVolatile()) || 2438 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) { 2439 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT, 2440 LN0->getChain(), LN0->getBasePtr(), 2441 LN0->getPointerInfo(), MemVT, 2442 LN0->isVolatile(), LN0->isNonTemporal(), 2443 LN0->getAlignment()); 2444 AddToWorkList(N); 2445 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 2446 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2447 } 2448 } 2449 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use 2450 if (ISD::isSEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 2451 N0.hasOneUse()) { 2452 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2453 EVT MemVT = LN0->getMemoryVT(); 2454 // If we zero all the possible extended bits, then we can turn this into 2455 // a zextload if we are running before legalize or the operation is legal. 2456 unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits(); 2457 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 2458 BitWidth - MemVT.getScalarType().getSizeInBits())) && 2459 ((!LegalOperations && !LN0->isVolatile()) || 2460 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) { 2461 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT, 2462 LN0->getChain(), 2463 LN0->getBasePtr(), LN0->getPointerInfo(), 2464 MemVT, 2465 LN0->isVolatile(), LN0->isNonTemporal(), 2466 LN0->getAlignment()); 2467 AddToWorkList(N); 2468 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 2469 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2470 } 2471 } 2472 2473 // fold (and (load x), 255) -> (zextload x, i8) 2474 // fold (and (extload x, i16), 255) -> (zextload x, i8) 2475 // fold (and (any_ext (extload x, i16)), 255) -> (zextload x, i8) 2476 if (N1C && (N0.getOpcode() == ISD::LOAD || 2477 (N0.getOpcode() == ISD::ANY_EXTEND && 2478 N0.getOperand(0).getOpcode() == ISD::LOAD))) { 2479 bool HasAnyExt = N0.getOpcode() == ISD::ANY_EXTEND; 2480 LoadSDNode *LN0 = HasAnyExt 2481 ? cast<LoadSDNode>(N0.getOperand(0)) 2482 : cast<LoadSDNode>(N0); 2483 if (LN0->getExtensionType() != ISD::SEXTLOAD && 2484 LN0->isUnindexed() && N0.hasOneUse() && LN0->hasOneUse()) { 2485 uint32_t ActiveBits = N1C->getAPIntValue().getActiveBits(); 2486 if (ActiveBits > 0 && APIntOps::isMask(ActiveBits, N1C->getAPIntValue())){ 2487 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), ActiveBits); 2488 EVT LoadedVT = LN0->getMemoryVT(); 2489 2490 if (ExtVT == LoadedVT && 2491 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) { 2492 EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT; 2493 2494 SDValue NewLoad = 2495 DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), LoadResultTy, 2496 LN0->getChain(), LN0->getBasePtr(), 2497 LN0->getPointerInfo(), 2498 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(), 2499 LN0->getAlignment()); 2500 AddToWorkList(N); 2501 CombineTo(LN0, NewLoad, NewLoad.getValue(1)); 2502 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2503 } 2504 2505 // Do not change the width of a volatile load. 2506 // Do not generate loads of non-round integer types since these can 2507 // be expensive (and would be wrong if the type is not byte sized). 2508 if (!LN0->isVolatile() && LoadedVT.bitsGT(ExtVT) && ExtVT.isRound() && 2509 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) { 2510 EVT PtrType = LN0->getOperand(1).getValueType(); 2511 2512 unsigned Alignment = LN0->getAlignment(); 2513 SDValue NewPtr = LN0->getBasePtr(); 2514 2515 // For big endian targets, we need to add an offset to the pointer 2516 // to load the correct bytes. For little endian systems, we merely 2517 // need to read fewer bytes from the same pointer. 2518 if (TLI.isBigEndian()) { 2519 unsigned LVTStoreBytes = LoadedVT.getStoreSize(); 2520 unsigned EVTStoreBytes = ExtVT.getStoreSize(); 2521 unsigned PtrOff = LVTStoreBytes - EVTStoreBytes; 2522 NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(), PtrType, 2523 NewPtr, DAG.getConstant(PtrOff, PtrType)); 2524 Alignment = MinAlign(Alignment, PtrOff); 2525 } 2526 2527 AddToWorkList(NewPtr.getNode()); 2528 2529 EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT; 2530 SDValue Load = 2531 DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), LoadResultTy, 2532 LN0->getChain(), NewPtr, 2533 LN0->getPointerInfo(), 2534 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(), 2535 Alignment); 2536 AddToWorkList(N); 2537 CombineTo(LN0, Load, Load.getValue(1)); 2538 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2539 } 2540 } 2541 } 2542 } 2543 2544 return SDValue(); 2545} 2546 2547/// MatchBSwapHWord - Match (a >> 8) | (a << 8) as (bswap a) >> 16 2548/// 2549SDValue DAGCombiner::MatchBSwapHWordLow(SDNode *N, SDValue N0, SDValue N1, 2550 bool DemandHighBits) { 2551 if (!LegalOperations) 2552 return SDValue(); 2553 2554 EVT VT = N->getValueType(0); 2555 if (VT != MVT::i64 && VT != MVT::i32 && VT != MVT::i16) 2556 return SDValue(); 2557 if (!TLI.isOperationLegal(ISD::BSWAP, VT)) 2558 return SDValue(); 2559 2560 // Recognize (and (shl a, 8), 0xff), (and (srl a, 8), 0xff00) 2561 bool LookPassAnd0 = false; 2562 bool LookPassAnd1 = false; 2563 if (N0.getOpcode() == ISD::AND && N0.getOperand(0).getOpcode() == ISD::SRL) 2564 std::swap(N0, N1); 2565 if (N1.getOpcode() == ISD::AND && N1.getOperand(0).getOpcode() == ISD::SHL) 2566 std::swap(N0, N1); 2567 if (N0.getOpcode() == ISD::AND) { 2568 if (!N0.getNode()->hasOneUse()) 2569 return SDValue(); 2570 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2571 if (!N01C || N01C->getZExtValue() != 0xFF00) 2572 return SDValue(); 2573 N0 = N0.getOperand(0); 2574 LookPassAnd0 = true; 2575 } 2576 2577 if (N1.getOpcode() == ISD::AND) { 2578 if (!N1.getNode()->hasOneUse()) 2579 return SDValue(); 2580 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1)); 2581 if (!N11C || N11C->getZExtValue() != 0xFF) 2582 return SDValue(); 2583 N1 = N1.getOperand(0); 2584 LookPassAnd1 = true; 2585 } 2586 2587 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL) 2588 std::swap(N0, N1); 2589 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL) 2590 return SDValue(); 2591 if (!N0.getNode()->hasOneUse() || 2592 !N1.getNode()->hasOneUse()) 2593 return SDValue(); 2594 2595 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2596 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1)); 2597 if (!N01C || !N11C) 2598 return SDValue(); 2599 if (N01C->getZExtValue() != 8 || N11C->getZExtValue() != 8) 2600 return SDValue(); 2601 2602 // Look for (shl (and a, 0xff), 8), (srl (and a, 0xff00), 8) 2603 SDValue N00 = N0->getOperand(0); 2604 if (!LookPassAnd0 && N00.getOpcode() == ISD::AND) { 2605 if (!N00.getNode()->hasOneUse()) 2606 return SDValue(); 2607 ConstantSDNode *N001C = dyn_cast<ConstantSDNode>(N00.getOperand(1)); 2608 if (!N001C || N001C->getZExtValue() != 0xFF) 2609 return SDValue(); 2610 N00 = N00.getOperand(0); 2611 LookPassAnd0 = true; 2612 } 2613 2614 SDValue N10 = N1->getOperand(0); 2615 if (!LookPassAnd1 && N10.getOpcode() == ISD::AND) { 2616 if (!N10.getNode()->hasOneUse()) 2617 return SDValue(); 2618 ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N10.getOperand(1)); 2619 if (!N101C || N101C->getZExtValue() != 0xFF00) 2620 return SDValue(); 2621 N10 = N10.getOperand(0); 2622 LookPassAnd1 = true; 2623 } 2624 2625 if (N00 != N10) 2626 return SDValue(); 2627 2628 // Make sure everything beyond the low halfword is zero since the SRL 16 2629 // will clear the top bits. 2630 unsigned OpSizeInBits = VT.getSizeInBits(); 2631 if (DemandHighBits && OpSizeInBits > 16 && 2632 (!LookPassAnd0 || !LookPassAnd1) && 2633 !DAG.MaskedValueIsZero(N10, APInt::getHighBitsSet(OpSizeInBits, 16))) 2634 return SDValue(); 2635 2636 SDValue Res = DAG.getNode(ISD::BSWAP, N->getDebugLoc(), VT, N00); 2637 if (OpSizeInBits > 16) 2638 Res = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, Res, 2639 DAG.getConstant(OpSizeInBits-16, getShiftAmountTy(VT))); 2640 return Res; 2641} 2642 2643/// isBSwapHWordElement - Return true if the specified node is an element 2644/// that makes up a 32-bit packed halfword byteswap. i.e. 2645/// ((x&0xff)<<8)|((x&0xff00)>>8)|((x&0x00ff0000)<<8)|((x&0xff000000)>>8) 2646static bool isBSwapHWordElement(SDValue N, SmallVector<SDNode*,4> &Parts) { 2647 if (!N.getNode()->hasOneUse()) 2648 return false; 2649 2650 unsigned Opc = N.getOpcode(); 2651 if (Opc != ISD::AND && Opc != ISD::SHL && Opc != ISD::SRL) 2652 return false; 2653 2654 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N.getOperand(1)); 2655 if (!N1C) 2656 return false; 2657 2658 unsigned Num; 2659 switch (N1C->getZExtValue()) { 2660 default: 2661 return false; 2662 case 0xFF: Num = 0; break; 2663 case 0xFF00: Num = 1; break; 2664 case 0xFF0000: Num = 2; break; 2665 case 0xFF000000: Num = 3; break; 2666 } 2667 2668 // Look for (x & 0xff) << 8 as well as ((x << 8) & 0xff00). 2669 SDValue N0 = N.getOperand(0); 2670 if (Opc == ISD::AND) { 2671 if (Num == 0 || Num == 2) { 2672 // (x >> 8) & 0xff 2673 // (x >> 8) & 0xff0000 2674 if (N0.getOpcode() != ISD::SRL) 2675 return false; 2676 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2677 if (!C || C->getZExtValue() != 8) 2678 return false; 2679 } else { 2680 // (x << 8) & 0xff00 2681 // (x << 8) & 0xff000000 2682 if (N0.getOpcode() != ISD::SHL) 2683 return false; 2684 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2685 if (!C || C->getZExtValue() != 8) 2686 return false; 2687 } 2688 } else if (Opc == ISD::SHL) { 2689 // (x & 0xff) << 8 2690 // (x & 0xff0000) << 8 2691 if (Num != 0 && Num != 2) 2692 return false; 2693 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N.getOperand(1)); 2694 if (!C || C->getZExtValue() != 8) 2695 return false; 2696 } else { // Opc == ISD::SRL 2697 // (x & 0xff00) >> 8 2698 // (x & 0xff000000) >> 8 2699 if (Num != 1 && Num != 3) 2700 return false; 2701 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N.getOperand(1)); 2702 if (!C || C->getZExtValue() != 8) 2703 return false; 2704 } 2705 2706 if (Parts[Num]) 2707 return false; 2708 2709 Parts[Num] = N0.getOperand(0).getNode(); 2710 return true; 2711} 2712 2713/// MatchBSwapHWord - Match a 32-bit packed halfword bswap. That is 2714/// ((x&0xff)<<8)|((x&0xff00)>>8)|((x&0x00ff0000)<<8)|((x&0xff000000)>>8) 2715/// => (rotl (bswap x), 16) 2716SDValue DAGCombiner::MatchBSwapHWord(SDNode *N, SDValue N0, SDValue N1) { 2717 if (!LegalOperations) 2718 return SDValue(); 2719 2720 EVT VT = N->getValueType(0); 2721 if (VT != MVT::i32) 2722 return SDValue(); 2723 if (!TLI.isOperationLegal(ISD::BSWAP, VT)) 2724 return SDValue(); 2725 2726 SmallVector<SDNode*,4> Parts(4, (SDNode*)0); 2727 // Look for either 2728 // (or (or (and), (and)), (or (and), (and))) 2729 // (or (or (or (and), (and)), (and)), (and)) 2730 if (N0.getOpcode() != ISD::OR) 2731 return SDValue(); 2732 SDValue N00 = N0.getOperand(0); 2733 SDValue N01 = N0.getOperand(1); 2734 2735 if (N1.getOpcode() == ISD::OR) { 2736 // (or (or (and), (and)), (or (and), (and))) 2737 SDValue N000 = N00.getOperand(0); 2738 if (!isBSwapHWordElement(N000, Parts)) 2739 return SDValue(); 2740 2741 SDValue N001 = N00.getOperand(1); 2742 if (!isBSwapHWordElement(N001, Parts)) 2743 return SDValue(); 2744 SDValue N010 = N01.getOperand(0); 2745 if (!isBSwapHWordElement(N010, Parts)) 2746 return SDValue(); 2747 SDValue N011 = N01.getOperand(1); 2748 if (!isBSwapHWordElement(N011, Parts)) 2749 return SDValue(); 2750 } else { 2751 // (or (or (or (and), (and)), (and)), (and)) 2752 if (!isBSwapHWordElement(N1, Parts)) 2753 return SDValue(); 2754 if (!isBSwapHWordElement(N01, Parts)) 2755 return SDValue(); 2756 if (N00.getOpcode() != ISD::OR) 2757 return SDValue(); 2758 SDValue N000 = N00.getOperand(0); 2759 if (!isBSwapHWordElement(N000, Parts)) 2760 return SDValue(); 2761 SDValue N001 = N00.getOperand(1); 2762 if (!isBSwapHWordElement(N001, Parts)) 2763 return SDValue(); 2764 } 2765 2766 // Make sure the parts are all coming from the same node. 2767 if (Parts[0] != Parts[1] || Parts[0] != Parts[2] || Parts[0] != Parts[3]) 2768 return SDValue(); 2769 2770 SDValue BSwap = DAG.getNode(ISD::BSWAP, N->getDebugLoc(), VT, 2771 SDValue(Parts[0],0)); 2772 2773 // Result of the bswap should be rotated by 16. If it's not legal, than 2774 // do (x << 16) | (x >> 16). 2775 SDValue ShAmt = DAG.getConstant(16, getShiftAmountTy(VT)); 2776 if (TLI.isOperationLegalOrCustom(ISD::ROTL, VT)) 2777 return DAG.getNode(ISD::ROTL, N->getDebugLoc(), VT, BSwap, ShAmt); 2778 else if (TLI.isOperationLegalOrCustom(ISD::ROTR, VT)) 2779 return DAG.getNode(ISD::ROTR, N->getDebugLoc(), VT, BSwap, ShAmt); 2780 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, 2781 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, BSwap, ShAmt), 2782 DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, BSwap, ShAmt)); 2783} 2784 2785SDValue DAGCombiner::visitOR(SDNode *N) { 2786 SDValue N0 = N->getOperand(0); 2787 SDValue N1 = N->getOperand(1); 2788 SDValue LL, LR, RL, RR, CC0, CC1; 2789 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2790 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2791 EVT VT = N1.getValueType(); 2792 2793 // fold vector ops 2794 if (VT.isVector()) { 2795 SDValue FoldedVOp = SimplifyVBinOp(N); 2796 if (FoldedVOp.getNode()) return FoldedVOp; 2797 } 2798 2799 // fold (or x, undef) -> -1 2800 if (!LegalOperations && 2801 (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)) { 2802 EVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT; 2803 return DAG.getConstant(APInt::getAllOnesValue(EltVT.getSizeInBits()), VT); 2804 } 2805 // fold (or c1, c2) -> c1|c2 2806 if (N0C && N1C) 2807 return DAG.FoldConstantArithmetic(ISD::OR, VT, N0C, N1C); 2808 // canonicalize constant to RHS 2809 if (N0C && !N1C) 2810 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N1, N0); 2811 // fold (or x, 0) -> x 2812 if (N1C && N1C->isNullValue()) 2813 return N0; 2814 // fold (or x, -1) -> -1 2815 if (N1C && N1C->isAllOnesValue()) 2816 return N1; 2817 // fold (or x, c) -> c iff (x & ~c) == 0 2818 if (N1C && DAG.MaskedValueIsZero(N0, ~N1C->getAPIntValue())) 2819 return N1; 2820 2821 // Recognize halfword bswaps as (bswap + rotl 16) or (bswap + shl 16) 2822 SDValue BSwap = MatchBSwapHWord(N, N0, N1); 2823 if (BSwap.getNode() != 0) 2824 return BSwap; 2825 BSwap = MatchBSwapHWordLow(N, N0, N1); 2826 if (BSwap.getNode() != 0) 2827 return BSwap; 2828 2829 // reassociate or 2830 SDValue ROR = ReassociateOps(ISD::OR, N->getDebugLoc(), N0, N1); 2831 if (ROR.getNode() != 0) 2832 return ROR; 2833 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2) 2834 // iff (c1 & c2) == 0. 2835 if (N1C && N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() && 2836 isa<ConstantSDNode>(N0.getOperand(1))) { 2837 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1)); 2838 if ((C1->getAPIntValue() & N1C->getAPIntValue()) != 0) 2839 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 2840 DAG.getNode(ISD::OR, N0.getDebugLoc(), VT, 2841 N0.getOperand(0), N1), 2842 DAG.FoldConstantArithmetic(ISD::OR, VT, N1C, C1)); 2843 } 2844 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y)) 2845 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 2846 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 2847 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 2848 2849 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 2850 LL.getValueType().isInteger()) { 2851 // fold (or (setne X, 0), (setne Y, 0)) -> (setne (or X, Y), 0) 2852 // fold (or (setlt X, 0), (setlt Y, 0)) -> (setne (or X, Y), 0) 2853 if (cast<ConstantSDNode>(LR)->isNullValue() && 2854 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) { 2855 SDValue ORNode = DAG.getNode(ISD::OR, LR.getDebugLoc(), 2856 LR.getValueType(), LL, RL); 2857 AddToWorkList(ORNode.getNode()); 2858 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 2859 } 2860 // fold (or (setne X, -1), (setne Y, -1)) -> (setne (and X, Y), -1) 2861 // fold (or (setgt X, -1), (setgt Y -1)) -> (setgt (and X, Y), -1) 2862 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && 2863 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) { 2864 SDValue ANDNode = DAG.getNode(ISD::AND, LR.getDebugLoc(), 2865 LR.getValueType(), LL, RL); 2866 AddToWorkList(ANDNode.getNode()); 2867 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1); 2868 } 2869 } 2870 // canonicalize equivalent to ll == rl 2871 if (LL == RR && LR == RL) { 2872 Op1 = ISD::getSetCCSwappedOperands(Op1); 2873 std::swap(RL, RR); 2874 } 2875 if (LL == RL && LR == RR) { 2876 bool isInteger = LL.getValueType().isInteger(); 2877 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger); 2878 if (Result != ISD::SETCC_INVALID && 2879 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType()))) 2880 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(), 2881 LL, LR, Result); 2882 } 2883 } 2884 2885 // Simplify: (or (op x...), (op y...)) -> (op (or x, y)) 2886 if (N0.getOpcode() == N1.getOpcode()) { 2887 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 2888 if (Tmp.getNode()) return Tmp; 2889 } 2890 2891 // (or (and X, C1), (and Y, C2)) -> (and (or X, Y), C3) if possible. 2892 if (N0.getOpcode() == ISD::AND && 2893 N1.getOpcode() == ISD::AND && 2894 N0.getOperand(1).getOpcode() == ISD::Constant && 2895 N1.getOperand(1).getOpcode() == ISD::Constant && 2896 // Don't increase # computations. 2897 (N0.getNode()->hasOneUse() || N1.getNode()->hasOneUse())) { 2898 // We can only do this xform if we know that bits from X that are set in C2 2899 // but not in C1 are already zero. Likewise for Y. 2900 const APInt &LHSMask = 2901 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 2902 const APInt &RHSMask = 2903 cast<ConstantSDNode>(N1.getOperand(1))->getAPIntValue(); 2904 2905 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) && 2906 DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) { 2907 SDValue X = DAG.getNode(ISD::OR, N0.getDebugLoc(), VT, 2908 N0.getOperand(0), N1.getOperand(0)); 2909 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, X, 2910 DAG.getConstant(LHSMask | RHSMask, VT)); 2911 } 2912 } 2913 2914 // See if this is some rotate idiom. 2915 if (SDNode *Rot = MatchRotate(N0, N1, N->getDebugLoc())) 2916 return SDValue(Rot, 0); 2917 2918 // Simplify the operands using demanded-bits information. 2919 if (!VT.isVector() && 2920 SimplifyDemandedBits(SDValue(N, 0))) 2921 return SDValue(N, 0); 2922 2923 return SDValue(); 2924} 2925 2926/// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present. 2927static bool MatchRotateHalf(SDValue Op, SDValue &Shift, SDValue &Mask) { 2928 if (Op.getOpcode() == ISD::AND) { 2929 if (isa<ConstantSDNode>(Op.getOperand(1))) { 2930 Mask = Op.getOperand(1); 2931 Op = Op.getOperand(0); 2932 } else { 2933 return false; 2934 } 2935 } 2936 2937 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) { 2938 Shift = Op; 2939 return true; 2940 } 2941 2942 return false; 2943} 2944 2945// MatchRotate - Handle an 'or' of two operands. If this is one of the many 2946// idioms for rotate, and if the target supports rotation instructions, generate 2947// a rot[lr]. 2948SDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL) { 2949 // Must be a legal type. Expanded 'n promoted things won't work with rotates. 2950 EVT VT = LHS.getValueType(); 2951 if (!TLI.isTypeLegal(VT)) return 0; 2952 2953 // The target must have at least one rotate flavor. 2954 bool HasROTL = TLI.isOperationLegalOrCustom(ISD::ROTL, VT); 2955 bool HasROTR = TLI.isOperationLegalOrCustom(ISD::ROTR, VT); 2956 if (!HasROTL && !HasROTR) return 0; 2957 2958 // Match "(X shl/srl V1) & V2" where V2 may not be present. 2959 SDValue LHSShift; // The shift. 2960 SDValue LHSMask; // AND value if any. 2961 if (!MatchRotateHalf(LHS, LHSShift, LHSMask)) 2962 return 0; // Not part of a rotate. 2963 2964 SDValue RHSShift; // The shift. 2965 SDValue RHSMask; // AND value if any. 2966 if (!MatchRotateHalf(RHS, RHSShift, RHSMask)) 2967 return 0; // Not part of a rotate. 2968 2969 if (LHSShift.getOperand(0) != RHSShift.getOperand(0)) 2970 return 0; // Not shifting the same value. 2971 2972 if (LHSShift.getOpcode() == RHSShift.getOpcode()) 2973 return 0; // Shifts must disagree. 2974 2975 // Canonicalize shl to left side in a shl/srl pair. 2976 if (RHSShift.getOpcode() == ISD::SHL) { 2977 std::swap(LHS, RHS); 2978 std::swap(LHSShift, RHSShift); 2979 std::swap(LHSMask , RHSMask ); 2980 } 2981 2982 unsigned OpSizeInBits = VT.getSizeInBits(); 2983 SDValue LHSShiftArg = LHSShift.getOperand(0); 2984 SDValue LHSShiftAmt = LHSShift.getOperand(1); 2985 SDValue RHSShiftAmt = RHSShift.getOperand(1); 2986 2987 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1) 2988 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2) 2989 if (LHSShiftAmt.getOpcode() == ISD::Constant && 2990 RHSShiftAmt.getOpcode() == ISD::Constant) { 2991 uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getZExtValue(); 2992 uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getZExtValue(); 2993 if ((LShVal + RShVal) != OpSizeInBits) 2994 return 0; 2995 2996 SDValue Rot; 2997 if (HasROTL) 2998 Rot = DAG.getNode(ISD::ROTL, DL, VT, LHSShiftArg, LHSShiftAmt); 2999 else 3000 Rot = DAG.getNode(ISD::ROTR, DL, VT, LHSShiftArg, RHSShiftAmt); 3001 3002 // If there is an AND of either shifted operand, apply it to the result. 3003 if (LHSMask.getNode() || RHSMask.getNode()) { 3004 APInt Mask = APInt::getAllOnesValue(OpSizeInBits); 3005 3006 if (LHSMask.getNode()) { 3007 APInt RHSBits = APInt::getLowBitsSet(OpSizeInBits, LShVal); 3008 Mask &= cast<ConstantSDNode>(LHSMask)->getAPIntValue() | RHSBits; 3009 } 3010 if (RHSMask.getNode()) { 3011 APInt LHSBits = APInt::getHighBitsSet(OpSizeInBits, RShVal); 3012 Mask &= cast<ConstantSDNode>(RHSMask)->getAPIntValue() | LHSBits; 3013 } 3014 3015 Rot = DAG.getNode(ISD::AND, DL, VT, Rot, DAG.getConstant(Mask, VT)); 3016 } 3017 3018 return Rot.getNode(); 3019 } 3020 3021 // If there is a mask here, and we have a variable shift, we can't be sure 3022 // that we're masking out the right stuff. 3023 if (LHSMask.getNode() || RHSMask.getNode()) 3024 return 0; 3025 3026 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y) 3027 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y)) 3028 if (RHSShiftAmt.getOpcode() == ISD::SUB && 3029 LHSShiftAmt == RHSShiftAmt.getOperand(1)) { 3030 if (ConstantSDNode *SUBC = 3031 dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) { 3032 if (SUBC->getAPIntValue() == OpSizeInBits) { 3033 if (HasROTL) 3034 return DAG.getNode(ISD::ROTL, DL, VT, 3035 LHSShiftArg, LHSShiftAmt).getNode(); 3036 else 3037 return DAG.getNode(ISD::ROTR, DL, VT, 3038 LHSShiftArg, RHSShiftAmt).getNode(); 3039 } 3040 } 3041 } 3042 3043 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y) 3044 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y)) 3045 if (LHSShiftAmt.getOpcode() == ISD::SUB && 3046 RHSShiftAmt == LHSShiftAmt.getOperand(1)) { 3047 if (ConstantSDNode *SUBC = 3048 dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) { 3049 if (SUBC->getAPIntValue() == OpSizeInBits) { 3050 if (HasROTR) 3051 return DAG.getNode(ISD::ROTR, DL, VT, 3052 LHSShiftArg, RHSShiftAmt).getNode(); 3053 else 3054 return DAG.getNode(ISD::ROTL, DL, VT, 3055 LHSShiftArg, LHSShiftAmt).getNode(); 3056 } 3057 } 3058 } 3059 3060 // Look for sign/zext/any-extended or truncate cases: 3061 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 3062 || LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 3063 || LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND 3064 || LHSShiftAmt.getOpcode() == ISD::TRUNCATE) && 3065 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 3066 || RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 3067 || RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND 3068 || RHSShiftAmt.getOpcode() == ISD::TRUNCATE)) { 3069 SDValue LExtOp0 = LHSShiftAmt.getOperand(0); 3070 SDValue RExtOp0 = RHSShiftAmt.getOperand(0); 3071 if (RExtOp0.getOpcode() == ISD::SUB && 3072 RExtOp0.getOperand(1) == LExtOp0) { 3073 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 3074 // (rotl x, y) 3075 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 3076 // (rotr x, (sub 32, y)) 3077 if (ConstantSDNode *SUBC = 3078 dyn_cast<ConstantSDNode>(RExtOp0.getOperand(0))) { 3079 if (SUBC->getAPIntValue() == OpSizeInBits) { 3080 return DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT, 3081 LHSShiftArg, 3082 HasROTL ? LHSShiftAmt : RHSShiftAmt).getNode(); 3083 } 3084 } 3085 } else if (LExtOp0.getOpcode() == ISD::SUB && 3086 RExtOp0 == LExtOp0.getOperand(1)) { 3087 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) -> 3088 // (rotr x, y) 3089 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) -> 3090 // (rotl x, (sub 32, y)) 3091 if (ConstantSDNode *SUBC = 3092 dyn_cast<ConstantSDNode>(LExtOp0.getOperand(0))) { 3093 if (SUBC->getAPIntValue() == OpSizeInBits) { 3094 return DAG.getNode(HasROTR ? ISD::ROTR : ISD::ROTL, DL, VT, 3095 LHSShiftArg, 3096 HasROTR ? RHSShiftAmt : LHSShiftAmt).getNode(); 3097 } 3098 } 3099 } 3100 } 3101 3102 return 0; 3103} 3104 3105SDValue DAGCombiner::visitXOR(SDNode *N) { 3106 SDValue N0 = N->getOperand(0); 3107 SDValue N1 = N->getOperand(1); 3108 SDValue LHS, RHS, CC; 3109 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3110 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3111 EVT VT = N0.getValueType(); 3112 3113 // fold vector ops 3114 if (VT.isVector()) { 3115 SDValue FoldedVOp = SimplifyVBinOp(N); 3116 if (FoldedVOp.getNode()) return FoldedVOp; 3117 } 3118 3119 // fold (xor undef, undef) -> 0. This is a common idiom (misuse). 3120 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF) 3121 return DAG.getConstant(0, VT); 3122 // fold (xor x, undef) -> undef 3123 if (N0.getOpcode() == ISD::UNDEF) 3124 return N0; 3125 if (N1.getOpcode() == ISD::UNDEF) 3126 return N1; 3127 // fold (xor c1, c2) -> c1^c2 3128 if (N0C && N1C) 3129 return DAG.FoldConstantArithmetic(ISD::XOR, VT, N0C, N1C); 3130 // canonicalize constant to RHS 3131 if (N0C && !N1C) 3132 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0); 3133 // fold (xor x, 0) -> x 3134 if (N1C && N1C->isNullValue()) 3135 return N0; 3136 // reassociate xor 3137 SDValue RXOR = ReassociateOps(ISD::XOR, N->getDebugLoc(), N0, N1); 3138 if (RXOR.getNode() != 0) 3139 return RXOR; 3140 3141 // fold !(x cc y) -> (x !cc y) 3142 if (N1C && N1C->getAPIntValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) { 3143 bool isInt = LHS.getValueType().isInteger(); 3144 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(), 3145 isInt); 3146 3147 if (!LegalOperations || TLI.isCondCodeLegal(NotCC, LHS.getValueType())) { 3148 switch (N0.getOpcode()) { 3149 default: 3150 llvm_unreachable("Unhandled SetCC Equivalent!"); 3151 case ISD::SETCC: 3152 return DAG.getSetCC(N->getDebugLoc(), VT, LHS, RHS, NotCC); 3153 case ISD::SELECT_CC: 3154 return DAG.getSelectCC(N->getDebugLoc(), LHS, RHS, N0.getOperand(2), 3155 N0.getOperand(3), NotCC); 3156 } 3157 } 3158 } 3159 3160 // fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y))) 3161 if (N1C && N1C->getAPIntValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND && 3162 N0.getNode()->hasOneUse() && 3163 isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){ 3164 SDValue V = N0.getOperand(0); 3165 V = DAG.getNode(ISD::XOR, N0.getDebugLoc(), V.getValueType(), V, 3166 DAG.getConstant(1, V.getValueType())); 3167 AddToWorkList(V.getNode()); 3168 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, V); 3169 } 3170 3171 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are setcc 3172 if (N1C && N1C->getAPIntValue() == 1 && VT == MVT::i1 && 3173 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 3174 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1); 3175 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) { 3176 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 3177 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS 3178 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS 3179 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode()); 3180 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS); 3181 } 3182 } 3183 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are constants 3184 if (N1C && N1C->isAllOnesValue() && 3185 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 3186 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1); 3187 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) { 3188 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 3189 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS 3190 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS 3191 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode()); 3192 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS); 3193 } 3194 } 3195 // fold (xor (xor x, c1), c2) -> (xor x, (xor c1, c2)) 3196 if (N1C && N0.getOpcode() == ISD::XOR) { 3197 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0)); 3198 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 3199 if (N00C) 3200 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(1), 3201 DAG.getConstant(N1C->getAPIntValue() ^ 3202 N00C->getAPIntValue(), VT)); 3203 if (N01C) 3204 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(0), 3205 DAG.getConstant(N1C->getAPIntValue() ^ 3206 N01C->getAPIntValue(), VT)); 3207 } 3208 // fold (xor x, x) -> 0 3209 if (N0 == N1) 3210 return tryFoldToZero(N->getDebugLoc(), TLI, VT, DAG, LegalOperations); 3211 3212 // Simplify: xor (op x...), (op y...) -> (op (xor x, y)) 3213 if (N0.getOpcode() == N1.getOpcode()) { 3214 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 3215 if (Tmp.getNode()) return Tmp; 3216 } 3217 3218 // Simplify the expression using non-local knowledge. 3219 if (!VT.isVector() && 3220 SimplifyDemandedBits(SDValue(N, 0))) 3221 return SDValue(N, 0); 3222 3223 return SDValue(); 3224} 3225 3226/// visitShiftByConstant - Handle transforms common to the three shifts, when 3227/// the shift amount is a constant. 3228SDValue DAGCombiner::visitShiftByConstant(SDNode *N, unsigned Amt) { 3229 SDNode *LHS = N->getOperand(0).getNode(); 3230 if (!LHS->hasOneUse()) return SDValue(); 3231 3232 // We want to pull some binops through shifts, so that we have (and (shift)) 3233 // instead of (shift (and)), likewise for add, or, xor, etc. This sort of 3234 // thing happens with address calculations, so it's important to canonicalize 3235 // it. 3236 bool HighBitSet = false; // Can we transform this if the high bit is set? 3237 3238 switch (LHS->getOpcode()) { 3239 default: return SDValue(); 3240 case ISD::OR: 3241 case ISD::XOR: 3242 HighBitSet = false; // We can only transform sra if the high bit is clear. 3243 break; 3244 case ISD::AND: 3245 HighBitSet = true; // We can only transform sra if the high bit is set. 3246 break; 3247 case ISD::ADD: 3248 if (N->getOpcode() != ISD::SHL) 3249 return SDValue(); // only shl(add) not sr[al](add). 3250 HighBitSet = false; // We can only transform sra if the high bit is clear. 3251 break; 3252 } 3253 3254 // We require the RHS of the binop to be a constant as well. 3255 ConstantSDNode *BinOpCst = dyn_cast<ConstantSDNode>(LHS->getOperand(1)); 3256 if (!BinOpCst) return SDValue(); 3257 3258 // FIXME: disable this unless the input to the binop is a shift by a constant. 3259 // If it is not a shift, it pessimizes some common cases like: 3260 // 3261 // void foo(int *X, int i) { X[i & 1235] = 1; } 3262 // int bar(int *X, int i) { return X[i & 255]; } 3263 SDNode *BinOpLHSVal = LHS->getOperand(0).getNode(); 3264 if ((BinOpLHSVal->getOpcode() != ISD::SHL && 3265 BinOpLHSVal->getOpcode() != ISD::SRA && 3266 BinOpLHSVal->getOpcode() != ISD::SRL) || 3267 !isa<ConstantSDNode>(BinOpLHSVal->getOperand(1))) 3268 return SDValue(); 3269 3270 EVT VT = N->getValueType(0); 3271 3272 // If this is a signed shift right, and the high bit is modified by the 3273 // logical operation, do not perform the transformation. The highBitSet 3274 // boolean indicates the value of the high bit of the constant which would 3275 // cause it to be modified for this operation. 3276 if (N->getOpcode() == ISD::SRA) { 3277 bool BinOpRHSSignSet = BinOpCst->getAPIntValue().isNegative(); 3278 if (BinOpRHSSignSet != HighBitSet) 3279 return SDValue(); 3280 } 3281 3282 // Fold the constants, shifting the binop RHS by the shift amount. 3283 SDValue NewRHS = DAG.getNode(N->getOpcode(), LHS->getOperand(1).getDebugLoc(), 3284 N->getValueType(0), 3285 LHS->getOperand(1), N->getOperand(1)); 3286 3287 // Create the new shift. 3288 SDValue NewShift = DAG.getNode(N->getOpcode(), 3289 LHS->getOperand(0).getDebugLoc(), 3290 VT, LHS->getOperand(0), N->getOperand(1)); 3291 3292 // Create the new binop. 3293 return DAG.getNode(LHS->getOpcode(), N->getDebugLoc(), VT, NewShift, NewRHS); 3294} 3295 3296SDValue DAGCombiner::visitSHL(SDNode *N) { 3297 SDValue N0 = N->getOperand(0); 3298 SDValue N1 = N->getOperand(1); 3299 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3300 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3301 EVT VT = N0.getValueType(); 3302 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits(); 3303 3304 // fold (shl c1, c2) -> c1<<c2 3305 if (N0C && N1C) 3306 return DAG.FoldConstantArithmetic(ISD::SHL, VT, N0C, N1C); 3307 // fold (shl 0, x) -> 0 3308 if (N0C && N0C->isNullValue()) 3309 return N0; 3310 // fold (shl x, c >= size(x)) -> undef 3311 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 3312 return DAG.getUNDEF(VT); 3313 // fold (shl x, 0) -> x 3314 if (N1C && N1C->isNullValue()) 3315 return N0; 3316 // fold (shl undef, x) -> 0 3317 if (N0.getOpcode() == ISD::UNDEF) 3318 return DAG.getConstant(0, VT); 3319 // if (shl x, c) is known to be zero, return 0 3320 if (DAG.MaskedValueIsZero(SDValue(N, 0), 3321 APInt::getAllOnesValue(OpSizeInBits))) 3322 return DAG.getConstant(0, VT); 3323 // fold (shl x, (trunc (and y, c))) -> (shl x, (and (trunc y), (trunc c))). 3324 if (N1.getOpcode() == ISD::TRUNCATE && 3325 N1.getOperand(0).getOpcode() == ISD::AND && 3326 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 3327 SDValue N101 = N1.getOperand(0).getOperand(1); 3328 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 3329 EVT TruncVT = N1.getValueType(); 3330 SDValue N100 = N1.getOperand(0).getOperand(0); 3331 APInt TruncC = N101C->getAPIntValue(); 3332 TruncC = TruncC.trunc(TruncVT.getSizeInBits()); 3333 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 3334 DAG.getNode(ISD::AND, N->getDebugLoc(), TruncVT, 3335 DAG.getNode(ISD::TRUNCATE, 3336 N->getDebugLoc(), 3337 TruncVT, N100), 3338 DAG.getConstant(TruncC, TruncVT))); 3339 } 3340 } 3341 3342 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 3343 return SDValue(N, 0); 3344 3345 // fold (shl (shl x, c1), c2) -> 0 or (shl x, (add c1, c2)) 3346 if (N1C && N0.getOpcode() == ISD::SHL && 3347 N0.getOperand(1).getOpcode() == ISD::Constant) { 3348 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 3349 uint64_t c2 = N1C->getZExtValue(); 3350 if (c1 + c2 >= OpSizeInBits) 3351 return DAG.getConstant(0, VT); 3352 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0.getOperand(0), 3353 DAG.getConstant(c1 + c2, N1.getValueType())); 3354 } 3355 3356 // fold (shl (ext (shl x, c1)), c2) -> (ext (shl x, (add c1, c2))) 3357 // For this to be valid, the second form must not preserve any of the bits 3358 // that are shifted out by the inner shift in the first form. This means 3359 // the outer shift size must be >= the number of bits added by the ext. 3360 // As a corollary, we don't care what kind of ext it is. 3361 if (N1C && (N0.getOpcode() == ISD::ZERO_EXTEND || 3362 N0.getOpcode() == ISD::ANY_EXTEND || 3363 N0.getOpcode() == ISD::SIGN_EXTEND) && 3364 N0.getOperand(0).getOpcode() == ISD::SHL && 3365 isa<ConstantSDNode>(N0.getOperand(0)->getOperand(1))) { 3366 uint64_t c1 = 3367 cast<ConstantSDNode>(N0.getOperand(0)->getOperand(1))->getZExtValue(); 3368 uint64_t c2 = N1C->getZExtValue(); 3369 EVT InnerShiftVT = N0.getOperand(0).getValueType(); 3370 uint64_t InnerShiftSize = InnerShiftVT.getScalarType().getSizeInBits(); 3371 if (c2 >= OpSizeInBits - InnerShiftSize) { 3372 if (c1 + c2 >= OpSizeInBits) 3373 return DAG.getConstant(0, VT); 3374 return DAG.getNode(ISD::SHL, N0->getDebugLoc(), VT, 3375 DAG.getNode(N0.getOpcode(), N0->getDebugLoc(), VT, 3376 N0.getOperand(0)->getOperand(0)), 3377 DAG.getConstant(c1 + c2, N1.getValueType())); 3378 } 3379 } 3380 3381 // fold (shl (srl x, c1), c2) -> (and (shl x, (sub c2, c1), MASK) or 3382 // (and (srl x, (sub c1, c2), MASK) 3383 // Only fold this if the inner shift has no other uses -- if it does, folding 3384 // this will increase the total number of instructions. 3385 if (N1C && N0.getOpcode() == ISD::SRL && N0.hasOneUse() && 3386 N0.getOperand(1).getOpcode() == ISD::Constant) { 3387 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 3388 if (c1 < VT.getSizeInBits()) { 3389 uint64_t c2 = N1C->getZExtValue(); 3390 APInt Mask = APInt::getHighBitsSet(VT.getSizeInBits(), 3391 VT.getSizeInBits() - c1); 3392 SDValue Shift; 3393 if (c2 > c1) { 3394 Mask = Mask.shl(c2-c1); 3395 Shift = DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0.getOperand(0), 3396 DAG.getConstant(c2-c1, N1.getValueType())); 3397 } else { 3398 Mask = Mask.lshr(c1-c2); 3399 Shift = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), 3400 DAG.getConstant(c1-c2, N1.getValueType())); 3401 } 3402 return DAG.getNode(ISD::AND, N0.getDebugLoc(), VT, Shift, 3403 DAG.getConstant(Mask, VT)); 3404 } 3405 } 3406 // fold (shl (sra x, c1), c1) -> (and x, (shl -1, c1)) 3407 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) { 3408 SDValue HiBitsMask = 3409 DAG.getConstant(APInt::getHighBitsSet(VT.getSizeInBits(), 3410 VT.getSizeInBits() - 3411 N1C->getZExtValue()), 3412 VT); 3413 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0), 3414 HiBitsMask); 3415 } 3416 3417 if (N1C) { 3418 SDValue NewSHL = visitShiftByConstant(N, N1C->getZExtValue()); 3419 if (NewSHL.getNode()) 3420 return NewSHL; 3421 } 3422 3423 return SDValue(); 3424} 3425 3426SDValue DAGCombiner::visitSRA(SDNode *N) { 3427 SDValue N0 = N->getOperand(0); 3428 SDValue N1 = N->getOperand(1); 3429 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3430 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3431 EVT VT = N0.getValueType(); 3432 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits(); 3433 3434 // fold (sra c1, c2) -> (sra c1, c2) 3435 if (N0C && N1C) 3436 return DAG.FoldConstantArithmetic(ISD::SRA, VT, N0C, N1C); 3437 // fold (sra 0, x) -> 0 3438 if (N0C && N0C->isNullValue()) 3439 return N0; 3440 // fold (sra -1, x) -> -1 3441 if (N0C && N0C->isAllOnesValue()) 3442 return N0; 3443 // fold (sra x, (setge c, size(x))) -> undef 3444 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 3445 return DAG.getUNDEF(VT); 3446 // fold (sra x, 0) -> x 3447 if (N1C && N1C->isNullValue()) 3448 return N0; 3449 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports 3450 // sext_inreg. 3451 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) { 3452 unsigned LowBits = OpSizeInBits - (unsigned)N1C->getZExtValue(); 3453 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), LowBits); 3454 if (VT.isVector()) 3455 ExtVT = EVT::getVectorVT(*DAG.getContext(), 3456 ExtVT, VT.getVectorNumElements()); 3457 if ((!LegalOperations || 3458 TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, ExtVT))) 3459 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, 3460 N0.getOperand(0), DAG.getValueType(ExtVT)); 3461 } 3462 3463 // fold (sra (sra x, c1), c2) -> (sra x, (add c1, c2)) 3464 if (N1C && N0.getOpcode() == ISD::SRA) { 3465 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 3466 unsigned Sum = N1C->getZExtValue() + C1->getZExtValue(); 3467 if (Sum >= OpSizeInBits) Sum = OpSizeInBits-1; 3468 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0.getOperand(0), 3469 DAG.getConstant(Sum, N1C->getValueType(0))); 3470 } 3471 } 3472 3473 // fold (sra (shl X, m), (sub result_size, n)) 3474 // -> (sign_extend (trunc (shl X, (sub (sub result_size, n), m)))) for 3475 // result_size - n != m. 3476 // If truncate is free for the target sext(shl) is likely to result in better 3477 // code. 3478 if (N0.getOpcode() == ISD::SHL) { 3479 // Get the two constanst of the shifts, CN0 = m, CN = n. 3480 const ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 3481 if (N01C && N1C) { 3482 // Determine what the truncate's result bitsize and type would be. 3483 EVT TruncVT = 3484 EVT::getIntegerVT(*DAG.getContext(), 3485 OpSizeInBits - N1C->getZExtValue()); 3486 // Determine the residual right-shift amount. 3487 signed ShiftAmt = N1C->getZExtValue() - N01C->getZExtValue(); 3488 3489 // If the shift is not a no-op (in which case this should be just a sign 3490 // extend already), the truncated to type is legal, sign_extend is legal 3491 // on that type, and the truncate to that type is both legal and free, 3492 // perform the transform. 3493 if ((ShiftAmt > 0) && 3494 TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND, TruncVT) && 3495 TLI.isOperationLegalOrCustom(ISD::TRUNCATE, VT) && 3496 TLI.isTruncateFree(VT, TruncVT)) { 3497 3498 SDValue Amt = DAG.getConstant(ShiftAmt, 3499 getShiftAmountTy(N0.getOperand(0).getValueType())); 3500 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, 3501 N0.getOperand(0), Amt); 3502 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), TruncVT, 3503 Shift); 3504 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), 3505 N->getValueType(0), Trunc); 3506 } 3507 } 3508 } 3509 3510 // fold (sra x, (trunc (and y, c))) -> (sra x, (and (trunc y), (trunc c))). 3511 if (N1.getOpcode() == ISD::TRUNCATE && 3512 N1.getOperand(0).getOpcode() == ISD::AND && 3513 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 3514 SDValue N101 = N1.getOperand(0).getOperand(1); 3515 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 3516 EVT TruncVT = N1.getValueType(); 3517 SDValue N100 = N1.getOperand(0).getOperand(0); 3518 APInt TruncC = N101C->getAPIntValue(); 3519 TruncC = TruncC.trunc(TruncVT.getScalarType().getSizeInBits()); 3520 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0, 3521 DAG.getNode(ISD::AND, N->getDebugLoc(), 3522 TruncVT, 3523 DAG.getNode(ISD::TRUNCATE, 3524 N->getDebugLoc(), 3525 TruncVT, N100), 3526 DAG.getConstant(TruncC, TruncVT))); 3527 } 3528 } 3529 3530 // fold (sra (trunc (sr x, c1)), c2) -> (trunc (sra x, c1+c2)) 3531 // if c1 is equal to the number of bits the trunc removes 3532 if (N0.getOpcode() == ISD::TRUNCATE && 3533 (N0.getOperand(0).getOpcode() == ISD::SRL || 3534 N0.getOperand(0).getOpcode() == ISD::SRA) && 3535 N0.getOperand(0).hasOneUse() && 3536 N0.getOperand(0).getOperand(1).hasOneUse() && 3537 N1C && isa<ConstantSDNode>(N0.getOperand(0).getOperand(1))) { 3538 EVT LargeVT = N0.getOperand(0).getValueType(); 3539 ConstantSDNode *LargeShiftAmt = 3540 cast<ConstantSDNode>(N0.getOperand(0).getOperand(1)); 3541 3542 if (LargeVT.getScalarType().getSizeInBits() - OpSizeInBits == 3543 LargeShiftAmt->getZExtValue()) { 3544 SDValue Amt = 3545 DAG.getConstant(LargeShiftAmt->getZExtValue() + N1C->getZExtValue(), 3546 getShiftAmountTy(N0.getOperand(0).getOperand(0).getValueType())); 3547 SDValue SRA = DAG.getNode(ISD::SRA, N->getDebugLoc(), LargeVT, 3548 N0.getOperand(0).getOperand(0), Amt); 3549 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, SRA); 3550 } 3551 } 3552 3553 // Simplify, based on bits shifted out of the LHS. 3554 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 3555 return SDValue(N, 0); 3556 3557 3558 // If the sign bit is known to be zero, switch this to a SRL. 3559 if (DAG.SignBitIsZero(N0)) 3560 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, N1); 3561 3562 if (N1C) { 3563 SDValue NewSRA = visitShiftByConstant(N, N1C->getZExtValue()); 3564 if (NewSRA.getNode()) 3565 return NewSRA; 3566 } 3567 3568 return SDValue(); 3569} 3570 3571SDValue DAGCombiner::visitSRL(SDNode *N) { 3572 SDValue N0 = N->getOperand(0); 3573 SDValue N1 = N->getOperand(1); 3574 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3575 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3576 EVT VT = N0.getValueType(); 3577 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits(); 3578 3579 // fold (srl c1, c2) -> c1 >>u c2 3580 if (N0C && N1C) 3581 return DAG.FoldConstantArithmetic(ISD::SRL, VT, N0C, N1C); 3582 // fold (srl 0, x) -> 0 3583 if (N0C && N0C->isNullValue()) 3584 return N0; 3585 // fold (srl x, c >= size(x)) -> undef 3586 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 3587 return DAG.getUNDEF(VT); 3588 // fold (srl x, 0) -> x 3589 if (N1C && N1C->isNullValue()) 3590 return N0; 3591 // if (srl x, c) is known to be zero, return 0 3592 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0), 3593 APInt::getAllOnesValue(OpSizeInBits))) 3594 return DAG.getConstant(0, VT); 3595 3596 // fold (srl (srl x, c1), c2) -> 0 or (srl x, (add c1, c2)) 3597 if (N1C && N0.getOpcode() == ISD::SRL && 3598 N0.getOperand(1).getOpcode() == ISD::Constant) { 3599 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 3600 uint64_t c2 = N1C->getZExtValue(); 3601 if (c1 + c2 >= OpSizeInBits) 3602 return DAG.getConstant(0, VT); 3603 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), 3604 DAG.getConstant(c1 + c2, N1.getValueType())); 3605 } 3606 3607 // fold (srl (trunc (srl x, c1)), c2) -> 0 or (trunc (srl x, (add c1, c2))) 3608 if (N1C && N0.getOpcode() == ISD::TRUNCATE && 3609 N0.getOperand(0).getOpcode() == ISD::SRL && 3610 isa<ConstantSDNode>(N0.getOperand(0)->getOperand(1))) { 3611 uint64_t c1 = 3612 cast<ConstantSDNode>(N0.getOperand(0)->getOperand(1))->getZExtValue(); 3613 uint64_t c2 = N1C->getZExtValue(); 3614 EVT InnerShiftVT = N0.getOperand(0).getValueType(); 3615 EVT ShiftCountVT = N0.getOperand(0)->getOperand(1).getValueType(); 3616 uint64_t InnerShiftSize = InnerShiftVT.getScalarType().getSizeInBits(); 3617 // This is only valid if the OpSizeInBits + c1 = size of inner shift. 3618 if (c1 + OpSizeInBits == InnerShiftSize) { 3619 if (c1 + c2 >= InnerShiftSize) 3620 return DAG.getConstant(0, VT); 3621 return DAG.getNode(ISD::TRUNCATE, N0->getDebugLoc(), VT, 3622 DAG.getNode(ISD::SRL, N0->getDebugLoc(), InnerShiftVT, 3623 N0.getOperand(0)->getOperand(0), 3624 DAG.getConstant(c1 + c2, ShiftCountVT))); 3625 } 3626 } 3627 3628 // fold (srl (shl x, c), c) -> (and x, cst2) 3629 if (N1C && N0.getOpcode() == ISD::SHL && N0.getOperand(1) == N1 && 3630 N0.getValueSizeInBits() <= 64) { 3631 uint64_t ShAmt = N1C->getZExtValue()+64-N0.getValueSizeInBits(); 3632 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0), 3633 DAG.getConstant(~0ULL >> ShAmt, VT)); 3634 } 3635 3636 3637 // fold (srl (anyextend x), c) -> (anyextend (srl x, c)) 3638 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 3639 // Shifting in all undef bits? 3640 EVT SmallVT = N0.getOperand(0).getValueType(); 3641 if (N1C->getZExtValue() >= SmallVT.getSizeInBits()) 3642 return DAG.getUNDEF(VT); 3643 3644 if (!LegalTypes || TLI.isTypeDesirableForOp(ISD::SRL, SmallVT)) { 3645 uint64_t ShiftAmt = N1C->getZExtValue(); 3646 SDValue SmallShift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), SmallVT, 3647 N0.getOperand(0), 3648 DAG.getConstant(ShiftAmt, getShiftAmountTy(SmallVT))); 3649 AddToWorkList(SmallShift.getNode()); 3650 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, SmallShift); 3651 } 3652 } 3653 3654 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign 3655 // bit, which is unmodified by sra. 3656 if (N1C && N1C->getZExtValue() + 1 == VT.getSizeInBits()) { 3657 if (N0.getOpcode() == ISD::SRA) 3658 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), N1); 3659 } 3660 3661 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit). 3662 if (N1C && N0.getOpcode() == ISD::CTLZ && 3663 N1C->getAPIntValue() == Log2_32(VT.getSizeInBits())) { 3664 APInt KnownZero, KnownOne; 3665 APInt Mask = APInt::getAllOnesValue(VT.getScalarType().getSizeInBits()); 3666 DAG.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne); 3667 3668 // If any of the input bits are KnownOne, then the input couldn't be all 3669 // zeros, thus the result of the srl will always be zero. 3670 if (KnownOne.getBoolValue()) return DAG.getConstant(0, VT); 3671 3672 // If all of the bits input the to ctlz node are known to be zero, then 3673 // the result of the ctlz is "32" and the result of the shift is one. 3674 APInt UnknownBits = ~KnownZero & Mask; 3675 if (UnknownBits == 0) return DAG.getConstant(1, VT); 3676 3677 // Otherwise, check to see if there is exactly one bit input to the ctlz. 3678 if ((UnknownBits & (UnknownBits - 1)) == 0) { 3679 // Okay, we know that only that the single bit specified by UnknownBits 3680 // could be set on input to the CTLZ node. If this bit is set, the SRL 3681 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair 3682 // to an SRL/XOR pair, which is likely to simplify more. 3683 unsigned ShAmt = UnknownBits.countTrailingZeros(); 3684 SDValue Op = N0.getOperand(0); 3685 3686 if (ShAmt) { 3687 Op = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, Op, 3688 DAG.getConstant(ShAmt, getShiftAmountTy(Op.getValueType()))); 3689 AddToWorkList(Op.getNode()); 3690 } 3691 3692 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, 3693 Op, DAG.getConstant(1, VT)); 3694 } 3695 } 3696 3697 // fold (srl x, (trunc (and y, c))) -> (srl x, (and (trunc y), (trunc c))). 3698 if (N1.getOpcode() == ISD::TRUNCATE && 3699 N1.getOperand(0).getOpcode() == ISD::AND && 3700 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 3701 SDValue N101 = N1.getOperand(0).getOperand(1); 3702 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 3703 EVT TruncVT = N1.getValueType(); 3704 SDValue N100 = N1.getOperand(0).getOperand(0); 3705 APInt TruncC = N101C->getAPIntValue(); 3706 TruncC = TruncC.trunc(TruncVT.getSizeInBits()); 3707 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, 3708 DAG.getNode(ISD::AND, N->getDebugLoc(), 3709 TruncVT, 3710 DAG.getNode(ISD::TRUNCATE, 3711 N->getDebugLoc(), 3712 TruncVT, N100), 3713 DAG.getConstant(TruncC, TruncVT))); 3714 } 3715 } 3716 3717 // fold operands of srl based on knowledge that the low bits are not 3718 // demanded. 3719 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 3720 return SDValue(N, 0); 3721 3722 if (N1C) { 3723 SDValue NewSRL = visitShiftByConstant(N, N1C->getZExtValue()); 3724 if (NewSRL.getNode()) 3725 return NewSRL; 3726 } 3727 3728 // Attempt to convert a srl of a load into a narrower zero-extending load. 3729 SDValue NarrowLoad = ReduceLoadWidth(N); 3730 if (NarrowLoad.getNode()) 3731 return NarrowLoad; 3732 3733 // Here is a common situation. We want to optimize: 3734 // 3735 // %a = ... 3736 // %b = and i32 %a, 2 3737 // %c = srl i32 %b, 1 3738 // brcond i32 %c ... 3739 // 3740 // into 3741 // 3742 // %a = ... 3743 // %b = and %a, 2 3744 // %c = setcc eq %b, 0 3745 // brcond %c ... 3746 // 3747 // However when after the source operand of SRL is optimized into AND, the SRL 3748 // itself may not be optimized further. Look for it and add the BRCOND into 3749 // the worklist. 3750 if (N->hasOneUse()) { 3751 SDNode *Use = *N->use_begin(); 3752 if (Use->getOpcode() == ISD::BRCOND) 3753 AddToWorkList(Use); 3754 else if (Use->getOpcode() == ISD::TRUNCATE && Use->hasOneUse()) { 3755 // Also look pass the truncate. 3756 Use = *Use->use_begin(); 3757 if (Use->getOpcode() == ISD::BRCOND) 3758 AddToWorkList(Use); 3759 } 3760 } 3761 3762 return SDValue(); 3763} 3764 3765SDValue DAGCombiner::visitCTLZ(SDNode *N) { 3766 SDValue N0 = N->getOperand(0); 3767 EVT VT = N->getValueType(0); 3768 3769 // fold (ctlz c1) -> c2 3770 if (isa<ConstantSDNode>(N0)) 3771 return DAG.getNode(ISD::CTLZ, N->getDebugLoc(), VT, N0); 3772 return SDValue(); 3773} 3774 3775SDValue DAGCombiner::visitCTLZ_ZERO_UNDEF(SDNode *N) { 3776 SDValue N0 = N->getOperand(0); 3777 EVT VT = N->getValueType(0); 3778 3779 // fold (ctlz_zero_undef c1) -> c2 3780 if (isa<ConstantSDNode>(N0)) 3781 return DAG.getNode(ISD::CTLZ_ZERO_UNDEF, N->getDebugLoc(), VT, N0); 3782 return SDValue(); 3783} 3784 3785SDValue DAGCombiner::visitCTTZ(SDNode *N) { 3786 SDValue N0 = N->getOperand(0); 3787 EVT VT = N->getValueType(0); 3788 3789 // fold (cttz c1) -> c2 3790 if (isa<ConstantSDNode>(N0)) 3791 return DAG.getNode(ISD::CTTZ, N->getDebugLoc(), VT, N0); 3792 return SDValue(); 3793} 3794 3795SDValue DAGCombiner::visitCTTZ_ZERO_UNDEF(SDNode *N) { 3796 SDValue N0 = N->getOperand(0); 3797 EVT VT = N->getValueType(0); 3798 3799 // fold (cttz_zero_undef c1) -> c2 3800 if (isa<ConstantSDNode>(N0)) 3801 return DAG.getNode(ISD::CTTZ_ZERO_UNDEF, N->getDebugLoc(), VT, N0); 3802 return SDValue(); 3803} 3804 3805SDValue DAGCombiner::visitCTPOP(SDNode *N) { 3806 SDValue N0 = N->getOperand(0); 3807 EVT VT = N->getValueType(0); 3808 3809 // fold (ctpop c1) -> c2 3810 if (isa<ConstantSDNode>(N0)) 3811 return DAG.getNode(ISD::CTPOP, N->getDebugLoc(), VT, N0); 3812 return SDValue(); 3813} 3814 3815SDValue DAGCombiner::visitSELECT(SDNode *N) { 3816 SDValue N0 = N->getOperand(0); 3817 SDValue N1 = N->getOperand(1); 3818 SDValue N2 = N->getOperand(2); 3819 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3820 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3821 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2); 3822 EVT VT = N->getValueType(0); 3823 EVT VT0 = N0.getValueType(); 3824 3825 // fold (select C, X, X) -> X 3826 if (N1 == N2) 3827 return N1; 3828 // fold (select true, X, Y) -> X 3829 if (N0C && !N0C->isNullValue()) 3830 return N1; 3831 // fold (select false, X, Y) -> Y 3832 if (N0C && N0C->isNullValue()) 3833 return N2; 3834 // fold (select C, 1, X) -> (or C, X) 3835 if (VT == MVT::i1 && N1C && N1C->getAPIntValue() == 1) 3836 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2); 3837 // fold (select C, 0, 1) -> (xor C, 1) 3838 if (VT.isInteger() && 3839 (VT0 == MVT::i1 || 3840 (VT0.isInteger() && 3841 TLI.getBooleanContents(false) == TargetLowering::ZeroOrOneBooleanContent)) && 3842 N1C && N2C && N1C->isNullValue() && N2C->getAPIntValue() == 1) { 3843 SDValue XORNode; 3844 if (VT == VT0) 3845 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT0, 3846 N0, DAG.getConstant(1, VT0)); 3847 XORNode = DAG.getNode(ISD::XOR, N0.getDebugLoc(), VT0, 3848 N0, DAG.getConstant(1, VT0)); 3849 AddToWorkList(XORNode.getNode()); 3850 if (VT.bitsGT(VT0)) 3851 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, XORNode); 3852 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, XORNode); 3853 } 3854 // fold (select C, 0, X) -> (and (not C), X) 3855 if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) { 3856 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT); 3857 AddToWorkList(NOTNode.getNode()); 3858 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, NOTNode, N2); 3859 } 3860 // fold (select C, X, 1) -> (or (not C), X) 3861 if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getAPIntValue() == 1) { 3862 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT); 3863 AddToWorkList(NOTNode.getNode()); 3864 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, NOTNode, N1); 3865 } 3866 // fold (select C, X, 0) -> (and C, X) 3867 if (VT == MVT::i1 && N2C && N2C->isNullValue()) 3868 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1); 3869 // fold (select X, X, Y) -> (or X, Y) 3870 // fold (select X, 1, Y) -> (or X, Y) 3871 if (VT == MVT::i1 && (N0 == N1 || (N1C && N1C->getAPIntValue() == 1))) 3872 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2); 3873 // fold (select X, Y, X) -> (and X, Y) 3874 // fold (select X, Y, 0) -> (and X, Y) 3875 if (VT == MVT::i1 && (N0 == N2 || (N2C && N2C->getAPIntValue() == 0))) 3876 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1); 3877 3878 // If we can fold this based on the true/false value, do so. 3879 if (SimplifySelectOps(N, N1, N2)) 3880 return SDValue(N, 0); // Don't revisit N. 3881 3882 // fold selects based on a setcc into other things, such as min/max/abs 3883 if (N0.getOpcode() == ISD::SETCC) { 3884 // FIXME: 3885 // Check against MVT::Other for SELECT_CC, which is a workaround for targets 3886 // having to say they don't support SELECT_CC on every type the DAG knows 3887 // about, since there is no way to mark an opcode illegal at all value types 3888 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other) && 3889 TLI.isOperationLegalOrCustom(ISD::SELECT_CC, VT)) 3890 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT, 3891 N0.getOperand(0), N0.getOperand(1), 3892 N1, N2, N0.getOperand(2)); 3893 return SimplifySelect(N->getDebugLoc(), N0, N1, N2); 3894 } 3895 3896 return SDValue(); 3897} 3898 3899SDValue DAGCombiner::visitSELECT_CC(SDNode *N) { 3900 SDValue N0 = N->getOperand(0); 3901 SDValue N1 = N->getOperand(1); 3902 SDValue N2 = N->getOperand(2); 3903 SDValue N3 = N->getOperand(3); 3904 SDValue N4 = N->getOperand(4); 3905 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get(); 3906 3907 // fold select_cc lhs, rhs, x, x, cc -> x 3908 if (N2 == N3) 3909 return N2; 3910 3911 // Determine if the condition we're dealing with is constant 3912 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()), 3913 N0, N1, CC, N->getDebugLoc(), false); 3914 if (SCC.getNode()) AddToWorkList(SCC.getNode()); 3915 3916 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode())) { 3917 if (!SCCC->isNullValue()) 3918 return N2; // cond always true -> true val 3919 else 3920 return N3; // cond always false -> false val 3921 } 3922 3923 // Fold to a simpler select_cc 3924 if (SCC.getNode() && SCC.getOpcode() == ISD::SETCC) 3925 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), N2.getValueType(), 3926 SCC.getOperand(0), SCC.getOperand(1), N2, N3, 3927 SCC.getOperand(2)); 3928 3929 // If we can fold this based on the true/false value, do so. 3930 if (SimplifySelectOps(N, N2, N3)) 3931 return SDValue(N, 0); // Don't revisit N. 3932 3933 // fold select_cc into other things, such as min/max/abs 3934 return SimplifySelectCC(N->getDebugLoc(), N0, N1, N2, N3, CC); 3935} 3936 3937SDValue DAGCombiner::visitSETCC(SDNode *N) { 3938 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1), 3939 cast<CondCodeSDNode>(N->getOperand(2))->get(), 3940 N->getDebugLoc()); 3941} 3942 3943// ExtendUsesToFormExtLoad - Trying to extend uses of a load to enable this: 3944// "fold ({s|z|a}ext (load x)) -> ({s|z|a}ext (truncate ({s|z|a}extload x)))" 3945// transformation. Returns true if extension are possible and the above 3946// mentioned transformation is profitable. 3947static bool ExtendUsesToFormExtLoad(SDNode *N, SDValue N0, 3948 unsigned ExtOpc, 3949 SmallVector<SDNode*, 4> &ExtendNodes, 3950 const TargetLowering &TLI) { 3951 bool HasCopyToRegUses = false; 3952 bool isTruncFree = TLI.isTruncateFree(N->getValueType(0), N0.getValueType()); 3953 for (SDNode::use_iterator UI = N0.getNode()->use_begin(), 3954 UE = N0.getNode()->use_end(); 3955 UI != UE; ++UI) { 3956 SDNode *User = *UI; 3957 if (User == N) 3958 continue; 3959 if (UI.getUse().getResNo() != N0.getResNo()) 3960 continue; 3961 // FIXME: Only extend SETCC N, N and SETCC N, c for now. 3962 if (ExtOpc != ISD::ANY_EXTEND && User->getOpcode() == ISD::SETCC) { 3963 ISD::CondCode CC = cast<CondCodeSDNode>(User->getOperand(2))->get(); 3964 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC)) 3965 // Sign bits will be lost after a zext. 3966 return false; 3967 bool Add = false; 3968 for (unsigned i = 0; i != 2; ++i) { 3969 SDValue UseOp = User->getOperand(i); 3970 if (UseOp == N0) 3971 continue; 3972 if (!isa<ConstantSDNode>(UseOp)) 3973 return false; 3974 Add = true; 3975 } 3976 if (Add) 3977 ExtendNodes.push_back(User); 3978 continue; 3979 } 3980 // If truncates aren't free and there are users we can't 3981 // extend, it isn't worthwhile. 3982 if (!isTruncFree) 3983 return false; 3984 // Remember if this value is live-out. 3985 if (User->getOpcode() == ISD::CopyToReg) 3986 HasCopyToRegUses = true; 3987 } 3988 3989 if (HasCopyToRegUses) { 3990 bool BothLiveOut = false; 3991 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 3992 UI != UE; ++UI) { 3993 SDUse &Use = UI.getUse(); 3994 if (Use.getResNo() == 0 && Use.getUser()->getOpcode() == ISD::CopyToReg) { 3995 BothLiveOut = true; 3996 break; 3997 } 3998 } 3999 if (BothLiveOut) 4000 // Both unextended and extended values are live out. There had better be 4001 // a good reason for the transformation. 4002 return ExtendNodes.size(); 4003 } 4004 return true; 4005} 4006 4007void DAGCombiner::ExtendSetCCUses(SmallVector<SDNode*, 4> SetCCs, 4008 SDValue Trunc, SDValue ExtLoad, DebugLoc DL, 4009 ISD::NodeType ExtType) { 4010 // Extend SetCC uses if necessary. 4011 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 4012 SDNode *SetCC = SetCCs[i]; 4013 SmallVector<SDValue, 4> Ops; 4014 4015 for (unsigned j = 0; j != 2; ++j) { 4016 SDValue SOp = SetCC->getOperand(j); 4017 if (SOp == Trunc) 4018 Ops.push_back(ExtLoad); 4019 else 4020 Ops.push_back(DAG.getNode(ExtType, DL, ExtLoad->getValueType(0), SOp)); 4021 } 4022 4023 Ops.push_back(SetCC->getOperand(2)); 4024 CombineTo(SetCC, DAG.getNode(ISD::SETCC, DL, SetCC->getValueType(0), 4025 &Ops[0], Ops.size())); 4026 } 4027} 4028 4029SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) { 4030 SDValue N0 = N->getOperand(0); 4031 EVT VT = N->getValueType(0); 4032 4033 // fold (sext c1) -> c1 4034 if (isa<ConstantSDNode>(N0)) 4035 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N0); 4036 4037 // fold (sext (sext x)) -> (sext x) 4038 // fold (sext (aext x)) -> (sext x) 4039 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 4040 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, 4041 N0.getOperand(0)); 4042 4043 if (N0.getOpcode() == ISD::TRUNCATE) { 4044 // fold (sext (truncate (load x))) -> (sext (smaller load x)) 4045 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n))) 4046 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 4047 if (NarrowLoad.getNode()) { 4048 SDNode* oye = N0.getNode()->getOperand(0).getNode(); 4049 if (NarrowLoad.getNode() != N0.getNode()) { 4050 CombineTo(N0.getNode(), NarrowLoad); 4051 // CombineTo deleted the truncate, if needed, but not what's under it. 4052 AddToWorkList(oye); 4053 } 4054 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4055 } 4056 4057 // See if the value being truncated is already sign extended. If so, just 4058 // eliminate the trunc/sext pair. 4059 SDValue Op = N0.getOperand(0); 4060 unsigned OpBits = Op.getValueType().getScalarType().getSizeInBits(); 4061 unsigned MidBits = N0.getValueType().getScalarType().getSizeInBits(); 4062 unsigned DestBits = VT.getScalarType().getSizeInBits(); 4063 unsigned NumSignBits = DAG.ComputeNumSignBits(Op); 4064 4065 if (OpBits == DestBits) { 4066 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign 4067 // bits, it is already ready. 4068 if (NumSignBits > DestBits-MidBits) 4069 return Op; 4070 } else if (OpBits < DestBits) { 4071 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign 4072 // bits, just sext from i32. 4073 if (NumSignBits > OpBits-MidBits) 4074 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, Op); 4075 } else { 4076 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign 4077 // bits, just truncate to i32. 4078 if (NumSignBits > OpBits-MidBits) 4079 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op); 4080 } 4081 4082 // fold (sext (truncate x)) -> (sextinreg x). 4083 if (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, 4084 N0.getValueType())) { 4085 if (OpBits < DestBits) 4086 Op = DAG.getNode(ISD::ANY_EXTEND, N0.getDebugLoc(), VT, Op); 4087 else if (OpBits > DestBits) 4088 Op = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), VT, Op); 4089 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, Op, 4090 DAG.getValueType(N0.getValueType())); 4091 } 4092 } 4093 4094 // fold (sext (load x)) -> (sext (truncate (sextload x))) 4095 // None of the supported targets knows how to perform load and sign extend 4096 // on vectors in one instruction. We only perform this transformation on 4097 // scalars. 4098 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() && 4099 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 4100 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()))) { 4101 bool DoXform = true; 4102 SmallVector<SDNode*, 4> SetCCs; 4103 if (!N0.hasOneUse()) 4104 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::SIGN_EXTEND, SetCCs, TLI); 4105 if (DoXform) { 4106 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4107 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 4108 LN0->getChain(), 4109 LN0->getBasePtr(), LN0->getPointerInfo(), 4110 N0.getValueType(), 4111 LN0->isVolatile(), LN0->isNonTemporal(), 4112 LN0->getAlignment()); 4113 CombineTo(N, ExtLoad); 4114 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 4115 N0.getValueType(), ExtLoad); 4116 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 4117 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(), 4118 ISD::SIGN_EXTEND); 4119 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4120 } 4121 } 4122 4123 // fold (sext (sextload x)) -> (sext (truncate (sextload x))) 4124 // fold (sext ( extload x)) -> (sext (truncate (sextload x))) 4125 if ((ISD::isSEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) && 4126 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) { 4127 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4128 EVT MemVT = LN0->getMemoryVT(); 4129 if ((!LegalOperations && !LN0->isVolatile()) || 4130 TLI.isLoadExtLegal(ISD::SEXTLOAD, MemVT)) { 4131 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 4132 LN0->getChain(), 4133 LN0->getBasePtr(), LN0->getPointerInfo(), 4134 MemVT, 4135 LN0->isVolatile(), LN0->isNonTemporal(), 4136 LN0->getAlignment()); 4137 CombineTo(N, ExtLoad); 4138 CombineTo(N0.getNode(), 4139 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 4140 N0.getValueType(), ExtLoad), 4141 ExtLoad.getValue(1)); 4142 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4143 } 4144 } 4145 4146 // fold (sext (and/or/xor (load x), cst)) -> 4147 // (and/or/xor (sextload x), (sext cst)) 4148 if ((N0.getOpcode() == ISD::AND || N0.getOpcode() == ISD::OR || 4149 N0.getOpcode() == ISD::XOR) && 4150 isa<LoadSDNode>(N0.getOperand(0)) && 4151 N0.getOperand(1).getOpcode() == ISD::Constant && 4152 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()) && 4153 (!LegalOperations && TLI.isOperationLegal(N0.getOpcode(), VT))) { 4154 LoadSDNode *LN0 = cast<LoadSDNode>(N0.getOperand(0)); 4155 if (LN0->getExtensionType() != ISD::ZEXTLOAD) { 4156 bool DoXform = true; 4157 SmallVector<SDNode*, 4> SetCCs; 4158 if (!N0.hasOneUse()) 4159 DoXform = ExtendUsesToFormExtLoad(N, N0.getOperand(0), ISD::SIGN_EXTEND, 4160 SetCCs, TLI); 4161 if (DoXform) { 4162 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, LN0->getDebugLoc(), VT, 4163 LN0->getChain(), LN0->getBasePtr(), 4164 LN0->getPointerInfo(), 4165 LN0->getMemoryVT(), 4166 LN0->isVolatile(), 4167 LN0->isNonTemporal(), 4168 LN0->getAlignment()); 4169 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 4170 Mask = Mask.sext(VT.getSizeInBits()); 4171 SDValue And = DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, 4172 ExtLoad, DAG.getConstant(Mask, VT)); 4173 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, 4174 N0.getOperand(0).getDebugLoc(), 4175 N0.getOperand(0).getValueType(), ExtLoad); 4176 CombineTo(N, And); 4177 CombineTo(N0.getOperand(0).getNode(), Trunc, ExtLoad.getValue(1)); 4178 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(), 4179 ISD::SIGN_EXTEND); 4180 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4181 } 4182 } 4183 } 4184 4185 if (N0.getOpcode() == ISD::SETCC) { 4186 // sext(setcc) -> sext_in_reg(vsetcc) for vectors. 4187 // Only do this before legalize for now. 4188 if (VT.isVector() && !LegalOperations) { 4189 EVT N0VT = N0.getOperand(0).getValueType(); 4190 // We know that the # elements of the results is the same as the 4191 // # elements of the compare (and the # elements of the compare result 4192 // for that matter). Check to see that they are the same size. If so, 4193 // we know that the element size of the sext'd result matches the 4194 // element size of the compare operands. 4195 if (VT.getSizeInBits() == N0VT.getSizeInBits()) 4196 return DAG.getSetCC(N->getDebugLoc(), VT, N0.getOperand(0), 4197 N0.getOperand(1), 4198 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 4199 // If the desired elements are smaller or larger than the source 4200 // elements we can use a matching integer vector type and then 4201 // truncate/sign extend 4202 else { 4203 EVT MatchingElementType = 4204 EVT::getIntegerVT(*DAG.getContext(), 4205 N0VT.getScalarType().getSizeInBits()); 4206 EVT MatchingVectorType = 4207 EVT::getVectorVT(*DAG.getContext(), MatchingElementType, 4208 N0VT.getVectorNumElements()); 4209 SDValue VsetCC = 4210 DAG.getSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0), 4211 N0.getOperand(1), 4212 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 4213 return DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT); 4214 } 4215 } 4216 4217 // sext(setcc x, y, cc) -> (select_cc x, y, -1, 0, cc) 4218 unsigned ElementWidth = VT.getScalarType().getSizeInBits(); 4219 SDValue NegOne = 4220 DAG.getConstant(APInt::getAllOnesValue(ElementWidth), VT); 4221 SDValue SCC = 4222 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 4223 NegOne, DAG.getConstant(0, VT), 4224 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 4225 if (SCC.getNode()) return SCC; 4226 if (!LegalOperations || 4227 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(VT))) 4228 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT, 4229 DAG.getSetCC(N->getDebugLoc(), 4230 TLI.getSetCCResultType(VT), 4231 N0.getOperand(0), N0.getOperand(1), 4232 cast<CondCodeSDNode>(N0.getOperand(2))->get()), 4233 NegOne, DAG.getConstant(0, VT)); 4234 } 4235 4236 // fold (sext x) -> (zext x) if the sign bit is known zero. 4237 if ((!LegalOperations || TLI.isOperationLegal(ISD::ZERO_EXTEND, VT)) && 4238 DAG.SignBitIsZero(N0)) 4239 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0); 4240 4241 return SDValue(); 4242} 4243 4244SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) { 4245 SDValue N0 = N->getOperand(0); 4246 EVT VT = N->getValueType(0); 4247 4248 // fold (zext c1) -> c1 4249 if (isa<ConstantSDNode>(N0)) 4250 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0); 4251 // fold (zext (zext x)) -> (zext x) 4252 // fold (zext (aext x)) -> (zext x) 4253 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 4254 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, 4255 N0.getOperand(0)); 4256 4257 // fold (zext (truncate (load x))) -> (zext (smaller load x)) 4258 // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n))) 4259 if (N0.getOpcode() == ISD::TRUNCATE) { 4260 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 4261 if (NarrowLoad.getNode()) { 4262 SDNode* oye = N0.getNode()->getOperand(0).getNode(); 4263 if (NarrowLoad.getNode() != N0.getNode()) { 4264 CombineTo(N0.getNode(), NarrowLoad); 4265 // CombineTo deleted the truncate, if needed, but not what's under it. 4266 AddToWorkList(oye); 4267 } 4268 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4269 } 4270 } 4271 4272 // fold (zext (truncate x)) -> (and x, mask) 4273 if (N0.getOpcode() == ISD::TRUNCATE && 4274 (!LegalOperations || TLI.isOperationLegal(ISD::AND, VT))) { 4275 4276 // fold (zext (truncate (load x))) -> (zext (smaller load x)) 4277 // fold (zext (truncate (srl (load x), c))) -> (zext (smaller load (x+c/n))) 4278 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 4279 if (NarrowLoad.getNode()) { 4280 SDNode* oye = N0.getNode()->getOperand(0).getNode(); 4281 if (NarrowLoad.getNode() != N0.getNode()) { 4282 CombineTo(N0.getNode(), NarrowLoad); 4283 // CombineTo deleted the truncate, if needed, but not what's under it. 4284 AddToWorkList(oye); 4285 } 4286 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4287 } 4288 4289 SDValue Op = N0.getOperand(0); 4290 if (Op.getValueType().bitsLT(VT)) { 4291 Op = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, Op); 4292 } else if (Op.getValueType().bitsGT(VT)) { 4293 Op = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op); 4294 } 4295 return DAG.getZeroExtendInReg(Op, N->getDebugLoc(), 4296 N0.getValueType().getScalarType()); 4297 } 4298 4299 // Fold (zext (and (trunc x), cst)) -> (and x, cst), 4300 // if either of the casts is not free. 4301 if (N0.getOpcode() == ISD::AND && 4302 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 4303 N0.getOperand(1).getOpcode() == ISD::Constant && 4304 (!TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(), 4305 N0.getValueType()) || 4306 !TLI.isZExtFree(N0.getValueType(), VT))) { 4307 SDValue X = N0.getOperand(0).getOperand(0); 4308 if (X.getValueType().bitsLT(VT)) { 4309 X = DAG.getNode(ISD::ANY_EXTEND, X.getDebugLoc(), VT, X); 4310 } else if (X.getValueType().bitsGT(VT)) { 4311 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X); 4312 } 4313 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 4314 Mask = Mask.zext(VT.getSizeInBits()); 4315 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 4316 X, DAG.getConstant(Mask, VT)); 4317 } 4318 4319 // fold (zext (load x)) -> (zext (truncate (zextload x))) 4320 // None of the supported targets knows how to perform load and vector_zext 4321 // on vectors in one instruction. We only perform this transformation on 4322 // scalars. 4323 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() && 4324 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 4325 TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()))) { 4326 bool DoXform = true; 4327 SmallVector<SDNode*, 4> SetCCs; 4328 if (!N0.hasOneUse()) 4329 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ZERO_EXTEND, SetCCs, TLI); 4330 if (DoXform) { 4331 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4332 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT, 4333 LN0->getChain(), 4334 LN0->getBasePtr(), LN0->getPointerInfo(), 4335 N0.getValueType(), 4336 LN0->isVolatile(), LN0->isNonTemporal(), 4337 LN0->getAlignment()); 4338 CombineTo(N, ExtLoad); 4339 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 4340 N0.getValueType(), ExtLoad); 4341 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 4342 4343 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(), 4344 ISD::ZERO_EXTEND); 4345 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4346 } 4347 } 4348 4349 // fold (zext (and/or/xor (load x), cst)) -> 4350 // (and/or/xor (zextload x), (zext cst)) 4351 if ((N0.getOpcode() == ISD::AND || N0.getOpcode() == ISD::OR || 4352 N0.getOpcode() == ISD::XOR) && 4353 isa<LoadSDNode>(N0.getOperand(0)) && 4354 N0.getOperand(1).getOpcode() == ISD::Constant && 4355 TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()) && 4356 (!LegalOperations && TLI.isOperationLegal(N0.getOpcode(), VT))) { 4357 LoadSDNode *LN0 = cast<LoadSDNode>(N0.getOperand(0)); 4358 if (LN0->getExtensionType() != ISD::SEXTLOAD) { 4359 bool DoXform = true; 4360 SmallVector<SDNode*, 4> SetCCs; 4361 if (!N0.hasOneUse()) 4362 DoXform = ExtendUsesToFormExtLoad(N, N0.getOperand(0), ISD::ZERO_EXTEND, 4363 SetCCs, TLI); 4364 if (DoXform) { 4365 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), VT, 4366 LN0->getChain(), LN0->getBasePtr(), 4367 LN0->getPointerInfo(), 4368 LN0->getMemoryVT(), 4369 LN0->isVolatile(), 4370 LN0->isNonTemporal(), 4371 LN0->getAlignment()); 4372 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 4373 Mask = Mask.zext(VT.getSizeInBits()); 4374 SDValue And = DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, 4375 ExtLoad, DAG.getConstant(Mask, VT)); 4376 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, 4377 N0.getOperand(0).getDebugLoc(), 4378 N0.getOperand(0).getValueType(), ExtLoad); 4379 CombineTo(N, And); 4380 CombineTo(N0.getOperand(0).getNode(), Trunc, ExtLoad.getValue(1)); 4381 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(), 4382 ISD::ZERO_EXTEND); 4383 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4384 } 4385 } 4386 } 4387 4388 // fold (zext (zextload x)) -> (zext (truncate (zextload x))) 4389 // fold (zext ( extload x)) -> (zext (truncate (zextload x))) 4390 if ((ISD::isZEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) && 4391 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) { 4392 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4393 EVT MemVT = LN0->getMemoryVT(); 4394 if ((!LegalOperations && !LN0->isVolatile()) || 4395 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT)) { 4396 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT, 4397 LN0->getChain(), 4398 LN0->getBasePtr(), LN0->getPointerInfo(), 4399 MemVT, 4400 LN0->isVolatile(), LN0->isNonTemporal(), 4401 LN0->getAlignment()); 4402 CombineTo(N, ExtLoad); 4403 CombineTo(N0.getNode(), 4404 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), N0.getValueType(), 4405 ExtLoad), 4406 ExtLoad.getValue(1)); 4407 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4408 } 4409 } 4410 4411 if (N0.getOpcode() == ISD::SETCC) { 4412 if (!LegalOperations && VT.isVector()) { 4413 // zext(setcc) -> (and (vsetcc), (1, 1, ...) for vectors. 4414 // Only do this before legalize for now. 4415 EVT N0VT = N0.getOperand(0).getValueType(); 4416 EVT EltVT = VT.getVectorElementType(); 4417 SmallVector<SDValue,8> OneOps(VT.getVectorNumElements(), 4418 DAG.getConstant(1, EltVT)); 4419 if (VT.getSizeInBits() == N0VT.getSizeInBits()) 4420 // We know that the # elements of the results is the same as the 4421 // # elements of the compare (and the # elements of the compare result 4422 // for that matter). Check to see that they are the same size. If so, 4423 // we know that the element size of the sext'd result matches the 4424 // element size of the compare operands. 4425 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 4426 DAG.getSetCC(N->getDebugLoc(), VT, N0.getOperand(0), 4427 N0.getOperand(1), 4428 cast<CondCodeSDNode>(N0.getOperand(2))->get()), 4429 DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT, 4430 &OneOps[0], OneOps.size())); 4431 4432 // If the desired elements are smaller or larger than the source 4433 // elements we can use a matching integer vector type and then 4434 // truncate/sign extend 4435 EVT MatchingElementType = 4436 EVT::getIntegerVT(*DAG.getContext(), 4437 N0VT.getScalarType().getSizeInBits()); 4438 EVT MatchingVectorType = 4439 EVT::getVectorVT(*DAG.getContext(), MatchingElementType, 4440 N0VT.getVectorNumElements()); 4441 SDValue VsetCC = 4442 DAG.getSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0), 4443 N0.getOperand(1), 4444 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 4445 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 4446 DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT), 4447 DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT, 4448 &OneOps[0], OneOps.size())); 4449 } 4450 4451 // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 4452 SDValue SCC = 4453 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 4454 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 4455 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 4456 if (SCC.getNode()) return SCC; 4457 } 4458 4459 // (zext (shl (zext x), cst)) -> (shl (zext x), cst) 4460 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL) && 4461 isa<ConstantSDNode>(N0.getOperand(1)) && 4462 N0.getOperand(0).getOpcode() == ISD::ZERO_EXTEND && 4463 N0.hasOneUse()) { 4464 SDValue ShAmt = N0.getOperand(1); 4465 unsigned ShAmtVal = cast<ConstantSDNode>(ShAmt)->getZExtValue(); 4466 if (N0.getOpcode() == ISD::SHL) { 4467 SDValue InnerZExt = N0.getOperand(0); 4468 // If the original shl may be shifting out bits, do not perform this 4469 // transformation. 4470 unsigned KnownZeroBits = InnerZExt.getValueType().getSizeInBits() - 4471 InnerZExt.getOperand(0).getValueType().getSizeInBits(); 4472 if (ShAmtVal > KnownZeroBits) 4473 return SDValue(); 4474 } 4475 4476 DebugLoc DL = N->getDebugLoc(); 4477 4478 // Ensure that the shift amount is wide enough for the shifted value. 4479 if (VT.getSizeInBits() >= 256) 4480 ShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, ShAmt); 4481 4482 return DAG.getNode(N0.getOpcode(), DL, VT, 4483 DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0)), 4484 ShAmt); 4485 } 4486 4487 return SDValue(); 4488} 4489 4490SDValue DAGCombiner::visitANY_EXTEND(SDNode *N) { 4491 SDValue N0 = N->getOperand(0); 4492 EVT VT = N->getValueType(0); 4493 4494 // fold (aext c1) -> c1 4495 if (isa<ConstantSDNode>(N0)) 4496 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, N0); 4497 // fold (aext (aext x)) -> (aext x) 4498 // fold (aext (zext x)) -> (zext x) 4499 // fold (aext (sext x)) -> (sext x) 4500 if (N0.getOpcode() == ISD::ANY_EXTEND || 4501 N0.getOpcode() == ISD::ZERO_EXTEND || 4502 N0.getOpcode() == ISD::SIGN_EXTEND) 4503 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, N0.getOperand(0)); 4504 4505 // fold (aext (truncate (load x))) -> (aext (smaller load x)) 4506 // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n))) 4507 if (N0.getOpcode() == ISD::TRUNCATE) { 4508 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 4509 if (NarrowLoad.getNode()) { 4510 SDNode* oye = N0.getNode()->getOperand(0).getNode(); 4511 if (NarrowLoad.getNode() != N0.getNode()) { 4512 CombineTo(N0.getNode(), NarrowLoad); 4513 // CombineTo deleted the truncate, if needed, but not what's under it. 4514 AddToWorkList(oye); 4515 } 4516 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4517 } 4518 } 4519 4520 // fold (aext (truncate x)) 4521 if (N0.getOpcode() == ISD::TRUNCATE) { 4522 SDValue TruncOp = N0.getOperand(0); 4523 if (TruncOp.getValueType() == VT) 4524 return TruncOp; // x iff x size == zext size. 4525 if (TruncOp.getValueType().bitsGT(VT)) 4526 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, TruncOp); 4527 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, TruncOp); 4528 } 4529 4530 // Fold (aext (and (trunc x), cst)) -> (and x, cst) 4531 // if the trunc is not free. 4532 if (N0.getOpcode() == ISD::AND && 4533 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 4534 N0.getOperand(1).getOpcode() == ISD::Constant && 4535 !TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(), 4536 N0.getValueType())) { 4537 SDValue X = N0.getOperand(0).getOperand(0); 4538 if (X.getValueType().bitsLT(VT)) { 4539 X = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, X); 4540 } else if (X.getValueType().bitsGT(VT)) { 4541 X = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, X); 4542 } 4543 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 4544 Mask = Mask.zext(VT.getSizeInBits()); 4545 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 4546 X, DAG.getConstant(Mask, VT)); 4547 } 4548 4549 // fold (aext (load x)) -> (aext (truncate (extload x))) 4550 // None of the supported targets knows how to perform load and any_ext 4551 // on vectors in one instruction. We only perform this transformation on 4552 // scalars. 4553 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() && 4554 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 4555 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) { 4556 bool DoXform = true; 4557 SmallVector<SDNode*, 4> SetCCs; 4558 if (!N0.hasOneUse()) 4559 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ANY_EXTEND, SetCCs, TLI); 4560 if (DoXform) { 4561 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4562 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT, 4563 LN0->getChain(), 4564 LN0->getBasePtr(), LN0->getPointerInfo(), 4565 N0.getValueType(), 4566 LN0->isVolatile(), LN0->isNonTemporal(), 4567 LN0->getAlignment()); 4568 CombineTo(N, ExtLoad); 4569 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 4570 N0.getValueType(), ExtLoad); 4571 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 4572 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(), 4573 ISD::ANY_EXTEND); 4574 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4575 } 4576 } 4577 4578 // fold (aext (zextload x)) -> (aext (truncate (zextload x))) 4579 // fold (aext (sextload x)) -> (aext (truncate (sextload x))) 4580 // fold (aext ( extload x)) -> (aext (truncate (extload x))) 4581 if (N0.getOpcode() == ISD::LOAD && 4582 !ISD::isNON_EXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 4583 N0.hasOneUse()) { 4584 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4585 EVT MemVT = LN0->getMemoryVT(); 4586 SDValue ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), N->getDebugLoc(), 4587 VT, LN0->getChain(), LN0->getBasePtr(), 4588 LN0->getPointerInfo(), MemVT, 4589 LN0->isVolatile(), LN0->isNonTemporal(), 4590 LN0->getAlignment()); 4591 CombineTo(N, ExtLoad); 4592 CombineTo(N0.getNode(), 4593 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 4594 N0.getValueType(), ExtLoad), 4595 ExtLoad.getValue(1)); 4596 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4597 } 4598 4599 if (N0.getOpcode() == ISD::SETCC) { 4600 // aext(setcc) -> sext_in_reg(vsetcc) for vectors. 4601 // Only do this before legalize for now. 4602 if (VT.isVector() && !LegalOperations) { 4603 EVT N0VT = N0.getOperand(0).getValueType(); 4604 // We know that the # elements of the results is the same as the 4605 // # elements of the compare (and the # elements of the compare result 4606 // for that matter). Check to see that they are the same size. If so, 4607 // we know that the element size of the sext'd result matches the 4608 // element size of the compare operands. 4609 if (VT.getSizeInBits() == N0VT.getSizeInBits()) 4610 return DAG.getSetCC(N->getDebugLoc(), VT, N0.getOperand(0), 4611 N0.getOperand(1), 4612 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 4613 // If the desired elements are smaller or larger than the source 4614 // elements we can use a matching integer vector type and then 4615 // truncate/sign extend 4616 else { 4617 EVT MatchingElementType = 4618 EVT::getIntegerVT(*DAG.getContext(), 4619 N0VT.getScalarType().getSizeInBits()); 4620 EVT MatchingVectorType = 4621 EVT::getVectorVT(*DAG.getContext(), MatchingElementType, 4622 N0VT.getVectorNumElements()); 4623 SDValue VsetCC = 4624 DAG.getSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0), 4625 N0.getOperand(1), 4626 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 4627 return DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT); 4628 } 4629 } 4630 4631 // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 4632 SDValue SCC = 4633 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 4634 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 4635 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 4636 if (SCC.getNode()) 4637 return SCC; 4638 } 4639 4640 return SDValue(); 4641} 4642 4643/// GetDemandedBits - See if the specified operand can be simplified with the 4644/// knowledge that only the bits specified by Mask are used. If so, return the 4645/// simpler operand, otherwise return a null SDValue. 4646SDValue DAGCombiner::GetDemandedBits(SDValue V, const APInt &Mask) { 4647 switch (V.getOpcode()) { 4648 default: break; 4649 case ISD::Constant: { 4650 const ConstantSDNode *CV = cast<ConstantSDNode>(V.getNode()); 4651 assert(CV != 0 && "Const value should be ConstSDNode."); 4652 const APInt &CVal = CV->getAPIntValue(); 4653 APInt NewVal = CVal & Mask; 4654 if (NewVal != CVal) { 4655 return DAG.getConstant(NewVal, V.getValueType()); 4656 } 4657 break; 4658 } 4659 case ISD::OR: 4660 case ISD::XOR: 4661 // If the LHS or RHS don't contribute bits to the or, drop them. 4662 if (DAG.MaskedValueIsZero(V.getOperand(0), Mask)) 4663 return V.getOperand(1); 4664 if (DAG.MaskedValueIsZero(V.getOperand(1), Mask)) 4665 return V.getOperand(0); 4666 break; 4667 case ISD::SRL: 4668 // Only look at single-use SRLs. 4669 if (!V.getNode()->hasOneUse()) 4670 break; 4671 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(V.getOperand(1))) { 4672 // See if we can recursively simplify the LHS. 4673 unsigned Amt = RHSC->getZExtValue(); 4674 4675 // Watch out for shift count overflow though. 4676 if (Amt >= Mask.getBitWidth()) break; 4677 APInt NewMask = Mask << Amt; 4678 SDValue SimplifyLHS = GetDemandedBits(V.getOperand(0), NewMask); 4679 if (SimplifyLHS.getNode()) 4680 return DAG.getNode(ISD::SRL, V.getDebugLoc(), V.getValueType(), 4681 SimplifyLHS, V.getOperand(1)); 4682 } 4683 } 4684 return SDValue(); 4685} 4686 4687/// ReduceLoadWidth - If the result of a wider load is shifted to right of N 4688/// bits and then truncated to a narrower type and where N is a multiple 4689/// of number of bits of the narrower type, transform it to a narrower load 4690/// from address + N / num of bits of new type. If the result is to be 4691/// extended, also fold the extension to form a extending load. 4692SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) { 4693 unsigned Opc = N->getOpcode(); 4694 4695 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD; 4696 SDValue N0 = N->getOperand(0); 4697 EVT VT = N->getValueType(0); 4698 EVT ExtVT = VT; 4699 4700 // This transformation isn't valid for vector loads. 4701 if (VT.isVector()) 4702 return SDValue(); 4703 4704 // Special case: SIGN_EXTEND_INREG is basically truncating to ExtVT then 4705 // extended to VT. 4706 if (Opc == ISD::SIGN_EXTEND_INREG) { 4707 ExtType = ISD::SEXTLOAD; 4708 ExtVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 4709 } else if (Opc == ISD::SRL) { 4710 // Another special-case: SRL is basically zero-extending a narrower value. 4711 ExtType = ISD::ZEXTLOAD; 4712 N0 = SDValue(N, 0); 4713 ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 4714 if (!N01) return SDValue(); 4715 ExtVT = EVT::getIntegerVT(*DAG.getContext(), 4716 VT.getSizeInBits() - N01->getZExtValue()); 4717 } 4718 if (LegalOperations && !TLI.isLoadExtLegal(ExtType, ExtVT)) 4719 return SDValue(); 4720 4721 unsigned EVTBits = ExtVT.getSizeInBits(); 4722 4723 // Do not generate loads of non-round integer types since these can 4724 // be expensive (and would be wrong if the type is not byte sized). 4725 if (!ExtVT.isRound()) 4726 return SDValue(); 4727 4728 unsigned ShAmt = 0; 4729 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) { 4730 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 4731 ShAmt = N01->getZExtValue(); 4732 // Is the shift amount a multiple of size of VT? 4733 if ((ShAmt & (EVTBits-1)) == 0) { 4734 N0 = N0.getOperand(0); 4735 // Is the load width a multiple of size of VT? 4736 if ((N0.getValueType().getSizeInBits() & (EVTBits-1)) != 0) 4737 return SDValue(); 4738 } 4739 4740 // At this point, we must have a load or else we can't do the transform. 4741 if (!isa<LoadSDNode>(N0)) return SDValue(); 4742 4743 // If the shift amount is larger than the input type then we're not 4744 // accessing any of the loaded bytes. If the load was a zextload/extload 4745 // then the result of the shift+trunc is zero/undef (handled elsewhere). 4746 // If the load was a sextload then the result is a splat of the sign bit 4747 // of the extended byte. This is not worth optimizing for. 4748 if (ShAmt >= cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits()) 4749 return SDValue(); 4750 } 4751 } 4752 4753 // If the load is shifted left (and the result isn't shifted back right), 4754 // we can fold the truncate through the shift. 4755 unsigned ShLeftAmt = 0; 4756 if (ShAmt == 0 && N0.getOpcode() == ISD::SHL && N0.hasOneUse() && 4757 ExtVT == VT && TLI.isNarrowingProfitable(N0.getValueType(), VT)) { 4758 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 4759 ShLeftAmt = N01->getZExtValue(); 4760 N0 = N0.getOperand(0); 4761 } 4762 } 4763 4764 // If we haven't found a load, we can't narrow it. Don't transform one with 4765 // multiple uses, this would require adding a new load. 4766 if (!isa<LoadSDNode>(N0) || !N0.hasOneUse() || 4767 // Don't change the width of a volatile load. 4768 cast<LoadSDNode>(N0)->isVolatile()) 4769 return SDValue(); 4770 4771 // Verify that we are actually reducing a load width here. 4772 if (cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits() < EVTBits) 4773 return SDValue(); 4774 4775 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4776 EVT PtrType = N0.getOperand(1).getValueType(); 4777 4778 // For big endian targets, we need to adjust the offset to the pointer to 4779 // load the correct bytes. 4780 if (TLI.isBigEndian()) { 4781 unsigned LVTStoreBits = LN0->getMemoryVT().getStoreSizeInBits(); 4782 unsigned EVTStoreBits = ExtVT.getStoreSizeInBits(); 4783 ShAmt = LVTStoreBits - EVTStoreBits - ShAmt; 4784 } 4785 4786 uint64_t PtrOff = ShAmt / 8; 4787 unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff); 4788 SDValue NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(), 4789 PtrType, LN0->getBasePtr(), 4790 DAG.getConstant(PtrOff, PtrType)); 4791 AddToWorkList(NewPtr.getNode()); 4792 4793 SDValue Load; 4794 if (ExtType == ISD::NON_EXTLOAD) 4795 Load = DAG.getLoad(VT, N0.getDebugLoc(), LN0->getChain(), NewPtr, 4796 LN0->getPointerInfo().getWithOffset(PtrOff), 4797 LN0->isVolatile(), LN0->isNonTemporal(), 4798 LN0->isInvariant(), NewAlign); 4799 else 4800 Load = DAG.getExtLoad(ExtType, N0.getDebugLoc(), VT, LN0->getChain(),NewPtr, 4801 LN0->getPointerInfo().getWithOffset(PtrOff), 4802 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(), 4803 NewAlign); 4804 4805 // Replace the old load's chain with the new load's chain. 4806 WorkListRemover DeadNodes(*this); 4807 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1), 4808 &DeadNodes); 4809 4810 // Shift the result left, if we've swallowed a left shift. 4811 SDValue Result = Load; 4812 if (ShLeftAmt != 0) { 4813 EVT ShImmTy = getShiftAmountTy(Result.getValueType()); 4814 if (!isUIntN(ShImmTy.getSizeInBits(), ShLeftAmt)) 4815 ShImmTy = VT; 4816 Result = DAG.getNode(ISD::SHL, N0.getDebugLoc(), VT, 4817 Result, DAG.getConstant(ShLeftAmt, ShImmTy)); 4818 } 4819 4820 // Return the new loaded value. 4821 return Result; 4822} 4823 4824SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) { 4825 SDValue N0 = N->getOperand(0); 4826 SDValue N1 = N->getOperand(1); 4827 EVT VT = N->getValueType(0); 4828 EVT EVT = cast<VTSDNode>(N1)->getVT(); 4829 unsigned VTBits = VT.getScalarType().getSizeInBits(); 4830 unsigned EVTBits = EVT.getScalarType().getSizeInBits(); 4831 4832 // fold (sext_in_reg c1) -> c1 4833 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF) 4834 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, N0, N1); 4835 4836 // If the input is already sign extended, just drop the extension. 4837 if (DAG.ComputeNumSignBits(N0) >= VTBits-EVTBits+1) 4838 return N0; 4839 4840 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2 4841 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 4842 EVT.bitsLT(cast<VTSDNode>(N0.getOperand(1))->getVT())) { 4843 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, 4844 N0.getOperand(0), N1); 4845 } 4846 4847 // fold (sext_in_reg (sext x)) -> (sext x) 4848 // fold (sext_in_reg (aext x)) -> (sext x) 4849 // if x is small enough. 4850 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) { 4851 SDValue N00 = N0.getOperand(0); 4852 if (N00.getValueType().getScalarType().getSizeInBits() <= EVTBits && 4853 (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND, VT))) 4854 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N00, N1); 4855 } 4856 4857 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero. 4858 if (DAG.MaskedValueIsZero(N0, APInt::getBitsSet(VTBits, EVTBits-1, EVTBits))) 4859 return DAG.getZeroExtendInReg(N0, N->getDebugLoc(), EVT); 4860 4861 // fold operands of sext_in_reg based on knowledge that the top bits are not 4862 // demanded. 4863 if (SimplifyDemandedBits(SDValue(N, 0))) 4864 return SDValue(N, 0); 4865 4866 // fold (sext_in_reg (load x)) -> (smaller sextload x) 4867 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits)) 4868 SDValue NarrowLoad = ReduceLoadWidth(N); 4869 if (NarrowLoad.getNode()) 4870 return NarrowLoad; 4871 4872 // fold (sext_in_reg (srl X, 24), i8) -> (sra X, 24) 4873 // fold (sext_in_reg (srl X, 23), i8) -> (sra X, 23) iff possible. 4874 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above. 4875 if (N0.getOpcode() == ISD::SRL) { 4876 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 4877 if (ShAmt->getZExtValue()+EVTBits <= VTBits) { 4878 // We can turn this into an SRA iff the input to the SRL is already sign 4879 // extended enough. 4880 unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0)); 4881 if (VTBits-(ShAmt->getZExtValue()+EVTBits) < InSignBits) 4882 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, 4883 N0.getOperand(0), N0.getOperand(1)); 4884 } 4885 } 4886 4887 // fold (sext_inreg (extload x)) -> (sextload x) 4888 if (ISD::isEXTLoad(N0.getNode()) && 4889 ISD::isUNINDEXEDLoad(N0.getNode()) && 4890 EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 4891 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 4892 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) { 4893 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4894 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 4895 LN0->getChain(), 4896 LN0->getBasePtr(), LN0->getPointerInfo(), 4897 EVT, 4898 LN0->isVolatile(), LN0->isNonTemporal(), 4899 LN0->getAlignment()); 4900 CombineTo(N, ExtLoad); 4901 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 4902 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4903 } 4904 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use 4905 if (ISD::isZEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 4906 N0.hasOneUse() && 4907 EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 4908 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 4909 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) { 4910 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4911 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 4912 LN0->getChain(), 4913 LN0->getBasePtr(), LN0->getPointerInfo(), 4914 EVT, 4915 LN0->isVolatile(), LN0->isNonTemporal(), 4916 LN0->getAlignment()); 4917 CombineTo(N, ExtLoad); 4918 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 4919 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4920 } 4921 4922 // Form (sext_inreg (bswap >> 16)) or (sext_inreg (rotl (bswap) 16)) 4923 if (EVTBits <= 16 && N0.getOpcode() == ISD::OR) { 4924 SDValue BSwap = MatchBSwapHWordLow(N0.getNode(), N0.getOperand(0), 4925 N0.getOperand(1), false); 4926 if (BSwap.getNode() != 0) 4927 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, 4928 BSwap, N1); 4929 } 4930 4931 return SDValue(); 4932} 4933 4934SDValue DAGCombiner::visitTRUNCATE(SDNode *N) { 4935 SDValue N0 = N->getOperand(0); 4936 EVT VT = N->getValueType(0); 4937 4938 // noop truncate 4939 if (N0.getValueType() == N->getValueType(0)) 4940 return N0; 4941 // fold (truncate c1) -> c1 4942 if (isa<ConstantSDNode>(N0)) 4943 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0); 4944 // fold (truncate (truncate x)) -> (truncate x) 4945 if (N0.getOpcode() == ISD::TRUNCATE) 4946 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0)); 4947 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x 4948 if (N0.getOpcode() == ISD::ZERO_EXTEND || 4949 N0.getOpcode() == ISD::SIGN_EXTEND || 4950 N0.getOpcode() == ISD::ANY_EXTEND) { 4951 if (N0.getOperand(0).getValueType().bitsLT(VT)) 4952 // if the source is smaller than the dest, we still need an extend 4953 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, 4954 N0.getOperand(0)); 4955 else if (N0.getOperand(0).getValueType().bitsGT(VT)) 4956 // if the source is larger than the dest, than we just need the truncate 4957 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0)); 4958 else 4959 // if the source and dest are the same type, we can drop both the extend 4960 // and the truncate. 4961 return N0.getOperand(0); 4962 } 4963 4964 // See if we can simplify the input to this truncate through knowledge that 4965 // only the low bits are being used. 4966 // For example "trunc (or (shl x, 8), y)" // -> trunc y 4967 // Currently we only perform this optimization on scalars because vectors 4968 // may have different active low bits. 4969 if (!VT.isVector()) { 4970 SDValue Shorter = 4971 GetDemandedBits(N0, APInt::getLowBitsSet(N0.getValueSizeInBits(), 4972 VT.getSizeInBits())); 4973 if (Shorter.getNode()) 4974 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Shorter); 4975 } 4976 // fold (truncate (load x)) -> (smaller load x) 4977 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits)) 4978 if (!LegalTypes || TLI.isTypeDesirableForOp(N0.getOpcode(), VT)) { 4979 SDValue Reduced = ReduceLoadWidth(N); 4980 if (Reduced.getNode()) 4981 return Reduced; 4982 } 4983 4984 // Simplify the operands using demanded-bits information. 4985 if (!VT.isVector() && 4986 SimplifyDemandedBits(SDValue(N, 0))) 4987 return SDValue(N, 0); 4988 4989 return SDValue(); 4990} 4991 4992static SDNode *getBuildPairElt(SDNode *N, unsigned i) { 4993 SDValue Elt = N->getOperand(i); 4994 if (Elt.getOpcode() != ISD::MERGE_VALUES) 4995 return Elt.getNode(); 4996 return Elt.getOperand(Elt.getResNo()).getNode(); 4997} 4998 4999/// CombineConsecutiveLoads - build_pair (load, load) -> load 5000/// if load locations are consecutive. 5001SDValue DAGCombiner::CombineConsecutiveLoads(SDNode *N, EVT VT) { 5002 assert(N->getOpcode() == ISD::BUILD_PAIR); 5003 5004 LoadSDNode *LD1 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 0)); 5005 LoadSDNode *LD2 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 1)); 5006 if (!LD1 || !LD2 || !ISD::isNON_EXTLoad(LD1) || !LD1->hasOneUse() || 5007 LD1->getPointerInfo().getAddrSpace() != 5008 LD2->getPointerInfo().getAddrSpace()) 5009 return SDValue(); 5010 EVT LD1VT = LD1->getValueType(0); 5011 5012 if (ISD::isNON_EXTLoad(LD2) && 5013 LD2->hasOneUse() && 5014 // If both are volatile this would reduce the number of volatile loads. 5015 // If one is volatile it might be ok, but play conservative and bail out. 5016 !LD1->isVolatile() && 5017 !LD2->isVolatile() && 5018 DAG.isConsecutiveLoad(LD2, LD1, LD1VT.getSizeInBits()/8, 1)) { 5019 unsigned Align = LD1->getAlignment(); 5020 unsigned NewAlign = TLI.getTargetData()-> 5021 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext())); 5022 5023 if (NewAlign <= Align && 5024 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) 5025 return DAG.getLoad(VT, N->getDebugLoc(), LD1->getChain(), 5026 LD1->getBasePtr(), LD1->getPointerInfo(), 5027 false, false, false, Align); 5028 } 5029 5030 return SDValue(); 5031} 5032 5033SDValue DAGCombiner::visitBITCAST(SDNode *N) { 5034 SDValue N0 = N->getOperand(0); 5035 EVT VT = N->getValueType(0); 5036 5037 // If the input is a BUILD_VECTOR with all constant elements, fold this now. 5038 // Only do this before legalize, since afterward the target may be depending 5039 // on the bitconvert. 5040 // First check to see if this is all constant. 5041 if (!LegalTypes && 5042 N0.getOpcode() == ISD::BUILD_VECTOR && N0.getNode()->hasOneUse() && 5043 VT.isVector()) { 5044 bool isSimple = true; 5045 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i) 5046 if (N0.getOperand(i).getOpcode() != ISD::UNDEF && 5047 N0.getOperand(i).getOpcode() != ISD::Constant && 5048 N0.getOperand(i).getOpcode() != ISD::ConstantFP) { 5049 isSimple = false; 5050 break; 5051 } 5052 5053 EVT DestEltVT = N->getValueType(0).getVectorElementType(); 5054 assert(!DestEltVT.isVector() && 5055 "Element type of vector ValueType must not be vector!"); 5056 if (isSimple) 5057 return ConstantFoldBITCASTofBUILD_VECTOR(N0.getNode(), DestEltVT); 5058 } 5059 5060 // If the input is a constant, let getNode fold it. 5061 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) { 5062 SDValue Res = DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, N0); 5063 if (Res.getNode() != N) { 5064 if (!LegalOperations || 5065 TLI.isOperationLegal(Res.getNode()->getOpcode(), VT)) 5066 return Res; 5067 5068 // Folding it resulted in an illegal node, and it's too late to 5069 // do that. Clean up the old node and forego the transformation. 5070 // Ideally this won't happen very often, because instcombine 5071 // and the earlier dagcombine runs (where illegal nodes are 5072 // permitted) should have folded most of them already. 5073 DAG.DeleteNode(Res.getNode()); 5074 } 5075 } 5076 5077 // (conv (conv x, t1), t2) -> (conv x, t2) 5078 if (N0.getOpcode() == ISD::BITCAST) 5079 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, 5080 N0.getOperand(0)); 5081 5082 // fold (conv (load x)) -> (load (conv*)x) 5083 // If the resultant load doesn't need a higher alignment than the original! 5084 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() && 5085 // Do not change the width of a volatile load. 5086 !cast<LoadSDNode>(N0)->isVolatile() && 5087 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) { 5088 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 5089 unsigned Align = TLI.getTargetData()-> 5090 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext())); 5091 unsigned OrigAlign = LN0->getAlignment(); 5092 5093 if (Align <= OrigAlign) { 5094 SDValue Load = DAG.getLoad(VT, N->getDebugLoc(), LN0->getChain(), 5095 LN0->getBasePtr(), LN0->getPointerInfo(), 5096 LN0->isVolatile(), LN0->isNonTemporal(), 5097 LN0->isInvariant(), OrigAlign); 5098 AddToWorkList(N); 5099 CombineTo(N0.getNode(), 5100 DAG.getNode(ISD::BITCAST, N0.getDebugLoc(), 5101 N0.getValueType(), Load), 5102 Load.getValue(1)); 5103 return Load; 5104 } 5105 } 5106 5107 // fold (bitconvert (fneg x)) -> (xor (bitconvert x), signbit) 5108 // fold (bitconvert (fabs x)) -> (and (bitconvert x), (not signbit)) 5109 // This often reduces constant pool loads. 5110 if ((N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FABS) && 5111 N0.getNode()->hasOneUse() && VT.isInteger() && !VT.isVector()) { 5112 SDValue NewConv = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(), VT, 5113 N0.getOperand(0)); 5114 AddToWorkList(NewConv.getNode()); 5115 5116 APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); 5117 if (N0.getOpcode() == ISD::FNEG) 5118 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, 5119 NewConv, DAG.getConstant(SignBit, VT)); 5120 assert(N0.getOpcode() == ISD::FABS); 5121 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 5122 NewConv, DAG.getConstant(~SignBit, VT)); 5123 } 5124 5125 // fold (bitconvert (fcopysign cst, x)) -> 5126 // (or (and (bitconvert x), sign), (and cst, (not sign))) 5127 // Note that we don't handle (copysign x, cst) because this can always be 5128 // folded to an fneg or fabs. 5129 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse() && 5130 isa<ConstantFPSDNode>(N0.getOperand(0)) && 5131 VT.isInteger() && !VT.isVector()) { 5132 unsigned OrigXWidth = N0.getOperand(1).getValueType().getSizeInBits(); 5133 EVT IntXVT = EVT::getIntegerVT(*DAG.getContext(), OrigXWidth); 5134 if (isTypeLegal(IntXVT)) { 5135 SDValue X = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(), 5136 IntXVT, N0.getOperand(1)); 5137 AddToWorkList(X.getNode()); 5138 5139 // If X has a different width than the result/lhs, sext it or truncate it. 5140 unsigned VTWidth = VT.getSizeInBits(); 5141 if (OrigXWidth < VTWidth) { 5142 X = DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, X); 5143 AddToWorkList(X.getNode()); 5144 } else if (OrigXWidth > VTWidth) { 5145 // To get the sign bit in the right place, we have to shift it right 5146 // before truncating. 5147 X = DAG.getNode(ISD::SRL, X.getDebugLoc(), 5148 X.getValueType(), X, 5149 DAG.getConstant(OrigXWidth-VTWidth, X.getValueType())); 5150 AddToWorkList(X.getNode()); 5151 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X); 5152 AddToWorkList(X.getNode()); 5153 } 5154 5155 APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); 5156 X = DAG.getNode(ISD::AND, X.getDebugLoc(), VT, 5157 X, DAG.getConstant(SignBit, VT)); 5158 AddToWorkList(X.getNode()); 5159 5160 SDValue Cst = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(), 5161 VT, N0.getOperand(0)); 5162 Cst = DAG.getNode(ISD::AND, Cst.getDebugLoc(), VT, 5163 Cst, DAG.getConstant(~SignBit, VT)); 5164 AddToWorkList(Cst.getNode()); 5165 5166 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, X, Cst); 5167 } 5168 } 5169 5170 // bitconvert(build_pair(ld, ld)) -> ld iff load locations are consecutive. 5171 if (N0.getOpcode() == ISD::BUILD_PAIR) { 5172 SDValue CombineLD = CombineConsecutiveLoads(N0.getNode(), VT); 5173 if (CombineLD.getNode()) 5174 return CombineLD; 5175 } 5176 5177 return SDValue(); 5178} 5179 5180SDValue DAGCombiner::visitBUILD_PAIR(SDNode *N) { 5181 EVT VT = N->getValueType(0); 5182 return CombineConsecutiveLoads(N, VT); 5183} 5184 5185/// ConstantFoldBITCASTofBUILD_VECTOR - We know that BV is a build_vector 5186/// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the 5187/// destination element value type. 5188SDValue DAGCombiner:: 5189ConstantFoldBITCASTofBUILD_VECTOR(SDNode *BV, EVT DstEltVT) { 5190 EVT SrcEltVT = BV->getValueType(0).getVectorElementType(); 5191 5192 // If this is already the right type, we're done. 5193 if (SrcEltVT == DstEltVT) return SDValue(BV, 0); 5194 5195 unsigned SrcBitSize = SrcEltVT.getSizeInBits(); 5196 unsigned DstBitSize = DstEltVT.getSizeInBits(); 5197 5198 // If this is a conversion of N elements of one type to N elements of another 5199 // type, convert each element. This handles FP<->INT cases. 5200 if (SrcBitSize == DstBitSize) { 5201 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, 5202 BV->getValueType(0).getVectorNumElements()); 5203 5204 // Due to the FP element handling below calling this routine recursively, 5205 // we can end up with a scalar-to-vector node here. 5206 if (BV->getOpcode() == ISD::SCALAR_TO_VECTOR) 5207 return DAG.getNode(ISD::SCALAR_TO_VECTOR, BV->getDebugLoc(), VT, 5208 DAG.getNode(ISD::BITCAST, BV->getDebugLoc(), 5209 DstEltVT, BV->getOperand(0))); 5210 5211 SmallVector<SDValue, 8> Ops; 5212 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 5213 SDValue Op = BV->getOperand(i); 5214 // If the vector element type is not legal, the BUILD_VECTOR operands 5215 // are promoted and implicitly truncated. Make that explicit here. 5216 if (Op.getValueType() != SrcEltVT) 5217 Op = DAG.getNode(ISD::TRUNCATE, BV->getDebugLoc(), SrcEltVT, Op); 5218 Ops.push_back(DAG.getNode(ISD::BITCAST, BV->getDebugLoc(), 5219 DstEltVT, Op)); 5220 AddToWorkList(Ops.back().getNode()); 5221 } 5222 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 5223 &Ops[0], Ops.size()); 5224 } 5225 5226 // Otherwise, we're growing or shrinking the elements. To avoid having to 5227 // handle annoying details of growing/shrinking FP values, we convert them to 5228 // int first. 5229 if (SrcEltVT.isFloatingPoint()) { 5230 // Convert the input float vector to a int vector where the elements are the 5231 // same sizes. 5232 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!"); 5233 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), SrcEltVT.getSizeInBits()); 5234 BV = ConstantFoldBITCASTofBUILD_VECTOR(BV, IntVT).getNode(); 5235 SrcEltVT = IntVT; 5236 } 5237 5238 // Now we know the input is an integer vector. If the output is a FP type, 5239 // convert to integer first, then to FP of the right size. 5240 if (DstEltVT.isFloatingPoint()) { 5241 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!"); 5242 EVT TmpVT = EVT::getIntegerVT(*DAG.getContext(), DstEltVT.getSizeInBits()); 5243 SDNode *Tmp = ConstantFoldBITCASTofBUILD_VECTOR(BV, TmpVT).getNode(); 5244 5245 // Next, convert to FP elements of the same size. 5246 return ConstantFoldBITCASTofBUILD_VECTOR(Tmp, DstEltVT); 5247 } 5248 5249 // Okay, we know the src/dst types are both integers of differing types. 5250 // Handling growing first. 5251 assert(SrcEltVT.isInteger() && DstEltVT.isInteger()); 5252 if (SrcBitSize < DstBitSize) { 5253 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize; 5254 5255 SmallVector<SDValue, 8> Ops; 5256 for (unsigned i = 0, e = BV->getNumOperands(); i != e; 5257 i += NumInputsPerOutput) { 5258 bool isLE = TLI.isLittleEndian(); 5259 APInt NewBits = APInt(DstBitSize, 0); 5260 bool EltIsUndef = true; 5261 for (unsigned j = 0; j != NumInputsPerOutput; ++j) { 5262 // Shift the previously computed bits over. 5263 NewBits <<= SrcBitSize; 5264 SDValue Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j)); 5265 if (Op.getOpcode() == ISD::UNDEF) continue; 5266 EltIsUndef = false; 5267 5268 NewBits |= cast<ConstantSDNode>(Op)->getAPIntValue(). 5269 zextOrTrunc(SrcBitSize).zext(DstBitSize); 5270 } 5271 5272 if (EltIsUndef) 5273 Ops.push_back(DAG.getUNDEF(DstEltVT)); 5274 else 5275 Ops.push_back(DAG.getConstant(NewBits, DstEltVT)); 5276 } 5277 5278 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, Ops.size()); 5279 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 5280 &Ops[0], Ops.size()); 5281 } 5282 5283 // Finally, this must be the case where we are shrinking elements: each input 5284 // turns into multiple outputs. 5285 bool isS2V = ISD::isScalarToVector(BV); 5286 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize; 5287 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, 5288 NumOutputsPerInput*BV->getNumOperands()); 5289 SmallVector<SDValue, 8> Ops; 5290 5291 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 5292 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) { 5293 for (unsigned j = 0; j != NumOutputsPerInput; ++j) 5294 Ops.push_back(DAG.getUNDEF(DstEltVT)); 5295 continue; 5296 } 5297 5298 APInt OpVal = cast<ConstantSDNode>(BV->getOperand(i))-> 5299 getAPIntValue().zextOrTrunc(SrcBitSize); 5300 5301 for (unsigned j = 0; j != NumOutputsPerInput; ++j) { 5302 APInt ThisVal = OpVal.trunc(DstBitSize); 5303 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT)); 5304 if (isS2V && i == 0 && j == 0 && ThisVal.zext(SrcBitSize) == OpVal) 5305 // Simply turn this into a SCALAR_TO_VECTOR of the new type. 5306 return DAG.getNode(ISD::SCALAR_TO_VECTOR, BV->getDebugLoc(), VT, 5307 Ops[0]); 5308 OpVal = OpVal.lshr(DstBitSize); 5309 } 5310 5311 // For big endian targets, swap the order of the pieces of each element. 5312 if (TLI.isBigEndian()) 5313 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end()); 5314 } 5315 5316 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 5317 &Ops[0], Ops.size()); 5318} 5319 5320SDValue DAGCombiner::visitFADD(SDNode *N) { 5321 SDValue N0 = N->getOperand(0); 5322 SDValue N1 = N->getOperand(1); 5323 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5324 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 5325 EVT VT = N->getValueType(0); 5326 5327 // fold vector ops 5328 if (VT.isVector()) { 5329 SDValue FoldedVOp = SimplifyVBinOp(N); 5330 if (FoldedVOp.getNode()) return FoldedVOp; 5331 } 5332 5333 // fold (fadd c1, c2) -> (fadd c1, c2) 5334 if (N0CFP && N1CFP && VT != MVT::ppcf128) 5335 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N1); 5336 // canonicalize constant to RHS 5337 if (N0CFP && !N1CFP) 5338 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N1, N0); 5339 // fold (fadd A, 0) -> A 5340 if (DAG.getTarget().Options.UnsafeFPMath && N1CFP && 5341 N1CFP->getValueAPF().isZero()) 5342 return N0; 5343 // fold (fadd A, (fneg B)) -> (fsub A, B) 5344 if (isNegatibleForFree(N1, LegalOperations, &DAG.getTarget().Options) == 2) 5345 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, 5346 GetNegatedExpression(N1, DAG, LegalOperations)); 5347 // fold (fadd (fneg A), B) -> (fsub B, A) 5348 if (isNegatibleForFree(N0, LegalOperations, &DAG.getTarget().Options) == 2) 5349 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N1, 5350 GetNegatedExpression(N0, DAG, LegalOperations)); 5351 5352 // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2)) 5353 if (DAG.getTarget().Options.UnsafeFPMath && N1CFP && 5354 N0.getOpcode() == ISD::FADD && N0.getNode()->hasOneUse() && 5355 isa<ConstantFPSDNode>(N0.getOperand(1))) 5356 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0.getOperand(0), 5357 DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, 5358 N0.getOperand(1), N1)); 5359 5360 return SDValue(); 5361} 5362 5363SDValue DAGCombiner::visitFSUB(SDNode *N) { 5364 SDValue N0 = N->getOperand(0); 5365 SDValue N1 = N->getOperand(1); 5366 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5367 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 5368 EVT VT = N->getValueType(0); 5369 5370 // fold vector ops 5371 if (VT.isVector()) { 5372 SDValue FoldedVOp = SimplifyVBinOp(N); 5373 if (FoldedVOp.getNode()) return FoldedVOp; 5374 } 5375 5376 // fold (fsub c1, c2) -> c1-c2 5377 if (N0CFP && N1CFP && VT != MVT::ppcf128) 5378 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, N1); 5379 // fold (fsub A, 0) -> A 5380 if (DAG.getTarget().Options.UnsafeFPMath && 5381 N1CFP && N1CFP->getValueAPF().isZero()) 5382 return N0; 5383 // fold (fsub 0, B) -> -B 5384 if (DAG.getTarget().Options.UnsafeFPMath && 5385 N0CFP && N0CFP->getValueAPF().isZero()) { 5386 if (isNegatibleForFree(N1, LegalOperations, &DAG.getTarget().Options)) 5387 return GetNegatedExpression(N1, DAG, LegalOperations); 5388 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 5389 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N1); 5390 } 5391 // fold (fsub A, (fneg B)) -> (fadd A, B) 5392 if (isNegatibleForFree(N1, LegalOperations, &DAG.getTarget().Options)) 5393 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, 5394 GetNegatedExpression(N1, DAG, LegalOperations)); 5395 5396 return SDValue(); 5397} 5398 5399SDValue DAGCombiner::visitFMUL(SDNode *N) { 5400 SDValue N0 = N->getOperand(0); 5401 SDValue N1 = N->getOperand(1); 5402 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5403 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 5404 EVT VT = N->getValueType(0); 5405 5406 // fold vector ops 5407 if (VT.isVector()) { 5408 SDValue FoldedVOp = SimplifyVBinOp(N); 5409 if (FoldedVOp.getNode()) return FoldedVOp; 5410 } 5411 5412 // fold (fmul c1, c2) -> c1*c2 5413 if (N0CFP && N1CFP && VT != MVT::ppcf128) 5414 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0, N1); 5415 // canonicalize constant to RHS 5416 if (N0CFP && !N1CFP) 5417 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N1, N0); 5418 // fold (fmul A, 0) -> 0 5419 if (DAG.getTarget().Options.UnsafeFPMath && 5420 N1CFP && N1CFP->getValueAPF().isZero()) 5421 return N1; 5422 // fold (fmul A, 0) -> 0, vector edition. 5423 if (DAG.getTarget().Options.UnsafeFPMath && 5424 ISD::isBuildVectorAllZeros(N1.getNode())) 5425 return N1; 5426 // fold (fmul X, 2.0) -> (fadd X, X) 5427 if (N1CFP && N1CFP->isExactlyValue(+2.0)) 5428 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N0); 5429 // fold (fmul X, -1.0) -> (fneg X) 5430 if (N1CFP && N1CFP->isExactlyValue(-1.0)) 5431 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 5432 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N0); 5433 5434 // fold (fmul (fneg X), (fneg Y)) -> (fmul X, Y) 5435 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations, 5436 &DAG.getTarget().Options)) { 5437 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations, 5438 &DAG.getTarget().Options)) { 5439 // Both can be negated for free, check to see if at least one is cheaper 5440 // negated. 5441 if (LHSNeg == 2 || RHSNeg == 2) 5442 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 5443 GetNegatedExpression(N0, DAG, LegalOperations), 5444 GetNegatedExpression(N1, DAG, LegalOperations)); 5445 } 5446 } 5447 5448 // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2)) 5449 if (DAG.getTarget().Options.UnsafeFPMath && 5450 N1CFP && N0.getOpcode() == ISD::FMUL && 5451 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 5452 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0.getOperand(0), 5453 DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 5454 N0.getOperand(1), N1)); 5455 5456 return SDValue(); 5457} 5458 5459SDValue DAGCombiner::visitFDIV(SDNode *N) { 5460 SDValue N0 = N->getOperand(0); 5461 SDValue N1 = N->getOperand(1); 5462 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5463 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 5464 EVT VT = N->getValueType(0); 5465 5466 // fold vector ops 5467 if (VT.isVector()) { 5468 SDValue FoldedVOp = SimplifyVBinOp(N); 5469 if (FoldedVOp.getNode()) return FoldedVOp; 5470 } 5471 5472 // fold (fdiv c1, c2) -> c1/c2 5473 if (N0CFP && N1CFP && VT != MVT::ppcf128) 5474 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, N0, N1); 5475 5476 5477 // (fdiv (fneg X), (fneg Y)) -> (fdiv X, Y) 5478 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations, 5479 &DAG.getTarget().Options)) { 5480 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations, 5481 &DAG.getTarget().Options)) { 5482 // Both can be negated for free, check to see if at least one is cheaper 5483 // negated. 5484 if (LHSNeg == 2 || RHSNeg == 2) 5485 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, 5486 GetNegatedExpression(N0, DAG, LegalOperations), 5487 GetNegatedExpression(N1, DAG, LegalOperations)); 5488 } 5489 } 5490 5491 return SDValue(); 5492} 5493 5494SDValue DAGCombiner::visitFREM(SDNode *N) { 5495 SDValue N0 = N->getOperand(0); 5496 SDValue N1 = N->getOperand(1); 5497 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5498 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 5499 EVT VT = N->getValueType(0); 5500 5501 // fold (frem c1, c2) -> fmod(c1,c2) 5502 if (N0CFP && N1CFP && VT != MVT::ppcf128) 5503 return DAG.getNode(ISD::FREM, N->getDebugLoc(), VT, N0, N1); 5504 5505 return SDValue(); 5506} 5507 5508SDValue DAGCombiner::visitFCOPYSIGN(SDNode *N) { 5509 SDValue N0 = N->getOperand(0); 5510 SDValue N1 = N->getOperand(1); 5511 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5512 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 5513 EVT VT = N->getValueType(0); 5514 5515 if (N0CFP && N1CFP && VT != MVT::ppcf128) // Constant fold 5516 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, N0, N1); 5517 5518 if (N1CFP) { 5519 const APFloat& V = N1CFP->getValueAPF(); 5520 // copysign(x, c1) -> fabs(x) iff ispos(c1) 5521 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1) 5522 if (!V.isNegative()) { 5523 if (!LegalOperations || TLI.isOperationLegal(ISD::FABS, VT)) 5524 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 5525 } else { 5526 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 5527 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, 5528 DAG.getNode(ISD::FABS, N0.getDebugLoc(), VT, N0)); 5529 } 5530 } 5531 5532 // copysign(fabs(x), y) -> copysign(x, y) 5533 // copysign(fneg(x), y) -> copysign(x, y) 5534 // copysign(copysign(x,z), y) -> copysign(x, y) 5535 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG || 5536 N0.getOpcode() == ISD::FCOPYSIGN) 5537 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 5538 N0.getOperand(0), N1); 5539 5540 // copysign(x, abs(y)) -> abs(x) 5541 if (N1.getOpcode() == ISD::FABS) 5542 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 5543 5544 // copysign(x, copysign(y,z)) -> copysign(x, z) 5545 if (N1.getOpcode() == ISD::FCOPYSIGN) 5546 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 5547 N0, N1.getOperand(1)); 5548 5549 // copysign(x, fp_extend(y)) -> copysign(x, y) 5550 // copysign(x, fp_round(y)) -> copysign(x, y) 5551 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND) 5552 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 5553 N0, N1.getOperand(0)); 5554 5555 return SDValue(); 5556} 5557 5558SDValue DAGCombiner::visitSINT_TO_FP(SDNode *N) { 5559 SDValue N0 = N->getOperand(0); 5560 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 5561 EVT VT = N->getValueType(0); 5562 EVT OpVT = N0.getValueType(); 5563 5564 // fold (sint_to_fp c1) -> c1fp 5565 if (N0C && OpVT != MVT::ppcf128 && 5566 // ...but only if the target supports immediate floating-point values 5567 (!LegalOperations || 5568 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT))) 5569 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0); 5570 5571 // If the input is a legal type, and SINT_TO_FP is not legal on this target, 5572 // but UINT_TO_FP is legal on this target, try to convert. 5573 if (!TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT) && 5574 TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT)) { 5575 // If the sign bit is known to be zero, we can change this to UINT_TO_FP. 5576 if (DAG.SignBitIsZero(N0)) 5577 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0); 5578 } 5579 5580 return SDValue(); 5581} 5582 5583SDValue DAGCombiner::visitUINT_TO_FP(SDNode *N) { 5584 SDValue N0 = N->getOperand(0); 5585 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 5586 EVT VT = N->getValueType(0); 5587 EVT OpVT = N0.getValueType(); 5588 5589 // fold (uint_to_fp c1) -> c1fp 5590 if (N0C && OpVT != MVT::ppcf128 && 5591 // ...but only if the target supports immediate floating-point values 5592 (!LegalOperations || 5593 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT))) 5594 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0); 5595 5596 // If the input is a legal type, and UINT_TO_FP is not legal on this target, 5597 // but SINT_TO_FP is legal on this target, try to convert. 5598 if (!TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT) && 5599 TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT)) { 5600 // If the sign bit is known to be zero, we can change this to SINT_TO_FP. 5601 if (DAG.SignBitIsZero(N0)) 5602 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0); 5603 } 5604 5605 return SDValue(); 5606} 5607 5608SDValue DAGCombiner::visitFP_TO_SINT(SDNode *N) { 5609 SDValue N0 = N->getOperand(0); 5610 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5611 EVT VT = N->getValueType(0); 5612 5613 // fold (fp_to_sint c1fp) -> c1 5614 if (N0CFP) 5615 return DAG.getNode(ISD::FP_TO_SINT, N->getDebugLoc(), VT, N0); 5616 5617 return SDValue(); 5618} 5619 5620SDValue DAGCombiner::visitFP_TO_UINT(SDNode *N) { 5621 SDValue N0 = N->getOperand(0); 5622 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5623 EVT VT = N->getValueType(0); 5624 5625 // fold (fp_to_uint c1fp) -> c1 5626 if (N0CFP && VT != MVT::ppcf128) 5627 return DAG.getNode(ISD::FP_TO_UINT, N->getDebugLoc(), VT, N0); 5628 5629 return SDValue(); 5630} 5631 5632SDValue DAGCombiner::visitFP_ROUND(SDNode *N) { 5633 SDValue N0 = N->getOperand(0); 5634 SDValue N1 = N->getOperand(1); 5635 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5636 EVT VT = N->getValueType(0); 5637 5638 // fold (fp_round c1fp) -> c1fp 5639 if (N0CFP && N0.getValueType() != MVT::ppcf128) 5640 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0, N1); 5641 5642 // fold (fp_round (fp_extend x)) -> x 5643 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType()) 5644 return N0.getOperand(0); 5645 5646 // fold (fp_round (fp_round x)) -> (fp_round x) 5647 if (N0.getOpcode() == ISD::FP_ROUND) { 5648 // This is a value preserving truncation if both round's are. 5649 bool IsTrunc = N->getConstantOperandVal(1) == 1 && 5650 N0.getNode()->getConstantOperandVal(1) == 1; 5651 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0.getOperand(0), 5652 DAG.getIntPtrConstant(IsTrunc)); 5653 } 5654 5655 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y) 5656 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse()) { 5657 SDValue Tmp = DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(), VT, 5658 N0.getOperand(0), N1); 5659 AddToWorkList(Tmp.getNode()); 5660 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 5661 Tmp, N0.getOperand(1)); 5662 } 5663 5664 return SDValue(); 5665} 5666 5667SDValue DAGCombiner::visitFP_ROUND_INREG(SDNode *N) { 5668 SDValue N0 = N->getOperand(0); 5669 EVT VT = N->getValueType(0); 5670 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 5671 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5672 5673 // fold (fp_round_inreg c1fp) -> c1fp 5674 if (N0CFP && isTypeLegal(EVT)) { 5675 SDValue Round = DAG.getConstantFP(*N0CFP->getConstantFPValue(), EVT); 5676 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, Round); 5677 } 5678 5679 return SDValue(); 5680} 5681 5682SDValue DAGCombiner::visitFP_EXTEND(SDNode *N) { 5683 SDValue N0 = N->getOperand(0); 5684 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5685 EVT VT = N->getValueType(0); 5686 5687 // If this is fp_round(fpextend), don't fold it, allow ourselves to be folded. 5688 if (N->hasOneUse() && 5689 N->use_begin()->getOpcode() == ISD::FP_ROUND) 5690 return SDValue(); 5691 5692 // fold (fp_extend c1fp) -> c1fp 5693 if (N0CFP && VT != MVT::ppcf128) 5694 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, N0); 5695 5696 // Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't affect the 5697 // value of X. 5698 if (N0.getOpcode() == ISD::FP_ROUND 5699 && N0.getNode()->getConstantOperandVal(1) == 1) { 5700 SDValue In = N0.getOperand(0); 5701 if (In.getValueType() == VT) return In; 5702 if (VT.bitsLT(In.getValueType())) 5703 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, 5704 In, N0.getOperand(1)); 5705 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, In); 5706 } 5707 5708 // fold (fpext (load x)) -> (fpext (fptrunc (extload x))) 5709 if (ISD::isNON_EXTLoad(N0.getNode()) && N0.hasOneUse() && 5710 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 5711 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) { 5712 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 5713 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT, 5714 LN0->getChain(), 5715 LN0->getBasePtr(), LN0->getPointerInfo(), 5716 N0.getValueType(), 5717 LN0->isVolatile(), LN0->isNonTemporal(), 5718 LN0->getAlignment()); 5719 CombineTo(N, ExtLoad); 5720 CombineTo(N0.getNode(), 5721 DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(), 5722 N0.getValueType(), ExtLoad, DAG.getIntPtrConstant(1)), 5723 ExtLoad.getValue(1)); 5724 return SDValue(N, 0); // Return N so it doesn't get rechecked! 5725 } 5726 5727 return SDValue(); 5728} 5729 5730SDValue DAGCombiner::visitFNEG(SDNode *N) { 5731 SDValue N0 = N->getOperand(0); 5732 EVT VT = N->getValueType(0); 5733 5734 if (isNegatibleForFree(N0, LegalOperations, &DAG.getTarget().Options)) 5735 return GetNegatedExpression(N0, DAG, LegalOperations); 5736 5737 // Transform fneg(bitconvert(x)) -> bitconvert(x^sign) to avoid loading 5738 // constant pool values. 5739 if (N0.getOpcode() == ISD::BITCAST && 5740 !VT.isVector() && 5741 N0.getNode()->hasOneUse() && 5742 N0.getOperand(0).getValueType().isInteger()) { 5743 SDValue Int = N0.getOperand(0); 5744 EVT IntVT = Int.getValueType(); 5745 if (IntVT.isInteger() && !IntVT.isVector()) { 5746 Int = DAG.getNode(ISD::XOR, N0.getDebugLoc(), IntVT, Int, 5747 DAG.getConstant(APInt::getSignBit(IntVT.getSizeInBits()), IntVT)); 5748 AddToWorkList(Int.getNode()); 5749 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), 5750 VT, Int); 5751 } 5752 } 5753 5754 return SDValue(); 5755} 5756 5757SDValue DAGCombiner::visitFABS(SDNode *N) { 5758 SDValue N0 = N->getOperand(0); 5759 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5760 EVT VT = N->getValueType(0); 5761 5762 // fold (fabs c1) -> fabs(c1) 5763 if (N0CFP && VT != MVT::ppcf128) 5764 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 5765 // fold (fabs (fabs x)) -> (fabs x) 5766 if (N0.getOpcode() == ISD::FABS) 5767 return N->getOperand(0); 5768 // fold (fabs (fneg x)) -> (fabs x) 5769 // fold (fabs (fcopysign x, y)) -> (fabs x) 5770 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN) 5771 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0.getOperand(0)); 5772 5773 // Transform fabs(bitconvert(x)) -> bitconvert(x&~sign) to avoid loading 5774 // constant pool values. 5775 if (N0.getOpcode() == ISD::BITCAST && N0.getNode()->hasOneUse() && 5776 N0.getOperand(0).getValueType().isInteger() && 5777 !N0.getOperand(0).getValueType().isVector()) { 5778 SDValue Int = N0.getOperand(0); 5779 EVT IntVT = Int.getValueType(); 5780 if (IntVT.isInteger() && !IntVT.isVector()) { 5781 Int = DAG.getNode(ISD::AND, N0.getDebugLoc(), IntVT, Int, 5782 DAG.getConstant(~APInt::getSignBit(IntVT.getSizeInBits()), IntVT)); 5783 AddToWorkList(Int.getNode()); 5784 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), 5785 N->getValueType(0), Int); 5786 } 5787 } 5788 5789 return SDValue(); 5790} 5791 5792SDValue DAGCombiner::visitBRCOND(SDNode *N) { 5793 SDValue Chain = N->getOperand(0); 5794 SDValue N1 = N->getOperand(1); 5795 SDValue N2 = N->getOperand(2); 5796 5797 // If N is a constant we could fold this into a fallthrough or unconditional 5798 // branch. However that doesn't happen very often in normal code, because 5799 // Instcombine/SimplifyCFG should have handled the available opportunities. 5800 // If we did this folding here, it would be necessary to update the 5801 // MachineBasicBlock CFG, which is awkward. 5802 5803 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal 5804 // on the target. 5805 if (N1.getOpcode() == ISD::SETCC && 5806 TLI.isOperationLegalOrCustom(ISD::BR_CC, MVT::Other)) { 5807 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other, 5808 Chain, N1.getOperand(2), 5809 N1.getOperand(0), N1.getOperand(1), N2); 5810 } 5811 5812 if ((N1.hasOneUse() && N1.getOpcode() == ISD::SRL) || 5813 ((N1.getOpcode() == ISD::TRUNCATE && N1.hasOneUse()) && 5814 (N1.getOperand(0).hasOneUse() && 5815 N1.getOperand(0).getOpcode() == ISD::SRL))) { 5816 SDNode *Trunc = 0; 5817 if (N1.getOpcode() == ISD::TRUNCATE) { 5818 // Look pass the truncate. 5819 Trunc = N1.getNode(); 5820 N1 = N1.getOperand(0); 5821 } 5822 5823 // Match this pattern so that we can generate simpler code: 5824 // 5825 // %a = ... 5826 // %b = and i32 %a, 2 5827 // %c = srl i32 %b, 1 5828 // brcond i32 %c ... 5829 // 5830 // into 5831 // 5832 // %a = ... 5833 // %b = and i32 %a, 2 5834 // %c = setcc eq %b, 0 5835 // brcond %c ... 5836 // 5837 // This applies only when the AND constant value has one bit set and the 5838 // SRL constant is equal to the log2 of the AND constant. The back-end is 5839 // smart enough to convert the result into a TEST/JMP sequence. 5840 SDValue Op0 = N1.getOperand(0); 5841 SDValue Op1 = N1.getOperand(1); 5842 5843 if (Op0.getOpcode() == ISD::AND && 5844 Op1.getOpcode() == ISD::Constant) { 5845 SDValue AndOp1 = Op0.getOperand(1); 5846 5847 if (AndOp1.getOpcode() == ISD::Constant) { 5848 const APInt &AndConst = cast<ConstantSDNode>(AndOp1)->getAPIntValue(); 5849 5850 if (AndConst.isPowerOf2() && 5851 cast<ConstantSDNode>(Op1)->getAPIntValue()==AndConst.logBase2()) { 5852 SDValue SetCC = 5853 DAG.getSetCC(N->getDebugLoc(), 5854 TLI.getSetCCResultType(Op0.getValueType()), 5855 Op0, DAG.getConstant(0, Op0.getValueType()), 5856 ISD::SETNE); 5857 5858 SDValue NewBRCond = DAG.getNode(ISD::BRCOND, N->getDebugLoc(), 5859 MVT::Other, Chain, SetCC, N2); 5860 // Don't add the new BRCond into the worklist or else SimplifySelectCC 5861 // will convert it back to (X & C1) >> C2. 5862 CombineTo(N, NewBRCond, false); 5863 // Truncate is dead. 5864 if (Trunc) { 5865 removeFromWorkList(Trunc); 5866 DAG.DeleteNode(Trunc); 5867 } 5868 // Replace the uses of SRL with SETCC 5869 WorkListRemover DeadNodes(*this); 5870 DAG.ReplaceAllUsesOfValueWith(N1, SetCC, &DeadNodes); 5871 removeFromWorkList(N1.getNode()); 5872 DAG.DeleteNode(N1.getNode()); 5873 return SDValue(N, 0); // Return N so it doesn't get rechecked! 5874 } 5875 } 5876 } 5877 5878 if (Trunc) 5879 // Restore N1 if the above transformation doesn't match. 5880 N1 = N->getOperand(1); 5881 } 5882 5883 // Transform br(xor(x, y)) -> br(x != y) 5884 // Transform br(xor(xor(x,y), 1)) -> br (x == y) 5885 if (N1.hasOneUse() && N1.getOpcode() == ISD::XOR) { 5886 SDNode *TheXor = N1.getNode(); 5887 SDValue Op0 = TheXor->getOperand(0); 5888 SDValue Op1 = TheXor->getOperand(1); 5889 if (Op0.getOpcode() == Op1.getOpcode()) { 5890 // Avoid missing important xor optimizations. 5891 SDValue Tmp = visitXOR(TheXor); 5892 if (Tmp.getNode() && Tmp.getNode() != TheXor) { 5893 DEBUG(dbgs() << "\nReplacing.8 "; 5894 TheXor->dump(&DAG); 5895 dbgs() << "\nWith: "; 5896 Tmp.getNode()->dump(&DAG); 5897 dbgs() << '\n'); 5898 WorkListRemover DeadNodes(*this); 5899 DAG.ReplaceAllUsesOfValueWith(N1, Tmp, &DeadNodes); 5900 removeFromWorkList(TheXor); 5901 DAG.DeleteNode(TheXor); 5902 return DAG.getNode(ISD::BRCOND, N->getDebugLoc(), 5903 MVT::Other, Chain, Tmp, N2); 5904 } 5905 } 5906 5907 if (Op0.getOpcode() != ISD::SETCC && Op1.getOpcode() != ISD::SETCC) { 5908 bool Equal = false; 5909 if (ConstantSDNode *RHSCI = dyn_cast<ConstantSDNode>(Op0)) 5910 if (RHSCI->getAPIntValue() == 1 && Op0.hasOneUse() && 5911 Op0.getOpcode() == ISD::XOR) { 5912 TheXor = Op0.getNode(); 5913 Equal = true; 5914 } 5915 5916 EVT SetCCVT = N1.getValueType(); 5917 if (LegalTypes) 5918 SetCCVT = TLI.getSetCCResultType(SetCCVT); 5919 SDValue SetCC = DAG.getSetCC(TheXor->getDebugLoc(), 5920 SetCCVT, 5921 Op0, Op1, 5922 Equal ? ISD::SETEQ : ISD::SETNE); 5923 // Replace the uses of XOR with SETCC 5924 WorkListRemover DeadNodes(*this); 5925 DAG.ReplaceAllUsesOfValueWith(N1, SetCC, &DeadNodes); 5926 removeFromWorkList(N1.getNode()); 5927 DAG.DeleteNode(N1.getNode()); 5928 return DAG.getNode(ISD::BRCOND, N->getDebugLoc(), 5929 MVT::Other, Chain, SetCC, N2); 5930 } 5931 } 5932 5933 return SDValue(); 5934} 5935 5936// Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB. 5937// 5938SDValue DAGCombiner::visitBR_CC(SDNode *N) { 5939 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1)); 5940 SDValue CondLHS = N->getOperand(2), CondRHS = N->getOperand(3); 5941 5942 // If N is a constant we could fold this into a fallthrough or unconditional 5943 // branch. However that doesn't happen very often in normal code, because 5944 // Instcombine/SimplifyCFG should have handled the available opportunities. 5945 // If we did this folding here, it would be necessary to update the 5946 // MachineBasicBlock CFG, which is awkward. 5947 5948 // Use SimplifySetCC to simplify SETCC's. 5949 SDValue Simp = SimplifySetCC(TLI.getSetCCResultType(CondLHS.getValueType()), 5950 CondLHS, CondRHS, CC->get(), N->getDebugLoc(), 5951 false); 5952 if (Simp.getNode()) AddToWorkList(Simp.getNode()); 5953 5954 // fold to a simpler setcc 5955 if (Simp.getNode() && Simp.getOpcode() == ISD::SETCC) 5956 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other, 5957 N->getOperand(0), Simp.getOperand(2), 5958 Simp.getOperand(0), Simp.getOperand(1), 5959 N->getOperand(4)); 5960 5961 return SDValue(); 5962} 5963 5964/// CombineToPreIndexedLoadStore - Try turning a load / store into a 5965/// pre-indexed load / store when the base pointer is an add or subtract 5966/// and it has other uses besides the load / store. After the 5967/// transformation, the new indexed load / store has effectively folded 5968/// the add / subtract in and all of its other uses are redirected to the 5969/// new load / store. 5970bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) { 5971 if (Level < AfterLegalizeDAG) 5972 return false; 5973 5974 bool isLoad = true; 5975 SDValue Ptr; 5976 EVT VT; 5977 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 5978 if (LD->isIndexed()) 5979 return false; 5980 VT = LD->getMemoryVT(); 5981 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) && 5982 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT)) 5983 return false; 5984 Ptr = LD->getBasePtr(); 5985 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 5986 if (ST->isIndexed()) 5987 return false; 5988 VT = ST->getMemoryVT(); 5989 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) && 5990 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT)) 5991 return false; 5992 Ptr = ST->getBasePtr(); 5993 isLoad = false; 5994 } else { 5995 return false; 5996 } 5997 5998 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail 5999 // out. There is no reason to make this a preinc/predec. 6000 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) || 6001 Ptr.getNode()->hasOneUse()) 6002 return false; 6003 6004 // Ask the target to do addressing mode selection. 6005 SDValue BasePtr; 6006 SDValue Offset; 6007 ISD::MemIndexedMode AM = ISD::UNINDEXED; 6008 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG)) 6009 return false; 6010 // Don't create a indexed load / store with zero offset. 6011 if (isa<ConstantSDNode>(Offset) && 6012 cast<ConstantSDNode>(Offset)->isNullValue()) 6013 return false; 6014 6015 // Try turning it into a pre-indexed load / store except when: 6016 // 1) The new base ptr is a frame index. 6017 // 2) If N is a store and the new base ptr is either the same as or is a 6018 // predecessor of the value being stored. 6019 // 3) Another use of old base ptr is a predecessor of N. If ptr is folded 6020 // that would create a cycle. 6021 // 4) All uses are load / store ops that use it as old base ptr. 6022 6023 // Check #1. Preinc'ing a frame index would require copying the stack pointer 6024 // (plus the implicit offset) to a register to preinc anyway. 6025 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr)) 6026 return false; 6027 6028 // Check #2. 6029 if (!isLoad) { 6030 SDValue Val = cast<StoreSDNode>(N)->getValue(); 6031 if (Val == BasePtr || BasePtr.getNode()->isPredecessorOf(Val.getNode())) 6032 return false; 6033 } 6034 6035 // Now check for #3 and #4. 6036 bool RealUse = false; 6037 6038 // Caches for hasPredecessorHelper 6039 SmallPtrSet<const SDNode *, 32> Visited; 6040 SmallVector<const SDNode *, 16> Worklist; 6041 6042 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(), 6043 E = Ptr.getNode()->use_end(); I != E; ++I) { 6044 SDNode *Use = *I; 6045 if (Use == N) 6046 continue; 6047 if (N->hasPredecessorHelper(Use, Visited, Worklist)) 6048 return false; 6049 6050 if (!((Use->getOpcode() == ISD::LOAD && 6051 cast<LoadSDNode>(Use)->getBasePtr() == Ptr) || 6052 (Use->getOpcode() == ISD::STORE && 6053 cast<StoreSDNode>(Use)->getBasePtr() == Ptr))) 6054 RealUse = true; 6055 } 6056 6057 if (!RealUse) 6058 return false; 6059 6060 SDValue Result; 6061 if (isLoad) 6062 Result = DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(), 6063 BasePtr, Offset, AM); 6064 else 6065 Result = DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(), 6066 BasePtr, Offset, AM); 6067 ++PreIndexedNodes; 6068 ++NodesCombined; 6069 DEBUG(dbgs() << "\nReplacing.4 "; 6070 N->dump(&DAG); 6071 dbgs() << "\nWith: "; 6072 Result.getNode()->dump(&DAG); 6073 dbgs() << '\n'); 6074 WorkListRemover DeadNodes(*this); 6075 if (isLoad) { 6076 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0), 6077 &DeadNodes); 6078 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2), 6079 &DeadNodes); 6080 } else { 6081 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1), 6082 &DeadNodes); 6083 } 6084 6085 // Finally, since the node is now dead, remove it from the graph. 6086 DAG.DeleteNode(N); 6087 6088 // Replace the uses of Ptr with uses of the updated base value. 6089 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0), 6090 &DeadNodes); 6091 removeFromWorkList(Ptr.getNode()); 6092 DAG.DeleteNode(Ptr.getNode()); 6093 6094 return true; 6095} 6096 6097/// CombineToPostIndexedLoadStore - Try to combine a load / store with a 6098/// add / sub of the base pointer node into a post-indexed load / store. 6099/// The transformation folded the add / subtract into the new indexed 6100/// load / store effectively and all of its uses are redirected to the 6101/// new load / store. 6102bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) { 6103 if (Level < AfterLegalizeDAG) 6104 return false; 6105 6106 bool isLoad = true; 6107 SDValue Ptr; 6108 EVT VT; 6109 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 6110 if (LD->isIndexed()) 6111 return false; 6112 VT = LD->getMemoryVT(); 6113 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) && 6114 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT)) 6115 return false; 6116 Ptr = LD->getBasePtr(); 6117 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 6118 if (ST->isIndexed()) 6119 return false; 6120 VT = ST->getMemoryVT(); 6121 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) && 6122 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT)) 6123 return false; 6124 Ptr = ST->getBasePtr(); 6125 isLoad = false; 6126 } else { 6127 return false; 6128 } 6129 6130 if (Ptr.getNode()->hasOneUse()) 6131 return false; 6132 6133 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(), 6134 E = Ptr.getNode()->use_end(); I != E; ++I) { 6135 SDNode *Op = *I; 6136 if (Op == N || 6137 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB)) 6138 continue; 6139 6140 SDValue BasePtr; 6141 SDValue Offset; 6142 ISD::MemIndexedMode AM = ISD::UNINDEXED; 6143 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) { 6144 // Don't create a indexed load / store with zero offset. 6145 if (isa<ConstantSDNode>(Offset) && 6146 cast<ConstantSDNode>(Offset)->isNullValue()) 6147 continue; 6148 6149 // Try turning it into a post-indexed load / store except when 6150 // 1) All uses are load / store ops that use it as base ptr. 6151 // 2) Op must be independent of N, i.e. Op is neither a predecessor 6152 // nor a successor of N. Otherwise, if Op is folded that would 6153 // create a cycle. 6154 6155 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr)) 6156 continue; 6157 6158 // Check for #1. 6159 bool TryNext = false; 6160 for (SDNode::use_iterator II = BasePtr.getNode()->use_begin(), 6161 EE = BasePtr.getNode()->use_end(); II != EE; ++II) { 6162 SDNode *Use = *II; 6163 if (Use == Ptr.getNode()) 6164 continue; 6165 6166 // If all the uses are load / store addresses, then don't do the 6167 // transformation. 6168 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){ 6169 bool RealUse = false; 6170 for (SDNode::use_iterator III = Use->use_begin(), 6171 EEE = Use->use_end(); III != EEE; ++III) { 6172 SDNode *UseUse = *III; 6173 if (!((UseUse->getOpcode() == ISD::LOAD && 6174 cast<LoadSDNode>(UseUse)->getBasePtr().getNode() == Use) || 6175 (UseUse->getOpcode() == ISD::STORE && 6176 cast<StoreSDNode>(UseUse)->getBasePtr().getNode() == Use))) 6177 RealUse = true; 6178 } 6179 6180 if (!RealUse) { 6181 TryNext = true; 6182 break; 6183 } 6184 } 6185 } 6186 6187 if (TryNext) 6188 continue; 6189 6190 // Check for #2 6191 if (!Op->isPredecessorOf(N) && !N->isPredecessorOf(Op)) { 6192 SDValue Result = isLoad 6193 ? DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(), 6194 BasePtr, Offset, AM) 6195 : DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(), 6196 BasePtr, Offset, AM); 6197 ++PostIndexedNodes; 6198 ++NodesCombined; 6199 DEBUG(dbgs() << "\nReplacing.5 "; 6200 N->dump(&DAG); 6201 dbgs() << "\nWith: "; 6202 Result.getNode()->dump(&DAG); 6203 dbgs() << '\n'); 6204 WorkListRemover DeadNodes(*this); 6205 if (isLoad) { 6206 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0), 6207 &DeadNodes); 6208 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2), 6209 &DeadNodes); 6210 } else { 6211 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1), 6212 &DeadNodes); 6213 } 6214 6215 // Finally, since the node is now dead, remove it from the graph. 6216 DAG.DeleteNode(N); 6217 6218 // Replace the uses of Use with uses of the updated base value. 6219 DAG.ReplaceAllUsesOfValueWith(SDValue(Op, 0), 6220 Result.getValue(isLoad ? 1 : 0), 6221 &DeadNodes); 6222 removeFromWorkList(Op); 6223 DAG.DeleteNode(Op); 6224 return true; 6225 } 6226 } 6227 } 6228 6229 return false; 6230} 6231 6232SDValue DAGCombiner::visitLOAD(SDNode *N) { 6233 LoadSDNode *LD = cast<LoadSDNode>(N); 6234 SDValue Chain = LD->getChain(); 6235 SDValue Ptr = LD->getBasePtr(); 6236 6237 // If load is not volatile and there are no uses of the loaded value (and 6238 // the updated indexed value in case of indexed loads), change uses of the 6239 // chain value into uses of the chain input (i.e. delete the dead load). 6240 if (!LD->isVolatile()) { 6241 if (N->getValueType(1) == MVT::Other) { 6242 // Unindexed loads. 6243 if (!N->hasAnyUseOfValue(0)) { 6244 // It's not safe to use the two value CombineTo variant here. e.g. 6245 // v1, chain2 = load chain1, loc 6246 // v2, chain3 = load chain2, loc 6247 // v3 = add v2, c 6248 // Now we replace use of chain2 with chain1. This makes the second load 6249 // isomorphic to the one we are deleting, and thus makes this load live. 6250 DEBUG(dbgs() << "\nReplacing.6 "; 6251 N->dump(&DAG); 6252 dbgs() << "\nWith chain: "; 6253 Chain.getNode()->dump(&DAG); 6254 dbgs() << "\n"); 6255 WorkListRemover DeadNodes(*this); 6256 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Chain, &DeadNodes); 6257 6258 if (N->use_empty()) { 6259 removeFromWorkList(N); 6260 DAG.DeleteNode(N); 6261 } 6262 6263 return SDValue(N, 0); // Return N so it doesn't get rechecked! 6264 } 6265 } else { 6266 // Indexed loads. 6267 assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?"); 6268 if (!N->hasAnyUseOfValue(0) && !N->hasAnyUseOfValue(1)) { 6269 SDValue Undef = DAG.getUNDEF(N->getValueType(0)); 6270 DEBUG(dbgs() << "\nReplacing.7 "; 6271 N->dump(&DAG); 6272 dbgs() << "\nWith: "; 6273 Undef.getNode()->dump(&DAG); 6274 dbgs() << " and 2 other values\n"); 6275 WorkListRemover DeadNodes(*this); 6276 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Undef, &DeadNodes); 6277 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), 6278 DAG.getUNDEF(N->getValueType(1)), 6279 &DeadNodes); 6280 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 2), Chain, &DeadNodes); 6281 removeFromWorkList(N); 6282 DAG.DeleteNode(N); 6283 return SDValue(N, 0); // Return N so it doesn't get rechecked! 6284 } 6285 } 6286 } 6287 6288 // If this load is directly stored, replace the load value with the stored 6289 // value. 6290 // TODO: Handle store large -> read small portion. 6291 // TODO: Handle TRUNCSTORE/LOADEXT 6292 if (ISD::isNormalLoad(N) && !LD->isVolatile()) { 6293 if (ISD::isNON_TRUNCStore(Chain.getNode())) { 6294 StoreSDNode *PrevST = cast<StoreSDNode>(Chain); 6295 if (PrevST->getBasePtr() == Ptr && 6296 PrevST->getValue().getValueType() == N->getValueType(0)) 6297 return CombineTo(N, Chain.getOperand(1), Chain); 6298 } 6299 } 6300 6301 // Try to infer better alignment information than the load already has. 6302 if (OptLevel != CodeGenOpt::None && LD->isUnindexed()) { 6303 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) { 6304 if (Align > LD->getAlignment()) 6305 return DAG.getExtLoad(LD->getExtensionType(), N->getDebugLoc(), 6306 LD->getValueType(0), 6307 Chain, Ptr, LD->getPointerInfo(), 6308 LD->getMemoryVT(), 6309 LD->isVolatile(), LD->isNonTemporal(), Align); 6310 } 6311 } 6312 6313 if (CombinerAA) { 6314 // Walk up chain skipping non-aliasing memory nodes. 6315 SDValue BetterChain = FindBetterChain(N, Chain); 6316 6317 // If there is a better chain. 6318 if (Chain != BetterChain) { 6319 SDValue ReplLoad; 6320 6321 // Replace the chain to void dependency. 6322 if (LD->getExtensionType() == ISD::NON_EXTLOAD) { 6323 ReplLoad = DAG.getLoad(N->getValueType(0), LD->getDebugLoc(), 6324 BetterChain, Ptr, LD->getPointerInfo(), 6325 LD->isVolatile(), LD->isNonTemporal(), 6326 LD->isInvariant(), LD->getAlignment()); 6327 } else { 6328 ReplLoad = DAG.getExtLoad(LD->getExtensionType(), LD->getDebugLoc(), 6329 LD->getValueType(0), 6330 BetterChain, Ptr, LD->getPointerInfo(), 6331 LD->getMemoryVT(), 6332 LD->isVolatile(), 6333 LD->isNonTemporal(), 6334 LD->getAlignment()); 6335 } 6336 6337 // Create token factor to keep old chain connected. 6338 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 6339 MVT::Other, Chain, ReplLoad.getValue(1)); 6340 6341 // Make sure the new and old chains are cleaned up. 6342 AddToWorkList(Token.getNode()); 6343 6344 // Replace uses with load result and token factor. Don't add users 6345 // to work list. 6346 return CombineTo(N, ReplLoad.getValue(0), Token, false); 6347 } 6348 } 6349 6350 // Try transforming N to an indexed load. 6351 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 6352 return SDValue(N, 0); 6353 6354 return SDValue(); 6355} 6356 6357/// CheckForMaskedLoad - Check to see if V is (and load (ptr), imm), where the 6358/// load is having specific bytes cleared out. If so, return the byte size 6359/// being masked out and the shift amount. 6360static std::pair<unsigned, unsigned> 6361CheckForMaskedLoad(SDValue V, SDValue Ptr, SDValue Chain) { 6362 std::pair<unsigned, unsigned> Result(0, 0); 6363 6364 // Check for the structure we're looking for. 6365 if (V->getOpcode() != ISD::AND || 6366 !isa<ConstantSDNode>(V->getOperand(1)) || 6367 !ISD::isNormalLoad(V->getOperand(0).getNode())) 6368 return Result; 6369 6370 // Check the chain and pointer. 6371 LoadSDNode *LD = cast<LoadSDNode>(V->getOperand(0)); 6372 if (LD->getBasePtr() != Ptr) return Result; // Not from same pointer. 6373 6374 // The store should be chained directly to the load or be an operand of a 6375 // tokenfactor. 6376 if (LD == Chain.getNode()) 6377 ; // ok. 6378 else if (Chain->getOpcode() != ISD::TokenFactor) 6379 return Result; // Fail. 6380 else { 6381 bool isOk = false; 6382 for (unsigned i = 0, e = Chain->getNumOperands(); i != e; ++i) 6383 if (Chain->getOperand(i).getNode() == LD) { 6384 isOk = true; 6385 break; 6386 } 6387 if (!isOk) return Result; 6388 } 6389 6390 // This only handles simple types. 6391 if (V.getValueType() != MVT::i16 && 6392 V.getValueType() != MVT::i32 && 6393 V.getValueType() != MVT::i64) 6394 return Result; 6395 6396 // Check the constant mask. Invert it so that the bits being masked out are 6397 // 0 and the bits being kept are 1. Use getSExtValue so that leading bits 6398 // follow the sign bit for uniformity. 6399 uint64_t NotMask = ~cast<ConstantSDNode>(V->getOperand(1))->getSExtValue(); 6400 unsigned NotMaskLZ = CountLeadingZeros_64(NotMask); 6401 if (NotMaskLZ & 7) return Result; // Must be multiple of a byte. 6402 unsigned NotMaskTZ = CountTrailingZeros_64(NotMask); 6403 if (NotMaskTZ & 7) return Result; // Must be multiple of a byte. 6404 if (NotMaskLZ == 64) return Result; // All zero mask. 6405 6406 // See if we have a continuous run of bits. If so, we have 0*1+0* 6407 if (CountTrailingOnes_64(NotMask >> NotMaskTZ)+NotMaskTZ+NotMaskLZ != 64) 6408 return Result; 6409 6410 // Adjust NotMaskLZ down to be from the actual size of the int instead of i64. 6411 if (V.getValueType() != MVT::i64 && NotMaskLZ) 6412 NotMaskLZ -= 64-V.getValueSizeInBits(); 6413 6414 unsigned MaskedBytes = (V.getValueSizeInBits()-NotMaskLZ-NotMaskTZ)/8; 6415 switch (MaskedBytes) { 6416 case 1: 6417 case 2: 6418 case 4: break; 6419 default: return Result; // All one mask, or 5-byte mask. 6420 } 6421 6422 // Verify that the first bit starts at a multiple of mask so that the access 6423 // is aligned the same as the access width. 6424 if (NotMaskTZ && NotMaskTZ/8 % MaskedBytes) return Result; 6425 6426 Result.first = MaskedBytes; 6427 Result.second = NotMaskTZ/8; 6428 return Result; 6429} 6430 6431 6432/// ShrinkLoadReplaceStoreWithStore - Check to see if IVal is something that 6433/// provides a value as specified by MaskInfo. If so, replace the specified 6434/// store with a narrower store of truncated IVal. 6435static SDNode * 6436ShrinkLoadReplaceStoreWithStore(const std::pair<unsigned, unsigned> &MaskInfo, 6437 SDValue IVal, StoreSDNode *St, 6438 DAGCombiner *DC) { 6439 unsigned NumBytes = MaskInfo.first; 6440 unsigned ByteShift = MaskInfo.second; 6441 SelectionDAG &DAG = DC->getDAG(); 6442 6443 // Check to see if IVal is all zeros in the part being masked in by the 'or' 6444 // that uses this. If not, this is not a replacement. 6445 APInt Mask = ~APInt::getBitsSet(IVal.getValueSizeInBits(), 6446 ByteShift*8, (ByteShift+NumBytes)*8); 6447 if (!DAG.MaskedValueIsZero(IVal, Mask)) return 0; 6448 6449 // Check that it is legal on the target to do this. It is legal if the new 6450 // VT we're shrinking to (i8/i16/i32) is legal or we're still before type 6451 // legalization. 6452 MVT VT = MVT::getIntegerVT(NumBytes*8); 6453 if (!DC->isTypeLegal(VT)) 6454 return 0; 6455 6456 // Okay, we can do this! Replace the 'St' store with a store of IVal that is 6457 // shifted by ByteShift and truncated down to NumBytes. 6458 if (ByteShift) 6459 IVal = DAG.getNode(ISD::SRL, IVal->getDebugLoc(), IVal.getValueType(), IVal, 6460 DAG.getConstant(ByteShift*8, 6461 DC->getShiftAmountTy(IVal.getValueType()))); 6462 6463 // Figure out the offset for the store and the alignment of the access. 6464 unsigned StOffset; 6465 unsigned NewAlign = St->getAlignment(); 6466 6467 if (DAG.getTargetLoweringInfo().isLittleEndian()) 6468 StOffset = ByteShift; 6469 else 6470 StOffset = IVal.getValueType().getStoreSize() - ByteShift - NumBytes; 6471 6472 SDValue Ptr = St->getBasePtr(); 6473 if (StOffset) { 6474 Ptr = DAG.getNode(ISD::ADD, IVal->getDebugLoc(), Ptr.getValueType(), 6475 Ptr, DAG.getConstant(StOffset, Ptr.getValueType())); 6476 NewAlign = MinAlign(NewAlign, StOffset); 6477 } 6478 6479 // Truncate down to the new size. 6480 IVal = DAG.getNode(ISD::TRUNCATE, IVal->getDebugLoc(), VT, IVal); 6481 6482 ++OpsNarrowed; 6483 return DAG.getStore(St->getChain(), St->getDebugLoc(), IVal, Ptr, 6484 St->getPointerInfo().getWithOffset(StOffset), 6485 false, false, NewAlign).getNode(); 6486} 6487 6488 6489/// ReduceLoadOpStoreWidth - Look for sequence of load / op / store where op is 6490/// one of 'or', 'xor', and 'and' of immediates. If 'op' is only touching some 6491/// of the loaded bits, try narrowing the load and store if it would end up 6492/// being a win for performance or code size. 6493SDValue DAGCombiner::ReduceLoadOpStoreWidth(SDNode *N) { 6494 StoreSDNode *ST = cast<StoreSDNode>(N); 6495 if (ST->isVolatile()) 6496 return SDValue(); 6497 6498 SDValue Chain = ST->getChain(); 6499 SDValue Value = ST->getValue(); 6500 SDValue Ptr = ST->getBasePtr(); 6501 EVT VT = Value.getValueType(); 6502 6503 if (ST->isTruncatingStore() || VT.isVector() || !Value.hasOneUse()) 6504 return SDValue(); 6505 6506 unsigned Opc = Value.getOpcode(); 6507 6508 // If this is "store (or X, Y), P" and X is "(and (load P), cst)", where cst 6509 // is a byte mask indicating a consecutive number of bytes, check to see if 6510 // Y is known to provide just those bytes. If so, we try to replace the 6511 // load + replace + store sequence with a single (narrower) store, which makes 6512 // the load dead. 6513 if (Opc == ISD::OR) { 6514 std::pair<unsigned, unsigned> MaskedLoad; 6515 MaskedLoad = CheckForMaskedLoad(Value.getOperand(0), Ptr, Chain); 6516 if (MaskedLoad.first) 6517 if (SDNode *NewST = ShrinkLoadReplaceStoreWithStore(MaskedLoad, 6518 Value.getOperand(1), ST,this)) 6519 return SDValue(NewST, 0); 6520 6521 // Or is commutative, so try swapping X and Y. 6522 MaskedLoad = CheckForMaskedLoad(Value.getOperand(1), Ptr, Chain); 6523 if (MaskedLoad.first) 6524 if (SDNode *NewST = ShrinkLoadReplaceStoreWithStore(MaskedLoad, 6525 Value.getOperand(0), ST,this)) 6526 return SDValue(NewST, 0); 6527 } 6528 6529 if ((Opc != ISD::OR && Opc != ISD::XOR && Opc != ISD::AND) || 6530 Value.getOperand(1).getOpcode() != ISD::Constant) 6531 return SDValue(); 6532 6533 SDValue N0 = Value.getOperand(0); 6534 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() && 6535 Chain == SDValue(N0.getNode(), 1)) { 6536 LoadSDNode *LD = cast<LoadSDNode>(N0); 6537 if (LD->getBasePtr() != Ptr || 6538 LD->getPointerInfo().getAddrSpace() != 6539 ST->getPointerInfo().getAddrSpace()) 6540 return SDValue(); 6541 6542 // Find the type to narrow it the load / op / store to. 6543 SDValue N1 = Value.getOperand(1); 6544 unsigned BitWidth = N1.getValueSizeInBits(); 6545 APInt Imm = cast<ConstantSDNode>(N1)->getAPIntValue(); 6546 if (Opc == ISD::AND) 6547 Imm ^= APInt::getAllOnesValue(BitWidth); 6548 if (Imm == 0 || Imm.isAllOnesValue()) 6549 return SDValue(); 6550 unsigned ShAmt = Imm.countTrailingZeros(); 6551 unsigned MSB = BitWidth - Imm.countLeadingZeros() - 1; 6552 unsigned NewBW = NextPowerOf2(MSB - ShAmt); 6553 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW); 6554 while (NewBW < BitWidth && 6555 !(TLI.isOperationLegalOrCustom(Opc, NewVT) && 6556 TLI.isNarrowingProfitable(VT, NewVT))) { 6557 NewBW = NextPowerOf2(NewBW); 6558 NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW); 6559 } 6560 if (NewBW >= BitWidth) 6561 return SDValue(); 6562 6563 // If the lsb changed does not start at the type bitwidth boundary, 6564 // start at the previous one. 6565 if (ShAmt % NewBW) 6566 ShAmt = (((ShAmt + NewBW - 1) / NewBW) * NewBW) - NewBW; 6567 APInt Mask = APInt::getBitsSet(BitWidth, ShAmt, ShAmt + NewBW); 6568 if ((Imm & Mask) == Imm) { 6569 APInt NewImm = (Imm & Mask).lshr(ShAmt).trunc(NewBW); 6570 if (Opc == ISD::AND) 6571 NewImm ^= APInt::getAllOnesValue(NewBW); 6572 uint64_t PtrOff = ShAmt / 8; 6573 // For big endian targets, we need to adjust the offset to the pointer to 6574 // load the correct bytes. 6575 if (TLI.isBigEndian()) 6576 PtrOff = (BitWidth + 7 - NewBW) / 8 - PtrOff; 6577 6578 unsigned NewAlign = MinAlign(LD->getAlignment(), PtrOff); 6579 Type *NewVTTy = NewVT.getTypeForEVT(*DAG.getContext()); 6580 if (NewAlign < TLI.getTargetData()->getABITypeAlignment(NewVTTy)) 6581 return SDValue(); 6582 6583 SDValue NewPtr = DAG.getNode(ISD::ADD, LD->getDebugLoc(), 6584 Ptr.getValueType(), Ptr, 6585 DAG.getConstant(PtrOff, Ptr.getValueType())); 6586 SDValue NewLD = DAG.getLoad(NewVT, N0.getDebugLoc(), 6587 LD->getChain(), NewPtr, 6588 LD->getPointerInfo().getWithOffset(PtrOff), 6589 LD->isVolatile(), LD->isNonTemporal(), 6590 LD->isInvariant(), NewAlign); 6591 SDValue NewVal = DAG.getNode(Opc, Value.getDebugLoc(), NewVT, NewLD, 6592 DAG.getConstant(NewImm, NewVT)); 6593 SDValue NewST = DAG.getStore(Chain, N->getDebugLoc(), 6594 NewVal, NewPtr, 6595 ST->getPointerInfo().getWithOffset(PtrOff), 6596 false, false, NewAlign); 6597 6598 AddToWorkList(NewPtr.getNode()); 6599 AddToWorkList(NewLD.getNode()); 6600 AddToWorkList(NewVal.getNode()); 6601 WorkListRemover DeadNodes(*this); 6602 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), NewLD.getValue(1), 6603 &DeadNodes); 6604 ++OpsNarrowed; 6605 return NewST; 6606 } 6607 } 6608 6609 return SDValue(); 6610} 6611 6612/// TransformFPLoadStorePair - For a given floating point load / store pair, 6613/// if the load value isn't used by any other operations, then consider 6614/// transforming the pair to integer load / store operations if the target 6615/// deems the transformation profitable. 6616SDValue DAGCombiner::TransformFPLoadStorePair(SDNode *N) { 6617 StoreSDNode *ST = cast<StoreSDNode>(N); 6618 SDValue Chain = ST->getChain(); 6619 SDValue Value = ST->getValue(); 6620 if (ISD::isNormalStore(ST) && ISD::isNormalLoad(Value.getNode()) && 6621 Value.hasOneUse() && 6622 Chain == SDValue(Value.getNode(), 1)) { 6623 LoadSDNode *LD = cast<LoadSDNode>(Value); 6624 EVT VT = LD->getMemoryVT(); 6625 if (!VT.isFloatingPoint() || 6626 VT != ST->getMemoryVT() || 6627 LD->isNonTemporal() || 6628 ST->isNonTemporal() || 6629 LD->getPointerInfo().getAddrSpace() != 0 || 6630 ST->getPointerInfo().getAddrSpace() != 0) 6631 return SDValue(); 6632 6633 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits()); 6634 if (!TLI.isOperationLegal(ISD::LOAD, IntVT) || 6635 !TLI.isOperationLegal(ISD::STORE, IntVT) || 6636 !TLI.isDesirableToTransformToIntegerOp(ISD::LOAD, VT) || 6637 !TLI.isDesirableToTransformToIntegerOp(ISD::STORE, VT)) 6638 return SDValue(); 6639 6640 unsigned LDAlign = LD->getAlignment(); 6641 unsigned STAlign = ST->getAlignment(); 6642 Type *IntVTTy = IntVT.getTypeForEVT(*DAG.getContext()); 6643 unsigned ABIAlign = TLI.getTargetData()->getABITypeAlignment(IntVTTy); 6644 if (LDAlign < ABIAlign || STAlign < ABIAlign) 6645 return SDValue(); 6646 6647 SDValue NewLD = DAG.getLoad(IntVT, Value.getDebugLoc(), 6648 LD->getChain(), LD->getBasePtr(), 6649 LD->getPointerInfo(), 6650 false, false, false, LDAlign); 6651 6652 SDValue NewST = DAG.getStore(NewLD.getValue(1), N->getDebugLoc(), 6653 NewLD, ST->getBasePtr(), 6654 ST->getPointerInfo(), 6655 false, false, STAlign); 6656 6657 AddToWorkList(NewLD.getNode()); 6658 AddToWorkList(NewST.getNode()); 6659 WorkListRemover DeadNodes(*this); 6660 DAG.ReplaceAllUsesOfValueWith(Value.getValue(1), NewLD.getValue(1), 6661 &DeadNodes); 6662 ++LdStFP2Int; 6663 return NewST; 6664 } 6665 6666 return SDValue(); 6667} 6668 6669SDValue DAGCombiner::visitSTORE(SDNode *N) { 6670 StoreSDNode *ST = cast<StoreSDNode>(N); 6671 SDValue Chain = ST->getChain(); 6672 SDValue Value = ST->getValue(); 6673 SDValue Ptr = ST->getBasePtr(); 6674 6675 // If this is a store of a bit convert, store the input value if the 6676 // resultant store does not need a higher alignment than the original. 6677 if (Value.getOpcode() == ISD::BITCAST && !ST->isTruncatingStore() && 6678 ST->isUnindexed()) { 6679 unsigned OrigAlign = ST->getAlignment(); 6680 EVT SVT = Value.getOperand(0).getValueType(); 6681 unsigned Align = TLI.getTargetData()-> 6682 getABITypeAlignment(SVT.getTypeForEVT(*DAG.getContext())); 6683 if (Align <= OrigAlign && 6684 ((!LegalOperations && !ST->isVolatile()) || 6685 TLI.isOperationLegalOrCustom(ISD::STORE, SVT))) 6686 return DAG.getStore(Chain, N->getDebugLoc(), Value.getOperand(0), 6687 Ptr, ST->getPointerInfo(), ST->isVolatile(), 6688 ST->isNonTemporal(), OrigAlign); 6689 } 6690 6691 // Turn 'store undef, Ptr' -> nothing. 6692 if (Value.getOpcode() == ISD::UNDEF && ST->isUnindexed()) 6693 return Chain; 6694 6695 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 6696 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) { 6697 // NOTE: If the original store is volatile, this transform must not increase 6698 // the number of stores. For example, on x86-32 an f64 can be stored in one 6699 // processor operation but an i64 (which is not legal) requires two. So the 6700 // transform should not be done in this case. 6701 if (Value.getOpcode() != ISD::TargetConstantFP) { 6702 SDValue Tmp; 6703 switch (CFP->getValueType(0).getSimpleVT().SimpleTy) { 6704 default: llvm_unreachable("Unknown FP type"); 6705 case MVT::f80: // We don't do this for these yet. 6706 case MVT::f128: 6707 case MVT::ppcf128: 6708 break; 6709 case MVT::f32: 6710 if ((isTypeLegal(MVT::i32) && !LegalOperations && !ST->isVolatile()) || 6711 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) { 6712 Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF(). 6713 bitcastToAPInt().getZExtValue(), MVT::i32); 6714 return DAG.getStore(Chain, N->getDebugLoc(), Tmp, 6715 Ptr, ST->getPointerInfo(), ST->isVolatile(), 6716 ST->isNonTemporal(), ST->getAlignment()); 6717 } 6718 break; 6719 case MVT::f64: 6720 if ((TLI.isTypeLegal(MVT::i64) && !LegalOperations && 6721 !ST->isVolatile()) || 6722 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i64)) { 6723 Tmp = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt(). 6724 getZExtValue(), MVT::i64); 6725 return DAG.getStore(Chain, N->getDebugLoc(), Tmp, 6726 Ptr, ST->getPointerInfo(), ST->isVolatile(), 6727 ST->isNonTemporal(), ST->getAlignment()); 6728 } 6729 6730 if (!ST->isVolatile() && 6731 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) { 6732 // Many FP stores are not made apparent until after legalize, e.g. for 6733 // argument passing. Since this is so common, custom legalize the 6734 // 64-bit integer store into two 32-bit stores. 6735 uint64_t Val = CFP->getValueAPF().bitcastToAPInt().getZExtValue(); 6736 SDValue Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32); 6737 SDValue Hi = DAG.getConstant(Val >> 32, MVT::i32); 6738 if (TLI.isBigEndian()) std::swap(Lo, Hi); 6739 6740 unsigned Alignment = ST->getAlignment(); 6741 bool isVolatile = ST->isVolatile(); 6742 bool isNonTemporal = ST->isNonTemporal(); 6743 6744 SDValue St0 = DAG.getStore(Chain, ST->getDebugLoc(), Lo, 6745 Ptr, ST->getPointerInfo(), 6746 isVolatile, isNonTemporal, 6747 ST->getAlignment()); 6748 Ptr = DAG.getNode(ISD::ADD, N->getDebugLoc(), Ptr.getValueType(), Ptr, 6749 DAG.getConstant(4, Ptr.getValueType())); 6750 Alignment = MinAlign(Alignment, 4U); 6751 SDValue St1 = DAG.getStore(Chain, ST->getDebugLoc(), Hi, 6752 Ptr, ST->getPointerInfo().getWithOffset(4), 6753 isVolatile, isNonTemporal, 6754 Alignment); 6755 return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, 6756 St0, St1); 6757 } 6758 6759 break; 6760 } 6761 } 6762 } 6763 6764 // Try to infer better alignment information than the store already has. 6765 if (OptLevel != CodeGenOpt::None && ST->isUnindexed()) { 6766 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) { 6767 if (Align > ST->getAlignment()) 6768 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value, 6769 Ptr, ST->getPointerInfo(), ST->getMemoryVT(), 6770 ST->isVolatile(), ST->isNonTemporal(), Align); 6771 } 6772 } 6773 6774 // Try transforming a pair floating point load / store ops to integer 6775 // load / store ops. 6776 SDValue NewST = TransformFPLoadStorePair(N); 6777 if (NewST.getNode()) 6778 return NewST; 6779 6780 if (CombinerAA) { 6781 // Walk up chain skipping non-aliasing memory nodes. 6782 SDValue BetterChain = FindBetterChain(N, Chain); 6783 6784 // If there is a better chain. 6785 if (Chain != BetterChain) { 6786 SDValue ReplStore; 6787 6788 // Replace the chain to avoid dependency. 6789 if (ST->isTruncatingStore()) { 6790 ReplStore = DAG.getTruncStore(BetterChain, N->getDebugLoc(), Value, Ptr, 6791 ST->getPointerInfo(), 6792 ST->getMemoryVT(), ST->isVolatile(), 6793 ST->isNonTemporal(), ST->getAlignment()); 6794 } else { 6795 ReplStore = DAG.getStore(BetterChain, N->getDebugLoc(), Value, Ptr, 6796 ST->getPointerInfo(), 6797 ST->isVolatile(), ST->isNonTemporal(), 6798 ST->getAlignment()); 6799 } 6800 6801 // Create token to keep both nodes around. 6802 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 6803 MVT::Other, Chain, ReplStore); 6804 6805 // Make sure the new and old chains are cleaned up. 6806 AddToWorkList(Token.getNode()); 6807 6808 // Don't add users to work list. 6809 return CombineTo(N, Token, false); 6810 } 6811 } 6812 6813 // Try transforming N to an indexed store. 6814 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 6815 return SDValue(N, 0); 6816 6817 // FIXME: is there such a thing as a truncating indexed store? 6818 if (ST->isTruncatingStore() && ST->isUnindexed() && 6819 Value.getValueType().isInteger()) { 6820 // See if we can simplify the input to this truncstore with knowledge that 6821 // only the low bits are being used. For example: 6822 // "truncstore (or (shl x, 8), y), i8" -> "truncstore y, i8" 6823 SDValue Shorter = 6824 GetDemandedBits(Value, 6825 APInt::getLowBitsSet( 6826 Value.getValueType().getScalarType().getSizeInBits(), 6827 ST->getMemoryVT().getScalarType().getSizeInBits())); 6828 AddToWorkList(Value.getNode()); 6829 if (Shorter.getNode()) 6830 return DAG.getTruncStore(Chain, N->getDebugLoc(), Shorter, 6831 Ptr, ST->getPointerInfo(), ST->getMemoryVT(), 6832 ST->isVolatile(), ST->isNonTemporal(), 6833 ST->getAlignment()); 6834 6835 // Otherwise, see if we can simplify the operation with 6836 // SimplifyDemandedBits, which only works if the value has a single use. 6837 if (SimplifyDemandedBits(Value, 6838 APInt::getLowBitsSet( 6839 Value.getValueType().getScalarType().getSizeInBits(), 6840 ST->getMemoryVT().getScalarType().getSizeInBits()))) 6841 return SDValue(N, 0); 6842 } 6843 6844 // If this is a load followed by a store to the same location, then the store 6845 // is dead/noop. 6846 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Value)) { 6847 if (Ld->getBasePtr() == Ptr && ST->getMemoryVT() == Ld->getMemoryVT() && 6848 ST->isUnindexed() && !ST->isVolatile() && 6849 // There can't be any side effects between the load and store, such as 6850 // a call or store. 6851 Chain.reachesChainWithoutSideEffects(SDValue(Ld, 1))) { 6852 // The store is dead, remove it. 6853 return Chain; 6854 } 6855 } 6856 6857 // If this is an FP_ROUND or TRUNC followed by a store, fold this into a 6858 // truncating store. We can do this even if this is already a truncstore. 6859 if ((Value.getOpcode() == ISD::FP_ROUND || Value.getOpcode() == ISD::TRUNCATE) 6860 && Value.getNode()->hasOneUse() && ST->isUnindexed() && 6861 TLI.isTruncStoreLegal(Value.getOperand(0).getValueType(), 6862 ST->getMemoryVT())) { 6863 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value.getOperand(0), 6864 Ptr, ST->getPointerInfo(), ST->getMemoryVT(), 6865 ST->isVolatile(), ST->isNonTemporal(), 6866 ST->getAlignment()); 6867 } 6868 6869 return ReduceLoadOpStoreWidth(N); 6870} 6871 6872SDValue DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) { 6873 SDValue InVec = N->getOperand(0); 6874 SDValue InVal = N->getOperand(1); 6875 SDValue EltNo = N->getOperand(2); 6876 DebugLoc dl = N->getDebugLoc(); 6877 6878 // If the inserted element is an UNDEF, just use the input vector. 6879 if (InVal.getOpcode() == ISD::UNDEF) 6880 return InVec; 6881 6882 EVT VT = InVec.getValueType(); 6883 6884 // If we can't generate a legal BUILD_VECTOR, exit 6885 if (LegalOperations && !TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) 6886 return SDValue(); 6887 6888 // Check that we know which element is being inserted 6889 if (!isa<ConstantSDNode>(EltNo)) 6890 return SDValue(); 6891 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 6892 6893 // Check that the operand is a BUILD_VECTOR (or UNDEF, which can essentially 6894 // be converted to a BUILD_VECTOR). Fill in the Ops vector with the 6895 // vector elements. 6896 SmallVector<SDValue, 8> Ops; 6897 if (InVec.getOpcode() == ISD::BUILD_VECTOR) { 6898 Ops.append(InVec.getNode()->op_begin(), 6899 InVec.getNode()->op_end()); 6900 } else if (InVec.getOpcode() == ISD::UNDEF) { 6901 unsigned NElts = VT.getVectorNumElements(); 6902 Ops.append(NElts, DAG.getUNDEF(InVal.getValueType())); 6903 } else { 6904 return SDValue(); 6905 } 6906 6907 // Insert the element 6908 if (Elt < Ops.size()) { 6909 // All the operands of BUILD_VECTOR must have the same type; 6910 // we enforce that here. 6911 EVT OpVT = Ops[0].getValueType(); 6912 if (InVal.getValueType() != OpVT) 6913 InVal = OpVT.bitsGT(InVal.getValueType()) ? 6914 DAG.getNode(ISD::ANY_EXTEND, dl, OpVT, InVal) : 6915 DAG.getNode(ISD::TRUNCATE, dl, OpVT, InVal); 6916 Ops[Elt] = InVal; 6917 } 6918 6919 // Return the new vector 6920 return DAG.getNode(ISD::BUILD_VECTOR, dl, 6921 VT, &Ops[0], Ops.size()); 6922} 6923 6924SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) { 6925 // (vextract (scalar_to_vector val, 0) -> val 6926 SDValue InVec = N->getOperand(0); 6927 6928 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) { 6929 // Check if the result type doesn't match the inserted element type. A 6930 // SCALAR_TO_VECTOR may truncate the inserted element and the 6931 // EXTRACT_VECTOR_ELT may widen the extracted vector. 6932 SDValue InOp = InVec.getOperand(0); 6933 EVT NVT = N->getValueType(0); 6934 if (InOp.getValueType() != NVT) { 6935 assert(InOp.getValueType().isInteger() && NVT.isInteger()); 6936 return DAG.getSExtOrTrunc(InOp, InVec.getDebugLoc(), NVT); 6937 } 6938 return InOp; 6939 } 6940 6941 // Perform only after legalization to ensure build_vector / vector_shuffle 6942 // optimizations have already been done. 6943 if (!LegalOperations) return SDValue(); 6944 6945 // (vextract (v4f32 load $addr), c) -> (f32 load $addr+c*size) 6946 // (vextract (v4f32 s2v (f32 load $addr)), c) -> (f32 load $addr+c*size) 6947 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), 0) -> (f32 load $addr) 6948 SDValue EltNo = N->getOperand(1); 6949 6950 if (isa<ConstantSDNode>(EltNo)) { 6951 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 6952 bool NewLoad = false; 6953 bool BCNumEltsChanged = false; 6954 EVT VT = InVec.getValueType(); 6955 EVT ExtVT = VT.getVectorElementType(); 6956 EVT LVT = ExtVT; 6957 6958 if (InVec.getOpcode() == ISD::BITCAST) { 6959 // Don't duplicate a load with other uses. 6960 if (!InVec.hasOneUse()) 6961 return SDValue(); 6962 6963 EVT BCVT = InVec.getOperand(0).getValueType(); 6964 if (!BCVT.isVector() || ExtVT.bitsGT(BCVT.getVectorElementType())) 6965 return SDValue(); 6966 if (VT.getVectorNumElements() != BCVT.getVectorNumElements()) 6967 BCNumEltsChanged = true; 6968 InVec = InVec.getOperand(0); 6969 ExtVT = BCVT.getVectorElementType(); 6970 NewLoad = true; 6971 } 6972 6973 LoadSDNode *LN0 = NULL; 6974 const ShuffleVectorSDNode *SVN = NULL; 6975 if (ISD::isNormalLoad(InVec.getNode())) { 6976 LN0 = cast<LoadSDNode>(InVec); 6977 } else if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR && 6978 InVec.getOperand(0).getValueType() == ExtVT && 6979 ISD::isNormalLoad(InVec.getOperand(0).getNode())) { 6980 // Don't duplicate a load with other uses. 6981 if (!InVec.hasOneUse()) 6982 return SDValue(); 6983 6984 LN0 = cast<LoadSDNode>(InVec.getOperand(0)); 6985 } else if ((SVN = dyn_cast<ShuffleVectorSDNode>(InVec))) { 6986 // (vextract (vector_shuffle (load $addr), v2, <1, u, u, u>), 1) 6987 // => 6988 // (load $addr+1*size) 6989 6990 // Don't duplicate a load with other uses. 6991 if (!InVec.hasOneUse()) 6992 return SDValue(); 6993 6994 // If the bit convert changed the number of elements, it is unsafe 6995 // to examine the mask. 6996 if (BCNumEltsChanged) 6997 return SDValue(); 6998 6999 // Select the input vector, guarding against out of range extract vector. 7000 unsigned NumElems = VT.getVectorNumElements(); 7001 int Idx = (Elt > (int)NumElems) ? -1 : SVN->getMaskElt(Elt); 7002 InVec = (Idx < (int)NumElems) ? InVec.getOperand(0) : InVec.getOperand(1); 7003 7004 if (InVec.getOpcode() == ISD::BITCAST) { 7005 // Don't duplicate a load with other uses. 7006 if (!InVec.hasOneUse()) 7007 return SDValue(); 7008 7009 InVec = InVec.getOperand(0); 7010 } 7011 if (ISD::isNormalLoad(InVec.getNode())) { 7012 LN0 = cast<LoadSDNode>(InVec); 7013 Elt = (Idx < (int)NumElems) ? Idx : Idx - (int)NumElems; 7014 } 7015 } 7016 7017 // Make sure we found a non-volatile load and the extractelement is 7018 // the only use. 7019 if (!LN0 || !LN0->hasNUsesOfValue(1,0) || LN0->isVolatile()) 7020 return SDValue(); 7021 7022 // If Idx was -1 above, Elt is going to be -1, so just return undef. 7023 if (Elt == -1) 7024 return DAG.getUNDEF(LVT); 7025 7026 unsigned Align = LN0->getAlignment(); 7027 if (NewLoad) { 7028 // Check the resultant load doesn't need a higher alignment than the 7029 // original load. 7030 unsigned NewAlign = 7031 TLI.getTargetData() 7032 ->getABITypeAlignment(LVT.getTypeForEVT(*DAG.getContext())); 7033 7034 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, LVT)) 7035 return SDValue(); 7036 7037 Align = NewAlign; 7038 } 7039 7040 SDValue NewPtr = LN0->getBasePtr(); 7041 unsigned PtrOff = 0; 7042 7043 if (Elt) { 7044 PtrOff = LVT.getSizeInBits() * Elt / 8; 7045 EVT PtrType = NewPtr.getValueType(); 7046 if (TLI.isBigEndian()) 7047 PtrOff = VT.getSizeInBits() / 8 - PtrOff; 7048 NewPtr = DAG.getNode(ISD::ADD, N->getDebugLoc(), PtrType, NewPtr, 7049 DAG.getConstant(PtrOff, PtrType)); 7050 } 7051 7052 // The replacement we need to do here is a little tricky: we need to 7053 // replace an extractelement of a load with a load. 7054 // Use ReplaceAllUsesOfValuesWith to do the replacement. 7055 // Note that this replacement assumes that the extractvalue is the only 7056 // use of the load; that's okay because we don't want to perform this 7057 // transformation in other cases anyway. 7058 SDValue Load = DAG.getLoad(LVT, N->getDebugLoc(), LN0->getChain(), NewPtr, 7059 LN0->getPointerInfo().getWithOffset(PtrOff), 7060 LN0->isVolatile(), LN0->isNonTemporal(), 7061 LN0->isInvariant(), Align); 7062 WorkListRemover DeadNodes(*this); 7063 SDValue From[] = { SDValue(N, 0), SDValue(LN0,1) }; 7064 SDValue To[] = { Load.getValue(0), Load.getValue(1) }; 7065 DAG.ReplaceAllUsesOfValuesWith(From, To, 2, &DeadNodes); 7066 // Since we're explcitly calling ReplaceAllUses, add the new node to the 7067 // worklist explicitly as well. 7068 AddToWorkList(Load.getNode()); 7069 // Make sure to revisit this node to clean it up; it will usually be dead. 7070 AddToWorkList(N); 7071 return SDValue(N, 0); 7072 } 7073 7074 return SDValue(); 7075} 7076 7077SDValue DAGCombiner::visitBUILD_VECTOR(SDNode *N) { 7078 unsigned NumInScalars = N->getNumOperands(); 7079 DebugLoc dl = N->getDebugLoc(); 7080 EVT VT = N->getValueType(0); 7081 // Check to see if this is a BUILD_VECTOR of a bunch of values 7082 // which come from any_extend or zero_extend nodes. If so, we can create 7083 // a new BUILD_VECTOR using bit-casts which may enable other BUILD_VECTOR 7084 // optimizations. We do not handle sign-extend because we can't fill the sign 7085 // using shuffles. 7086 EVT SourceType = MVT::Other; 7087 bool allAnyExt = true; 7088 for (unsigned i = 0; i < NumInScalars; ++i) { 7089 SDValue In = N->getOperand(i); 7090 // Ignore undef inputs. 7091 if (In.getOpcode() == ISD::UNDEF) continue; 7092 7093 bool AnyExt = In.getOpcode() == ISD::ANY_EXTEND; 7094 bool ZeroExt = In.getOpcode() == ISD::ZERO_EXTEND; 7095 7096 // Abort if the element is not an extension. 7097 if (!ZeroExt && !AnyExt) { 7098 SourceType = MVT::Other; 7099 break; 7100 } 7101 7102 // The input is a ZeroExt or AnyExt. Check the original type. 7103 EVT InTy = In.getOperand(0).getValueType(); 7104 7105 // Check that all of the widened source types are the same. 7106 if (SourceType == MVT::Other) 7107 // First time. 7108 SourceType = InTy; 7109 else if (InTy != SourceType) { 7110 // Multiple income types. Abort. 7111 SourceType = MVT::Other; 7112 break; 7113 } 7114 7115 // Check if all of the extends are ANY_EXTENDs. 7116 allAnyExt &= AnyExt; 7117 } 7118 7119 7120 // In order to have valid types, all of the inputs must be extended from the 7121 // same source type and all of the inputs must be any or zero extend. 7122 // Scalar sizes must be a power of two. 7123 EVT OutScalarTy = N->getValueType(0).getScalarType(); 7124 bool validTypes = SourceType != MVT::Other && 7125 isPowerOf2_32(OutScalarTy.getSizeInBits()) && 7126 isPowerOf2_32(SourceType.getSizeInBits()); 7127 7128 // We perform this optimization post type-legalization because 7129 // the type-legalizer often scalarizes integer-promoted vectors. 7130 // Performing this optimization before may create bit-casts which 7131 // will be type-legalized to complex code sequences. 7132 // We perform this optimization only before the operation legalizer because we 7133 // may introduce illegal operations. 7134 if (LegalTypes && !LegalOperations && validTypes) { 7135 bool isLE = TLI.isLittleEndian(); 7136 unsigned ElemRatio = OutScalarTy.getSizeInBits()/SourceType.getSizeInBits(); 7137 assert(ElemRatio > 1 && "Invalid element size ratio"); 7138 SDValue Filler = allAnyExt ? DAG.getUNDEF(SourceType): 7139 DAG.getConstant(0, SourceType); 7140 7141 unsigned NewBVElems = ElemRatio * N->getValueType(0).getVectorNumElements(); 7142 SmallVector<SDValue, 8> Ops(NewBVElems, Filler); 7143 7144 // Populate the new build_vector 7145 for (unsigned i=0; i < N->getNumOperands(); ++i) { 7146 SDValue Cast = N->getOperand(i); 7147 assert((Cast.getOpcode() == ISD::ANY_EXTEND || 7148 Cast.getOpcode() == ISD::ZERO_EXTEND || 7149 Cast.getOpcode() == ISD::UNDEF) && "Invalid cast opcode"); 7150 SDValue In; 7151 if (Cast.getOpcode() == ISD::UNDEF) 7152 In = DAG.getUNDEF(SourceType); 7153 else 7154 In = Cast->getOperand(0); 7155 unsigned Index = isLE ? (i * ElemRatio) : 7156 (i * ElemRatio + (ElemRatio - 1)); 7157 7158 assert(Index < Ops.size() && "Invalid index"); 7159 Ops[Index] = In; 7160 } 7161 7162 // The type of the new BUILD_VECTOR node. 7163 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), SourceType, NewBVElems); 7164 assert(VecVT.getSizeInBits() == N->getValueType(0).getSizeInBits() && 7165 "Invalid vector size"); 7166 // Check if the new vector type is legal. 7167 if (!isTypeLegal(VecVT)) return SDValue(); 7168 7169 // Make the new BUILD_VECTOR. 7170 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 7171 VecVT, &Ops[0], Ops.size()); 7172 7173 // Bitcast to the desired type. 7174 return DAG.getNode(ISD::BITCAST, dl, N->getValueType(0), BV); 7175 } 7176 7177 // Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT 7178 // operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from 7179 // at most two distinct vectors, turn this into a shuffle node. 7180 SDValue VecIn1, VecIn2; 7181 for (unsigned i = 0; i != NumInScalars; ++i) { 7182 // Ignore undef inputs. 7183 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 7184 7185 // If this input is something other than a EXTRACT_VECTOR_ELT with a 7186 // constant index, bail out. 7187 if (N->getOperand(i).getOpcode() != ISD::EXTRACT_VECTOR_ELT || 7188 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) { 7189 VecIn1 = VecIn2 = SDValue(0, 0); 7190 break; 7191 } 7192 7193 // If the input vector type disagrees with the result of the build_vector, 7194 // we can't make a shuffle. 7195 SDValue ExtractedFromVec = N->getOperand(i).getOperand(0); 7196 if (ExtractedFromVec.getValueType() != VT) { 7197 VecIn1 = VecIn2 = SDValue(0, 0); 7198 break; 7199 } 7200 7201 // Otherwise, remember this. We allow up to two distinct input vectors. 7202 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2) 7203 continue; 7204 7205 if (VecIn1.getNode() == 0) { 7206 VecIn1 = ExtractedFromVec; 7207 } else if (VecIn2.getNode() == 0) { 7208 VecIn2 = ExtractedFromVec; 7209 } else { 7210 // Too many inputs. 7211 VecIn1 = VecIn2 = SDValue(0, 0); 7212 break; 7213 } 7214 } 7215 7216 // If everything is good, we can make a shuffle operation. 7217 if (VecIn1.getNode()) { 7218 SmallVector<int, 8> Mask; 7219 for (unsigned i = 0; i != NumInScalars; ++i) { 7220 if (N->getOperand(i).getOpcode() == ISD::UNDEF) { 7221 Mask.push_back(-1); 7222 continue; 7223 } 7224 7225 // If extracting from the first vector, just use the index directly. 7226 SDValue Extract = N->getOperand(i); 7227 SDValue ExtVal = Extract.getOperand(1); 7228 if (Extract.getOperand(0) == VecIn1) { 7229 unsigned ExtIndex = cast<ConstantSDNode>(ExtVal)->getZExtValue(); 7230 if (ExtIndex > VT.getVectorNumElements()) 7231 return SDValue(); 7232 7233 Mask.push_back(ExtIndex); 7234 continue; 7235 } 7236 7237 // Otherwise, use InIdx + VecSize 7238 unsigned Idx = cast<ConstantSDNode>(ExtVal)->getZExtValue(); 7239 Mask.push_back(Idx+NumInScalars); 7240 } 7241 7242 // Add count and size info. 7243 if (!isTypeLegal(VT)) 7244 return SDValue(); 7245 7246 // Return the new VECTOR_SHUFFLE node. 7247 SDValue Ops[2]; 7248 Ops[0] = VecIn1; 7249 Ops[1] = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT); 7250 return DAG.getVectorShuffle(VT, N->getDebugLoc(), Ops[0], Ops[1], &Mask[0]); 7251 } 7252 7253 return SDValue(); 7254} 7255 7256SDValue DAGCombiner::visitCONCAT_VECTORS(SDNode *N) { 7257 // TODO: Check to see if this is a CONCAT_VECTORS of a bunch of 7258 // EXTRACT_SUBVECTOR operations. If so, and if the EXTRACT_SUBVECTOR vector 7259 // inputs come from at most two distinct vectors, turn this into a shuffle 7260 // node. 7261 7262 // If we only have one input vector, we don't need to do any concatenation. 7263 if (N->getNumOperands() == 1) 7264 return N->getOperand(0); 7265 7266 return SDValue(); 7267} 7268 7269SDValue DAGCombiner::visitEXTRACT_SUBVECTOR(SDNode* N) { 7270 EVT NVT = N->getValueType(0); 7271 SDValue V = N->getOperand(0); 7272 7273 if (V->getOpcode() == ISD::INSERT_SUBVECTOR) { 7274 // Handle only simple case where vector being inserted and vector 7275 // being extracted are of same type, and are half size of larger vectors. 7276 EVT BigVT = V->getOperand(0).getValueType(); 7277 EVT SmallVT = V->getOperand(1).getValueType(); 7278 if (NVT != SmallVT || NVT.getSizeInBits()*2 != BigVT.getSizeInBits()) 7279 return SDValue(); 7280 7281 // Only handle cases where both indexes are constants with the same type. 7282 ConstantSDNode *InsIdx = dyn_cast<ConstantSDNode>(N->getOperand(1)); 7283 ConstantSDNode *ExtIdx = dyn_cast<ConstantSDNode>(V->getOperand(2)); 7284 7285 if (InsIdx && ExtIdx && 7286 InsIdx->getValueType(0).getSizeInBits() <= 64 && 7287 ExtIdx->getValueType(0).getSizeInBits() <= 64) { 7288 // Combine: 7289 // (extract_subvec (insert_subvec V1, V2, InsIdx), ExtIdx) 7290 // Into: 7291 // indices are equal => V1 7292 // otherwise => (extract_subvec V1, ExtIdx) 7293 if (InsIdx->getZExtValue() == ExtIdx->getZExtValue()) 7294 return V->getOperand(1); 7295 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, N->getDebugLoc(), NVT, 7296 V->getOperand(0), N->getOperand(1)); 7297 } 7298 } 7299 7300 return SDValue(); 7301} 7302 7303SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) { 7304 EVT VT = N->getValueType(0); 7305 unsigned NumElts = VT.getVectorNumElements(); 7306 7307 SDValue N0 = N->getOperand(0); 7308 SDValue N1 = N->getOperand(1); 7309 7310 assert(N0.getValueType().getVectorNumElements() == NumElts && 7311 "Vector shuffle must be normalized in DAG"); 7312 7313 // Canonicalize shuffle undef, undef -> undef 7314 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF) 7315 return DAG.getUNDEF(VT); 7316 7317 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N); 7318 7319 // Canonicalize shuffle v, v -> v, undef 7320 if (N0 == N1) { 7321 SmallVector<int, 8> NewMask; 7322 for (unsigned i = 0; i != NumElts; ++i) { 7323 int Idx = SVN->getMaskElt(i); 7324 if (Idx >= (int)NumElts) Idx -= NumElts; 7325 NewMask.push_back(Idx); 7326 } 7327 return DAG.getVectorShuffle(VT, N->getDebugLoc(), N0, DAG.getUNDEF(VT), 7328 &NewMask[0]); 7329 } 7330 7331 // Canonicalize shuffle undef, v -> v, undef. Commute the shuffle mask. 7332 if (N0.getOpcode() == ISD::UNDEF) { 7333 SmallVector<int, 8> NewMask; 7334 for (unsigned i = 0; i != NumElts; ++i) { 7335 int Idx = SVN->getMaskElt(i); 7336 if (Idx < 0) 7337 NewMask.push_back(Idx); 7338 else if (Idx < (int)NumElts) 7339 NewMask.push_back(Idx + NumElts); 7340 else 7341 NewMask.push_back(Idx - NumElts); 7342 } 7343 return DAG.getVectorShuffle(VT, N->getDebugLoc(), N1, DAG.getUNDEF(VT), 7344 &NewMask[0]); 7345 } 7346 7347 // Remove references to rhs if it is undef 7348 if (N1.getOpcode() == ISD::UNDEF) { 7349 bool Changed = false; 7350 SmallVector<int, 8> NewMask; 7351 for (unsigned i = 0; i != NumElts; ++i) { 7352 int Idx = SVN->getMaskElt(i); 7353 if (Idx >= (int)NumElts) { 7354 Idx = -1; 7355 Changed = true; 7356 } 7357 NewMask.push_back(Idx); 7358 } 7359 if (Changed) 7360 return DAG.getVectorShuffle(VT, N->getDebugLoc(), N0, N1, &NewMask[0]); 7361 } 7362 7363 // If it is a splat, check if the argument vector is another splat or a 7364 // build_vector with all scalar elements the same. 7365 if (SVN->isSplat() && SVN->getSplatIndex() < (int)NumElts) { 7366 SDNode *V = N0.getNode(); 7367 7368 // If this is a bit convert that changes the element type of the vector but 7369 // not the number of vector elements, look through it. Be careful not to 7370 // look though conversions that change things like v4f32 to v2f64. 7371 if (V->getOpcode() == ISD::BITCAST) { 7372 SDValue ConvInput = V->getOperand(0); 7373 if (ConvInput.getValueType().isVector() && 7374 ConvInput.getValueType().getVectorNumElements() == NumElts) 7375 V = ConvInput.getNode(); 7376 } 7377 7378 if (V->getOpcode() == ISD::BUILD_VECTOR) { 7379 assert(V->getNumOperands() == NumElts && 7380 "BUILD_VECTOR has wrong number of operands"); 7381 SDValue Base; 7382 bool AllSame = true; 7383 for (unsigned i = 0; i != NumElts; ++i) { 7384 if (V->getOperand(i).getOpcode() != ISD::UNDEF) { 7385 Base = V->getOperand(i); 7386 break; 7387 } 7388 } 7389 // Splat of <u, u, u, u>, return <u, u, u, u> 7390 if (!Base.getNode()) 7391 return N0; 7392 for (unsigned i = 0; i != NumElts; ++i) { 7393 if (V->getOperand(i) != Base) { 7394 AllSame = false; 7395 break; 7396 } 7397 } 7398 // Splat of <x, x, x, x>, return <x, x, x, x> 7399 if (AllSame) 7400 return N0; 7401 } 7402 } 7403 return SDValue(); 7404} 7405 7406SDValue DAGCombiner::visitMEMBARRIER(SDNode* N) { 7407 if (!TLI.getShouldFoldAtomicFences()) 7408 return SDValue(); 7409 7410 SDValue atomic = N->getOperand(0); 7411 switch (atomic.getOpcode()) { 7412 case ISD::ATOMIC_CMP_SWAP: 7413 case ISD::ATOMIC_SWAP: 7414 case ISD::ATOMIC_LOAD_ADD: 7415 case ISD::ATOMIC_LOAD_SUB: 7416 case ISD::ATOMIC_LOAD_AND: 7417 case ISD::ATOMIC_LOAD_OR: 7418 case ISD::ATOMIC_LOAD_XOR: 7419 case ISD::ATOMIC_LOAD_NAND: 7420 case ISD::ATOMIC_LOAD_MIN: 7421 case ISD::ATOMIC_LOAD_MAX: 7422 case ISD::ATOMIC_LOAD_UMIN: 7423 case ISD::ATOMIC_LOAD_UMAX: 7424 break; 7425 default: 7426 return SDValue(); 7427 } 7428 7429 SDValue fence = atomic.getOperand(0); 7430 if (fence.getOpcode() != ISD::MEMBARRIER) 7431 return SDValue(); 7432 7433 switch (atomic.getOpcode()) { 7434 case ISD::ATOMIC_CMP_SWAP: 7435 return SDValue(DAG.UpdateNodeOperands(atomic.getNode(), 7436 fence.getOperand(0), 7437 atomic.getOperand(1), atomic.getOperand(2), 7438 atomic.getOperand(3)), atomic.getResNo()); 7439 case ISD::ATOMIC_SWAP: 7440 case ISD::ATOMIC_LOAD_ADD: 7441 case ISD::ATOMIC_LOAD_SUB: 7442 case ISD::ATOMIC_LOAD_AND: 7443 case ISD::ATOMIC_LOAD_OR: 7444 case ISD::ATOMIC_LOAD_XOR: 7445 case ISD::ATOMIC_LOAD_NAND: 7446 case ISD::ATOMIC_LOAD_MIN: 7447 case ISD::ATOMIC_LOAD_MAX: 7448 case ISD::ATOMIC_LOAD_UMIN: 7449 case ISD::ATOMIC_LOAD_UMAX: 7450 return SDValue(DAG.UpdateNodeOperands(atomic.getNode(), 7451 fence.getOperand(0), 7452 atomic.getOperand(1), atomic.getOperand(2)), 7453 atomic.getResNo()); 7454 default: 7455 return SDValue(); 7456 } 7457} 7458 7459/// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform 7460/// an AND to a vector_shuffle with the destination vector and a zero vector. 7461/// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==> 7462/// vector_shuffle V, Zero, <0, 4, 2, 4> 7463SDValue DAGCombiner::XformToShuffleWithZero(SDNode *N) { 7464 EVT VT = N->getValueType(0); 7465 DebugLoc dl = N->getDebugLoc(); 7466 SDValue LHS = N->getOperand(0); 7467 SDValue RHS = N->getOperand(1); 7468 if (N->getOpcode() == ISD::AND) { 7469 if (RHS.getOpcode() == ISD::BITCAST) 7470 RHS = RHS.getOperand(0); 7471 if (RHS.getOpcode() == ISD::BUILD_VECTOR) { 7472 SmallVector<int, 8> Indices; 7473 unsigned NumElts = RHS.getNumOperands(); 7474 for (unsigned i = 0; i != NumElts; ++i) { 7475 SDValue Elt = RHS.getOperand(i); 7476 if (!isa<ConstantSDNode>(Elt)) 7477 return SDValue(); 7478 else if (cast<ConstantSDNode>(Elt)->isAllOnesValue()) 7479 Indices.push_back(i); 7480 else if (cast<ConstantSDNode>(Elt)->isNullValue()) 7481 Indices.push_back(NumElts); 7482 else 7483 return SDValue(); 7484 } 7485 7486 // Let's see if the target supports this vector_shuffle. 7487 EVT RVT = RHS.getValueType(); 7488 if (!TLI.isVectorClearMaskLegal(Indices, RVT)) 7489 return SDValue(); 7490 7491 // Return the new VECTOR_SHUFFLE node. 7492 EVT EltVT = RVT.getVectorElementType(); 7493 SmallVector<SDValue,8> ZeroOps(RVT.getVectorNumElements(), 7494 DAG.getConstant(0, EltVT)); 7495 SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 7496 RVT, &ZeroOps[0], ZeroOps.size()); 7497 LHS = DAG.getNode(ISD::BITCAST, dl, RVT, LHS); 7498 SDValue Shuf = DAG.getVectorShuffle(RVT, dl, LHS, Zero, &Indices[0]); 7499 return DAG.getNode(ISD::BITCAST, dl, VT, Shuf); 7500 } 7501 } 7502 7503 return SDValue(); 7504} 7505 7506/// SimplifyVBinOp - Visit a binary vector operation, like ADD. 7507SDValue DAGCombiner::SimplifyVBinOp(SDNode *N) { 7508 // After legalize, the target may be depending on adds and other 7509 // binary ops to provide legal ways to construct constants or other 7510 // things. Simplifying them may result in a loss of legality. 7511 if (LegalOperations) return SDValue(); 7512 7513 assert(N->getValueType(0).isVector() && 7514 "SimplifyVBinOp only works on vectors!"); 7515 7516 SDValue LHS = N->getOperand(0); 7517 SDValue RHS = N->getOperand(1); 7518 SDValue Shuffle = XformToShuffleWithZero(N); 7519 if (Shuffle.getNode()) return Shuffle; 7520 7521 // If the LHS and RHS are BUILD_VECTOR nodes, see if we can constant fold 7522 // this operation. 7523 if (LHS.getOpcode() == ISD::BUILD_VECTOR && 7524 RHS.getOpcode() == ISD::BUILD_VECTOR) { 7525 SmallVector<SDValue, 8> Ops; 7526 for (unsigned i = 0, e = LHS.getNumOperands(); i != e; ++i) { 7527 SDValue LHSOp = LHS.getOperand(i); 7528 SDValue RHSOp = RHS.getOperand(i); 7529 // If these two elements can't be folded, bail out. 7530 if ((LHSOp.getOpcode() != ISD::UNDEF && 7531 LHSOp.getOpcode() != ISD::Constant && 7532 LHSOp.getOpcode() != ISD::ConstantFP) || 7533 (RHSOp.getOpcode() != ISD::UNDEF && 7534 RHSOp.getOpcode() != ISD::Constant && 7535 RHSOp.getOpcode() != ISD::ConstantFP)) 7536 break; 7537 7538 // Can't fold divide by zero. 7539 if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV || 7540 N->getOpcode() == ISD::FDIV) { 7541 if ((RHSOp.getOpcode() == ISD::Constant && 7542 cast<ConstantSDNode>(RHSOp.getNode())->isNullValue()) || 7543 (RHSOp.getOpcode() == ISD::ConstantFP && 7544 cast<ConstantFPSDNode>(RHSOp.getNode())->getValueAPF().isZero())) 7545 break; 7546 } 7547 7548 EVT VT = LHSOp.getValueType(); 7549 EVT RVT = RHSOp.getValueType(); 7550 if (RVT != VT) { 7551 // Integer BUILD_VECTOR operands may have types larger than the element 7552 // size (e.g., when the element type is not legal). Prior to type 7553 // legalization, the types may not match between the two BUILD_VECTORS. 7554 // Truncate one of the operands to make them match. 7555 if (RVT.getSizeInBits() > VT.getSizeInBits()) { 7556 RHSOp = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, RHSOp); 7557 } else { 7558 LHSOp = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), RVT, LHSOp); 7559 VT = RVT; 7560 } 7561 } 7562 SDValue FoldOp = DAG.getNode(N->getOpcode(), LHS.getDebugLoc(), VT, 7563 LHSOp, RHSOp); 7564 if (FoldOp.getOpcode() != ISD::UNDEF && 7565 FoldOp.getOpcode() != ISD::Constant && 7566 FoldOp.getOpcode() != ISD::ConstantFP) 7567 break; 7568 Ops.push_back(FoldOp); 7569 AddToWorkList(FoldOp.getNode()); 7570 } 7571 7572 if (Ops.size() == LHS.getNumOperands()) 7573 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 7574 LHS.getValueType(), &Ops[0], Ops.size()); 7575 } 7576 7577 return SDValue(); 7578} 7579 7580SDValue DAGCombiner::SimplifySelect(DebugLoc DL, SDValue N0, 7581 SDValue N1, SDValue N2){ 7582 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!"); 7583 7584 SDValue SCC = SimplifySelectCC(DL, N0.getOperand(0), N0.getOperand(1), N1, N2, 7585 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 7586 7587 // If we got a simplified select_cc node back from SimplifySelectCC, then 7588 // break it down into a new SETCC node, and a new SELECT node, and then return 7589 // the SELECT node, since we were called with a SELECT node. 7590 if (SCC.getNode()) { 7591 // Check to see if we got a select_cc back (to turn into setcc/select). 7592 // Otherwise, just return whatever node we got back, like fabs. 7593 if (SCC.getOpcode() == ISD::SELECT_CC) { 7594 SDValue SETCC = DAG.getNode(ISD::SETCC, N0.getDebugLoc(), 7595 N0.getValueType(), 7596 SCC.getOperand(0), SCC.getOperand(1), 7597 SCC.getOperand(4)); 7598 AddToWorkList(SETCC.getNode()); 7599 return DAG.getNode(ISD::SELECT, SCC.getDebugLoc(), SCC.getValueType(), 7600 SCC.getOperand(2), SCC.getOperand(3), SETCC); 7601 } 7602 7603 return SCC; 7604 } 7605 return SDValue(); 7606} 7607 7608/// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS 7609/// are the two values being selected between, see if we can simplify the 7610/// select. Callers of this should assume that TheSelect is deleted if this 7611/// returns true. As such, they should return the appropriate thing (e.g. the 7612/// node) back to the top-level of the DAG combiner loop to avoid it being 7613/// looked at. 7614bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDValue LHS, 7615 SDValue RHS) { 7616 7617 // Cannot simplify select with vector condition 7618 if (TheSelect->getOperand(0).getValueType().isVector()) return false; 7619 7620 // If this is a select from two identical things, try to pull the operation 7621 // through the select. 7622 if (LHS.getOpcode() != RHS.getOpcode() || 7623 !LHS.hasOneUse() || !RHS.hasOneUse()) 7624 return false; 7625 7626 // If this is a load and the token chain is identical, replace the select 7627 // of two loads with a load through a select of the address to load from. 7628 // This triggers in things like "select bool X, 10.0, 123.0" after the FP 7629 // constants have been dropped into the constant pool. 7630 if (LHS.getOpcode() == ISD::LOAD) { 7631 LoadSDNode *LLD = cast<LoadSDNode>(LHS); 7632 LoadSDNode *RLD = cast<LoadSDNode>(RHS); 7633 7634 // Token chains must be identical. 7635 if (LHS.getOperand(0) != RHS.getOperand(0) || 7636 // Do not let this transformation reduce the number of volatile loads. 7637 LLD->isVolatile() || RLD->isVolatile() || 7638 // If this is an EXTLOAD, the VT's must match. 7639 LLD->getMemoryVT() != RLD->getMemoryVT() || 7640 // If this is an EXTLOAD, the kind of extension must match. 7641 (LLD->getExtensionType() != RLD->getExtensionType() && 7642 // The only exception is if one of the extensions is anyext. 7643 LLD->getExtensionType() != ISD::EXTLOAD && 7644 RLD->getExtensionType() != ISD::EXTLOAD) || 7645 // FIXME: this discards src value information. This is 7646 // over-conservative. It would be beneficial to be able to remember 7647 // both potential memory locations. Since we are discarding 7648 // src value info, don't do the transformation if the memory 7649 // locations are not in the default address space. 7650 LLD->getPointerInfo().getAddrSpace() != 0 || 7651 RLD->getPointerInfo().getAddrSpace() != 0) 7652 return false; 7653 7654 // Check that the select condition doesn't reach either load. If so, 7655 // folding this will induce a cycle into the DAG. If not, this is safe to 7656 // xform, so create a select of the addresses. 7657 SDValue Addr; 7658 if (TheSelect->getOpcode() == ISD::SELECT) { 7659 SDNode *CondNode = TheSelect->getOperand(0).getNode(); 7660 if ((LLD->hasAnyUseOfValue(1) && LLD->isPredecessorOf(CondNode)) || 7661 (RLD->hasAnyUseOfValue(1) && RLD->isPredecessorOf(CondNode))) 7662 return false; 7663 Addr = DAG.getNode(ISD::SELECT, TheSelect->getDebugLoc(), 7664 LLD->getBasePtr().getValueType(), 7665 TheSelect->getOperand(0), LLD->getBasePtr(), 7666 RLD->getBasePtr()); 7667 } else { // Otherwise SELECT_CC 7668 SDNode *CondLHS = TheSelect->getOperand(0).getNode(); 7669 SDNode *CondRHS = TheSelect->getOperand(1).getNode(); 7670 7671 if ((LLD->hasAnyUseOfValue(1) && 7672 (LLD->isPredecessorOf(CondLHS) || LLD->isPredecessorOf(CondRHS))) || 7673 (LLD->hasAnyUseOfValue(1) && 7674 (LLD->isPredecessorOf(CondLHS) || LLD->isPredecessorOf(CondRHS)))) 7675 return false; 7676 7677 Addr = DAG.getNode(ISD::SELECT_CC, TheSelect->getDebugLoc(), 7678 LLD->getBasePtr().getValueType(), 7679 TheSelect->getOperand(0), 7680 TheSelect->getOperand(1), 7681 LLD->getBasePtr(), RLD->getBasePtr(), 7682 TheSelect->getOperand(4)); 7683 } 7684 7685 SDValue Load; 7686 if (LLD->getExtensionType() == ISD::NON_EXTLOAD) { 7687 Load = DAG.getLoad(TheSelect->getValueType(0), 7688 TheSelect->getDebugLoc(), 7689 // FIXME: Discards pointer info. 7690 LLD->getChain(), Addr, MachinePointerInfo(), 7691 LLD->isVolatile(), LLD->isNonTemporal(), 7692 LLD->isInvariant(), LLD->getAlignment()); 7693 } else { 7694 Load = DAG.getExtLoad(LLD->getExtensionType() == ISD::EXTLOAD ? 7695 RLD->getExtensionType() : LLD->getExtensionType(), 7696 TheSelect->getDebugLoc(), 7697 TheSelect->getValueType(0), 7698 // FIXME: Discards pointer info. 7699 LLD->getChain(), Addr, MachinePointerInfo(), 7700 LLD->getMemoryVT(), LLD->isVolatile(), 7701 LLD->isNonTemporal(), LLD->getAlignment()); 7702 } 7703 7704 // Users of the select now use the result of the load. 7705 CombineTo(TheSelect, Load); 7706 7707 // Users of the old loads now use the new load's chain. We know the 7708 // old-load value is dead now. 7709 CombineTo(LHS.getNode(), Load.getValue(0), Load.getValue(1)); 7710 CombineTo(RHS.getNode(), Load.getValue(0), Load.getValue(1)); 7711 return true; 7712 } 7713 7714 return false; 7715} 7716 7717/// SimplifySelectCC - Simplify an expression of the form (N0 cond N1) ? N2 : N3 7718/// where 'cond' is the comparison specified by CC. 7719SDValue DAGCombiner::SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, 7720 SDValue N2, SDValue N3, 7721 ISD::CondCode CC, bool NotExtCompare) { 7722 // (x ? y : y) -> y. 7723 if (N2 == N3) return N2; 7724 7725 EVT VT = N2.getValueType(); 7726 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 7727 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode()); 7728 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.getNode()); 7729 7730 // Determine if the condition we're dealing with is constant 7731 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()), 7732 N0, N1, CC, DL, false); 7733 if (SCC.getNode()) AddToWorkList(SCC.getNode()); 7734 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode()); 7735 7736 // fold select_cc true, x, y -> x 7737 if (SCCC && !SCCC->isNullValue()) 7738 return N2; 7739 // fold select_cc false, x, y -> y 7740 if (SCCC && SCCC->isNullValue()) 7741 return N3; 7742 7743 // Check to see if we can simplify the select into an fabs node 7744 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) { 7745 // Allow either -0.0 or 0.0 7746 if (CFP->getValueAPF().isZero()) { 7747 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs 7748 if ((CC == ISD::SETGE || CC == ISD::SETGT) && 7749 N0 == N2 && N3.getOpcode() == ISD::FNEG && 7750 N2 == N3.getOperand(0)) 7751 return DAG.getNode(ISD::FABS, DL, VT, N0); 7752 7753 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs 7754 if ((CC == ISD::SETLT || CC == ISD::SETLE) && 7755 N0 == N3 && N2.getOpcode() == ISD::FNEG && 7756 N2.getOperand(0) == N3) 7757 return DAG.getNode(ISD::FABS, DL, VT, N3); 7758 } 7759 } 7760 7761 // Turn "(a cond b) ? 1.0f : 2.0f" into "load (tmp + ((a cond b) ? 0 : 4)" 7762 // where "tmp" is a constant pool entry containing an array with 1.0 and 2.0 7763 // in it. This is a win when the constant is not otherwise available because 7764 // it replaces two constant pool loads with one. We only do this if the FP 7765 // type is known to be legal, because if it isn't, then we are before legalize 7766 // types an we want the other legalization to happen first (e.g. to avoid 7767 // messing with soft float) and if the ConstantFP is not legal, because if 7768 // it is legal, we may not need to store the FP constant in a constant pool. 7769 if (ConstantFPSDNode *TV = dyn_cast<ConstantFPSDNode>(N2)) 7770 if (ConstantFPSDNode *FV = dyn_cast<ConstantFPSDNode>(N3)) { 7771 if (TLI.isTypeLegal(N2.getValueType()) && 7772 (TLI.getOperationAction(ISD::ConstantFP, N2.getValueType()) != 7773 TargetLowering::Legal) && 7774 // If both constants have multiple uses, then we won't need to do an 7775 // extra load, they are likely around in registers for other users. 7776 (TV->hasOneUse() || FV->hasOneUse())) { 7777 Constant *Elts[] = { 7778 const_cast<ConstantFP*>(FV->getConstantFPValue()), 7779 const_cast<ConstantFP*>(TV->getConstantFPValue()) 7780 }; 7781 Type *FPTy = Elts[0]->getType(); 7782 const TargetData &TD = *TLI.getTargetData(); 7783 7784 // Create a ConstantArray of the two constants. 7785 Constant *CA = ConstantArray::get(ArrayType::get(FPTy, 2), Elts); 7786 SDValue CPIdx = DAG.getConstantPool(CA, TLI.getPointerTy(), 7787 TD.getPrefTypeAlignment(FPTy)); 7788 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 7789 7790 // Get the offsets to the 0 and 1 element of the array so that we can 7791 // select between them. 7792 SDValue Zero = DAG.getIntPtrConstant(0); 7793 unsigned EltSize = (unsigned)TD.getTypeAllocSize(Elts[0]->getType()); 7794 SDValue One = DAG.getIntPtrConstant(EltSize); 7795 7796 SDValue Cond = DAG.getSetCC(DL, 7797 TLI.getSetCCResultType(N0.getValueType()), 7798 N0, N1, CC); 7799 AddToWorkList(Cond.getNode()); 7800 SDValue CstOffset = DAG.getNode(ISD::SELECT, DL, Zero.getValueType(), 7801 Cond, One, Zero); 7802 AddToWorkList(CstOffset.getNode()); 7803 CPIdx = DAG.getNode(ISD::ADD, DL, TLI.getPointerTy(), CPIdx, 7804 CstOffset); 7805 AddToWorkList(CPIdx.getNode()); 7806 return DAG.getLoad(TV->getValueType(0), DL, DAG.getEntryNode(), CPIdx, 7807 MachinePointerInfo::getConstantPool(), false, 7808 false, false, Alignment); 7809 7810 } 7811 } 7812 7813 // Check to see if we can perform the "gzip trick", transforming 7814 // (select_cc setlt X, 0, A, 0) -> (and (sra X, (sub size(X), 1), A) 7815 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT && 7816 (N1C->isNullValue() || // (a < 0) ? b : 0 7817 (N1C->getAPIntValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0 7818 EVT XType = N0.getValueType(); 7819 EVT AType = N2.getValueType(); 7820 if (XType.bitsGE(AType)) { 7821 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a 7822 // single-bit constant. 7823 if (N2C && ((N2C->getAPIntValue() & (N2C->getAPIntValue()-1)) == 0)) { 7824 unsigned ShCtV = N2C->getAPIntValue().logBase2(); 7825 ShCtV = XType.getSizeInBits()-ShCtV-1; 7826 SDValue ShCt = DAG.getConstant(ShCtV, 7827 getShiftAmountTy(N0.getValueType())); 7828 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), 7829 XType, N0, ShCt); 7830 AddToWorkList(Shift.getNode()); 7831 7832 if (XType.bitsGT(AType)) { 7833 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift); 7834 AddToWorkList(Shift.getNode()); 7835 } 7836 7837 return DAG.getNode(ISD::AND, DL, AType, Shift, N2); 7838 } 7839 7840 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), 7841 XType, N0, 7842 DAG.getConstant(XType.getSizeInBits()-1, 7843 getShiftAmountTy(N0.getValueType()))); 7844 AddToWorkList(Shift.getNode()); 7845 7846 if (XType.bitsGT(AType)) { 7847 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift); 7848 AddToWorkList(Shift.getNode()); 7849 } 7850 7851 return DAG.getNode(ISD::AND, DL, AType, Shift, N2); 7852 } 7853 } 7854 7855 // fold (select_cc seteq (and x, y), 0, 0, A) -> (and (shr (shl x)) A) 7856 // where y is has a single bit set. 7857 // A plaintext description would be, we can turn the SELECT_CC into an AND 7858 // when the condition can be materialized as an all-ones register. Any 7859 // single bit-test can be materialized as an all-ones register with 7860 // shift-left and shift-right-arith. 7861 if (CC == ISD::SETEQ && N0->getOpcode() == ISD::AND && 7862 N0->getValueType(0) == VT && 7863 N1C && N1C->isNullValue() && 7864 N2C && N2C->isNullValue()) { 7865 SDValue AndLHS = N0->getOperand(0); 7866 ConstantSDNode *ConstAndRHS = dyn_cast<ConstantSDNode>(N0->getOperand(1)); 7867 if (ConstAndRHS && ConstAndRHS->getAPIntValue().countPopulation() == 1) { 7868 // Shift the tested bit over the sign bit. 7869 APInt AndMask = ConstAndRHS->getAPIntValue(); 7870 SDValue ShlAmt = 7871 DAG.getConstant(AndMask.countLeadingZeros(), 7872 getShiftAmountTy(AndLHS.getValueType())); 7873 SDValue Shl = DAG.getNode(ISD::SHL, N0.getDebugLoc(), VT, AndLHS, ShlAmt); 7874 7875 // Now arithmetic right shift it all the way over, so the result is either 7876 // all-ones, or zero. 7877 SDValue ShrAmt = 7878 DAG.getConstant(AndMask.getBitWidth()-1, 7879 getShiftAmountTy(Shl.getValueType())); 7880 SDValue Shr = DAG.getNode(ISD::SRA, N0.getDebugLoc(), VT, Shl, ShrAmt); 7881 7882 return DAG.getNode(ISD::AND, DL, VT, Shr, N3); 7883 } 7884 } 7885 7886 // fold select C, 16, 0 -> shl C, 4 7887 if (N2C && N3C && N3C->isNullValue() && N2C->getAPIntValue().isPowerOf2() && 7888 TLI.getBooleanContents(N0.getValueType().isVector()) == 7889 TargetLowering::ZeroOrOneBooleanContent) { 7890 7891 // If the caller doesn't want us to simplify this into a zext of a compare, 7892 // don't do it. 7893 if (NotExtCompare && N2C->getAPIntValue() == 1) 7894 return SDValue(); 7895 7896 // Get a SetCC of the condition 7897 // FIXME: Should probably make sure that setcc is legal if we ever have a 7898 // target where it isn't. 7899 SDValue Temp, SCC; 7900 // cast from setcc result type to select result type 7901 if (LegalTypes) { 7902 SCC = DAG.getSetCC(DL, TLI.getSetCCResultType(N0.getValueType()), 7903 N0, N1, CC); 7904 if (N2.getValueType().bitsLT(SCC.getValueType())) 7905 Temp = DAG.getZeroExtendInReg(SCC, N2.getDebugLoc(), N2.getValueType()); 7906 else 7907 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(), 7908 N2.getValueType(), SCC); 7909 } else { 7910 SCC = DAG.getSetCC(N0.getDebugLoc(), MVT::i1, N0, N1, CC); 7911 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(), 7912 N2.getValueType(), SCC); 7913 } 7914 7915 AddToWorkList(SCC.getNode()); 7916 AddToWorkList(Temp.getNode()); 7917 7918 if (N2C->getAPIntValue() == 1) 7919 return Temp; 7920 7921 // shl setcc result by log2 n2c 7922 return DAG.getNode(ISD::SHL, DL, N2.getValueType(), Temp, 7923 DAG.getConstant(N2C->getAPIntValue().logBase2(), 7924 getShiftAmountTy(Temp.getValueType()))); 7925 } 7926 7927 // Check to see if this is the equivalent of setcc 7928 // FIXME: Turn all of these into setcc if setcc if setcc is legal 7929 // otherwise, go ahead with the folds. 7930 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getAPIntValue() == 1ULL)) { 7931 EVT XType = N0.getValueType(); 7932 if (!LegalOperations || 7933 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(XType))) { 7934 SDValue Res = DAG.getSetCC(DL, TLI.getSetCCResultType(XType), N0, N1, CC); 7935 if (Res.getValueType() != VT) 7936 Res = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, Res); 7937 return Res; 7938 } 7939 7940 // fold (seteq X, 0) -> (srl (ctlz X, log2(size(X)))) 7941 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ && 7942 (!LegalOperations || 7943 TLI.isOperationLegal(ISD::CTLZ, XType))) { 7944 SDValue Ctlz = DAG.getNode(ISD::CTLZ, N0.getDebugLoc(), XType, N0); 7945 return DAG.getNode(ISD::SRL, DL, XType, Ctlz, 7946 DAG.getConstant(Log2_32(XType.getSizeInBits()), 7947 getShiftAmountTy(Ctlz.getValueType()))); 7948 } 7949 // fold (setgt X, 0) -> (srl (and (-X, ~X), size(X)-1)) 7950 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) { 7951 SDValue NegN0 = DAG.getNode(ISD::SUB, N0.getDebugLoc(), 7952 XType, DAG.getConstant(0, XType), N0); 7953 SDValue NotN0 = DAG.getNOT(N0.getDebugLoc(), N0, XType); 7954 return DAG.getNode(ISD::SRL, DL, XType, 7955 DAG.getNode(ISD::AND, DL, XType, NegN0, NotN0), 7956 DAG.getConstant(XType.getSizeInBits()-1, 7957 getShiftAmountTy(XType))); 7958 } 7959 // fold (setgt X, -1) -> (xor (srl (X, size(X)-1), 1)) 7960 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) { 7961 SDValue Sign = DAG.getNode(ISD::SRL, N0.getDebugLoc(), XType, N0, 7962 DAG.getConstant(XType.getSizeInBits()-1, 7963 getShiftAmountTy(N0.getValueType()))); 7964 return DAG.getNode(ISD::XOR, DL, XType, Sign, DAG.getConstant(1, XType)); 7965 } 7966 } 7967 7968 // Check to see if this is an integer abs. 7969 // select_cc setg[te] X, 0, X, -X -> 7970 // select_cc setgt X, -1, X, -X -> 7971 // select_cc setl[te] X, 0, -X, X -> 7972 // select_cc setlt X, 1, -X, X -> 7973 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 7974 if (N1C) { 7975 ConstantSDNode *SubC = NULL; 7976 if (((N1C->isNullValue() && (CC == ISD::SETGT || CC == ISD::SETGE)) || 7977 (N1C->isAllOnesValue() && CC == ISD::SETGT)) && 7978 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1)) 7979 SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0)); 7980 else if (((N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE)) || 7981 (N1C->isOne() && CC == ISD::SETLT)) && 7982 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1)) 7983 SubC = dyn_cast<ConstantSDNode>(N2.getOperand(0)); 7984 7985 EVT XType = N0.getValueType(); 7986 if (SubC && SubC->isNullValue() && XType.isInteger()) { 7987 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), XType, 7988 N0, 7989 DAG.getConstant(XType.getSizeInBits()-1, 7990 getShiftAmountTy(N0.getValueType()))); 7991 SDValue Add = DAG.getNode(ISD::ADD, N0.getDebugLoc(), 7992 XType, N0, Shift); 7993 AddToWorkList(Shift.getNode()); 7994 AddToWorkList(Add.getNode()); 7995 return DAG.getNode(ISD::XOR, DL, XType, Add, Shift); 7996 } 7997 } 7998 7999 return SDValue(); 8000} 8001 8002/// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC. 8003SDValue DAGCombiner::SimplifySetCC(EVT VT, SDValue N0, 8004 SDValue N1, ISD::CondCode Cond, 8005 DebugLoc DL, bool foldBooleans) { 8006 TargetLowering::DAGCombinerInfo 8007 DagCombineInfo(DAG, !LegalTypes, !LegalOperations, false, this); 8008 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo, DL); 8009} 8010 8011/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 8012/// return a DAG expression to select that will generate the same value by 8013/// multiplying by a magic number. See: 8014/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 8015SDValue DAGCombiner::BuildSDIV(SDNode *N) { 8016 std::vector<SDNode*> Built; 8017 SDValue S = TLI.BuildSDIV(N, DAG, LegalOperations, &Built); 8018 8019 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 8020 ii != ee; ++ii) 8021 AddToWorkList(*ii); 8022 return S; 8023} 8024 8025/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 8026/// return a DAG expression to select that will generate the same value by 8027/// multiplying by a magic number. See: 8028/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 8029SDValue DAGCombiner::BuildUDIV(SDNode *N) { 8030 std::vector<SDNode*> Built; 8031 SDValue S = TLI.BuildUDIV(N, DAG, LegalOperations, &Built); 8032 8033 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 8034 ii != ee; ++ii) 8035 AddToWorkList(*ii); 8036 return S; 8037} 8038 8039/// FindBaseOffset - Return true if base is a frame index, which is known not 8040// to alias with anything but itself. Provides base object and offset as 8041// results. 8042static bool FindBaseOffset(SDValue Ptr, SDValue &Base, int64_t &Offset, 8043 const GlobalValue *&GV, void *&CV) { 8044 // Assume it is a primitive operation. 8045 Base = Ptr; Offset = 0; GV = 0; CV = 0; 8046 8047 // If it's an adding a simple constant then integrate the offset. 8048 if (Base.getOpcode() == ISD::ADD) { 8049 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) { 8050 Base = Base.getOperand(0); 8051 Offset += C->getZExtValue(); 8052 } 8053 } 8054 8055 // Return the underlying GlobalValue, and update the Offset. Return false 8056 // for GlobalAddressSDNode since the same GlobalAddress may be represented 8057 // by multiple nodes with different offsets. 8058 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Base)) { 8059 GV = G->getGlobal(); 8060 Offset += G->getOffset(); 8061 return false; 8062 } 8063 8064 // Return the underlying Constant value, and update the Offset. Return false 8065 // for ConstantSDNodes since the same constant pool entry may be represented 8066 // by multiple nodes with different offsets. 8067 if (ConstantPoolSDNode *C = dyn_cast<ConstantPoolSDNode>(Base)) { 8068 CV = C->isMachineConstantPoolEntry() ? (void *)C->getMachineCPVal() 8069 : (void *)C->getConstVal(); 8070 Offset += C->getOffset(); 8071 return false; 8072 } 8073 // If it's any of the following then it can't alias with anything but itself. 8074 return isa<FrameIndexSDNode>(Base); 8075} 8076 8077/// isAlias - Return true if there is any possibility that the two addresses 8078/// overlap. 8079bool DAGCombiner::isAlias(SDValue Ptr1, int64_t Size1, 8080 const Value *SrcValue1, int SrcValueOffset1, 8081 unsigned SrcValueAlign1, 8082 const MDNode *TBAAInfo1, 8083 SDValue Ptr2, int64_t Size2, 8084 const Value *SrcValue2, int SrcValueOffset2, 8085 unsigned SrcValueAlign2, 8086 const MDNode *TBAAInfo2) const { 8087 // If they are the same then they must be aliases. 8088 if (Ptr1 == Ptr2) return true; 8089 8090 // Gather base node and offset information. 8091 SDValue Base1, Base2; 8092 int64_t Offset1, Offset2; 8093 const GlobalValue *GV1, *GV2; 8094 void *CV1, *CV2; 8095 bool isFrameIndex1 = FindBaseOffset(Ptr1, Base1, Offset1, GV1, CV1); 8096 bool isFrameIndex2 = FindBaseOffset(Ptr2, Base2, Offset2, GV2, CV2); 8097 8098 // If they have a same base address then check to see if they overlap. 8099 if (Base1 == Base2 || (GV1 && (GV1 == GV2)) || (CV1 && (CV1 == CV2))) 8100 return !((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1); 8101 8102 // It is possible for different frame indices to alias each other, mostly 8103 // when tail call optimization reuses return address slots for arguments. 8104 // To catch this case, look up the actual index of frame indices to compute 8105 // the real alias relationship. 8106 if (isFrameIndex1 && isFrameIndex2) { 8107 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 8108 Offset1 += MFI->getObjectOffset(cast<FrameIndexSDNode>(Base1)->getIndex()); 8109 Offset2 += MFI->getObjectOffset(cast<FrameIndexSDNode>(Base2)->getIndex()); 8110 return !((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1); 8111 } 8112 8113 // Otherwise, if we know what the bases are, and they aren't identical, then 8114 // we know they cannot alias. 8115 if ((isFrameIndex1 || CV1 || GV1) && (isFrameIndex2 || CV2 || GV2)) 8116 return false; 8117 8118 // If we know required SrcValue1 and SrcValue2 have relatively large alignment 8119 // compared to the size and offset of the access, we may be able to prove they 8120 // do not alias. This check is conservative for now to catch cases created by 8121 // splitting vector types. 8122 if ((SrcValueAlign1 == SrcValueAlign2) && 8123 (SrcValueOffset1 != SrcValueOffset2) && 8124 (Size1 == Size2) && (SrcValueAlign1 > Size1)) { 8125 int64_t OffAlign1 = SrcValueOffset1 % SrcValueAlign1; 8126 int64_t OffAlign2 = SrcValueOffset2 % SrcValueAlign1; 8127 8128 // There is no overlap between these relatively aligned accesses of similar 8129 // size, return no alias. 8130 if ((OffAlign1 + Size1) <= OffAlign2 || (OffAlign2 + Size2) <= OffAlign1) 8131 return false; 8132 } 8133 8134 if (CombinerGlobalAA) { 8135 // Use alias analysis information. 8136 int64_t MinOffset = std::min(SrcValueOffset1, SrcValueOffset2); 8137 int64_t Overlap1 = Size1 + SrcValueOffset1 - MinOffset; 8138 int64_t Overlap2 = Size2 + SrcValueOffset2 - MinOffset; 8139 AliasAnalysis::AliasResult AAResult = 8140 AA.alias(AliasAnalysis::Location(SrcValue1, Overlap1, TBAAInfo1), 8141 AliasAnalysis::Location(SrcValue2, Overlap2, TBAAInfo2)); 8142 if (AAResult == AliasAnalysis::NoAlias) 8143 return false; 8144 } 8145 8146 // Otherwise we have to assume they alias. 8147 return true; 8148} 8149 8150/// FindAliasInfo - Extracts the relevant alias information from the memory 8151/// node. Returns true if the operand was a load. 8152bool DAGCombiner::FindAliasInfo(SDNode *N, 8153 SDValue &Ptr, int64_t &Size, 8154 const Value *&SrcValue, 8155 int &SrcValueOffset, 8156 unsigned &SrcValueAlign, 8157 const MDNode *&TBAAInfo) const { 8158 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 8159 Ptr = LD->getBasePtr(); 8160 Size = LD->getMemoryVT().getSizeInBits() >> 3; 8161 SrcValue = LD->getSrcValue(); 8162 SrcValueOffset = LD->getSrcValueOffset(); 8163 SrcValueAlign = LD->getOriginalAlignment(); 8164 TBAAInfo = LD->getTBAAInfo(); 8165 return true; 8166 } 8167 if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 8168 Ptr = ST->getBasePtr(); 8169 Size = ST->getMemoryVT().getSizeInBits() >> 3; 8170 SrcValue = ST->getSrcValue(); 8171 SrcValueOffset = ST->getSrcValueOffset(); 8172 SrcValueAlign = ST->getOriginalAlignment(); 8173 TBAAInfo = ST->getTBAAInfo(); 8174 return false; 8175 } 8176 llvm_unreachable("FindAliasInfo expected a memory operand"); 8177} 8178 8179/// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 8180/// looking for aliasing nodes and adding them to the Aliases vector. 8181void DAGCombiner::GatherAllAliases(SDNode *N, SDValue OriginalChain, 8182 SmallVector<SDValue, 8> &Aliases) { 8183 SmallVector<SDValue, 8> Chains; // List of chains to visit. 8184 SmallPtrSet<SDNode *, 16> Visited; // Visited node set. 8185 8186 // Get alias information for node. 8187 SDValue Ptr; 8188 int64_t Size; 8189 const Value *SrcValue; 8190 int SrcValueOffset; 8191 unsigned SrcValueAlign; 8192 const MDNode *SrcTBAAInfo; 8193 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset, 8194 SrcValueAlign, SrcTBAAInfo); 8195 8196 // Starting off. 8197 Chains.push_back(OriginalChain); 8198 unsigned Depth = 0; 8199 8200 // Look at each chain and determine if it is an alias. If so, add it to the 8201 // aliases list. If not, then continue up the chain looking for the next 8202 // candidate. 8203 while (!Chains.empty()) { 8204 SDValue Chain = Chains.back(); 8205 Chains.pop_back(); 8206 8207 // For TokenFactor nodes, look at each operand and only continue up the 8208 // chain until we find two aliases. If we've seen two aliases, assume we'll 8209 // find more and revert to original chain since the xform is unlikely to be 8210 // profitable. 8211 // 8212 // FIXME: The depth check could be made to return the last non-aliasing 8213 // chain we found before we hit a tokenfactor rather than the original 8214 // chain. 8215 if (Depth > 6 || Aliases.size() == 2) { 8216 Aliases.clear(); 8217 Aliases.push_back(OriginalChain); 8218 break; 8219 } 8220 8221 // Don't bother if we've been before. 8222 if (!Visited.insert(Chain.getNode())) 8223 continue; 8224 8225 switch (Chain.getOpcode()) { 8226 case ISD::EntryToken: 8227 // Entry token is ideal chain operand, but handled in FindBetterChain. 8228 break; 8229 8230 case ISD::LOAD: 8231 case ISD::STORE: { 8232 // Get alias information for Chain. 8233 SDValue OpPtr; 8234 int64_t OpSize; 8235 const Value *OpSrcValue; 8236 int OpSrcValueOffset; 8237 unsigned OpSrcValueAlign; 8238 const MDNode *OpSrcTBAAInfo; 8239 bool IsOpLoad = FindAliasInfo(Chain.getNode(), OpPtr, OpSize, 8240 OpSrcValue, OpSrcValueOffset, 8241 OpSrcValueAlign, 8242 OpSrcTBAAInfo); 8243 8244 // If chain is alias then stop here. 8245 if (!(IsLoad && IsOpLoad) && 8246 isAlias(Ptr, Size, SrcValue, SrcValueOffset, SrcValueAlign, 8247 SrcTBAAInfo, 8248 OpPtr, OpSize, OpSrcValue, OpSrcValueOffset, 8249 OpSrcValueAlign, OpSrcTBAAInfo)) { 8250 Aliases.push_back(Chain); 8251 } else { 8252 // Look further up the chain. 8253 Chains.push_back(Chain.getOperand(0)); 8254 ++Depth; 8255 } 8256 break; 8257 } 8258 8259 case ISD::TokenFactor: 8260 // We have to check each of the operands of the token factor for "small" 8261 // token factors, so we queue them up. Adding the operands to the queue 8262 // (stack) in reverse order maintains the original order and increases the 8263 // likelihood that getNode will find a matching token factor (CSE.) 8264 if (Chain.getNumOperands() > 16) { 8265 Aliases.push_back(Chain); 8266 break; 8267 } 8268 for (unsigned n = Chain.getNumOperands(); n;) 8269 Chains.push_back(Chain.getOperand(--n)); 8270 ++Depth; 8271 break; 8272 8273 default: 8274 // For all other instructions we will just have to take what we can get. 8275 Aliases.push_back(Chain); 8276 break; 8277 } 8278 } 8279} 8280 8281/// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking 8282/// for a better chain (aliasing node.) 8283SDValue DAGCombiner::FindBetterChain(SDNode *N, SDValue OldChain) { 8284 SmallVector<SDValue, 8> Aliases; // Ops for replacing token factor. 8285 8286 // Accumulate all the aliases to this node. 8287 GatherAllAliases(N, OldChain, Aliases); 8288 8289 // If no operands then chain to entry token. 8290 if (Aliases.size() == 0) 8291 return DAG.getEntryNode(); 8292 8293 // If a single operand then chain to it. We don't need to revisit it. 8294 if (Aliases.size() == 1) 8295 return Aliases[0]; 8296 8297 // Construct a custom tailored token factor. 8298 return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, 8299 &Aliases[0], Aliases.size()); 8300} 8301 8302// SelectionDAG::Combine - This is the entry point for the file. 8303// 8304void SelectionDAG::Combine(CombineLevel Level, AliasAnalysis &AA, 8305 CodeGenOpt::Level OptLevel) { 8306 /// run - This is the main entry point to this class. 8307 /// 8308 DAGCombiner(*this, AA, OptLevel).Run(Level); 8309} 8310