DAGCombiner.cpp revision 731d348166792bb9846022a82f7712c7bcec8f30
1//===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by Nate Begeman and is distributed under the 6// University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run 11// both before and after the DAG is legalized. 12// 13// FIXME: Missing folds 14// sdiv, udiv, srem, urem (X, const) where X is an integer can be expanded into 15// a sequence of multiplies, shifts, and adds. This should be controlled by 16// some kind of hint from the target that int div is expensive. 17// various folds of mulh[s,u] by constants such as -1, powers of 2, etc. 18// 19// FIXME: Should add a corresponding version of fold AND with 20// ZERO_EXTEND/SIGN_EXTEND by converting them to an ANY_EXTEND node which 21// we don't have yet. 22// 23// FIXME: select C, pow2, pow2 -> something smart 24// FIXME: trunc(select X, Y, Z) -> select X, trunc(Y), trunc(Z) 25// FIXME: Dead stores -> nuke 26// FIXME: shr X, (and Y,31) -> shr X, Y (TRICKY!) 27// FIXME: mul (x, const) -> shifts + adds 28// FIXME: undef values 29// FIXME: make truncate see through SIGN_EXTEND and AND 30// FIXME: (sra (sra x, c1), c2) -> (sra x, c1+c2) 31// FIXME: verify that getNode can't return extends with an operand whose type 32// is >= to that of the extend. 33// FIXME: divide by zero is currently left unfolded. do we want to turn this 34// into an undef? 35// FIXME: select ne (select cc, 1, 0), 0, true, false -> select cc, true, false 36// FIXME: reassociate (X+C)+Y into (X+Y)+C if the inner expression has one use 37// 38//===----------------------------------------------------------------------===// 39 40#define DEBUG_TYPE "dagcombine" 41#include "llvm/ADT/Statistic.h" 42#include "llvm/CodeGen/SelectionDAG.h" 43#include "llvm/Support/Debug.h" 44#include "llvm/Support/MathExtras.h" 45#include "llvm/Target/TargetLowering.h" 46#include <algorithm> 47#include <cmath> 48using namespace llvm; 49 50namespace { 51 Statistic<> NodesCombined ("dagcombiner", "Number of dag nodes combined"); 52 53 class DAGCombiner { 54 SelectionDAG &DAG; 55 TargetLowering &TLI; 56 bool AfterLegalize; 57 58 // Worklist of all of the nodes that need to be simplified. 59 std::vector<SDNode*> WorkList; 60 61 /// AddUsersToWorkList - When an instruction is simplified, add all users of 62 /// the instruction to the work lists because they might get more simplified 63 /// now. 64 /// 65 void AddUsersToWorkList(SDNode *N) { 66 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 67 UI != UE; ++UI) 68 WorkList.push_back(*UI); 69 } 70 71 /// removeFromWorkList - remove all instances of N from the worklist. 72 void removeFromWorkList(SDNode *N) { 73 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N), 74 WorkList.end()); 75 } 76 77 SDOperand CombineTo(SDNode *N, const std::vector<SDOperand> &To) { 78 ++NodesCombined; 79 DEBUG(std::cerr << "\nReplacing "; N->dump(); 80 std::cerr << "\nWith: "; To[0].Val->dump(); 81 std::cerr << " and " << To.size()-1 << " other values\n"); 82 std::vector<SDNode*> NowDead; 83 DAG.ReplaceAllUsesWith(N, To, &NowDead); 84 85 // Push the new nodes and any users onto the worklist 86 for (unsigned i = 0, e = To.size(); i != e; ++i) { 87 WorkList.push_back(To[i].Val); 88 AddUsersToWorkList(To[i].Val); 89 } 90 91 // Nodes can end up on the worklist more than once. Make sure we do 92 // not process a node that has been replaced. 93 removeFromWorkList(N); 94 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 95 removeFromWorkList(NowDead[i]); 96 97 // Finally, since the node is now dead, remove it from the graph. 98 DAG.DeleteNode(N); 99 return SDOperand(N, 0); 100 } 101 102 SDOperand CombineTo(SDNode *N, SDOperand Res) { 103 std::vector<SDOperand> To; 104 To.push_back(Res); 105 return CombineTo(N, To); 106 } 107 108 SDOperand CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1) { 109 std::vector<SDOperand> To; 110 To.push_back(Res0); 111 To.push_back(Res1); 112 return CombineTo(N, To); 113 } 114 115 /// visit - call the node-specific routine that knows how to fold each 116 /// particular type of node. 117 SDOperand visit(SDNode *N); 118 119 // Visitation implementation - Implement dag node combining for different 120 // node types. The semantics are as follows: 121 // Return Value: 122 // SDOperand.Val == 0 - No change was made 123 // SDOperand.Val == N - N was replaced, is dead, and is already handled. 124 // otherwise - N should be replaced by the returned Operand. 125 // 126 SDOperand visitTokenFactor(SDNode *N); 127 SDOperand visitADD(SDNode *N); 128 SDOperand visitSUB(SDNode *N); 129 SDOperand visitMUL(SDNode *N); 130 SDOperand visitSDIV(SDNode *N); 131 SDOperand visitUDIV(SDNode *N); 132 SDOperand visitSREM(SDNode *N); 133 SDOperand visitUREM(SDNode *N); 134 SDOperand visitMULHU(SDNode *N); 135 SDOperand visitMULHS(SDNode *N); 136 SDOperand visitAND(SDNode *N); 137 SDOperand visitOR(SDNode *N); 138 SDOperand visitXOR(SDNode *N); 139 SDOperand visitSHL(SDNode *N); 140 SDOperand visitSRA(SDNode *N); 141 SDOperand visitSRL(SDNode *N); 142 SDOperand visitCTLZ(SDNode *N); 143 SDOperand visitCTTZ(SDNode *N); 144 SDOperand visitCTPOP(SDNode *N); 145 SDOperand visitSELECT(SDNode *N); 146 SDOperand visitSELECT_CC(SDNode *N); 147 SDOperand visitSETCC(SDNode *N); 148 SDOperand visitADD_PARTS(SDNode *N); 149 SDOperand visitSUB_PARTS(SDNode *N); 150 SDOperand visitSIGN_EXTEND(SDNode *N); 151 SDOperand visitZERO_EXTEND(SDNode *N); 152 SDOperand visitSIGN_EXTEND_INREG(SDNode *N); 153 SDOperand visitTRUNCATE(SDNode *N); 154 155 SDOperand visitFADD(SDNode *N); 156 SDOperand visitFSUB(SDNode *N); 157 SDOperand visitFMUL(SDNode *N); 158 SDOperand visitFDIV(SDNode *N); 159 SDOperand visitFREM(SDNode *N); 160 SDOperand visitSINT_TO_FP(SDNode *N); 161 SDOperand visitUINT_TO_FP(SDNode *N); 162 SDOperand visitFP_TO_SINT(SDNode *N); 163 SDOperand visitFP_TO_UINT(SDNode *N); 164 SDOperand visitFP_ROUND(SDNode *N); 165 SDOperand visitFP_ROUND_INREG(SDNode *N); 166 SDOperand visitFP_EXTEND(SDNode *N); 167 SDOperand visitFNEG(SDNode *N); 168 SDOperand visitFABS(SDNode *N); 169 SDOperand visitBRCOND(SDNode *N); 170 SDOperand visitBRCONDTWOWAY(SDNode *N); 171 SDOperand visitBR_CC(SDNode *N); 172 SDOperand visitBRTWOWAY_CC(SDNode *N); 173 174 SDOperand visitLOAD(SDNode *N); 175 SDOperand visitSTORE(SDNode *N); 176 177 bool SimplifySelectOps(SDNode *SELECT, SDOperand LHS, SDOperand RHS); 178 SDOperand SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2); 179 SDOperand SimplifySelectCC(SDOperand N0, SDOperand N1, SDOperand N2, 180 SDOperand N3, ISD::CondCode CC); 181 SDOperand SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1, 182 ISD::CondCode Cond, bool foldBooleans = true); 183 184 SDOperand BuildSDIV(SDNode *N); 185 SDOperand BuildUDIV(SDNode *N); 186public: 187 DAGCombiner(SelectionDAG &D) 188 : DAG(D), TLI(D.getTargetLoweringInfo()), AfterLegalize(false) {} 189 190 /// Run - runs the dag combiner on all nodes in the work list 191 void Run(bool RunningAfterLegalize); 192 }; 193} 194 195struct ms { 196 int64_t m; // magic number 197 int64_t s; // shift amount 198}; 199 200struct mu { 201 uint64_t m; // magic number 202 int64_t a; // add indicator 203 int64_t s; // shift amount 204}; 205 206/// magic - calculate the magic numbers required to codegen an integer sdiv as 207/// a sequence of multiply and shifts. Requires that the divisor not be 0, 1, 208/// or -1. 209static ms magic32(int32_t d) { 210 int32_t p; 211 uint32_t ad, anc, delta, q1, r1, q2, r2, t; 212 const uint32_t two31 = 0x80000000U; 213 struct ms mag; 214 215 ad = abs(d); 216 t = two31 + ((uint32_t)d >> 31); 217 anc = t - 1 - t%ad; // absolute value of nc 218 p = 31; // initialize p 219 q1 = two31/anc; // initialize q1 = 2p/abs(nc) 220 r1 = two31 - q1*anc; // initialize r1 = rem(2p,abs(nc)) 221 q2 = two31/ad; // initialize q2 = 2p/abs(d) 222 r2 = two31 - q2*ad; // initialize r2 = rem(2p,abs(d)) 223 do { 224 p = p + 1; 225 q1 = 2*q1; // update q1 = 2p/abs(nc) 226 r1 = 2*r1; // update r1 = rem(2p/abs(nc)) 227 if (r1 >= anc) { // must be unsigned comparison 228 q1 = q1 + 1; 229 r1 = r1 - anc; 230 } 231 q2 = 2*q2; // update q2 = 2p/abs(d) 232 r2 = 2*r2; // update r2 = rem(2p/abs(d)) 233 if (r2 >= ad) { // must be unsigned comparison 234 q2 = q2 + 1; 235 r2 = r2 - ad; 236 } 237 delta = ad - r2; 238 } while (q1 < delta || (q1 == delta && r1 == 0)); 239 240 mag.m = (int32_t)(q2 + 1); // make sure to sign extend 241 if (d < 0) mag.m = -mag.m; // resulting magic number 242 mag.s = p - 32; // resulting shift 243 return mag; 244} 245 246/// magicu - calculate the magic numbers required to codegen an integer udiv as 247/// a sequence of multiply, add and shifts. Requires that the divisor not be 0. 248static mu magicu32(uint32_t d) { 249 int32_t p; 250 uint32_t nc, delta, q1, r1, q2, r2; 251 struct mu magu; 252 magu.a = 0; // initialize "add" indicator 253 nc = - 1 - (-d)%d; 254 p = 31; // initialize p 255 q1 = 0x80000000/nc; // initialize q1 = 2p/nc 256 r1 = 0x80000000 - q1*nc; // initialize r1 = rem(2p,nc) 257 q2 = 0x7FFFFFFF/d; // initialize q2 = (2p-1)/d 258 r2 = 0x7FFFFFFF - q2*d; // initialize r2 = rem((2p-1),d) 259 do { 260 p = p + 1; 261 if (r1 >= nc - r1 ) { 262 q1 = 2*q1 + 1; // update q1 263 r1 = 2*r1 - nc; // update r1 264 } 265 else { 266 q1 = 2*q1; // update q1 267 r1 = 2*r1; // update r1 268 } 269 if (r2 + 1 >= d - r2) { 270 if (q2 >= 0x7FFFFFFF) magu.a = 1; 271 q2 = 2*q2 + 1; // update q2 272 r2 = 2*r2 + 1 - d; // update r2 273 } 274 else { 275 if (q2 >= 0x80000000) magu.a = 1; 276 q2 = 2*q2; // update q2 277 r2 = 2*r2 + 1; // update r2 278 } 279 delta = d - 1 - r2; 280 } while (p < 64 && (q1 < delta || (q1 == delta && r1 == 0))); 281 magu.m = q2 + 1; // resulting magic number 282 magu.s = p - 32; // resulting shift 283 return magu; 284} 285 286/// magic - calculate the magic numbers required to codegen an integer sdiv as 287/// a sequence of multiply and shifts. Requires that the divisor not be 0, 1, 288/// or -1. 289static ms magic64(int64_t d) { 290 int64_t p; 291 uint64_t ad, anc, delta, q1, r1, q2, r2, t; 292 const uint64_t two63 = 9223372036854775808ULL; // 2^63 293 struct ms mag; 294 295 ad = d >= 0 ? d : -d; 296 t = two63 + ((uint64_t)d >> 63); 297 anc = t - 1 - t%ad; // absolute value of nc 298 p = 63; // initialize p 299 q1 = two63/anc; // initialize q1 = 2p/abs(nc) 300 r1 = two63 - q1*anc; // initialize r1 = rem(2p,abs(nc)) 301 q2 = two63/ad; // initialize q2 = 2p/abs(d) 302 r2 = two63 - q2*ad; // initialize r2 = rem(2p,abs(d)) 303 do { 304 p = p + 1; 305 q1 = 2*q1; // update q1 = 2p/abs(nc) 306 r1 = 2*r1; // update r1 = rem(2p/abs(nc)) 307 if (r1 >= anc) { // must be unsigned comparison 308 q1 = q1 + 1; 309 r1 = r1 - anc; 310 } 311 q2 = 2*q2; // update q2 = 2p/abs(d) 312 r2 = 2*r2; // update r2 = rem(2p/abs(d)) 313 if (r2 >= ad) { // must be unsigned comparison 314 q2 = q2 + 1; 315 r2 = r2 - ad; 316 } 317 delta = ad - r2; 318 } while (q1 < delta || (q1 == delta && r1 == 0)); 319 320 mag.m = q2 + 1; 321 if (d < 0) mag.m = -mag.m; // resulting magic number 322 mag.s = p - 64; // resulting shift 323 return mag; 324} 325 326/// magicu - calculate the magic numbers required to codegen an integer udiv as 327/// a sequence of multiply, add and shifts. Requires that the divisor not be 0. 328static mu magicu64(uint64_t d) 329{ 330 int64_t p; 331 uint64_t nc, delta, q1, r1, q2, r2; 332 struct mu magu; 333 magu.a = 0; // initialize "add" indicator 334 nc = - 1 - (-d)%d; 335 p = 63; // initialize p 336 q1 = 0x8000000000000000ull/nc; // initialize q1 = 2p/nc 337 r1 = 0x8000000000000000ull - q1*nc; // initialize r1 = rem(2p,nc) 338 q2 = 0x7FFFFFFFFFFFFFFFull/d; // initialize q2 = (2p-1)/d 339 r2 = 0x7FFFFFFFFFFFFFFFull - q2*d; // initialize r2 = rem((2p-1),d) 340 do { 341 p = p + 1; 342 if (r1 >= nc - r1 ) { 343 q1 = 2*q1 + 1; // update q1 344 r1 = 2*r1 - nc; // update r1 345 } 346 else { 347 q1 = 2*q1; // update q1 348 r1 = 2*r1; // update r1 349 } 350 if (r2 + 1 >= d - r2) { 351 if (q2 >= 0x7FFFFFFFFFFFFFFFull) magu.a = 1; 352 q2 = 2*q2 + 1; // update q2 353 r2 = 2*r2 + 1 - d; // update r2 354 } 355 else { 356 if (q2 >= 0x8000000000000000ull) magu.a = 1; 357 q2 = 2*q2; // update q2 358 r2 = 2*r2 + 1; // update r2 359 } 360 delta = d - 1 - r2; 361 } while (p < 64 && (q1 < delta || (q1 == delta && r1 == 0))); 362 magu.m = q2 + 1; // resulting magic number 363 magu.s = p - 64; // resulting shift 364 return magu; 365} 366 367/// MaskedValueIsZero - Return true if 'Op & Mask' is known to be zero. We use 368/// this predicate to simplify operations downstream. Op and Mask are known to 369/// be the same type. 370static bool MaskedValueIsZero(const SDOperand &Op, uint64_t Mask, 371 const TargetLowering &TLI) { 372 unsigned SrcBits; 373 if (Mask == 0) return true; 374 375 // If we know the result of a setcc has the top bits zero, use this info. 376 switch (Op.getOpcode()) { 377 case ISD::Constant: 378 return (cast<ConstantSDNode>(Op)->getValue() & Mask) == 0; 379 case ISD::SETCC: 380 return ((Mask & 1) == 0) && 381 TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult; 382 case ISD::ZEXTLOAD: 383 SrcBits = MVT::getSizeInBits(cast<VTSDNode>(Op.getOperand(3))->getVT()); 384 return (Mask & ((1ULL << SrcBits)-1)) == 0; // Returning only the zext bits. 385 case ISD::ZERO_EXTEND: 386 SrcBits = MVT::getSizeInBits(Op.getOperand(0).getValueType()); 387 return MaskedValueIsZero(Op.getOperand(0),Mask & ((1ULL << SrcBits)-1),TLI); 388 case ISD::AssertZext: 389 SrcBits = MVT::getSizeInBits(cast<VTSDNode>(Op.getOperand(1))->getVT()); 390 return (Mask & ((1ULL << SrcBits)-1)) == 0; // Returning only the zext bits. 391 case ISD::AND: 392 // If either of the operands has zero bits, the result will too. 393 if (MaskedValueIsZero(Op.getOperand(1), Mask, TLI) || 394 MaskedValueIsZero(Op.getOperand(0), Mask, TLI)) 395 return true; 396 // (X & C1) & C2 == 0 iff C1 & C2 == 0. 397 if (ConstantSDNode *AndRHS = dyn_cast<ConstantSDNode>(Op.getOperand(1))) 398 return MaskedValueIsZero(Op.getOperand(0),AndRHS->getValue() & Mask, TLI); 399 return false; 400 case ISD::OR: 401 case ISD::XOR: 402 return MaskedValueIsZero(Op.getOperand(0), Mask, TLI) && 403 MaskedValueIsZero(Op.getOperand(1), Mask, TLI); 404 case ISD::SELECT: 405 return MaskedValueIsZero(Op.getOperand(1), Mask, TLI) && 406 MaskedValueIsZero(Op.getOperand(2), Mask, TLI); 407 case ISD::SELECT_CC: 408 return MaskedValueIsZero(Op.getOperand(2), Mask, TLI) && 409 MaskedValueIsZero(Op.getOperand(3), Mask, TLI); 410 case ISD::SRL: 411 // (ushr X, C1) & C2 == 0 iff X & (C2 << C1) == 0 412 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 413 uint64_t NewVal = Mask << ShAmt->getValue(); 414 SrcBits = MVT::getSizeInBits(Op.getValueType()); 415 if (SrcBits != 64) NewVal &= (1ULL << SrcBits)-1; 416 return MaskedValueIsZero(Op.getOperand(0), NewVal, TLI); 417 } 418 return false; 419 case ISD::SHL: 420 // (ushl X, C1) & C2 == 0 iff X & (C2 >> C1) == 0 421 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 422 uint64_t NewVal = Mask >> ShAmt->getValue(); 423 return MaskedValueIsZero(Op.getOperand(0), NewVal, TLI); 424 } 425 return false; 426 case ISD::ADD: 427 // (add X, Y) & C == 0 iff (X&C)|(Y&C) == 0 and all bits are low bits. 428 if ((Mask&(Mask+1)) == 0) { // All low bits 429 if (MaskedValueIsZero(Op.getOperand(0), Mask, TLI) && 430 MaskedValueIsZero(Op.getOperand(1), Mask, TLI)) 431 return true; 432 } 433 break; 434 case ISD::SUB: 435 if (ConstantSDNode *CLHS = dyn_cast<ConstantSDNode>(Op.getOperand(0))) { 436 // We know that the top bits of C-X are clear if X contains less bits 437 // than C (i.e. no wrap-around can happen). For example, 20-X is 438 // positive if we can prove that X is >= 0 and < 16. 439 unsigned Bits = MVT::getSizeInBits(CLHS->getValueType(0)); 440 if ((CLHS->getValue() & (1 << (Bits-1))) == 0) { // sign bit clear 441 unsigned NLZ = CountLeadingZeros_64(CLHS->getValue()+1); 442 uint64_t MaskV = (1ULL << (63-NLZ))-1; 443 if (MaskedValueIsZero(Op.getOperand(1), ~MaskV, TLI)) { 444 // High bits are clear this value is known to be >= C. 445 unsigned NLZ2 = CountLeadingZeros_64(CLHS->getValue()); 446 if ((Mask & ((1ULL << (64-NLZ2))-1)) == 0) 447 return true; 448 } 449 } 450 } 451 break; 452 case ISD::CTTZ: 453 case ISD::CTLZ: 454 case ISD::CTPOP: 455 // Bit counting instructions can not set the high bits of the result 456 // register. The max number of bits sets depends on the input. 457 return (Mask & (MVT::getSizeInBits(Op.getValueType())*2-1)) == 0; 458 default: break; 459 } 460 return false; 461} 462 463// isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc 464// that selects between the values 1 and 0, making it equivalent to a setcc. 465// Also, set the incoming LHS, RHS, and CC references to the appropriate 466// nodes based on the type of node we are checking. This simplifies life a 467// bit for the callers. 468static bool isSetCCEquivalent(SDOperand N, SDOperand &LHS, SDOperand &RHS, 469 SDOperand &CC) { 470 if (N.getOpcode() == ISD::SETCC) { 471 LHS = N.getOperand(0); 472 RHS = N.getOperand(1); 473 CC = N.getOperand(2); 474 return true; 475 } 476 if (N.getOpcode() == ISD::SELECT_CC && 477 N.getOperand(2).getOpcode() == ISD::Constant && 478 N.getOperand(3).getOpcode() == ISD::Constant && 479 cast<ConstantSDNode>(N.getOperand(2))->getValue() == 1 && 480 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) { 481 LHS = N.getOperand(0); 482 RHS = N.getOperand(1); 483 CC = N.getOperand(4); 484 return true; 485 } 486 return false; 487} 488 489// isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only 490// one use. If this is true, it allows the users to invert the operation for 491// free when it is profitable to do so. 492static bool isOneUseSetCC(SDOperand N) { 493 SDOperand N0, N1, N2; 494 if (isSetCCEquivalent(N, N0, N1, N2) && N.Val->hasOneUse()) 495 return true; 496 return false; 497} 498 499// FIXME: This should probably go in the ISD class rather than being duplicated 500// in several files. 501static bool isCommutativeBinOp(unsigned Opcode) { 502 switch (Opcode) { 503 case ISD::ADD: 504 case ISD::MUL: 505 case ISD::AND: 506 case ISD::OR: 507 case ISD::XOR: return true; 508 default: return false; // FIXME: Need commutative info for user ops! 509 } 510} 511 512void DAGCombiner::Run(bool RunningAfterLegalize) { 513 // set the instance variable, so that the various visit routines may use it. 514 AfterLegalize = RunningAfterLegalize; 515 516 // Add all the dag nodes to the worklist. 517 WorkList.insert(WorkList.end(), DAG.allnodes_begin(), DAG.allnodes_end()); 518 519 // Create a dummy node (which is not added to allnodes), that adds a reference 520 // to the root node, preventing it from being deleted, and tracking any 521 // changes of the root. 522 HandleSDNode Dummy(DAG.getRoot()); 523 524 // while the worklist isn't empty, inspect the node on the end of it and 525 // try and combine it. 526 while (!WorkList.empty()) { 527 SDNode *N = WorkList.back(); 528 WorkList.pop_back(); 529 530 // If N has no uses, it is dead. Make sure to revisit all N's operands once 531 // N is deleted from the DAG, since they too may now be dead or may have a 532 // reduced number of uses, allowing other xforms. 533 if (N->use_empty() && N != &Dummy) { 534 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 535 WorkList.push_back(N->getOperand(i).Val); 536 537 removeFromWorkList(N); 538 DAG.DeleteNode(N); 539 continue; 540 } 541 542 SDOperand RV = visit(N); 543 if (RV.Val) { 544 ++NodesCombined; 545 // If we get back the same node we passed in, rather than a new node or 546 // zero, we know that the node must have defined multiple values and 547 // CombineTo was used. Since CombineTo takes care of the worklist 548 // mechanics for us, we have no work to do in this case. 549 if (RV.Val != N) { 550 DEBUG(std::cerr << "\nReplacing "; N->dump(); 551 std::cerr << "\nWith: "; RV.Val->dump(); 552 std::cerr << '\n'); 553 std::vector<SDNode*> NowDead; 554 DAG.ReplaceAllUsesWith(N, std::vector<SDOperand>(1, RV), &NowDead); 555 556 // Push the new node and any users onto the worklist 557 WorkList.push_back(RV.Val); 558 AddUsersToWorkList(RV.Val); 559 560 // Nodes can end up on the worklist more than once. Make sure we do 561 // not process a node that has been replaced. 562 removeFromWorkList(N); 563 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 564 removeFromWorkList(NowDead[i]); 565 566 // Finally, since the node is now dead, remove it from the graph. 567 DAG.DeleteNode(N); 568 } 569 } 570 } 571 572 // If the root changed (e.g. it was a dead load, update the root). 573 DAG.setRoot(Dummy.getValue()); 574} 575 576SDOperand DAGCombiner::visit(SDNode *N) { 577 switch(N->getOpcode()) { 578 default: break; 579 case ISD::TokenFactor: return visitTokenFactor(N); 580 case ISD::ADD: return visitADD(N); 581 case ISD::SUB: return visitSUB(N); 582 case ISD::MUL: return visitMUL(N); 583 case ISD::SDIV: return visitSDIV(N); 584 case ISD::UDIV: return visitUDIV(N); 585 case ISD::SREM: return visitSREM(N); 586 case ISD::UREM: return visitUREM(N); 587 case ISD::MULHU: return visitMULHU(N); 588 case ISD::MULHS: return visitMULHS(N); 589 case ISD::AND: return visitAND(N); 590 case ISD::OR: return visitOR(N); 591 case ISD::XOR: return visitXOR(N); 592 case ISD::SHL: return visitSHL(N); 593 case ISD::SRA: return visitSRA(N); 594 case ISD::SRL: return visitSRL(N); 595 case ISD::CTLZ: return visitCTLZ(N); 596 case ISD::CTTZ: return visitCTTZ(N); 597 case ISD::CTPOP: return visitCTPOP(N); 598 case ISD::SELECT: return visitSELECT(N); 599 case ISD::SELECT_CC: return visitSELECT_CC(N); 600 case ISD::SETCC: return visitSETCC(N); 601 case ISD::ADD_PARTS: return visitADD_PARTS(N); 602 case ISD::SUB_PARTS: return visitSUB_PARTS(N); 603 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N); 604 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N); 605 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N); 606 case ISD::TRUNCATE: return visitTRUNCATE(N); 607 case ISD::FADD: return visitFADD(N); 608 case ISD::FSUB: return visitFSUB(N); 609 case ISD::FMUL: return visitFMUL(N); 610 case ISD::FDIV: return visitFDIV(N); 611 case ISD::FREM: return visitFREM(N); 612 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N); 613 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N); 614 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N); 615 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N); 616 case ISD::FP_ROUND: return visitFP_ROUND(N); 617 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N); 618 case ISD::FP_EXTEND: return visitFP_EXTEND(N); 619 case ISD::FNEG: return visitFNEG(N); 620 case ISD::FABS: return visitFABS(N); 621 case ISD::BRCOND: return visitBRCOND(N); 622 case ISD::BRCONDTWOWAY: return visitBRCONDTWOWAY(N); 623 case ISD::BR_CC: return visitBR_CC(N); 624 case ISD::BRTWOWAY_CC: return visitBRTWOWAY_CC(N); 625 case ISD::LOAD: return visitLOAD(N); 626 case ISD::STORE: return visitSTORE(N); 627 } 628 return SDOperand(); 629} 630 631SDOperand DAGCombiner::visitTokenFactor(SDNode *N) { 632 std::vector<SDOperand> Ops; 633 bool Changed = false; 634 635 // If the token factor has two operands and one is the entry token, replace 636 // the token factor with the other operand. 637 if (N->getNumOperands() == 2) { 638 if (N->getOperand(0).getOpcode() == ISD::EntryToken) 639 return N->getOperand(1); 640 if (N->getOperand(1).getOpcode() == ISD::EntryToken) 641 return N->getOperand(0); 642 } 643 644 // fold (tokenfactor (tokenfactor)) -> tokenfactor 645 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { 646 SDOperand Op = N->getOperand(i); 647 if (Op.getOpcode() == ISD::TokenFactor && Op.hasOneUse()) { 648 Changed = true; 649 for (unsigned j = 0, e = Op.getNumOperands(); j != e; ++j) 650 Ops.push_back(Op.getOperand(j)); 651 } else { 652 Ops.push_back(Op); 653 } 654 } 655 if (Changed) 656 return DAG.getNode(ISD::TokenFactor, MVT::Other, Ops); 657 return SDOperand(); 658} 659 660SDOperand DAGCombiner::visitADD(SDNode *N) { 661 SDOperand N0 = N->getOperand(0); 662 SDOperand N1 = N->getOperand(1); 663 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 664 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 665 MVT::ValueType VT = N0.getValueType(); 666 667 // fold (add c1, c2) -> c1+c2 668 if (N0C && N1C) 669 return DAG.getConstant(N0C->getValue() + N1C->getValue(), VT); 670 // canonicalize constant to RHS 671 if (N0C && !N1C) 672 return DAG.getNode(ISD::ADD, VT, N1, N0); 673 // fold (add x, 0) -> x 674 if (N1C && N1C->isNullValue()) 675 return N0; 676 // fold (add (add x, c1), c2) -> (add x, c1+c2) 677 if (N1C && N0.getOpcode() == ISD::ADD) { 678 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0)); 679 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 680 if (N00C) 681 return DAG.getNode(ISD::ADD, VT, N0.getOperand(1), 682 DAG.getConstant(N1C->getValue()+N00C->getValue(), VT)); 683 if (N01C) 684 return DAG.getNode(ISD::ADD, VT, N0.getOperand(0), 685 DAG.getConstant(N1C->getValue()+N01C->getValue(), VT)); 686 } 687 // fold ((0-A) + B) -> B-A 688 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) && 689 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue()) 690 return DAG.getNode(ISD::SUB, VT, N1, N0.getOperand(1)); 691 // fold (A + (0-B)) -> A-B 692 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) && 693 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue()) 694 return DAG.getNode(ISD::SUB, VT, N0, N1.getOperand(1)); 695 // fold (A+(B-A)) -> B 696 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1)) 697 return N1.getOperand(0); 698 return SDOperand(); 699} 700 701SDOperand DAGCombiner::visitSUB(SDNode *N) { 702 SDOperand N0 = N->getOperand(0); 703 SDOperand N1 = N->getOperand(1); 704 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 705 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 706 707 // fold (sub x, x) -> 0 708 if (N0 == N1) 709 return DAG.getConstant(0, N->getValueType(0)); 710 711 // fold (sub c1, c2) -> c1-c2 712 if (N0C && N1C) 713 return DAG.getConstant(N0C->getValue() - N1C->getValue(), 714 N->getValueType(0)); 715 // fold (sub x, c) -> (add x, -c) 716 if (N1C) 717 return DAG.getNode(ISD::ADD, N0.getValueType(), N0, 718 DAG.getConstant(-N1C->getValue(), N0.getValueType())); 719 720 // fold (A+B)-A -> B 721 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1) 722 return N0.getOperand(1); 723 // fold (A+B)-B -> A 724 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1) 725 return N0.getOperand(0); 726 return SDOperand(); 727} 728 729SDOperand DAGCombiner::visitMUL(SDNode *N) { 730 SDOperand N0 = N->getOperand(0); 731 SDOperand N1 = N->getOperand(1); 732 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 733 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 734 MVT::ValueType VT = N0.getValueType(); 735 736 // fold (mul c1, c2) -> c1*c2 737 if (N0C && N1C) 738 return DAG.getConstant(N0C->getValue() * N1C->getValue(), 739 N->getValueType(0)); 740 // canonicalize constant to RHS 741 if (N0C && !N1C) 742 return DAG.getNode(ISD::MUL, VT, N1, N0); 743 // fold (mul x, 0) -> 0 744 if (N1C && N1C->isNullValue()) 745 return N1; 746 // fold (mul x, -1) -> 0-x 747 if (N1C && N1C->isAllOnesValue()) 748 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0); 749 // fold (mul x, (1 << c)) -> x << c 750 if (N1C && isPowerOf2_64(N1C->getValue())) 751 return DAG.getNode(ISD::SHL, N->getValueType(0), N0, 752 DAG.getConstant(Log2_64(N1C->getValue()), 753 TLI.getShiftAmountTy())); 754 // fold (mul (mul x, c1), c2) -> (mul x, c1*c2) 755 if (N1C && N0.getOpcode() == ISD::MUL) { 756 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0)); 757 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 758 if (N00C) 759 return DAG.getNode(ISD::MUL, VT, N0.getOperand(1), 760 DAG.getConstant(N1C->getValue()*N00C->getValue(), VT)); 761 if (N01C) 762 return DAG.getNode(ISD::MUL, VT, N0.getOperand(0), 763 DAG.getConstant(N1C->getValue()*N01C->getValue(), VT)); 764 } 765 return SDOperand(); 766} 767 768SDOperand DAGCombiner::visitSDIV(SDNode *N) { 769 SDOperand N0 = N->getOperand(0); 770 SDOperand N1 = N->getOperand(1); 771 MVT::ValueType VT = N->getValueType(0); 772 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 773 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 774 775 // fold (sdiv c1, c2) -> c1/c2 776 if (N0C && N1C && !N1C->isNullValue()) 777 return DAG.getConstant(N0C->getSignExtended() / N1C->getSignExtended(), 778 N->getValueType(0)); 779 // fold (sdiv X, 1) -> X 780 if (N1C && N1C->getSignExtended() == 1LL) 781 return N0; 782 // fold (sdiv X, -1) -> 0-X 783 if (N1C && N1C->isAllOnesValue()) 784 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0); 785 // If we know the sign bits of both operands are zero, strength reduce to a 786 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2 787 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1); 788 if (MaskedValueIsZero(N1, SignBit, TLI) && 789 MaskedValueIsZero(N0, SignBit, TLI)) 790 return DAG.getNode(ISD::UDIV, N1.getValueType(), N0, N1); 791 // fold (sdiv X, pow2) -> (add (sra X, log(pow2)), (srl X, sizeof(X)-1)) 792 if (N1C && N1C->getValue() && !TLI.isIntDivCheap() && 793 (isPowerOf2_64(N1C->getSignExtended()) || 794 isPowerOf2_64(-N1C->getSignExtended()))) { 795 // If dividing by powers of two is cheap, then don't perform the following 796 // fold. 797 if (TLI.isPow2DivCheap()) 798 return SDOperand(); 799 int64_t pow2 = N1C->getSignExtended(); 800 int64_t abs2 = pow2 > 0 ? pow2 : -pow2; 801 SDOperand SRL = DAG.getNode(ISD::SRL, VT, N0, 802 DAG.getConstant(MVT::getSizeInBits(VT)-1, 803 TLI.getShiftAmountTy())); 804 WorkList.push_back(SRL.Val); 805 SDOperand SGN = DAG.getNode(ISD::ADD, VT, N0, SRL); 806 WorkList.push_back(SGN.Val); 807 SDOperand SRA = DAG.getNode(ISD::SRA, VT, SGN, 808 DAG.getConstant(Log2_64(abs2), 809 TLI.getShiftAmountTy())); 810 // If we're dividing by a positive value, we're done. Otherwise, we must 811 // negate the result. 812 if (pow2 > 0) 813 return SRA; 814 WorkList.push_back(SRA.Val); 815 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), SRA); 816 } 817 // if integer divide is expensive and we satisfy the requirements, emit an 818 // alternate sequence. 819 if (N1C && (N1C->getSignExtended() < -1 || N1C->getSignExtended() > 1) && 820 !TLI.isIntDivCheap()) { 821 SDOperand Op = BuildSDIV(N); 822 if (Op.Val) return Op; 823 } 824 return SDOperand(); 825} 826 827SDOperand DAGCombiner::visitUDIV(SDNode *N) { 828 SDOperand N0 = N->getOperand(0); 829 SDOperand N1 = N->getOperand(1); 830 MVT::ValueType VT = N->getValueType(0); 831 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 832 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 833 834 // fold (udiv c1, c2) -> c1/c2 835 if (N0C && N1C && !N1C->isNullValue()) 836 return DAG.getConstant(N0C->getValue() / N1C->getValue(), 837 N->getValueType(0)); 838 // fold (udiv x, (1 << c)) -> x >>u c 839 if (N1C && isPowerOf2_64(N1C->getValue())) 840 return DAG.getNode(ISD::SRL, N->getValueType(0), N0, 841 DAG.getConstant(Log2_64(N1C->getValue()), 842 TLI.getShiftAmountTy())); 843 // fold (udiv x, c) -> alternate 844 if (N1C && N1C->getValue() && !TLI.isIntDivCheap()) { 845 SDOperand Op = BuildUDIV(N); 846 if (Op.Val) return Op; 847 } 848 849 return SDOperand(); 850} 851 852SDOperand DAGCombiner::visitSREM(SDNode *N) { 853 SDOperand N0 = N->getOperand(0); 854 SDOperand N1 = N->getOperand(1); 855 MVT::ValueType VT = N->getValueType(0); 856 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 857 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 858 859 // fold (srem c1, c2) -> c1%c2 860 if (N0C && N1C && !N1C->isNullValue()) 861 return DAG.getConstant(N0C->getSignExtended() % N1C->getSignExtended(), 862 N->getValueType(0)); 863 // If we know the sign bits of both operands are zero, strength reduce to a 864 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15 865 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1); 866 if (MaskedValueIsZero(N1, SignBit, TLI) && 867 MaskedValueIsZero(N0, SignBit, TLI)) 868 return DAG.getNode(ISD::UREM, N1.getValueType(), N0, N1); 869 return SDOperand(); 870} 871 872SDOperand DAGCombiner::visitUREM(SDNode *N) { 873 SDOperand N0 = N->getOperand(0); 874 SDOperand N1 = N->getOperand(1); 875 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 876 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 877 878 // fold (urem c1, c2) -> c1%c2 879 if (N0C && N1C && !N1C->isNullValue()) 880 return DAG.getConstant(N0C->getValue() % N1C->getValue(), 881 N->getValueType(0)); 882 // fold (urem x, pow2) -> (and x, pow2-1) 883 if (N1C && !N1C->isNullValue() && isPowerOf2_64(N1C->getValue())) 884 return DAG.getNode(ISD::AND, N0.getValueType(), N0, 885 DAG.getConstant(N1C->getValue()-1, N1.getValueType())); 886 return SDOperand(); 887} 888 889SDOperand DAGCombiner::visitMULHS(SDNode *N) { 890 SDOperand N0 = N->getOperand(0); 891 SDOperand N1 = N->getOperand(1); 892 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 893 894 // fold (mulhs x, 0) -> 0 895 if (N1C && N1C->isNullValue()) 896 return N1; 897 // fold (mulhs x, 1) -> (sra x, size(x)-1) 898 if (N1C && N1C->getValue() == 1) 899 return DAG.getNode(ISD::SRA, N0.getValueType(), N0, 900 DAG.getConstant(MVT::getSizeInBits(N0.getValueType())-1, 901 TLI.getShiftAmountTy())); 902 return SDOperand(); 903} 904 905SDOperand DAGCombiner::visitMULHU(SDNode *N) { 906 SDOperand N0 = N->getOperand(0); 907 SDOperand N1 = N->getOperand(1); 908 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 909 910 // fold (mulhu x, 0) -> 0 911 if (N1C && N1C->isNullValue()) 912 return N1; 913 // fold (mulhu x, 1) -> 0 914 if (N1C && N1C->getValue() == 1) 915 return DAG.getConstant(0, N0.getValueType()); 916 return SDOperand(); 917} 918 919SDOperand DAGCombiner::visitAND(SDNode *N) { 920 SDOperand N0 = N->getOperand(0); 921 SDOperand N1 = N->getOperand(1); 922 SDOperand LL, LR, RL, RR, CC0, CC1; 923 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 924 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 925 MVT::ValueType VT = N1.getValueType(); 926 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 927 928 // fold (and c1, c2) -> c1&c2 929 if (N0C && N1C) 930 return DAG.getConstant(N0C->getValue() & N1C->getValue(), VT); 931 // canonicalize constant to RHS 932 if (N0C && !N1C) 933 return DAG.getNode(ISD::AND, VT, N1, N0); 934 // fold (and x, -1) -> x 935 if (N1C && N1C->isAllOnesValue()) 936 return N0; 937 // if (and x, c) is known to be zero, return 0 938 if (N1C && MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits),TLI)) 939 return DAG.getConstant(0, VT); 940 // fold (and x, c) -> x iff (x & ~c) == 0 941 if (N1C && MaskedValueIsZero(N0,~N1C->getValue() & (~0ULL>>(64-OpSizeInBits)), 942 TLI)) 943 return N0; 944 // fold (and (and x, c1), c2) -> (and x, c1^c2) 945 if (N1C && N0.getOpcode() == ISD::AND) { 946 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0)); 947 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 948 if (N00C) 949 return DAG.getNode(ISD::AND, VT, N0.getOperand(1), 950 DAG.getConstant(N1C->getValue()&N00C->getValue(), VT)); 951 if (N01C) 952 return DAG.getNode(ISD::AND, VT, N0.getOperand(0), 953 DAG.getConstant(N1C->getValue()&N01C->getValue(), VT)); 954 } 955 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1) 956 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG) { 957 unsigned ExtendBits = 958 MVT::getSizeInBits(cast<VTSDNode>(N0.getOperand(1))->getVT()); 959 if ((N1C->getValue() & (~0ULL << ExtendBits)) == 0) 960 return DAG.getNode(ISD::AND, VT, N0.getOperand(0), N1); 961 } 962 // fold (and (or x, 0xFFFF), 0xFF) -> 0xFF 963 if (N0.getOpcode() == ISD::OR && N1C) 964 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 965 if ((ORI->getValue() & N1C->getValue()) == N1C->getValue()) 966 return N1; 967 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y)) 968 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 969 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 970 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 971 972 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 973 MVT::isInteger(LL.getValueType())) { 974 // fold (X == 0) & (Y == 0) -> (X|Y == 0) 975 if (cast<ConstantSDNode>(LR)->getValue() == 0 && Op1 == ISD::SETEQ) { 976 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 977 WorkList.push_back(ORNode.Val); 978 return DAG.getSetCC(VT, ORNode, LR, Op1); 979 } 980 // fold (X == -1) & (Y == -1) -> (X&Y == -1) 981 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) { 982 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL); 983 WorkList.push_back(ANDNode.Val); 984 return DAG.getSetCC(VT, ANDNode, LR, Op1); 985 } 986 // fold (X > -1) & (Y > -1) -> (X|Y > -1) 987 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) { 988 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 989 WorkList.push_back(ORNode.Val); 990 return DAG.getSetCC(VT, ORNode, LR, Op1); 991 } 992 } 993 // canonicalize equivalent to ll == rl 994 if (LL == RR && LR == RL) { 995 Op1 = ISD::getSetCCSwappedOperands(Op1); 996 std::swap(RL, RR); 997 } 998 if (LL == RL && LR == RR) { 999 bool isInteger = MVT::isInteger(LL.getValueType()); 1000 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger); 1001 if (Result != ISD::SETCC_INVALID) 1002 return DAG.getSetCC(N0.getValueType(), LL, LR, Result); 1003 } 1004 } 1005 // fold (and (zext x), (zext y)) -> (zext (and x, y)) 1006 if (N0.getOpcode() == ISD::ZERO_EXTEND && 1007 N1.getOpcode() == ISD::ZERO_EXTEND && 1008 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) { 1009 SDOperand ANDNode = DAG.getNode(ISD::AND, N0.getOperand(0).getValueType(), 1010 N0.getOperand(0), N1.getOperand(0)); 1011 WorkList.push_back(ANDNode.Val); 1012 return DAG.getNode(ISD::ZERO_EXTEND, VT, ANDNode); 1013 } 1014 // fold (and (shl/srl x), (shl/srl y)) -> (shl/srl (and x, y)) 1015 if (((N0.getOpcode() == ISD::SHL && N1.getOpcode() == ISD::SHL) || 1016 (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SRL)) && 1017 N0.getOperand(1) == N1.getOperand(1)) { 1018 SDOperand ANDNode = DAG.getNode(ISD::AND, N0.getOperand(0).getValueType(), 1019 N0.getOperand(0), N1.getOperand(0)); 1020 WorkList.push_back(ANDNode.Val); 1021 return DAG.getNode(N0.getOpcode(), VT, ANDNode, N0.getOperand(1)); 1022 } 1023 // fold (and (sra)) -> (and (srl)) when possible. 1024 if (N0.getOpcode() == ISD::SRA && N0.Val->hasOneUse()) 1025 if (ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 1026 // If the RHS of the AND has zeros where the sign bits of the SRA will 1027 // land, turn the SRA into an SRL. 1028 if (MaskedValueIsZero(N1, (~0ULL << (OpSizeInBits-N01C->getValue())) & 1029 (~0ULL>>(64-OpSizeInBits)), TLI)) { 1030 WorkList.push_back(N); 1031 CombineTo(N0.Val, DAG.getNode(ISD::SRL, VT, N0.getOperand(0), 1032 N0.getOperand(1))); 1033 return SDOperand(); 1034 } 1035 } 1036 1037 // fold (zext_inreg (extload x)) -> (zextload x) 1038 if (N0.getOpcode() == ISD::EXTLOAD) { 1039 MVT::ValueType EVT = cast<VTSDNode>(N0.getOperand(3))->getVT(); 1040 // If we zero all the possible extended bits, then we can turn this into 1041 // a zextload if we are running before legalize or the operation is legal. 1042 if (MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT), TLI) && 1043 (!AfterLegalize || TLI.isOperationLegal(ISD::ZEXTLOAD, EVT))) { 1044 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0), 1045 N0.getOperand(1), N0.getOperand(2), 1046 EVT); 1047 WorkList.push_back(N); 1048 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 1049 return SDOperand(); 1050 } 1051 } 1052 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use 1053 if (N0.getOpcode() == ISD::SEXTLOAD && N0.hasOneUse()) { 1054 MVT::ValueType EVT = cast<VTSDNode>(N0.getOperand(3))->getVT(); 1055 // If we zero all the possible extended bits, then we can turn this into 1056 // a zextload if we are running before legalize or the operation is legal. 1057 if (MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT), TLI) && 1058 (!AfterLegalize || TLI.isOperationLegal(ISD::ZEXTLOAD, EVT))) { 1059 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0), 1060 N0.getOperand(1), N0.getOperand(2), 1061 EVT); 1062 WorkList.push_back(N); 1063 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 1064 return SDOperand(); 1065 } 1066 } 1067 return SDOperand(); 1068} 1069 1070SDOperand DAGCombiner::visitOR(SDNode *N) { 1071 SDOperand N0 = N->getOperand(0); 1072 SDOperand N1 = N->getOperand(1); 1073 SDOperand LL, LR, RL, RR, CC0, CC1; 1074 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1075 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1076 MVT::ValueType VT = N1.getValueType(); 1077 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 1078 1079 // fold (or c1, c2) -> c1|c2 1080 if (N0C && N1C) 1081 return DAG.getConstant(N0C->getValue() | N1C->getValue(), 1082 N->getValueType(0)); 1083 // canonicalize constant to RHS 1084 if (N0C && !N1C) 1085 return DAG.getNode(ISD::OR, VT, N1, N0); 1086 // fold (or x, 0) -> x 1087 if (N1C && N1C->isNullValue()) 1088 return N0; 1089 // fold (or x, -1) -> -1 1090 if (N1C && N1C->isAllOnesValue()) 1091 return N1; 1092 // fold (or x, c) -> c iff (x & ~c) == 0 1093 if (N1C && MaskedValueIsZero(N0,~N1C->getValue() & (~0ULL>>(64-OpSizeInBits)), 1094 TLI)) 1095 return N1; 1096 // fold (or (or x, c1), c2) -> (or x, c1|c2) 1097 if (N1C && N0.getOpcode() == ISD::OR) { 1098 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0)); 1099 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 1100 if (N00C) 1101 return DAG.getNode(ISD::OR, VT, N0.getOperand(1), 1102 DAG.getConstant(N1C->getValue()|N00C->getValue(), VT)); 1103 if (N01C) 1104 return DAG.getNode(ISD::OR, VT, N0.getOperand(0), 1105 DAG.getConstant(N1C->getValue()|N01C->getValue(), VT)); 1106 } else if (N1C && N0.getOpcode() == ISD::AND && N0.Val->hasOneUse() && 1107 isa<ConstantSDNode>(N0.getOperand(1))) { 1108 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2) 1109 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1)); 1110 return DAG.getNode(ISD::AND, VT, DAG.getNode(ISD::OR, VT, N0.getOperand(0), 1111 N1), 1112 DAG.getConstant(N1C->getValue() | C1->getValue(), VT)); 1113 } 1114 1115 1116 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y)) 1117 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 1118 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 1119 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 1120 1121 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 1122 MVT::isInteger(LL.getValueType())) { 1123 // fold (X != 0) | (Y != 0) -> (X|Y != 0) 1124 // fold (X < 0) | (Y < 0) -> (X|Y < 0) 1125 if (cast<ConstantSDNode>(LR)->getValue() == 0 && 1126 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) { 1127 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 1128 WorkList.push_back(ORNode.Val); 1129 return DAG.getSetCC(VT, ORNode, LR, Op1); 1130 } 1131 // fold (X != -1) | (Y != -1) -> (X&Y != -1) 1132 // fold (X > -1) | (Y > -1) -> (X&Y > -1) 1133 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && 1134 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) { 1135 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL); 1136 WorkList.push_back(ANDNode.Val); 1137 return DAG.getSetCC(VT, ANDNode, LR, Op1); 1138 } 1139 } 1140 // canonicalize equivalent to ll == rl 1141 if (LL == RR && LR == RL) { 1142 Op1 = ISD::getSetCCSwappedOperands(Op1); 1143 std::swap(RL, RR); 1144 } 1145 if (LL == RL && LR == RR) { 1146 bool isInteger = MVT::isInteger(LL.getValueType()); 1147 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger); 1148 if (Result != ISD::SETCC_INVALID) 1149 return DAG.getSetCC(N0.getValueType(), LL, LR, Result); 1150 } 1151 } 1152 // fold (or (zext x), (zext y)) -> (zext (or x, y)) 1153 if (N0.getOpcode() == ISD::ZERO_EXTEND && 1154 N1.getOpcode() == ISD::ZERO_EXTEND && 1155 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) { 1156 SDOperand ORNode = DAG.getNode(ISD::OR, N0.getOperand(0).getValueType(), 1157 N0.getOperand(0), N1.getOperand(0)); 1158 WorkList.push_back(ORNode.Val); 1159 return DAG.getNode(ISD::ZERO_EXTEND, VT, ORNode); 1160 } 1161 return SDOperand(); 1162} 1163 1164SDOperand DAGCombiner::visitXOR(SDNode *N) { 1165 SDOperand N0 = N->getOperand(0); 1166 SDOperand N1 = N->getOperand(1); 1167 SDOperand LHS, RHS, CC; 1168 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1169 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1170 MVT::ValueType VT = N0.getValueType(); 1171 1172 // fold (xor c1, c2) -> c1^c2 1173 if (N0C && N1C) 1174 return DAG.getConstant(N0C->getValue() ^ N1C->getValue(), VT); 1175 // canonicalize constant to RHS 1176 if (N0C && !N1C) 1177 return DAG.getNode(ISD::XOR, VT, N1, N0); 1178 // fold (xor x, 0) -> x 1179 if (N1C && N1C->isNullValue()) 1180 return N0; 1181 // fold !(x cc y) -> (x !cc y) 1182 if (N1C && N1C->getValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) { 1183 bool isInt = MVT::isInteger(LHS.getValueType()); 1184 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(), 1185 isInt); 1186 if (N0.getOpcode() == ISD::SETCC) 1187 return DAG.getSetCC(VT, LHS, RHS, NotCC); 1188 if (N0.getOpcode() == ISD::SELECT_CC) 1189 return DAG.getSelectCC(LHS, RHS, N0.getOperand(2),N0.getOperand(3),NotCC); 1190 assert(0 && "Unhandled SetCC Equivalent!"); 1191 abort(); 1192 } 1193 // fold !(x or y) -> (!x and !y) iff x or y are setcc 1194 if (N1C && N1C->getValue() == 1 && 1195 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 1196 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1); 1197 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) { 1198 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 1199 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS 1200 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS 1201 WorkList.push_back(LHS.Val); WorkList.push_back(RHS.Val); 1202 return DAG.getNode(NewOpcode, VT, LHS, RHS); 1203 } 1204 } 1205 // fold !(x or y) -> (!x and !y) iff x or y are constants 1206 if (N1C && N1C->isAllOnesValue() && 1207 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 1208 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1); 1209 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) { 1210 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 1211 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS 1212 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS 1213 WorkList.push_back(LHS.Val); WorkList.push_back(RHS.Val); 1214 return DAG.getNode(NewOpcode, VT, LHS, RHS); 1215 } 1216 } 1217 // fold (xor (xor x, c1), c2) -> (xor x, c1^c2) 1218 if (N1C && N0.getOpcode() == ISD::XOR) { 1219 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0)); 1220 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 1221 if (N00C) 1222 return DAG.getNode(ISD::XOR, VT, N0.getOperand(1), 1223 DAG.getConstant(N1C->getValue()^N00C->getValue(), VT)); 1224 if (N01C) 1225 return DAG.getNode(ISD::XOR, VT, N0.getOperand(0), 1226 DAG.getConstant(N1C->getValue()^N01C->getValue(), VT)); 1227 } 1228 // fold (xor x, x) -> 0 1229 if (N0 == N1) 1230 return DAG.getConstant(0, VT); 1231 // fold (xor (zext x), (zext y)) -> (zext (xor x, y)) 1232 if (N0.getOpcode() == ISD::ZERO_EXTEND && 1233 N1.getOpcode() == ISD::ZERO_EXTEND && 1234 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) { 1235 SDOperand XORNode = DAG.getNode(ISD::XOR, N0.getOperand(0).getValueType(), 1236 N0.getOperand(0), N1.getOperand(0)); 1237 WorkList.push_back(XORNode.Val); 1238 return DAG.getNode(ISD::ZERO_EXTEND, VT, XORNode); 1239 } 1240 return SDOperand(); 1241} 1242 1243SDOperand DAGCombiner::visitSHL(SDNode *N) { 1244 SDOperand N0 = N->getOperand(0); 1245 SDOperand N1 = N->getOperand(1); 1246 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1247 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1248 MVT::ValueType VT = N0.getValueType(); 1249 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 1250 1251 // fold (shl c1, c2) -> c1<<c2 1252 if (N0C && N1C) 1253 return DAG.getConstant(N0C->getValue() << N1C->getValue(), VT); 1254 // fold (shl 0, x) -> 0 1255 if (N0C && N0C->isNullValue()) 1256 return N0; 1257 // fold (shl x, c >= size(x)) -> undef 1258 if (N1C && N1C->getValue() >= OpSizeInBits) 1259 return DAG.getNode(ISD::UNDEF, VT); 1260 // fold (shl x, 0) -> x 1261 if (N1C && N1C->isNullValue()) 1262 return N0; 1263 // if (shl x, c) is known to be zero, return 0 1264 if (N1C && MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits),TLI)) 1265 return DAG.getConstant(0, VT); 1266 // fold (shl (shl x, c1), c2) -> 0 or (shl x, c1+c2) 1267 if (N1C && N0.getOpcode() == ISD::SHL && 1268 N0.getOperand(1).getOpcode() == ISD::Constant) { 1269 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 1270 uint64_t c2 = N1C->getValue(); 1271 if (c1 + c2 > OpSizeInBits) 1272 return DAG.getConstant(0, VT); 1273 return DAG.getNode(ISD::SHL, VT, N0.getOperand(0), 1274 DAG.getConstant(c1 + c2, N1.getValueType())); 1275 } 1276 // fold (shl (srl x, c1), c2) -> (shl (and x, -1 << c1), c2-c1) or 1277 // (srl (and x, -1 << c1), c1-c2) 1278 if (N1C && N0.getOpcode() == ISD::SRL && 1279 N0.getOperand(1).getOpcode() == ISD::Constant) { 1280 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 1281 uint64_t c2 = N1C->getValue(); 1282 SDOperand Mask = DAG.getNode(ISD::AND, VT, N0.getOperand(0), 1283 DAG.getConstant(~0ULL << c1, VT)); 1284 if (c2 > c1) 1285 return DAG.getNode(ISD::SHL, VT, Mask, 1286 DAG.getConstant(c2-c1, N1.getValueType())); 1287 else 1288 return DAG.getNode(ISD::SRL, VT, Mask, 1289 DAG.getConstant(c1-c2, N1.getValueType())); 1290 } 1291 // fold (shl (sra x, c1), c1) -> (and x, -1 << c1) 1292 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) 1293 return DAG.getNode(ISD::AND, VT, N0.getOperand(0), 1294 DAG.getConstant(~0ULL << N1C->getValue(), VT)); 1295 return SDOperand(); 1296} 1297 1298SDOperand DAGCombiner::visitSRA(SDNode *N) { 1299 SDOperand N0 = N->getOperand(0); 1300 SDOperand N1 = N->getOperand(1); 1301 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1302 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1303 MVT::ValueType VT = N0.getValueType(); 1304 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 1305 1306 // fold (sra c1, c2) -> c1>>c2 1307 if (N0C && N1C) 1308 return DAG.getConstant(N0C->getSignExtended() >> N1C->getValue(), VT); 1309 // fold (sra 0, x) -> 0 1310 if (N0C && N0C->isNullValue()) 1311 return N0; 1312 // fold (sra -1, x) -> -1 1313 if (N0C && N0C->isAllOnesValue()) 1314 return N0; 1315 // fold (sra x, c >= size(x)) -> undef 1316 if (N1C && N1C->getValue() >= OpSizeInBits) 1317 return DAG.getNode(ISD::UNDEF, VT); 1318 // fold (sra x, 0) -> x 1319 if (N1C && N1C->isNullValue()) 1320 return N0; 1321 // If the sign bit is known to be zero, switch this to a SRL. 1322 if (MaskedValueIsZero(N0, (1ULL << (OpSizeInBits-1)), TLI)) 1323 return DAG.getNode(ISD::SRL, VT, N0, N1); 1324 return SDOperand(); 1325} 1326 1327SDOperand DAGCombiner::visitSRL(SDNode *N) { 1328 SDOperand N0 = N->getOperand(0); 1329 SDOperand N1 = N->getOperand(1); 1330 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1331 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1332 MVT::ValueType VT = N0.getValueType(); 1333 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 1334 1335 // fold (srl c1, c2) -> c1 >>u c2 1336 if (N0C && N1C) 1337 return DAG.getConstant(N0C->getValue() >> N1C->getValue(), VT); 1338 // fold (srl 0, x) -> 0 1339 if (N0C && N0C->isNullValue()) 1340 return N0; 1341 // fold (srl x, c >= size(x)) -> undef 1342 if (N1C && N1C->getValue() >= OpSizeInBits) 1343 return DAG.getNode(ISD::UNDEF, VT); 1344 // fold (srl x, 0) -> x 1345 if (N1C && N1C->isNullValue()) 1346 return N0; 1347 // if (srl x, c) is known to be zero, return 0 1348 if (N1C && MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits),TLI)) 1349 return DAG.getConstant(0, VT); 1350 // fold (srl (srl x, c1), c2) -> 0 or (srl x, c1+c2) 1351 if (N1C && N0.getOpcode() == ISD::SRL && 1352 N0.getOperand(1).getOpcode() == ISD::Constant) { 1353 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 1354 uint64_t c2 = N1C->getValue(); 1355 if (c1 + c2 > OpSizeInBits) 1356 return DAG.getConstant(0, VT); 1357 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0), 1358 DAG.getConstant(c1 + c2, N1.getValueType())); 1359 } 1360 return SDOperand(); 1361} 1362 1363SDOperand DAGCombiner::visitCTLZ(SDNode *N) { 1364 SDOperand N0 = N->getOperand(0); 1365 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1366 1367 // fold (ctlz c1) -> c2 1368 if (N0C) 1369 return DAG.getConstant(CountLeadingZeros_64(N0C->getValue()), 1370 N0.getValueType()); 1371 return SDOperand(); 1372} 1373 1374SDOperand DAGCombiner::visitCTTZ(SDNode *N) { 1375 SDOperand N0 = N->getOperand(0); 1376 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1377 1378 // fold (cttz c1) -> c2 1379 if (N0C) 1380 return DAG.getConstant(CountTrailingZeros_64(N0C->getValue()), 1381 N0.getValueType()); 1382 return SDOperand(); 1383} 1384 1385SDOperand DAGCombiner::visitCTPOP(SDNode *N) { 1386 SDOperand N0 = N->getOperand(0); 1387 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1388 1389 // fold (ctpop c1) -> c2 1390 if (N0C) 1391 return DAG.getConstant(CountPopulation_64(N0C->getValue()), 1392 N0.getValueType()); 1393 return SDOperand(); 1394} 1395 1396SDOperand DAGCombiner::visitSELECT(SDNode *N) { 1397 SDOperand N0 = N->getOperand(0); 1398 SDOperand N1 = N->getOperand(1); 1399 SDOperand N2 = N->getOperand(2); 1400 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1401 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1402 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2); 1403 MVT::ValueType VT = N->getValueType(0); 1404 1405 // fold select C, X, X -> X 1406 if (N1 == N2) 1407 return N1; 1408 // fold select true, X, Y -> X 1409 if (N0C && !N0C->isNullValue()) 1410 return N1; 1411 // fold select false, X, Y -> Y 1412 if (N0C && N0C->isNullValue()) 1413 return N2; 1414 // fold select C, 1, X -> C | X 1415 if (MVT::i1 == VT && N1C && N1C->getValue() == 1) 1416 return DAG.getNode(ISD::OR, VT, N0, N2); 1417 // fold select C, 0, X -> ~C & X 1418 // FIXME: this should check for C type == X type, not i1? 1419 if (MVT::i1 == VT && N1C && N1C->isNullValue()) { 1420 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT)); 1421 WorkList.push_back(XORNode.Val); 1422 return DAG.getNode(ISD::AND, VT, XORNode, N2); 1423 } 1424 // fold select C, X, 1 -> ~C | X 1425 if (MVT::i1 == VT && N2C && N2C->getValue() == 1) { 1426 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT)); 1427 WorkList.push_back(XORNode.Val); 1428 return DAG.getNode(ISD::OR, VT, XORNode, N1); 1429 } 1430 // fold select C, X, 0 -> C & X 1431 // FIXME: this should check for C type == X type, not i1? 1432 if (MVT::i1 == VT && N2C && N2C->isNullValue()) 1433 return DAG.getNode(ISD::AND, VT, N0, N1); 1434 // fold X ? X : Y --> X ? 1 : Y --> X | Y 1435 if (MVT::i1 == VT && N0 == N1) 1436 return DAG.getNode(ISD::OR, VT, N0, N2); 1437 // fold X ? Y : X --> X ? Y : 0 --> X & Y 1438 if (MVT::i1 == VT && N0 == N2) 1439 return DAG.getNode(ISD::AND, VT, N0, N1); 1440 1441 // If we can fold this based on the true/false value, do so. 1442 if (SimplifySelectOps(N, N1, N2)) 1443 return SDOperand(); 1444 1445 // fold selects based on a setcc into other things, such as min/max/abs 1446 if (N0.getOpcode() == ISD::SETCC) 1447 return SimplifySelect(N0, N1, N2); 1448 return SDOperand(); 1449} 1450 1451SDOperand DAGCombiner::visitSELECT_CC(SDNode *N) { 1452 SDOperand N0 = N->getOperand(0); 1453 SDOperand N1 = N->getOperand(1); 1454 SDOperand N2 = N->getOperand(2); 1455 SDOperand N3 = N->getOperand(3); 1456 SDOperand N4 = N->getOperand(4); 1457 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1458 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1459 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2); 1460 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get(); 1461 1462 // Determine if the condition we're dealing with is constant 1463 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false); 1464 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val); 1465 1466 // fold select_cc lhs, rhs, x, x, cc -> x 1467 if (N2 == N3) 1468 return N2; 1469 1470 // If we can fold this based on the true/false value, do so. 1471 if (SimplifySelectOps(N, N2, N3)) 1472 return SDOperand(); 1473 1474 // fold select_cc into other things, such as min/max/abs 1475 return SimplifySelectCC(N0, N1, N2, N3, CC); 1476} 1477 1478SDOperand DAGCombiner::visitSETCC(SDNode *N) { 1479 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1), 1480 cast<CondCodeSDNode>(N->getOperand(2))->get()); 1481} 1482 1483SDOperand DAGCombiner::visitADD_PARTS(SDNode *N) { 1484 SDOperand LHSLo = N->getOperand(0); 1485 SDOperand RHSLo = N->getOperand(2); 1486 MVT::ValueType VT = LHSLo.getValueType(); 1487 1488 // fold (a_Hi, 0) + (b_Hi, b_Lo) -> (b_Hi + a_Hi, b_Lo) 1489 if (MaskedValueIsZero(LHSLo, (1ULL << MVT::getSizeInBits(VT))-1, TLI)) { 1490 SDOperand Hi = DAG.getNode(ISD::ADD, VT, N->getOperand(1), 1491 N->getOperand(3)); 1492 WorkList.push_back(Hi.Val); 1493 CombineTo(N, RHSLo, Hi); 1494 return SDOperand(); 1495 } 1496 // fold (a_Hi, a_Lo) + (b_Hi, 0) -> (a_Hi + b_Hi, a_Lo) 1497 if (MaskedValueIsZero(RHSLo, (1ULL << MVT::getSizeInBits(VT))-1, TLI)) { 1498 SDOperand Hi = DAG.getNode(ISD::ADD, VT, N->getOperand(1), 1499 N->getOperand(3)); 1500 WorkList.push_back(Hi.Val); 1501 CombineTo(N, LHSLo, Hi); 1502 return SDOperand(); 1503 } 1504 return SDOperand(); 1505} 1506 1507SDOperand DAGCombiner::visitSUB_PARTS(SDNode *N) { 1508 SDOperand LHSLo = N->getOperand(0); 1509 SDOperand RHSLo = N->getOperand(2); 1510 MVT::ValueType VT = LHSLo.getValueType(); 1511 1512 // fold (a_Hi, a_Lo) - (b_Hi, 0) -> (a_Hi - b_Hi, a_Lo) 1513 if (MaskedValueIsZero(RHSLo, (1ULL << MVT::getSizeInBits(VT))-1, TLI)) { 1514 SDOperand Hi = DAG.getNode(ISD::SUB, VT, N->getOperand(1), 1515 N->getOperand(3)); 1516 WorkList.push_back(Hi.Val); 1517 CombineTo(N, LHSLo, Hi); 1518 return SDOperand(); 1519 } 1520 return SDOperand(); 1521} 1522 1523SDOperand DAGCombiner::visitSIGN_EXTEND(SDNode *N) { 1524 SDOperand N0 = N->getOperand(0); 1525 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1526 MVT::ValueType VT = N->getValueType(0); 1527 1528 // fold (sext c1) -> c1 1529 if (N0C) 1530 return DAG.getConstant(N0C->getSignExtended(), VT); 1531 // fold (sext (sext x)) -> (sext x) 1532 if (N0.getOpcode() == ISD::SIGN_EXTEND) 1533 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0.getOperand(0)); 1534 // fold (sext (sextload x)) -> (sextload x) 1535 if (N0.getOpcode() == ISD::SEXTLOAD && VT == N0.getValueType()) 1536 return N0; 1537 // fold (sext (load x)) -> (sextload x) 1538 if (N0.getOpcode() == ISD::LOAD && N0.hasOneUse()) { 1539 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N0.getOperand(0), 1540 N0.getOperand(1), N0.getOperand(2), 1541 N0.getValueType()); 1542 WorkList.push_back(N); 1543 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 1544 ExtLoad.getValue(1)); 1545 return SDOperand(); 1546 } 1547 return SDOperand(); 1548} 1549 1550SDOperand DAGCombiner::visitZERO_EXTEND(SDNode *N) { 1551 SDOperand N0 = N->getOperand(0); 1552 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1553 MVT::ValueType VT = N->getValueType(0); 1554 1555 // fold (zext c1) -> c1 1556 if (N0C) 1557 return DAG.getConstant(N0C->getValue(), VT); 1558 // fold (zext (zext x)) -> (zext x) 1559 if (N0.getOpcode() == ISD::ZERO_EXTEND) 1560 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0.getOperand(0)); 1561 return SDOperand(); 1562} 1563 1564SDOperand DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) { 1565 SDOperand N0 = N->getOperand(0); 1566 SDOperand N1 = N->getOperand(1); 1567 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1568 MVT::ValueType VT = N->getValueType(0); 1569 MVT::ValueType EVT = cast<VTSDNode>(N1)->getVT(); 1570 unsigned EVTBits = MVT::getSizeInBits(EVT); 1571 1572 // fold (sext_in_reg c1) -> c1 1573 if (N0C) { 1574 SDOperand Truncate = DAG.getConstant(N0C->getValue(), EVT); 1575 return DAG.getNode(ISD::SIGN_EXTEND, VT, Truncate); 1576 } 1577 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt1 1578 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 1579 cast<VTSDNode>(N0.getOperand(1))->getVT() <= EVT) { 1580 return N0; 1581 } 1582 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2 1583 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 1584 EVT < cast<VTSDNode>(N0.getOperand(1))->getVT()) { 1585 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), N1); 1586 } 1587 // fold (sext_in_reg (assert_sext x)) -> (assert_sext x) 1588 if (N0.getOpcode() == ISD::AssertSext && 1589 cast<VTSDNode>(N0.getOperand(1))->getVT() <= EVT) { 1590 return N0; 1591 } 1592 // fold (sext_in_reg (sextload x)) -> (sextload x) 1593 if (N0.getOpcode() == ISD::SEXTLOAD && 1594 cast<VTSDNode>(N0.getOperand(3))->getVT() <= EVT) { 1595 return N0; 1596 } 1597 // fold (sext_in_reg (setcc x)) -> setcc x iff (setcc x) == 0 or -1 1598 if (N0.getOpcode() == ISD::SETCC && 1599 TLI.getSetCCResultContents() == 1600 TargetLowering::ZeroOrNegativeOneSetCCResult) 1601 return N0; 1602 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is zero 1603 if (MaskedValueIsZero(N0, 1ULL << (EVTBits-1), TLI)) 1604 return DAG.getNode(ISD::AND, N0.getValueType(), N0, 1605 DAG.getConstant(~0ULL >> (64-EVTBits), VT)); 1606 // fold (sext_in_reg (srl x)) -> sra x 1607 if (N0.getOpcode() == ISD::SRL && 1608 N0.getOperand(1).getOpcode() == ISD::Constant && 1609 cast<ConstantSDNode>(N0.getOperand(1))->getValue() == EVTBits) { 1610 return DAG.getNode(ISD::SRA, N0.getValueType(), N0.getOperand(0), 1611 N0.getOperand(1)); 1612 } 1613 // fold (sext_inreg (extload x)) -> (sextload x) 1614 if (N0.getOpcode() == ISD::EXTLOAD && 1615 EVT == cast<VTSDNode>(N0.getOperand(3))->getVT() && 1616 (!AfterLegalize || TLI.isOperationLegal(ISD::SEXTLOAD, EVT))) { 1617 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N0.getOperand(0), 1618 N0.getOperand(1), N0.getOperand(2), 1619 EVT); 1620 WorkList.push_back(N); 1621 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 1622 return SDOperand(); 1623 } 1624 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use 1625 if (N0.getOpcode() == ISD::ZEXTLOAD && N0.hasOneUse() && 1626 EVT == cast<VTSDNode>(N0.getOperand(3))->getVT() && 1627 (!AfterLegalize || TLI.isOperationLegal(ISD::SEXTLOAD, EVT))) { 1628 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N0.getOperand(0), 1629 N0.getOperand(1), N0.getOperand(2), 1630 EVT); 1631 WorkList.push_back(N); 1632 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 1633 return SDOperand(); 1634 } 1635 return SDOperand(); 1636} 1637 1638SDOperand DAGCombiner::visitTRUNCATE(SDNode *N) { 1639 SDOperand N0 = N->getOperand(0); 1640 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1641 MVT::ValueType VT = N->getValueType(0); 1642 1643 // noop truncate 1644 if (N0.getValueType() == N->getValueType(0)) 1645 return N0; 1646 // fold (truncate c1) -> c1 1647 if (N0C) 1648 return DAG.getConstant(N0C->getValue(), VT); 1649 // fold (truncate (truncate x)) -> (truncate x) 1650 if (N0.getOpcode() == ISD::TRUNCATE) 1651 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0)); 1652 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x 1653 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::SIGN_EXTEND){ 1654 if (N0.getValueType() < VT) 1655 // if the source is smaller than the dest, we still need an extend 1656 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0)); 1657 else if (N0.getValueType() > VT) 1658 // if the source is larger than the dest, than we just need the truncate 1659 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0)); 1660 else 1661 // if the source and dest are the same type, we can drop both the extend 1662 // and the truncate 1663 return N0.getOperand(0); 1664 } 1665 // fold (truncate (load x)) -> (smaller load x) 1666 if (N0.getOpcode() == ISD::LOAD && N0.hasOneUse()) { 1667 assert(MVT::getSizeInBits(N0.getValueType()) > MVT::getSizeInBits(VT) && 1668 "Cannot truncate to larger type!"); 1669 MVT::ValueType PtrType = N0.getOperand(1).getValueType(); 1670 // For big endian targets, we need to add an offset to the pointer to load 1671 // the correct bytes. For little endian systems, we merely need to read 1672 // fewer bytes from the same pointer. 1673 uint64_t PtrOff = 1674 (MVT::getSizeInBits(N0.getValueType()) - MVT::getSizeInBits(VT)) / 8; 1675 SDOperand NewPtr = TLI.isLittleEndian() ? N0.getOperand(1) : 1676 DAG.getNode(ISD::ADD, PtrType, N0.getOperand(1), 1677 DAG.getConstant(PtrOff, PtrType)); 1678 WorkList.push_back(NewPtr.Val); 1679 SDOperand Load = DAG.getLoad(VT, N0.getOperand(0), NewPtr,N0.getOperand(2)); 1680 WorkList.push_back(N); 1681 CombineTo(N0.Val, Load, Load.getValue(1)); 1682 return SDOperand(); 1683 } 1684 return SDOperand(); 1685} 1686 1687SDOperand DAGCombiner::visitFADD(SDNode *N) { 1688 SDOperand N0 = N->getOperand(0); 1689 SDOperand N1 = N->getOperand(1); 1690 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 1691 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 1692 MVT::ValueType VT = N->getValueType(0); 1693 1694 // fold (fadd c1, c2) -> c1+c2 1695 if (N0CFP && N1CFP) 1696 return DAG.getConstantFP(N0CFP->getValue() + N1CFP->getValue(), VT); 1697 // canonicalize constant to RHS 1698 if (N0CFP && !N1CFP) 1699 return DAG.getNode(ISD::FADD, VT, N1, N0); 1700 // fold (A + (-B)) -> A-B 1701 if (N1.getOpcode() == ISD::FNEG) 1702 return DAG.getNode(ISD::FSUB, VT, N0, N1.getOperand(0)); 1703 // fold ((-A) + B) -> B-A 1704 if (N0.getOpcode() == ISD::FNEG) 1705 return DAG.getNode(ISD::FSUB, VT, N1, N0.getOperand(0)); 1706 return SDOperand(); 1707} 1708 1709SDOperand DAGCombiner::visitFSUB(SDNode *N) { 1710 SDOperand N0 = N->getOperand(0); 1711 SDOperand N1 = N->getOperand(1); 1712 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 1713 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 1714 MVT::ValueType VT = N->getValueType(0); 1715 1716 // fold (fsub c1, c2) -> c1-c2 1717 if (N0CFP && N1CFP) 1718 return DAG.getConstantFP(N0CFP->getValue() - N1CFP->getValue(), VT); 1719 // fold (A-(-B)) -> A+B 1720 if (N1.getOpcode() == ISD::FNEG) 1721 return DAG.getNode(ISD::FADD, N0.getValueType(), N0, N1.getOperand(0)); 1722 return SDOperand(); 1723} 1724 1725SDOperand DAGCombiner::visitFMUL(SDNode *N) { 1726 SDOperand N0 = N->getOperand(0); 1727 SDOperand N1 = N->getOperand(1); 1728 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 1729 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 1730 MVT::ValueType VT = N->getValueType(0); 1731 1732 // fold (fmul c1, c2) -> c1*c2 1733 if (N0CFP && N1CFP) 1734 return DAG.getConstantFP(N0CFP->getValue() * N1CFP->getValue(), VT); 1735 // canonicalize constant to RHS 1736 if (N0CFP && !N1CFP) 1737 return DAG.getNode(ISD::FMUL, VT, N1, N0); 1738 // fold (fmul X, 2.0) -> (fadd X, X) 1739 if (N1CFP && N1CFP->isExactlyValue(+2.0)) 1740 return DAG.getNode(ISD::FADD, VT, N0, N0); 1741 return SDOperand(); 1742} 1743 1744SDOperand DAGCombiner::visitFDIV(SDNode *N) { 1745 SDOperand N0 = N->getOperand(0); 1746 SDOperand N1 = N->getOperand(1); 1747 MVT::ValueType VT = N->getValueType(0); 1748 1749 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0)) 1750 if (ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1)) { 1751 // fold floating point (fdiv c1, c2) 1752 return DAG.getConstantFP(N0CFP->getValue() / N1CFP->getValue(), VT); 1753 } 1754 return SDOperand(); 1755} 1756 1757SDOperand DAGCombiner::visitFREM(SDNode *N) { 1758 SDOperand N0 = N->getOperand(0); 1759 SDOperand N1 = N->getOperand(1); 1760 MVT::ValueType VT = N->getValueType(0); 1761 1762 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0)) 1763 if (ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1)) { 1764 // fold floating point (frem c1, c2) -> fmod(c1, c2) 1765 return DAG.getConstantFP(fmod(N0CFP->getValue(),N1CFP->getValue()), VT); 1766 } 1767 return SDOperand(); 1768} 1769 1770 1771SDOperand DAGCombiner::visitSINT_TO_FP(SDNode *N) { 1772 SDOperand N0 = N->getOperand(0); 1773 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1774 1775 // fold (sint_to_fp c1) -> c1fp 1776 if (N0C) 1777 return DAG.getConstantFP(N0C->getSignExtended(), N->getValueType(0)); 1778 return SDOperand(); 1779} 1780 1781SDOperand DAGCombiner::visitUINT_TO_FP(SDNode *N) { 1782 SDOperand N0 = N->getOperand(0); 1783 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1784 1785 // fold (uint_to_fp c1) -> c1fp 1786 if (N0C) 1787 return DAG.getConstantFP(N0C->getValue(), N->getValueType(0)); 1788 return SDOperand(); 1789} 1790 1791SDOperand DAGCombiner::visitFP_TO_SINT(SDNode *N) { 1792 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0)); 1793 1794 // fold (fp_to_sint c1fp) -> c1 1795 if (N0CFP) 1796 return DAG.getConstant((int64_t)N0CFP->getValue(), N->getValueType(0)); 1797 return SDOperand(); 1798} 1799 1800SDOperand DAGCombiner::visitFP_TO_UINT(SDNode *N) { 1801 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0)); 1802 1803 // fold (fp_to_uint c1fp) -> c1 1804 if (N0CFP) 1805 return DAG.getConstant((uint64_t)N0CFP->getValue(), N->getValueType(0)); 1806 return SDOperand(); 1807} 1808 1809SDOperand DAGCombiner::visitFP_ROUND(SDNode *N) { 1810 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0)); 1811 1812 // fold (fp_round c1fp) -> c1fp 1813 if (N0CFP) 1814 return DAG.getConstantFP(N0CFP->getValue(), N->getValueType(0)); 1815 return SDOperand(); 1816} 1817 1818SDOperand DAGCombiner::visitFP_ROUND_INREG(SDNode *N) { 1819 SDOperand N0 = N->getOperand(0); 1820 MVT::ValueType VT = N->getValueType(0); 1821 MVT::ValueType EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 1822 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 1823 1824 // fold (fp_round_inreg c1fp) -> c1fp 1825 if (N0CFP) { 1826 SDOperand Round = DAG.getConstantFP(N0CFP->getValue(), EVT); 1827 return DAG.getNode(ISD::FP_EXTEND, VT, Round); 1828 } 1829 return SDOperand(); 1830} 1831 1832SDOperand DAGCombiner::visitFP_EXTEND(SDNode *N) { 1833 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0)); 1834 1835 // fold (fp_extend c1fp) -> c1fp 1836 if (N0CFP) 1837 return DAG.getConstantFP(N0CFP->getValue(), N->getValueType(0)); 1838 return SDOperand(); 1839} 1840 1841SDOperand DAGCombiner::visitFNEG(SDNode *N) { 1842 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0)); 1843 // fold (neg c1) -> -c1 1844 if (N0CFP) 1845 return DAG.getConstantFP(-N0CFP->getValue(), N->getValueType(0)); 1846 // fold (neg (sub x, y)) -> (sub y, x) 1847 if (N->getOperand(0).getOpcode() == ISD::SUB) 1848 return DAG.getNode(ISD::SUB, N->getValueType(0), N->getOperand(1), 1849 N->getOperand(0)); 1850 // fold (neg (neg x)) -> x 1851 if (N->getOperand(0).getOpcode() == ISD::FNEG) 1852 return N->getOperand(0).getOperand(0); 1853 return SDOperand(); 1854} 1855 1856SDOperand DAGCombiner::visitFABS(SDNode *N) { 1857 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0)); 1858 // fold (fabs c1) -> fabs(c1) 1859 if (N0CFP) 1860 return DAG.getConstantFP(fabs(N0CFP->getValue()), N->getValueType(0)); 1861 // fold (fabs (fabs x)) -> (fabs x) 1862 if (N->getOperand(0).getOpcode() == ISD::FABS) 1863 return N->getOperand(0); 1864 // fold (fabs (fneg x)) -> (fabs x) 1865 if (N->getOperand(0).getOpcode() == ISD::FNEG) 1866 return DAG.getNode(ISD::FABS, N->getValueType(0), 1867 N->getOperand(0).getOperand(0)); 1868 return SDOperand(); 1869} 1870 1871SDOperand DAGCombiner::visitBRCOND(SDNode *N) { 1872 SDOperand Chain = N->getOperand(0); 1873 SDOperand N1 = N->getOperand(1); 1874 SDOperand N2 = N->getOperand(2); 1875 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1876 1877 // never taken branch, fold to chain 1878 if (N1C && N1C->isNullValue()) 1879 return Chain; 1880 // unconditional branch 1881 if (N1C && N1C->getValue() == 1) 1882 return DAG.getNode(ISD::BR, MVT::Other, Chain, N2); 1883 return SDOperand(); 1884} 1885 1886SDOperand DAGCombiner::visitBRCONDTWOWAY(SDNode *N) { 1887 SDOperand Chain = N->getOperand(0); 1888 SDOperand N1 = N->getOperand(1); 1889 SDOperand N2 = N->getOperand(2); 1890 SDOperand N3 = N->getOperand(3); 1891 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1892 1893 // unconditional branch to true mbb 1894 if (N1C && N1C->getValue() == 1) 1895 return DAG.getNode(ISD::BR, MVT::Other, Chain, N2); 1896 // unconditional branch to false mbb 1897 if (N1C && N1C->isNullValue()) 1898 return DAG.getNode(ISD::BR, MVT::Other, Chain, N3); 1899 return SDOperand(); 1900} 1901 1902// Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB. 1903// 1904SDOperand DAGCombiner::visitBR_CC(SDNode *N) { 1905 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1)); 1906 SDOperand CondLHS = N->getOperand(2), CondRHS = N->getOperand(3); 1907 1908 // Use SimplifySetCC to simplify SETCC's. 1909 SDOperand Simp = SimplifySetCC(MVT::i1, CondLHS, CondRHS, CC->get(), false); 1910 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(Simp.Val); 1911 1912 // fold br_cc true, dest -> br dest (unconditional branch) 1913 if (SCCC && SCCC->getValue()) 1914 return DAG.getNode(ISD::BR, MVT::Other, N->getOperand(0), 1915 N->getOperand(4)); 1916 // fold br_cc false, dest -> unconditional fall through 1917 if (SCCC && SCCC->isNullValue()) 1918 return N->getOperand(0); 1919 // fold to a simpler setcc 1920 if (Simp.Val && Simp.getOpcode() == ISD::SETCC) 1921 return DAG.getNode(ISD::BR_CC, MVT::Other, N->getOperand(0), 1922 Simp.getOperand(2), Simp.getOperand(0), 1923 Simp.getOperand(1), N->getOperand(4)); 1924 return SDOperand(); 1925} 1926 1927SDOperand DAGCombiner::visitBRTWOWAY_CC(SDNode *N) { 1928 SDOperand Chain = N->getOperand(0); 1929 SDOperand CCN = N->getOperand(1); 1930 SDOperand LHS = N->getOperand(2); 1931 SDOperand RHS = N->getOperand(3); 1932 SDOperand N4 = N->getOperand(4); 1933 SDOperand N5 = N->getOperand(5); 1934 1935 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), LHS, RHS, 1936 cast<CondCodeSDNode>(CCN)->get(), false); 1937 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val); 1938 1939 // fold select_cc lhs, rhs, x, x, cc -> x 1940 if (N4 == N5) 1941 return DAG.getNode(ISD::BR, MVT::Other, Chain, N4); 1942 // fold select_cc true, x, y -> x 1943 if (SCCC && SCCC->getValue()) 1944 return DAG.getNode(ISD::BR, MVT::Other, Chain, N4); 1945 // fold select_cc false, x, y -> y 1946 if (SCCC && SCCC->isNullValue()) 1947 return DAG.getNode(ISD::BR, MVT::Other, Chain, N5); 1948 // fold to a simpler setcc 1949 if (SCC.Val && SCC.getOpcode() == ISD::SETCC) 1950 return DAG.getBR2Way_CC(Chain, SCC.getOperand(2), SCC.getOperand(0), 1951 SCC.getOperand(1), N4, N5); 1952 return SDOperand(); 1953} 1954 1955SDOperand DAGCombiner::visitLOAD(SDNode *N) { 1956 SDOperand Chain = N->getOperand(0); 1957 SDOperand Ptr = N->getOperand(1); 1958 SDOperand SrcValue = N->getOperand(2); 1959 1960 // If this load is directly stored, replace the load value with the stored 1961 // value. 1962 // TODO: Handle store large -> read small portion. 1963 // TODO: Handle TRUNCSTORE/EXTLOAD 1964 if (Chain.getOpcode() == ISD::STORE && Chain.getOperand(2) == Ptr && 1965 Chain.getOperand(1).getValueType() == N->getValueType(0)) 1966 return CombineTo(N, Chain.getOperand(1), Chain); 1967 1968 return SDOperand(); 1969} 1970 1971SDOperand DAGCombiner::visitSTORE(SDNode *N) { 1972 SDOperand Chain = N->getOperand(0); 1973 SDOperand Value = N->getOperand(1); 1974 SDOperand Ptr = N->getOperand(2); 1975 SDOperand SrcValue = N->getOperand(3); 1976 1977 // If this is a store that kills a previous store, remove the previous store. 1978 if (Chain.getOpcode() == ISD::STORE && Chain.getOperand(2) == Ptr && 1979 Chain.Val->hasOneUse() /* Avoid introducing DAG cycles */) { 1980 // Create a new store of Value that replaces both stores. 1981 SDNode *PrevStore = Chain.Val; 1982 if (PrevStore->getOperand(1) == Value) // Same value multiply stored. 1983 return Chain; 1984 SDOperand NewStore = DAG.getNode(ISD::STORE, MVT::Other, 1985 PrevStore->getOperand(0), Value, Ptr, 1986 SrcValue); 1987 CombineTo(N, NewStore); // Nuke this store. 1988 CombineTo(PrevStore, NewStore); // Nuke the previous store. 1989 return SDOperand(N, 0); 1990 } 1991 1992 return SDOperand(); 1993} 1994 1995SDOperand DAGCombiner::SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2){ 1996 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!"); 1997 1998 SDOperand SCC = SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), N1, N2, 1999 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 2000 // If we got a simplified select_cc node back from SimplifySelectCC, then 2001 // break it down into a new SETCC node, and a new SELECT node, and then return 2002 // the SELECT node, since we were called with a SELECT node. 2003 if (SCC.Val) { 2004 // Check to see if we got a select_cc back (to turn into setcc/select). 2005 // Otherwise, just return whatever node we got back, like fabs. 2006 if (SCC.getOpcode() == ISD::SELECT_CC) { 2007 SDOperand SETCC = DAG.getNode(ISD::SETCC, N0.getValueType(), 2008 SCC.getOperand(0), SCC.getOperand(1), 2009 SCC.getOperand(4)); 2010 WorkList.push_back(SETCC.Val); 2011 return DAG.getNode(ISD::SELECT, SCC.getValueType(), SCC.getOperand(2), 2012 SCC.getOperand(3), SETCC); 2013 } 2014 return SCC; 2015 } 2016 return SDOperand(); 2017} 2018 2019/// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS 2020/// are the two values being selected between, see if we can simplify the 2021/// select. 2022/// 2023bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDOperand LHS, 2024 SDOperand RHS) { 2025 2026 // If this is a select from two identical things, try to pull the operation 2027 // through the select. 2028 if (LHS.getOpcode() == RHS.getOpcode() && LHS.hasOneUse() && RHS.hasOneUse()){ 2029#if 0 2030 std::cerr << "SELECT: ["; LHS.Val->dump(); 2031 std::cerr << "] ["; RHS.Val->dump(); 2032 std::cerr << "]\n"; 2033#endif 2034 2035 // If this is a load and the token chain is identical, replace the select 2036 // of two loads with a load through a select of the address to load from. 2037 // This triggers in things like "select bool X, 10.0, 123.0" after the FP 2038 // constants have been dropped into the constant pool. 2039 if ((LHS.getOpcode() == ISD::LOAD || 2040 LHS.getOpcode() == ISD::EXTLOAD || 2041 LHS.getOpcode() == ISD::ZEXTLOAD || 2042 LHS.getOpcode() == ISD::SEXTLOAD) && 2043 // Token chains must be identical. 2044 LHS.getOperand(0) == RHS.getOperand(0) && 2045 // If this is an EXTLOAD, the VT's must match. 2046 (LHS.getOpcode() == ISD::LOAD || 2047 LHS.getOperand(3) == RHS.getOperand(3))) { 2048 // FIXME: this conflates two src values, discarding one. This is not 2049 // the right thing to do, but nothing uses srcvalues now. When they do, 2050 // turn SrcValue into a list of locations. 2051 SDOperand Addr; 2052 if (TheSelect->getOpcode() == ISD::SELECT) 2053 Addr = DAG.getNode(ISD::SELECT, LHS.getOperand(1).getValueType(), 2054 TheSelect->getOperand(0), LHS.getOperand(1), 2055 RHS.getOperand(1)); 2056 else 2057 Addr = DAG.getNode(ISD::SELECT_CC, LHS.getOperand(1).getValueType(), 2058 TheSelect->getOperand(0), 2059 TheSelect->getOperand(1), 2060 LHS.getOperand(1), RHS.getOperand(1), 2061 TheSelect->getOperand(4)); 2062 2063 SDOperand Load; 2064 if (LHS.getOpcode() == ISD::LOAD) 2065 Load = DAG.getLoad(TheSelect->getValueType(0), LHS.getOperand(0), 2066 Addr, LHS.getOperand(2)); 2067 else 2068 Load = DAG.getExtLoad(LHS.getOpcode(), TheSelect->getValueType(0), 2069 LHS.getOperand(0), Addr, LHS.getOperand(2), 2070 cast<VTSDNode>(LHS.getOperand(3))->getVT()); 2071 // Users of the select now use the result of the load. 2072 CombineTo(TheSelect, Load); 2073 2074 // Users of the old loads now use the new load's chain. We know the 2075 // old-load value is dead now. 2076 CombineTo(LHS.Val, Load.getValue(0), Load.getValue(1)); 2077 CombineTo(RHS.Val, Load.getValue(0), Load.getValue(1)); 2078 return true; 2079 } 2080 } 2081 2082 return false; 2083} 2084 2085SDOperand DAGCombiner::SimplifySelectCC(SDOperand N0, SDOperand N1, 2086 SDOperand N2, SDOperand N3, 2087 ISD::CondCode CC) { 2088 2089 MVT::ValueType VT = N2.getValueType(); 2090 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 2091 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 2092 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val); 2093 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.Val); 2094 2095 // Determine if the condition we're dealing with is constant 2096 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false); 2097 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val); 2098 2099 // fold select_cc true, x, y -> x 2100 if (SCCC && SCCC->getValue()) 2101 return N2; 2102 // fold select_cc false, x, y -> y 2103 if (SCCC && SCCC->getValue() == 0) 2104 return N3; 2105 2106 // Check to see if we can simplify the select into an fabs node 2107 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) { 2108 // Allow either -0.0 or 0.0 2109 if (CFP->getValue() == 0.0) { 2110 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs 2111 if ((CC == ISD::SETGE || CC == ISD::SETGT) && 2112 N0 == N2 && N3.getOpcode() == ISD::FNEG && 2113 N2 == N3.getOperand(0)) 2114 return DAG.getNode(ISD::FABS, VT, N0); 2115 2116 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs 2117 if ((CC == ISD::SETLT || CC == ISD::SETLE) && 2118 N0 == N3 && N2.getOpcode() == ISD::FNEG && 2119 N2.getOperand(0) == N3) 2120 return DAG.getNode(ISD::FABS, VT, N3); 2121 } 2122 } 2123 2124 // Check to see if we can perform the "gzip trick", transforming 2125 // select_cc setlt X, 0, A, 0 -> and (sra X, size(X)-1), A 2126 if (N1C && N1C->isNullValue() && N3C && N3C->isNullValue() && 2127 MVT::isInteger(N0.getValueType()) && 2128 MVT::isInteger(N2.getValueType()) && CC == ISD::SETLT) { 2129 MVT::ValueType XType = N0.getValueType(); 2130 MVT::ValueType AType = N2.getValueType(); 2131 if (XType >= AType) { 2132 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a 2133 // single-bit constant. 2134 if (N2C && ((N2C->getValue() & (N2C->getValue()-1)) == 0)) { 2135 unsigned ShCtV = Log2_64(N2C->getValue()); 2136 ShCtV = MVT::getSizeInBits(XType)-ShCtV-1; 2137 SDOperand ShCt = DAG.getConstant(ShCtV, TLI.getShiftAmountTy()); 2138 SDOperand Shift = DAG.getNode(ISD::SRL, XType, N0, ShCt); 2139 WorkList.push_back(Shift.Val); 2140 if (XType > AType) { 2141 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift); 2142 WorkList.push_back(Shift.Val); 2143 } 2144 return DAG.getNode(ISD::AND, AType, Shift, N2); 2145 } 2146 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0, 2147 DAG.getConstant(MVT::getSizeInBits(XType)-1, 2148 TLI.getShiftAmountTy())); 2149 WorkList.push_back(Shift.Val); 2150 if (XType > AType) { 2151 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift); 2152 WorkList.push_back(Shift.Val); 2153 } 2154 return DAG.getNode(ISD::AND, AType, Shift, N2); 2155 } 2156 } 2157 2158 // fold select C, 16, 0 -> shl C, 4 2159 if (N2C && N3C && N3C->isNullValue() && isPowerOf2_64(N2C->getValue()) && 2160 TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult) { 2161 // Get a SetCC of the condition 2162 // FIXME: Should probably make sure that setcc is legal if we ever have a 2163 // target where it isn't. 2164 SDOperand Temp, SCC = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC); 2165 WorkList.push_back(SCC.Val); 2166 // cast from setcc result type to select result type 2167 if (AfterLegalize) 2168 Temp = DAG.getZeroExtendInReg(SCC, N2.getValueType()); 2169 else 2170 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC); 2171 WorkList.push_back(Temp.Val); 2172 // shl setcc result by log2 n2c 2173 return DAG.getNode(ISD::SHL, N2.getValueType(), Temp, 2174 DAG.getConstant(Log2_64(N2C->getValue()), 2175 TLI.getShiftAmountTy())); 2176 } 2177 2178 // Check to see if this is the equivalent of setcc 2179 // FIXME: Turn all of these into setcc if setcc if setcc is legal 2180 // otherwise, go ahead with the folds. 2181 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getValue() == 1ULL)) { 2182 MVT::ValueType XType = N0.getValueType(); 2183 if (TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultTy())) { 2184 SDOperand Res = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC); 2185 if (Res.getValueType() != VT) 2186 Res = DAG.getNode(ISD::ZERO_EXTEND, VT, Res); 2187 return Res; 2188 } 2189 2190 // seteq X, 0 -> srl (ctlz X, log2(size(X))) 2191 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ && 2192 TLI.isOperationLegal(ISD::CTLZ, XType)) { 2193 SDOperand Ctlz = DAG.getNode(ISD::CTLZ, XType, N0); 2194 return DAG.getNode(ISD::SRL, XType, Ctlz, 2195 DAG.getConstant(Log2_32(MVT::getSizeInBits(XType)), 2196 TLI.getShiftAmountTy())); 2197 } 2198 // setgt X, 0 -> srl (and (-X, ~X), size(X)-1) 2199 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) { 2200 SDOperand NegN0 = DAG.getNode(ISD::SUB, XType, DAG.getConstant(0, XType), 2201 N0); 2202 SDOperand NotN0 = DAG.getNode(ISD::XOR, XType, N0, 2203 DAG.getConstant(~0ULL, XType)); 2204 return DAG.getNode(ISD::SRL, XType, 2205 DAG.getNode(ISD::AND, XType, NegN0, NotN0), 2206 DAG.getConstant(MVT::getSizeInBits(XType)-1, 2207 TLI.getShiftAmountTy())); 2208 } 2209 // setgt X, -1 -> xor (srl (X, size(X)-1), 1) 2210 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) { 2211 SDOperand Sign = DAG.getNode(ISD::SRL, XType, N0, 2212 DAG.getConstant(MVT::getSizeInBits(XType)-1, 2213 TLI.getShiftAmountTy())); 2214 return DAG.getNode(ISD::XOR, XType, Sign, DAG.getConstant(1, XType)); 2215 } 2216 } 2217 2218 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X -> 2219 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 2220 if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) && 2221 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1)) { 2222 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N2.getOperand(0))) { 2223 MVT::ValueType XType = N0.getValueType(); 2224 if (SubC->isNullValue() && MVT::isInteger(XType)) { 2225 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0, 2226 DAG.getConstant(MVT::getSizeInBits(XType)-1, 2227 TLI.getShiftAmountTy())); 2228 SDOperand Add = DAG.getNode(ISD::ADD, XType, N0, Shift); 2229 WorkList.push_back(Shift.Val); 2230 WorkList.push_back(Add.Val); 2231 return DAG.getNode(ISD::XOR, XType, Add, Shift); 2232 } 2233 } 2234 } 2235 2236 return SDOperand(); 2237} 2238 2239SDOperand DAGCombiner::SimplifySetCC(MVT::ValueType VT, SDOperand N0, 2240 SDOperand N1, ISD::CondCode Cond, 2241 bool foldBooleans) { 2242 // These setcc operations always fold. 2243 switch (Cond) { 2244 default: break; 2245 case ISD::SETFALSE: 2246 case ISD::SETFALSE2: return DAG.getConstant(0, VT); 2247 case ISD::SETTRUE: 2248 case ISD::SETTRUE2: return DAG.getConstant(1, VT); 2249 } 2250 2251 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val)) { 2252 uint64_t C1 = N1C->getValue(); 2253 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val)) { 2254 uint64_t C0 = N0C->getValue(); 2255 2256 // Sign extend the operands if required 2257 if (ISD::isSignedIntSetCC(Cond)) { 2258 C0 = N0C->getSignExtended(); 2259 C1 = N1C->getSignExtended(); 2260 } 2261 2262 switch (Cond) { 2263 default: assert(0 && "Unknown integer setcc!"); 2264 case ISD::SETEQ: return DAG.getConstant(C0 == C1, VT); 2265 case ISD::SETNE: return DAG.getConstant(C0 != C1, VT); 2266 case ISD::SETULT: return DAG.getConstant(C0 < C1, VT); 2267 case ISD::SETUGT: return DAG.getConstant(C0 > C1, VT); 2268 case ISD::SETULE: return DAG.getConstant(C0 <= C1, VT); 2269 case ISD::SETUGE: return DAG.getConstant(C0 >= C1, VT); 2270 case ISD::SETLT: return DAG.getConstant((int64_t)C0 < (int64_t)C1, VT); 2271 case ISD::SETGT: return DAG.getConstant((int64_t)C0 > (int64_t)C1, VT); 2272 case ISD::SETLE: return DAG.getConstant((int64_t)C0 <= (int64_t)C1, VT); 2273 case ISD::SETGE: return DAG.getConstant((int64_t)C0 >= (int64_t)C1, VT); 2274 } 2275 } else { 2276 // If the LHS is a ZERO_EXTEND, perform the comparison on the input. 2277 if (N0.getOpcode() == ISD::ZERO_EXTEND) { 2278 unsigned InSize = MVT::getSizeInBits(N0.getOperand(0).getValueType()); 2279 2280 // If the comparison constant has bits in the upper part, the 2281 // zero-extended value could never match. 2282 if (C1 & (~0ULL << InSize)) { 2283 unsigned VSize = MVT::getSizeInBits(N0.getValueType()); 2284 switch (Cond) { 2285 case ISD::SETUGT: 2286 case ISD::SETUGE: 2287 case ISD::SETEQ: return DAG.getConstant(0, VT); 2288 case ISD::SETULT: 2289 case ISD::SETULE: 2290 case ISD::SETNE: return DAG.getConstant(1, VT); 2291 case ISD::SETGT: 2292 case ISD::SETGE: 2293 // True if the sign bit of C1 is set. 2294 return DAG.getConstant((C1 & (1ULL << VSize)) != 0, VT); 2295 case ISD::SETLT: 2296 case ISD::SETLE: 2297 // True if the sign bit of C1 isn't set. 2298 return DAG.getConstant((C1 & (1ULL << VSize)) == 0, VT); 2299 default: 2300 break; 2301 } 2302 } 2303 2304 // Otherwise, we can perform the comparison with the low bits. 2305 switch (Cond) { 2306 case ISD::SETEQ: 2307 case ISD::SETNE: 2308 case ISD::SETUGT: 2309 case ISD::SETUGE: 2310 case ISD::SETULT: 2311 case ISD::SETULE: 2312 return DAG.getSetCC(VT, N0.getOperand(0), 2313 DAG.getConstant(C1, N0.getOperand(0).getValueType()), 2314 Cond); 2315 default: 2316 break; // todo, be more careful with signed comparisons 2317 } 2318 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 2319 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { 2320 MVT::ValueType ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT(); 2321 unsigned ExtSrcTyBits = MVT::getSizeInBits(ExtSrcTy); 2322 MVT::ValueType ExtDstTy = N0.getValueType(); 2323 unsigned ExtDstTyBits = MVT::getSizeInBits(ExtDstTy); 2324 2325 // If the extended part has any inconsistent bits, it cannot ever 2326 // compare equal. In other words, they have to be all ones or all 2327 // zeros. 2328 uint64_t ExtBits = 2329 (~0ULL >> (64-ExtSrcTyBits)) & (~0ULL << (ExtDstTyBits-1)); 2330 if ((C1 & ExtBits) != 0 && (C1 & ExtBits) != ExtBits) 2331 return DAG.getConstant(Cond == ISD::SETNE, VT); 2332 2333 SDOperand ZextOp; 2334 MVT::ValueType Op0Ty = N0.getOperand(0).getValueType(); 2335 if (Op0Ty == ExtSrcTy) { 2336 ZextOp = N0.getOperand(0); 2337 } else { 2338 int64_t Imm = ~0ULL >> (64-ExtSrcTyBits); 2339 ZextOp = DAG.getNode(ISD::AND, Op0Ty, N0.getOperand(0), 2340 DAG.getConstant(Imm, Op0Ty)); 2341 } 2342 WorkList.push_back(ZextOp.Val); 2343 // Otherwise, make this a use of a zext. 2344 return DAG.getSetCC(VT, ZextOp, 2345 DAG.getConstant(C1 & (~0ULL>>(64-ExtSrcTyBits)), 2346 ExtDstTy), 2347 Cond); 2348 } 2349 2350 uint64_t MinVal, MaxVal; 2351 unsigned OperandBitSize = MVT::getSizeInBits(N1C->getValueType(0)); 2352 if (ISD::isSignedIntSetCC(Cond)) { 2353 MinVal = 1ULL << (OperandBitSize-1); 2354 if (OperandBitSize != 1) // Avoid X >> 64, which is undefined. 2355 MaxVal = ~0ULL >> (65-OperandBitSize); 2356 else 2357 MaxVal = 0; 2358 } else { 2359 MinVal = 0; 2360 MaxVal = ~0ULL >> (64-OperandBitSize); 2361 } 2362 2363 // Canonicalize GE/LE comparisons to use GT/LT comparisons. 2364 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) { 2365 if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true 2366 --C1; // X >= C0 --> X > (C0-1) 2367 return DAG.getSetCC(VT, N0, DAG.getConstant(C1, N1.getValueType()), 2368 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT); 2369 } 2370 2371 if (Cond == ISD::SETLE || Cond == ISD::SETULE) { 2372 if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true 2373 ++C1; // X <= C0 --> X < (C0+1) 2374 return DAG.getSetCC(VT, N0, DAG.getConstant(C1, N1.getValueType()), 2375 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT); 2376 } 2377 2378 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal) 2379 return DAG.getConstant(0, VT); // X < MIN --> false 2380 2381 // Canonicalize setgt X, Min --> setne X, Min 2382 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal) 2383 return DAG.getSetCC(VT, N0, N1, ISD::SETNE); 2384 // Canonicalize setlt X, Max --> setne X, Max 2385 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal) 2386 return DAG.getSetCC(VT, N0, N1, ISD::SETNE); 2387 2388 // If we have setult X, 1, turn it into seteq X, 0 2389 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1) 2390 return DAG.getSetCC(VT, N0, DAG.getConstant(MinVal, N0.getValueType()), 2391 ISD::SETEQ); 2392 // If we have setugt X, Max-1, turn it into seteq X, Max 2393 else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1) 2394 return DAG.getSetCC(VT, N0, DAG.getConstant(MaxVal, N0.getValueType()), 2395 ISD::SETEQ); 2396 2397 // If we have "setcc X, C0", check to see if we can shrink the immediate 2398 // by changing cc. 2399 2400 // SETUGT X, SINTMAX -> SETLT X, 0 2401 if (Cond == ISD::SETUGT && OperandBitSize != 1 && 2402 C1 == (~0ULL >> (65-OperandBitSize))) 2403 return DAG.getSetCC(VT, N0, DAG.getConstant(0, N1.getValueType()), 2404 ISD::SETLT); 2405 2406 // FIXME: Implement the rest of these. 2407 2408 // Fold bit comparisons when we can. 2409 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 2410 VT == N0.getValueType() && N0.getOpcode() == ISD::AND) 2411 if (ConstantSDNode *AndRHS = 2412 dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 2413 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3 2414 // Perform the xform if the AND RHS is a single bit. 2415 if ((AndRHS->getValue() & (AndRHS->getValue()-1)) == 0) { 2416 return DAG.getNode(ISD::SRL, VT, N0, 2417 DAG.getConstant(Log2_64(AndRHS->getValue()), 2418 TLI.getShiftAmountTy())); 2419 } 2420 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getValue()) { 2421 // (X & 8) == 8 --> (X & 8) >> 3 2422 // Perform the xform if C1 is a single bit. 2423 if ((C1 & (C1-1)) == 0) { 2424 return DAG.getNode(ISD::SRL, VT, N0, 2425 DAG.getConstant(Log2_64(C1),TLI.getShiftAmountTy())); 2426 } 2427 } 2428 } 2429 } 2430 } else if (isa<ConstantSDNode>(N0.Val)) { 2431 // Ensure that the constant occurs on the RHS. 2432 return DAG.getSetCC(VT, N1, N0, ISD::getSetCCSwappedOperands(Cond)); 2433 } 2434 2435 if (ConstantFPSDNode *N0C = dyn_cast<ConstantFPSDNode>(N0.Val)) 2436 if (ConstantFPSDNode *N1C = dyn_cast<ConstantFPSDNode>(N1.Val)) { 2437 double C0 = N0C->getValue(), C1 = N1C->getValue(); 2438 2439 switch (Cond) { 2440 default: break; // FIXME: Implement the rest of these! 2441 case ISD::SETEQ: return DAG.getConstant(C0 == C1, VT); 2442 case ISD::SETNE: return DAG.getConstant(C0 != C1, VT); 2443 case ISD::SETLT: return DAG.getConstant(C0 < C1, VT); 2444 case ISD::SETGT: return DAG.getConstant(C0 > C1, VT); 2445 case ISD::SETLE: return DAG.getConstant(C0 <= C1, VT); 2446 case ISD::SETGE: return DAG.getConstant(C0 >= C1, VT); 2447 } 2448 } else { 2449 // Ensure that the constant occurs on the RHS. 2450 return DAG.getSetCC(VT, N1, N0, ISD::getSetCCSwappedOperands(Cond)); 2451 } 2452 2453 if (N0 == N1) { 2454 // We can always fold X == Y for integer setcc's. 2455 if (MVT::isInteger(N0.getValueType())) 2456 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT); 2457 unsigned UOF = ISD::getUnorderedFlavor(Cond); 2458 if (UOF == 2) // FP operators that are undefined on NaNs. 2459 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT); 2460 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond))) 2461 return DAG.getConstant(UOF, VT); 2462 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO 2463 // if it is not already. 2464 ISD::CondCode NewCond = UOF == 0 ? ISD::SETUO : ISD::SETO; 2465 if (NewCond != Cond) 2466 return DAG.getSetCC(VT, N0, N1, NewCond); 2467 } 2468 2469 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 2470 MVT::isInteger(N0.getValueType())) { 2471 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB || 2472 N0.getOpcode() == ISD::XOR) { 2473 // Simplify (X+Y) == (X+Z) --> Y == Z 2474 if (N0.getOpcode() == N1.getOpcode()) { 2475 if (N0.getOperand(0) == N1.getOperand(0)) 2476 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(1), Cond); 2477 if (N0.getOperand(1) == N1.getOperand(1)) 2478 return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(0), Cond); 2479 if (isCommutativeBinOp(N0.getOpcode())) { 2480 // If X op Y == Y op X, try other combinations. 2481 if (N0.getOperand(0) == N1.getOperand(1)) 2482 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(0), Cond); 2483 if (N0.getOperand(1) == N1.getOperand(0)) 2484 return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(1), Cond); 2485 } 2486 } 2487 2488 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0. Common for condcodes. 2489 if (N0.getOpcode() == ISD::XOR) 2490 if (ConstantSDNode *XORC = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 2491 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) { 2492 // If we know that all of the inverted bits are zero, don't bother 2493 // performing the inversion. 2494 if (MaskedValueIsZero(N0.getOperand(0), ~XORC->getValue(), TLI)) 2495 return DAG.getSetCC(VT, N0.getOperand(0), 2496 DAG.getConstant(XORC->getValue()^RHSC->getValue(), 2497 N0.getValueType()), Cond); 2498 } 2499 2500 // Simplify (X+Z) == X --> Z == 0 2501 if (N0.getOperand(0) == N1) 2502 return DAG.getSetCC(VT, N0.getOperand(1), 2503 DAG.getConstant(0, N0.getValueType()), Cond); 2504 if (N0.getOperand(1) == N1) { 2505 if (isCommutativeBinOp(N0.getOpcode())) 2506 return DAG.getSetCC(VT, N0.getOperand(0), 2507 DAG.getConstant(0, N0.getValueType()), Cond); 2508 else { 2509 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!"); 2510 // (Z-X) == X --> Z == X<<1 2511 SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(), 2512 N1, 2513 DAG.getConstant(1,TLI.getShiftAmountTy())); 2514 WorkList.push_back(SH.Val); 2515 return DAG.getSetCC(VT, N0.getOperand(0), SH, Cond); 2516 } 2517 } 2518 } 2519 2520 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB || 2521 N1.getOpcode() == ISD::XOR) { 2522 // Simplify X == (X+Z) --> Z == 0 2523 if (N1.getOperand(0) == N0) { 2524 return DAG.getSetCC(VT, N1.getOperand(1), 2525 DAG.getConstant(0, N1.getValueType()), Cond); 2526 } else if (N1.getOperand(1) == N0) { 2527 if (isCommutativeBinOp(N1.getOpcode())) { 2528 return DAG.getSetCC(VT, N1.getOperand(0), 2529 DAG.getConstant(0, N1.getValueType()), Cond); 2530 } else { 2531 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!"); 2532 // X == (Z-X) --> X<<1 == Z 2533 SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(), N0, 2534 DAG.getConstant(1,TLI.getShiftAmountTy())); 2535 WorkList.push_back(SH.Val); 2536 return DAG.getSetCC(VT, SH, N1.getOperand(0), Cond); 2537 } 2538 } 2539 } 2540 } 2541 2542 // Fold away ALL boolean setcc's. 2543 SDOperand Temp; 2544 if (N0.getValueType() == MVT::i1 && foldBooleans) { 2545 switch (Cond) { 2546 default: assert(0 && "Unknown integer setcc!"); 2547 case ISD::SETEQ: // X == Y -> (X^Y)^1 2548 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, N1); 2549 N0 = DAG.getNode(ISD::XOR, MVT::i1, Temp, DAG.getConstant(1, MVT::i1)); 2550 WorkList.push_back(Temp.Val); 2551 break; 2552 case ISD::SETNE: // X != Y --> (X^Y) 2553 N0 = DAG.getNode(ISD::XOR, MVT::i1, N0, N1); 2554 break; 2555 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> X^1 & Y 2556 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> X^1 & Y 2557 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1)); 2558 N0 = DAG.getNode(ISD::AND, MVT::i1, N1, Temp); 2559 WorkList.push_back(Temp.Val); 2560 break; 2561 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> Y^1 & X 2562 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> Y^1 & X 2563 Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1)); 2564 N0 = DAG.getNode(ISD::AND, MVT::i1, N0, Temp); 2565 WorkList.push_back(Temp.Val); 2566 break; 2567 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> X^1 | Y 2568 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> X^1 | Y 2569 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1)); 2570 N0 = DAG.getNode(ISD::OR, MVT::i1, N1, Temp); 2571 WorkList.push_back(Temp.Val); 2572 break; 2573 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> Y^1 | X 2574 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> Y^1 | X 2575 Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1)); 2576 N0 = DAG.getNode(ISD::OR, MVT::i1, N0, Temp); 2577 break; 2578 } 2579 if (VT != MVT::i1) { 2580 WorkList.push_back(N0.Val); 2581 // FIXME: If running after legalize, we probably can't do this. 2582 N0 = DAG.getNode(ISD::ZERO_EXTEND, VT, N0); 2583 } 2584 return N0; 2585 } 2586 2587 // Could not fold it. 2588 return SDOperand(); 2589} 2590 2591/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 2592/// return a DAG expression to select that will generate the same value by 2593/// multiplying by a magic number. See: 2594/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 2595SDOperand DAGCombiner::BuildSDIV(SDNode *N) { 2596 MVT::ValueType VT = N->getValueType(0); 2597 2598 // Check to see if we can do this. 2599 if (!TLI.isTypeLegal(VT) || (VT != MVT::i32 && VT != MVT::i64)) 2600 return SDOperand(); // BuildSDIV only operates on i32 or i64 2601 if (!TLI.isOperationLegal(ISD::MULHS, VT)) 2602 return SDOperand(); // Make sure the target supports MULHS. 2603 2604 int64_t d = cast<ConstantSDNode>(N->getOperand(1))->getSignExtended(); 2605 ms magics = (VT == MVT::i32) ? magic32(d) : magic64(d); 2606 2607 // Multiply the numerator (operand 0) by the magic value 2608 SDOperand Q = DAG.getNode(ISD::MULHS, VT, N->getOperand(0), 2609 DAG.getConstant(magics.m, VT)); 2610 // If d > 0 and m < 0, add the numerator 2611 if (d > 0 && magics.m < 0) { 2612 Q = DAG.getNode(ISD::ADD, VT, Q, N->getOperand(0)); 2613 WorkList.push_back(Q.Val); 2614 } 2615 // If d < 0 and m > 0, subtract the numerator. 2616 if (d < 0 && magics.m > 0) { 2617 Q = DAG.getNode(ISD::SUB, VT, Q, N->getOperand(0)); 2618 WorkList.push_back(Q.Val); 2619 } 2620 // Shift right algebraic if shift value is nonzero 2621 if (magics.s > 0) { 2622 Q = DAG.getNode(ISD::SRA, VT, Q, 2623 DAG.getConstant(magics.s, TLI.getShiftAmountTy())); 2624 WorkList.push_back(Q.Val); 2625 } 2626 // Extract the sign bit and add it to the quotient 2627 SDOperand T = 2628 DAG.getNode(ISD::SRL, VT, Q, DAG.getConstant(MVT::getSizeInBits(VT)-1, 2629 TLI.getShiftAmountTy())); 2630 WorkList.push_back(T.Val); 2631 return DAG.getNode(ISD::ADD, VT, Q, T); 2632} 2633 2634/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 2635/// return a DAG expression to select that will generate the same value by 2636/// multiplying by a magic number. See: 2637/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 2638SDOperand DAGCombiner::BuildUDIV(SDNode *N) { 2639 MVT::ValueType VT = N->getValueType(0); 2640 2641 // Check to see if we can do this. 2642 if (!TLI.isTypeLegal(VT) || (VT != MVT::i32 && VT != MVT::i64)) 2643 return SDOperand(); // BuildUDIV only operates on i32 or i64 2644 if (!TLI.isOperationLegal(ISD::MULHU, VT)) 2645 return SDOperand(); // Make sure the target supports MULHU. 2646 2647 uint64_t d = cast<ConstantSDNode>(N->getOperand(1))->getValue(); 2648 mu magics = (VT == MVT::i32) ? magicu32(d) : magicu64(d); 2649 2650 // Multiply the numerator (operand 0) by the magic value 2651 SDOperand Q = DAG.getNode(ISD::MULHU, VT, N->getOperand(0), 2652 DAG.getConstant(magics.m, VT)); 2653 WorkList.push_back(Q.Val); 2654 2655 if (magics.a == 0) { 2656 return DAG.getNode(ISD::SRL, VT, Q, 2657 DAG.getConstant(magics.s, TLI.getShiftAmountTy())); 2658 } else { 2659 SDOperand NPQ = DAG.getNode(ISD::SUB, VT, N->getOperand(0), Q); 2660 WorkList.push_back(NPQ.Val); 2661 NPQ = DAG.getNode(ISD::SRL, VT, NPQ, 2662 DAG.getConstant(1, TLI.getShiftAmountTy())); 2663 WorkList.push_back(NPQ.Val); 2664 NPQ = DAG.getNode(ISD::ADD, VT, NPQ, Q); 2665 WorkList.push_back(NPQ.Val); 2666 return DAG.getNode(ISD::SRL, VT, NPQ, 2667 DAG.getConstant(magics.s-1, TLI.getShiftAmountTy())); 2668 } 2669} 2670 2671// SelectionDAG::Combine - This is the entry point for the file. 2672// 2673void SelectionDAG::Combine(bool RunningAfterLegalize) { 2674 /// run - This is the main entry point to this class. 2675 /// 2676 DAGCombiner(*this).Run(RunningAfterLegalize); 2677} 2678