DAGCombiner.cpp revision 77d9521945fa46e03af9451b526fe0e588f44a04
1//===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run 11// both before and after the DAG is legalized. 12// 13// This pass is not a substitute for the LLVM IR instcombine pass. This pass is 14// primarily intended to handle simplification opportunities that are implicit 15// in the LLVM IR and exposed by the various codegen lowering phases. 16// 17//===----------------------------------------------------------------------===// 18 19#define DEBUG_TYPE "dagcombine" 20#include "llvm/CodeGen/SelectionDAG.h" 21#include "llvm/DerivedTypes.h" 22#include "llvm/LLVMContext.h" 23#include "llvm/CodeGen/MachineFunction.h" 24#include "llvm/CodeGen/MachineFrameInfo.h" 25#include "llvm/Analysis/AliasAnalysis.h" 26#include "llvm/Target/TargetData.h" 27#include "llvm/Target/TargetLowering.h" 28#include "llvm/Target/TargetMachine.h" 29#include "llvm/Target/TargetOptions.h" 30#include "llvm/ADT/SmallPtrSet.h" 31#include "llvm/ADT/Statistic.h" 32#include "llvm/Support/CommandLine.h" 33#include "llvm/Support/Debug.h" 34#include "llvm/Support/ErrorHandling.h" 35#include "llvm/Support/MathExtras.h" 36#include "llvm/Support/raw_ostream.h" 37#include <algorithm> 38using namespace llvm; 39 40STATISTIC(NodesCombined , "Number of dag nodes combined"); 41STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created"); 42STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created"); 43STATISTIC(OpsNarrowed , "Number of load/op/store narrowed"); 44STATISTIC(LdStFP2Int , "Number of fp load/store pairs transformed to int"); 45 46namespace { 47 static cl::opt<bool> 48 CombinerAA("combiner-alias-analysis", cl::Hidden, 49 cl::desc("Turn on alias analysis during testing")); 50 51 static cl::opt<bool> 52 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden, 53 cl::desc("Include global information in alias analysis")); 54 55//------------------------------ DAGCombiner ---------------------------------// 56 57 class DAGCombiner { 58 SelectionDAG &DAG; 59 const TargetLowering &TLI; 60 CombineLevel Level; 61 CodeGenOpt::Level OptLevel; 62 bool LegalOperations; 63 bool LegalTypes; 64 65 // Worklist of all of the nodes that need to be simplified. 66 // 67 // This has the semantics that when adding to the worklist, 68 // the item added must be next to be processed. It should 69 // also only appear once. The naive approach to this takes 70 // linear time. 71 // 72 // To reduce the insert/remove time to logarithmic, we use 73 // a set and a vector to maintain our worklist. 74 // 75 // The set contains the items on the worklist, but does not 76 // maintain the order they should be visited. 77 // 78 // The vector maintains the order nodes should be visited, but may 79 // contain duplicate or removed nodes. When choosing a node to 80 // visit, we pop off the order stack until we find an item that is 81 // also in the contents set. All operations are O(log N). 82 SmallPtrSet<SDNode*, 64> WorkListContents; 83 SmallVector<SDNode*, 64> WorkListOrder; 84 85 // AA - Used for DAG load/store alias analysis. 86 AliasAnalysis &AA; 87 88 /// AddUsersToWorkList - When an instruction is simplified, add all users of 89 /// the instruction to the work lists because they might get more simplified 90 /// now. 91 /// 92 void AddUsersToWorkList(SDNode *N) { 93 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 94 UI != UE; ++UI) 95 AddToWorkList(*UI); 96 } 97 98 /// visit - call the node-specific routine that knows how to fold each 99 /// particular type of node. 100 SDValue visit(SDNode *N); 101 102 public: 103 /// AddToWorkList - Add to the work list making sure its instance is at the 104 /// back (next to be processed.) 105 void AddToWorkList(SDNode *N) { 106 WorkListContents.insert(N); 107 WorkListOrder.push_back(N); 108 } 109 110 /// removeFromWorkList - remove all instances of N from the worklist. 111 /// 112 void removeFromWorkList(SDNode *N) { 113 WorkListContents.erase(N); 114 } 115 116 SDValue CombineTo(SDNode *N, const SDValue *To, unsigned NumTo, 117 bool AddTo = true); 118 119 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true) { 120 return CombineTo(N, &Res, 1, AddTo); 121 } 122 123 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, 124 bool AddTo = true) { 125 SDValue To[] = { Res0, Res1 }; 126 return CombineTo(N, To, 2, AddTo); 127 } 128 129 void CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO); 130 131 private: 132 133 /// SimplifyDemandedBits - Check the specified integer node value to see if 134 /// it can be simplified or if things it uses can be simplified by bit 135 /// propagation. If so, return true. 136 bool SimplifyDemandedBits(SDValue Op) { 137 unsigned BitWidth = Op.getValueType().getScalarType().getSizeInBits(); 138 APInt Demanded = APInt::getAllOnesValue(BitWidth); 139 return SimplifyDemandedBits(Op, Demanded); 140 } 141 142 bool SimplifyDemandedBits(SDValue Op, const APInt &Demanded); 143 144 bool CombineToPreIndexedLoadStore(SDNode *N); 145 bool CombineToPostIndexedLoadStore(SDNode *N); 146 147 void ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad); 148 SDValue PromoteOperand(SDValue Op, EVT PVT, bool &Replace); 149 SDValue SExtPromoteOperand(SDValue Op, EVT PVT); 150 SDValue ZExtPromoteOperand(SDValue Op, EVT PVT); 151 SDValue PromoteIntBinOp(SDValue Op); 152 SDValue PromoteIntShiftOp(SDValue Op); 153 SDValue PromoteExtend(SDValue Op); 154 bool PromoteLoad(SDValue Op); 155 156 void ExtendSetCCUses(SmallVector<SDNode*, 4> SetCCs, 157 SDValue Trunc, SDValue ExtLoad, DebugLoc DL, 158 ISD::NodeType ExtType); 159 160 /// combine - call the node-specific routine that knows how to fold each 161 /// particular type of node. If that doesn't do anything, try the 162 /// target-specific DAG combines. 163 SDValue combine(SDNode *N); 164 165 // Visitation implementation - Implement dag node combining for different 166 // node types. The semantics are as follows: 167 // Return Value: 168 // SDValue.getNode() == 0 - No change was made 169 // SDValue.getNode() == N - N was replaced, is dead and has been handled. 170 // otherwise - N should be replaced by the returned Operand. 171 // 172 SDValue visitTokenFactor(SDNode *N); 173 SDValue visitMERGE_VALUES(SDNode *N); 174 SDValue visitADD(SDNode *N); 175 SDValue visitSUB(SDNode *N); 176 SDValue visitADDC(SDNode *N); 177 SDValue visitSUBC(SDNode *N); 178 SDValue visitADDE(SDNode *N); 179 SDValue visitSUBE(SDNode *N); 180 SDValue visitMUL(SDNode *N); 181 SDValue visitSDIV(SDNode *N); 182 SDValue visitUDIV(SDNode *N); 183 SDValue visitSREM(SDNode *N); 184 SDValue visitUREM(SDNode *N); 185 SDValue visitMULHU(SDNode *N); 186 SDValue visitMULHS(SDNode *N); 187 SDValue visitSMUL_LOHI(SDNode *N); 188 SDValue visitUMUL_LOHI(SDNode *N); 189 SDValue visitSMULO(SDNode *N); 190 SDValue visitUMULO(SDNode *N); 191 SDValue visitSDIVREM(SDNode *N); 192 SDValue visitUDIVREM(SDNode *N); 193 SDValue visitAND(SDNode *N); 194 SDValue visitOR(SDNode *N); 195 SDValue visitXOR(SDNode *N); 196 SDValue SimplifyVBinOp(SDNode *N); 197 SDValue visitSHL(SDNode *N); 198 SDValue visitSRA(SDNode *N); 199 SDValue visitSRL(SDNode *N); 200 SDValue visitCTLZ(SDNode *N); 201 SDValue visitCTLZ_ZERO_UNDEF(SDNode *N); 202 SDValue visitCTTZ(SDNode *N); 203 SDValue visitCTTZ_ZERO_UNDEF(SDNode *N); 204 SDValue visitCTPOP(SDNode *N); 205 SDValue visitSELECT(SDNode *N); 206 SDValue visitSELECT_CC(SDNode *N); 207 SDValue visitSETCC(SDNode *N); 208 SDValue visitSIGN_EXTEND(SDNode *N); 209 SDValue visitZERO_EXTEND(SDNode *N); 210 SDValue visitANY_EXTEND(SDNode *N); 211 SDValue visitSIGN_EXTEND_INREG(SDNode *N); 212 SDValue visitTRUNCATE(SDNode *N); 213 SDValue visitBITCAST(SDNode *N); 214 SDValue visitBUILD_PAIR(SDNode *N); 215 SDValue visitFADD(SDNode *N); 216 SDValue visitFSUB(SDNode *N); 217 SDValue visitFMUL(SDNode *N); 218 SDValue visitFDIV(SDNode *N); 219 SDValue visitFREM(SDNode *N); 220 SDValue visitFCOPYSIGN(SDNode *N); 221 SDValue visitSINT_TO_FP(SDNode *N); 222 SDValue visitUINT_TO_FP(SDNode *N); 223 SDValue visitFP_TO_SINT(SDNode *N); 224 SDValue visitFP_TO_UINT(SDNode *N); 225 SDValue visitFP_ROUND(SDNode *N); 226 SDValue visitFP_ROUND_INREG(SDNode *N); 227 SDValue visitFP_EXTEND(SDNode *N); 228 SDValue visitFNEG(SDNode *N); 229 SDValue visitFABS(SDNode *N); 230 SDValue visitBRCOND(SDNode *N); 231 SDValue visitBR_CC(SDNode *N); 232 SDValue visitLOAD(SDNode *N); 233 SDValue visitSTORE(SDNode *N); 234 SDValue visitINSERT_VECTOR_ELT(SDNode *N); 235 SDValue visitEXTRACT_VECTOR_ELT(SDNode *N); 236 SDValue visitBUILD_VECTOR(SDNode *N); 237 SDValue visitCONCAT_VECTORS(SDNode *N); 238 SDValue visitEXTRACT_SUBVECTOR(SDNode *N); 239 SDValue visitVECTOR_SHUFFLE(SDNode *N); 240 SDValue visitMEMBARRIER(SDNode *N); 241 242 SDValue XformToShuffleWithZero(SDNode *N); 243 SDValue ReassociateOps(unsigned Opc, DebugLoc DL, SDValue LHS, SDValue RHS); 244 245 SDValue visitShiftByConstant(SDNode *N, unsigned Amt); 246 247 bool SimplifySelectOps(SDNode *SELECT, SDValue LHS, SDValue RHS); 248 SDValue SimplifyBinOpWithSameOpcodeHands(SDNode *N); 249 SDValue SimplifySelect(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2); 250 SDValue SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2, 251 SDValue N3, ISD::CondCode CC, 252 bool NotExtCompare = false); 253 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond, 254 DebugLoc DL, bool foldBooleans = true); 255 SDValue SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 256 unsigned HiOp); 257 SDValue CombineConsecutiveLoads(SDNode *N, EVT VT); 258 SDValue ConstantFoldBITCASTofBUILD_VECTOR(SDNode *, EVT); 259 SDValue BuildSDIV(SDNode *N); 260 SDValue BuildUDIV(SDNode *N); 261 SDValue MatchBSwapHWordLow(SDNode *N, SDValue N0, SDValue N1, 262 bool DemandHighBits = true); 263 SDValue MatchBSwapHWord(SDNode *N, SDValue N0, SDValue N1); 264 SDNode *MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL); 265 SDValue ReduceLoadWidth(SDNode *N); 266 SDValue ReduceLoadOpStoreWidth(SDNode *N); 267 SDValue TransformFPLoadStorePair(SDNode *N); 268 269 SDValue GetDemandedBits(SDValue V, const APInt &Mask); 270 271 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 272 /// looking for aliasing nodes and adding them to the Aliases vector. 273 void GatherAllAliases(SDNode *N, SDValue OriginalChain, 274 SmallVector<SDValue, 8> &Aliases); 275 276 /// isAlias - Return true if there is any possibility that the two addresses 277 /// overlap. 278 bool isAlias(SDValue Ptr1, int64_t Size1, 279 const Value *SrcValue1, int SrcValueOffset1, 280 unsigned SrcValueAlign1, 281 const MDNode *TBAAInfo1, 282 SDValue Ptr2, int64_t Size2, 283 const Value *SrcValue2, int SrcValueOffset2, 284 unsigned SrcValueAlign2, 285 const MDNode *TBAAInfo2) const; 286 287 /// FindAliasInfo - Extracts the relevant alias information from the memory 288 /// node. Returns true if the operand was a load. 289 bool FindAliasInfo(SDNode *N, 290 SDValue &Ptr, int64_t &Size, 291 const Value *&SrcValue, int &SrcValueOffset, 292 unsigned &SrcValueAlignment, 293 const MDNode *&TBAAInfo) const; 294 295 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, 296 /// looking for a better chain (aliasing node.) 297 SDValue FindBetterChain(SDNode *N, SDValue Chain); 298 299 public: 300 DAGCombiner(SelectionDAG &D, AliasAnalysis &A, CodeGenOpt::Level OL) 301 : DAG(D), TLI(D.getTargetLoweringInfo()), Level(BeforeLegalizeTypes), 302 OptLevel(OL), LegalOperations(false), LegalTypes(false), AA(A) {} 303 304 /// Run - runs the dag combiner on all nodes in the work list 305 void Run(CombineLevel AtLevel); 306 307 SelectionDAG &getDAG() const { return DAG; } 308 309 /// getShiftAmountTy - Returns a type large enough to hold any valid 310 /// shift amount - before type legalization these can be huge. 311 EVT getShiftAmountTy(EVT LHSTy) { 312 return LegalTypes ? TLI.getShiftAmountTy(LHSTy) : TLI.getPointerTy(); 313 } 314 315 /// isTypeLegal - This method returns true if we are running before type 316 /// legalization or if the specified VT is legal. 317 bool isTypeLegal(const EVT &VT) { 318 if (!LegalTypes) return true; 319 return TLI.isTypeLegal(VT); 320 } 321 }; 322} 323 324 325namespace { 326/// WorkListRemover - This class is a DAGUpdateListener that removes any deleted 327/// nodes from the worklist. 328class WorkListRemover : public SelectionDAG::DAGUpdateListener { 329 DAGCombiner &DC; 330public: 331 explicit WorkListRemover(DAGCombiner &dc) : DC(dc) {} 332 333 virtual void NodeDeleted(SDNode *N, SDNode *E) { 334 DC.removeFromWorkList(N); 335 } 336 337 virtual void NodeUpdated(SDNode *N) { 338 // Ignore updates. 339 } 340}; 341} 342 343//===----------------------------------------------------------------------===// 344// TargetLowering::DAGCombinerInfo implementation 345//===----------------------------------------------------------------------===// 346 347void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) { 348 ((DAGCombiner*)DC)->AddToWorkList(N); 349} 350 351void TargetLowering::DAGCombinerInfo::RemoveFromWorklist(SDNode *N) { 352 ((DAGCombiner*)DC)->removeFromWorkList(N); 353} 354 355SDValue TargetLowering::DAGCombinerInfo:: 356CombineTo(SDNode *N, const std::vector<SDValue> &To, bool AddTo) { 357 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size(), AddTo); 358} 359 360SDValue TargetLowering::DAGCombinerInfo:: 361CombineTo(SDNode *N, SDValue Res, bool AddTo) { 362 return ((DAGCombiner*)DC)->CombineTo(N, Res, AddTo); 363} 364 365 366SDValue TargetLowering::DAGCombinerInfo:: 367CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo) { 368 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1, AddTo); 369} 370 371void TargetLowering::DAGCombinerInfo:: 372CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) { 373 return ((DAGCombiner*)DC)->CommitTargetLoweringOpt(TLO); 374} 375 376//===----------------------------------------------------------------------===// 377// Helper Functions 378//===----------------------------------------------------------------------===// 379 380/// isNegatibleForFree - Return 1 if we can compute the negated form of the 381/// specified expression for the same cost as the expression itself, or 2 if we 382/// can compute the negated form more cheaply than the expression itself. 383static char isNegatibleForFree(SDValue Op, bool LegalOperations, 384 const TargetLowering &TLI, 385 const TargetOptions *Options, 386 unsigned Depth = 0) { 387 // No compile time optimizations on this type. 388 if (Op.getValueType() == MVT::ppcf128) 389 return 0; 390 391 // fneg is removable even if it has multiple uses. 392 if (Op.getOpcode() == ISD::FNEG) return 2; 393 394 // Don't allow anything with multiple uses. 395 if (!Op.hasOneUse()) return 0; 396 397 // Don't recurse exponentially. 398 if (Depth > 6) return 0; 399 400 switch (Op.getOpcode()) { 401 default: return false; 402 case ISD::ConstantFP: 403 // Don't invert constant FP values after legalize. The negated constant 404 // isn't necessarily legal. 405 return LegalOperations ? 0 : 1; 406 case ISD::FADD: 407 // FIXME: determine better conditions for this xform. 408 if (!Options->UnsafeFPMath) return 0; 409 410 // After operation legalization, it might not be legal to create new FSUBs. 411 if (LegalOperations && 412 !TLI.isOperationLegalOrCustom(ISD::FSUB, Op.getValueType())) 413 return 0; 414 415 // fold (fsub (fadd A, B)) -> (fsub (fneg A), B) 416 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI, 417 Options, Depth + 1)) 418 return V; 419 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A) 420 return isNegatibleForFree(Op.getOperand(1), LegalOperations, TLI, Options, 421 Depth + 1); 422 case ISD::FSUB: 423 // We can't turn -(A-B) into B-A when we honor signed zeros. 424 if (!Options->UnsafeFPMath) return 0; 425 426 // fold (fneg (fsub A, B)) -> (fsub B, A) 427 return 1; 428 429 case ISD::FMUL: 430 case ISD::FDIV: 431 if (Options->HonorSignDependentRoundingFPMath()) return 0; 432 433 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) or (fmul X, (fneg Y)) 434 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI, 435 Options, Depth + 1)) 436 return V; 437 438 return isNegatibleForFree(Op.getOperand(1), LegalOperations, TLI, Options, 439 Depth + 1); 440 441 case ISD::FP_EXTEND: 442 case ISD::FP_ROUND: 443 case ISD::FSIN: 444 return isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI, Options, 445 Depth + 1); 446 } 447} 448 449/// GetNegatedExpression - If isNegatibleForFree returns true, this function 450/// returns the newly negated expression. 451static SDValue GetNegatedExpression(SDValue Op, SelectionDAG &DAG, 452 bool LegalOperations, unsigned Depth = 0) { 453 // fneg is removable even if it has multiple uses. 454 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0); 455 456 // Don't allow anything with multiple uses. 457 assert(Op.hasOneUse() && "Unknown reuse!"); 458 459 assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree"); 460 switch (Op.getOpcode()) { 461 default: llvm_unreachable("Unknown code"); 462 case ISD::ConstantFP: { 463 APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF(); 464 V.changeSign(); 465 return DAG.getConstantFP(V, Op.getValueType()); 466 } 467 case ISD::FADD: 468 // FIXME: determine better conditions for this xform. 469 assert(DAG.getTarget().Options.UnsafeFPMath); 470 471 // fold (fneg (fadd A, B)) -> (fsub (fneg A), B) 472 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, 473 DAG.getTargetLoweringInfo(), 474 &DAG.getTarget().Options, Depth+1)) 475 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 476 GetNegatedExpression(Op.getOperand(0), DAG, 477 LegalOperations, Depth+1), 478 Op.getOperand(1)); 479 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A) 480 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 481 GetNegatedExpression(Op.getOperand(1), DAG, 482 LegalOperations, Depth+1), 483 Op.getOperand(0)); 484 case ISD::FSUB: 485 // We can't turn -(A-B) into B-A when we honor signed zeros. 486 assert(DAG.getTarget().Options.UnsafeFPMath); 487 488 // fold (fneg (fsub 0, B)) -> B 489 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(Op.getOperand(0))) 490 if (N0CFP->getValueAPF().isZero()) 491 return Op.getOperand(1); 492 493 // fold (fneg (fsub A, B)) -> (fsub B, A) 494 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 495 Op.getOperand(1), Op.getOperand(0)); 496 497 case ISD::FMUL: 498 case ISD::FDIV: 499 assert(!DAG.getTarget().Options.HonorSignDependentRoundingFPMath()); 500 501 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) 502 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, 503 DAG.getTargetLoweringInfo(), 504 &DAG.getTarget().Options, Depth+1)) 505 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 506 GetNegatedExpression(Op.getOperand(0), DAG, 507 LegalOperations, Depth+1), 508 Op.getOperand(1)); 509 510 // fold (fneg (fmul X, Y)) -> (fmul X, (fneg Y)) 511 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 512 Op.getOperand(0), 513 GetNegatedExpression(Op.getOperand(1), DAG, 514 LegalOperations, Depth+1)); 515 516 case ISD::FP_EXTEND: 517 case ISD::FSIN: 518 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 519 GetNegatedExpression(Op.getOperand(0), DAG, 520 LegalOperations, Depth+1)); 521 case ISD::FP_ROUND: 522 return DAG.getNode(ISD::FP_ROUND, Op.getDebugLoc(), Op.getValueType(), 523 GetNegatedExpression(Op.getOperand(0), DAG, 524 LegalOperations, Depth+1), 525 Op.getOperand(1)); 526 } 527} 528 529 530// isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc 531// that selects between the values 1 and 0, making it equivalent to a setcc. 532// Also, set the incoming LHS, RHS, and CC references to the appropriate 533// nodes based on the type of node we are checking. This simplifies life a 534// bit for the callers. 535static bool isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS, 536 SDValue &CC) { 537 if (N.getOpcode() == ISD::SETCC) { 538 LHS = N.getOperand(0); 539 RHS = N.getOperand(1); 540 CC = N.getOperand(2); 541 return true; 542 } 543 if (N.getOpcode() == ISD::SELECT_CC && 544 N.getOperand(2).getOpcode() == ISD::Constant && 545 N.getOperand(3).getOpcode() == ISD::Constant && 546 cast<ConstantSDNode>(N.getOperand(2))->getAPIntValue() == 1 && 547 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) { 548 LHS = N.getOperand(0); 549 RHS = N.getOperand(1); 550 CC = N.getOperand(4); 551 return true; 552 } 553 return false; 554} 555 556// isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only 557// one use. If this is true, it allows the users to invert the operation for 558// free when it is profitable to do so. 559static bool isOneUseSetCC(SDValue N) { 560 SDValue N0, N1, N2; 561 if (isSetCCEquivalent(N, N0, N1, N2) && N.getNode()->hasOneUse()) 562 return true; 563 return false; 564} 565 566SDValue DAGCombiner::ReassociateOps(unsigned Opc, DebugLoc DL, 567 SDValue N0, SDValue N1) { 568 EVT VT = N0.getValueType(); 569 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) { 570 if (isa<ConstantSDNode>(N1)) { 571 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2)) 572 SDValue OpNode = 573 DAG.FoldConstantArithmetic(Opc, VT, 574 cast<ConstantSDNode>(N0.getOperand(1)), 575 cast<ConstantSDNode>(N1)); 576 return DAG.getNode(Opc, DL, VT, N0.getOperand(0), OpNode); 577 } 578 if (N0.hasOneUse()) { 579 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use 580 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT, 581 N0.getOperand(0), N1); 582 AddToWorkList(OpNode.getNode()); 583 return DAG.getNode(Opc, DL, VT, OpNode, N0.getOperand(1)); 584 } 585 } 586 587 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) { 588 if (isa<ConstantSDNode>(N0)) { 589 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2)) 590 SDValue OpNode = 591 DAG.FoldConstantArithmetic(Opc, VT, 592 cast<ConstantSDNode>(N1.getOperand(1)), 593 cast<ConstantSDNode>(N0)); 594 return DAG.getNode(Opc, DL, VT, N1.getOperand(0), OpNode); 595 } 596 if (N1.hasOneUse()) { 597 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use 598 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT, 599 N1.getOperand(0), N0); 600 AddToWorkList(OpNode.getNode()); 601 return DAG.getNode(Opc, DL, VT, OpNode, N1.getOperand(1)); 602 } 603 } 604 605 return SDValue(); 606} 607 608SDValue DAGCombiner::CombineTo(SDNode *N, const SDValue *To, unsigned NumTo, 609 bool AddTo) { 610 assert(N->getNumValues() == NumTo && "Broken CombineTo call!"); 611 ++NodesCombined; 612 DEBUG(dbgs() << "\nReplacing.1 "; 613 N->dump(&DAG); 614 dbgs() << "\nWith: "; 615 To[0].getNode()->dump(&DAG); 616 dbgs() << " and " << NumTo-1 << " other values\n"; 617 for (unsigned i = 0, e = NumTo; i != e; ++i) 618 assert((!To[i].getNode() || 619 N->getValueType(i) == To[i].getValueType()) && 620 "Cannot combine value to value of different type!")); 621 WorkListRemover DeadNodes(*this); 622 DAG.ReplaceAllUsesWith(N, To, &DeadNodes); 623 624 if (AddTo) { 625 // Push the new nodes and any users onto the worklist 626 for (unsigned i = 0, e = NumTo; i != e; ++i) { 627 if (To[i].getNode()) { 628 AddToWorkList(To[i].getNode()); 629 AddUsersToWorkList(To[i].getNode()); 630 } 631 } 632 } 633 634 // Finally, if the node is now dead, remove it from the graph. The node 635 // may not be dead if the replacement process recursively simplified to 636 // something else needing this node. 637 if (N->use_empty()) { 638 // Nodes can be reintroduced into the worklist. Make sure we do not 639 // process a node that has been replaced. 640 removeFromWorkList(N); 641 642 // Finally, since the node is now dead, remove it from the graph. 643 DAG.DeleteNode(N); 644 } 645 return SDValue(N, 0); 646} 647 648void DAGCombiner:: 649CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) { 650 // Replace all uses. If any nodes become isomorphic to other nodes and 651 // are deleted, make sure to remove them from our worklist. 652 WorkListRemover DeadNodes(*this); 653 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &DeadNodes); 654 655 // Push the new node and any (possibly new) users onto the worklist. 656 AddToWorkList(TLO.New.getNode()); 657 AddUsersToWorkList(TLO.New.getNode()); 658 659 // Finally, if the node is now dead, remove it from the graph. The node 660 // may not be dead if the replacement process recursively simplified to 661 // something else needing this node. 662 if (TLO.Old.getNode()->use_empty()) { 663 removeFromWorkList(TLO.Old.getNode()); 664 665 // If the operands of this node are only used by the node, they will now 666 // be dead. Make sure to visit them first to delete dead nodes early. 667 for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands(); i != e; ++i) 668 if (TLO.Old.getNode()->getOperand(i).getNode()->hasOneUse()) 669 AddToWorkList(TLO.Old.getNode()->getOperand(i).getNode()); 670 671 DAG.DeleteNode(TLO.Old.getNode()); 672 } 673} 674 675/// SimplifyDemandedBits - Check the specified integer node value to see if 676/// it can be simplified or if things it uses can be simplified by bit 677/// propagation. If so, return true. 678bool DAGCombiner::SimplifyDemandedBits(SDValue Op, const APInt &Demanded) { 679 TargetLowering::TargetLoweringOpt TLO(DAG, LegalTypes, LegalOperations); 680 APInt KnownZero, KnownOne; 681 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO)) 682 return false; 683 684 // Revisit the node. 685 AddToWorkList(Op.getNode()); 686 687 // Replace the old value with the new one. 688 ++NodesCombined; 689 DEBUG(dbgs() << "\nReplacing.2 "; 690 TLO.Old.getNode()->dump(&DAG); 691 dbgs() << "\nWith: "; 692 TLO.New.getNode()->dump(&DAG); 693 dbgs() << '\n'); 694 695 CommitTargetLoweringOpt(TLO); 696 return true; 697} 698 699void DAGCombiner::ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad) { 700 DebugLoc dl = Load->getDebugLoc(); 701 EVT VT = Load->getValueType(0); 702 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, VT, SDValue(ExtLoad, 0)); 703 704 DEBUG(dbgs() << "\nReplacing.9 "; 705 Load->dump(&DAG); 706 dbgs() << "\nWith: "; 707 Trunc.getNode()->dump(&DAG); 708 dbgs() << '\n'); 709 WorkListRemover DeadNodes(*this); 710 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 0), Trunc, &DeadNodes); 711 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 1), SDValue(ExtLoad, 1), 712 &DeadNodes); 713 removeFromWorkList(Load); 714 DAG.DeleteNode(Load); 715 AddToWorkList(Trunc.getNode()); 716} 717 718SDValue DAGCombiner::PromoteOperand(SDValue Op, EVT PVT, bool &Replace) { 719 Replace = false; 720 DebugLoc dl = Op.getDebugLoc(); 721 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Op)) { 722 EVT MemVT = LD->getMemoryVT(); 723 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD) 724 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT) ? ISD::ZEXTLOAD 725 : ISD::EXTLOAD) 726 : LD->getExtensionType(); 727 Replace = true; 728 return DAG.getExtLoad(ExtType, dl, PVT, 729 LD->getChain(), LD->getBasePtr(), 730 LD->getPointerInfo(), 731 MemVT, LD->isVolatile(), 732 LD->isNonTemporal(), LD->getAlignment()); 733 } 734 735 unsigned Opc = Op.getOpcode(); 736 switch (Opc) { 737 default: break; 738 case ISD::AssertSext: 739 return DAG.getNode(ISD::AssertSext, dl, PVT, 740 SExtPromoteOperand(Op.getOperand(0), PVT), 741 Op.getOperand(1)); 742 case ISD::AssertZext: 743 return DAG.getNode(ISD::AssertZext, dl, PVT, 744 ZExtPromoteOperand(Op.getOperand(0), PVT), 745 Op.getOperand(1)); 746 case ISD::Constant: { 747 unsigned ExtOpc = 748 Op.getValueType().isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; 749 return DAG.getNode(ExtOpc, dl, PVT, Op); 750 } 751 } 752 753 if (!TLI.isOperationLegal(ISD::ANY_EXTEND, PVT)) 754 return SDValue(); 755 return DAG.getNode(ISD::ANY_EXTEND, dl, PVT, Op); 756} 757 758SDValue DAGCombiner::SExtPromoteOperand(SDValue Op, EVT PVT) { 759 if (!TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, PVT)) 760 return SDValue(); 761 EVT OldVT = Op.getValueType(); 762 DebugLoc dl = Op.getDebugLoc(); 763 bool Replace = false; 764 SDValue NewOp = PromoteOperand(Op, PVT, Replace); 765 if (NewOp.getNode() == 0) 766 return SDValue(); 767 AddToWorkList(NewOp.getNode()); 768 769 if (Replace) 770 ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode()); 771 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NewOp.getValueType(), NewOp, 772 DAG.getValueType(OldVT)); 773} 774 775SDValue DAGCombiner::ZExtPromoteOperand(SDValue Op, EVT PVT) { 776 EVT OldVT = Op.getValueType(); 777 DebugLoc dl = Op.getDebugLoc(); 778 bool Replace = false; 779 SDValue NewOp = PromoteOperand(Op, PVT, Replace); 780 if (NewOp.getNode() == 0) 781 return SDValue(); 782 AddToWorkList(NewOp.getNode()); 783 784 if (Replace) 785 ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode()); 786 return DAG.getZeroExtendInReg(NewOp, dl, OldVT); 787} 788 789/// PromoteIntBinOp - Promote the specified integer binary operation if the 790/// target indicates it is beneficial. e.g. On x86, it's usually better to 791/// promote i16 operations to i32 since i16 instructions are longer. 792SDValue DAGCombiner::PromoteIntBinOp(SDValue Op) { 793 if (!LegalOperations) 794 return SDValue(); 795 796 EVT VT = Op.getValueType(); 797 if (VT.isVector() || !VT.isInteger()) 798 return SDValue(); 799 800 // If operation type is 'undesirable', e.g. i16 on x86, consider 801 // promoting it. 802 unsigned Opc = Op.getOpcode(); 803 if (TLI.isTypeDesirableForOp(Opc, VT)) 804 return SDValue(); 805 806 EVT PVT = VT; 807 // Consult target whether it is a good idea to promote this operation and 808 // what's the right type to promote it to. 809 if (TLI.IsDesirableToPromoteOp(Op, PVT)) { 810 assert(PVT != VT && "Don't know what type to promote to!"); 811 812 bool Replace0 = false; 813 SDValue N0 = Op.getOperand(0); 814 SDValue NN0 = PromoteOperand(N0, PVT, Replace0); 815 if (NN0.getNode() == 0) 816 return SDValue(); 817 818 bool Replace1 = false; 819 SDValue N1 = Op.getOperand(1); 820 SDValue NN1; 821 if (N0 == N1) 822 NN1 = NN0; 823 else { 824 NN1 = PromoteOperand(N1, PVT, Replace1); 825 if (NN1.getNode() == 0) 826 return SDValue(); 827 } 828 829 AddToWorkList(NN0.getNode()); 830 if (NN1.getNode()) 831 AddToWorkList(NN1.getNode()); 832 833 if (Replace0) 834 ReplaceLoadWithPromotedLoad(N0.getNode(), NN0.getNode()); 835 if (Replace1) 836 ReplaceLoadWithPromotedLoad(N1.getNode(), NN1.getNode()); 837 838 DEBUG(dbgs() << "\nPromoting "; 839 Op.getNode()->dump(&DAG)); 840 DebugLoc dl = Op.getDebugLoc(); 841 return DAG.getNode(ISD::TRUNCATE, dl, VT, 842 DAG.getNode(Opc, dl, PVT, NN0, NN1)); 843 } 844 return SDValue(); 845} 846 847/// PromoteIntShiftOp - Promote the specified integer shift operation if the 848/// target indicates it is beneficial. e.g. On x86, it's usually better to 849/// promote i16 operations to i32 since i16 instructions are longer. 850SDValue DAGCombiner::PromoteIntShiftOp(SDValue Op) { 851 if (!LegalOperations) 852 return SDValue(); 853 854 EVT VT = Op.getValueType(); 855 if (VT.isVector() || !VT.isInteger()) 856 return SDValue(); 857 858 // If operation type is 'undesirable', e.g. i16 on x86, consider 859 // promoting it. 860 unsigned Opc = Op.getOpcode(); 861 if (TLI.isTypeDesirableForOp(Opc, VT)) 862 return SDValue(); 863 864 EVT PVT = VT; 865 // Consult target whether it is a good idea to promote this operation and 866 // what's the right type to promote it to. 867 if (TLI.IsDesirableToPromoteOp(Op, PVT)) { 868 assert(PVT != VT && "Don't know what type to promote to!"); 869 870 bool Replace = false; 871 SDValue N0 = Op.getOperand(0); 872 if (Opc == ISD::SRA) 873 N0 = SExtPromoteOperand(Op.getOperand(0), PVT); 874 else if (Opc == ISD::SRL) 875 N0 = ZExtPromoteOperand(Op.getOperand(0), PVT); 876 else 877 N0 = PromoteOperand(N0, PVT, Replace); 878 if (N0.getNode() == 0) 879 return SDValue(); 880 881 AddToWorkList(N0.getNode()); 882 if (Replace) 883 ReplaceLoadWithPromotedLoad(Op.getOperand(0).getNode(), N0.getNode()); 884 885 DEBUG(dbgs() << "\nPromoting "; 886 Op.getNode()->dump(&DAG)); 887 DebugLoc dl = Op.getDebugLoc(); 888 return DAG.getNode(ISD::TRUNCATE, dl, VT, 889 DAG.getNode(Opc, dl, PVT, N0, Op.getOperand(1))); 890 } 891 return SDValue(); 892} 893 894SDValue DAGCombiner::PromoteExtend(SDValue Op) { 895 if (!LegalOperations) 896 return SDValue(); 897 898 EVT VT = Op.getValueType(); 899 if (VT.isVector() || !VT.isInteger()) 900 return SDValue(); 901 902 // If operation type is 'undesirable', e.g. i16 on x86, consider 903 // promoting it. 904 unsigned Opc = Op.getOpcode(); 905 if (TLI.isTypeDesirableForOp(Opc, VT)) 906 return SDValue(); 907 908 EVT PVT = VT; 909 // Consult target whether it is a good idea to promote this operation and 910 // what's the right type to promote it to. 911 if (TLI.IsDesirableToPromoteOp(Op, PVT)) { 912 assert(PVT != VT && "Don't know what type to promote to!"); 913 // fold (aext (aext x)) -> (aext x) 914 // fold (aext (zext x)) -> (zext x) 915 // fold (aext (sext x)) -> (sext x) 916 DEBUG(dbgs() << "\nPromoting "; 917 Op.getNode()->dump(&DAG)); 918 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), VT, Op.getOperand(0)); 919 } 920 return SDValue(); 921} 922 923bool DAGCombiner::PromoteLoad(SDValue Op) { 924 if (!LegalOperations) 925 return false; 926 927 EVT VT = Op.getValueType(); 928 if (VT.isVector() || !VT.isInteger()) 929 return false; 930 931 // If operation type is 'undesirable', e.g. i16 on x86, consider 932 // promoting it. 933 unsigned Opc = Op.getOpcode(); 934 if (TLI.isTypeDesirableForOp(Opc, VT)) 935 return false; 936 937 EVT PVT = VT; 938 // Consult target whether it is a good idea to promote this operation and 939 // what's the right type to promote it to. 940 if (TLI.IsDesirableToPromoteOp(Op, PVT)) { 941 assert(PVT != VT && "Don't know what type to promote to!"); 942 943 DebugLoc dl = Op.getDebugLoc(); 944 SDNode *N = Op.getNode(); 945 LoadSDNode *LD = cast<LoadSDNode>(N); 946 EVT MemVT = LD->getMemoryVT(); 947 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD) 948 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT) ? ISD::ZEXTLOAD 949 : ISD::EXTLOAD) 950 : LD->getExtensionType(); 951 SDValue NewLD = DAG.getExtLoad(ExtType, dl, PVT, 952 LD->getChain(), LD->getBasePtr(), 953 LD->getPointerInfo(), 954 MemVT, LD->isVolatile(), 955 LD->isNonTemporal(), LD->getAlignment()); 956 SDValue Result = DAG.getNode(ISD::TRUNCATE, dl, VT, NewLD); 957 958 DEBUG(dbgs() << "\nPromoting "; 959 N->dump(&DAG); 960 dbgs() << "\nTo: "; 961 Result.getNode()->dump(&DAG); 962 dbgs() << '\n'); 963 WorkListRemover DeadNodes(*this); 964 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result, &DeadNodes); 965 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), NewLD.getValue(1), &DeadNodes); 966 removeFromWorkList(N); 967 DAG.DeleteNode(N); 968 AddToWorkList(Result.getNode()); 969 return true; 970 } 971 return false; 972} 973 974 975//===----------------------------------------------------------------------===// 976// Main DAG Combiner implementation 977//===----------------------------------------------------------------------===// 978 979void DAGCombiner::Run(CombineLevel AtLevel) { 980 // set the instance variables, so that the various visit routines may use it. 981 Level = AtLevel; 982 LegalOperations = Level >= AfterLegalizeVectorOps; 983 LegalTypes = Level >= AfterLegalizeTypes; 984 985 // Add all the dag nodes to the worklist. 986 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 987 E = DAG.allnodes_end(); I != E; ++I) 988 AddToWorkList(I); 989 990 // Create a dummy node (which is not added to allnodes), that adds a reference 991 // to the root node, preventing it from being deleted, and tracking any 992 // changes of the root. 993 HandleSDNode Dummy(DAG.getRoot()); 994 995 // The root of the dag may dangle to deleted nodes until the dag combiner is 996 // done. Set it to null to avoid confusion. 997 DAG.setRoot(SDValue()); 998 999 // while the worklist isn't empty, find a node and 1000 // try and combine it. 1001 while (!WorkListContents.empty()) { 1002 SDNode *N; 1003 // The WorkListOrder holds the SDNodes in order, but it may contain duplicates. 1004 // In order to avoid a linear scan, we use a set (O(log N)) to hold what the 1005 // worklist *should* contain, and check the node we want to visit is should 1006 // actually be visited. 1007 do { 1008 N = WorkListOrder.pop_back_val(); 1009 } while (!WorkListContents.erase(N)); 1010 1011 // If N has no uses, it is dead. Make sure to revisit all N's operands once 1012 // N is deleted from the DAG, since they too may now be dead or may have a 1013 // reduced number of uses, allowing other xforms. 1014 if (N->use_empty() && N != &Dummy) { 1015 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 1016 AddToWorkList(N->getOperand(i).getNode()); 1017 1018 DAG.DeleteNode(N); 1019 continue; 1020 } 1021 1022 SDValue RV = combine(N); 1023 1024 if (RV.getNode() == 0) 1025 continue; 1026 1027 ++NodesCombined; 1028 1029 // If we get back the same node we passed in, rather than a new node or 1030 // zero, we know that the node must have defined multiple values and 1031 // CombineTo was used. Since CombineTo takes care of the worklist 1032 // mechanics for us, we have no work to do in this case. 1033 if (RV.getNode() == N) 1034 continue; 1035 1036 assert(N->getOpcode() != ISD::DELETED_NODE && 1037 RV.getNode()->getOpcode() != ISD::DELETED_NODE && 1038 "Node was deleted but visit returned new node!"); 1039 1040 DEBUG(dbgs() << "\nReplacing.3 "; 1041 N->dump(&DAG); 1042 dbgs() << "\nWith: "; 1043 RV.getNode()->dump(&DAG); 1044 dbgs() << '\n'); 1045 1046 // Transfer debug value. 1047 DAG.TransferDbgValues(SDValue(N, 0), RV); 1048 WorkListRemover DeadNodes(*this); 1049 if (N->getNumValues() == RV.getNode()->getNumValues()) 1050 DAG.ReplaceAllUsesWith(N, RV.getNode(), &DeadNodes); 1051 else { 1052 assert(N->getValueType(0) == RV.getValueType() && 1053 N->getNumValues() == 1 && "Type mismatch"); 1054 SDValue OpV = RV; 1055 DAG.ReplaceAllUsesWith(N, &OpV, &DeadNodes); 1056 } 1057 1058 // Push the new node and any users onto the worklist 1059 AddToWorkList(RV.getNode()); 1060 AddUsersToWorkList(RV.getNode()); 1061 1062 // Add any uses of the old node to the worklist in case this node is the 1063 // last one that uses them. They may become dead after this node is 1064 // deleted. 1065 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 1066 AddToWorkList(N->getOperand(i).getNode()); 1067 1068 // Finally, if the node is now dead, remove it from the graph. The node 1069 // may not be dead if the replacement process recursively simplified to 1070 // something else needing this node. 1071 if (N->use_empty()) { 1072 // Nodes can be reintroduced into the worklist. Make sure we do not 1073 // process a node that has been replaced. 1074 removeFromWorkList(N); 1075 1076 // Finally, since the node is now dead, remove it from the graph. 1077 DAG.DeleteNode(N); 1078 } 1079 } 1080 1081 // If the root changed (e.g. it was a dead load, update the root). 1082 DAG.setRoot(Dummy.getValue()); 1083} 1084 1085SDValue DAGCombiner::visit(SDNode *N) { 1086 switch (N->getOpcode()) { 1087 default: break; 1088 case ISD::TokenFactor: return visitTokenFactor(N); 1089 case ISD::MERGE_VALUES: return visitMERGE_VALUES(N); 1090 case ISD::ADD: return visitADD(N); 1091 case ISD::SUB: return visitSUB(N); 1092 case ISD::ADDC: return visitADDC(N); 1093 case ISD::SUBC: return visitSUBC(N); 1094 case ISD::ADDE: return visitADDE(N); 1095 case ISD::SUBE: return visitSUBE(N); 1096 case ISD::MUL: return visitMUL(N); 1097 case ISD::SDIV: return visitSDIV(N); 1098 case ISD::UDIV: return visitUDIV(N); 1099 case ISD::SREM: return visitSREM(N); 1100 case ISD::UREM: return visitUREM(N); 1101 case ISD::MULHU: return visitMULHU(N); 1102 case ISD::MULHS: return visitMULHS(N); 1103 case ISD::SMUL_LOHI: return visitSMUL_LOHI(N); 1104 case ISD::UMUL_LOHI: return visitUMUL_LOHI(N); 1105 case ISD::SMULO: return visitSMULO(N); 1106 case ISD::UMULO: return visitUMULO(N); 1107 case ISD::SDIVREM: return visitSDIVREM(N); 1108 case ISD::UDIVREM: return visitUDIVREM(N); 1109 case ISD::AND: return visitAND(N); 1110 case ISD::OR: return visitOR(N); 1111 case ISD::XOR: return visitXOR(N); 1112 case ISD::SHL: return visitSHL(N); 1113 case ISD::SRA: return visitSRA(N); 1114 case ISD::SRL: return visitSRL(N); 1115 case ISD::CTLZ: return visitCTLZ(N); 1116 case ISD::CTLZ_ZERO_UNDEF: return visitCTLZ_ZERO_UNDEF(N); 1117 case ISD::CTTZ: return visitCTTZ(N); 1118 case ISD::CTTZ_ZERO_UNDEF: return visitCTTZ_ZERO_UNDEF(N); 1119 case ISD::CTPOP: return visitCTPOP(N); 1120 case ISD::SELECT: return visitSELECT(N); 1121 case ISD::SELECT_CC: return visitSELECT_CC(N); 1122 case ISD::SETCC: return visitSETCC(N); 1123 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N); 1124 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N); 1125 case ISD::ANY_EXTEND: return visitANY_EXTEND(N); 1126 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N); 1127 case ISD::TRUNCATE: return visitTRUNCATE(N); 1128 case ISD::BITCAST: return visitBITCAST(N); 1129 case ISD::BUILD_PAIR: return visitBUILD_PAIR(N); 1130 case ISD::FADD: return visitFADD(N); 1131 case ISD::FSUB: return visitFSUB(N); 1132 case ISD::FMUL: return visitFMUL(N); 1133 case ISD::FDIV: return visitFDIV(N); 1134 case ISD::FREM: return visitFREM(N); 1135 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N); 1136 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N); 1137 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N); 1138 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N); 1139 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N); 1140 case ISD::FP_ROUND: return visitFP_ROUND(N); 1141 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N); 1142 case ISD::FP_EXTEND: return visitFP_EXTEND(N); 1143 case ISD::FNEG: return visitFNEG(N); 1144 case ISD::FABS: return visitFABS(N); 1145 case ISD::BRCOND: return visitBRCOND(N); 1146 case ISD::BR_CC: return visitBR_CC(N); 1147 case ISD::LOAD: return visitLOAD(N); 1148 case ISD::STORE: return visitSTORE(N); 1149 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N); 1150 case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N); 1151 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N); 1152 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N); 1153 case ISD::EXTRACT_SUBVECTOR: return visitEXTRACT_SUBVECTOR(N); 1154 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N); 1155 case ISD::MEMBARRIER: return visitMEMBARRIER(N); 1156 } 1157 return SDValue(); 1158} 1159 1160SDValue DAGCombiner::combine(SDNode *N) { 1161 SDValue RV = visit(N); 1162 1163 // If nothing happened, try a target-specific DAG combine. 1164 if (RV.getNode() == 0) { 1165 assert(N->getOpcode() != ISD::DELETED_NODE && 1166 "Node was deleted but visit returned NULL!"); 1167 1168 if (N->getOpcode() >= ISD::BUILTIN_OP_END || 1169 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) { 1170 1171 // Expose the DAG combiner to the target combiner impls. 1172 TargetLowering::DAGCombinerInfo 1173 DagCombineInfo(DAG, !LegalTypes, !LegalOperations, false, this); 1174 1175 RV = TLI.PerformDAGCombine(N, DagCombineInfo); 1176 } 1177 } 1178 1179 // If nothing happened still, try promoting the operation. 1180 if (RV.getNode() == 0) { 1181 switch (N->getOpcode()) { 1182 default: break; 1183 case ISD::ADD: 1184 case ISD::SUB: 1185 case ISD::MUL: 1186 case ISD::AND: 1187 case ISD::OR: 1188 case ISD::XOR: 1189 RV = PromoteIntBinOp(SDValue(N, 0)); 1190 break; 1191 case ISD::SHL: 1192 case ISD::SRA: 1193 case ISD::SRL: 1194 RV = PromoteIntShiftOp(SDValue(N, 0)); 1195 break; 1196 case ISD::SIGN_EXTEND: 1197 case ISD::ZERO_EXTEND: 1198 case ISD::ANY_EXTEND: 1199 RV = PromoteExtend(SDValue(N, 0)); 1200 break; 1201 case ISD::LOAD: 1202 if (PromoteLoad(SDValue(N, 0))) 1203 RV = SDValue(N, 0); 1204 break; 1205 } 1206 } 1207 1208 // If N is a commutative binary node, try commuting it to enable more 1209 // sdisel CSE. 1210 if (RV.getNode() == 0 && 1211 SelectionDAG::isCommutativeBinOp(N->getOpcode()) && 1212 N->getNumValues() == 1) { 1213 SDValue N0 = N->getOperand(0); 1214 SDValue N1 = N->getOperand(1); 1215 1216 // Constant operands are canonicalized to RHS. 1217 if (isa<ConstantSDNode>(N0) || !isa<ConstantSDNode>(N1)) { 1218 SDValue Ops[] = { N1, N0 }; 1219 SDNode *CSENode = DAG.getNodeIfExists(N->getOpcode(), N->getVTList(), 1220 Ops, 2); 1221 if (CSENode) 1222 return SDValue(CSENode, 0); 1223 } 1224 } 1225 1226 return RV; 1227} 1228 1229/// getInputChainForNode - Given a node, return its input chain if it has one, 1230/// otherwise return a null sd operand. 1231static SDValue getInputChainForNode(SDNode *N) { 1232 if (unsigned NumOps = N->getNumOperands()) { 1233 if (N->getOperand(0).getValueType() == MVT::Other) 1234 return N->getOperand(0); 1235 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other) 1236 return N->getOperand(NumOps-1); 1237 for (unsigned i = 1; i < NumOps-1; ++i) 1238 if (N->getOperand(i).getValueType() == MVT::Other) 1239 return N->getOperand(i); 1240 } 1241 return SDValue(); 1242} 1243 1244SDValue DAGCombiner::visitTokenFactor(SDNode *N) { 1245 // If N has two operands, where one has an input chain equal to the other, 1246 // the 'other' chain is redundant. 1247 if (N->getNumOperands() == 2) { 1248 if (getInputChainForNode(N->getOperand(0).getNode()) == N->getOperand(1)) 1249 return N->getOperand(0); 1250 if (getInputChainForNode(N->getOperand(1).getNode()) == N->getOperand(0)) 1251 return N->getOperand(1); 1252 } 1253 1254 SmallVector<SDNode *, 8> TFs; // List of token factors to visit. 1255 SmallVector<SDValue, 8> Ops; // Ops for replacing token factor. 1256 SmallPtrSet<SDNode*, 16> SeenOps; 1257 bool Changed = false; // If we should replace this token factor. 1258 1259 // Start out with this token factor. 1260 TFs.push_back(N); 1261 1262 // Iterate through token factors. The TFs grows when new token factors are 1263 // encountered. 1264 for (unsigned i = 0; i < TFs.size(); ++i) { 1265 SDNode *TF = TFs[i]; 1266 1267 // Check each of the operands. 1268 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) { 1269 SDValue Op = TF->getOperand(i); 1270 1271 switch (Op.getOpcode()) { 1272 case ISD::EntryToken: 1273 // Entry tokens don't need to be added to the list. They are 1274 // rededundant. 1275 Changed = true; 1276 break; 1277 1278 case ISD::TokenFactor: 1279 if (Op.hasOneUse() && 1280 std::find(TFs.begin(), TFs.end(), Op.getNode()) == TFs.end()) { 1281 // Queue up for processing. 1282 TFs.push_back(Op.getNode()); 1283 // Clean up in case the token factor is removed. 1284 AddToWorkList(Op.getNode()); 1285 Changed = true; 1286 break; 1287 } 1288 // Fall thru 1289 1290 default: 1291 // Only add if it isn't already in the list. 1292 if (SeenOps.insert(Op.getNode())) 1293 Ops.push_back(Op); 1294 else 1295 Changed = true; 1296 break; 1297 } 1298 } 1299 } 1300 1301 SDValue Result; 1302 1303 // If we've change things around then replace token factor. 1304 if (Changed) { 1305 if (Ops.empty()) { 1306 // The entry token is the only possible outcome. 1307 Result = DAG.getEntryNode(); 1308 } else { 1309 // New and improved token factor. 1310 Result = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 1311 MVT::Other, &Ops[0], Ops.size()); 1312 } 1313 1314 // Don't add users to work list. 1315 return CombineTo(N, Result, false); 1316 } 1317 1318 return Result; 1319} 1320 1321/// MERGE_VALUES can always be eliminated. 1322SDValue DAGCombiner::visitMERGE_VALUES(SDNode *N) { 1323 WorkListRemover DeadNodes(*this); 1324 // Replacing results may cause a different MERGE_VALUES to suddenly 1325 // be CSE'd with N, and carry its uses with it. Iterate until no 1326 // uses remain, to ensure that the node can be safely deleted. 1327 do { 1328 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 1329 DAG.ReplaceAllUsesOfValueWith(SDValue(N, i), N->getOperand(i), 1330 &DeadNodes); 1331 } while (!N->use_empty()); 1332 removeFromWorkList(N); 1333 DAG.DeleteNode(N); 1334 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1335} 1336 1337static 1338SDValue combineShlAddConstant(DebugLoc DL, SDValue N0, SDValue N1, 1339 SelectionDAG &DAG) { 1340 EVT VT = N0.getValueType(); 1341 SDValue N00 = N0.getOperand(0); 1342 SDValue N01 = N0.getOperand(1); 1343 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01); 1344 1345 if (N01C && N00.getOpcode() == ISD::ADD && N00.getNode()->hasOneUse() && 1346 isa<ConstantSDNode>(N00.getOperand(1))) { 1347 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 1348 N0 = DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, 1349 DAG.getNode(ISD::SHL, N00.getDebugLoc(), VT, 1350 N00.getOperand(0), N01), 1351 DAG.getNode(ISD::SHL, N01.getDebugLoc(), VT, 1352 N00.getOperand(1), N01)); 1353 return DAG.getNode(ISD::ADD, DL, VT, N0, N1); 1354 } 1355 1356 return SDValue(); 1357} 1358 1359SDValue DAGCombiner::visitADD(SDNode *N) { 1360 SDValue N0 = N->getOperand(0); 1361 SDValue N1 = N->getOperand(1); 1362 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1363 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1364 EVT VT = N0.getValueType(); 1365 1366 // fold vector ops 1367 if (VT.isVector()) { 1368 SDValue FoldedVOp = SimplifyVBinOp(N); 1369 if (FoldedVOp.getNode()) return FoldedVOp; 1370 } 1371 1372 // fold (add x, undef) -> undef 1373 if (N0.getOpcode() == ISD::UNDEF) 1374 return N0; 1375 if (N1.getOpcode() == ISD::UNDEF) 1376 return N1; 1377 // fold (add c1, c2) -> c1+c2 1378 if (N0C && N1C) 1379 return DAG.FoldConstantArithmetic(ISD::ADD, VT, N0C, N1C); 1380 // canonicalize constant to RHS 1381 if (N0C && !N1C) 1382 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0); 1383 // fold (add x, 0) -> x 1384 if (N1C && N1C->isNullValue()) 1385 return N0; 1386 // fold (add Sym, c) -> Sym+c 1387 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0)) 1388 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA) && N1C && 1389 GA->getOpcode() == ISD::GlobalAddress) 1390 return DAG.getGlobalAddress(GA->getGlobal(), N1C->getDebugLoc(), VT, 1391 GA->getOffset() + 1392 (uint64_t)N1C->getSExtValue()); 1393 // fold ((c1-A)+c2) -> (c1+c2)-A 1394 if (N1C && N0.getOpcode() == ISD::SUB) 1395 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0))) 1396 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1397 DAG.getConstant(N1C->getAPIntValue()+ 1398 N0C->getAPIntValue(), VT), 1399 N0.getOperand(1)); 1400 // reassociate add 1401 SDValue RADD = ReassociateOps(ISD::ADD, N->getDebugLoc(), N0, N1); 1402 if (RADD.getNode() != 0) 1403 return RADD; 1404 // fold ((0-A) + B) -> B-A 1405 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) && 1406 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue()) 1407 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1, N0.getOperand(1)); 1408 // fold (A + (0-B)) -> A-B 1409 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) && 1410 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue()) 1411 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, N1.getOperand(1)); 1412 // fold (A+(B-A)) -> B 1413 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1)) 1414 return N1.getOperand(0); 1415 // fold ((B-A)+A) -> B 1416 if (N0.getOpcode() == ISD::SUB && N1 == N0.getOperand(1)) 1417 return N0.getOperand(0); 1418 // fold (A+(B-(A+C))) to (B-C) 1419 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD && 1420 N0 == N1.getOperand(1).getOperand(0)) 1421 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0), 1422 N1.getOperand(1).getOperand(1)); 1423 // fold (A+(B-(C+A))) to (B-C) 1424 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD && 1425 N0 == N1.getOperand(1).getOperand(1)) 1426 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0), 1427 N1.getOperand(1).getOperand(0)); 1428 // fold (A+((B-A)+or-C)) to (B+or-C) 1429 if ((N1.getOpcode() == ISD::SUB || N1.getOpcode() == ISD::ADD) && 1430 N1.getOperand(0).getOpcode() == ISD::SUB && 1431 N0 == N1.getOperand(0).getOperand(1)) 1432 return DAG.getNode(N1.getOpcode(), N->getDebugLoc(), VT, 1433 N1.getOperand(0).getOperand(0), N1.getOperand(1)); 1434 1435 // fold (A-B)+(C-D) to (A+C)-(B+D) when A or C is constant 1436 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB) { 1437 SDValue N00 = N0.getOperand(0); 1438 SDValue N01 = N0.getOperand(1); 1439 SDValue N10 = N1.getOperand(0); 1440 SDValue N11 = N1.getOperand(1); 1441 1442 if (isa<ConstantSDNode>(N00) || isa<ConstantSDNode>(N10)) 1443 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1444 DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, N00, N10), 1445 DAG.getNode(ISD::ADD, N1.getDebugLoc(), VT, N01, N11)); 1446 } 1447 1448 if (!VT.isVector() && SimplifyDemandedBits(SDValue(N, 0))) 1449 return SDValue(N, 0); 1450 1451 // fold (a+b) -> (a|b) iff a and b share no bits. 1452 if (VT.isInteger() && !VT.isVector()) { 1453 APInt LHSZero, LHSOne; 1454 APInt RHSZero, RHSOne; 1455 APInt Mask = APInt::getAllOnesValue(VT.getScalarType().getSizeInBits()); 1456 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 1457 1458 if (LHSZero.getBoolValue()) { 1459 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 1460 1461 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1462 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1463 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 1464 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 1465 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1); 1466 } 1467 } 1468 1469 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 1470 if (N0.getOpcode() == ISD::SHL && N0.getNode()->hasOneUse()) { 1471 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N0, N1, DAG); 1472 if (Result.getNode()) return Result; 1473 } 1474 if (N1.getOpcode() == ISD::SHL && N1.getNode()->hasOneUse()) { 1475 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N1, N0, DAG); 1476 if (Result.getNode()) return Result; 1477 } 1478 1479 // fold (add x, shl(0 - y, n)) -> sub(x, shl(y, n)) 1480 if (N1.getOpcode() == ISD::SHL && 1481 N1.getOperand(0).getOpcode() == ISD::SUB) 1482 if (ConstantSDNode *C = 1483 dyn_cast<ConstantSDNode>(N1.getOperand(0).getOperand(0))) 1484 if (C->getAPIntValue() == 0) 1485 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, 1486 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1487 N1.getOperand(0).getOperand(1), 1488 N1.getOperand(1))); 1489 if (N0.getOpcode() == ISD::SHL && 1490 N0.getOperand(0).getOpcode() == ISD::SUB) 1491 if (ConstantSDNode *C = 1492 dyn_cast<ConstantSDNode>(N0.getOperand(0).getOperand(0))) 1493 if (C->getAPIntValue() == 0) 1494 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1, 1495 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1496 N0.getOperand(0).getOperand(1), 1497 N0.getOperand(1))); 1498 1499 if (N1.getOpcode() == ISD::AND) { 1500 SDValue AndOp0 = N1.getOperand(0); 1501 ConstantSDNode *AndOp1 = dyn_cast<ConstantSDNode>(N1->getOperand(1)); 1502 unsigned NumSignBits = DAG.ComputeNumSignBits(AndOp0); 1503 unsigned DestBits = VT.getScalarType().getSizeInBits(); 1504 1505 // (add z, (and (sbbl x, x), 1)) -> (sub z, (sbbl x, x)) 1506 // and similar xforms where the inner op is either ~0 or 0. 1507 if (NumSignBits == DestBits && AndOp1 && AndOp1->isOne()) { 1508 DebugLoc DL = N->getDebugLoc(); 1509 return DAG.getNode(ISD::SUB, DL, VT, N->getOperand(0), AndOp0); 1510 } 1511 } 1512 1513 // add (sext i1), X -> sub X, (zext i1) 1514 if (N0.getOpcode() == ISD::SIGN_EXTEND && 1515 N0.getOperand(0).getValueType() == MVT::i1 && 1516 !TLI.isOperationLegal(ISD::SIGN_EXTEND, MVT::i1)) { 1517 DebugLoc DL = N->getDebugLoc(); 1518 SDValue ZExt = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0)); 1519 return DAG.getNode(ISD::SUB, DL, VT, N1, ZExt); 1520 } 1521 1522 return SDValue(); 1523} 1524 1525SDValue DAGCombiner::visitADDC(SDNode *N) { 1526 SDValue N0 = N->getOperand(0); 1527 SDValue N1 = N->getOperand(1); 1528 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1529 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1530 EVT VT = N0.getValueType(); 1531 1532 // If the flag result is dead, turn this into an ADD. 1533 if (!N->hasAnyUseOfValue(1)) 1534 return CombineTo(N, DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, N1), 1535 DAG.getNode(ISD::CARRY_FALSE, 1536 N->getDebugLoc(), MVT::Glue)); 1537 1538 // canonicalize constant to RHS. 1539 if (N0C && !N1C) 1540 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0); 1541 1542 // fold (addc x, 0) -> x + no carry out 1543 if (N1C && N1C->isNullValue()) 1544 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, 1545 N->getDebugLoc(), MVT::Glue)); 1546 1547 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits. 1548 APInt LHSZero, LHSOne; 1549 APInt RHSZero, RHSOne; 1550 APInt Mask = APInt::getAllOnesValue(VT.getScalarType().getSizeInBits()); 1551 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 1552 1553 if (LHSZero.getBoolValue()) { 1554 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 1555 1556 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1557 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1558 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 1559 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 1560 return CombineTo(N, DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1), 1561 DAG.getNode(ISD::CARRY_FALSE, 1562 N->getDebugLoc(), MVT::Glue)); 1563 } 1564 1565 return SDValue(); 1566} 1567 1568SDValue DAGCombiner::visitADDE(SDNode *N) { 1569 SDValue N0 = N->getOperand(0); 1570 SDValue N1 = N->getOperand(1); 1571 SDValue CarryIn = N->getOperand(2); 1572 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1573 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1574 1575 // canonicalize constant to RHS 1576 if (N0C && !N1C) 1577 return DAG.getNode(ISD::ADDE, N->getDebugLoc(), N->getVTList(), 1578 N1, N0, CarryIn); 1579 1580 // fold (adde x, y, false) -> (addc x, y) 1581 if (CarryIn.getOpcode() == ISD::CARRY_FALSE) 1582 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N0, N1); 1583 1584 return SDValue(); 1585} 1586 1587// Since it may not be valid to emit a fold to zero for vector initializers 1588// check if we can before folding. 1589static SDValue tryFoldToZero(DebugLoc DL, const TargetLowering &TLI, EVT VT, 1590 SelectionDAG &DAG, bool LegalOperations) { 1591 if (!VT.isVector()) { 1592 return DAG.getConstant(0, VT); 1593 } 1594 if (!LegalOperations || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) { 1595 // Produce a vector of zeros. 1596 SDValue El = DAG.getConstant(0, VT.getVectorElementType()); 1597 std::vector<SDValue> Ops(VT.getVectorNumElements(), El); 1598 return DAG.getNode(ISD::BUILD_VECTOR, DL, VT, 1599 &Ops[0], Ops.size()); 1600 } 1601 return SDValue(); 1602} 1603 1604SDValue DAGCombiner::visitSUB(SDNode *N) { 1605 SDValue N0 = N->getOperand(0); 1606 SDValue N1 = N->getOperand(1); 1607 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1608 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1609 ConstantSDNode *N1C1 = N1.getOpcode() != ISD::ADD ? 0 : 1610 dyn_cast<ConstantSDNode>(N1.getOperand(1).getNode()); 1611 EVT VT = N0.getValueType(); 1612 1613 // fold vector ops 1614 if (VT.isVector()) { 1615 SDValue FoldedVOp = SimplifyVBinOp(N); 1616 if (FoldedVOp.getNode()) return FoldedVOp; 1617 } 1618 1619 // fold (sub x, x) -> 0 1620 // FIXME: Refactor this and xor and other similar operations together. 1621 if (N0 == N1) 1622 return tryFoldToZero(N->getDebugLoc(), TLI, VT, DAG, LegalOperations); 1623 // fold (sub c1, c2) -> c1-c2 1624 if (N0C && N1C) 1625 return DAG.FoldConstantArithmetic(ISD::SUB, VT, N0C, N1C); 1626 // fold (sub x, c) -> (add x, -c) 1627 if (N1C) 1628 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, 1629 DAG.getConstant(-N1C->getAPIntValue(), VT)); 1630 // Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1) 1631 if (N0C && N0C->isAllOnesValue()) 1632 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0); 1633 // fold A-(A-B) -> B 1634 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(0)) 1635 return N1.getOperand(1); 1636 // fold (A+B)-A -> B 1637 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1) 1638 return N0.getOperand(1); 1639 // fold (A+B)-B -> A 1640 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1) 1641 return N0.getOperand(0); 1642 // fold C2-(A+C1) -> (C2-C1)-A 1643 if (N1.getOpcode() == ISD::ADD && N0C && N1C1) { 1644 SDValue NewC = DAG.getConstant((N0C->getAPIntValue() - N1C1->getAPIntValue()), VT); 1645 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, NewC, 1646 N1.getOperand(0)); 1647 } 1648 // fold ((A+(B+or-C))-B) -> A+or-C 1649 if (N0.getOpcode() == ISD::ADD && 1650 (N0.getOperand(1).getOpcode() == ISD::SUB || 1651 N0.getOperand(1).getOpcode() == ISD::ADD) && 1652 N0.getOperand(1).getOperand(0) == N1) 1653 return DAG.getNode(N0.getOperand(1).getOpcode(), N->getDebugLoc(), VT, 1654 N0.getOperand(0), N0.getOperand(1).getOperand(1)); 1655 // fold ((A+(C+B))-B) -> A+C 1656 if (N0.getOpcode() == ISD::ADD && 1657 N0.getOperand(1).getOpcode() == ISD::ADD && 1658 N0.getOperand(1).getOperand(1) == N1) 1659 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, 1660 N0.getOperand(0), N0.getOperand(1).getOperand(0)); 1661 // fold ((A-(B-C))-C) -> A-B 1662 if (N0.getOpcode() == ISD::SUB && 1663 N0.getOperand(1).getOpcode() == ISD::SUB && 1664 N0.getOperand(1).getOperand(1) == N1) 1665 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1666 N0.getOperand(0), N0.getOperand(1).getOperand(0)); 1667 1668 // If either operand of a sub is undef, the result is undef 1669 if (N0.getOpcode() == ISD::UNDEF) 1670 return N0; 1671 if (N1.getOpcode() == ISD::UNDEF) 1672 return N1; 1673 1674 // If the relocation model supports it, consider symbol offsets. 1675 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0)) 1676 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA)) { 1677 // fold (sub Sym, c) -> Sym-c 1678 if (N1C && GA->getOpcode() == ISD::GlobalAddress) 1679 return DAG.getGlobalAddress(GA->getGlobal(), N1C->getDebugLoc(), VT, 1680 GA->getOffset() - 1681 (uint64_t)N1C->getSExtValue()); 1682 // fold (sub Sym+c1, Sym+c2) -> c1-c2 1683 if (GlobalAddressSDNode *GB = dyn_cast<GlobalAddressSDNode>(N1)) 1684 if (GA->getGlobal() == GB->getGlobal()) 1685 return DAG.getConstant((uint64_t)GA->getOffset() - GB->getOffset(), 1686 VT); 1687 } 1688 1689 return SDValue(); 1690} 1691 1692SDValue DAGCombiner::visitSUBC(SDNode *N) { 1693 SDValue N0 = N->getOperand(0); 1694 SDValue N1 = N->getOperand(1); 1695 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1696 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1697 EVT VT = N0.getValueType(); 1698 1699 // If the flag result is dead, turn this into an SUB. 1700 if (!N->hasAnyUseOfValue(1)) 1701 return CombineTo(N, DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, N1), 1702 DAG.getNode(ISD::CARRY_FALSE, N->getDebugLoc(), 1703 MVT::Glue)); 1704 1705 // fold (subc x, x) -> 0 + no borrow 1706 if (N0 == N1) 1707 return CombineTo(N, DAG.getConstant(0, VT), 1708 DAG.getNode(ISD::CARRY_FALSE, N->getDebugLoc(), 1709 MVT::Glue)); 1710 1711 // fold (subc x, 0) -> x + no borrow 1712 if (N1C && N1C->isNullValue()) 1713 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, N->getDebugLoc(), 1714 MVT::Glue)); 1715 1716 // Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1) + no borrow 1717 if (N0C && N0C->isAllOnesValue()) 1718 return CombineTo(N, DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0), 1719 DAG.getNode(ISD::CARRY_FALSE, N->getDebugLoc(), 1720 MVT::Glue)); 1721 1722 return SDValue(); 1723} 1724 1725SDValue DAGCombiner::visitSUBE(SDNode *N) { 1726 SDValue N0 = N->getOperand(0); 1727 SDValue N1 = N->getOperand(1); 1728 SDValue CarryIn = N->getOperand(2); 1729 1730 // fold (sube x, y, false) -> (subc x, y) 1731 if (CarryIn.getOpcode() == ISD::CARRY_FALSE) 1732 return DAG.getNode(ISD::SUBC, N->getDebugLoc(), N->getVTList(), N0, N1); 1733 1734 return SDValue(); 1735} 1736 1737SDValue DAGCombiner::visitMUL(SDNode *N) { 1738 SDValue N0 = N->getOperand(0); 1739 SDValue N1 = N->getOperand(1); 1740 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1741 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1742 EVT VT = N0.getValueType(); 1743 1744 // fold vector ops 1745 if (VT.isVector()) { 1746 SDValue FoldedVOp = SimplifyVBinOp(N); 1747 if (FoldedVOp.getNode()) return FoldedVOp; 1748 } 1749 1750 // fold (mul x, undef) -> 0 1751 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1752 return DAG.getConstant(0, VT); 1753 // fold (mul c1, c2) -> c1*c2 1754 if (N0C && N1C) 1755 return DAG.FoldConstantArithmetic(ISD::MUL, VT, N0C, N1C); 1756 // canonicalize constant to RHS 1757 if (N0C && !N1C) 1758 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, N1, N0); 1759 // fold (mul x, 0) -> 0 1760 if (N1C && N1C->isNullValue()) 1761 return N1; 1762 // fold (mul x, -1) -> 0-x 1763 if (N1C && N1C->isAllOnesValue()) 1764 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1765 DAG.getConstant(0, VT), N0); 1766 // fold (mul x, (1 << c)) -> x << c 1767 if (N1C && N1C->getAPIntValue().isPowerOf2()) 1768 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 1769 DAG.getConstant(N1C->getAPIntValue().logBase2(), 1770 getShiftAmountTy(N0.getValueType()))); 1771 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c 1772 if (N1C && (-N1C->getAPIntValue()).isPowerOf2()) { 1773 unsigned Log2Val = (-N1C->getAPIntValue()).logBase2(); 1774 // FIXME: If the input is something that is easily negated (e.g. a 1775 // single-use add), we should put the negate there. 1776 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1777 DAG.getConstant(0, VT), 1778 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 1779 DAG.getConstant(Log2Val, 1780 getShiftAmountTy(N0.getValueType())))); 1781 } 1782 // (mul (shl X, c1), c2) -> (mul X, c2 << c1) 1783 if (N1C && N0.getOpcode() == ISD::SHL && 1784 isa<ConstantSDNode>(N0.getOperand(1))) { 1785 SDValue C3 = DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1786 N1, N0.getOperand(1)); 1787 AddToWorkList(C3.getNode()); 1788 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1789 N0.getOperand(0), C3); 1790 } 1791 1792 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one 1793 // use. 1794 { 1795 SDValue Sh(0,0), Y(0,0); 1796 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)). 1797 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) && 1798 N0.getNode()->hasOneUse()) { 1799 Sh = N0; Y = N1; 1800 } else if (N1.getOpcode() == ISD::SHL && 1801 isa<ConstantSDNode>(N1.getOperand(1)) && 1802 N1.getNode()->hasOneUse()) { 1803 Sh = N1; Y = N0; 1804 } 1805 1806 if (Sh.getNode()) { 1807 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1808 Sh.getOperand(0), Y); 1809 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1810 Mul, Sh.getOperand(1)); 1811 } 1812 } 1813 1814 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2) 1815 if (N1C && N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse() && 1816 isa<ConstantSDNode>(N0.getOperand(1))) 1817 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, 1818 DAG.getNode(ISD::MUL, N0.getDebugLoc(), VT, 1819 N0.getOperand(0), N1), 1820 DAG.getNode(ISD::MUL, N1.getDebugLoc(), VT, 1821 N0.getOperand(1), N1)); 1822 1823 // reassociate mul 1824 SDValue RMUL = ReassociateOps(ISD::MUL, N->getDebugLoc(), N0, N1); 1825 if (RMUL.getNode() != 0) 1826 return RMUL; 1827 1828 return SDValue(); 1829} 1830 1831SDValue DAGCombiner::visitSDIV(SDNode *N) { 1832 SDValue N0 = N->getOperand(0); 1833 SDValue N1 = N->getOperand(1); 1834 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1835 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1836 EVT VT = N->getValueType(0); 1837 1838 // fold vector ops 1839 if (VT.isVector()) { 1840 SDValue FoldedVOp = SimplifyVBinOp(N); 1841 if (FoldedVOp.getNode()) return FoldedVOp; 1842 } 1843 1844 // fold (sdiv c1, c2) -> c1/c2 1845 if (N0C && N1C && !N1C->isNullValue()) 1846 return DAG.FoldConstantArithmetic(ISD::SDIV, VT, N0C, N1C); 1847 // fold (sdiv X, 1) -> X 1848 if (N1C && N1C->getAPIntValue() == 1LL) 1849 return N0; 1850 // fold (sdiv X, -1) -> 0-X 1851 if (N1C && N1C->isAllOnesValue()) 1852 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1853 DAG.getConstant(0, VT), N0); 1854 // If we know the sign bits of both operands are zero, strength reduce to a 1855 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2 1856 if (!VT.isVector()) { 1857 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 1858 return DAG.getNode(ISD::UDIV, N->getDebugLoc(), N1.getValueType(), 1859 N0, N1); 1860 } 1861 // fold (sdiv X, pow2) -> simple ops after legalize 1862 if (N1C && !N1C->isNullValue() && 1863 (N1C->getAPIntValue().isPowerOf2() || 1864 (-N1C->getAPIntValue()).isPowerOf2())) { 1865 // If dividing by powers of two is cheap, then don't perform the following 1866 // fold. 1867 if (TLI.isPow2DivCheap()) 1868 return SDValue(); 1869 1870 unsigned lg2 = N1C->getAPIntValue().countTrailingZeros(); 1871 1872 // Splat the sign bit into the register 1873 SDValue SGN = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0, 1874 DAG.getConstant(VT.getSizeInBits()-1, 1875 getShiftAmountTy(N0.getValueType()))); 1876 AddToWorkList(SGN.getNode()); 1877 1878 // Add (N0 < 0) ? abs2 - 1 : 0; 1879 SDValue SRL = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, SGN, 1880 DAG.getConstant(VT.getSizeInBits() - lg2, 1881 getShiftAmountTy(SGN.getValueType()))); 1882 SDValue ADD = DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, SRL); 1883 AddToWorkList(SRL.getNode()); 1884 AddToWorkList(ADD.getNode()); // Divide by pow2 1885 SDValue SRA = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, ADD, 1886 DAG.getConstant(lg2, getShiftAmountTy(ADD.getValueType()))); 1887 1888 // If we're dividing by a positive value, we're done. Otherwise, we must 1889 // negate the result. 1890 if (N1C->getAPIntValue().isNonNegative()) 1891 return SRA; 1892 1893 AddToWorkList(SRA.getNode()); 1894 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1895 DAG.getConstant(0, VT), SRA); 1896 } 1897 1898 // if integer divide is expensive and we satisfy the requirements, emit an 1899 // alternate sequence. 1900 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) { 1901 SDValue Op = BuildSDIV(N); 1902 if (Op.getNode()) return Op; 1903 } 1904 1905 // undef / X -> 0 1906 if (N0.getOpcode() == ISD::UNDEF) 1907 return DAG.getConstant(0, VT); 1908 // X / undef -> undef 1909 if (N1.getOpcode() == ISD::UNDEF) 1910 return N1; 1911 1912 return SDValue(); 1913} 1914 1915SDValue DAGCombiner::visitUDIV(SDNode *N) { 1916 SDValue N0 = N->getOperand(0); 1917 SDValue N1 = N->getOperand(1); 1918 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1919 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1920 EVT VT = N->getValueType(0); 1921 1922 // fold vector ops 1923 if (VT.isVector()) { 1924 SDValue FoldedVOp = SimplifyVBinOp(N); 1925 if (FoldedVOp.getNode()) return FoldedVOp; 1926 } 1927 1928 // fold (udiv c1, c2) -> c1/c2 1929 if (N0C && N1C && !N1C->isNullValue()) 1930 return DAG.FoldConstantArithmetic(ISD::UDIV, VT, N0C, N1C); 1931 // fold (udiv x, (1 << c)) -> x >>u c 1932 if (N1C && N1C->getAPIntValue().isPowerOf2()) 1933 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, 1934 DAG.getConstant(N1C->getAPIntValue().logBase2(), 1935 getShiftAmountTy(N0.getValueType()))); 1936 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2 1937 if (N1.getOpcode() == ISD::SHL) { 1938 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1939 if (SHC->getAPIntValue().isPowerOf2()) { 1940 EVT ADDVT = N1.getOperand(1).getValueType(); 1941 SDValue Add = DAG.getNode(ISD::ADD, N->getDebugLoc(), ADDVT, 1942 N1.getOperand(1), 1943 DAG.getConstant(SHC->getAPIntValue() 1944 .logBase2(), 1945 ADDVT)); 1946 AddToWorkList(Add.getNode()); 1947 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, Add); 1948 } 1949 } 1950 } 1951 // fold (udiv x, c) -> alternate 1952 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) { 1953 SDValue Op = BuildUDIV(N); 1954 if (Op.getNode()) return Op; 1955 } 1956 1957 // undef / X -> 0 1958 if (N0.getOpcode() == ISD::UNDEF) 1959 return DAG.getConstant(0, VT); 1960 // X / undef -> undef 1961 if (N1.getOpcode() == ISD::UNDEF) 1962 return N1; 1963 1964 return SDValue(); 1965} 1966 1967SDValue DAGCombiner::visitSREM(SDNode *N) { 1968 SDValue N0 = N->getOperand(0); 1969 SDValue N1 = N->getOperand(1); 1970 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1971 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1972 EVT VT = N->getValueType(0); 1973 1974 // fold (srem c1, c2) -> c1%c2 1975 if (N0C && N1C && !N1C->isNullValue()) 1976 return DAG.FoldConstantArithmetic(ISD::SREM, VT, N0C, N1C); 1977 // If we know the sign bits of both operands are zero, strength reduce to a 1978 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15 1979 if (!VT.isVector()) { 1980 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 1981 return DAG.getNode(ISD::UREM, N->getDebugLoc(), VT, N0, N1); 1982 } 1983 1984 // If X/C can be simplified by the division-by-constant logic, lower 1985 // X%C to the equivalent of X-X/C*C. 1986 if (N1C && !N1C->isNullValue()) { 1987 SDValue Div = DAG.getNode(ISD::SDIV, N->getDebugLoc(), VT, N0, N1); 1988 AddToWorkList(Div.getNode()); 1989 SDValue OptimizedDiv = combine(Div.getNode()); 1990 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) { 1991 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1992 OptimizedDiv, N1); 1993 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul); 1994 AddToWorkList(Mul.getNode()); 1995 return Sub; 1996 } 1997 } 1998 1999 // undef % X -> 0 2000 if (N0.getOpcode() == ISD::UNDEF) 2001 return DAG.getConstant(0, VT); 2002 // X % undef -> undef 2003 if (N1.getOpcode() == ISD::UNDEF) 2004 return N1; 2005 2006 return SDValue(); 2007} 2008 2009SDValue DAGCombiner::visitUREM(SDNode *N) { 2010 SDValue N0 = N->getOperand(0); 2011 SDValue N1 = N->getOperand(1); 2012 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2013 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2014 EVT VT = N->getValueType(0); 2015 2016 // fold (urem c1, c2) -> c1%c2 2017 if (N0C && N1C && !N1C->isNullValue()) 2018 return DAG.FoldConstantArithmetic(ISD::UREM, VT, N0C, N1C); 2019 // fold (urem x, pow2) -> (and x, pow2-1) 2020 if (N1C && !N1C->isNullValue() && N1C->getAPIntValue().isPowerOf2()) 2021 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, 2022 DAG.getConstant(N1C->getAPIntValue()-1,VT)); 2023 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1)) 2024 if (N1.getOpcode() == ISD::SHL) { 2025 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 2026 if (SHC->getAPIntValue().isPowerOf2()) { 2027 SDValue Add = 2028 DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, 2029 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), 2030 VT)); 2031 AddToWorkList(Add.getNode()); 2032 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, Add); 2033 } 2034 } 2035 } 2036 2037 // If X/C can be simplified by the division-by-constant logic, lower 2038 // X%C to the equivalent of X-X/C*C. 2039 if (N1C && !N1C->isNullValue()) { 2040 SDValue Div = DAG.getNode(ISD::UDIV, N->getDebugLoc(), VT, N0, N1); 2041 AddToWorkList(Div.getNode()); 2042 SDValue OptimizedDiv = combine(Div.getNode()); 2043 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) { 2044 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 2045 OptimizedDiv, N1); 2046 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul); 2047 AddToWorkList(Mul.getNode()); 2048 return Sub; 2049 } 2050 } 2051 2052 // undef % X -> 0 2053 if (N0.getOpcode() == ISD::UNDEF) 2054 return DAG.getConstant(0, VT); 2055 // X % undef -> undef 2056 if (N1.getOpcode() == ISD::UNDEF) 2057 return N1; 2058 2059 return SDValue(); 2060} 2061 2062SDValue DAGCombiner::visitMULHS(SDNode *N) { 2063 SDValue N0 = N->getOperand(0); 2064 SDValue N1 = N->getOperand(1); 2065 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2066 EVT VT = N->getValueType(0); 2067 DebugLoc DL = N->getDebugLoc(); 2068 2069 // fold (mulhs x, 0) -> 0 2070 if (N1C && N1C->isNullValue()) 2071 return N1; 2072 // fold (mulhs x, 1) -> (sra x, size(x)-1) 2073 if (N1C && N1C->getAPIntValue() == 1) 2074 return DAG.getNode(ISD::SRA, N->getDebugLoc(), N0.getValueType(), N0, 2075 DAG.getConstant(N0.getValueType().getSizeInBits() - 1, 2076 getShiftAmountTy(N0.getValueType()))); 2077 // fold (mulhs x, undef) -> 0 2078 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 2079 return DAG.getConstant(0, VT); 2080 2081 // If the type twice as wide is legal, transform the mulhs to a wider multiply 2082 // plus a shift. 2083 if (VT.isSimple() && !VT.isVector()) { 2084 MVT Simple = VT.getSimpleVT(); 2085 unsigned SimpleSize = Simple.getSizeInBits(); 2086 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2); 2087 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { 2088 N0 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N0); 2089 N1 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N1); 2090 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1); 2091 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1, 2092 DAG.getConstant(SimpleSize, getShiftAmountTy(N1.getValueType()))); 2093 return DAG.getNode(ISD::TRUNCATE, DL, VT, N1); 2094 } 2095 } 2096 2097 return SDValue(); 2098} 2099 2100SDValue DAGCombiner::visitMULHU(SDNode *N) { 2101 SDValue N0 = N->getOperand(0); 2102 SDValue N1 = N->getOperand(1); 2103 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2104 EVT VT = N->getValueType(0); 2105 DebugLoc DL = N->getDebugLoc(); 2106 2107 // fold (mulhu x, 0) -> 0 2108 if (N1C && N1C->isNullValue()) 2109 return N1; 2110 // fold (mulhu x, 1) -> 0 2111 if (N1C && N1C->getAPIntValue() == 1) 2112 return DAG.getConstant(0, N0.getValueType()); 2113 // fold (mulhu x, undef) -> 0 2114 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 2115 return DAG.getConstant(0, VT); 2116 2117 // If the type twice as wide is legal, transform the mulhu to a wider multiply 2118 // plus a shift. 2119 if (VT.isSimple() && !VT.isVector()) { 2120 MVT Simple = VT.getSimpleVT(); 2121 unsigned SimpleSize = Simple.getSizeInBits(); 2122 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2); 2123 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { 2124 N0 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N0); 2125 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N1); 2126 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1); 2127 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1, 2128 DAG.getConstant(SimpleSize, getShiftAmountTy(N1.getValueType()))); 2129 return DAG.getNode(ISD::TRUNCATE, DL, VT, N1); 2130 } 2131 } 2132 2133 return SDValue(); 2134} 2135 2136/// SimplifyNodeWithTwoResults - Perform optimizations common to nodes that 2137/// compute two values. LoOp and HiOp give the opcodes for the two computations 2138/// that are being performed. Return true if a simplification was made. 2139/// 2140SDValue DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 2141 unsigned HiOp) { 2142 // If the high half is not needed, just compute the low half. 2143 bool HiExists = N->hasAnyUseOfValue(1); 2144 if (!HiExists && 2145 (!LegalOperations || 2146 TLI.isOperationLegal(LoOp, N->getValueType(0)))) { 2147 SDValue Res = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0), 2148 N->op_begin(), N->getNumOperands()); 2149 return CombineTo(N, Res, Res); 2150 } 2151 2152 // If the low half is not needed, just compute the high half. 2153 bool LoExists = N->hasAnyUseOfValue(0); 2154 if (!LoExists && 2155 (!LegalOperations || 2156 TLI.isOperationLegal(HiOp, N->getValueType(1)))) { 2157 SDValue Res = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1), 2158 N->op_begin(), N->getNumOperands()); 2159 return CombineTo(N, Res, Res); 2160 } 2161 2162 // If both halves are used, return as it is. 2163 if (LoExists && HiExists) 2164 return SDValue(); 2165 2166 // If the two computed results can be simplified separately, separate them. 2167 if (LoExists) { 2168 SDValue Lo = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0), 2169 N->op_begin(), N->getNumOperands()); 2170 AddToWorkList(Lo.getNode()); 2171 SDValue LoOpt = combine(Lo.getNode()); 2172 if (LoOpt.getNode() && LoOpt.getNode() != Lo.getNode() && 2173 (!LegalOperations || 2174 TLI.isOperationLegal(LoOpt.getOpcode(), LoOpt.getValueType()))) 2175 return CombineTo(N, LoOpt, LoOpt); 2176 } 2177 2178 if (HiExists) { 2179 SDValue Hi = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1), 2180 N->op_begin(), N->getNumOperands()); 2181 AddToWorkList(Hi.getNode()); 2182 SDValue HiOpt = combine(Hi.getNode()); 2183 if (HiOpt.getNode() && HiOpt != Hi && 2184 (!LegalOperations || 2185 TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType()))) 2186 return CombineTo(N, HiOpt, HiOpt); 2187 } 2188 2189 return SDValue(); 2190} 2191 2192SDValue DAGCombiner::visitSMUL_LOHI(SDNode *N) { 2193 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS); 2194 if (Res.getNode()) return Res; 2195 2196 EVT VT = N->getValueType(0); 2197 DebugLoc DL = N->getDebugLoc(); 2198 2199 // If the type twice as wide is legal, transform the mulhu to a wider multiply 2200 // plus a shift. 2201 if (VT.isSimple() && !VT.isVector()) { 2202 MVT Simple = VT.getSimpleVT(); 2203 unsigned SimpleSize = Simple.getSizeInBits(); 2204 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2); 2205 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { 2206 SDValue Lo = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(0)); 2207 SDValue Hi = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(1)); 2208 Lo = DAG.getNode(ISD::MUL, DL, NewVT, Lo, Hi); 2209 // Compute the high part as N1. 2210 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo, 2211 DAG.getConstant(SimpleSize, getShiftAmountTy(Lo.getValueType()))); 2212 Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi); 2213 // Compute the low part as N0. 2214 Lo = DAG.getNode(ISD::TRUNCATE, DL, VT, Lo); 2215 return CombineTo(N, Lo, Hi); 2216 } 2217 } 2218 2219 return SDValue(); 2220} 2221 2222SDValue DAGCombiner::visitUMUL_LOHI(SDNode *N) { 2223 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU); 2224 if (Res.getNode()) return Res; 2225 2226 EVT VT = N->getValueType(0); 2227 DebugLoc DL = N->getDebugLoc(); 2228 2229 // If the type twice as wide is legal, transform the mulhu to a wider multiply 2230 // plus a shift. 2231 if (VT.isSimple() && !VT.isVector()) { 2232 MVT Simple = VT.getSimpleVT(); 2233 unsigned SimpleSize = Simple.getSizeInBits(); 2234 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2); 2235 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { 2236 SDValue Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(0)); 2237 SDValue Hi = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(1)); 2238 Lo = DAG.getNode(ISD::MUL, DL, NewVT, Lo, Hi); 2239 // Compute the high part as N1. 2240 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo, 2241 DAG.getConstant(SimpleSize, getShiftAmountTy(Lo.getValueType()))); 2242 Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi); 2243 // Compute the low part as N0. 2244 Lo = DAG.getNode(ISD::TRUNCATE, DL, VT, Lo); 2245 return CombineTo(N, Lo, Hi); 2246 } 2247 } 2248 2249 return SDValue(); 2250} 2251 2252SDValue DAGCombiner::visitSMULO(SDNode *N) { 2253 // (smulo x, 2) -> (saddo x, x) 2254 if (ConstantSDNode *C2 = dyn_cast<ConstantSDNode>(N->getOperand(1))) 2255 if (C2->getAPIntValue() == 2) 2256 return DAG.getNode(ISD::SADDO, N->getDebugLoc(), N->getVTList(), 2257 N->getOperand(0), N->getOperand(0)); 2258 2259 return SDValue(); 2260} 2261 2262SDValue DAGCombiner::visitUMULO(SDNode *N) { 2263 // (umulo x, 2) -> (uaddo x, x) 2264 if (ConstantSDNode *C2 = dyn_cast<ConstantSDNode>(N->getOperand(1))) 2265 if (C2->getAPIntValue() == 2) 2266 return DAG.getNode(ISD::UADDO, N->getDebugLoc(), N->getVTList(), 2267 N->getOperand(0), N->getOperand(0)); 2268 2269 return SDValue(); 2270} 2271 2272SDValue DAGCombiner::visitSDIVREM(SDNode *N) { 2273 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM); 2274 if (Res.getNode()) return Res; 2275 2276 return SDValue(); 2277} 2278 2279SDValue DAGCombiner::visitUDIVREM(SDNode *N) { 2280 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM); 2281 if (Res.getNode()) return Res; 2282 2283 return SDValue(); 2284} 2285 2286/// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with 2287/// two operands of the same opcode, try to simplify it. 2288SDValue DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) { 2289 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1); 2290 EVT VT = N0.getValueType(); 2291 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!"); 2292 2293 // Bail early if none of these transforms apply. 2294 if (N0.getNode()->getNumOperands() == 0) return SDValue(); 2295 2296 // For each of OP in AND/OR/XOR: 2297 // fold (OP (zext x), (zext y)) -> (zext (OP x, y)) 2298 // fold (OP (sext x), (sext y)) -> (sext (OP x, y)) 2299 // fold (OP (aext x), (aext y)) -> (aext (OP x, y)) 2300 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y)) (if trunc isn't free) 2301 // 2302 // do not sink logical op inside of a vector extend, since it may combine 2303 // into a vsetcc. 2304 EVT Op0VT = N0.getOperand(0).getValueType(); 2305 if ((N0.getOpcode() == ISD::ZERO_EXTEND || 2306 N0.getOpcode() == ISD::SIGN_EXTEND || 2307 // Avoid infinite looping with PromoteIntBinOp. 2308 (N0.getOpcode() == ISD::ANY_EXTEND && 2309 (!LegalTypes || TLI.isTypeDesirableForOp(N->getOpcode(), Op0VT))) || 2310 (N0.getOpcode() == ISD::TRUNCATE && 2311 (!TLI.isZExtFree(VT, Op0VT) || 2312 !TLI.isTruncateFree(Op0VT, VT)) && 2313 TLI.isTypeLegal(Op0VT))) && 2314 !VT.isVector() && 2315 Op0VT == N1.getOperand(0).getValueType() && 2316 (!LegalOperations || TLI.isOperationLegal(N->getOpcode(), Op0VT))) { 2317 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(), 2318 N0.getOperand(0).getValueType(), 2319 N0.getOperand(0), N1.getOperand(0)); 2320 AddToWorkList(ORNode.getNode()); 2321 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, ORNode); 2322 } 2323 2324 // For each of OP in SHL/SRL/SRA/AND... 2325 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z) 2326 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z) 2327 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z) 2328 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL || 2329 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) && 2330 N0.getOperand(1) == N1.getOperand(1)) { 2331 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(), 2332 N0.getOperand(0).getValueType(), 2333 N0.getOperand(0), N1.getOperand(0)); 2334 AddToWorkList(ORNode.getNode()); 2335 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, 2336 ORNode, N0.getOperand(1)); 2337 } 2338 2339 return SDValue(); 2340} 2341 2342SDValue DAGCombiner::visitAND(SDNode *N) { 2343 SDValue N0 = N->getOperand(0); 2344 SDValue N1 = N->getOperand(1); 2345 SDValue LL, LR, RL, RR, CC0, CC1; 2346 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2347 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2348 EVT VT = N1.getValueType(); 2349 unsigned BitWidth = VT.getScalarType().getSizeInBits(); 2350 2351 // fold vector ops 2352 if (VT.isVector()) { 2353 SDValue FoldedVOp = SimplifyVBinOp(N); 2354 if (FoldedVOp.getNode()) return FoldedVOp; 2355 } 2356 2357 // fold (and x, undef) -> 0 2358 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 2359 return DAG.getConstant(0, VT); 2360 // fold (and c1, c2) -> c1&c2 2361 if (N0C && N1C) 2362 return DAG.FoldConstantArithmetic(ISD::AND, VT, N0C, N1C); 2363 // canonicalize constant to RHS 2364 if (N0C && !N1C) 2365 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N1, N0); 2366 // fold (and x, -1) -> x 2367 if (N1C && N1C->isAllOnesValue()) 2368 return N0; 2369 // if (and x, c) is known to be zero, return 0 2370 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0), 2371 APInt::getAllOnesValue(BitWidth))) 2372 return DAG.getConstant(0, VT); 2373 // reassociate and 2374 SDValue RAND = ReassociateOps(ISD::AND, N->getDebugLoc(), N0, N1); 2375 if (RAND.getNode() != 0) 2376 return RAND; 2377 // fold (and (or x, C), D) -> D if (C & D) == D 2378 if (N1C && N0.getOpcode() == ISD::OR) 2379 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 2380 if ((ORI->getAPIntValue() & N1C->getAPIntValue()) == N1C->getAPIntValue()) 2381 return N1; 2382 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits. 2383 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 2384 SDValue N0Op0 = N0.getOperand(0); 2385 APInt Mask = ~N1C->getAPIntValue(); 2386 Mask = Mask.trunc(N0Op0.getValueSizeInBits()); 2387 if (DAG.MaskedValueIsZero(N0Op0, Mask)) { 2388 SDValue Zext = DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), 2389 N0.getValueType(), N0Op0); 2390 2391 // Replace uses of the AND with uses of the Zero extend node. 2392 CombineTo(N, Zext); 2393 2394 // We actually want to replace all uses of the any_extend with the 2395 // zero_extend, to avoid duplicating things. This will later cause this 2396 // AND to be folded. 2397 CombineTo(N0.getNode(), Zext); 2398 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2399 } 2400 } 2401 // similarly fold (and (X (load ([non_ext|any_ext|zero_ext] V))), c) -> 2402 // (X (load ([non_ext|zero_ext] V))) if 'and' only clears top bits which must 2403 // already be zero by virtue of the width of the base type of the load. 2404 // 2405 // the 'X' node here can either be nothing or an extract_vector_elt to catch 2406 // more cases. 2407 if ((N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT && 2408 N0.getOperand(0).getOpcode() == ISD::LOAD) || 2409 N0.getOpcode() == ISD::LOAD) { 2410 LoadSDNode *Load = cast<LoadSDNode>( (N0.getOpcode() == ISD::LOAD) ? 2411 N0 : N0.getOperand(0) ); 2412 2413 // Get the constant (if applicable) the zero'th operand is being ANDed with. 2414 // This can be a pure constant or a vector splat, in which case we treat the 2415 // vector as a scalar and use the splat value. 2416 APInt Constant = APInt::getNullValue(1); 2417 if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(N1)) { 2418 Constant = C->getAPIntValue(); 2419 } else if (BuildVectorSDNode *Vector = dyn_cast<BuildVectorSDNode>(N1)) { 2420 APInt SplatValue, SplatUndef; 2421 unsigned SplatBitSize; 2422 bool HasAnyUndefs; 2423 bool IsSplat = Vector->isConstantSplat(SplatValue, SplatUndef, 2424 SplatBitSize, HasAnyUndefs); 2425 if (IsSplat) { 2426 // Undef bits can contribute to a possible optimisation if set, so 2427 // set them. 2428 SplatValue |= SplatUndef; 2429 2430 // The splat value may be something like "0x00FFFFFF", which means 0 for 2431 // the first vector value and FF for the rest, repeating. We need a mask 2432 // that will apply equally to all members of the vector, so AND all the 2433 // lanes of the constant together. 2434 EVT VT = Vector->getValueType(0); 2435 unsigned BitWidth = VT.getVectorElementType().getSizeInBits(); 2436 Constant = APInt::getAllOnesValue(BitWidth); 2437 for (unsigned i = 0, n = VT.getVectorNumElements(); i < n; ++i) 2438 Constant &= SplatValue.lshr(i*BitWidth).zextOrTrunc(BitWidth); 2439 } 2440 } 2441 2442 // If we want to change an EXTLOAD to a ZEXTLOAD, ensure a ZEXTLOAD is 2443 // actually legal and isn't going to get expanded, else this is a false 2444 // optimisation. 2445 bool CanZextLoadProfitably = TLI.isLoadExtLegal(ISD::ZEXTLOAD, 2446 Load->getMemoryVT()); 2447 2448 // Resize the constant to the same size as the original memory access before 2449 // extension. If it is still the AllOnesValue then this AND is completely 2450 // unneeded. 2451 Constant = 2452 Constant.zextOrTrunc(Load->getMemoryVT().getScalarType().getSizeInBits()); 2453 2454 bool B; 2455 switch (Load->getExtensionType()) { 2456 default: B = false; break; 2457 case ISD::EXTLOAD: B = CanZextLoadProfitably; break; 2458 case ISD::ZEXTLOAD: 2459 case ISD::NON_EXTLOAD: B = true; break; 2460 } 2461 2462 if (B && Constant.isAllOnesValue()) { 2463 // If the load type was an EXTLOAD, convert to ZEXTLOAD in order to 2464 // preserve semantics once we get rid of the AND. 2465 SDValue NewLoad(Load, 0); 2466 if (Load->getExtensionType() == ISD::EXTLOAD) { 2467 NewLoad = DAG.getLoad(Load->getAddressingMode(), ISD::ZEXTLOAD, 2468 Load->getValueType(0), Load->getDebugLoc(), 2469 Load->getChain(), Load->getBasePtr(), 2470 Load->getOffset(), Load->getMemoryVT(), 2471 Load->getMemOperand()); 2472 // Replace uses of the EXTLOAD with the new ZEXTLOAD. 2473 CombineTo(Load, NewLoad.getValue(0), NewLoad.getValue(1)); 2474 } 2475 2476 // Fold the AND away, taking care not to fold to the old load node if we 2477 // replaced it. 2478 CombineTo(N, (N0.getNode() == Load) ? NewLoad : N0); 2479 2480 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2481 } 2482 } 2483 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y)) 2484 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 2485 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 2486 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 2487 2488 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 2489 LL.getValueType().isInteger()) { 2490 // fold (and (seteq X, 0), (seteq Y, 0)) -> (seteq (or X, Y), 0) 2491 if (cast<ConstantSDNode>(LR)->isNullValue() && Op1 == ISD::SETEQ) { 2492 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(), 2493 LR.getValueType(), LL, RL); 2494 AddToWorkList(ORNode.getNode()); 2495 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 2496 } 2497 // fold (and (seteq X, -1), (seteq Y, -1)) -> (seteq (and X, Y), -1) 2498 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) { 2499 SDValue ANDNode = DAG.getNode(ISD::AND, N0.getDebugLoc(), 2500 LR.getValueType(), LL, RL); 2501 AddToWorkList(ANDNode.getNode()); 2502 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1); 2503 } 2504 // fold (and (setgt X, -1), (setgt Y, -1)) -> (setgt (or X, Y), -1) 2505 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) { 2506 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(), 2507 LR.getValueType(), LL, RL); 2508 AddToWorkList(ORNode.getNode()); 2509 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 2510 } 2511 } 2512 // canonicalize equivalent to ll == rl 2513 if (LL == RR && LR == RL) { 2514 Op1 = ISD::getSetCCSwappedOperands(Op1); 2515 std::swap(RL, RR); 2516 } 2517 if (LL == RL && LR == RR) { 2518 bool isInteger = LL.getValueType().isInteger(); 2519 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger); 2520 if (Result != ISD::SETCC_INVALID && 2521 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType()))) 2522 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(), 2523 LL, LR, Result); 2524 } 2525 } 2526 2527 // Simplify: (and (op x...), (op y...)) -> (op (and x, y)) 2528 if (N0.getOpcode() == N1.getOpcode()) { 2529 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 2530 if (Tmp.getNode()) return Tmp; 2531 } 2532 2533 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1) 2534 // fold (and (sra)) -> (and (srl)) when possible. 2535 if (!VT.isVector() && 2536 SimplifyDemandedBits(SDValue(N, 0))) 2537 return SDValue(N, 0); 2538 2539 // fold (zext_inreg (extload x)) -> (zextload x) 2540 if (ISD::isEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode())) { 2541 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2542 EVT MemVT = LN0->getMemoryVT(); 2543 // If we zero all the possible extended bits, then we can turn this into 2544 // a zextload if we are running before legalize or the operation is legal. 2545 unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits(); 2546 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 2547 BitWidth - MemVT.getScalarType().getSizeInBits())) && 2548 ((!LegalOperations && !LN0->isVolatile()) || 2549 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) { 2550 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT, 2551 LN0->getChain(), LN0->getBasePtr(), 2552 LN0->getPointerInfo(), MemVT, 2553 LN0->isVolatile(), LN0->isNonTemporal(), 2554 LN0->getAlignment()); 2555 AddToWorkList(N); 2556 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 2557 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2558 } 2559 } 2560 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use 2561 if (ISD::isSEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 2562 N0.hasOneUse()) { 2563 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2564 EVT MemVT = LN0->getMemoryVT(); 2565 // If we zero all the possible extended bits, then we can turn this into 2566 // a zextload if we are running before legalize or the operation is legal. 2567 unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits(); 2568 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 2569 BitWidth - MemVT.getScalarType().getSizeInBits())) && 2570 ((!LegalOperations && !LN0->isVolatile()) || 2571 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) { 2572 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT, 2573 LN0->getChain(), 2574 LN0->getBasePtr(), LN0->getPointerInfo(), 2575 MemVT, 2576 LN0->isVolatile(), LN0->isNonTemporal(), 2577 LN0->getAlignment()); 2578 AddToWorkList(N); 2579 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 2580 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2581 } 2582 } 2583 2584 // fold (and (load x), 255) -> (zextload x, i8) 2585 // fold (and (extload x, i16), 255) -> (zextload x, i8) 2586 // fold (and (any_ext (extload x, i16)), 255) -> (zextload x, i8) 2587 if (N1C && (N0.getOpcode() == ISD::LOAD || 2588 (N0.getOpcode() == ISD::ANY_EXTEND && 2589 N0.getOperand(0).getOpcode() == ISD::LOAD))) { 2590 bool HasAnyExt = N0.getOpcode() == ISD::ANY_EXTEND; 2591 LoadSDNode *LN0 = HasAnyExt 2592 ? cast<LoadSDNode>(N0.getOperand(0)) 2593 : cast<LoadSDNode>(N0); 2594 if (LN0->getExtensionType() != ISD::SEXTLOAD && 2595 LN0->isUnindexed() && N0.hasOneUse() && LN0->hasOneUse()) { 2596 uint32_t ActiveBits = N1C->getAPIntValue().getActiveBits(); 2597 if (ActiveBits > 0 && APIntOps::isMask(ActiveBits, N1C->getAPIntValue())){ 2598 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), ActiveBits); 2599 EVT LoadedVT = LN0->getMemoryVT(); 2600 2601 if (ExtVT == LoadedVT && 2602 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) { 2603 EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT; 2604 2605 SDValue NewLoad = 2606 DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), LoadResultTy, 2607 LN0->getChain(), LN0->getBasePtr(), 2608 LN0->getPointerInfo(), 2609 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(), 2610 LN0->getAlignment()); 2611 AddToWorkList(N); 2612 CombineTo(LN0, NewLoad, NewLoad.getValue(1)); 2613 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2614 } 2615 2616 // Do not change the width of a volatile load. 2617 // Do not generate loads of non-round integer types since these can 2618 // be expensive (and would be wrong if the type is not byte sized). 2619 if (!LN0->isVolatile() && LoadedVT.bitsGT(ExtVT) && ExtVT.isRound() && 2620 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) { 2621 EVT PtrType = LN0->getOperand(1).getValueType(); 2622 2623 unsigned Alignment = LN0->getAlignment(); 2624 SDValue NewPtr = LN0->getBasePtr(); 2625 2626 // For big endian targets, we need to add an offset to the pointer 2627 // to load the correct bytes. For little endian systems, we merely 2628 // need to read fewer bytes from the same pointer. 2629 if (TLI.isBigEndian()) { 2630 unsigned LVTStoreBytes = LoadedVT.getStoreSize(); 2631 unsigned EVTStoreBytes = ExtVT.getStoreSize(); 2632 unsigned PtrOff = LVTStoreBytes - EVTStoreBytes; 2633 NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(), PtrType, 2634 NewPtr, DAG.getConstant(PtrOff, PtrType)); 2635 Alignment = MinAlign(Alignment, PtrOff); 2636 } 2637 2638 AddToWorkList(NewPtr.getNode()); 2639 2640 EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT; 2641 SDValue Load = 2642 DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), LoadResultTy, 2643 LN0->getChain(), NewPtr, 2644 LN0->getPointerInfo(), 2645 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(), 2646 Alignment); 2647 AddToWorkList(N); 2648 CombineTo(LN0, Load, Load.getValue(1)); 2649 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2650 } 2651 } 2652 } 2653 } 2654 2655 return SDValue(); 2656} 2657 2658/// MatchBSwapHWord - Match (a >> 8) | (a << 8) as (bswap a) >> 16 2659/// 2660SDValue DAGCombiner::MatchBSwapHWordLow(SDNode *N, SDValue N0, SDValue N1, 2661 bool DemandHighBits) { 2662 if (!LegalOperations) 2663 return SDValue(); 2664 2665 EVT VT = N->getValueType(0); 2666 if (VT != MVT::i64 && VT != MVT::i32 && VT != MVT::i16) 2667 return SDValue(); 2668 if (!TLI.isOperationLegal(ISD::BSWAP, VT)) 2669 return SDValue(); 2670 2671 // Recognize (and (shl a, 8), 0xff), (and (srl a, 8), 0xff00) 2672 bool LookPassAnd0 = false; 2673 bool LookPassAnd1 = false; 2674 if (N0.getOpcode() == ISD::AND && N0.getOperand(0).getOpcode() == ISD::SRL) 2675 std::swap(N0, N1); 2676 if (N1.getOpcode() == ISD::AND && N1.getOperand(0).getOpcode() == ISD::SHL) 2677 std::swap(N0, N1); 2678 if (N0.getOpcode() == ISD::AND) { 2679 if (!N0.getNode()->hasOneUse()) 2680 return SDValue(); 2681 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2682 if (!N01C || N01C->getZExtValue() != 0xFF00) 2683 return SDValue(); 2684 N0 = N0.getOperand(0); 2685 LookPassAnd0 = true; 2686 } 2687 2688 if (N1.getOpcode() == ISD::AND) { 2689 if (!N1.getNode()->hasOneUse()) 2690 return SDValue(); 2691 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1)); 2692 if (!N11C || N11C->getZExtValue() != 0xFF) 2693 return SDValue(); 2694 N1 = N1.getOperand(0); 2695 LookPassAnd1 = true; 2696 } 2697 2698 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL) 2699 std::swap(N0, N1); 2700 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL) 2701 return SDValue(); 2702 if (!N0.getNode()->hasOneUse() || 2703 !N1.getNode()->hasOneUse()) 2704 return SDValue(); 2705 2706 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2707 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1)); 2708 if (!N01C || !N11C) 2709 return SDValue(); 2710 if (N01C->getZExtValue() != 8 || N11C->getZExtValue() != 8) 2711 return SDValue(); 2712 2713 // Look for (shl (and a, 0xff), 8), (srl (and a, 0xff00), 8) 2714 SDValue N00 = N0->getOperand(0); 2715 if (!LookPassAnd0 && N00.getOpcode() == ISD::AND) { 2716 if (!N00.getNode()->hasOneUse()) 2717 return SDValue(); 2718 ConstantSDNode *N001C = dyn_cast<ConstantSDNode>(N00.getOperand(1)); 2719 if (!N001C || N001C->getZExtValue() != 0xFF) 2720 return SDValue(); 2721 N00 = N00.getOperand(0); 2722 LookPassAnd0 = true; 2723 } 2724 2725 SDValue N10 = N1->getOperand(0); 2726 if (!LookPassAnd1 && N10.getOpcode() == ISD::AND) { 2727 if (!N10.getNode()->hasOneUse()) 2728 return SDValue(); 2729 ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N10.getOperand(1)); 2730 if (!N101C || N101C->getZExtValue() != 0xFF00) 2731 return SDValue(); 2732 N10 = N10.getOperand(0); 2733 LookPassAnd1 = true; 2734 } 2735 2736 if (N00 != N10) 2737 return SDValue(); 2738 2739 // Make sure everything beyond the low halfword is zero since the SRL 16 2740 // will clear the top bits. 2741 unsigned OpSizeInBits = VT.getSizeInBits(); 2742 if (DemandHighBits && OpSizeInBits > 16 && 2743 (!LookPassAnd0 || !LookPassAnd1) && 2744 !DAG.MaskedValueIsZero(N10, APInt::getHighBitsSet(OpSizeInBits, 16))) 2745 return SDValue(); 2746 2747 SDValue Res = DAG.getNode(ISD::BSWAP, N->getDebugLoc(), VT, N00); 2748 if (OpSizeInBits > 16) 2749 Res = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, Res, 2750 DAG.getConstant(OpSizeInBits-16, getShiftAmountTy(VT))); 2751 return Res; 2752} 2753 2754/// isBSwapHWordElement - Return true if the specified node is an element 2755/// that makes up a 32-bit packed halfword byteswap. i.e. 2756/// ((x&0xff)<<8)|((x&0xff00)>>8)|((x&0x00ff0000)<<8)|((x&0xff000000)>>8) 2757static bool isBSwapHWordElement(SDValue N, SmallVector<SDNode*,4> &Parts) { 2758 if (!N.getNode()->hasOneUse()) 2759 return false; 2760 2761 unsigned Opc = N.getOpcode(); 2762 if (Opc != ISD::AND && Opc != ISD::SHL && Opc != ISD::SRL) 2763 return false; 2764 2765 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N.getOperand(1)); 2766 if (!N1C) 2767 return false; 2768 2769 unsigned Num; 2770 switch (N1C->getZExtValue()) { 2771 default: 2772 return false; 2773 case 0xFF: Num = 0; break; 2774 case 0xFF00: Num = 1; break; 2775 case 0xFF0000: Num = 2; break; 2776 case 0xFF000000: Num = 3; break; 2777 } 2778 2779 // Look for (x & 0xff) << 8 as well as ((x << 8) & 0xff00). 2780 SDValue N0 = N.getOperand(0); 2781 if (Opc == ISD::AND) { 2782 if (Num == 0 || Num == 2) { 2783 // (x >> 8) & 0xff 2784 // (x >> 8) & 0xff0000 2785 if (N0.getOpcode() != ISD::SRL) 2786 return false; 2787 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2788 if (!C || C->getZExtValue() != 8) 2789 return false; 2790 } else { 2791 // (x << 8) & 0xff00 2792 // (x << 8) & 0xff000000 2793 if (N0.getOpcode() != ISD::SHL) 2794 return false; 2795 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2796 if (!C || C->getZExtValue() != 8) 2797 return false; 2798 } 2799 } else if (Opc == ISD::SHL) { 2800 // (x & 0xff) << 8 2801 // (x & 0xff0000) << 8 2802 if (Num != 0 && Num != 2) 2803 return false; 2804 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N.getOperand(1)); 2805 if (!C || C->getZExtValue() != 8) 2806 return false; 2807 } else { // Opc == ISD::SRL 2808 // (x & 0xff00) >> 8 2809 // (x & 0xff000000) >> 8 2810 if (Num != 1 && Num != 3) 2811 return false; 2812 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N.getOperand(1)); 2813 if (!C || C->getZExtValue() != 8) 2814 return false; 2815 } 2816 2817 if (Parts[Num]) 2818 return false; 2819 2820 Parts[Num] = N0.getOperand(0).getNode(); 2821 return true; 2822} 2823 2824/// MatchBSwapHWord - Match a 32-bit packed halfword bswap. That is 2825/// ((x&0xff)<<8)|((x&0xff00)>>8)|((x&0x00ff0000)<<8)|((x&0xff000000)>>8) 2826/// => (rotl (bswap x), 16) 2827SDValue DAGCombiner::MatchBSwapHWord(SDNode *N, SDValue N0, SDValue N1) { 2828 if (!LegalOperations) 2829 return SDValue(); 2830 2831 EVT VT = N->getValueType(0); 2832 if (VT != MVT::i32) 2833 return SDValue(); 2834 if (!TLI.isOperationLegal(ISD::BSWAP, VT)) 2835 return SDValue(); 2836 2837 SmallVector<SDNode*,4> Parts(4, (SDNode*)0); 2838 // Look for either 2839 // (or (or (and), (and)), (or (and), (and))) 2840 // (or (or (or (and), (and)), (and)), (and)) 2841 if (N0.getOpcode() != ISD::OR) 2842 return SDValue(); 2843 SDValue N00 = N0.getOperand(0); 2844 SDValue N01 = N0.getOperand(1); 2845 2846 if (N1.getOpcode() == ISD::OR) { 2847 // (or (or (and), (and)), (or (and), (and))) 2848 SDValue N000 = N00.getOperand(0); 2849 if (!isBSwapHWordElement(N000, Parts)) 2850 return SDValue(); 2851 2852 SDValue N001 = N00.getOperand(1); 2853 if (!isBSwapHWordElement(N001, Parts)) 2854 return SDValue(); 2855 SDValue N010 = N01.getOperand(0); 2856 if (!isBSwapHWordElement(N010, Parts)) 2857 return SDValue(); 2858 SDValue N011 = N01.getOperand(1); 2859 if (!isBSwapHWordElement(N011, Parts)) 2860 return SDValue(); 2861 } else { 2862 // (or (or (or (and), (and)), (and)), (and)) 2863 if (!isBSwapHWordElement(N1, Parts)) 2864 return SDValue(); 2865 if (!isBSwapHWordElement(N01, Parts)) 2866 return SDValue(); 2867 if (N00.getOpcode() != ISD::OR) 2868 return SDValue(); 2869 SDValue N000 = N00.getOperand(0); 2870 if (!isBSwapHWordElement(N000, Parts)) 2871 return SDValue(); 2872 SDValue N001 = N00.getOperand(1); 2873 if (!isBSwapHWordElement(N001, Parts)) 2874 return SDValue(); 2875 } 2876 2877 // Make sure the parts are all coming from the same node. 2878 if (Parts[0] != Parts[1] || Parts[0] != Parts[2] || Parts[0] != Parts[3]) 2879 return SDValue(); 2880 2881 SDValue BSwap = DAG.getNode(ISD::BSWAP, N->getDebugLoc(), VT, 2882 SDValue(Parts[0],0)); 2883 2884 // Result of the bswap should be rotated by 16. If it's not legal, than 2885 // do (x << 16) | (x >> 16). 2886 SDValue ShAmt = DAG.getConstant(16, getShiftAmountTy(VT)); 2887 if (TLI.isOperationLegalOrCustom(ISD::ROTL, VT)) 2888 return DAG.getNode(ISD::ROTL, N->getDebugLoc(), VT, BSwap, ShAmt); 2889 else if (TLI.isOperationLegalOrCustom(ISD::ROTR, VT)) 2890 return DAG.getNode(ISD::ROTR, N->getDebugLoc(), VT, BSwap, ShAmt); 2891 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, 2892 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, BSwap, ShAmt), 2893 DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, BSwap, ShAmt)); 2894} 2895 2896SDValue DAGCombiner::visitOR(SDNode *N) { 2897 SDValue N0 = N->getOperand(0); 2898 SDValue N1 = N->getOperand(1); 2899 SDValue LL, LR, RL, RR, CC0, CC1; 2900 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2901 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2902 EVT VT = N1.getValueType(); 2903 2904 // fold vector ops 2905 if (VT.isVector()) { 2906 SDValue FoldedVOp = SimplifyVBinOp(N); 2907 if (FoldedVOp.getNode()) return FoldedVOp; 2908 } 2909 2910 // fold (or x, undef) -> -1 2911 if (!LegalOperations && 2912 (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)) { 2913 EVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT; 2914 return DAG.getConstant(APInt::getAllOnesValue(EltVT.getSizeInBits()), VT); 2915 } 2916 // fold (or c1, c2) -> c1|c2 2917 if (N0C && N1C) 2918 return DAG.FoldConstantArithmetic(ISD::OR, VT, N0C, N1C); 2919 // canonicalize constant to RHS 2920 if (N0C && !N1C) 2921 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N1, N0); 2922 // fold (or x, 0) -> x 2923 if (N1C && N1C->isNullValue()) 2924 return N0; 2925 // fold (or x, -1) -> -1 2926 if (N1C && N1C->isAllOnesValue()) 2927 return N1; 2928 // fold (or x, c) -> c iff (x & ~c) == 0 2929 if (N1C && DAG.MaskedValueIsZero(N0, ~N1C->getAPIntValue())) 2930 return N1; 2931 2932 // Recognize halfword bswaps as (bswap + rotl 16) or (bswap + shl 16) 2933 SDValue BSwap = MatchBSwapHWord(N, N0, N1); 2934 if (BSwap.getNode() != 0) 2935 return BSwap; 2936 BSwap = MatchBSwapHWordLow(N, N0, N1); 2937 if (BSwap.getNode() != 0) 2938 return BSwap; 2939 2940 // reassociate or 2941 SDValue ROR = ReassociateOps(ISD::OR, N->getDebugLoc(), N0, N1); 2942 if (ROR.getNode() != 0) 2943 return ROR; 2944 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2) 2945 // iff (c1 & c2) == 0. 2946 if (N1C && N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() && 2947 isa<ConstantSDNode>(N0.getOperand(1))) { 2948 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1)); 2949 if ((C1->getAPIntValue() & N1C->getAPIntValue()) != 0) 2950 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 2951 DAG.getNode(ISD::OR, N0.getDebugLoc(), VT, 2952 N0.getOperand(0), N1), 2953 DAG.FoldConstantArithmetic(ISD::OR, VT, N1C, C1)); 2954 } 2955 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y)) 2956 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 2957 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 2958 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 2959 2960 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 2961 LL.getValueType().isInteger()) { 2962 // fold (or (setne X, 0), (setne Y, 0)) -> (setne (or X, Y), 0) 2963 // fold (or (setlt X, 0), (setlt Y, 0)) -> (setne (or X, Y), 0) 2964 if (cast<ConstantSDNode>(LR)->isNullValue() && 2965 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) { 2966 SDValue ORNode = DAG.getNode(ISD::OR, LR.getDebugLoc(), 2967 LR.getValueType(), LL, RL); 2968 AddToWorkList(ORNode.getNode()); 2969 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 2970 } 2971 // fold (or (setne X, -1), (setne Y, -1)) -> (setne (and X, Y), -1) 2972 // fold (or (setgt X, -1), (setgt Y -1)) -> (setgt (and X, Y), -1) 2973 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && 2974 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) { 2975 SDValue ANDNode = DAG.getNode(ISD::AND, LR.getDebugLoc(), 2976 LR.getValueType(), LL, RL); 2977 AddToWorkList(ANDNode.getNode()); 2978 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1); 2979 } 2980 } 2981 // canonicalize equivalent to ll == rl 2982 if (LL == RR && LR == RL) { 2983 Op1 = ISD::getSetCCSwappedOperands(Op1); 2984 std::swap(RL, RR); 2985 } 2986 if (LL == RL && LR == RR) { 2987 bool isInteger = LL.getValueType().isInteger(); 2988 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger); 2989 if (Result != ISD::SETCC_INVALID && 2990 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType()))) 2991 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(), 2992 LL, LR, Result); 2993 } 2994 } 2995 2996 // Simplify: (or (op x...), (op y...)) -> (op (or x, y)) 2997 if (N0.getOpcode() == N1.getOpcode()) { 2998 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 2999 if (Tmp.getNode()) return Tmp; 3000 } 3001 3002 // (or (and X, C1), (and Y, C2)) -> (and (or X, Y), C3) if possible. 3003 if (N0.getOpcode() == ISD::AND && 3004 N1.getOpcode() == ISD::AND && 3005 N0.getOperand(1).getOpcode() == ISD::Constant && 3006 N1.getOperand(1).getOpcode() == ISD::Constant && 3007 // Don't increase # computations. 3008 (N0.getNode()->hasOneUse() || N1.getNode()->hasOneUse())) { 3009 // We can only do this xform if we know that bits from X that are set in C2 3010 // but not in C1 are already zero. Likewise for Y. 3011 const APInt &LHSMask = 3012 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 3013 const APInt &RHSMask = 3014 cast<ConstantSDNode>(N1.getOperand(1))->getAPIntValue(); 3015 3016 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) && 3017 DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) { 3018 SDValue X = DAG.getNode(ISD::OR, N0.getDebugLoc(), VT, 3019 N0.getOperand(0), N1.getOperand(0)); 3020 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, X, 3021 DAG.getConstant(LHSMask | RHSMask, VT)); 3022 } 3023 } 3024 3025 // See if this is some rotate idiom. 3026 if (SDNode *Rot = MatchRotate(N0, N1, N->getDebugLoc())) 3027 return SDValue(Rot, 0); 3028 3029 // Simplify the operands using demanded-bits information. 3030 if (!VT.isVector() && 3031 SimplifyDemandedBits(SDValue(N, 0))) 3032 return SDValue(N, 0); 3033 3034 return SDValue(); 3035} 3036 3037/// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present. 3038static bool MatchRotateHalf(SDValue Op, SDValue &Shift, SDValue &Mask) { 3039 if (Op.getOpcode() == ISD::AND) { 3040 if (isa<ConstantSDNode>(Op.getOperand(1))) { 3041 Mask = Op.getOperand(1); 3042 Op = Op.getOperand(0); 3043 } else { 3044 return false; 3045 } 3046 } 3047 3048 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) { 3049 Shift = Op; 3050 return true; 3051 } 3052 3053 return false; 3054} 3055 3056// MatchRotate - Handle an 'or' of two operands. If this is one of the many 3057// idioms for rotate, and if the target supports rotation instructions, generate 3058// a rot[lr]. 3059SDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL) { 3060 // Must be a legal type. Expanded 'n promoted things won't work with rotates. 3061 EVT VT = LHS.getValueType(); 3062 if (!TLI.isTypeLegal(VT)) return 0; 3063 3064 // The target must have at least one rotate flavor. 3065 bool HasROTL = TLI.isOperationLegalOrCustom(ISD::ROTL, VT); 3066 bool HasROTR = TLI.isOperationLegalOrCustom(ISD::ROTR, VT); 3067 if (!HasROTL && !HasROTR) return 0; 3068 3069 // Match "(X shl/srl V1) & V2" where V2 may not be present. 3070 SDValue LHSShift; // The shift. 3071 SDValue LHSMask; // AND value if any. 3072 if (!MatchRotateHalf(LHS, LHSShift, LHSMask)) 3073 return 0; // Not part of a rotate. 3074 3075 SDValue RHSShift; // The shift. 3076 SDValue RHSMask; // AND value if any. 3077 if (!MatchRotateHalf(RHS, RHSShift, RHSMask)) 3078 return 0; // Not part of a rotate. 3079 3080 if (LHSShift.getOperand(0) != RHSShift.getOperand(0)) 3081 return 0; // Not shifting the same value. 3082 3083 if (LHSShift.getOpcode() == RHSShift.getOpcode()) 3084 return 0; // Shifts must disagree. 3085 3086 // Canonicalize shl to left side in a shl/srl pair. 3087 if (RHSShift.getOpcode() == ISD::SHL) { 3088 std::swap(LHS, RHS); 3089 std::swap(LHSShift, RHSShift); 3090 std::swap(LHSMask , RHSMask ); 3091 } 3092 3093 unsigned OpSizeInBits = VT.getSizeInBits(); 3094 SDValue LHSShiftArg = LHSShift.getOperand(0); 3095 SDValue LHSShiftAmt = LHSShift.getOperand(1); 3096 SDValue RHSShiftAmt = RHSShift.getOperand(1); 3097 3098 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1) 3099 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2) 3100 if (LHSShiftAmt.getOpcode() == ISD::Constant && 3101 RHSShiftAmt.getOpcode() == ISD::Constant) { 3102 uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getZExtValue(); 3103 uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getZExtValue(); 3104 if ((LShVal + RShVal) != OpSizeInBits) 3105 return 0; 3106 3107 SDValue Rot; 3108 if (HasROTL) 3109 Rot = DAG.getNode(ISD::ROTL, DL, VT, LHSShiftArg, LHSShiftAmt); 3110 else 3111 Rot = DAG.getNode(ISD::ROTR, DL, VT, LHSShiftArg, RHSShiftAmt); 3112 3113 // If there is an AND of either shifted operand, apply it to the result. 3114 if (LHSMask.getNode() || RHSMask.getNode()) { 3115 APInt Mask = APInt::getAllOnesValue(OpSizeInBits); 3116 3117 if (LHSMask.getNode()) { 3118 APInt RHSBits = APInt::getLowBitsSet(OpSizeInBits, LShVal); 3119 Mask &= cast<ConstantSDNode>(LHSMask)->getAPIntValue() | RHSBits; 3120 } 3121 if (RHSMask.getNode()) { 3122 APInt LHSBits = APInt::getHighBitsSet(OpSizeInBits, RShVal); 3123 Mask &= cast<ConstantSDNode>(RHSMask)->getAPIntValue() | LHSBits; 3124 } 3125 3126 Rot = DAG.getNode(ISD::AND, DL, VT, Rot, DAG.getConstant(Mask, VT)); 3127 } 3128 3129 return Rot.getNode(); 3130 } 3131 3132 // If there is a mask here, and we have a variable shift, we can't be sure 3133 // that we're masking out the right stuff. 3134 if (LHSMask.getNode() || RHSMask.getNode()) 3135 return 0; 3136 3137 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y) 3138 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y)) 3139 if (RHSShiftAmt.getOpcode() == ISD::SUB && 3140 LHSShiftAmt == RHSShiftAmt.getOperand(1)) { 3141 if (ConstantSDNode *SUBC = 3142 dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) { 3143 if (SUBC->getAPIntValue() == OpSizeInBits) { 3144 if (HasROTL) 3145 return DAG.getNode(ISD::ROTL, DL, VT, 3146 LHSShiftArg, LHSShiftAmt).getNode(); 3147 else 3148 return DAG.getNode(ISD::ROTR, DL, VT, 3149 LHSShiftArg, RHSShiftAmt).getNode(); 3150 } 3151 } 3152 } 3153 3154 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y) 3155 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y)) 3156 if (LHSShiftAmt.getOpcode() == ISD::SUB && 3157 RHSShiftAmt == LHSShiftAmt.getOperand(1)) { 3158 if (ConstantSDNode *SUBC = 3159 dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) { 3160 if (SUBC->getAPIntValue() == OpSizeInBits) { 3161 if (HasROTR) 3162 return DAG.getNode(ISD::ROTR, DL, VT, 3163 LHSShiftArg, RHSShiftAmt).getNode(); 3164 else 3165 return DAG.getNode(ISD::ROTL, DL, VT, 3166 LHSShiftArg, LHSShiftAmt).getNode(); 3167 } 3168 } 3169 } 3170 3171 // Look for sign/zext/any-extended or truncate cases: 3172 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 3173 || LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 3174 || LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND 3175 || LHSShiftAmt.getOpcode() == ISD::TRUNCATE) && 3176 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 3177 || RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 3178 || RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND 3179 || RHSShiftAmt.getOpcode() == ISD::TRUNCATE)) { 3180 SDValue LExtOp0 = LHSShiftAmt.getOperand(0); 3181 SDValue RExtOp0 = RHSShiftAmt.getOperand(0); 3182 if (RExtOp0.getOpcode() == ISD::SUB && 3183 RExtOp0.getOperand(1) == LExtOp0) { 3184 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 3185 // (rotl x, y) 3186 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 3187 // (rotr x, (sub 32, y)) 3188 if (ConstantSDNode *SUBC = 3189 dyn_cast<ConstantSDNode>(RExtOp0.getOperand(0))) { 3190 if (SUBC->getAPIntValue() == OpSizeInBits) { 3191 return DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT, 3192 LHSShiftArg, 3193 HasROTL ? LHSShiftAmt : RHSShiftAmt).getNode(); 3194 } 3195 } 3196 } else if (LExtOp0.getOpcode() == ISD::SUB && 3197 RExtOp0 == LExtOp0.getOperand(1)) { 3198 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) -> 3199 // (rotr x, y) 3200 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) -> 3201 // (rotl x, (sub 32, y)) 3202 if (ConstantSDNode *SUBC = 3203 dyn_cast<ConstantSDNode>(LExtOp0.getOperand(0))) { 3204 if (SUBC->getAPIntValue() == OpSizeInBits) { 3205 return DAG.getNode(HasROTR ? ISD::ROTR : ISD::ROTL, DL, VT, 3206 LHSShiftArg, 3207 HasROTR ? RHSShiftAmt : LHSShiftAmt).getNode(); 3208 } 3209 } 3210 } 3211 } 3212 3213 return 0; 3214} 3215 3216SDValue DAGCombiner::visitXOR(SDNode *N) { 3217 SDValue N0 = N->getOperand(0); 3218 SDValue N1 = N->getOperand(1); 3219 SDValue LHS, RHS, CC; 3220 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3221 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3222 EVT VT = N0.getValueType(); 3223 3224 // fold vector ops 3225 if (VT.isVector()) { 3226 SDValue FoldedVOp = SimplifyVBinOp(N); 3227 if (FoldedVOp.getNode()) return FoldedVOp; 3228 } 3229 3230 // fold (xor undef, undef) -> 0. This is a common idiom (misuse). 3231 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF) 3232 return DAG.getConstant(0, VT); 3233 // fold (xor x, undef) -> undef 3234 if (N0.getOpcode() == ISD::UNDEF) 3235 return N0; 3236 if (N1.getOpcode() == ISD::UNDEF) 3237 return N1; 3238 // fold (xor c1, c2) -> c1^c2 3239 if (N0C && N1C) 3240 return DAG.FoldConstantArithmetic(ISD::XOR, VT, N0C, N1C); 3241 // canonicalize constant to RHS 3242 if (N0C && !N1C) 3243 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0); 3244 // fold (xor x, 0) -> x 3245 if (N1C && N1C->isNullValue()) 3246 return N0; 3247 // reassociate xor 3248 SDValue RXOR = ReassociateOps(ISD::XOR, N->getDebugLoc(), N0, N1); 3249 if (RXOR.getNode() != 0) 3250 return RXOR; 3251 3252 // fold !(x cc y) -> (x !cc y) 3253 if (N1C && N1C->getAPIntValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) { 3254 bool isInt = LHS.getValueType().isInteger(); 3255 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(), 3256 isInt); 3257 3258 if (!LegalOperations || TLI.isCondCodeLegal(NotCC, LHS.getValueType())) { 3259 switch (N0.getOpcode()) { 3260 default: 3261 llvm_unreachable("Unhandled SetCC Equivalent!"); 3262 case ISD::SETCC: 3263 return DAG.getSetCC(N->getDebugLoc(), VT, LHS, RHS, NotCC); 3264 case ISD::SELECT_CC: 3265 return DAG.getSelectCC(N->getDebugLoc(), LHS, RHS, N0.getOperand(2), 3266 N0.getOperand(3), NotCC); 3267 } 3268 } 3269 } 3270 3271 // fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y))) 3272 if (N1C && N1C->getAPIntValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND && 3273 N0.getNode()->hasOneUse() && 3274 isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){ 3275 SDValue V = N0.getOperand(0); 3276 V = DAG.getNode(ISD::XOR, N0.getDebugLoc(), V.getValueType(), V, 3277 DAG.getConstant(1, V.getValueType())); 3278 AddToWorkList(V.getNode()); 3279 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, V); 3280 } 3281 3282 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are setcc 3283 if (N1C && N1C->getAPIntValue() == 1 && VT == MVT::i1 && 3284 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 3285 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1); 3286 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) { 3287 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 3288 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS 3289 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS 3290 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode()); 3291 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS); 3292 } 3293 } 3294 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are constants 3295 if (N1C && N1C->isAllOnesValue() && 3296 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 3297 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1); 3298 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) { 3299 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 3300 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS 3301 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS 3302 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode()); 3303 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS); 3304 } 3305 } 3306 // fold (xor (xor x, c1), c2) -> (xor x, (xor c1, c2)) 3307 if (N1C && N0.getOpcode() == ISD::XOR) { 3308 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0)); 3309 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 3310 if (N00C) 3311 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(1), 3312 DAG.getConstant(N1C->getAPIntValue() ^ 3313 N00C->getAPIntValue(), VT)); 3314 if (N01C) 3315 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(0), 3316 DAG.getConstant(N1C->getAPIntValue() ^ 3317 N01C->getAPIntValue(), VT)); 3318 } 3319 // fold (xor x, x) -> 0 3320 if (N0 == N1) 3321 return tryFoldToZero(N->getDebugLoc(), TLI, VT, DAG, LegalOperations); 3322 3323 // Simplify: xor (op x...), (op y...) -> (op (xor x, y)) 3324 if (N0.getOpcode() == N1.getOpcode()) { 3325 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 3326 if (Tmp.getNode()) return Tmp; 3327 } 3328 3329 // Simplify the expression using non-local knowledge. 3330 if (!VT.isVector() && 3331 SimplifyDemandedBits(SDValue(N, 0))) 3332 return SDValue(N, 0); 3333 3334 return SDValue(); 3335} 3336 3337/// visitShiftByConstant - Handle transforms common to the three shifts, when 3338/// the shift amount is a constant. 3339SDValue DAGCombiner::visitShiftByConstant(SDNode *N, unsigned Amt) { 3340 SDNode *LHS = N->getOperand(0).getNode(); 3341 if (!LHS->hasOneUse()) return SDValue(); 3342 3343 // We want to pull some binops through shifts, so that we have (and (shift)) 3344 // instead of (shift (and)), likewise for add, or, xor, etc. This sort of 3345 // thing happens with address calculations, so it's important to canonicalize 3346 // it. 3347 bool HighBitSet = false; // Can we transform this if the high bit is set? 3348 3349 switch (LHS->getOpcode()) { 3350 default: return SDValue(); 3351 case ISD::OR: 3352 case ISD::XOR: 3353 HighBitSet = false; // We can only transform sra if the high bit is clear. 3354 break; 3355 case ISD::AND: 3356 HighBitSet = true; // We can only transform sra if the high bit is set. 3357 break; 3358 case ISD::ADD: 3359 if (N->getOpcode() != ISD::SHL) 3360 return SDValue(); // only shl(add) not sr[al](add). 3361 HighBitSet = false; // We can only transform sra if the high bit is clear. 3362 break; 3363 } 3364 3365 // We require the RHS of the binop to be a constant as well. 3366 ConstantSDNode *BinOpCst = dyn_cast<ConstantSDNode>(LHS->getOperand(1)); 3367 if (!BinOpCst) return SDValue(); 3368 3369 // FIXME: disable this unless the input to the binop is a shift by a constant. 3370 // If it is not a shift, it pessimizes some common cases like: 3371 // 3372 // void foo(int *X, int i) { X[i & 1235] = 1; } 3373 // int bar(int *X, int i) { return X[i & 255]; } 3374 SDNode *BinOpLHSVal = LHS->getOperand(0).getNode(); 3375 if ((BinOpLHSVal->getOpcode() != ISD::SHL && 3376 BinOpLHSVal->getOpcode() != ISD::SRA && 3377 BinOpLHSVal->getOpcode() != ISD::SRL) || 3378 !isa<ConstantSDNode>(BinOpLHSVal->getOperand(1))) 3379 return SDValue(); 3380 3381 EVT VT = N->getValueType(0); 3382 3383 // If this is a signed shift right, and the high bit is modified by the 3384 // logical operation, do not perform the transformation. The highBitSet 3385 // boolean indicates the value of the high bit of the constant which would 3386 // cause it to be modified for this operation. 3387 if (N->getOpcode() == ISD::SRA) { 3388 bool BinOpRHSSignSet = BinOpCst->getAPIntValue().isNegative(); 3389 if (BinOpRHSSignSet != HighBitSet) 3390 return SDValue(); 3391 } 3392 3393 // Fold the constants, shifting the binop RHS by the shift amount. 3394 SDValue NewRHS = DAG.getNode(N->getOpcode(), LHS->getOperand(1).getDebugLoc(), 3395 N->getValueType(0), 3396 LHS->getOperand(1), N->getOperand(1)); 3397 3398 // Create the new shift. 3399 SDValue NewShift = DAG.getNode(N->getOpcode(), 3400 LHS->getOperand(0).getDebugLoc(), 3401 VT, LHS->getOperand(0), N->getOperand(1)); 3402 3403 // Create the new binop. 3404 return DAG.getNode(LHS->getOpcode(), N->getDebugLoc(), VT, NewShift, NewRHS); 3405} 3406 3407SDValue DAGCombiner::visitSHL(SDNode *N) { 3408 SDValue N0 = N->getOperand(0); 3409 SDValue N1 = N->getOperand(1); 3410 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3411 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3412 EVT VT = N0.getValueType(); 3413 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits(); 3414 3415 // fold (shl c1, c2) -> c1<<c2 3416 if (N0C && N1C) 3417 return DAG.FoldConstantArithmetic(ISD::SHL, VT, N0C, N1C); 3418 // fold (shl 0, x) -> 0 3419 if (N0C && N0C->isNullValue()) 3420 return N0; 3421 // fold (shl x, c >= size(x)) -> undef 3422 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 3423 return DAG.getUNDEF(VT); 3424 // fold (shl x, 0) -> x 3425 if (N1C && N1C->isNullValue()) 3426 return N0; 3427 // fold (shl undef, x) -> 0 3428 if (N0.getOpcode() == ISD::UNDEF) 3429 return DAG.getConstant(0, VT); 3430 // if (shl x, c) is known to be zero, return 0 3431 if (DAG.MaskedValueIsZero(SDValue(N, 0), 3432 APInt::getAllOnesValue(OpSizeInBits))) 3433 return DAG.getConstant(0, VT); 3434 // fold (shl x, (trunc (and y, c))) -> (shl x, (and (trunc y), (trunc c))). 3435 if (N1.getOpcode() == ISD::TRUNCATE && 3436 N1.getOperand(0).getOpcode() == ISD::AND && 3437 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 3438 SDValue N101 = N1.getOperand(0).getOperand(1); 3439 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 3440 EVT TruncVT = N1.getValueType(); 3441 SDValue N100 = N1.getOperand(0).getOperand(0); 3442 APInt TruncC = N101C->getAPIntValue(); 3443 TruncC = TruncC.trunc(TruncVT.getSizeInBits()); 3444 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 3445 DAG.getNode(ISD::AND, N->getDebugLoc(), TruncVT, 3446 DAG.getNode(ISD::TRUNCATE, 3447 N->getDebugLoc(), 3448 TruncVT, N100), 3449 DAG.getConstant(TruncC, TruncVT))); 3450 } 3451 } 3452 3453 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 3454 return SDValue(N, 0); 3455 3456 // fold (shl (shl x, c1), c2) -> 0 or (shl x, (add c1, c2)) 3457 if (N1C && N0.getOpcode() == ISD::SHL && 3458 N0.getOperand(1).getOpcode() == ISD::Constant) { 3459 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 3460 uint64_t c2 = N1C->getZExtValue(); 3461 if (c1 + c2 >= OpSizeInBits) 3462 return DAG.getConstant(0, VT); 3463 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0.getOperand(0), 3464 DAG.getConstant(c1 + c2, N1.getValueType())); 3465 } 3466 3467 // fold (shl (ext (shl x, c1)), c2) -> (ext (shl x, (add c1, c2))) 3468 // For this to be valid, the second form must not preserve any of the bits 3469 // that are shifted out by the inner shift in the first form. This means 3470 // the outer shift size must be >= the number of bits added by the ext. 3471 // As a corollary, we don't care what kind of ext it is. 3472 if (N1C && (N0.getOpcode() == ISD::ZERO_EXTEND || 3473 N0.getOpcode() == ISD::ANY_EXTEND || 3474 N0.getOpcode() == ISD::SIGN_EXTEND) && 3475 N0.getOperand(0).getOpcode() == ISD::SHL && 3476 isa<ConstantSDNode>(N0.getOperand(0)->getOperand(1))) { 3477 uint64_t c1 = 3478 cast<ConstantSDNode>(N0.getOperand(0)->getOperand(1))->getZExtValue(); 3479 uint64_t c2 = N1C->getZExtValue(); 3480 EVT InnerShiftVT = N0.getOperand(0).getValueType(); 3481 uint64_t InnerShiftSize = InnerShiftVT.getScalarType().getSizeInBits(); 3482 if (c2 >= OpSizeInBits - InnerShiftSize) { 3483 if (c1 + c2 >= OpSizeInBits) 3484 return DAG.getConstant(0, VT); 3485 return DAG.getNode(ISD::SHL, N0->getDebugLoc(), VT, 3486 DAG.getNode(N0.getOpcode(), N0->getDebugLoc(), VT, 3487 N0.getOperand(0)->getOperand(0)), 3488 DAG.getConstant(c1 + c2, N1.getValueType())); 3489 } 3490 } 3491 3492 // fold (shl (srl x, c1), c2) -> (and (shl x, (sub c2, c1), MASK) or 3493 // (and (srl x, (sub c1, c2), MASK) 3494 // Only fold this if the inner shift has no other uses -- if it does, folding 3495 // this will increase the total number of instructions. 3496 if (N1C && N0.getOpcode() == ISD::SRL && N0.hasOneUse() && 3497 N0.getOperand(1).getOpcode() == ISD::Constant) { 3498 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 3499 if (c1 < VT.getSizeInBits()) { 3500 uint64_t c2 = N1C->getZExtValue(); 3501 APInt Mask = APInt::getHighBitsSet(VT.getSizeInBits(), 3502 VT.getSizeInBits() - c1); 3503 SDValue Shift; 3504 if (c2 > c1) { 3505 Mask = Mask.shl(c2-c1); 3506 Shift = DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0.getOperand(0), 3507 DAG.getConstant(c2-c1, N1.getValueType())); 3508 } else { 3509 Mask = Mask.lshr(c1-c2); 3510 Shift = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), 3511 DAG.getConstant(c1-c2, N1.getValueType())); 3512 } 3513 return DAG.getNode(ISD::AND, N0.getDebugLoc(), VT, Shift, 3514 DAG.getConstant(Mask, VT)); 3515 } 3516 } 3517 // fold (shl (sra x, c1), c1) -> (and x, (shl -1, c1)) 3518 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) { 3519 SDValue HiBitsMask = 3520 DAG.getConstant(APInt::getHighBitsSet(VT.getSizeInBits(), 3521 VT.getSizeInBits() - 3522 N1C->getZExtValue()), 3523 VT); 3524 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0), 3525 HiBitsMask); 3526 } 3527 3528 if (N1C) { 3529 SDValue NewSHL = visitShiftByConstant(N, N1C->getZExtValue()); 3530 if (NewSHL.getNode()) 3531 return NewSHL; 3532 } 3533 3534 return SDValue(); 3535} 3536 3537SDValue DAGCombiner::visitSRA(SDNode *N) { 3538 SDValue N0 = N->getOperand(0); 3539 SDValue N1 = N->getOperand(1); 3540 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3541 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3542 EVT VT = N0.getValueType(); 3543 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits(); 3544 3545 // fold (sra c1, c2) -> (sra c1, c2) 3546 if (N0C && N1C) 3547 return DAG.FoldConstantArithmetic(ISD::SRA, VT, N0C, N1C); 3548 // fold (sra 0, x) -> 0 3549 if (N0C && N0C->isNullValue()) 3550 return N0; 3551 // fold (sra -1, x) -> -1 3552 if (N0C && N0C->isAllOnesValue()) 3553 return N0; 3554 // fold (sra x, (setge c, size(x))) -> undef 3555 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 3556 return DAG.getUNDEF(VT); 3557 // fold (sra x, 0) -> x 3558 if (N1C && N1C->isNullValue()) 3559 return N0; 3560 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports 3561 // sext_inreg. 3562 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) { 3563 unsigned LowBits = OpSizeInBits - (unsigned)N1C->getZExtValue(); 3564 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), LowBits); 3565 if (VT.isVector()) 3566 ExtVT = EVT::getVectorVT(*DAG.getContext(), 3567 ExtVT, VT.getVectorNumElements()); 3568 if ((!LegalOperations || 3569 TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, ExtVT))) 3570 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, 3571 N0.getOperand(0), DAG.getValueType(ExtVT)); 3572 } 3573 3574 // fold (sra (sra x, c1), c2) -> (sra x, (add c1, c2)) 3575 if (N1C && N0.getOpcode() == ISD::SRA) { 3576 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 3577 unsigned Sum = N1C->getZExtValue() + C1->getZExtValue(); 3578 if (Sum >= OpSizeInBits) Sum = OpSizeInBits-1; 3579 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0.getOperand(0), 3580 DAG.getConstant(Sum, N1C->getValueType(0))); 3581 } 3582 } 3583 3584 // fold (sra (shl X, m), (sub result_size, n)) 3585 // -> (sign_extend (trunc (shl X, (sub (sub result_size, n), m)))) for 3586 // result_size - n != m. 3587 // If truncate is free for the target sext(shl) is likely to result in better 3588 // code. 3589 if (N0.getOpcode() == ISD::SHL) { 3590 // Get the two constanst of the shifts, CN0 = m, CN = n. 3591 const ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 3592 if (N01C && N1C) { 3593 // Determine what the truncate's result bitsize and type would be. 3594 EVT TruncVT = 3595 EVT::getIntegerVT(*DAG.getContext(), 3596 OpSizeInBits - N1C->getZExtValue()); 3597 // Determine the residual right-shift amount. 3598 signed ShiftAmt = N1C->getZExtValue() - N01C->getZExtValue(); 3599 3600 // If the shift is not a no-op (in which case this should be just a sign 3601 // extend already), the truncated to type is legal, sign_extend is legal 3602 // on that type, and the truncate to that type is both legal and free, 3603 // perform the transform. 3604 if ((ShiftAmt > 0) && 3605 TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND, TruncVT) && 3606 TLI.isOperationLegalOrCustom(ISD::TRUNCATE, VT) && 3607 TLI.isTruncateFree(VT, TruncVT)) { 3608 3609 SDValue Amt = DAG.getConstant(ShiftAmt, 3610 getShiftAmountTy(N0.getOperand(0).getValueType())); 3611 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, 3612 N0.getOperand(0), Amt); 3613 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), TruncVT, 3614 Shift); 3615 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), 3616 N->getValueType(0), Trunc); 3617 } 3618 } 3619 } 3620 3621 // fold (sra x, (trunc (and y, c))) -> (sra x, (and (trunc y), (trunc c))). 3622 if (N1.getOpcode() == ISD::TRUNCATE && 3623 N1.getOperand(0).getOpcode() == ISD::AND && 3624 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 3625 SDValue N101 = N1.getOperand(0).getOperand(1); 3626 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 3627 EVT TruncVT = N1.getValueType(); 3628 SDValue N100 = N1.getOperand(0).getOperand(0); 3629 APInt TruncC = N101C->getAPIntValue(); 3630 TruncC = TruncC.trunc(TruncVT.getScalarType().getSizeInBits()); 3631 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0, 3632 DAG.getNode(ISD::AND, N->getDebugLoc(), 3633 TruncVT, 3634 DAG.getNode(ISD::TRUNCATE, 3635 N->getDebugLoc(), 3636 TruncVT, N100), 3637 DAG.getConstant(TruncC, TruncVT))); 3638 } 3639 } 3640 3641 // fold (sra (trunc (sr x, c1)), c2) -> (trunc (sra x, c1+c2)) 3642 // if c1 is equal to the number of bits the trunc removes 3643 if (N0.getOpcode() == ISD::TRUNCATE && 3644 (N0.getOperand(0).getOpcode() == ISD::SRL || 3645 N0.getOperand(0).getOpcode() == ISD::SRA) && 3646 N0.getOperand(0).hasOneUse() && 3647 N0.getOperand(0).getOperand(1).hasOneUse() && 3648 N1C && isa<ConstantSDNode>(N0.getOperand(0).getOperand(1))) { 3649 EVT LargeVT = N0.getOperand(0).getValueType(); 3650 ConstantSDNode *LargeShiftAmt = 3651 cast<ConstantSDNode>(N0.getOperand(0).getOperand(1)); 3652 3653 if (LargeVT.getScalarType().getSizeInBits() - OpSizeInBits == 3654 LargeShiftAmt->getZExtValue()) { 3655 SDValue Amt = 3656 DAG.getConstant(LargeShiftAmt->getZExtValue() + N1C->getZExtValue(), 3657 getShiftAmountTy(N0.getOperand(0).getOperand(0).getValueType())); 3658 SDValue SRA = DAG.getNode(ISD::SRA, N->getDebugLoc(), LargeVT, 3659 N0.getOperand(0).getOperand(0), Amt); 3660 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, SRA); 3661 } 3662 } 3663 3664 // Simplify, based on bits shifted out of the LHS. 3665 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 3666 return SDValue(N, 0); 3667 3668 3669 // If the sign bit is known to be zero, switch this to a SRL. 3670 if (DAG.SignBitIsZero(N0)) 3671 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, N1); 3672 3673 if (N1C) { 3674 SDValue NewSRA = visitShiftByConstant(N, N1C->getZExtValue()); 3675 if (NewSRA.getNode()) 3676 return NewSRA; 3677 } 3678 3679 return SDValue(); 3680} 3681 3682SDValue DAGCombiner::visitSRL(SDNode *N) { 3683 SDValue N0 = N->getOperand(0); 3684 SDValue N1 = N->getOperand(1); 3685 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3686 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3687 EVT VT = N0.getValueType(); 3688 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits(); 3689 3690 // fold (srl c1, c2) -> c1 >>u c2 3691 if (N0C && N1C) 3692 return DAG.FoldConstantArithmetic(ISD::SRL, VT, N0C, N1C); 3693 // fold (srl 0, x) -> 0 3694 if (N0C && N0C->isNullValue()) 3695 return N0; 3696 // fold (srl x, c >= size(x)) -> undef 3697 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 3698 return DAG.getUNDEF(VT); 3699 // fold (srl x, 0) -> x 3700 if (N1C && N1C->isNullValue()) 3701 return N0; 3702 // if (srl x, c) is known to be zero, return 0 3703 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0), 3704 APInt::getAllOnesValue(OpSizeInBits))) 3705 return DAG.getConstant(0, VT); 3706 3707 // fold (srl (srl x, c1), c2) -> 0 or (srl x, (add c1, c2)) 3708 if (N1C && N0.getOpcode() == ISD::SRL && 3709 N0.getOperand(1).getOpcode() == ISD::Constant) { 3710 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 3711 uint64_t c2 = N1C->getZExtValue(); 3712 if (c1 + c2 >= OpSizeInBits) 3713 return DAG.getConstant(0, VT); 3714 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), 3715 DAG.getConstant(c1 + c2, N1.getValueType())); 3716 } 3717 3718 // fold (srl (trunc (srl x, c1)), c2) -> 0 or (trunc (srl x, (add c1, c2))) 3719 if (N1C && N0.getOpcode() == ISD::TRUNCATE && 3720 N0.getOperand(0).getOpcode() == ISD::SRL && 3721 isa<ConstantSDNode>(N0.getOperand(0)->getOperand(1))) { 3722 uint64_t c1 = 3723 cast<ConstantSDNode>(N0.getOperand(0)->getOperand(1))->getZExtValue(); 3724 uint64_t c2 = N1C->getZExtValue(); 3725 EVT InnerShiftVT = N0.getOperand(0).getValueType(); 3726 EVT ShiftCountVT = N0.getOperand(0)->getOperand(1).getValueType(); 3727 uint64_t InnerShiftSize = InnerShiftVT.getScalarType().getSizeInBits(); 3728 // This is only valid if the OpSizeInBits + c1 = size of inner shift. 3729 if (c1 + OpSizeInBits == InnerShiftSize) { 3730 if (c1 + c2 >= InnerShiftSize) 3731 return DAG.getConstant(0, VT); 3732 return DAG.getNode(ISD::TRUNCATE, N0->getDebugLoc(), VT, 3733 DAG.getNode(ISD::SRL, N0->getDebugLoc(), InnerShiftVT, 3734 N0.getOperand(0)->getOperand(0), 3735 DAG.getConstant(c1 + c2, ShiftCountVT))); 3736 } 3737 } 3738 3739 // fold (srl (shl x, c), c) -> (and x, cst2) 3740 if (N1C && N0.getOpcode() == ISD::SHL && N0.getOperand(1) == N1 && 3741 N0.getValueSizeInBits() <= 64) { 3742 uint64_t ShAmt = N1C->getZExtValue()+64-N0.getValueSizeInBits(); 3743 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0), 3744 DAG.getConstant(~0ULL >> ShAmt, VT)); 3745 } 3746 3747 3748 // fold (srl (anyextend x), c) -> (anyextend (srl x, c)) 3749 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 3750 // Shifting in all undef bits? 3751 EVT SmallVT = N0.getOperand(0).getValueType(); 3752 if (N1C->getZExtValue() >= SmallVT.getSizeInBits()) 3753 return DAG.getUNDEF(VT); 3754 3755 if (!LegalTypes || TLI.isTypeDesirableForOp(ISD::SRL, SmallVT)) { 3756 uint64_t ShiftAmt = N1C->getZExtValue(); 3757 SDValue SmallShift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), SmallVT, 3758 N0.getOperand(0), 3759 DAG.getConstant(ShiftAmt, getShiftAmountTy(SmallVT))); 3760 AddToWorkList(SmallShift.getNode()); 3761 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, SmallShift); 3762 } 3763 } 3764 3765 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign 3766 // bit, which is unmodified by sra. 3767 if (N1C && N1C->getZExtValue() + 1 == VT.getSizeInBits()) { 3768 if (N0.getOpcode() == ISD::SRA) 3769 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), N1); 3770 } 3771 3772 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit). 3773 if (N1C && N0.getOpcode() == ISD::CTLZ && 3774 N1C->getAPIntValue() == Log2_32(VT.getSizeInBits())) { 3775 APInt KnownZero, KnownOne; 3776 APInt Mask = APInt::getAllOnesValue(VT.getScalarType().getSizeInBits()); 3777 DAG.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne); 3778 3779 // If any of the input bits are KnownOne, then the input couldn't be all 3780 // zeros, thus the result of the srl will always be zero. 3781 if (KnownOne.getBoolValue()) return DAG.getConstant(0, VT); 3782 3783 // If all of the bits input the to ctlz node are known to be zero, then 3784 // the result of the ctlz is "32" and the result of the shift is one. 3785 APInt UnknownBits = ~KnownZero & Mask; 3786 if (UnknownBits == 0) return DAG.getConstant(1, VT); 3787 3788 // Otherwise, check to see if there is exactly one bit input to the ctlz. 3789 if ((UnknownBits & (UnknownBits - 1)) == 0) { 3790 // Okay, we know that only that the single bit specified by UnknownBits 3791 // could be set on input to the CTLZ node. If this bit is set, the SRL 3792 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair 3793 // to an SRL/XOR pair, which is likely to simplify more. 3794 unsigned ShAmt = UnknownBits.countTrailingZeros(); 3795 SDValue Op = N0.getOperand(0); 3796 3797 if (ShAmt) { 3798 Op = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, Op, 3799 DAG.getConstant(ShAmt, getShiftAmountTy(Op.getValueType()))); 3800 AddToWorkList(Op.getNode()); 3801 } 3802 3803 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, 3804 Op, DAG.getConstant(1, VT)); 3805 } 3806 } 3807 3808 // fold (srl x, (trunc (and y, c))) -> (srl x, (and (trunc y), (trunc c))). 3809 if (N1.getOpcode() == ISD::TRUNCATE && 3810 N1.getOperand(0).getOpcode() == ISD::AND && 3811 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 3812 SDValue N101 = N1.getOperand(0).getOperand(1); 3813 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 3814 EVT TruncVT = N1.getValueType(); 3815 SDValue N100 = N1.getOperand(0).getOperand(0); 3816 APInt TruncC = N101C->getAPIntValue(); 3817 TruncC = TruncC.trunc(TruncVT.getSizeInBits()); 3818 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, 3819 DAG.getNode(ISD::AND, N->getDebugLoc(), 3820 TruncVT, 3821 DAG.getNode(ISD::TRUNCATE, 3822 N->getDebugLoc(), 3823 TruncVT, N100), 3824 DAG.getConstant(TruncC, TruncVT))); 3825 } 3826 } 3827 3828 // fold operands of srl based on knowledge that the low bits are not 3829 // demanded. 3830 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 3831 return SDValue(N, 0); 3832 3833 if (N1C) { 3834 SDValue NewSRL = visitShiftByConstant(N, N1C->getZExtValue()); 3835 if (NewSRL.getNode()) 3836 return NewSRL; 3837 } 3838 3839 // Attempt to convert a srl of a load into a narrower zero-extending load. 3840 SDValue NarrowLoad = ReduceLoadWidth(N); 3841 if (NarrowLoad.getNode()) 3842 return NarrowLoad; 3843 3844 // Here is a common situation. We want to optimize: 3845 // 3846 // %a = ... 3847 // %b = and i32 %a, 2 3848 // %c = srl i32 %b, 1 3849 // brcond i32 %c ... 3850 // 3851 // into 3852 // 3853 // %a = ... 3854 // %b = and %a, 2 3855 // %c = setcc eq %b, 0 3856 // brcond %c ... 3857 // 3858 // However when after the source operand of SRL is optimized into AND, the SRL 3859 // itself may not be optimized further. Look for it and add the BRCOND into 3860 // the worklist. 3861 if (N->hasOneUse()) { 3862 SDNode *Use = *N->use_begin(); 3863 if (Use->getOpcode() == ISD::BRCOND) 3864 AddToWorkList(Use); 3865 else if (Use->getOpcode() == ISD::TRUNCATE && Use->hasOneUse()) { 3866 // Also look pass the truncate. 3867 Use = *Use->use_begin(); 3868 if (Use->getOpcode() == ISD::BRCOND) 3869 AddToWorkList(Use); 3870 } 3871 } 3872 3873 return SDValue(); 3874} 3875 3876SDValue DAGCombiner::visitCTLZ(SDNode *N) { 3877 SDValue N0 = N->getOperand(0); 3878 EVT VT = N->getValueType(0); 3879 3880 // fold (ctlz c1) -> c2 3881 if (isa<ConstantSDNode>(N0)) 3882 return DAG.getNode(ISD::CTLZ, N->getDebugLoc(), VT, N0); 3883 return SDValue(); 3884} 3885 3886SDValue DAGCombiner::visitCTLZ_ZERO_UNDEF(SDNode *N) { 3887 SDValue N0 = N->getOperand(0); 3888 EVT VT = N->getValueType(0); 3889 3890 // fold (ctlz_zero_undef c1) -> c2 3891 if (isa<ConstantSDNode>(N0)) 3892 return DAG.getNode(ISD::CTLZ_ZERO_UNDEF, N->getDebugLoc(), VT, N0); 3893 return SDValue(); 3894} 3895 3896SDValue DAGCombiner::visitCTTZ(SDNode *N) { 3897 SDValue N0 = N->getOperand(0); 3898 EVT VT = N->getValueType(0); 3899 3900 // fold (cttz c1) -> c2 3901 if (isa<ConstantSDNode>(N0)) 3902 return DAG.getNode(ISD::CTTZ, N->getDebugLoc(), VT, N0); 3903 return SDValue(); 3904} 3905 3906SDValue DAGCombiner::visitCTTZ_ZERO_UNDEF(SDNode *N) { 3907 SDValue N0 = N->getOperand(0); 3908 EVT VT = N->getValueType(0); 3909 3910 // fold (cttz_zero_undef c1) -> c2 3911 if (isa<ConstantSDNode>(N0)) 3912 return DAG.getNode(ISD::CTTZ_ZERO_UNDEF, N->getDebugLoc(), VT, N0); 3913 return SDValue(); 3914} 3915 3916SDValue DAGCombiner::visitCTPOP(SDNode *N) { 3917 SDValue N0 = N->getOperand(0); 3918 EVT VT = N->getValueType(0); 3919 3920 // fold (ctpop c1) -> c2 3921 if (isa<ConstantSDNode>(N0)) 3922 return DAG.getNode(ISD::CTPOP, N->getDebugLoc(), VT, N0); 3923 return SDValue(); 3924} 3925 3926SDValue DAGCombiner::visitSELECT(SDNode *N) { 3927 SDValue N0 = N->getOperand(0); 3928 SDValue N1 = N->getOperand(1); 3929 SDValue N2 = N->getOperand(2); 3930 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3931 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3932 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2); 3933 EVT VT = N->getValueType(0); 3934 EVT VT0 = N0.getValueType(); 3935 3936 // fold (select C, X, X) -> X 3937 if (N1 == N2) 3938 return N1; 3939 // fold (select true, X, Y) -> X 3940 if (N0C && !N0C->isNullValue()) 3941 return N1; 3942 // fold (select false, X, Y) -> Y 3943 if (N0C && N0C->isNullValue()) 3944 return N2; 3945 // fold (select C, 1, X) -> (or C, X) 3946 if (VT == MVT::i1 && N1C && N1C->getAPIntValue() == 1) 3947 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2); 3948 // fold (select C, 0, 1) -> (xor C, 1) 3949 if (VT.isInteger() && 3950 (VT0 == MVT::i1 || 3951 (VT0.isInteger() && 3952 TLI.getBooleanContents(false) == TargetLowering::ZeroOrOneBooleanContent)) && 3953 N1C && N2C && N1C->isNullValue() && N2C->getAPIntValue() == 1) { 3954 SDValue XORNode; 3955 if (VT == VT0) 3956 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT0, 3957 N0, DAG.getConstant(1, VT0)); 3958 XORNode = DAG.getNode(ISD::XOR, N0.getDebugLoc(), VT0, 3959 N0, DAG.getConstant(1, VT0)); 3960 AddToWorkList(XORNode.getNode()); 3961 if (VT.bitsGT(VT0)) 3962 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, XORNode); 3963 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, XORNode); 3964 } 3965 // fold (select C, 0, X) -> (and (not C), X) 3966 if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) { 3967 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT); 3968 AddToWorkList(NOTNode.getNode()); 3969 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, NOTNode, N2); 3970 } 3971 // fold (select C, X, 1) -> (or (not C), X) 3972 if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getAPIntValue() == 1) { 3973 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT); 3974 AddToWorkList(NOTNode.getNode()); 3975 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, NOTNode, N1); 3976 } 3977 // fold (select C, X, 0) -> (and C, X) 3978 if (VT == MVT::i1 && N2C && N2C->isNullValue()) 3979 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1); 3980 // fold (select X, X, Y) -> (or X, Y) 3981 // fold (select X, 1, Y) -> (or X, Y) 3982 if (VT == MVT::i1 && (N0 == N1 || (N1C && N1C->getAPIntValue() == 1))) 3983 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2); 3984 // fold (select X, Y, X) -> (and X, Y) 3985 // fold (select X, Y, 0) -> (and X, Y) 3986 if (VT == MVT::i1 && (N0 == N2 || (N2C && N2C->getAPIntValue() == 0))) 3987 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1); 3988 3989 // If we can fold this based on the true/false value, do so. 3990 if (SimplifySelectOps(N, N1, N2)) 3991 return SDValue(N, 0); // Don't revisit N. 3992 3993 // fold selects based on a setcc into other things, such as min/max/abs 3994 if (N0.getOpcode() == ISD::SETCC) { 3995 // FIXME: 3996 // Check against MVT::Other for SELECT_CC, which is a workaround for targets 3997 // having to say they don't support SELECT_CC on every type the DAG knows 3998 // about, since there is no way to mark an opcode illegal at all value types 3999 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other) && 4000 TLI.isOperationLegalOrCustom(ISD::SELECT_CC, VT)) 4001 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT, 4002 N0.getOperand(0), N0.getOperand(1), 4003 N1, N2, N0.getOperand(2)); 4004 return SimplifySelect(N->getDebugLoc(), N0, N1, N2); 4005 } 4006 4007 return SDValue(); 4008} 4009 4010SDValue DAGCombiner::visitSELECT_CC(SDNode *N) { 4011 SDValue N0 = N->getOperand(0); 4012 SDValue N1 = N->getOperand(1); 4013 SDValue N2 = N->getOperand(2); 4014 SDValue N3 = N->getOperand(3); 4015 SDValue N4 = N->getOperand(4); 4016 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get(); 4017 4018 // fold select_cc lhs, rhs, x, x, cc -> x 4019 if (N2 == N3) 4020 return N2; 4021 4022 // Determine if the condition we're dealing with is constant 4023 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()), 4024 N0, N1, CC, N->getDebugLoc(), false); 4025 if (SCC.getNode()) AddToWorkList(SCC.getNode()); 4026 4027 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode())) { 4028 if (!SCCC->isNullValue()) 4029 return N2; // cond always true -> true val 4030 else 4031 return N3; // cond always false -> false val 4032 } 4033 4034 // Fold to a simpler select_cc 4035 if (SCC.getNode() && SCC.getOpcode() == ISD::SETCC) 4036 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), N2.getValueType(), 4037 SCC.getOperand(0), SCC.getOperand(1), N2, N3, 4038 SCC.getOperand(2)); 4039 4040 // If we can fold this based on the true/false value, do so. 4041 if (SimplifySelectOps(N, N2, N3)) 4042 return SDValue(N, 0); // Don't revisit N. 4043 4044 // fold select_cc into other things, such as min/max/abs 4045 return SimplifySelectCC(N->getDebugLoc(), N0, N1, N2, N3, CC); 4046} 4047 4048SDValue DAGCombiner::visitSETCC(SDNode *N) { 4049 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1), 4050 cast<CondCodeSDNode>(N->getOperand(2))->get(), 4051 N->getDebugLoc()); 4052} 4053 4054// ExtendUsesToFormExtLoad - Trying to extend uses of a load to enable this: 4055// "fold ({s|z|a}ext (load x)) -> ({s|z|a}ext (truncate ({s|z|a}extload x)))" 4056// transformation. Returns true if extension are possible and the above 4057// mentioned transformation is profitable. 4058static bool ExtendUsesToFormExtLoad(SDNode *N, SDValue N0, 4059 unsigned ExtOpc, 4060 SmallVector<SDNode*, 4> &ExtendNodes, 4061 const TargetLowering &TLI) { 4062 bool HasCopyToRegUses = false; 4063 bool isTruncFree = TLI.isTruncateFree(N->getValueType(0), N0.getValueType()); 4064 for (SDNode::use_iterator UI = N0.getNode()->use_begin(), 4065 UE = N0.getNode()->use_end(); 4066 UI != UE; ++UI) { 4067 SDNode *User = *UI; 4068 if (User == N) 4069 continue; 4070 if (UI.getUse().getResNo() != N0.getResNo()) 4071 continue; 4072 // FIXME: Only extend SETCC N, N and SETCC N, c for now. 4073 if (ExtOpc != ISD::ANY_EXTEND && User->getOpcode() == ISD::SETCC) { 4074 ISD::CondCode CC = cast<CondCodeSDNode>(User->getOperand(2))->get(); 4075 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC)) 4076 // Sign bits will be lost after a zext. 4077 return false; 4078 bool Add = false; 4079 for (unsigned i = 0; i != 2; ++i) { 4080 SDValue UseOp = User->getOperand(i); 4081 if (UseOp == N0) 4082 continue; 4083 if (!isa<ConstantSDNode>(UseOp)) 4084 return false; 4085 Add = true; 4086 } 4087 if (Add) 4088 ExtendNodes.push_back(User); 4089 continue; 4090 } 4091 // If truncates aren't free and there are users we can't 4092 // extend, it isn't worthwhile. 4093 if (!isTruncFree) 4094 return false; 4095 // Remember if this value is live-out. 4096 if (User->getOpcode() == ISD::CopyToReg) 4097 HasCopyToRegUses = true; 4098 } 4099 4100 if (HasCopyToRegUses) { 4101 bool BothLiveOut = false; 4102 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 4103 UI != UE; ++UI) { 4104 SDUse &Use = UI.getUse(); 4105 if (Use.getResNo() == 0 && Use.getUser()->getOpcode() == ISD::CopyToReg) { 4106 BothLiveOut = true; 4107 break; 4108 } 4109 } 4110 if (BothLiveOut) 4111 // Both unextended and extended values are live out. There had better be 4112 // a good reason for the transformation. 4113 return ExtendNodes.size(); 4114 } 4115 return true; 4116} 4117 4118void DAGCombiner::ExtendSetCCUses(SmallVector<SDNode*, 4> SetCCs, 4119 SDValue Trunc, SDValue ExtLoad, DebugLoc DL, 4120 ISD::NodeType ExtType) { 4121 // Extend SetCC uses if necessary. 4122 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 4123 SDNode *SetCC = SetCCs[i]; 4124 SmallVector<SDValue, 4> Ops; 4125 4126 for (unsigned j = 0; j != 2; ++j) { 4127 SDValue SOp = SetCC->getOperand(j); 4128 if (SOp == Trunc) 4129 Ops.push_back(ExtLoad); 4130 else 4131 Ops.push_back(DAG.getNode(ExtType, DL, ExtLoad->getValueType(0), SOp)); 4132 } 4133 4134 Ops.push_back(SetCC->getOperand(2)); 4135 CombineTo(SetCC, DAG.getNode(ISD::SETCC, DL, SetCC->getValueType(0), 4136 &Ops[0], Ops.size())); 4137 } 4138} 4139 4140SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) { 4141 SDValue N0 = N->getOperand(0); 4142 EVT VT = N->getValueType(0); 4143 4144 // fold (sext c1) -> c1 4145 if (isa<ConstantSDNode>(N0)) 4146 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N0); 4147 4148 // fold (sext (sext x)) -> (sext x) 4149 // fold (sext (aext x)) -> (sext x) 4150 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 4151 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, 4152 N0.getOperand(0)); 4153 4154 if (N0.getOpcode() == ISD::TRUNCATE) { 4155 // fold (sext (truncate (load x))) -> (sext (smaller load x)) 4156 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n))) 4157 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 4158 if (NarrowLoad.getNode()) { 4159 SDNode* oye = N0.getNode()->getOperand(0).getNode(); 4160 if (NarrowLoad.getNode() != N0.getNode()) { 4161 CombineTo(N0.getNode(), NarrowLoad); 4162 // CombineTo deleted the truncate, if needed, but not what's under it. 4163 AddToWorkList(oye); 4164 } 4165 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4166 } 4167 4168 // See if the value being truncated is already sign extended. If so, just 4169 // eliminate the trunc/sext pair. 4170 SDValue Op = N0.getOperand(0); 4171 unsigned OpBits = Op.getValueType().getScalarType().getSizeInBits(); 4172 unsigned MidBits = N0.getValueType().getScalarType().getSizeInBits(); 4173 unsigned DestBits = VT.getScalarType().getSizeInBits(); 4174 unsigned NumSignBits = DAG.ComputeNumSignBits(Op); 4175 4176 if (OpBits == DestBits) { 4177 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign 4178 // bits, it is already ready. 4179 if (NumSignBits > DestBits-MidBits) 4180 return Op; 4181 } else if (OpBits < DestBits) { 4182 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign 4183 // bits, just sext from i32. 4184 if (NumSignBits > OpBits-MidBits) 4185 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, Op); 4186 } else { 4187 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign 4188 // bits, just truncate to i32. 4189 if (NumSignBits > OpBits-MidBits) 4190 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op); 4191 } 4192 4193 // fold (sext (truncate x)) -> (sextinreg x). 4194 if (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, 4195 N0.getValueType())) { 4196 if (OpBits < DestBits) 4197 Op = DAG.getNode(ISD::ANY_EXTEND, N0.getDebugLoc(), VT, Op); 4198 else if (OpBits > DestBits) 4199 Op = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), VT, Op); 4200 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, Op, 4201 DAG.getValueType(N0.getValueType())); 4202 } 4203 } 4204 4205 // fold (sext (load x)) -> (sext (truncate (sextload x))) 4206 // None of the supported targets knows how to perform load and sign extend 4207 // on vectors in one instruction. We only perform this transformation on 4208 // scalars. 4209 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() && 4210 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 4211 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()))) { 4212 bool DoXform = true; 4213 SmallVector<SDNode*, 4> SetCCs; 4214 if (!N0.hasOneUse()) 4215 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::SIGN_EXTEND, SetCCs, TLI); 4216 if (DoXform) { 4217 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4218 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 4219 LN0->getChain(), 4220 LN0->getBasePtr(), LN0->getPointerInfo(), 4221 N0.getValueType(), 4222 LN0->isVolatile(), LN0->isNonTemporal(), 4223 LN0->getAlignment()); 4224 CombineTo(N, ExtLoad); 4225 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 4226 N0.getValueType(), ExtLoad); 4227 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 4228 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(), 4229 ISD::SIGN_EXTEND); 4230 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4231 } 4232 } 4233 4234 // fold (sext (sextload x)) -> (sext (truncate (sextload x))) 4235 // fold (sext ( extload x)) -> (sext (truncate (sextload x))) 4236 if ((ISD::isSEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) && 4237 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) { 4238 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4239 EVT MemVT = LN0->getMemoryVT(); 4240 if ((!LegalOperations && !LN0->isVolatile()) || 4241 TLI.isLoadExtLegal(ISD::SEXTLOAD, MemVT)) { 4242 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 4243 LN0->getChain(), 4244 LN0->getBasePtr(), LN0->getPointerInfo(), 4245 MemVT, 4246 LN0->isVolatile(), LN0->isNonTemporal(), 4247 LN0->getAlignment()); 4248 CombineTo(N, ExtLoad); 4249 CombineTo(N0.getNode(), 4250 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 4251 N0.getValueType(), ExtLoad), 4252 ExtLoad.getValue(1)); 4253 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4254 } 4255 } 4256 4257 // fold (sext (and/or/xor (load x), cst)) -> 4258 // (and/or/xor (sextload x), (sext cst)) 4259 if ((N0.getOpcode() == ISD::AND || N0.getOpcode() == ISD::OR || 4260 N0.getOpcode() == ISD::XOR) && 4261 isa<LoadSDNode>(N0.getOperand(0)) && 4262 N0.getOperand(1).getOpcode() == ISD::Constant && 4263 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()) && 4264 (!LegalOperations && TLI.isOperationLegal(N0.getOpcode(), VT))) { 4265 LoadSDNode *LN0 = cast<LoadSDNode>(N0.getOperand(0)); 4266 if (LN0->getExtensionType() != ISD::ZEXTLOAD) { 4267 bool DoXform = true; 4268 SmallVector<SDNode*, 4> SetCCs; 4269 if (!N0.hasOneUse()) 4270 DoXform = ExtendUsesToFormExtLoad(N, N0.getOperand(0), ISD::SIGN_EXTEND, 4271 SetCCs, TLI); 4272 if (DoXform) { 4273 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, LN0->getDebugLoc(), VT, 4274 LN0->getChain(), LN0->getBasePtr(), 4275 LN0->getPointerInfo(), 4276 LN0->getMemoryVT(), 4277 LN0->isVolatile(), 4278 LN0->isNonTemporal(), 4279 LN0->getAlignment()); 4280 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 4281 Mask = Mask.sext(VT.getSizeInBits()); 4282 SDValue And = DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, 4283 ExtLoad, DAG.getConstant(Mask, VT)); 4284 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, 4285 N0.getOperand(0).getDebugLoc(), 4286 N0.getOperand(0).getValueType(), ExtLoad); 4287 CombineTo(N, And); 4288 CombineTo(N0.getOperand(0).getNode(), Trunc, ExtLoad.getValue(1)); 4289 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(), 4290 ISD::SIGN_EXTEND); 4291 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4292 } 4293 } 4294 } 4295 4296 if (N0.getOpcode() == ISD::SETCC) { 4297 // sext(setcc) -> sext_in_reg(vsetcc) for vectors. 4298 // Only do this before legalize for now. 4299 if (VT.isVector() && !LegalOperations) { 4300 EVT N0VT = N0.getOperand(0).getValueType(); 4301 // We know that the # elements of the results is the same as the 4302 // # elements of the compare (and the # elements of the compare result 4303 // for that matter). Check to see that they are the same size. If so, 4304 // we know that the element size of the sext'd result matches the 4305 // element size of the compare operands. 4306 if (VT.getSizeInBits() == N0VT.getSizeInBits()) 4307 return DAG.getSetCC(N->getDebugLoc(), VT, N0.getOperand(0), 4308 N0.getOperand(1), 4309 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 4310 // If the desired elements are smaller or larger than the source 4311 // elements we can use a matching integer vector type and then 4312 // truncate/sign extend 4313 else { 4314 EVT MatchingElementType = 4315 EVT::getIntegerVT(*DAG.getContext(), 4316 N0VT.getScalarType().getSizeInBits()); 4317 EVT MatchingVectorType = 4318 EVT::getVectorVT(*DAG.getContext(), MatchingElementType, 4319 N0VT.getVectorNumElements()); 4320 SDValue VsetCC = 4321 DAG.getSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0), 4322 N0.getOperand(1), 4323 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 4324 return DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT); 4325 } 4326 } 4327 4328 // sext(setcc x, y, cc) -> (select_cc x, y, -1, 0, cc) 4329 unsigned ElementWidth = VT.getScalarType().getSizeInBits(); 4330 SDValue NegOne = 4331 DAG.getConstant(APInt::getAllOnesValue(ElementWidth), VT); 4332 SDValue SCC = 4333 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 4334 NegOne, DAG.getConstant(0, VT), 4335 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 4336 if (SCC.getNode()) return SCC; 4337 if (!LegalOperations || 4338 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(VT))) 4339 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT, 4340 DAG.getSetCC(N->getDebugLoc(), 4341 TLI.getSetCCResultType(VT), 4342 N0.getOperand(0), N0.getOperand(1), 4343 cast<CondCodeSDNode>(N0.getOperand(2))->get()), 4344 NegOne, DAG.getConstant(0, VT)); 4345 } 4346 4347 // fold (sext x) -> (zext x) if the sign bit is known zero. 4348 if ((!LegalOperations || TLI.isOperationLegal(ISD::ZERO_EXTEND, VT)) && 4349 DAG.SignBitIsZero(N0)) 4350 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0); 4351 4352 return SDValue(); 4353} 4354 4355SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) { 4356 SDValue N0 = N->getOperand(0); 4357 EVT VT = N->getValueType(0); 4358 4359 // fold (zext c1) -> c1 4360 if (isa<ConstantSDNode>(N0)) 4361 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0); 4362 // fold (zext (zext x)) -> (zext x) 4363 // fold (zext (aext x)) -> (zext x) 4364 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 4365 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, 4366 N0.getOperand(0)); 4367 4368 // fold (zext (truncate x)) -> (zext x) or 4369 // (zext (truncate x)) -> (truncate x) 4370 // This is valid when the truncated bits of x are already zero. 4371 // FIXME: We should extend this to work for vectors too. 4372 if (N0.getOpcode() == ISD::TRUNCATE && !VT.isVector()) { 4373 SDValue Op = N0.getOperand(0); 4374 APInt TruncatedBits 4375 = APInt::getBitsSet(Op.getValueSizeInBits(), 4376 N0.getValueSizeInBits(), 4377 std::min(Op.getValueSizeInBits(), 4378 VT.getSizeInBits())); 4379 APInt KnownZero, KnownOne; 4380 DAG.ComputeMaskedBits(Op, TruncatedBits, KnownZero, KnownOne); 4381 if (TruncatedBits == KnownZero) { 4382 if (VT.bitsGT(Op.getValueType())) 4383 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, Op); 4384 if (VT.bitsLT(Op.getValueType())) 4385 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op); 4386 4387 return Op; 4388 } 4389 } 4390 4391 // fold (zext (truncate (load x))) -> (zext (smaller load x)) 4392 // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n))) 4393 if (N0.getOpcode() == ISD::TRUNCATE) { 4394 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 4395 if (NarrowLoad.getNode()) { 4396 SDNode* oye = N0.getNode()->getOperand(0).getNode(); 4397 if (NarrowLoad.getNode() != N0.getNode()) { 4398 CombineTo(N0.getNode(), NarrowLoad); 4399 // CombineTo deleted the truncate, if needed, but not what's under it. 4400 AddToWorkList(oye); 4401 } 4402 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4403 } 4404 } 4405 4406 // fold (zext (truncate x)) -> (and x, mask) 4407 if (N0.getOpcode() == ISD::TRUNCATE && 4408 (!LegalOperations || TLI.isOperationLegal(ISD::AND, VT))) { 4409 4410 // fold (zext (truncate (load x))) -> (zext (smaller load x)) 4411 // fold (zext (truncate (srl (load x), c))) -> (zext (smaller load (x+c/n))) 4412 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 4413 if (NarrowLoad.getNode()) { 4414 SDNode* oye = N0.getNode()->getOperand(0).getNode(); 4415 if (NarrowLoad.getNode() != N0.getNode()) { 4416 CombineTo(N0.getNode(), NarrowLoad); 4417 // CombineTo deleted the truncate, if needed, but not what's under it. 4418 AddToWorkList(oye); 4419 } 4420 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4421 } 4422 4423 SDValue Op = N0.getOperand(0); 4424 if (Op.getValueType().bitsLT(VT)) { 4425 Op = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, Op); 4426 } else if (Op.getValueType().bitsGT(VT)) { 4427 Op = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op); 4428 } 4429 return DAG.getZeroExtendInReg(Op, N->getDebugLoc(), 4430 N0.getValueType().getScalarType()); 4431 } 4432 4433 // Fold (zext (and (trunc x), cst)) -> (and x, cst), 4434 // if either of the casts is not free. 4435 if (N0.getOpcode() == ISD::AND && 4436 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 4437 N0.getOperand(1).getOpcode() == ISD::Constant && 4438 (!TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(), 4439 N0.getValueType()) || 4440 !TLI.isZExtFree(N0.getValueType(), VT))) { 4441 SDValue X = N0.getOperand(0).getOperand(0); 4442 if (X.getValueType().bitsLT(VT)) { 4443 X = DAG.getNode(ISD::ANY_EXTEND, X.getDebugLoc(), VT, X); 4444 } else if (X.getValueType().bitsGT(VT)) { 4445 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X); 4446 } 4447 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 4448 Mask = Mask.zext(VT.getSizeInBits()); 4449 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 4450 X, DAG.getConstant(Mask, VT)); 4451 } 4452 4453 // fold (zext (load x)) -> (zext (truncate (zextload x))) 4454 // None of the supported targets knows how to perform load and vector_zext 4455 // on vectors in one instruction. We only perform this transformation on 4456 // scalars. 4457 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() && 4458 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 4459 TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()))) { 4460 bool DoXform = true; 4461 SmallVector<SDNode*, 4> SetCCs; 4462 if (!N0.hasOneUse()) 4463 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ZERO_EXTEND, SetCCs, TLI); 4464 if (DoXform) { 4465 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4466 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT, 4467 LN0->getChain(), 4468 LN0->getBasePtr(), LN0->getPointerInfo(), 4469 N0.getValueType(), 4470 LN0->isVolatile(), LN0->isNonTemporal(), 4471 LN0->getAlignment()); 4472 CombineTo(N, ExtLoad); 4473 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 4474 N0.getValueType(), ExtLoad); 4475 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 4476 4477 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(), 4478 ISD::ZERO_EXTEND); 4479 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4480 } 4481 } 4482 4483 // fold (zext (and/or/xor (load x), cst)) -> 4484 // (and/or/xor (zextload x), (zext cst)) 4485 if ((N0.getOpcode() == ISD::AND || N0.getOpcode() == ISD::OR || 4486 N0.getOpcode() == ISD::XOR) && 4487 isa<LoadSDNode>(N0.getOperand(0)) && 4488 N0.getOperand(1).getOpcode() == ISD::Constant && 4489 TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()) && 4490 (!LegalOperations && TLI.isOperationLegal(N0.getOpcode(), VT))) { 4491 LoadSDNode *LN0 = cast<LoadSDNode>(N0.getOperand(0)); 4492 if (LN0->getExtensionType() != ISD::SEXTLOAD) { 4493 bool DoXform = true; 4494 SmallVector<SDNode*, 4> SetCCs; 4495 if (!N0.hasOneUse()) 4496 DoXform = ExtendUsesToFormExtLoad(N, N0.getOperand(0), ISD::ZERO_EXTEND, 4497 SetCCs, TLI); 4498 if (DoXform) { 4499 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), VT, 4500 LN0->getChain(), LN0->getBasePtr(), 4501 LN0->getPointerInfo(), 4502 LN0->getMemoryVT(), 4503 LN0->isVolatile(), 4504 LN0->isNonTemporal(), 4505 LN0->getAlignment()); 4506 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 4507 Mask = Mask.zext(VT.getSizeInBits()); 4508 SDValue And = DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, 4509 ExtLoad, DAG.getConstant(Mask, VT)); 4510 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, 4511 N0.getOperand(0).getDebugLoc(), 4512 N0.getOperand(0).getValueType(), ExtLoad); 4513 CombineTo(N, And); 4514 CombineTo(N0.getOperand(0).getNode(), Trunc, ExtLoad.getValue(1)); 4515 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(), 4516 ISD::ZERO_EXTEND); 4517 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4518 } 4519 } 4520 } 4521 4522 // fold (zext (zextload x)) -> (zext (truncate (zextload x))) 4523 // fold (zext ( extload x)) -> (zext (truncate (zextload x))) 4524 if ((ISD::isZEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) && 4525 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) { 4526 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4527 EVT MemVT = LN0->getMemoryVT(); 4528 if ((!LegalOperations && !LN0->isVolatile()) || 4529 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT)) { 4530 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT, 4531 LN0->getChain(), 4532 LN0->getBasePtr(), LN0->getPointerInfo(), 4533 MemVT, 4534 LN0->isVolatile(), LN0->isNonTemporal(), 4535 LN0->getAlignment()); 4536 CombineTo(N, ExtLoad); 4537 CombineTo(N0.getNode(), 4538 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), N0.getValueType(), 4539 ExtLoad), 4540 ExtLoad.getValue(1)); 4541 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4542 } 4543 } 4544 4545 if (N0.getOpcode() == ISD::SETCC) { 4546 if (!LegalOperations && VT.isVector()) { 4547 // zext(setcc) -> (and (vsetcc), (1, 1, ...) for vectors. 4548 // Only do this before legalize for now. 4549 EVT N0VT = N0.getOperand(0).getValueType(); 4550 EVT EltVT = VT.getVectorElementType(); 4551 SmallVector<SDValue,8> OneOps(VT.getVectorNumElements(), 4552 DAG.getConstant(1, EltVT)); 4553 if (VT.getSizeInBits() == N0VT.getSizeInBits()) 4554 // We know that the # elements of the results is the same as the 4555 // # elements of the compare (and the # elements of the compare result 4556 // for that matter). Check to see that they are the same size. If so, 4557 // we know that the element size of the sext'd result matches the 4558 // element size of the compare operands. 4559 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 4560 DAG.getSetCC(N->getDebugLoc(), VT, N0.getOperand(0), 4561 N0.getOperand(1), 4562 cast<CondCodeSDNode>(N0.getOperand(2))->get()), 4563 DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT, 4564 &OneOps[0], OneOps.size())); 4565 4566 // If the desired elements are smaller or larger than the source 4567 // elements we can use a matching integer vector type and then 4568 // truncate/sign extend 4569 EVT MatchingElementType = 4570 EVT::getIntegerVT(*DAG.getContext(), 4571 N0VT.getScalarType().getSizeInBits()); 4572 EVT MatchingVectorType = 4573 EVT::getVectorVT(*DAG.getContext(), MatchingElementType, 4574 N0VT.getVectorNumElements()); 4575 SDValue VsetCC = 4576 DAG.getSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0), 4577 N0.getOperand(1), 4578 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 4579 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 4580 DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT), 4581 DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT, 4582 &OneOps[0], OneOps.size())); 4583 } 4584 4585 // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 4586 SDValue SCC = 4587 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 4588 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 4589 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 4590 if (SCC.getNode()) return SCC; 4591 } 4592 4593 // (zext (shl (zext x), cst)) -> (shl (zext x), cst) 4594 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL) && 4595 isa<ConstantSDNode>(N0.getOperand(1)) && 4596 N0.getOperand(0).getOpcode() == ISD::ZERO_EXTEND && 4597 N0.hasOneUse()) { 4598 SDValue ShAmt = N0.getOperand(1); 4599 unsigned ShAmtVal = cast<ConstantSDNode>(ShAmt)->getZExtValue(); 4600 if (N0.getOpcode() == ISD::SHL) { 4601 SDValue InnerZExt = N0.getOperand(0); 4602 // If the original shl may be shifting out bits, do not perform this 4603 // transformation. 4604 unsigned KnownZeroBits = InnerZExt.getValueType().getSizeInBits() - 4605 InnerZExt.getOperand(0).getValueType().getSizeInBits(); 4606 if (ShAmtVal > KnownZeroBits) 4607 return SDValue(); 4608 } 4609 4610 DebugLoc DL = N->getDebugLoc(); 4611 4612 // Ensure that the shift amount is wide enough for the shifted value. 4613 if (VT.getSizeInBits() >= 256) 4614 ShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, ShAmt); 4615 4616 return DAG.getNode(N0.getOpcode(), DL, VT, 4617 DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0)), 4618 ShAmt); 4619 } 4620 4621 return SDValue(); 4622} 4623 4624SDValue DAGCombiner::visitANY_EXTEND(SDNode *N) { 4625 SDValue N0 = N->getOperand(0); 4626 EVT VT = N->getValueType(0); 4627 4628 // fold (aext c1) -> c1 4629 if (isa<ConstantSDNode>(N0)) 4630 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, N0); 4631 // fold (aext (aext x)) -> (aext x) 4632 // fold (aext (zext x)) -> (zext x) 4633 // fold (aext (sext x)) -> (sext x) 4634 if (N0.getOpcode() == ISD::ANY_EXTEND || 4635 N0.getOpcode() == ISD::ZERO_EXTEND || 4636 N0.getOpcode() == ISD::SIGN_EXTEND) 4637 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, N0.getOperand(0)); 4638 4639 // fold (aext (truncate (load x))) -> (aext (smaller load x)) 4640 // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n))) 4641 if (N0.getOpcode() == ISD::TRUNCATE) { 4642 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 4643 if (NarrowLoad.getNode()) { 4644 SDNode* oye = N0.getNode()->getOperand(0).getNode(); 4645 if (NarrowLoad.getNode() != N0.getNode()) { 4646 CombineTo(N0.getNode(), NarrowLoad); 4647 // CombineTo deleted the truncate, if needed, but not what's under it. 4648 AddToWorkList(oye); 4649 } 4650 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4651 } 4652 } 4653 4654 // fold (aext (truncate x)) 4655 if (N0.getOpcode() == ISD::TRUNCATE) { 4656 SDValue TruncOp = N0.getOperand(0); 4657 if (TruncOp.getValueType() == VT) 4658 return TruncOp; // x iff x size == zext size. 4659 if (TruncOp.getValueType().bitsGT(VT)) 4660 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, TruncOp); 4661 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, TruncOp); 4662 } 4663 4664 // Fold (aext (and (trunc x), cst)) -> (and x, cst) 4665 // if the trunc is not free. 4666 if (N0.getOpcode() == ISD::AND && 4667 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 4668 N0.getOperand(1).getOpcode() == ISD::Constant && 4669 !TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(), 4670 N0.getValueType())) { 4671 SDValue X = N0.getOperand(0).getOperand(0); 4672 if (X.getValueType().bitsLT(VT)) { 4673 X = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, X); 4674 } else if (X.getValueType().bitsGT(VT)) { 4675 X = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, X); 4676 } 4677 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 4678 Mask = Mask.zext(VT.getSizeInBits()); 4679 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 4680 X, DAG.getConstant(Mask, VT)); 4681 } 4682 4683 // fold (aext (load x)) -> (aext (truncate (extload x))) 4684 // None of the supported targets knows how to perform load and any_ext 4685 // on vectors in one instruction. We only perform this transformation on 4686 // scalars. 4687 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() && 4688 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 4689 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) { 4690 bool DoXform = true; 4691 SmallVector<SDNode*, 4> SetCCs; 4692 if (!N0.hasOneUse()) 4693 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ANY_EXTEND, SetCCs, TLI); 4694 if (DoXform) { 4695 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4696 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT, 4697 LN0->getChain(), 4698 LN0->getBasePtr(), LN0->getPointerInfo(), 4699 N0.getValueType(), 4700 LN0->isVolatile(), LN0->isNonTemporal(), 4701 LN0->getAlignment()); 4702 CombineTo(N, ExtLoad); 4703 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 4704 N0.getValueType(), ExtLoad); 4705 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 4706 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(), 4707 ISD::ANY_EXTEND); 4708 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4709 } 4710 } 4711 4712 // fold (aext (zextload x)) -> (aext (truncate (zextload x))) 4713 // fold (aext (sextload x)) -> (aext (truncate (sextload x))) 4714 // fold (aext ( extload x)) -> (aext (truncate (extload x))) 4715 if (N0.getOpcode() == ISD::LOAD && 4716 !ISD::isNON_EXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 4717 N0.hasOneUse()) { 4718 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4719 EVT MemVT = LN0->getMemoryVT(); 4720 SDValue ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), N->getDebugLoc(), 4721 VT, LN0->getChain(), LN0->getBasePtr(), 4722 LN0->getPointerInfo(), MemVT, 4723 LN0->isVolatile(), LN0->isNonTemporal(), 4724 LN0->getAlignment()); 4725 CombineTo(N, ExtLoad); 4726 CombineTo(N0.getNode(), 4727 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 4728 N0.getValueType(), ExtLoad), 4729 ExtLoad.getValue(1)); 4730 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4731 } 4732 4733 if (N0.getOpcode() == ISD::SETCC) { 4734 // aext(setcc) -> sext_in_reg(vsetcc) for vectors. 4735 // Only do this before legalize for now. 4736 if (VT.isVector() && !LegalOperations) { 4737 EVT N0VT = N0.getOperand(0).getValueType(); 4738 // We know that the # elements of the results is the same as the 4739 // # elements of the compare (and the # elements of the compare result 4740 // for that matter). Check to see that they are the same size. If so, 4741 // we know that the element size of the sext'd result matches the 4742 // element size of the compare operands. 4743 if (VT.getSizeInBits() == N0VT.getSizeInBits()) 4744 return DAG.getSetCC(N->getDebugLoc(), VT, N0.getOperand(0), 4745 N0.getOperand(1), 4746 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 4747 // If the desired elements are smaller or larger than the source 4748 // elements we can use a matching integer vector type and then 4749 // truncate/sign extend 4750 else { 4751 EVT MatchingElementType = 4752 EVT::getIntegerVT(*DAG.getContext(), 4753 N0VT.getScalarType().getSizeInBits()); 4754 EVT MatchingVectorType = 4755 EVT::getVectorVT(*DAG.getContext(), MatchingElementType, 4756 N0VT.getVectorNumElements()); 4757 SDValue VsetCC = 4758 DAG.getSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0), 4759 N0.getOperand(1), 4760 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 4761 return DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT); 4762 } 4763 } 4764 4765 // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 4766 SDValue SCC = 4767 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 4768 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 4769 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 4770 if (SCC.getNode()) 4771 return SCC; 4772 } 4773 4774 return SDValue(); 4775} 4776 4777/// GetDemandedBits - See if the specified operand can be simplified with the 4778/// knowledge that only the bits specified by Mask are used. If so, return the 4779/// simpler operand, otherwise return a null SDValue. 4780SDValue DAGCombiner::GetDemandedBits(SDValue V, const APInt &Mask) { 4781 switch (V.getOpcode()) { 4782 default: break; 4783 case ISD::Constant: { 4784 const ConstantSDNode *CV = cast<ConstantSDNode>(V.getNode()); 4785 assert(CV != 0 && "Const value should be ConstSDNode."); 4786 const APInt &CVal = CV->getAPIntValue(); 4787 APInt NewVal = CVal & Mask; 4788 if (NewVal != CVal) { 4789 return DAG.getConstant(NewVal, V.getValueType()); 4790 } 4791 break; 4792 } 4793 case ISD::OR: 4794 case ISD::XOR: 4795 // If the LHS or RHS don't contribute bits to the or, drop them. 4796 if (DAG.MaskedValueIsZero(V.getOperand(0), Mask)) 4797 return V.getOperand(1); 4798 if (DAG.MaskedValueIsZero(V.getOperand(1), Mask)) 4799 return V.getOperand(0); 4800 break; 4801 case ISD::SRL: 4802 // Only look at single-use SRLs. 4803 if (!V.getNode()->hasOneUse()) 4804 break; 4805 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(V.getOperand(1))) { 4806 // See if we can recursively simplify the LHS. 4807 unsigned Amt = RHSC->getZExtValue(); 4808 4809 // Watch out for shift count overflow though. 4810 if (Amt >= Mask.getBitWidth()) break; 4811 APInt NewMask = Mask << Amt; 4812 SDValue SimplifyLHS = GetDemandedBits(V.getOperand(0), NewMask); 4813 if (SimplifyLHS.getNode()) 4814 return DAG.getNode(ISD::SRL, V.getDebugLoc(), V.getValueType(), 4815 SimplifyLHS, V.getOperand(1)); 4816 } 4817 } 4818 return SDValue(); 4819} 4820 4821/// ReduceLoadWidth - If the result of a wider load is shifted to right of N 4822/// bits and then truncated to a narrower type and where N is a multiple 4823/// of number of bits of the narrower type, transform it to a narrower load 4824/// from address + N / num of bits of new type. If the result is to be 4825/// extended, also fold the extension to form a extending load. 4826SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) { 4827 unsigned Opc = N->getOpcode(); 4828 4829 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD; 4830 SDValue N0 = N->getOperand(0); 4831 EVT VT = N->getValueType(0); 4832 EVT ExtVT = VT; 4833 4834 // This transformation isn't valid for vector loads. 4835 if (VT.isVector()) 4836 return SDValue(); 4837 4838 // Special case: SIGN_EXTEND_INREG is basically truncating to ExtVT then 4839 // extended to VT. 4840 if (Opc == ISD::SIGN_EXTEND_INREG) { 4841 ExtType = ISD::SEXTLOAD; 4842 ExtVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 4843 } else if (Opc == ISD::SRL) { 4844 // Another special-case: SRL is basically zero-extending a narrower value. 4845 ExtType = ISD::ZEXTLOAD; 4846 N0 = SDValue(N, 0); 4847 ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 4848 if (!N01) return SDValue(); 4849 ExtVT = EVT::getIntegerVT(*DAG.getContext(), 4850 VT.getSizeInBits() - N01->getZExtValue()); 4851 } 4852 if (LegalOperations && !TLI.isLoadExtLegal(ExtType, ExtVT)) 4853 return SDValue(); 4854 4855 unsigned EVTBits = ExtVT.getSizeInBits(); 4856 4857 // Do not generate loads of non-round integer types since these can 4858 // be expensive (and would be wrong if the type is not byte sized). 4859 if (!ExtVT.isRound()) 4860 return SDValue(); 4861 4862 unsigned ShAmt = 0; 4863 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) { 4864 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 4865 ShAmt = N01->getZExtValue(); 4866 // Is the shift amount a multiple of size of VT? 4867 if ((ShAmt & (EVTBits-1)) == 0) { 4868 N0 = N0.getOperand(0); 4869 // Is the load width a multiple of size of VT? 4870 if ((N0.getValueType().getSizeInBits() & (EVTBits-1)) != 0) 4871 return SDValue(); 4872 } 4873 4874 // At this point, we must have a load or else we can't do the transform. 4875 if (!isa<LoadSDNode>(N0)) return SDValue(); 4876 4877 // If the shift amount is larger than the input type then we're not 4878 // accessing any of the loaded bytes. If the load was a zextload/extload 4879 // then the result of the shift+trunc is zero/undef (handled elsewhere). 4880 // If the load was a sextload then the result is a splat of the sign bit 4881 // of the extended byte. This is not worth optimizing for. 4882 if (ShAmt >= cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits()) 4883 return SDValue(); 4884 } 4885 } 4886 4887 // If the load is shifted left (and the result isn't shifted back right), 4888 // we can fold the truncate through the shift. 4889 unsigned ShLeftAmt = 0; 4890 if (ShAmt == 0 && N0.getOpcode() == ISD::SHL && N0.hasOneUse() && 4891 ExtVT == VT && TLI.isNarrowingProfitable(N0.getValueType(), VT)) { 4892 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 4893 ShLeftAmt = N01->getZExtValue(); 4894 N0 = N0.getOperand(0); 4895 } 4896 } 4897 4898 // If we haven't found a load, we can't narrow it. Don't transform one with 4899 // multiple uses, this would require adding a new load. 4900 if (!isa<LoadSDNode>(N0) || !N0.hasOneUse() || 4901 // Don't change the width of a volatile load. 4902 cast<LoadSDNode>(N0)->isVolatile()) 4903 return SDValue(); 4904 4905 // Verify that we are actually reducing a load width here. 4906 if (cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits() < EVTBits) 4907 return SDValue(); 4908 4909 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4910 EVT PtrType = N0.getOperand(1).getValueType(); 4911 4912 // For big endian targets, we need to adjust the offset to the pointer to 4913 // load the correct bytes. 4914 if (TLI.isBigEndian()) { 4915 unsigned LVTStoreBits = LN0->getMemoryVT().getStoreSizeInBits(); 4916 unsigned EVTStoreBits = ExtVT.getStoreSizeInBits(); 4917 ShAmt = LVTStoreBits - EVTStoreBits - ShAmt; 4918 } 4919 4920 uint64_t PtrOff = ShAmt / 8; 4921 unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff); 4922 SDValue NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(), 4923 PtrType, LN0->getBasePtr(), 4924 DAG.getConstant(PtrOff, PtrType)); 4925 AddToWorkList(NewPtr.getNode()); 4926 4927 SDValue Load; 4928 if (ExtType == ISD::NON_EXTLOAD) 4929 Load = DAG.getLoad(VT, N0.getDebugLoc(), LN0->getChain(), NewPtr, 4930 LN0->getPointerInfo().getWithOffset(PtrOff), 4931 LN0->isVolatile(), LN0->isNonTemporal(), 4932 LN0->isInvariant(), NewAlign); 4933 else 4934 Load = DAG.getExtLoad(ExtType, N0.getDebugLoc(), VT, LN0->getChain(),NewPtr, 4935 LN0->getPointerInfo().getWithOffset(PtrOff), 4936 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(), 4937 NewAlign); 4938 4939 // Replace the old load's chain with the new load's chain. 4940 WorkListRemover DeadNodes(*this); 4941 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1), 4942 &DeadNodes); 4943 4944 // Shift the result left, if we've swallowed a left shift. 4945 SDValue Result = Load; 4946 if (ShLeftAmt != 0) { 4947 EVT ShImmTy = getShiftAmountTy(Result.getValueType()); 4948 if (!isUIntN(ShImmTy.getSizeInBits(), ShLeftAmt)) 4949 ShImmTy = VT; 4950 Result = DAG.getNode(ISD::SHL, N0.getDebugLoc(), VT, 4951 Result, DAG.getConstant(ShLeftAmt, ShImmTy)); 4952 } 4953 4954 // Return the new loaded value. 4955 return Result; 4956} 4957 4958SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) { 4959 SDValue N0 = N->getOperand(0); 4960 SDValue N1 = N->getOperand(1); 4961 EVT VT = N->getValueType(0); 4962 EVT EVT = cast<VTSDNode>(N1)->getVT(); 4963 unsigned VTBits = VT.getScalarType().getSizeInBits(); 4964 unsigned EVTBits = EVT.getScalarType().getSizeInBits(); 4965 4966 // fold (sext_in_reg c1) -> c1 4967 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF) 4968 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, N0, N1); 4969 4970 // If the input is already sign extended, just drop the extension. 4971 if (DAG.ComputeNumSignBits(N0) >= VTBits-EVTBits+1) 4972 return N0; 4973 4974 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2 4975 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 4976 EVT.bitsLT(cast<VTSDNode>(N0.getOperand(1))->getVT())) { 4977 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, 4978 N0.getOperand(0), N1); 4979 } 4980 4981 // fold (sext_in_reg (sext x)) -> (sext x) 4982 // fold (sext_in_reg (aext x)) -> (sext x) 4983 // if x is small enough. 4984 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) { 4985 SDValue N00 = N0.getOperand(0); 4986 if (N00.getValueType().getScalarType().getSizeInBits() <= EVTBits && 4987 (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND, VT))) 4988 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N00, N1); 4989 } 4990 4991 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero. 4992 if (DAG.MaskedValueIsZero(N0, APInt::getBitsSet(VTBits, EVTBits-1, EVTBits))) 4993 return DAG.getZeroExtendInReg(N0, N->getDebugLoc(), EVT); 4994 4995 // fold operands of sext_in_reg based on knowledge that the top bits are not 4996 // demanded. 4997 if (SimplifyDemandedBits(SDValue(N, 0))) 4998 return SDValue(N, 0); 4999 5000 // fold (sext_in_reg (load x)) -> (smaller sextload x) 5001 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits)) 5002 SDValue NarrowLoad = ReduceLoadWidth(N); 5003 if (NarrowLoad.getNode()) 5004 return NarrowLoad; 5005 5006 // fold (sext_in_reg (srl X, 24), i8) -> (sra X, 24) 5007 // fold (sext_in_reg (srl X, 23), i8) -> (sra X, 23) iff possible. 5008 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above. 5009 if (N0.getOpcode() == ISD::SRL) { 5010 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 5011 if (ShAmt->getZExtValue()+EVTBits <= VTBits) { 5012 // We can turn this into an SRA iff the input to the SRL is already sign 5013 // extended enough. 5014 unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0)); 5015 if (VTBits-(ShAmt->getZExtValue()+EVTBits) < InSignBits) 5016 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, 5017 N0.getOperand(0), N0.getOperand(1)); 5018 } 5019 } 5020 5021 // fold (sext_inreg (extload x)) -> (sextload x) 5022 if (ISD::isEXTLoad(N0.getNode()) && 5023 ISD::isUNINDEXEDLoad(N0.getNode()) && 5024 EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 5025 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 5026 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) { 5027 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 5028 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 5029 LN0->getChain(), 5030 LN0->getBasePtr(), LN0->getPointerInfo(), 5031 EVT, 5032 LN0->isVolatile(), LN0->isNonTemporal(), 5033 LN0->getAlignment()); 5034 CombineTo(N, ExtLoad); 5035 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 5036 return SDValue(N, 0); // Return N so it doesn't get rechecked! 5037 } 5038 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use 5039 if (ISD::isZEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 5040 N0.hasOneUse() && 5041 EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 5042 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 5043 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) { 5044 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 5045 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 5046 LN0->getChain(), 5047 LN0->getBasePtr(), LN0->getPointerInfo(), 5048 EVT, 5049 LN0->isVolatile(), LN0->isNonTemporal(), 5050 LN0->getAlignment()); 5051 CombineTo(N, ExtLoad); 5052 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 5053 return SDValue(N, 0); // Return N so it doesn't get rechecked! 5054 } 5055 5056 // Form (sext_inreg (bswap >> 16)) or (sext_inreg (rotl (bswap) 16)) 5057 if (EVTBits <= 16 && N0.getOpcode() == ISD::OR) { 5058 SDValue BSwap = MatchBSwapHWordLow(N0.getNode(), N0.getOperand(0), 5059 N0.getOperand(1), false); 5060 if (BSwap.getNode() != 0) 5061 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, 5062 BSwap, N1); 5063 } 5064 5065 return SDValue(); 5066} 5067 5068SDValue DAGCombiner::visitTRUNCATE(SDNode *N) { 5069 SDValue N0 = N->getOperand(0); 5070 EVT VT = N->getValueType(0); 5071 bool isLE = TLI.isLittleEndian(); 5072 5073 // noop truncate 5074 if (N0.getValueType() == N->getValueType(0)) 5075 return N0; 5076 // fold (truncate c1) -> c1 5077 if (isa<ConstantSDNode>(N0)) 5078 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0); 5079 // fold (truncate (truncate x)) -> (truncate x) 5080 if (N0.getOpcode() == ISD::TRUNCATE) 5081 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0)); 5082 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x 5083 if (N0.getOpcode() == ISD::ZERO_EXTEND || 5084 N0.getOpcode() == ISD::SIGN_EXTEND || 5085 N0.getOpcode() == ISD::ANY_EXTEND) { 5086 if (N0.getOperand(0).getValueType().bitsLT(VT)) 5087 // if the source is smaller than the dest, we still need an extend 5088 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, 5089 N0.getOperand(0)); 5090 else if (N0.getOperand(0).getValueType().bitsGT(VT)) 5091 // if the source is larger than the dest, than we just need the truncate 5092 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0)); 5093 else 5094 // if the source and dest are the same type, we can drop both the extend 5095 // and the truncate. 5096 return N0.getOperand(0); 5097 } 5098 5099 // Fold extract-and-trunc into a narrow extract. For example: 5100 // i64 x = EXTRACT_VECTOR_ELT(v2i64 val, i32 1) 5101 // i32 y = TRUNCATE(i64 x) 5102 // -- becomes -- 5103 // v16i8 b = BITCAST (v2i64 val) 5104 // i8 x = EXTRACT_VECTOR_ELT(v16i8 b, i32 8) 5105 // 5106 // Note: We only run this optimization after type legalization (which often 5107 // creates this pattern) and before operation legalization after which 5108 // we need to be more careful about the vector instructions that we generate. 5109 if (N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT && 5110 LegalTypes && !LegalOperations && N0->hasOneUse()) { 5111 5112 EVT VecTy = N0.getOperand(0).getValueType(); 5113 EVT ExTy = N0.getValueType(); 5114 EVT TrTy = N->getValueType(0); 5115 5116 unsigned NumElem = VecTy.getVectorNumElements(); 5117 unsigned SizeRatio = ExTy.getSizeInBits()/TrTy.getSizeInBits(); 5118 5119 EVT NVT = EVT::getVectorVT(*DAG.getContext(), TrTy, SizeRatio * NumElem); 5120 assert(NVT.getSizeInBits() == VecTy.getSizeInBits() && "Invalid Size"); 5121 5122 SDValue EltNo = N0->getOperand(1); 5123 if (isa<ConstantSDNode>(EltNo) && isTypeLegal(NVT)) { 5124 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 5125 5126 int Index = isLE ? (Elt*SizeRatio) : (Elt*SizeRatio + (SizeRatio-1)); 5127 5128 SDValue V = DAG.getNode(ISD::BITCAST, N->getDebugLoc(), 5129 NVT, N0.getOperand(0)); 5130 5131 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, 5132 N->getDebugLoc(), TrTy, V, 5133 DAG.getConstant(Index, MVT::i32)); 5134 } 5135 } 5136 5137 // See if we can simplify the input to this truncate through knowledge that 5138 // only the low bits are being used. 5139 // For example "trunc (or (shl x, 8), y)" // -> trunc y 5140 // Currently we only perform this optimization on scalars because vectors 5141 // may have different active low bits. 5142 if (!VT.isVector()) { 5143 SDValue Shorter = 5144 GetDemandedBits(N0, APInt::getLowBitsSet(N0.getValueSizeInBits(), 5145 VT.getSizeInBits())); 5146 if (Shorter.getNode()) 5147 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Shorter); 5148 } 5149 // fold (truncate (load x)) -> (smaller load x) 5150 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits)) 5151 if (!LegalTypes || TLI.isTypeDesirableForOp(N0.getOpcode(), VT)) { 5152 SDValue Reduced = ReduceLoadWidth(N); 5153 if (Reduced.getNode()) 5154 return Reduced; 5155 } 5156 5157 // Simplify the operands using demanded-bits information. 5158 if (!VT.isVector() && 5159 SimplifyDemandedBits(SDValue(N, 0))) 5160 return SDValue(N, 0); 5161 5162 return SDValue(); 5163} 5164 5165static SDNode *getBuildPairElt(SDNode *N, unsigned i) { 5166 SDValue Elt = N->getOperand(i); 5167 if (Elt.getOpcode() != ISD::MERGE_VALUES) 5168 return Elt.getNode(); 5169 return Elt.getOperand(Elt.getResNo()).getNode(); 5170} 5171 5172/// CombineConsecutiveLoads - build_pair (load, load) -> load 5173/// if load locations are consecutive. 5174SDValue DAGCombiner::CombineConsecutiveLoads(SDNode *N, EVT VT) { 5175 assert(N->getOpcode() == ISD::BUILD_PAIR); 5176 5177 LoadSDNode *LD1 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 0)); 5178 LoadSDNode *LD2 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 1)); 5179 if (!LD1 || !LD2 || !ISD::isNON_EXTLoad(LD1) || !LD1->hasOneUse() || 5180 LD1->getPointerInfo().getAddrSpace() != 5181 LD2->getPointerInfo().getAddrSpace()) 5182 return SDValue(); 5183 EVT LD1VT = LD1->getValueType(0); 5184 5185 if (ISD::isNON_EXTLoad(LD2) && 5186 LD2->hasOneUse() && 5187 // If both are volatile this would reduce the number of volatile loads. 5188 // If one is volatile it might be ok, but play conservative and bail out. 5189 !LD1->isVolatile() && 5190 !LD2->isVolatile() && 5191 DAG.isConsecutiveLoad(LD2, LD1, LD1VT.getSizeInBits()/8, 1)) { 5192 unsigned Align = LD1->getAlignment(); 5193 unsigned NewAlign = TLI.getTargetData()-> 5194 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext())); 5195 5196 if (NewAlign <= Align && 5197 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) 5198 return DAG.getLoad(VT, N->getDebugLoc(), LD1->getChain(), 5199 LD1->getBasePtr(), LD1->getPointerInfo(), 5200 false, false, false, Align); 5201 } 5202 5203 return SDValue(); 5204} 5205 5206SDValue DAGCombiner::visitBITCAST(SDNode *N) { 5207 SDValue N0 = N->getOperand(0); 5208 EVT VT = N->getValueType(0); 5209 5210 // If the input is a BUILD_VECTOR with all constant elements, fold this now. 5211 // Only do this before legalize, since afterward the target may be depending 5212 // on the bitconvert. 5213 // First check to see if this is all constant. 5214 if (!LegalTypes && 5215 N0.getOpcode() == ISD::BUILD_VECTOR && N0.getNode()->hasOneUse() && 5216 VT.isVector()) { 5217 bool isSimple = true; 5218 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i) 5219 if (N0.getOperand(i).getOpcode() != ISD::UNDEF && 5220 N0.getOperand(i).getOpcode() != ISD::Constant && 5221 N0.getOperand(i).getOpcode() != ISD::ConstantFP) { 5222 isSimple = false; 5223 break; 5224 } 5225 5226 EVT DestEltVT = N->getValueType(0).getVectorElementType(); 5227 assert(!DestEltVT.isVector() && 5228 "Element type of vector ValueType must not be vector!"); 5229 if (isSimple) 5230 return ConstantFoldBITCASTofBUILD_VECTOR(N0.getNode(), DestEltVT); 5231 } 5232 5233 // If the input is a constant, let getNode fold it. 5234 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) { 5235 SDValue Res = DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, N0); 5236 if (Res.getNode() != N) { 5237 if (!LegalOperations || 5238 TLI.isOperationLegal(Res.getNode()->getOpcode(), VT)) 5239 return Res; 5240 5241 // Folding it resulted in an illegal node, and it's too late to 5242 // do that. Clean up the old node and forego the transformation. 5243 // Ideally this won't happen very often, because instcombine 5244 // and the earlier dagcombine runs (where illegal nodes are 5245 // permitted) should have folded most of them already. 5246 DAG.DeleteNode(Res.getNode()); 5247 } 5248 } 5249 5250 // (conv (conv x, t1), t2) -> (conv x, t2) 5251 if (N0.getOpcode() == ISD::BITCAST) 5252 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, 5253 N0.getOperand(0)); 5254 5255 // fold (conv (load x)) -> (load (conv*)x) 5256 // If the resultant load doesn't need a higher alignment than the original! 5257 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() && 5258 // Do not change the width of a volatile load. 5259 !cast<LoadSDNode>(N0)->isVolatile() && 5260 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) { 5261 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 5262 unsigned Align = TLI.getTargetData()-> 5263 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext())); 5264 unsigned OrigAlign = LN0->getAlignment(); 5265 5266 if (Align <= OrigAlign) { 5267 SDValue Load = DAG.getLoad(VT, N->getDebugLoc(), LN0->getChain(), 5268 LN0->getBasePtr(), LN0->getPointerInfo(), 5269 LN0->isVolatile(), LN0->isNonTemporal(), 5270 LN0->isInvariant(), OrigAlign); 5271 AddToWorkList(N); 5272 CombineTo(N0.getNode(), 5273 DAG.getNode(ISD::BITCAST, N0.getDebugLoc(), 5274 N0.getValueType(), Load), 5275 Load.getValue(1)); 5276 return Load; 5277 } 5278 } 5279 5280 // fold (bitconvert (fneg x)) -> (xor (bitconvert x), signbit) 5281 // fold (bitconvert (fabs x)) -> (and (bitconvert x), (not signbit)) 5282 // This often reduces constant pool loads. 5283 if ((N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FABS) && 5284 N0.getNode()->hasOneUse() && VT.isInteger() && !VT.isVector()) { 5285 SDValue NewConv = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(), VT, 5286 N0.getOperand(0)); 5287 AddToWorkList(NewConv.getNode()); 5288 5289 APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); 5290 if (N0.getOpcode() == ISD::FNEG) 5291 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, 5292 NewConv, DAG.getConstant(SignBit, VT)); 5293 assert(N0.getOpcode() == ISD::FABS); 5294 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 5295 NewConv, DAG.getConstant(~SignBit, VT)); 5296 } 5297 5298 // fold (bitconvert (fcopysign cst, x)) -> 5299 // (or (and (bitconvert x), sign), (and cst, (not sign))) 5300 // Note that we don't handle (copysign x, cst) because this can always be 5301 // folded to an fneg or fabs. 5302 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse() && 5303 isa<ConstantFPSDNode>(N0.getOperand(0)) && 5304 VT.isInteger() && !VT.isVector()) { 5305 unsigned OrigXWidth = N0.getOperand(1).getValueType().getSizeInBits(); 5306 EVT IntXVT = EVT::getIntegerVT(*DAG.getContext(), OrigXWidth); 5307 if (isTypeLegal(IntXVT)) { 5308 SDValue X = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(), 5309 IntXVT, N0.getOperand(1)); 5310 AddToWorkList(X.getNode()); 5311 5312 // If X has a different width than the result/lhs, sext it or truncate it. 5313 unsigned VTWidth = VT.getSizeInBits(); 5314 if (OrigXWidth < VTWidth) { 5315 X = DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, X); 5316 AddToWorkList(X.getNode()); 5317 } else if (OrigXWidth > VTWidth) { 5318 // To get the sign bit in the right place, we have to shift it right 5319 // before truncating. 5320 X = DAG.getNode(ISD::SRL, X.getDebugLoc(), 5321 X.getValueType(), X, 5322 DAG.getConstant(OrigXWidth-VTWidth, X.getValueType())); 5323 AddToWorkList(X.getNode()); 5324 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X); 5325 AddToWorkList(X.getNode()); 5326 } 5327 5328 APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); 5329 X = DAG.getNode(ISD::AND, X.getDebugLoc(), VT, 5330 X, DAG.getConstant(SignBit, VT)); 5331 AddToWorkList(X.getNode()); 5332 5333 SDValue Cst = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(), 5334 VT, N0.getOperand(0)); 5335 Cst = DAG.getNode(ISD::AND, Cst.getDebugLoc(), VT, 5336 Cst, DAG.getConstant(~SignBit, VT)); 5337 AddToWorkList(Cst.getNode()); 5338 5339 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, X, Cst); 5340 } 5341 } 5342 5343 // bitconvert(build_pair(ld, ld)) -> ld iff load locations are consecutive. 5344 if (N0.getOpcode() == ISD::BUILD_PAIR) { 5345 SDValue CombineLD = CombineConsecutiveLoads(N0.getNode(), VT); 5346 if (CombineLD.getNode()) 5347 return CombineLD; 5348 } 5349 5350 return SDValue(); 5351} 5352 5353SDValue DAGCombiner::visitBUILD_PAIR(SDNode *N) { 5354 EVT VT = N->getValueType(0); 5355 return CombineConsecutiveLoads(N, VT); 5356} 5357 5358/// ConstantFoldBITCASTofBUILD_VECTOR - We know that BV is a build_vector 5359/// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the 5360/// destination element value type. 5361SDValue DAGCombiner:: 5362ConstantFoldBITCASTofBUILD_VECTOR(SDNode *BV, EVT DstEltVT) { 5363 EVT SrcEltVT = BV->getValueType(0).getVectorElementType(); 5364 5365 // If this is already the right type, we're done. 5366 if (SrcEltVT == DstEltVT) return SDValue(BV, 0); 5367 5368 unsigned SrcBitSize = SrcEltVT.getSizeInBits(); 5369 unsigned DstBitSize = DstEltVT.getSizeInBits(); 5370 5371 // If this is a conversion of N elements of one type to N elements of another 5372 // type, convert each element. This handles FP<->INT cases. 5373 if (SrcBitSize == DstBitSize) { 5374 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, 5375 BV->getValueType(0).getVectorNumElements()); 5376 5377 // Due to the FP element handling below calling this routine recursively, 5378 // we can end up with a scalar-to-vector node here. 5379 if (BV->getOpcode() == ISD::SCALAR_TO_VECTOR) 5380 return DAG.getNode(ISD::SCALAR_TO_VECTOR, BV->getDebugLoc(), VT, 5381 DAG.getNode(ISD::BITCAST, BV->getDebugLoc(), 5382 DstEltVT, BV->getOperand(0))); 5383 5384 SmallVector<SDValue, 8> Ops; 5385 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 5386 SDValue Op = BV->getOperand(i); 5387 // If the vector element type is not legal, the BUILD_VECTOR operands 5388 // are promoted and implicitly truncated. Make that explicit here. 5389 if (Op.getValueType() != SrcEltVT) 5390 Op = DAG.getNode(ISD::TRUNCATE, BV->getDebugLoc(), SrcEltVT, Op); 5391 Ops.push_back(DAG.getNode(ISD::BITCAST, BV->getDebugLoc(), 5392 DstEltVT, Op)); 5393 AddToWorkList(Ops.back().getNode()); 5394 } 5395 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 5396 &Ops[0], Ops.size()); 5397 } 5398 5399 // Otherwise, we're growing or shrinking the elements. To avoid having to 5400 // handle annoying details of growing/shrinking FP values, we convert them to 5401 // int first. 5402 if (SrcEltVT.isFloatingPoint()) { 5403 // Convert the input float vector to a int vector where the elements are the 5404 // same sizes. 5405 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!"); 5406 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), SrcEltVT.getSizeInBits()); 5407 BV = ConstantFoldBITCASTofBUILD_VECTOR(BV, IntVT).getNode(); 5408 SrcEltVT = IntVT; 5409 } 5410 5411 // Now we know the input is an integer vector. If the output is a FP type, 5412 // convert to integer first, then to FP of the right size. 5413 if (DstEltVT.isFloatingPoint()) { 5414 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!"); 5415 EVT TmpVT = EVT::getIntegerVT(*DAG.getContext(), DstEltVT.getSizeInBits()); 5416 SDNode *Tmp = ConstantFoldBITCASTofBUILD_VECTOR(BV, TmpVT).getNode(); 5417 5418 // Next, convert to FP elements of the same size. 5419 return ConstantFoldBITCASTofBUILD_VECTOR(Tmp, DstEltVT); 5420 } 5421 5422 // Okay, we know the src/dst types are both integers of differing types. 5423 // Handling growing first. 5424 assert(SrcEltVT.isInteger() && DstEltVT.isInteger()); 5425 if (SrcBitSize < DstBitSize) { 5426 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize; 5427 5428 SmallVector<SDValue, 8> Ops; 5429 for (unsigned i = 0, e = BV->getNumOperands(); i != e; 5430 i += NumInputsPerOutput) { 5431 bool isLE = TLI.isLittleEndian(); 5432 APInt NewBits = APInt(DstBitSize, 0); 5433 bool EltIsUndef = true; 5434 for (unsigned j = 0; j != NumInputsPerOutput; ++j) { 5435 // Shift the previously computed bits over. 5436 NewBits <<= SrcBitSize; 5437 SDValue Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j)); 5438 if (Op.getOpcode() == ISD::UNDEF) continue; 5439 EltIsUndef = false; 5440 5441 NewBits |= cast<ConstantSDNode>(Op)->getAPIntValue(). 5442 zextOrTrunc(SrcBitSize).zext(DstBitSize); 5443 } 5444 5445 if (EltIsUndef) 5446 Ops.push_back(DAG.getUNDEF(DstEltVT)); 5447 else 5448 Ops.push_back(DAG.getConstant(NewBits, DstEltVT)); 5449 } 5450 5451 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, Ops.size()); 5452 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 5453 &Ops[0], Ops.size()); 5454 } 5455 5456 // Finally, this must be the case where we are shrinking elements: each input 5457 // turns into multiple outputs. 5458 bool isS2V = ISD::isScalarToVector(BV); 5459 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize; 5460 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, 5461 NumOutputsPerInput*BV->getNumOperands()); 5462 SmallVector<SDValue, 8> Ops; 5463 5464 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 5465 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) { 5466 for (unsigned j = 0; j != NumOutputsPerInput; ++j) 5467 Ops.push_back(DAG.getUNDEF(DstEltVT)); 5468 continue; 5469 } 5470 5471 APInt OpVal = cast<ConstantSDNode>(BV->getOperand(i))-> 5472 getAPIntValue().zextOrTrunc(SrcBitSize); 5473 5474 for (unsigned j = 0; j != NumOutputsPerInput; ++j) { 5475 APInt ThisVal = OpVal.trunc(DstBitSize); 5476 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT)); 5477 if (isS2V && i == 0 && j == 0 && ThisVal.zext(SrcBitSize) == OpVal) 5478 // Simply turn this into a SCALAR_TO_VECTOR of the new type. 5479 return DAG.getNode(ISD::SCALAR_TO_VECTOR, BV->getDebugLoc(), VT, 5480 Ops[0]); 5481 OpVal = OpVal.lshr(DstBitSize); 5482 } 5483 5484 // For big endian targets, swap the order of the pieces of each element. 5485 if (TLI.isBigEndian()) 5486 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end()); 5487 } 5488 5489 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 5490 &Ops[0], Ops.size()); 5491} 5492 5493SDValue DAGCombiner::visitFADD(SDNode *N) { 5494 SDValue N0 = N->getOperand(0); 5495 SDValue N1 = N->getOperand(1); 5496 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5497 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 5498 EVT VT = N->getValueType(0); 5499 5500 // fold vector ops 5501 if (VT.isVector()) { 5502 SDValue FoldedVOp = SimplifyVBinOp(N); 5503 if (FoldedVOp.getNode()) return FoldedVOp; 5504 } 5505 5506 // fold (fadd c1, c2) -> (fadd c1, c2) 5507 if (N0CFP && N1CFP && VT != MVT::ppcf128) 5508 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N1); 5509 // canonicalize constant to RHS 5510 if (N0CFP && !N1CFP) 5511 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N1, N0); 5512 // fold (fadd A, 0) -> A 5513 if (DAG.getTarget().Options.UnsafeFPMath && N1CFP && 5514 N1CFP->getValueAPF().isZero()) 5515 return N0; 5516 // fold (fadd A, (fneg B)) -> (fsub A, B) 5517 if ((!LegalOperations || TLI.isOperationLegalOrCustom(ISD::FSUB, VT)) && 5518 isNegatibleForFree(N1, LegalOperations, TLI, &DAG.getTarget().Options) == 2) 5519 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, 5520 GetNegatedExpression(N1, DAG, LegalOperations)); 5521 // fold (fadd (fneg A), B) -> (fsub B, A) 5522 if ((!LegalOperations || TLI.isOperationLegalOrCustom(ISD::FSUB, VT)) && 5523 isNegatibleForFree(N0, LegalOperations, TLI, &DAG.getTarget().Options) == 2) 5524 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N1, 5525 GetNegatedExpression(N0, DAG, LegalOperations)); 5526 5527 // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2)) 5528 if (DAG.getTarget().Options.UnsafeFPMath && N1CFP && 5529 N0.getOpcode() == ISD::FADD && N0.getNode()->hasOneUse() && 5530 isa<ConstantFPSDNode>(N0.getOperand(1))) 5531 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0.getOperand(0), 5532 DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, 5533 N0.getOperand(1), N1)); 5534 5535 return SDValue(); 5536} 5537 5538SDValue DAGCombiner::visitFSUB(SDNode *N) { 5539 SDValue N0 = N->getOperand(0); 5540 SDValue N1 = N->getOperand(1); 5541 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5542 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 5543 EVT VT = N->getValueType(0); 5544 5545 // fold vector ops 5546 if (VT.isVector()) { 5547 SDValue FoldedVOp = SimplifyVBinOp(N); 5548 if (FoldedVOp.getNode()) return FoldedVOp; 5549 } 5550 5551 // fold (fsub c1, c2) -> c1-c2 5552 if (N0CFP && N1CFP && VT != MVT::ppcf128) 5553 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, N1); 5554 // fold (fsub A, 0) -> A 5555 if (DAG.getTarget().Options.UnsafeFPMath && 5556 N1CFP && N1CFP->getValueAPF().isZero()) 5557 return N0; 5558 // fold (fsub 0, B) -> -B 5559 if (DAG.getTarget().Options.UnsafeFPMath && 5560 N0CFP && N0CFP->getValueAPF().isZero()) { 5561 if (isNegatibleForFree(N1, LegalOperations, TLI, &DAG.getTarget().Options)) 5562 return GetNegatedExpression(N1, DAG, LegalOperations); 5563 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 5564 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N1); 5565 } 5566 // fold (fsub A, (fneg B)) -> (fadd A, B) 5567 if (isNegatibleForFree(N1, LegalOperations, TLI, &DAG.getTarget().Options)) 5568 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, 5569 GetNegatedExpression(N1, DAG, LegalOperations)); 5570 5571 // If 'unsafe math' is enabled, fold 5572 // (fsub x, (fadd x, y)) -> (fneg y) & 5573 // (fsub x, (fadd y, x)) -> (fneg y) 5574 if (DAG.getTarget().Options.UnsafeFPMath) { 5575 if (N1.getOpcode() == ISD::FADD) { 5576 SDValue N10 = N1->getOperand(0); 5577 SDValue N11 = N1->getOperand(1); 5578 5579 if (N10 == N0 && isNegatibleForFree(N11, LegalOperations, TLI, 5580 &DAG.getTarget().Options)) 5581 return GetNegatedExpression(N11, DAG, LegalOperations); 5582 else if (N11 == N0 && isNegatibleForFree(N10, LegalOperations, TLI, 5583 &DAG.getTarget().Options)) 5584 return GetNegatedExpression(N10, DAG, LegalOperations); 5585 } 5586 } 5587 5588 return SDValue(); 5589} 5590 5591SDValue DAGCombiner::visitFMUL(SDNode *N) { 5592 SDValue N0 = N->getOperand(0); 5593 SDValue N1 = N->getOperand(1); 5594 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5595 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 5596 EVT VT = N->getValueType(0); 5597 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 5598 5599 // fold vector ops 5600 if (VT.isVector()) { 5601 SDValue FoldedVOp = SimplifyVBinOp(N); 5602 if (FoldedVOp.getNode()) return FoldedVOp; 5603 } 5604 5605 // fold (fmul c1, c2) -> c1*c2 5606 if (N0CFP && N1CFP && VT != MVT::ppcf128) 5607 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0, N1); 5608 // canonicalize constant to RHS 5609 if (N0CFP && !N1CFP) 5610 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N1, N0); 5611 // fold (fmul A, 0) -> 0 5612 if (DAG.getTarget().Options.UnsafeFPMath && 5613 N1CFP && N1CFP->getValueAPF().isZero()) 5614 return N1; 5615 // fold (fmul A, 0) -> 0, vector edition. 5616 if (DAG.getTarget().Options.UnsafeFPMath && 5617 ISD::isBuildVectorAllZeros(N1.getNode())) 5618 return N1; 5619 // fold (fmul X, 2.0) -> (fadd X, X) 5620 if (N1CFP && N1CFP->isExactlyValue(+2.0)) 5621 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N0); 5622 // fold (fmul X, -1.0) -> (fneg X) 5623 if (N1CFP && N1CFP->isExactlyValue(-1.0)) 5624 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 5625 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N0); 5626 5627 // fold (fmul (fneg X), (fneg Y)) -> (fmul X, Y) 5628 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations, TLI, 5629 &DAG.getTarget().Options)) { 5630 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations, TLI, 5631 &DAG.getTarget().Options)) { 5632 // Both can be negated for free, check to see if at least one is cheaper 5633 // negated. 5634 if (LHSNeg == 2 || RHSNeg == 2) 5635 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 5636 GetNegatedExpression(N0, DAG, LegalOperations), 5637 GetNegatedExpression(N1, DAG, LegalOperations)); 5638 } 5639 } 5640 5641 // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2)) 5642 if (DAG.getTarget().Options.UnsafeFPMath && 5643 N1CFP && N0.getOpcode() == ISD::FMUL && 5644 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 5645 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0.getOperand(0), 5646 DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 5647 N0.getOperand(1), N1)); 5648 5649 return SDValue(); 5650} 5651 5652SDValue DAGCombiner::visitFDIV(SDNode *N) { 5653 SDValue N0 = N->getOperand(0); 5654 SDValue N1 = N->getOperand(1); 5655 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5656 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 5657 EVT VT = N->getValueType(0); 5658 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 5659 5660 // fold vector ops 5661 if (VT.isVector()) { 5662 SDValue FoldedVOp = SimplifyVBinOp(N); 5663 if (FoldedVOp.getNode()) return FoldedVOp; 5664 } 5665 5666 // fold (fdiv c1, c2) -> c1/c2 5667 if (N0CFP && N1CFP && VT != MVT::ppcf128) 5668 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, N0, N1); 5669 5670 5671 // (fdiv (fneg X), (fneg Y)) -> (fdiv X, Y) 5672 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations, TLI, 5673 &DAG.getTarget().Options)) { 5674 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations, TLI, 5675 &DAG.getTarget().Options)) { 5676 // Both can be negated for free, check to see if at least one is cheaper 5677 // negated. 5678 if (LHSNeg == 2 || RHSNeg == 2) 5679 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, 5680 GetNegatedExpression(N0, DAG, LegalOperations), 5681 GetNegatedExpression(N1, DAG, LegalOperations)); 5682 } 5683 } 5684 5685 return SDValue(); 5686} 5687 5688SDValue DAGCombiner::visitFREM(SDNode *N) { 5689 SDValue N0 = N->getOperand(0); 5690 SDValue N1 = N->getOperand(1); 5691 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5692 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 5693 EVT VT = N->getValueType(0); 5694 5695 // fold (frem c1, c2) -> fmod(c1,c2) 5696 if (N0CFP && N1CFP && VT != MVT::ppcf128) 5697 return DAG.getNode(ISD::FREM, N->getDebugLoc(), VT, N0, N1); 5698 5699 return SDValue(); 5700} 5701 5702SDValue DAGCombiner::visitFCOPYSIGN(SDNode *N) { 5703 SDValue N0 = N->getOperand(0); 5704 SDValue N1 = N->getOperand(1); 5705 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5706 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 5707 EVT VT = N->getValueType(0); 5708 5709 if (N0CFP && N1CFP && VT != MVT::ppcf128) // Constant fold 5710 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, N0, N1); 5711 5712 if (N1CFP) { 5713 const APFloat& V = N1CFP->getValueAPF(); 5714 // copysign(x, c1) -> fabs(x) iff ispos(c1) 5715 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1) 5716 if (!V.isNegative()) { 5717 if (!LegalOperations || TLI.isOperationLegal(ISD::FABS, VT)) 5718 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 5719 } else { 5720 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 5721 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, 5722 DAG.getNode(ISD::FABS, N0.getDebugLoc(), VT, N0)); 5723 } 5724 } 5725 5726 // copysign(fabs(x), y) -> copysign(x, y) 5727 // copysign(fneg(x), y) -> copysign(x, y) 5728 // copysign(copysign(x,z), y) -> copysign(x, y) 5729 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG || 5730 N0.getOpcode() == ISD::FCOPYSIGN) 5731 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 5732 N0.getOperand(0), N1); 5733 5734 // copysign(x, abs(y)) -> abs(x) 5735 if (N1.getOpcode() == ISD::FABS) 5736 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 5737 5738 // copysign(x, copysign(y,z)) -> copysign(x, z) 5739 if (N1.getOpcode() == ISD::FCOPYSIGN) 5740 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 5741 N0, N1.getOperand(1)); 5742 5743 // copysign(x, fp_extend(y)) -> copysign(x, y) 5744 // copysign(x, fp_round(y)) -> copysign(x, y) 5745 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND) 5746 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 5747 N0, N1.getOperand(0)); 5748 5749 return SDValue(); 5750} 5751 5752SDValue DAGCombiner::visitSINT_TO_FP(SDNode *N) { 5753 SDValue N0 = N->getOperand(0); 5754 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 5755 EVT VT = N->getValueType(0); 5756 EVT OpVT = N0.getValueType(); 5757 5758 // fold (sint_to_fp c1) -> c1fp 5759 if (N0C && OpVT != MVT::ppcf128 && 5760 // ...but only if the target supports immediate floating-point values 5761 (!LegalOperations || 5762 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT))) 5763 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0); 5764 5765 // If the input is a legal type, and SINT_TO_FP is not legal on this target, 5766 // but UINT_TO_FP is legal on this target, try to convert. 5767 if (!TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT) && 5768 TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT)) { 5769 // If the sign bit is known to be zero, we can change this to UINT_TO_FP. 5770 if (DAG.SignBitIsZero(N0)) 5771 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0); 5772 } 5773 5774 return SDValue(); 5775} 5776 5777SDValue DAGCombiner::visitUINT_TO_FP(SDNode *N) { 5778 SDValue N0 = N->getOperand(0); 5779 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 5780 EVT VT = N->getValueType(0); 5781 EVT OpVT = N0.getValueType(); 5782 5783 // fold (uint_to_fp c1) -> c1fp 5784 if (N0C && OpVT != MVT::ppcf128 && 5785 // ...but only if the target supports immediate floating-point values 5786 (!LegalOperations || 5787 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT))) 5788 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0); 5789 5790 // If the input is a legal type, and UINT_TO_FP is not legal on this target, 5791 // but SINT_TO_FP is legal on this target, try to convert. 5792 if (!TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT) && 5793 TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT)) { 5794 // If the sign bit is known to be zero, we can change this to SINT_TO_FP. 5795 if (DAG.SignBitIsZero(N0)) 5796 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0); 5797 } 5798 5799 return SDValue(); 5800} 5801 5802SDValue DAGCombiner::visitFP_TO_SINT(SDNode *N) { 5803 SDValue N0 = N->getOperand(0); 5804 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5805 EVT VT = N->getValueType(0); 5806 5807 // fold (fp_to_sint c1fp) -> c1 5808 if (N0CFP) 5809 return DAG.getNode(ISD::FP_TO_SINT, N->getDebugLoc(), VT, N0); 5810 5811 return SDValue(); 5812} 5813 5814SDValue DAGCombiner::visitFP_TO_UINT(SDNode *N) { 5815 SDValue N0 = N->getOperand(0); 5816 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5817 EVT VT = N->getValueType(0); 5818 5819 // fold (fp_to_uint c1fp) -> c1 5820 if (N0CFP && VT != MVT::ppcf128) 5821 return DAG.getNode(ISD::FP_TO_UINT, N->getDebugLoc(), VT, N0); 5822 5823 return SDValue(); 5824} 5825 5826SDValue DAGCombiner::visitFP_ROUND(SDNode *N) { 5827 SDValue N0 = N->getOperand(0); 5828 SDValue N1 = N->getOperand(1); 5829 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5830 EVT VT = N->getValueType(0); 5831 5832 // fold (fp_round c1fp) -> c1fp 5833 if (N0CFP && N0.getValueType() != MVT::ppcf128) 5834 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0, N1); 5835 5836 // fold (fp_round (fp_extend x)) -> x 5837 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType()) 5838 return N0.getOperand(0); 5839 5840 // fold (fp_round (fp_round x)) -> (fp_round x) 5841 if (N0.getOpcode() == ISD::FP_ROUND) { 5842 // This is a value preserving truncation if both round's are. 5843 bool IsTrunc = N->getConstantOperandVal(1) == 1 && 5844 N0.getNode()->getConstantOperandVal(1) == 1; 5845 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0.getOperand(0), 5846 DAG.getIntPtrConstant(IsTrunc)); 5847 } 5848 5849 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y) 5850 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse()) { 5851 SDValue Tmp = DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(), VT, 5852 N0.getOperand(0), N1); 5853 AddToWorkList(Tmp.getNode()); 5854 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 5855 Tmp, N0.getOperand(1)); 5856 } 5857 5858 return SDValue(); 5859} 5860 5861SDValue DAGCombiner::visitFP_ROUND_INREG(SDNode *N) { 5862 SDValue N0 = N->getOperand(0); 5863 EVT VT = N->getValueType(0); 5864 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 5865 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5866 5867 // fold (fp_round_inreg c1fp) -> c1fp 5868 if (N0CFP && isTypeLegal(EVT)) { 5869 SDValue Round = DAG.getConstantFP(*N0CFP->getConstantFPValue(), EVT); 5870 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, Round); 5871 } 5872 5873 return SDValue(); 5874} 5875 5876SDValue DAGCombiner::visitFP_EXTEND(SDNode *N) { 5877 SDValue N0 = N->getOperand(0); 5878 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5879 EVT VT = N->getValueType(0); 5880 5881 // If this is fp_round(fpextend), don't fold it, allow ourselves to be folded. 5882 if (N->hasOneUse() && 5883 N->use_begin()->getOpcode() == ISD::FP_ROUND) 5884 return SDValue(); 5885 5886 // fold (fp_extend c1fp) -> c1fp 5887 if (N0CFP && VT != MVT::ppcf128) 5888 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, N0); 5889 5890 // Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't affect the 5891 // value of X. 5892 if (N0.getOpcode() == ISD::FP_ROUND 5893 && N0.getNode()->getConstantOperandVal(1) == 1) { 5894 SDValue In = N0.getOperand(0); 5895 if (In.getValueType() == VT) return In; 5896 if (VT.bitsLT(In.getValueType())) 5897 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, 5898 In, N0.getOperand(1)); 5899 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, In); 5900 } 5901 5902 // fold (fpext (load x)) -> (fpext (fptrunc (extload x))) 5903 if (ISD::isNON_EXTLoad(N0.getNode()) && N0.hasOneUse() && 5904 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 5905 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) { 5906 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 5907 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT, 5908 LN0->getChain(), 5909 LN0->getBasePtr(), LN0->getPointerInfo(), 5910 N0.getValueType(), 5911 LN0->isVolatile(), LN0->isNonTemporal(), 5912 LN0->getAlignment()); 5913 CombineTo(N, ExtLoad); 5914 CombineTo(N0.getNode(), 5915 DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(), 5916 N0.getValueType(), ExtLoad, DAG.getIntPtrConstant(1)), 5917 ExtLoad.getValue(1)); 5918 return SDValue(N, 0); // Return N so it doesn't get rechecked! 5919 } 5920 5921 return SDValue(); 5922} 5923 5924SDValue DAGCombiner::visitFNEG(SDNode *N) { 5925 SDValue N0 = N->getOperand(0); 5926 EVT VT = N->getValueType(0); 5927 5928 if (isNegatibleForFree(N0, LegalOperations, DAG.getTargetLoweringInfo(), 5929 &DAG.getTarget().Options)) 5930 return GetNegatedExpression(N0, DAG, LegalOperations); 5931 5932 // Transform fneg(bitconvert(x)) -> bitconvert(x^sign) to avoid loading 5933 // constant pool values. 5934 if (N0.getOpcode() == ISD::BITCAST && 5935 !VT.isVector() && 5936 N0.getNode()->hasOneUse() && 5937 N0.getOperand(0).getValueType().isInteger()) { 5938 SDValue Int = N0.getOperand(0); 5939 EVT IntVT = Int.getValueType(); 5940 if (IntVT.isInteger() && !IntVT.isVector()) { 5941 Int = DAG.getNode(ISD::XOR, N0.getDebugLoc(), IntVT, Int, 5942 DAG.getConstant(APInt::getSignBit(IntVT.getSizeInBits()), IntVT)); 5943 AddToWorkList(Int.getNode()); 5944 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), 5945 VT, Int); 5946 } 5947 } 5948 5949 return SDValue(); 5950} 5951 5952SDValue DAGCombiner::visitFABS(SDNode *N) { 5953 SDValue N0 = N->getOperand(0); 5954 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5955 EVT VT = N->getValueType(0); 5956 5957 // fold (fabs c1) -> fabs(c1) 5958 if (N0CFP && VT != MVT::ppcf128) 5959 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 5960 // fold (fabs (fabs x)) -> (fabs x) 5961 if (N0.getOpcode() == ISD::FABS) 5962 return N->getOperand(0); 5963 // fold (fabs (fneg x)) -> (fabs x) 5964 // fold (fabs (fcopysign x, y)) -> (fabs x) 5965 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN) 5966 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0.getOperand(0)); 5967 5968 // Transform fabs(bitconvert(x)) -> bitconvert(x&~sign) to avoid loading 5969 // constant pool values. 5970 if (N0.getOpcode() == ISD::BITCAST && N0.getNode()->hasOneUse() && 5971 N0.getOperand(0).getValueType().isInteger() && 5972 !N0.getOperand(0).getValueType().isVector()) { 5973 SDValue Int = N0.getOperand(0); 5974 EVT IntVT = Int.getValueType(); 5975 if (IntVT.isInteger() && !IntVT.isVector()) { 5976 Int = DAG.getNode(ISD::AND, N0.getDebugLoc(), IntVT, Int, 5977 DAG.getConstant(~APInt::getSignBit(IntVT.getSizeInBits()), IntVT)); 5978 AddToWorkList(Int.getNode()); 5979 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), 5980 N->getValueType(0), Int); 5981 } 5982 } 5983 5984 return SDValue(); 5985} 5986 5987SDValue DAGCombiner::visitBRCOND(SDNode *N) { 5988 SDValue Chain = N->getOperand(0); 5989 SDValue N1 = N->getOperand(1); 5990 SDValue N2 = N->getOperand(2); 5991 5992 // If N is a constant we could fold this into a fallthrough or unconditional 5993 // branch. However that doesn't happen very often in normal code, because 5994 // Instcombine/SimplifyCFG should have handled the available opportunities. 5995 // If we did this folding here, it would be necessary to update the 5996 // MachineBasicBlock CFG, which is awkward. 5997 5998 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal 5999 // on the target. 6000 if (N1.getOpcode() == ISD::SETCC && 6001 TLI.isOperationLegalOrCustom(ISD::BR_CC, MVT::Other)) { 6002 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other, 6003 Chain, N1.getOperand(2), 6004 N1.getOperand(0), N1.getOperand(1), N2); 6005 } 6006 6007 if ((N1.hasOneUse() && N1.getOpcode() == ISD::SRL) || 6008 ((N1.getOpcode() == ISD::TRUNCATE && N1.hasOneUse()) && 6009 (N1.getOperand(0).hasOneUse() && 6010 N1.getOperand(0).getOpcode() == ISD::SRL))) { 6011 SDNode *Trunc = 0; 6012 if (N1.getOpcode() == ISD::TRUNCATE) { 6013 // Look pass the truncate. 6014 Trunc = N1.getNode(); 6015 N1 = N1.getOperand(0); 6016 } 6017 6018 // Match this pattern so that we can generate simpler code: 6019 // 6020 // %a = ... 6021 // %b = and i32 %a, 2 6022 // %c = srl i32 %b, 1 6023 // brcond i32 %c ... 6024 // 6025 // into 6026 // 6027 // %a = ... 6028 // %b = and i32 %a, 2 6029 // %c = setcc eq %b, 0 6030 // brcond %c ... 6031 // 6032 // This applies only when the AND constant value has one bit set and the 6033 // SRL constant is equal to the log2 of the AND constant. The back-end is 6034 // smart enough to convert the result into a TEST/JMP sequence. 6035 SDValue Op0 = N1.getOperand(0); 6036 SDValue Op1 = N1.getOperand(1); 6037 6038 if (Op0.getOpcode() == ISD::AND && 6039 Op1.getOpcode() == ISD::Constant) { 6040 SDValue AndOp1 = Op0.getOperand(1); 6041 6042 if (AndOp1.getOpcode() == ISD::Constant) { 6043 const APInt &AndConst = cast<ConstantSDNode>(AndOp1)->getAPIntValue(); 6044 6045 if (AndConst.isPowerOf2() && 6046 cast<ConstantSDNode>(Op1)->getAPIntValue()==AndConst.logBase2()) { 6047 SDValue SetCC = 6048 DAG.getSetCC(N->getDebugLoc(), 6049 TLI.getSetCCResultType(Op0.getValueType()), 6050 Op0, DAG.getConstant(0, Op0.getValueType()), 6051 ISD::SETNE); 6052 6053 SDValue NewBRCond = DAG.getNode(ISD::BRCOND, N->getDebugLoc(), 6054 MVT::Other, Chain, SetCC, N2); 6055 // Don't add the new BRCond into the worklist or else SimplifySelectCC 6056 // will convert it back to (X & C1) >> C2. 6057 CombineTo(N, NewBRCond, false); 6058 // Truncate is dead. 6059 if (Trunc) { 6060 removeFromWorkList(Trunc); 6061 DAG.DeleteNode(Trunc); 6062 } 6063 // Replace the uses of SRL with SETCC 6064 WorkListRemover DeadNodes(*this); 6065 DAG.ReplaceAllUsesOfValueWith(N1, SetCC, &DeadNodes); 6066 removeFromWorkList(N1.getNode()); 6067 DAG.DeleteNode(N1.getNode()); 6068 return SDValue(N, 0); // Return N so it doesn't get rechecked! 6069 } 6070 } 6071 } 6072 6073 if (Trunc) 6074 // Restore N1 if the above transformation doesn't match. 6075 N1 = N->getOperand(1); 6076 } 6077 6078 // Transform br(xor(x, y)) -> br(x != y) 6079 // Transform br(xor(xor(x,y), 1)) -> br (x == y) 6080 if (N1.hasOneUse() && N1.getOpcode() == ISD::XOR) { 6081 SDNode *TheXor = N1.getNode(); 6082 SDValue Op0 = TheXor->getOperand(0); 6083 SDValue Op1 = TheXor->getOperand(1); 6084 if (Op0.getOpcode() == Op1.getOpcode()) { 6085 // Avoid missing important xor optimizations. 6086 SDValue Tmp = visitXOR(TheXor); 6087 if (Tmp.getNode() && Tmp.getNode() != TheXor) { 6088 DEBUG(dbgs() << "\nReplacing.8 "; 6089 TheXor->dump(&DAG); 6090 dbgs() << "\nWith: "; 6091 Tmp.getNode()->dump(&DAG); 6092 dbgs() << '\n'); 6093 WorkListRemover DeadNodes(*this); 6094 DAG.ReplaceAllUsesOfValueWith(N1, Tmp, &DeadNodes); 6095 removeFromWorkList(TheXor); 6096 DAG.DeleteNode(TheXor); 6097 return DAG.getNode(ISD::BRCOND, N->getDebugLoc(), 6098 MVT::Other, Chain, Tmp, N2); 6099 } 6100 } 6101 6102 if (Op0.getOpcode() != ISD::SETCC && Op1.getOpcode() != ISD::SETCC) { 6103 bool Equal = false; 6104 if (ConstantSDNode *RHSCI = dyn_cast<ConstantSDNode>(Op0)) 6105 if (RHSCI->getAPIntValue() == 1 && Op0.hasOneUse() && 6106 Op0.getOpcode() == ISD::XOR) { 6107 TheXor = Op0.getNode(); 6108 Equal = true; 6109 } 6110 6111 EVT SetCCVT = N1.getValueType(); 6112 if (LegalTypes) 6113 SetCCVT = TLI.getSetCCResultType(SetCCVT); 6114 SDValue SetCC = DAG.getSetCC(TheXor->getDebugLoc(), 6115 SetCCVT, 6116 Op0, Op1, 6117 Equal ? ISD::SETEQ : ISD::SETNE); 6118 // Replace the uses of XOR with SETCC 6119 WorkListRemover DeadNodes(*this); 6120 DAG.ReplaceAllUsesOfValueWith(N1, SetCC, &DeadNodes); 6121 removeFromWorkList(N1.getNode()); 6122 DAG.DeleteNode(N1.getNode()); 6123 return DAG.getNode(ISD::BRCOND, N->getDebugLoc(), 6124 MVT::Other, Chain, SetCC, N2); 6125 } 6126 } 6127 6128 return SDValue(); 6129} 6130 6131// Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB. 6132// 6133SDValue DAGCombiner::visitBR_CC(SDNode *N) { 6134 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1)); 6135 SDValue CondLHS = N->getOperand(2), CondRHS = N->getOperand(3); 6136 6137 // If N is a constant we could fold this into a fallthrough or unconditional 6138 // branch. However that doesn't happen very often in normal code, because 6139 // Instcombine/SimplifyCFG should have handled the available opportunities. 6140 // If we did this folding here, it would be necessary to update the 6141 // MachineBasicBlock CFG, which is awkward. 6142 6143 // Use SimplifySetCC to simplify SETCC's. 6144 SDValue Simp = SimplifySetCC(TLI.getSetCCResultType(CondLHS.getValueType()), 6145 CondLHS, CondRHS, CC->get(), N->getDebugLoc(), 6146 false); 6147 if (Simp.getNode()) AddToWorkList(Simp.getNode()); 6148 6149 // fold to a simpler setcc 6150 if (Simp.getNode() && Simp.getOpcode() == ISD::SETCC) 6151 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other, 6152 N->getOperand(0), Simp.getOperand(2), 6153 Simp.getOperand(0), Simp.getOperand(1), 6154 N->getOperand(4)); 6155 6156 return SDValue(); 6157} 6158 6159/// canFoldInAddressingMode - Return true if 'Use' is a load or a store that 6160/// uses N as its base pointer and that N may be folded in the load / store 6161/// addressing mode. 6162static bool canFoldInAddressingMode(SDNode *N, SDNode *Use, 6163 SelectionDAG &DAG, 6164 const TargetLowering &TLI) { 6165 EVT VT; 6166 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Use)) { 6167 if (LD->isIndexed() || LD->getBasePtr().getNode() != N) 6168 return false; 6169 VT = Use->getValueType(0); 6170 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(Use)) { 6171 if (ST->isIndexed() || ST->getBasePtr().getNode() != N) 6172 return false; 6173 VT = ST->getValue().getValueType(); 6174 } else 6175 return false; 6176 6177 TargetLowering::AddrMode AM; 6178 if (N->getOpcode() == ISD::ADD) { 6179 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1)); 6180 if (Offset) 6181 // [reg +/- imm] 6182 AM.BaseOffs = Offset->getSExtValue(); 6183 else 6184 // [reg +/- reg] 6185 AM.Scale = 1; 6186 } else if (N->getOpcode() == ISD::SUB) { 6187 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1)); 6188 if (Offset) 6189 // [reg +/- imm] 6190 AM.BaseOffs = -Offset->getSExtValue(); 6191 else 6192 // [reg +/- reg] 6193 AM.Scale = 1; 6194 } else 6195 return false; 6196 6197 return TLI.isLegalAddressingMode(AM, VT.getTypeForEVT(*DAG.getContext())); 6198} 6199 6200/// CombineToPreIndexedLoadStore - Try turning a load / store into a 6201/// pre-indexed load / store when the base pointer is an add or subtract 6202/// and it has other uses besides the load / store. After the 6203/// transformation, the new indexed load / store has effectively folded 6204/// the add / subtract in and all of its other uses are redirected to the 6205/// new load / store. 6206bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) { 6207 if (Level < AfterLegalizeDAG) 6208 return false; 6209 6210 bool isLoad = true; 6211 SDValue Ptr; 6212 EVT VT; 6213 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 6214 if (LD->isIndexed()) 6215 return false; 6216 VT = LD->getMemoryVT(); 6217 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) && 6218 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT)) 6219 return false; 6220 Ptr = LD->getBasePtr(); 6221 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 6222 if (ST->isIndexed()) 6223 return false; 6224 VT = ST->getMemoryVT(); 6225 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) && 6226 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT)) 6227 return false; 6228 Ptr = ST->getBasePtr(); 6229 isLoad = false; 6230 } else { 6231 return false; 6232 } 6233 6234 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail 6235 // out. There is no reason to make this a preinc/predec. 6236 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) || 6237 Ptr.getNode()->hasOneUse()) 6238 return false; 6239 6240 // Ask the target to do addressing mode selection. 6241 SDValue BasePtr; 6242 SDValue Offset; 6243 ISD::MemIndexedMode AM = ISD::UNINDEXED; 6244 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG)) 6245 return false; 6246 // Don't create a indexed load / store with zero offset. 6247 if (isa<ConstantSDNode>(Offset) && 6248 cast<ConstantSDNode>(Offset)->isNullValue()) 6249 return false; 6250 6251 // Try turning it into a pre-indexed load / store except when: 6252 // 1) The new base ptr is a frame index. 6253 // 2) If N is a store and the new base ptr is either the same as or is a 6254 // predecessor of the value being stored. 6255 // 3) Another use of old base ptr is a predecessor of N. If ptr is folded 6256 // that would create a cycle. 6257 // 4) All uses are load / store ops that use it as old base ptr. 6258 6259 // Check #1. Preinc'ing a frame index would require copying the stack pointer 6260 // (plus the implicit offset) to a register to preinc anyway. 6261 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr)) 6262 return false; 6263 6264 // Check #2. 6265 if (!isLoad) { 6266 SDValue Val = cast<StoreSDNode>(N)->getValue(); 6267 if (Val == BasePtr || BasePtr.getNode()->isPredecessorOf(Val.getNode())) 6268 return false; 6269 } 6270 6271 // Now check for #3 and #4. 6272 bool RealUse = false; 6273 6274 // Caches for hasPredecessorHelper 6275 SmallPtrSet<const SDNode *, 32> Visited; 6276 SmallVector<const SDNode *, 16> Worklist; 6277 6278 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(), 6279 E = Ptr.getNode()->use_end(); I != E; ++I) { 6280 SDNode *Use = *I; 6281 if (Use == N) 6282 continue; 6283 if (N->hasPredecessorHelper(Use, Visited, Worklist)) 6284 return false; 6285 6286 // If Ptr may be folded in addressing mode of other use, then it's 6287 // not profitable to do this transformation. 6288 if (!canFoldInAddressingMode(Ptr.getNode(), Use, DAG, TLI)) 6289 RealUse = true; 6290 } 6291 6292 if (!RealUse) 6293 return false; 6294 6295 SDValue Result; 6296 if (isLoad) 6297 Result = DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(), 6298 BasePtr, Offset, AM); 6299 else 6300 Result = DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(), 6301 BasePtr, Offset, AM); 6302 ++PreIndexedNodes; 6303 ++NodesCombined; 6304 DEBUG(dbgs() << "\nReplacing.4 "; 6305 N->dump(&DAG); 6306 dbgs() << "\nWith: "; 6307 Result.getNode()->dump(&DAG); 6308 dbgs() << '\n'); 6309 WorkListRemover DeadNodes(*this); 6310 if (isLoad) { 6311 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0), 6312 &DeadNodes); 6313 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2), 6314 &DeadNodes); 6315 } else { 6316 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1), 6317 &DeadNodes); 6318 } 6319 6320 // Finally, since the node is now dead, remove it from the graph. 6321 DAG.DeleteNode(N); 6322 6323 // Replace the uses of Ptr with uses of the updated base value. 6324 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0), 6325 &DeadNodes); 6326 removeFromWorkList(Ptr.getNode()); 6327 DAG.DeleteNode(Ptr.getNode()); 6328 6329 return true; 6330} 6331 6332/// CombineToPostIndexedLoadStore - Try to combine a load / store with a 6333/// add / sub of the base pointer node into a post-indexed load / store. 6334/// The transformation folded the add / subtract into the new indexed 6335/// load / store effectively and all of its uses are redirected to the 6336/// new load / store. 6337bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) { 6338 if (Level < AfterLegalizeDAG) 6339 return false; 6340 6341 bool isLoad = true; 6342 SDValue Ptr; 6343 EVT VT; 6344 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 6345 if (LD->isIndexed()) 6346 return false; 6347 VT = LD->getMemoryVT(); 6348 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) && 6349 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT)) 6350 return false; 6351 Ptr = LD->getBasePtr(); 6352 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 6353 if (ST->isIndexed()) 6354 return false; 6355 VT = ST->getMemoryVT(); 6356 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) && 6357 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT)) 6358 return false; 6359 Ptr = ST->getBasePtr(); 6360 isLoad = false; 6361 } else { 6362 return false; 6363 } 6364 6365 if (Ptr.getNode()->hasOneUse()) 6366 return false; 6367 6368 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(), 6369 E = Ptr.getNode()->use_end(); I != E; ++I) { 6370 SDNode *Op = *I; 6371 if (Op == N || 6372 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB)) 6373 continue; 6374 6375 SDValue BasePtr; 6376 SDValue Offset; 6377 ISD::MemIndexedMode AM = ISD::UNINDEXED; 6378 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) { 6379 // Don't create a indexed load / store with zero offset. 6380 if (isa<ConstantSDNode>(Offset) && 6381 cast<ConstantSDNode>(Offset)->isNullValue()) 6382 continue; 6383 6384 // Try turning it into a post-indexed load / store except when 6385 // 1) All uses are load / store ops that use it as base ptr (and 6386 // it may be folded as addressing mmode). 6387 // 2) Op must be independent of N, i.e. Op is neither a predecessor 6388 // nor a successor of N. Otherwise, if Op is folded that would 6389 // create a cycle. 6390 6391 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr)) 6392 continue; 6393 6394 // Check for #1. 6395 bool TryNext = false; 6396 for (SDNode::use_iterator II = BasePtr.getNode()->use_begin(), 6397 EE = BasePtr.getNode()->use_end(); II != EE; ++II) { 6398 SDNode *Use = *II; 6399 if (Use == Ptr.getNode()) 6400 continue; 6401 6402 // If all the uses are load / store addresses, then don't do the 6403 // transformation. 6404 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){ 6405 bool RealUse = false; 6406 for (SDNode::use_iterator III = Use->use_begin(), 6407 EEE = Use->use_end(); III != EEE; ++III) { 6408 SDNode *UseUse = *III; 6409 if (!canFoldInAddressingMode(Use, UseUse, DAG, TLI)) 6410 RealUse = true; 6411 } 6412 6413 if (!RealUse) { 6414 TryNext = true; 6415 break; 6416 } 6417 } 6418 } 6419 6420 if (TryNext) 6421 continue; 6422 6423 // Check for #2 6424 if (!Op->isPredecessorOf(N) && !N->isPredecessorOf(Op)) { 6425 SDValue Result = isLoad 6426 ? DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(), 6427 BasePtr, Offset, AM) 6428 : DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(), 6429 BasePtr, Offset, AM); 6430 ++PostIndexedNodes; 6431 ++NodesCombined; 6432 DEBUG(dbgs() << "\nReplacing.5 "; 6433 N->dump(&DAG); 6434 dbgs() << "\nWith: "; 6435 Result.getNode()->dump(&DAG); 6436 dbgs() << '\n'); 6437 WorkListRemover DeadNodes(*this); 6438 if (isLoad) { 6439 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0), 6440 &DeadNodes); 6441 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2), 6442 &DeadNodes); 6443 } else { 6444 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1), 6445 &DeadNodes); 6446 } 6447 6448 // Finally, since the node is now dead, remove it from the graph. 6449 DAG.DeleteNode(N); 6450 6451 // Replace the uses of Use with uses of the updated base value. 6452 DAG.ReplaceAllUsesOfValueWith(SDValue(Op, 0), 6453 Result.getValue(isLoad ? 1 : 0), 6454 &DeadNodes); 6455 removeFromWorkList(Op); 6456 DAG.DeleteNode(Op); 6457 return true; 6458 } 6459 } 6460 } 6461 6462 return false; 6463} 6464 6465SDValue DAGCombiner::visitLOAD(SDNode *N) { 6466 LoadSDNode *LD = cast<LoadSDNode>(N); 6467 SDValue Chain = LD->getChain(); 6468 SDValue Ptr = LD->getBasePtr(); 6469 6470 // If load is not volatile and there are no uses of the loaded value (and 6471 // the updated indexed value in case of indexed loads), change uses of the 6472 // chain value into uses of the chain input (i.e. delete the dead load). 6473 if (!LD->isVolatile()) { 6474 if (N->getValueType(1) == MVT::Other) { 6475 // Unindexed loads. 6476 if (!N->hasAnyUseOfValue(0)) { 6477 // It's not safe to use the two value CombineTo variant here. e.g. 6478 // v1, chain2 = load chain1, loc 6479 // v2, chain3 = load chain2, loc 6480 // v3 = add v2, c 6481 // Now we replace use of chain2 with chain1. This makes the second load 6482 // isomorphic to the one we are deleting, and thus makes this load live. 6483 DEBUG(dbgs() << "\nReplacing.6 "; 6484 N->dump(&DAG); 6485 dbgs() << "\nWith chain: "; 6486 Chain.getNode()->dump(&DAG); 6487 dbgs() << "\n"); 6488 WorkListRemover DeadNodes(*this); 6489 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Chain, &DeadNodes); 6490 6491 if (N->use_empty()) { 6492 removeFromWorkList(N); 6493 DAG.DeleteNode(N); 6494 } 6495 6496 return SDValue(N, 0); // Return N so it doesn't get rechecked! 6497 } 6498 } else { 6499 // Indexed loads. 6500 assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?"); 6501 if (!N->hasAnyUseOfValue(0) && !N->hasAnyUseOfValue(1)) { 6502 SDValue Undef = DAG.getUNDEF(N->getValueType(0)); 6503 DEBUG(dbgs() << "\nReplacing.7 "; 6504 N->dump(&DAG); 6505 dbgs() << "\nWith: "; 6506 Undef.getNode()->dump(&DAG); 6507 dbgs() << " and 2 other values\n"); 6508 WorkListRemover DeadNodes(*this); 6509 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Undef, &DeadNodes); 6510 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), 6511 DAG.getUNDEF(N->getValueType(1)), 6512 &DeadNodes); 6513 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 2), Chain, &DeadNodes); 6514 removeFromWorkList(N); 6515 DAG.DeleteNode(N); 6516 return SDValue(N, 0); // Return N so it doesn't get rechecked! 6517 } 6518 } 6519 } 6520 6521 // If this load is directly stored, replace the load value with the stored 6522 // value. 6523 // TODO: Handle store large -> read small portion. 6524 // TODO: Handle TRUNCSTORE/LOADEXT 6525 if (ISD::isNormalLoad(N) && !LD->isVolatile()) { 6526 if (ISD::isNON_TRUNCStore(Chain.getNode())) { 6527 StoreSDNode *PrevST = cast<StoreSDNode>(Chain); 6528 if (PrevST->getBasePtr() == Ptr && 6529 PrevST->getValue().getValueType() == N->getValueType(0)) 6530 return CombineTo(N, Chain.getOperand(1), Chain); 6531 } 6532 } 6533 6534 // Try to infer better alignment information than the load already has. 6535 if (OptLevel != CodeGenOpt::None && LD->isUnindexed()) { 6536 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) { 6537 if (Align > LD->getAlignment()) 6538 return DAG.getExtLoad(LD->getExtensionType(), N->getDebugLoc(), 6539 LD->getValueType(0), 6540 Chain, Ptr, LD->getPointerInfo(), 6541 LD->getMemoryVT(), 6542 LD->isVolatile(), LD->isNonTemporal(), Align); 6543 } 6544 } 6545 6546 if (CombinerAA) { 6547 // Walk up chain skipping non-aliasing memory nodes. 6548 SDValue BetterChain = FindBetterChain(N, Chain); 6549 6550 // If there is a better chain. 6551 if (Chain != BetterChain) { 6552 SDValue ReplLoad; 6553 6554 // Replace the chain to void dependency. 6555 if (LD->getExtensionType() == ISD::NON_EXTLOAD) { 6556 ReplLoad = DAG.getLoad(N->getValueType(0), LD->getDebugLoc(), 6557 BetterChain, Ptr, LD->getPointerInfo(), 6558 LD->isVolatile(), LD->isNonTemporal(), 6559 LD->isInvariant(), LD->getAlignment()); 6560 } else { 6561 ReplLoad = DAG.getExtLoad(LD->getExtensionType(), LD->getDebugLoc(), 6562 LD->getValueType(0), 6563 BetterChain, Ptr, LD->getPointerInfo(), 6564 LD->getMemoryVT(), 6565 LD->isVolatile(), 6566 LD->isNonTemporal(), 6567 LD->getAlignment()); 6568 } 6569 6570 // Create token factor to keep old chain connected. 6571 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 6572 MVT::Other, Chain, ReplLoad.getValue(1)); 6573 6574 // Make sure the new and old chains are cleaned up. 6575 AddToWorkList(Token.getNode()); 6576 6577 // Replace uses with load result and token factor. Don't add users 6578 // to work list. 6579 return CombineTo(N, ReplLoad.getValue(0), Token, false); 6580 } 6581 } 6582 6583 // Try transforming N to an indexed load. 6584 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 6585 return SDValue(N, 0); 6586 6587 return SDValue(); 6588} 6589 6590/// CheckForMaskedLoad - Check to see if V is (and load (ptr), imm), where the 6591/// load is having specific bytes cleared out. If so, return the byte size 6592/// being masked out and the shift amount. 6593static std::pair<unsigned, unsigned> 6594CheckForMaskedLoad(SDValue V, SDValue Ptr, SDValue Chain) { 6595 std::pair<unsigned, unsigned> Result(0, 0); 6596 6597 // Check for the structure we're looking for. 6598 if (V->getOpcode() != ISD::AND || 6599 !isa<ConstantSDNode>(V->getOperand(1)) || 6600 !ISD::isNormalLoad(V->getOperand(0).getNode())) 6601 return Result; 6602 6603 // Check the chain and pointer. 6604 LoadSDNode *LD = cast<LoadSDNode>(V->getOperand(0)); 6605 if (LD->getBasePtr() != Ptr) return Result; // Not from same pointer. 6606 6607 // The store should be chained directly to the load or be an operand of a 6608 // tokenfactor. 6609 if (LD == Chain.getNode()) 6610 ; // ok. 6611 else if (Chain->getOpcode() != ISD::TokenFactor) 6612 return Result; // Fail. 6613 else { 6614 bool isOk = false; 6615 for (unsigned i = 0, e = Chain->getNumOperands(); i != e; ++i) 6616 if (Chain->getOperand(i).getNode() == LD) { 6617 isOk = true; 6618 break; 6619 } 6620 if (!isOk) return Result; 6621 } 6622 6623 // This only handles simple types. 6624 if (V.getValueType() != MVT::i16 && 6625 V.getValueType() != MVT::i32 && 6626 V.getValueType() != MVT::i64) 6627 return Result; 6628 6629 // Check the constant mask. Invert it so that the bits being masked out are 6630 // 0 and the bits being kept are 1. Use getSExtValue so that leading bits 6631 // follow the sign bit for uniformity. 6632 uint64_t NotMask = ~cast<ConstantSDNode>(V->getOperand(1))->getSExtValue(); 6633 unsigned NotMaskLZ = CountLeadingZeros_64(NotMask); 6634 if (NotMaskLZ & 7) return Result; // Must be multiple of a byte. 6635 unsigned NotMaskTZ = CountTrailingZeros_64(NotMask); 6636 if (NotMaskTZ & 7) return Result; // Must be multiple of a byte. 6637 if (NotMaskLZ == 64) return Result; // All zero mask. 6638 6639 // See if we have a continuous run of bits. If so, we have 0*1+0* 6640 if (CountTrailingOnes_64(NotMask >> NotMaskTZ)+NotMaskTZ+NotMaskLZ != 64) 6641 return Result; 6642 6643 // Adjust NotMaskLZ down to be from the actual size of the int instead of i64. 6644 if (V.getValueType() != MVT::i64 && NotMaskLZ) 6645 NotMaskLZ -= 64-V.getValueSizeInBits(); 6646 6647 unsigned MaskedBytes = (V.getValueSizeInBits()-NotMaskLZ-NotMaskTZ)/8; 6648 switch (MaskedBytes) { 6649 case 1: 6650 case 2: 6651 case 4: break; 6652 default: return Result; // All one mask, or 5-byte mask. 6653 } 6654 6655 // Verify that the first bit starts at a multiple of mask so that the access 6656 // is aligned the same as the access width. 6657 if (NotMaskTZ && NotMaskTZ/8 % MaskedBytes) return Result; 6658 6659 Result.first = MaskedBytes; 6660 Result.second = NotMaskTZ/8; 6661 return Result; 6662} 6663 6664 6665/// ShrinkLoadReplaceStoreWithStore - Check to see if IVal is something that 6666/// provides a value as specified by MaskInfo. If so, replace the specified 6667/// store with a narrower store of truncated IVal. 6668static SDNode * 6669ShrinkLoadReplaceStoreWithStore(const std::pair<unsigned, unsigned> &MaskInfo, 6670 SDValue IVal, StoreSDNode *St, 6671 DAGCombiner *DC) { 6672 unsigned NumBytes = MaskInfo.first; 6673 unsigned ByteShift = MaskInfo.second; 6674 SelectionDAG &DAG = DC->getDAG(); 6675 6676 // Check to see if IVal is all zeros in the part being masked in by the 'or' 6677 // that uses this. If not, this is not a replacement. 6678 APInt Mask = ~APInt::getBitsSet(IVal.getValueSizeInBits(), 6679 ByteShift*8, (ByteShift+NumBytes)*8); 6680 if (!DAG.MaskedValueIsZero(IVal, Mask)) return 0; 6681 6682 // Check that it is legal on the target to do this. It is legal if the new 6683 // VT we're shrinking to (i8/i16/i32) is legal or we're still before type 6684 // legalization. 6685 MVT VT = MVT::getIntegerVT(NumBytes*8); 6686 if (!DC->isTypeLegal(VT)) 6687 return 0; 6688 6689 // Okay, we can do this! Replace the 'St' store with a store of IVal that is 6690 // shifted by ByteShift and truncated down to NumBytes. 6691 if (ByteShift) 6692 IVal = DAG.getNode(ISD::SRL, IVal->getDebugLoc(), IVal.getValueType(), IVal, 6693 DAG.getConstant(ByteShift*8, 6694 DC->getShiftAmountTy(IVal.getValueType()))); 6695 6696 // Figure out the offset for the store and the alignment of the access. 6697 unsigned StOffset; 6698 unsigned NewAlign = St->getAlignment(); 6699 6700 if (DAG.getTargetLoweringInfo().isLittleEndian()) 6701 StOffset = ByteShift; 6702 else 6703 StOffset = IVal.getValueType().getStoreSize() - ByteShift - NumBytes; 6704 6705 SDValue Ptr = St->getBasePtr(); 6706 if (StOffset) { 6707 Ptr = DAG.getNode(ISD::ADD, IVal->getDebugLoc(), Ptr.getValueType(), 6708 Ptr, DAG.getConstant(StOffset, Ptr.getValueType())); 6709 NewAlign = MinAlign(NewAlign, StOffset); 6710 } 6711 6712 // Truncate down to the new size. 6713 IVal = DAG.getNode(ISD::TRUNCATE, IVal->getDebugLoc(), VT, IVal); 6714 6715 ++OpsNarrowed; 6716 return DAG.getStore(St->getChain(), St->getDebugLoc(), IVal, Ptr, 6717 St->getPointerInfo().getWithOffset(StOffset), 6718 false, false, NewAlign).getNode(); 6719} 6720 6721 6722/// ReduceLoadOpStoreWidth - Look for sequence of load / op / store where op is 6723/// one of 'or', 'xor', and 'and' of immediates. If 'op' is only touching some 6724/// of the loaded bits, try narrowing the load and store if it would end up 6725/// being a win for performance or code size. 6726SDValue DAGCombiner::ReduceLoadOpStoreWidth(SDNode *N) { 6727 StoreSDNode *ST = cast<StoreSDNode>(N); 6728 if (ST->isVolatile()) 6729 return SDValue(); 6730 6731 SDValue Chain = ST->getChain(); 6732 SDValue Value = ST->getValue(); 6733 SDValue Ptr = ST->getBasePtr(); 6734 EVT VT = Value.getValueType(); 6735 6736 if (ST->isTruncatingStore() || VT.isVector() || !Value.hasOneUse()) 6737 return SDValue(); 6738 6739 unsigned Opc = Value.getOpcode(); 6740 6741 // If this is "store (or X, Y), P" and X is "(and (load P), cst)", where cst 6742 // is a byte mask indicating a consecutive number of bytes, check to see if 6743 // Y is known to provide just those bytes. If so, we try to replace the 6744 // load + replace + store sequence with a single (narrower) store, which makes 6745 // the load dead. 6746 if (Opc == ISD::OR) { 6747 std::pair<unsigned, unsigned> MaskedLoad; 6748 MaskedLoad = CheckForMaskedLoad(Value.getOperand(0), Ptr, Chain); 6749 if (MaskedLoad.first) 6750 if (SDNode *NewST = ShrinkLoadReplaceStoreWithStore(MaskedLoad, 6751 Value.getOperand(1), ST,this)) 6752 return SDValue(NewST, 0); 6753 6754 // Or is commutative, so try swapping X and Y. 6755 MaskedLoad = CheckForMaskedLoad(Value.getOperand(1), Ptr, Chain); 6756 if (MaskedLoad.first) 6757 if (SDNode *NewST = ShrinkLoadReplaceStoreWithStore(MaskedLoad, 6758 Value.getOperand(0), ST,this)) 6759 return SDValue(NewST, 0); 6760 } 6761 6762 if ((Opc != ISD::OR && Opc != ISD::XOR && Opc != ISD::AND) || 6763 Value.getOperand(1).getOpcode() != ISD::Constant) 6764 return SDValue(); 6765 6766 SDValue N0 = Value.getOperand(0); 6767 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() && 6768 Chain == SDValue(N0.getNode(), 1)) { 6769 LoadSDNode *LD = cast<LoadSDNode>(N0); 6770 if (LD->getBasePtr() != Ptr || 6771 LD->getPointerInfo().getAddrSpace() != 6772 ST->getPointerInfo().getAddrSpace()) 6773 return SDValue(); 6774 6775 // Find the type to narrow it the load / op / store to. 6776 SDValue N1 = Value.getOperand(1); 6777 unsigned BitWidth = N1.getValueSizeInBits(); 6778 APInt Imm = cast<ConstantSDNode>(N1)->getAPIntValue(); 6779 if (Opc == ISD::AND) 6780 Imm ^= APInt::getAllOnesValue(BitWidth); 6781 if (Imm == 0 || Imm.isAllOnesValue()) 6782 return SDValue(); 6783 unsigned ShAmt = Imm.countTrailingZeros(); 6784 unsigned MSB = BitWidth - Imm.countLeadingZeros() - 1; 6785 unsigned NewBW = NextPowerOf2(MSB - ShAmt); 6786 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW); 6787 while (NewBW < BitWidth && 6788 !(TLI.isOperationLegalOrCustom(Opc, NewVT) && 6789 TLI.isNarrowingProfitable(VT, NewVT))) { 6790 NewBW = NextPowerOf2(NewBW); 6791 NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW); 6792 } 6793 if (NewBW >= BitWidth) 6794 return SDValue(); 6795 6796 // If the lsb changed does not start at the type bitwidth boundary, 6797 // start at the previous one. 6798 if (ShAmt % NewBW) 6799 ShAmt = (((ShAmt + NewBW - 1) / NewBW) * NewBW) - NewBW; 6800 APInt Mask = APInt::getBitsSet(BitWidth, ShAmt, ShAmt + NewBW); 6801 if ((Imm & Mask) == Imm) { 6802 APInt NewImm = (Imm & Mask).lshr(ShAmt).trunc(NewBW); 6803 if (Opc == ISD::AND) 6804 NewImm ^= APInt::getAllOnesValue(NewBW); 6805 uint64_t PtrOff = ShAmt / 8; 6806 // For big endian targets, we need to adjust the offset to the pointer to 6807 // load the correct bytes. 6808 if (TLI.isBigEndian()) 6809 PtrOff = (BitWidth + 7 - NewBW) / 8 - PtrOff; 6810 6811 unsigned NewAlign = MinAlign(LD->getAlignment(), PtrOff); 6812 Type *NewVTTy = NewVT.getTypeForEVT(*DAG.getContext()); 6813 if (NewAlign < TLI.getTargetData()->getABITypeAlignment(NewVTTy)) 6814 return SDValue(); 6815 6816 SDValue NewPtr = DAG.getNode(ISD::ADD, LD->getDebugLoc(), 6817 Ptr.getValueType(), Ptr, 6818 DAG.getConstant(PtrOff, Ptr.getValueType())); 6819 SDValue NewLD = DAG.getLoad(NewVT, N0.getDebugLoc(), 6820 LD->getChain(), NewPtr, 6821 LD->getPointerInfo().getWithOffset(PtrOff), 6822 LD->isVolatile(), LD->isNonTemporal(), 6823 LD->isInvariant(), NewAlign); 6824 SDValue NewVal = DAG.getNode(Opc, Value.getDebugLoc(), NewVT, NewLD, 6825 DAG.getConstant(NewImm, NewVT)); 6826 SDValue NewST = DAG.getStore(Chain, N->getDebugLoc(), 6827 NewVal, NewPtr, 6828 ST->getPointerInfo().getWithOffset(PtrOff), 6829 false, false, NewAlign); 6830 6831 AddToWorkList(NewPtr.getNode()); 6832 AddToWorkList(NewLD.getNode()); 6833 AddToWorkList(NewVal.getNode()); 6834 WorkListRemover DeadNodes(*this); 6835 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), NewLD.getValue(1), 6836 &DeadNodes); 6837 ++OpsNarrowed; 6838 return NewST; 6839 } 6840 } 6841 6842 return SDValue(); 6843} 6844 6845/// TransformFPLoadStorePair - For a given floating point load / store pair, 6846/// if the load value isn't used by any other operations, then consider 6847/// transforming the pair to integer load / store operations if the target 6848/// deems the transformation profitable. 6849SDValue DAGCombiner::TransformFPLoadStorePair(SDNode *N) { 6850 StoreSDNode *ST = cast<StoreSDNode>(N); 6851 SDValue Chain = ST->getChain(); 6852 SDValue Value = ST->getValue(); 6853 if (ISD::isNormalStore(ST) && ISD::isNormalLoad(Value.getNode()) && 6854 Value.hasOneUse() && 6855 Chain == SDValue(Value.getNode(), 1)) { 6856 LoadSDNode *LD = cast<LoadSDNode>(Value); 6857 EVT VT = LD->getMemoryVT(); 6858 if (!VT.isFloatingPoint() || 6859 VT != ST->getMemoryVT() || 6860 LD->isNonTemporal() || 6861 ST->isNonTemporal() || 6862 LD->getPointerInfo().getAddrSpace() != 0 || 6863 ST->getPointerInfo().getAddrSpace() != 0) 6864 return SDValue(); 6865 6866 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits()); 6867 if (!TLI.isOperationLegal(ISD::LOAD, IntVT) || 6868 !TLI.isOperationLegal(ISD::STORE, IntVT) || 6869 !TLI.isDesirableToTransformToIntegerOp(ISD::LOAD, VT) || 6870 !TLI.isDesirableToTransformToIntegerOp(ISD::STORE, VT)) 6871 return SDValue(); 6872 6873 unsigned LDAlign = LD->getAlignment(); 6874 unsigned STAlign = ST->getAlignment(); 6875 Type *IntVTTy = IntVT.getTypeForEVT(*DAG.getContext()); 6876 unsigned ABIAlign = TLI.getTargetData()->getABITypeAlignment(IntVTTy); 6877 if (LDAlign < ABIAlign || STAlign < ABIAlign) 6878 return SDValue(); 6879 6880 SDValue NewLD = DAG.getLoad(IntVT, Value.getDebugLoc(), 6881 LD->getChain(), LD->getBasePtr(), 6882 LD->getPointerInfo(), 6883 false, false, false, LDAlign); 6884 6885 SDValue NewST = DAG.getStore(NewLD.getValue(1), N->getDebugLoc(), 6886 NewLD, ST->getBasePtr(), 6887 ST->getPointerInfo(), 6888 false, false, STAlign); 6889 6890 AddToWorkList(NewLD.getNode()); 6891 AddToWorkList(NewST.getNode()); 6892 WorkListRemover DeadNodes(*this); 6893 DAG.ReplaceAllUsesOfValueWith(Value.getValue(1), NewLD.getValue(1), 6894 &DeadNodes); 6895 ++LdStFP2Int; 6896 return NewST; 6897 } 6898 6899 return SDValue(); 6900} 6901 6902SDValue DAGCombiner::visitSTORE(SDNode *N) { 6903 StoreSDNode *ST = cast<StoreSDNode>(N); 6904 SDValue Chain = ST->getChain(); 6905 SDValue Value = ST->getValue(); 6906 SDValue Ptr = ST->getBasePtr(); 6907 6908 // If this is a store of a bit convert, store the input value if the 6909 // resultant store does not need a higher alignment than the original. 6910 if (Value.getOpcode() == ISD::BITCAST && !ST->isTruncatingStore() && 6911 ST->isUnindexed()) { 6912 unsigned OrigAlign = ST->getAlignment(); 6913 EVT SVT = Value.getOperand(0).getValueType(); 6914 unsigned Align = TLI.getTargetData()-> 6915 getABITypeAlignment(SVT.getTypeForEVT(*DAG.getContext())); 6916 if (Align <= OrigAlign && 6917 ((!LegalOperations && !ST->isVolatile()) || 6918 TLI.isOperationLegalOrCustom(ISD::STORE, SVT))) 6919 return DAG.getStore(Chain, N->getDebugLoc(), Value.getOperand(0), 6920 Ptr, ST->getPointerInfo(), ST->isVolatile(), 6921 ST->isNonTemporal(), OrigAlign); 6922 } 6923 6924 // Turn 'store undef, Ptr' -> nothing. 6925 if (Value.getOpcode() == ISD::UNDEF && ST->isUnindexed()) 6926 return Chain; 6927 6928 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 6929 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) { 6930 // NOTE: If the original store is volatile, this transform must not increase 6931 // the number of stores. For example, on x86-32 an f64 can be stored in one 6932 // processor operation but an i64 (which is not legal) requires two. So the 6933 // transform should not be done in this case. 6934 if (Value.getOpcode() != ISD::TargetConstantFP) { 6935 SDValue Tmp; 6936 switch (CFP->getValueType(0).getSimpleVT().SimpleTy) { 6937 default: llvm_unreachable("Unknown FP type"); 6938 case MVT::f80: // We don't do this for these yet. 6939 case MVT::f128: 6940 case MVT::ppcf128: 6941 break; 6942 case MVT::f32: 6943 if ((isTypeLegal(MVT::i32) && !LegalOperations && !ST->isVolatile()) || 6944 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) { 6945 Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF(). 6946 bitcastToAPInt().getZExtValue(), MVT::i32); 6947 return DAG.getStore(Chain, N->getDebugLoc(), Tmp, 6948 Ptr, ST->getPointerInfo(), ST->isVolatile(), 6949 ST->isNonTemporal(), ST->getAlignment()); 6950 } 6951 break; 6952 case MVT::f64: 6953 if ((TLI.isTypeLegal(MVT::i64) && !LegalOperations && 6954 !ST->isVolatile()) || 6955 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i64)) { 6956 Tmp = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt(). 6957 getZExtValue(), MVT::i64); 6958 return DAG.getStore(Chain, N->getDebugLoc(), Tmp, 6959 Ptr, ST->getPointerInfo(), ST->isVolatile(), 6960 ST->isNonTemporal(), ST->getAlignment()); 6961 } 6962 6963 if (!ST->isVolatile() && 6964 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) { 6965 // Many FP stores are not made apparent until after legalize, e.g. for 6966 // argument passing. Since this is so common, custom legalize the 6967 // 64-bit integer store into two 32-bit stores. 6968 uint64_t Val = CFP->getValueAPF().bitcastToAPInt().getZExtValue(); 6969 SDValue Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32); 6970 SDValue Hi = DAG.getConstant(Val >> 32, MVT::i32); 6971 if (TLI.isBigEndian()) std::swap(Lo, Hi); 6972 6973 unsigned Alignment = ST->getAlignment(); 6974 bool isVolatile = ST->isVolatile(); 6975 bool isNonTemporal = ST->isNonTemporal(); 6976 6977 SDValue St0 = DAG.getStore(Chain, ST->getDebugLoc(), Lo, 6978 Ptr, ST->getPointerInfo(), 6979 isVolatile, isNonTemporal, 6980 ST->getAlignment()); 6981 Ptr = DAG.getNode(ISD::ADD, N->getDebugLoc(), Ptr.getValueType(), Ptr, 6982 DAG.getConstant(4, Ptr.getValueType())); 6983 Alignment = MinAlign(Alignment, 4U); 6984 SDValue St1 = DAG.getStore(Chain, ST->getDebugLoc(), Hi, 6985 Ptr, ST->getPointerInfo().getWithOffset(4), 6986 isVolatile, isNonTemporal, 6987 Alignment); 6988 return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, 6989 St0, St1); 6990 } 6991 6992 break; 6993 } 6994 } 6995 } 6996 6997 // Try to infer better alignment information than the store already has. 6998 if (OptLevel != CodeGenOpt::None && ST->isUnindexed()) { 6999 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) { 7000 if (Align > ST->getAlignment()) 7001 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value, 7002 Ptr, ST->getPointerInfo(), ST->getMemoryVT(), 7003 ST->isVolatile(), ST->isNonTemporal(), Align); 7004 } 7005 } 7006 7007 // Try transforming a pair floating point load / store ops to integer 7008 // load / store ops. 7009 SDValue NewST = TransformFPLoadStorePair(N); 7010 if (NewST.getNode()) 7011 return NewST; 7012 7013 if (CombinerAA) { 7014 // Walk up chain skipping non-aliasing memory nodes. 7015 SDValue BetterChain = FindBetterChain(N, Chain); 7016 7017 // If there is a better chain. 7018 if (Chain != BetterChain) { 7019 SDValue ReplStore; 7020 7021 // Replace the chain to avoid dependency. 7022 if (ST->isTruncatingStore()) { 7023 ReplStore = DAG.getTruncStore(BetterChain, N->getDebugLoc(), Value, Ptr, 7024 ST->getPointerInfo(), 7025 ST->getMemoryVT(), ST->isVolatile(), 7026 ST->isNonTemporal(), ST->getAlignment()); 7027 } else { 7028 ReplStore = DAG.getStore(BetterChain, N->getDebugLoc(), Value, Ptr, 7029 ST->getPointerInfo(), 7030 ST->isVolatile(), ST->isNonTemporal(), 7031 ST->getAlignment()); 7032 } 7033 7034 // Create token to keep both nodes around. 7035 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 7036 MVT::Other, Chain, ReplStore); 7037 7038 // Make sure the new and old chains are cleaned up. 7039 AddToWorkList(Token.getNode()); 7040 7041 // Don't add users to work list. 7042 return CombineTo(N, Token, false); 7043 } 7044 } 7045 7046 // Try transforming N to an indexed store. 7047 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 7048 return SDValue(N, 0); 7049 7050 // FIXME: is there such a thing as a truncating indexed store? 7051 if (ST->isTruncatingStore() && ST->isUnindexed() && 7052 Value.getValueType().isInteger()) { 7053 // See if we can simplify the input to this truncstore with knowledge that 7054 // only the low bits are being used. For example: 7055 // "truncstore (or (shl x, 8), y), i8" -> "truncstore y, i8" 7056 SDValue Shorter = 7057 GetDemandedBits(Value, 7058 APInt::getLowBitsSet( 7059 Value.getValueType().getScalarType().getSizeInBits(), 7060 ST->getMemoryVT().getScalarType().getSizeInBits())); 7061 AddToWorkList(Value.getNode()); 7062 if (Shorter.getNode()) 7063 return DAG.getTruncStore(Chain, N->getDebugLoc(), Shorter, 7064 Ptr, ST->getPointerInfo(), ST->getMemoryVT(), 7065 ST->isVolatile(), ST->isNonTemporal(), 7066 ST->getAlignment()); 7067 7068 // Otherwise, see if we can simplify the operation with 7069 // SimplifyDemandedBits, which only works if the value has a single use. 7070 if (SimplifyDemandedBits(Value, 7071 APInt::getLowBitsSet( 7072 Value.getValueType().getScalarType().getSizeInBits(), 7073 ST->getMemoryVT().getScalarType().getSizeInBits()))) 7074 return SDValue(N, 0); 7075 } 7076 7077 // If this is a load followed by a store to the same location, then the store 7078 // is dead/noop. 7079 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Value)) { 7080 if (Ld->getBasePtr() == Ptr && ST->getMemoryVT() == Ld->getMemoryVT() && 7081 ST->isUnindexed() && !ST->isVolatile() && 7082 // There can't be any side effects between the load and store, such as 7083 // a call or store. 7084 Chain.reachesChainWithoutSideEffects(SDValue(Ld, 1))) { 7085 // The store is dead, remove it. 7086 return Chain; 7087 } 7088 } 7089 7090 // If this is an FP_ROUND or TRUNC followed by a store, fold this into a 7091 // truncating store. We can do this even if this is already a truncstore. 7092 if ((Value.getOpcode() == ISD::FP_ROUND || Value.getOpcode() == ISD::TRUNCATE) 7093 && Value.getNode()->hasOneUse() && ST->isUnindexed() && 7094 TLI.isTruncStoreLegal(Value.getOperand(0).getValueType(), 7095 ST->getMemoryVT())) { 7096 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value.getOperand(0), 7097 Ptr, ST->getPointerInfo(), ST->getMemoryVT(), 7098 ST->isVolatile(), ST->isNonTemporal(), 7099 ST->getAlignment()); 7100 } 7101 7102 return ReduceLoadOpStoreWidth(N); 7103} 7104 7105SDValue DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) { 7106 SDValue InVec = N->getOperand(0); 7107 SDValue InVal = N->getOperand(1); 7108 SDValue EltNo = N->getOperand(2); 7109 DebugLoc dl = N->getDebugLoc(); 7110 7111 // If the inserted element is an UNDEF, just use the input vector. 7112 if (InVal.getOpcode() == ISD::UNDEF) 7113 return InVec; 7114 7115 EVT VT = InVec.getValueType(); 7116 7117 // If we can't generate a legal BUILD_VECTOR, exit 7118 if (LegalOperations && !TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) 7119 return SDValue(); 7120 7121 // Check that we know which element is being inserted 7122 if (!isa<ConstantSDNode>(EltNo)) 7123 return SDValue(); 7124 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 7125 7126 // Check that the operand is a BUILD_VECTOR (or UNDEF, which can essentially 7127 // be converted to a BUILD_VECTOR). Fill in the Ops vector with the 7128 // vector elements. 7129 SmallVector<SDValue, 8> Ops; 7130 if (InVec.getOpcode() == ISD::BUILD_VECTOR) { 7131 Ops.append(InVec.getNode()->op_begin(), 7132 InVec.getNode()->op_end()); 7133 } else if (InVec.getOpcode() == ISD::UNDEF) { 7134 unsigned NElts = VT.getVectorNumElements(); 7135 Ops.append(NElts, DAG.getUNDEF(InVal.getValueType())); 7136 } else { 7137 return SDValue(); 7138 } 7139 7140 // Insert the element 7141 if (Elt < Ops.size()) { 7142 // All the operands of BUILD_VECTOR must have the same type; 7143 // we enforce that here. 7144 EVT OpVT = Ops[0].getValueType(); 7145 if (InVal.getValueType() != OpVT) 7146 InVal = OpVT.bitsGT(InVal.getValueType()) ? 7147 DAG.getNode(ISD::ANY_EXTEND, dl, OpVT, InVal) : 7148 DAG.getNode(ISD::TRUNCATE, dl, OpVT, InVal); 7149 Ops[Elt] = InVal; 7150 } 7151 7152 // Return the new vector 7153 return DAG.getNode(ISD::BUILD_VECTOR, dl, 7154 VT, &Ops[0], Ops.size()); 7155} 7156 7157SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) { 7158 // (vextract (scalar_to_vector val, 0) -> val 7159 SDValue InVec = N->getOperand(0); 7160 EVT VT = InVec.getValueType(); 7161 EVT NVT = N->getValueType(0); 7162 7163 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) { 7164 // Check if the result type doesn't match the inserted element type. A 7165 // SCALAR_TO_VECTOR may truncate the inserted element and the 7166 // EXTRACT_VECTOR_ELT may widen the extracted vector. 7167 SDValue InOp = InVec.getOperand(0); 7168 if (InOp.getValueType() != NVT) { 7169 assert(InOp.getValueType().isInteger() && NVT.isInteger()); 7170 return DAG.getSExtOrTrunc(InOp, InVec.getDebugLoc(), NVT); 7171 } 7172 return InOp; 7173 } 7174 7175 SDValue EltNo = N->getOperand(1); 7176 bool ConstEltNo = isa<ConstantSDNode>(EltNo); 7177 7178 // Transform: (EXTRACT_VECTOR_ELT( VECTOR_SHUFFLE )) -> EXTRACT_VECTOR_ELT. 7179 // We only perform this optimization before the op legalization phase because 7180 // we may introduce new vector instructions which are not backed by TD patterns. 7181 // For example on AVX, extracting elements from a wide vector without using 7182 // extract_subvector. 7183 if (InVec.getOpcode() == ISD::VECTOR_SHUFFLE 7184 && ConstEltNo && !LegalOperations) { 7185 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 7186 int NumElem = VT.getVectorNumElements(); 7187 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(InVec); 7188 // Find the new index to extract from. 7189 int OrigElt = SVOp->getMaskElt(Elt); 7190 7191 // Extracting an undef index is undef. 7192 if (OrigElt == -1) 7193 return DAG.getUNDEF(NVT); 7194 7195 // Select the right vector half to extract from. 7196 if (OrigElt < NumElem) { 7197 InVec = InVec->getOperand(0); 7198 } else { 7199 InVec = InVec->getOperand(1); 7200 OrigElt -= NumElem; 7201 } 7202 7203 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, N->getDebugLoc(), NVT, 7204 InVec, DAG.getConstant(OrigElt, MVT::i32)); 7205 } 7206 7207 // Perform only after legalization to ensure build_vector / vector_shuffle 7208 // optimizations have already been done. 7209 if (!LegalOperations) return SDValue(); 7210 7211 // (vextract (v4f32 load $addr), c) -> (f32 load $addr+c*size) 7212 // (vextract (v4f32 s2v (f32 load $addr)), c) -> (f32 load $addr+c*size) 7213 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), 0) -> (f32 load $addr) 7214 7215 if (ConstEltNo) { 7216 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 7217 bool NewLoad = false; 7218 bool BCNumEltsChanged = false; 7219 EVT ExtVT = VT.getVectorElementType(); 7220 EVT LVT = ExtVT; 7221 7222 // If the result of load has to be truncated, then it's not necessarily 7223 // profitable. 7224 if (NVT.bitsLT(LVT) && !TLI.isTruncateFree(LVT, NVT)) 7225 return SDValue(); 7226 7227 if (InVec.getOpcode() == ISD::BITCAST) { 7228 // Don't duplicate a load with other uses. 7229 if (!InVec.hasOneUse()) 7230 return SDValue(); 7231 7232 EVT BCVT = InVec.getOperand(0).getValueType(); 7233 if (!BCVT.isVector() || ExtVT.bitsGT(BCVT.getVectorElementType())) 7234 return SDValue(); 7235 if (VT.getVectorNumElements() != BCVT.getVectorNumElements()) 7236 BCNumEltsChanged = true; 7237 InVec = InVec.getOperand(0); 7238 ExtVT = BCVT.getVectorElementType(); 7239 NewLoad = true; 7240 } 7241 7242 LoadSDNode *LN0 = NULL; 7243 const ShuffleVectorSDNode *SVN = NULL; 7244 if (ISD::isNormalLoad(InVec.getNode())) { 7245 LN0 = cast<LoadSDNode>(InVec); 7246 } else if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR && 7247 InVec.getOperand(0).getValueType() == ExtVT && 7248 ISD::isNormalLoad(InVec.getOperand(0).getNode())) { 7249 // Don't duplicate a load with other uses. 7250 if (!InVec.hasOneUse()) 7251 return SDValue(); 7252 7253 LN0 = cast<LoadSDNode>(InVec.getOperand(0)); 7254 } else if ((SVN = dyn_cast<ShuffleVectorSDNode>(InVec))) { 7255 // (vextract (vector_shuffle (load $addr), v2, <1, u, u, u>), 1) 7256 // => 7257 // (load $addr+1*size) 7258 7259 // Don't duplicate a load with other uses. 7260 if (!InVec.hasOneUse()) 7261 return SDValue(); 7262 7263 // If the bit convert changed the number of elements, it is unsafe 7264 // to examine the mask. 7265 if (BCNumEltsChanged) 7266 return SDValue(); 7267 7268 // Select the input vector, guarding against out of range extract vector. 7269 unsigned NumElems = VT.getVectorNumElements(); 7270 int Idx = (Elt > (int)NumElems) ? -1 : SVN->getMaskElt(Elt); 7271 InVec = (Idx < (int)NumElems) ? InVec.getOperand(0) : InVec.getOperand(1); 7272 7273 if (InVec.getOpcode() == ISD::BITCAST) { 7274 // Don't duplicate a load with other uses. 7275 if (!InVec.hasOneUse()) 7276 return SDValue(); 7277 7278 InVec = InVec.getOperand(0); 7279 } 7280 if (ISD::isNormalLoad(InVec.getNode())) { 7281 LN0 = cast<LoadSDNode>(InVec); 7282 Elt = (Idx < (int)NumElems) ? Idx : Idx - (int)NumElems; 7283 } 7284 } 7285 7286 // Make sure we found a non-volatile load and the extractelement is 7287 // the only use. 7288 if (!LN0 || !LN0->hasNUsesOfValue(1,0) || LN0->isVolatile()) 7289 return SDValue(); 7290 7291 // If Idx was -1 above, Elt is going to be -1, so just return undef. 7292 if (Elt == -1) 7293 return DAG.getUNDEF(LVT); 7294 7295 unsigned Align = LN0->getAlignment(); 7296 if (NewLoad) { 7297 // Check the resultant load doesn't need a higher alignment than the 7298 // original load. 7299 unsigned NewAlign = 7300 TLI.getTargetData() 7301 ->getABITypeAlignment(LVT.getTypeForEVT(*DAG.getContext())); 7302 7303 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, LVT)) 7304 return SDValue(); 7305 7306 Align = NewAlign; 7307 } 7308 7309 SDValue NewPtr = LN0->getBasePtr(); 7310 unsigned PtrOff = 0; 7311 7312 if (Elt) { 7313 PtrOff = LVT.getSizeInBits() * Elt / 8; 7314 EVT PtrType = NewPtr.getValueType(); 7315 if (TLI.isBigEndian()) 7316 PtrOff = VT.getSizeInBits() / 8 - PtrOff; 7317 NewPtr = DAG.getNode(ISD::ADD, N->getDebugLoc(), PtrType, NewPtr, 7318 DAG.getConstant(PtrOff, PtrType)); 7319 } 7320 7321 // The replacement we need to do here is a little tricky: we need to 7322 // replace an extractelement of a load with a load. 7323 // Use ReplaceAllUsesOfValuesWith to do the replacement. 7324 // Note that this replacement assumes that the extractvalue is the only 7325 // use of the load; that's okay because we don't want to perform this 7326 // transformation in other cases anyway. 7327 SDValue Load; 7328 SDValue Chain; 7329 if (NVT.bitsGT(LVT)) { 7330 // If the result type of vextract is wider than the load, then issue an 7331 // extending load instead. 7332 ISD::LoadExtType ExtType = TLI.isLoadExtLegal(ISD::ZEXTLOAD, LVT) 7333 ? ISD::ZEXTLOAD : ISD::EXTLOAD; 7334 Load = DAG.getExtLoad(ExtType, N->getDebugLoc(), NVT, LN0->getChain(), 7335 NewPtr, LN0->getPointerInfo().getWithOffset(PtrOff), 7336 LVT, LN0->isVolatile(), LN0->isNonTemporal(),Align); 7337 Chain = Load.getValue(1); 7338 } else { 7339 Load = DAG.getLoad(LVT, N->getDebugLoc(), LN0->getChain(), NewPtr, 7340 LN0->getPointerInfo().getWithOffset(PtrOff), 7341 LN0->isVolatile(), LN0->isNonTemporal(), 7342 LN0->isInvariant(), Align); 7343 Chain = Load.getValue(1); 7344 if (NVT.bitsLT(LVT)) 7345 Load = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), NVT, Load); 7346 else 7347 Load = DAG.getNode(ISD::BITCAST, N->getDebugLoc(), NVT, Load); 7348 } 7349 WorkListRemover DeadNodes(*this); 7350 SDValue From[] = { SDValue(N, 0), SDValue(LN0,1) }; 7351 SDValue To[] = { Load, Chain }; 7352 DAG.ReplaceAllUsesOfValuesWith(From, To, 2, &DeadNodes); 7353 // Since we're explcitly calling ReplaceAllUses, add the new node to the 7354 // worklist explicitly as well. 7355 AddToWorkList(Load.getNode()); 7356 AddUsersToWorkList(Load.getNode()); // Add users too 7357 // Make sure to revisit this node to clean it up; it will usually be dead. 7358 AddToWorkList(N); 7359 return SDValue(N, 0); 7360 } 7361 7362 return SDValue(); 7363} 7364 7365SDValue DAGCombiner::visitBUILD_VECTOR(SDNode *N) { 7366 unsigned NumInScalars = N->getNumOperands(); 7367 DebugLoc dl = N->getDebugLoc(); 7368 EVT VT = N->getValueType(0); 7369 // Check to see if this is a BUILD_VECTOR of a bunch of values 7370 // which come from any_extend or zero_extend nodes. If so, we can create 7371 // a new BUILD_VECTOR using bit-casts which may enable other BUILD_VECTOR 7372 // optimizations. We do not handle sign-extend because we can't fill the sign 7373 // using shuffles. 7374 EVT SourceType = MVT::Other; 7375 bool AllAnyExt = true; 7376 bool AllUndef = true; 7377 for (unsigned i = 0; i != NumInScalars; ++i) { 7378 SDValue In = N->getOperand(i); 7379 // Ignore undef inputs. 7380 if (In.getOpcode() == ISD::UNDEF) continue; 7381 AllUndef = false; 7382 7383 bool AnyExt = In.getOpcode() == ISD::ANY_EXTEND; 7384 bool ZeroExt = In.getOpcode() == ISD::ZERO_EXTEND; 7385 7386 // Abort if the element is not an extension. 7387 if (!ZeroExt && !AnyExt) { 7388 SourceType = MVT::Other; 7389 break; 7390 } 7391 7392 // The input is a ZeroExt or AnyExt. Check the original type. 7393 EVT InTy = In.getOperand(0).getValueType(); 7394 7395 // Check that all of the widened source types are the same. 7396 if (SourceType == MVT::Other) 7397 // First time. 7398 SourceType = InTy; 7399 else if (InTy != SourceType) { 7400 // Multiple income types. Abort. 7401 SourceType = MVT::Other; 7402 break; 7403 } 7404 7405 // Check if all of the extends are ANY_EXTENDs. 7406 AllAnyExt &= AnyExt; 7407 } 7408 7409 if (AllUndef) 7410 return DAG.getUNDEF(VT); 7411 7412 // In order to have valid types, all of the inputs must be extended from the 7413 // same source type and all of the inputs must be any or zero extend. 7414 // Scalar sizes must be a power of two. 7415 EVT OutScalarTy = N->getValueType(0).getScalarType(); 7416 bool ValidTypes = SourceType != MVT::Other && 7417 isPowerOf2_32(OutScalarTy.getSizeInBits()) && 7418 isPowerOf2_32(SourceType.getSizeInBits()); 7419 7420 // We perform this optimization post type-legalization because 7421 // the type-legalizer often scalarizes integer-promoted vectors. 7422 // Performing this optimization before may create bit-casts which 7423 // will be type-legalized to complex code sequences. 7424 // We perform this optimization only before the operation legalizer because we 7425 // may introduce illegal operations. 7426 // Create a new simpler BUILD_VECTOR sequence which other optimizations can 7427 // turn into a single shuffle instruction. 7428 if ((Level == AfterLegalizeVectorOps || Level == AfterLegalizeTypes) && 7429 ValidTypes) { 7430 bool isLE = TLI.isLittleEndian(); 7431 unsigned ElemRatio = OutScalarTy.getSizeInBits()/SourceType.getSizeInBits(); 7432 assert(ElemRatio > 1 && "Invalid element size ratio"); 7433 SDValue Filler = AllAnyExt ? DAG.getUNDEF(SourceType): 7434 DAG.getConstant(0, SourceType); 7435 7436 unsigned NewBVElems = ElemRatio * N->getValueType(0).getVectorNumElements(); 7437 SmallVector<SDValue, 8> Ops(NewBVElems, Filler); 7438 7439 // Populate the new build_vector 7440 for (unsigned i=0; i < N->getNumOperands(); ++i) { 7441 SDValue Cast = N->getOperand(i); 7442 assert((Cast.getOpcode() == ISD::ANY_EXTEND || 7443 Cast.getOpcode() == ISD::ZERO_EXTEND || 7444 Cast.getOpcode() == ISD::UNDEF) && "Invalid cast opcode"); 7445 SDValue In; 7446 if (Cast.getOpcode() == ISD::UNDEF) 7447 In = DAG.getUNDEF(SourceType); 7448 else 7449 In = Cast->getOperand(0); 7450 unsigned Index = isLE ? (i * ElemRatio) : 7451 (i * ElemRatio + (ElemRatio - 1)); 7452 7453 assert(Index < Ops.size() && "Invalid index"); 7454 Ops[Index] = In; 7455 } 7456 7457 // The type of the new BUILD_VECTOR node. 7458 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), SourceType, NewBVElems); 7459 assert(VecVT.getSizeInBits() == N->getValueType(0).getSizeInBits() && 7460 "Invalid vector size"); 7461 // Check if the new vector type is legal. 7462 if (!isTypeLegal(VecVT)) return SDValue(); 7463 7464 // Make the new BUILD_VECTOR. 7465 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 7466 VecVT, &Ops[0], Ops.size()); 7467 7468 // The new BUILD_VECTOR node has the potential to be further optimized. 7469 AddToWorkList(BV.getNode()); 7470 // Bitcast to the desired type. 7471 return DAG.getNode(ISD::BITCAST, dl, N->getValueType(0), BV); 7472 } 7473 7474 // Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT 7475 // operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from 7476 // at most two distinct vectors, turn this into a shuffle node. 7477 7478 // May only combine to shuffle after legalize if shuffle is legal. 7479 if (LegalOperations && 7480 !TLI.isOperationLegalOrCustom(ISD::VECTOR_SHUFFLE, VT)) 7481 return SDValue(); 7482 7483 SDValue VecIn1, VecIn2; 7484 for (unsigned i = 0; i != NumInScalars; ++i) { 7485 // Ignore undef inputs. 7486 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 7487 7488 // If this input is something other than a EXTRACT_VECTOR_ELT with a 7489 // constant index, bail out. 7490 if (N->getOperand(i).getOpcode() != ISD::EXTRACT_VECTOR_ELT || 7491 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) { 7492 VecIn1 = VecIn2 = SDValue(0, 0); 7493 break; 7494 } 7495 7496 // We allow up to two distinct input vectors. 7497 SDValue ExtractedFromVec = N->getOperand(i).getOperand(0); 7498 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2) 7499 continue; 7500 7501 if (VecIn1.getNode() == 0) { 7502 VecIn1 = ExtractedFromVec; 7503 } else if (VecIn2.getNode() == 0) { 7504 VecIn2 = ExtractedFromVec; 7505 } else { 7506 // Too many inputs. 7507 VecIn1 = VecIn2 = SDValue(0, 0); 7508 break; 7509 } 7510 } 7511 7512 // If everything is good, we can make a shuffle operation. 7513 if (VecIn1.getNode()) { 7514 SmallVector<int, 8> Mask; 7515 for (unsigned i = 0; i != NumInScalars; ++i) { 7516 if (N->getOperand(i).getOpcode() == ISD::UNDEF) { 7517 Mask.push_back(-1); 7518 continue; 7519 } 7520 7521 // If extracting from the first vector, just use the index directly. 7522 SDValue Extract = N->getOperand(i); 7523 SDValue ExtVal = Extract.getOperand(1); 7524 if (Extract.getOperand(0) == VecIn1) { 7525 unsigned ExtIndex = cast<ConstantSDNode>(ExtVal)->getZExtValue(); 7526 if (ExtIndex > VT.getVectorNumElements()) 7527 return SDValue(); 7528 7529 Mask.push_back(ExtIndex); 7530 continue; 7531 } 7532 7533 // Otherwise, use InIdx + VecSize 7534 unsigned Idx = cast<ConstantSDNode>(ExtVal)->getZExtValue(); 7535 Mask.push_back(Idx+NumInScalars); 7536 } 7537 7538 // We can't generate a shuffle node with mismatched input and output types. 7539 // Attempt to transform a single input vector to the correct type. 7540 if ((VT != VecIn1.getValueType())) { 7541 // We don't support shuffeling between TWO values of different types. 7542 if (VecIn2.getNode() != 0) 7543 return SDValue(); 7544 7545 // We only support widening of vectors which are half the size of the 7546 // output registers. For example XMM->YMM widening on X86 with AVX. 7547 if (VecIn1.getValueType().getSizeInBits()*2 != VT.getSizeInBits()) 7548 return SDValue(); 7549 7550 // Widen the input vector by adding undef values. 7551 VecIn1 = DAG.getNode(ISD::CONCAT_VECTORS, N->getDebugLoc(), VT, 7552 VecIn1, DAG.getUNDEF(VecIn1.getValueType())); 7553 } 7554 7555 // If VecIn2 is unused then change it to undef. 7556 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT); 7557 7558 // Check that we were able to transform all incoming values to the same type. 7559 if (VecIn2.getValueType() != VecIn1.getValueType() || 7560 VecIn1.getValueType() != VT) 7561 return SDValue(); 7562 7563 // Only type-legal BUILD_VECTOR nodes are converted to shuffle nodes. 7564 if (!isTypeLegal(VT)) 7565 return SDValue(); 7566 7567 // Return the new VECTOR_SHUFFLE node. 7568 SDValue Ops[2]; 7569 Ops[0] = VecIn1; 7570 Ops[1] = VecIn2; 7571 return DAG.getVectorShuffle(VT, N->getDebugLoc(), Ops[0], Ops[1], &Mask[0]); 7572 } 7573 7574 return SDValue(); 7575} 7576 7577SDValue DAGCombiner::visitCONCAT_VECTORS(SDNode *N) { 7578 // TODO: Check to see if this is a CONCAT_VECTORS of a bunch of 7579 // EXTRACT_SUBVECTOR operations. If so, and if the EXTRACT_SUBVECTOR vector 7580 // inputs come from at most two distinct vectors, turn this into a shuffle 7581 // node. 7582 7583 // If we only have one input vector, we don't need to do any concatenation. 7584 if (N->getNumOperands() == 1) 7585 return N->getOperand(0); 7586 7587 return SDValue(); 7588} 7589 7590SDValue DAGCombiner::visitEXTRACT_SUBVECTOR(SDNode* N) { 7591 EVT NVT = N->getValueType(0); 7592 SDValue V = N->getOperand(0); 7593 7594 if (V->getOpcode() == ISD::INSERT_SUBVECTOR) { 7595 // Handle only simple case where vector being inserted and vector 7596 // being extracted are of same type, and are half size of larger vectors. 7597 EVT BigVT = V->getOperand(0).getValueType(); 7598 EVT SmallVT = V->getOperand(1).getValueType(); 7599 if (NVT != SmallVT || NVT.getSizeInBits()*2 != BigVT.getSizeInBits()) 7600 return SDValue(); 7601 7602 // Only handle cases where both indexes are constants with the same type. 7603 ConstantSDNode *InsIdx = dyn_cast<ConstantSDNode>(N->getOperand(1)); 7604 ConstantSDNode *ExtIdx = dyn_cast<ConstantSDNode>(V->getOperand(2)); 7605 7606 if (InsIdx && ExtIdx && 7607 InsIdx->getValueType(0).getSizeInBits() <= 64 && 7608 ExtIdx->getValueType(0).getSizeInBits() <= 64) { 7609 // Combine: 7610 // (extract_subvec (insert_subvec V1, V2, InsIdx), ExtIdx) 7611 // Into: 7612 // indices are equal => V1 7613 // otherwise => (extract_subvec V1, ExtIdx) 7614 if (InsIdx->getZExtValue() == ExtIdx->getZExtValue()) 7615 return V->getOperand(1); 7616 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, N->getDebugLoc(), NVT, 7617 V->getOperand(0), N->getOperand(1)); 7618 } 7619 } 7620 7621 return SDValue(); 7622} 7623 7624SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) { 7625 EVT VT = N->getValueType(0); 7626 unsigned NumElts = VT.getVectorNumElements(); 7627 7628 SDValue N0 = N->getOperand(0); 7629 SDValue N1 = N->getOperand(1); 7630 7631 assert(N0.getValueType().getVectorNumElements() == NumElts && 7632 "Vector shuffle must be normalized in DAG"); 7633 7634 // Canonicalize shuffle undef, undef -> undef 7635 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF) 7636 return DAG.getUNDEF(VT); 7637 7638 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N); 7639 7640 // Canonicalize shuffle v, v -> v, undef 7641 if (N0 == N1) { 7642 SmallVector<int, 8> NewMask; 7643 for (unsigned i = 0; i != NumElts; ++i) { 7644 int Idx = SVN->getMaskElt(i); 7645 if (Idx >= (int)NumElts) Idx -= NumElts; 7646 NewMask.push_back(Idx); 7647 } 7648 return DAG.getVectorShuffle(VT, N->getDebugLoc(), N0, DAG.getUNDEF(VT), 7649 &NewMask[0]); 7650 } 7651 7652 // Canonicalize shuffle undef, v -> v, undef. Commute the shuffle mask. 7653 if (N0.getOpcode() == ISD::UNDEF) { 7654 SmallVector<int, 8> NewMask; 7655 for (unsigned i = 0; i != NumElts; ++i) { 7656 int Idx = SVN->getMaskElt(i); 7657 if (Idx < 0) 7658 NewMask.push_back(Idx); 7659 else if (Idx < (int)NumElts) 7660 NewMask.push_back(Idx + NumElts); 7661 else 7662 NewMask.push_back(Idx - NumElts); 7663 } 7664 return DAG.getVectorShuffle(VT, N->getDebugLoc(), N1, DAG.getUNDEF(VT), 7665 &NewMask[0]); 7666 } 7667 7668 // Remove references to rhs if it is undef 7669 if (N1.getOpcode() == ISD::UNDEF) { 7670 bool Changed = false; 7671 SmallVector<int, 8> NewMask; 7672 for (unsigned i = 0; i != NumElts; ++i) { 7673 int Idx = SVN->getMaskElt(i); 7674 if (Idx >= (int)NumElts) { 7675 Idx = -1; 7676 Changed = true; 7677 } 7678 NewMask.push_back(Idx); 7679 } 7680 if (Changed) 7681 return DAG.getVectorShuffle(VT, N->getDebugLoc(), N0, N1, &NewMask[0]); 7682 } 7683 7684 // If it is a splat, check if the argument vector is another splat or a 7685 // build_vector with all scalar elements the same. 7686 if (SVN->isSplat() && SVN->getSplatIndex() < (int)NumElts) { 7687 SDNode *V = N0.getNode(); 7688 7689 // If this is a bit convert that changes the element type of the vector but 7690 // not the number of vector elements, look through it. Be careful not to 7691 // look though conversions that change things like v4f32 to v2f64. 7692 if (V->getOpcode() == ISD::BITCAST) { 7693 SDValue ConvInput = V->getOperand(0); 7694 if (ConvInput.getValueType().isVector() && 7695 ConvInput.getValueType().getVectorNumElements() == NumElts) 7696 V = ConvInput.getNode(); 7697 } 7698 7699 if (V->getOpcode() == ISD::BUILD_VECTOR) { 7700 assert(V->getNumOperands() == NumElts && 7701 "BUILD_VECTOR has wrong number of operands"); 7702 SDValue Base; 7703 bool AllSame = true; 7704 for (unsigned i = 0; i != NumElts; ++i) { 7705 if (V->getOperand(i).getOpcode() != ISD::UNDEF) { 7706 Base = V->getOperand(i); 7707 break; 7708 } 7709 } 7710 // Splat of <u, u, u, u>, return <u, u, u, u> 7711 if (!Base.getNode()) 7712 return N0; 7713 for (unsigned i = 0; i != NumElts; ++i) { 7714 if (V->getOperand(i) != Base) { 7715 AllSame = false; 7716 break; 7717 } 7718 } 7719 // Splat of <x, x, x, x>, return <x, x, x, x> 7720 if (AllSame) 7721 return N0; 7722 } 7723 } 7724 return SDValue(); 7725} 7726 7727SDValue DAGCombiner::visitMEMBARRIER(SDNode* N) { 7728 if (!TLI.getShouldFoldAtomicFences()) 7729 return SDValue(); 7730 7731 SDValue atomic = N->getOperand(0); 7732 switch (atomic.getOpcode()) { 7733 case ISD::ATOMIC_CMP_SWAP: 7734 case ISD::ATOMIC_SWAP: 7735 case ISD::ATOMIC_LOAD_ADD: 7736 case ISD::ATOMIC_LOAD_SUB: 7737 case ISD::ATOMIC_LOAD_AND: 7738 case ISD::ATOMIC_LOAD_OR: 7739 case ISD::ATOMIC_LOAD_XOR: 7740 case ISD::ATOMIC_LOAD_NAND: 7741 case ISD::ATOMIC_LOAD_MIN: 7742 case ISD::ATOMIC_LOAD_MAX: 7743 case ISD::ATOMIC_LOAD_UMIN: 7744 case ISD::ATOMIC_LOAD_UMAX: 7745 break; 7746 default: 7747 return SDValue(); 7748 } 7749 7750 SDValue fence = atomic.getOperand(0); 7751 if (fence.getOpcode() != ISD::MEMBARRIER) 7752 return SDValue(); 7753 7754 switch (atomic.getOpcode()) { 7755 case ISD::ATOMIC_CMP_SWAP: 7756 return SDValue(DAG.UpdateNodeOperands(atomic.getNode(), 7757 fence.getOperand(0), 7758 atomic.getOperand(1), atomic.getOperand(2), 7759 atomic.getOperand(3)), atomic.getResNo()); 7760 case ISD::ATOMIC_SWAP: 7761 case ISD::ATOMIC_LOAD_ADD: 7762 case ISD::ATOMIC_LOAD_SUB: 7763 case ISD::ATOMIC_LOAD_AND: 7764 case ISD::ATOMIC_LOAD_OR: 7765 case ISD::ATOMIC_LOAD_XOR: 7766 case ISD::ATOMIC_LOAD_NAND: 7767 case ISD::ATOMIC_LOAD_MIN: 7768 case ISD::ATOMIC_LOAD_MAX: 7769 case ISD::ATOMIC_LOAD_UMIN: 7770 case ISD::ATOMIC_LOAD_UMAX: 7771 return SDValue(DAG.UpdateNodeOperands(atomic.getNode(), 7772 fence.getOperand(0), 7773 atomic.getOperand(1), atomic.getOperand(2)), 7774 atomic.getResNo()); 7775 default: 7776 return SDValue(); 7777 } 7778} 7779 7780/// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform 7781/// an AND to a vector_shuffle with the destination vector and a zero vector. 7782/// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==> 7783/// vector_shuffle V, Zero, <0, 4, 2, 4> 7784SDValue DAGCombiner::XformToShuffleWithZero(SDNode *N) { 7785 EVT VT = N->getValueType(0); 7786 DebugLoc dl = N->getDebugLoc(); 7787 SDValue LHS = N->getOperand(0); 7788 SDValue RHS = N->getOperand(1); 7789 if (N->getOpcode() == ISD::AND) { 7790 if (RHS.getOpcode() == ISD::BITCAST) 7791 RHS = RHS.getOperand(0); 7792 if (RHS.getOpcode() == ISD::BUILD_VECTOR) { 7793 SmallVector<int, 8> Indices; 7794 unsigned NumElts = RHS.getNumOperands(); 7795 for (unsigned i = 0; i != NumElts; ++i) { 7796 SDValue Elt = RHS.getOperand(i); 7797 if (!isa<ConstantSDNode>(Elt)) 7798 return SDValue(); 7799 else if (cast<ConstantSDNode>(Elt)->isAllOnesValue()) 7800 Indices.push_back(i); 7801 else if (cast<ConstantSDNode>(Elt)->isNullValue()) 7802 Indices.push_back(NumElts); 7803 else 7804 return SDValue(); 7805 } 7806 7807 // Let's see if the target supports this vector_shuffle. 7808 EVT RVT = RHS.getValueType(); 7809 if (!TLI.isVectorClearMaskLegal(Indices, RVT)) 7810 return SDValue(); 7811 7812 // Return the new VECTOR_SHUFFLE node. 7813 EVT EltVT = RVT.getVectorElementType(); 7814 SmallVector<SDValue,8> ZeroOps(RVT.getVectorNumElements(), 7815 DAG.getConstant(0, EltVT)); 7816 SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 7817 RVT, &ZeroOps[0], ZeroOps.size()); 7818 LHS = DAG.getNode(ISD::BITCAST, dl, RVT, LHS); 7819 SDValue Shuf = DAG.getVectorShuffle(RVT, dl, LHS, Zero, &Indices[0]); 7820 return DAG.getNode(ISD::BITCAST, dl, VT, Shuf); 7821 } 7822 } 7823 7824 return SDValue(); 7825} 7826 7827/// SimplifyVBinOp - Visit a binary vector operation, like ADD. 7828SDValue DAGCombiner::SimplifyVBinOp(SDNode *N) { 7829 // After legalize, the target may be depending on adds and other 7830 // binary ops to provide legal ways to construct constants or other 7831 // things. Simplifying them may result in a loss of legality. 7832 if (LegalOperations) return SDValue(); 7833 7834 assert(N->getValueType(0).isVector() && 7835 "SimplifyVBinOp only works on vectors!"); 7836 7837 SDValue LHS = N->getOperand(0); 7838 SDValue RHS = N->getOperand(1); 7839 SDValue Shuffle = XformToShuffleWithZero(N); 7840 if (Shuffle.getNode()) return Shuffle; 7841 7842 // If the LHS and RHS are BUILD_VECTOR nodes, see if we can constant fold 7843 // this operation. 7844 if (LHS.getOpcode() == ISD::BUILD_VECTOR && 7845 RHS.getOpcode() == ISD::BUILD_VECTOR) { 7846 SmallVector<SDValue, 8> Ops; 7847 for (unsigned i = 0, e = LHS.getNumOperands(); i != e; ++i) { 7848 SDValue LHSOp = LHS.getOperand(i); 7849 SDValue RHSOp = RHS.getOperand(i); 7850 // If these two elements can't be folded, bail out. 7851 if ((LHSOp.getOpcode() != ISD::UNDEF && 7852 LHSOp.getOpcode() != ISD::Constant && 7853 LHSOp.getOpcode() != ISD::ConstantFP) || 7854 (RHSOp.getOpcode() != ISD::UNDEF && 7855 RHSOp.getOpcode() != ISD::Constant && 7856 RHSOp.getOpcode() != ISD::ConstantFP)) 7857 break; 7858 7859 // Can't fold divide by zero. 7860 if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV || 7861 N->getOpcode() == ISD::FDIV) { 7862 if ((RHSOp.getOpcode() == ISD::Constant && 7863 cast<ConstantSDNode>(RHSOp.getNode())->isNullValue()) || 7864 (RHSOp.getOpcode() == ISD::ConstantFP && 7865 cast<ConstantFPSDNode>(RHSOp.getNode())->getValueAPF().isZero())) 7866 break; 7867 } 7868 7869 EVT VT = LHSOp.getValueType(); 7870 EVT RVT = RHSOp.getValueType(); 7871 if (RVT != VT) { 7872 // Integer BUILD_VECTOR operands may have types larger than the element 7873 // size (e.g., when the element type is not legal). Prior to type 7874 // legalization, the types may not match between the two BUILD_VECTORS. 7875 // Truncate one of the operands to make them match. 7876 if (RVT.getSizeInBits() > VT.getSizeInBits()) { 7877 RHSOp = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, RHSOp); 7878 } else { 7879 LHSOp = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), RVT, LHSOp); 7880 VT = RVT; 7881 } 7882 } 7883 SDValue FoldOp = DAG.getNode(N->getOpcode(), LHS.getDebugLoc(), VT, 7884 LHSOp, RHSOp); 7885 if (FoldOp.getOpcode() != ISD::UNDEF && 7886 FoldOp.getOpcode() != ISD::Constant && 7887 FoldOp.getOpcode() != ISD::ConstantFP) 7888 break; 7889 Ops.push_back(FoldOp); 7890 AddToWorkList(FoldOp.getNode()); 7891 } 7892 7893 if (Ops.size() == LHS.getNumOperands()) 7894 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 7895 LHS.getValueType(), &Ops[0], Ops.size()); 7896 } 7897 7898 return SDValue(); 7899} 7900 7901SDValue DAGCombiner::SimplifySelect(DebugLoc DL, SDValue N0, 7902 SDValue N1, SDValue N2){ 7903 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!"); 7904 7905 SDValue SCC = SimplifySelectCC(DL, N0.getOperand(0), N0.getOperand(1), N1, N2, 7906 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 7907 7908 // If we got a simplified select_cc node back from SimplifySelectCC, then 7909 // break it down into a new SETCC node, and a new SELECT node, and then return 7910 // the SELECT node, since we were called with a SELECT node. 7911 if (SCC.getNode()) { 7912 // Check to see if we got a select_cc back (to turn into setcc/select). 7913 // Otherwise, just return whatever node we got back, like fabs. 7914 if (SCC.getOpcode() == ISD::SELECT_CC) { 7915 SDValue SETCC = DAG.getNode(ISD::SETCC, N0.getDebugLoc(), 7916 N0.getValueType(), 7917 SCC.getOperand(0), SCC.getOperand(1), 7918 SCC.getOperand(4)); 7919 AddToWorkList(SETCC.getNode()); 7920 return DAG.getNode(ISD::SELECT, SCC.getDebugLoc(), SCC.getValueType(), 7921 SCC.getOperand(2), SCC.getOperand(3), SETCC); 7922 } 7923 7924 return SCC; 7925 } 7926 return SDValue(); 7927} 7928 7929/// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS 7930/// are the two values being selected between, see if we can simplify the 7931/// select. Callers of this should assume that TheSelect is deleted if this 7932/// returns true. As such, they should return the appropriate thing (e.g. the 7933/// node) back to the top-level of the DAG combiner loop to avoid it being 7934/// looked at. 7935bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDValue LHS, 7936 SDValue RHS) { 7937 7938 // Cannot simplify select with vector condition 7939 if (TheSelect->getOperand(0).getValueType().isVector()) return false; 7940 7941 // If this is a select from two identical things, try to pull the operation 7942 // through the select. 7943 if (LHS.getOpcode() != RHS.getOpcode() || 7944 !LHS.hasOneUse() || !RHS.hasOneUse()) 7945 return false; 7946 7947 // If this is a load and the token chain is identical, replace the select 7948 // of two loads with a load through a select of the address to load from. 7949 // This triggers in things like "select bool X, 10.0, 123.0" after the FP 7950 // constants have been dropped into the constant pool. 7951 if (LHS.getOpcode() == ISD::LOAD) { 7952 LoadSDNode *LLD = cast<LoadSDNode>(LHS); 7953 LoadSDNode *RLD = cast<LoadSDNode>(RHS); 7954 7955 // Token chains must be identical. 7956 if (LHS.getOperand(0) != RHS.getOperand(0) || 7957 // Do not let this transformation reduce the number of volatile loads. 7958 LLD->isVolatile() || RLD->isVolatile() || 7959 // If this is an EXTLOAD, the VT's must match. 7960 LLD->getMemoryVT() != RLD->getMemoryVT() || 7961 // If this is an EXTLOAD, the kind of extension must match. 7962 (LLD->getExtensionType() != RLD->getExtensionType() && 7963 // The only exception is if one of the extensions is anyext. 7964 LLD->getExtensionType() != ISD::EXTLOAD && 7965 RLD->getExtensionType() != ISD::EXTLOAD) || 7966 // FIXME: this discards src value information. This is 7967 // over-conservative. It would be beneficial to be able to remember 7968 // both potential memory locations. Since we are discarding 7969 // src value info, don't do the transformation if the memory 7970 // locations are not in the default address space. 7971 LLD->getPointerInfo().getAddrSpace() != 0 || 7972 RLD->getPointerInfo().getAddrSpace() != 0) 7973 return false; 7974 7975 // Check that the select condition doesn't reach either load. If so, 7976 // folding this will induce a cycle into the DAG. If not, this is safe to 7977 // xform, so create a select of the addresses. 7978 SDValue Addr; 7979 if (TheSelect->getOpcode() == ISD::SELECT) { 7980 SDNode *CondNode = TheSelect->getOperand(0).getNode(); 7981 if ((LLD->hasAnyUseOfValue(1) && LLD->isPredecessorOf(CondNode)) || 7982 (RLD->hasAnyUseOfValue(1) && RLD->isPredecessorOf(CondNode))) 7983 return false; 7984 Addr = DAG.getNode(ISD::SELECT, TheSelect->getDebugLoc(), 7985 LLD->getBasePtr().getValueType(), 7986 TheSelect->getOperand(0), LLD->getBasePtr(), 7987 RLD->getBasePtr()); 7988 } else { // Otherwise SELECT_CC 7989 SDNode *CondLHS = TheSelect->getOperand(0).getNode(); 7990 SDNode *CondRHS = TheSelect->getOperand(1).getNode(); 7991 7992 if ((LLD->hasAnyUseOfValue(1) && 7993 (LLD->isPredecessorOf(CondLHS) || LLD->isPredecessorOf(CondRHS))) || 7994 (RLD->hasAnyUseOfValue(1) && 7995 (RLD->isPredecessorOf(CondLHS) || RLD->isPredecessorOf(CondRHS)))) 7996 return false; 7997 7998 Addr = DAG.getNode(ISD::SELECT_CC, TheSelect->getDebugLoc(), 7999 LLD->getBasePtr().getValueType(), 8000 TheSelect->getOperand(0), 8001 TheSelect->getOperand(1), 8002 LLD->getBasePtr(), RLD->getBasePtr(), 8003 TheSelect->getOperand(4)); 8004 } 8005 8006 SDValue Load; 8007 if (LLD->getExtensionType() == ISD::NON_EXTLOAD) { 8008 Load = DAG.getLoad(TheSelect->getValueType(0), 8009 TheSelect->getDebugLoc(), 8010 // FIXME: Discards pointer info. 8011 LLD->getChain(), Addr, MachinePointerInfo(), 8012 LLD->isVolatile(), LLD->isNonTemporal(), 8013 LLD->isInvariant(), LLD->getAlignment()); 8014 } else { 8015 Load = DAG.getExtLoad(LLD->getExtensionType() == ISD::EXTLOAD ? 8016 RLD->getExtensionType() : LLD->getExtensionType(), 8017 TheSelect->getDebugLoc(), 8018 TheSelect->getValueType(0), 8019 // FIXME: Discards pointer info. 8020 LLD->getChain(), Addr, MachinePointerInfo(), 8021 LLD->getMemoryVT(), LLD->isVolatile(), 8022 LLD->isNonTemporal(), LLD->getAlignment()); 8023 } 8024 8025 // Users of the select now use the result of the load. 8026 CombineTo(TheSelect, Load); 8027 8028 // Users of the old loads now use the new load's chain. We know the 8029 // old-load value is dead now. 8030 CombineTo(LHS.getNode(), Load.getValue(0), Load.getValue(1)); 8031 CombineTo(RHS.getNode(), Load.getValue(0), Load.getValue(1)); 8032 return true; 8033 } 8034 8035 return false; 8036} 8037 8038/// SimplifySelectCC - Simplify an expression of the form (N0 cond N1) ? N2 : N3 8039/// where 'cond' is the comparison specified by CC. 8040SDValue DAGCombiner::SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, 8041 SDValue N2, SDValue N3, 8042 ISD::CondCode CC, bool NotExtCompare) { 8043 // (x ? y : y) -> y. 8044 if (N2 == N3) return N2; 8045 8046 EVT VT = N2.getValueType(); 8047 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 8048 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode()); 8049 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.getNode()); 8050 8051 // Determine if the condition we're dealing with is constant 8052 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()), 8053 N0, N1, CC, DL, false); 8054 if (SCC.getNode()) AddToWorkList(SCC.getNode()); 8055 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode()); 8056 8057 // fold select_cc true, x, y -> x 8058 if (SCCC && !SCCC->isNullValue()) 8059 return N2; 8060 // fold select_cc false, x, y -> y 8061 if (SCCC && SCCC->isNullValue()) 8062 return N3; 8063 8064 // Check to see if we can simplify the select into an fabs node 8065 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) { 8066 // Allow either -0.0 or 0.0 8067 if (CFP->getValueAPF().isZero()) { 8068 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs 8069 if ((CC == ISD::SETGE || CC == ISD::SETGT) && 8070 N0 == N2 && N3.getOpcode() == ISD::FNEG && 8071 N2 == N3.getOperand(0)) 8072 return DAG.getNode(ISD::FABS, DL, VT, N0); 8073 8074 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs 8075 if ((CC == ISD::SETLT || CC == ISD::SETLE) && 8076 N0 == N3 && N2.getOpcode() == ISD::FNEG && 8077 N2.getOperand(0) == N3) 8078 return DAG.getNode(ISD::FABS, DL, VT, N3); 8079 } 8080 } 8081 8082 // Turn "(a cond b) ? 1.0f : 2.0f" into "load (tmp + ((a cond b) ? 0 : 4)" 8083 // where "tmp" is a constant pool entry containing an array with 1.0 and 2.0 8084 // in it. This is a win when the constant is not otherwise available because 8085 // it replaces two constant pool loads with one. We only do this if the FP 8086 // type is known to be legal, because if it isn't, then we are before legalize 8087 // types an we want the other legalization to happen first (e.g. to avoid 8088 // messing with soft float) and if the ConstantFP is not legal, because if 8089 // it is legal, we may not need to store the FP constant in a constant pool. 8090 if (ConstantFPSDNode *TV = dyn_cast<ConstantFPSDNode>(N2)) 8091 if (ConstantFPSDNode *FV = dyn_cast<ConstantFPSDNode>(N3)) { 8092 if (TLI.isTypeLegal(N2.getValueType()) && 8093 (TLI.getOperationAction(ISD::ConstantFP, N2.getValueType()) != 8094 TargetLowering::Legal) && 8095 // If both constants have multiple uses, then we won't need to do an 8096 // extra load, they are likely around in registers for other users. 8097 (TV->hasOneUse() || FV->hasOneUse())) { 8098 Constant *Elts[] = { 8099 const_cast<ConstantFP*>(FV->getConstantFPValue()), 8100 const_cast<ConstantFP*>(TV->getConstantFPValue()) 8101 }; 8102 Type *FPTy = Elts[0]->getType(); 8103 const TargetData &TD = *TLI.getTargetData(); 8104 8105 // Create a ConstantArray of the two constants. 8106 Constant *CA = ConstantArray::get(ArrayType::get(FPTy, 2), Elts); 8107 SDValue CPIdx = DAG.getConstantPool(CA, TLI.getPointerTy(), 8108 TD.getPrefTypeAlignment(FPTy)); 8109 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 8110 8111 // Get the offsets to the 0 and 1 element of the array so that we can 8112 // select between them. 8113 SDValue Zero = DAG.getIntPtrConstant(0); 8114 unsigned EltSize = (unsigned)TD.getTypeAllocSize(Elts[0]->getType()); 8115 SDValue One = DAG.getIntPtrConstant(EltSize); 8116 8117 SDValue Cond = DAG.getSetCC(DL, 8118 TLI.getSetCCResultType(N0.getValueType()), 8119 N0, N1, CC); 8120 AddToWorkList(Cond.getNode()); 8121 SDValue CstOffset = DAG.getNode(ISD::SELECT, DL, Zero.getValueType(), 8122 Cond, One, Zero); 8123 AddToWorkList(CstOffset.getNode()); 8124 CPIdx = DAG.getNode(ISD::ADD, DL, TLI.getPointerTy(), CPIdx, 8125 CstOffset); 8126 AddToWorkList(CPIdx.getNode()); 8127 return DAG.getLoad(TV->getValueType(0), DL, DAG.getEntryNode(), CPIdx, 8128 MachinePointerInfo::getConstantPool(), false, 8129 false, false, Alignment); 8130 8131 } 8132 } 8133 8134 // Check to see if we can perform the "gzip trick", transforming 8135 // (select_cc setlt X, 0, A, 0) -> (and (sra X, (sub size(X), 1), A) 8136 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT && 8137 (N1C->isNullValue() || // (a < 0) ? b : 0 8138 (N1C->getAPIntValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0 8139 EVT XType = N0.getValueType(); 8140 EVT AType = N2.getValueType(); 8141 if (XType.bitsGE(AType)) { 8142 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a 8143 // single-bit constant. 8144 if (N2C && ((N2C->getAPIntValue() & (N2C->getAPIntValue()-1)) == 0)) { 8145 unsigned ShCtV = N2C->getAPIntValue().logBase2(); 8146 ShCtV = XType.getSizeInBits()-ShCtV-1; 8147 SDValue ShCt = DAG.getConstant(ShCtV, 8148 getShiftAmountTy(N0.getValueType())); 8149 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), 8150 XType, N0, ShCt); 8151 AddToWorkList(Shift.getNode()); 8152 8153 if (XType.bitsGT(AType)) { 8154 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift); 8155 AddToWorkList(Shift.getNode()); 8156 } 8157 8158 return DAG.getNode(ISD::AND, DL, AType, Shift, N2); 8159 } 8160 8161 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), 8162 XType, N0, 8163 DAG.getConstant(XType.getSizeInBits()-1, 8164 getShiftAmountTy(N0.getValueType()))); 8165 AddToWorkList(Shift.getNode()); 8166 8167 if (XType.bitsGT(AType)) { 8168 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift); 8169 AddToWorkList(Shift.getNode()); 8170 } 8171 8172 return DAG.getNode(ISD::AND, DL, AType, Shift, N2); 8173 } 8174 } 8175 8176 // fold (select_cc seteq (and x, y), 0, 0, A) -> (and (shr (shl x)) A) 8177 // where y is has a single bit set. 8178 // A plaintext description would be, we can turn the SELECT_CC into an AND 8179 // when the condition can be materialized as an all-ones register. Any 8180 // single bit-test can be materialized as an all-ones register with 8181 // shift-left and shift-right-arith. 8182 if (CC == ISD::SETEQ && N0->getOpcode() == ISD::AND && 8183 N0->getValueType(0) == VT && 8184 N1C && N1C->isNullValue() && 8185 N2C && N2C->isNullValue()) { 8186 SDValue AndLHS = N0->getOperand(0); 8187 ConstantSDNode *ConstAndRHS = dyn_cast<ConstantSDNode>(N0->getOperand(1)); 8188 if (ConstAndRHS && ConstAndRHS->getAPIntValue().countPopulation() == 1) { 8189 // Shift the tested bit over the sign bit. 8190 APInt AndMask = ConstAndRHS->getAPIntValue(); 8191 SDValue ShlAmt = 8192 DAG.getConstant(AndMask.countLeadingZeros(), 8193 getShiftAmountTy(AndLHS.getValueType())); 8194 SDValue Shl = DAG.getNode(ISD::SHL, N0.getDebugLoc(), VT, AndLHS, ShlAmt); 8195 8196 // Now arithmetic right shift it all the way over, so the result is either 8197 // all-ones, or zero. 8198 SDValue ShrAmt = 8199 DAG.getConstant(AndMask.getBitWidth()-1, 8200 getShiftAmountTy(Shl.getValueType())); 8201 SDValue Shr = DAG.getNode(ISD::SRA, N0.getDebugLoc(), VT, Shl, ShrAmt); 8202 8203 return DAG.getNode(ISD::AND, DL, VT, Shr, N3); 8204 } 8205 } 8206 8207 // fold select C, 16, 0 -> shl C, 4 8208 if (N2C && N3C && N3C->isNullValue() && N2C->getAPIntValue().isPowerOf2() && 8209 TLI.getBooleanContents(N0.getValueType().isVector()) == 8210 TargetLowering::ZeroOrOneBooleanContent) { 8211 8212 // If the caller doesn't want us to simplify this into a zext of a compare, 8213 // don't do it. 8214 if (NotExtCompare && N2C->getAPIntValue() == 1) 8215 return SDValue(); 8216 8217 // Get a SetCC of the condition 8218 // FIXME: Should probably make sure that setcc is legal if we ever have a 8219 // target where it isn't. 8220 SDValue Temp, SCC; 8221 // cast from setcc result type to select result type 8222 if (LegalTypes) { 8223 SCC = DAG.getSetCC(DL, TLI.getSetCCResultType(N0.getValueType()), 8224 N0, N1, CC); 8225 if (N2.getValueType().bitsLT(SCC.getValueType())) 8226 Temp = DAG.getZeroExtendInReg(SCC, N2.getDebugLoc(), N2.getValueType()); 8227 else 8228 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(), 8229 N2.getValueType(), SCC); 8230 } else { 8231 SCC = DAG.getSetCC(N0.getDebugLoc(), MVT::i1, N0, N1, CC); 8232 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(), 8233 N2.getValueType(), SCC); 8234 } 8235 8236 AddToWorkList(SCC.getNode()); 8237 AddToWorkList(Temp.getNode()); 8238 8239 if (N2C->getAPIntValue() == 1) 8240 return Temp; 8241 8242 // shl setcc result by log2 n2c 8243 return DAG.getNode(ISD::SHL, DL, N2.getValueType(), Temp, 8244 DAG.getConstant(N2C->getAPIntValue().logBase2(), 8245 getShiftAmountTy(Temp.getValueType()))); 8246 } 8247 8248 // Check to see if this is the equivalent of setcc 8249 // FIXME: Turn all of these into setcc if setcc if setcc is legal 8250 // otherwise, go ahead with the folds. 8251 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getAPIntValue() == 1ULL)) { 8252 EVT XType = N0.getValueType(); 8253 if (!LegalOperations || 8254 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(XType))) { 8255 SDValue Res = DAG.getSetCC(DL, TLI.getSetCCResultType(XType), N0, N1, CC); 8256 if (Res.getValueType() != VT) 8257 Res = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, Res); 8258 return Res; 8259 } 8260 8261 // fold (seteq X, 0) -> (srl (ctlz X, log2(size(X)))) 8262 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ && 8263 (!LegalOperations || 8264 TLI.isOperationLegal(ISD::CTLZ, XType))) { 8265 SDValue Ctlz = DAG.getNode(ISD::CTLZ, N0.getDebugLoc(), XType, N0); 8266 return DAG.getNode(ISD::SRL, DL, XType, Ctlz, 8267 DAG.getConstant(Log2_32(XType.getSizeInBits()), 8268 getShiftAmountTy(Ctlz.getValueType()))); 8269 } 8270 // fold (setgt X, 0) -> (srl (and (-X, ~X), size(X)-1)) 8271 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) { 8272 SDValue NegN0 = DAG.getNode(ISD::SUB, N0.getDebugLoc(), 8273 XType, DAG.getConstant(0, XType), N0); 8274 SDValue NotN0 = DAG.getNOT(N0.getDebugLoc(), N0, XType); 8275 return DAG.getNode(ISD::SRL, DL, XType, 8276 DAG.getNode(ISD::AND, DL, XType, NegN0, NotN0), 8277 DAG.getConstant(XType.getSizeInBits()-1, 8278 getShiftAmountTy(XType))); 8279 } 8280 // fold (setgt X, -1) -> (xor (srl (X, size(X)-1), 1)) 8281 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) { 8282 SDValue Sign = DAG.getNode(ISD::SRL, N0.getDebugLoc(), XType, N0, 8283 DAG.getConstant(XType.getSizeInBits()-1, 8284 getShiftAmountTy(N0.getValueType()))); 8285 return DAG.getNode(ISD::XOR, DL, XType, Sign, DAG.getConstant(1, XType)); 8286 } 8287 } 8288 8289 // Check to see if this is an integer abs. 8290 // select_cc setg[te] X, 0, X, -X -> 8291 // select_cc setgt X, -1, X, -X -> 8292 // select_cc setl[te] X, 0, -X, X -> 8293 // select_cc setlt X, 1, -X, X -> 8294 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 8295 if (N1C) { 8296 ConstantSDNode *SubC = NULL; 8297 if (((N1C->isNullValue() && (CC == ISD::SETGT || CC == ISD::SETGE)) || 8298 (N1C->isAllOnesValue() && CC == ISD::SETGT)) && 8299 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1)) 8300 SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0)); 8301 else if (((N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE)) || 8302 (N1C->isOne() && CC == ISD::SETLT)) && 8303 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1)) 8304 SubC = dyn_cast<ConstantSDNode>(N2.getOperand(0)); 8305 8306 EVT XType = N0.getValueType(); 8307 if (SubC && SubC->isNullValue() && XType.isInteger()) { 8308 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), XType, 8309 N0, 8310 DAG.getConstant(XType.getSizeInBits()-1, 8311 getShiftAmountTy(N0.getValueType()))); 8312 SDValue Add = DAG.getNode(ISD::ADD, N0.getDebugLoc(), 8313 XType, N0, Shift); 8314 AddToWorkList(Shift.getNode()); 8315 AddToWorkList(Add.getNode()); 8316 return DAG.getNode(ISD::XOR, DL, XType, Add, Shift); 8317 } 8318 } 8319 8320 return SDValue(); 8321} 8322 8323/// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC. 8324SDValue DAGCombiner::SimplifySetCC(EVT VT, SDValue N0, 8325 SDValue N1, ISD::CondCode Cond, 8326 DebugLoc DL, bool foldBooleans) { 8327 TargetLowering::DAGCombinerInfo 8328 DagCombineInfo(DAG, !LegalTypes, !LegalOperations, false, this); 8329 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo, DL); 8330} 8331 8332/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 8333/// return a DAG expression to select that will generate the same value by 8334/// multiplying by a magic number. See: 8335/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 8336SDValue DAGCombiner::BuildSDIV(SDNode *N) { 8337 std::vector<SDNode*> Built; 8338 SDValue S = TLI.BuildSDIV(N, DAG, LegalOperations, &Built); 8339 8340 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 8341 ii != ee; ++ii) 8342 AddToWorkList(*ii); 8343 return S; 8344} 8345 8346/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 8347/// return a DAG expression to select that will generate the same value by 8348/// multiplying by a magic number. See: 8349/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 8350SDValue DAGCombiner::BuildUDIV(SDNode *N) { 8351 std::vector<SDNode*> Built; 8352 SDValue S = TLI.BuildUDIV(N, DAG, LegalOperations, &Built); 8353 8354 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 8355 ii != ee; ++ii) 8356 AddToWorkList(*ii); 8357 return S; 8358} 8359 8360/// FindBaseOffset - Return true if base is a frame index, which is known not 8361// to alias with anything but itself. Provides base object and offset as 8362// results. 8363static bool FindBaseOffset(SDValue Ptr, SDValue &Base, int64_t &Offset, 8364 const GlobalValue *&GV, void *&CV) { 8365 // Assume it is a primitive operation. 8366 Base = Ptr; Offset = 0; GV = 0; CV = 0; 8367 8368 // If it's an adding a simple constant then integrate the offset. 8369 if (Base.getOpcode() == ISD::ADD) { 8370 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) { 8371 Base = Base.getOperand(0); 8372 Offset += C->getZExtValue(); 8373 } 8374 } 8375 8376 // Return the underlying GlobalValue, and update the Offset. Return false 8377 // for GlobalAddressSDNode since the same GlobalAddress may be represented 8378 // by multiple nodes with different offsets. 8379 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Base)) { 8380 GV = G->getGlobal(); 8381 Offset += G->getOffset(); 8382 return false; 8383 } 8384 8385 // Return the underlying Constant value, and update the Offset. Return false 8386 // for ConstantSDNodes since the same constant pool entry may be represented 8387 // by multiple nodes with different offsets. 8388 if (ConstantPoolSDNode *C = dyn_cast<ConstantPoolSDNode>(Base)) { 8389 CV = C->isMachineConstantPoolEntry() ? (void *)C->getMachineCPVal() 8390 : (void *)C->getConstVal(); 8391 Offset += C->getOffset(); 8392 return false; 8393 } 8394 // If it's any of the following then it can't alias with anything but itself. 8395 return isa<FrameIndexSDNode>(Base); 8396} 8397 8398/// isAlias - Return true if there is any possibility that the two addresses 8399/// overlap. 8400bool DAGCombiner::isAlias(SDValue Ptr1, int64_t Size1, 8401 const Value *SrcValue1, int SrcValueOffset1, 8402 unsigned SrcValueAlign1, 8403 const MDNode *TBAAInfo1, 8404 SDValue Ptr2, int64_t Size2, 8405 const Value *SrcValue2, int SrcValueOffset2, 8406 unsigned SrcValueAlign2, 8407 const MDNode *TBAAInfo2) const { 8408 // If they are the same then they must be aliases. 8409 if (Ptr1 == Ptr2) return true; 8410 8411 // Gather base node and offset information. 8412 SDValue Base1, Base2; 8413 int64_t Offset1, Offset2; 8414 const GlobalValue *GV1, *GV2; 8415 void *CV1, *CV2; 8416 bool isFrameIndex1 = FindBaseOffset(Ptr1, Base1, Offset1, GV1, CV1); 8417 bool isFrameIndex2 = FindBaseOffset(Ptr2, Base2, Offset2, GV2, CV2); 8418 8419 // If they have a same base address then check to see if they overlap. 8420 if (Base1 == Base2 || (GV1 && (GV1 == GV2)) || (CV1 && (CV1 == CV2))) 8421 return !((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1); 8422 8423 // It is possible for different frame indices to alias each other, mostly 8424 // when tail call optimization reuses return address slots for arguments. 8425 // To catch this case, look up the actual index of frame indices to compute 8426 // the real alias relationship. 8427 if (isFrameIndex1 && isFrameIndex2) { 8428 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 8429 Offset1 += MFI->getObjectOffset(cast<FrameIndexSDNode>(Base1)->getIndex()); 8430 Offset2 += MFI->getObjectOffset(cast<FrameIndexSDNode>(Base2)->getIndex()); 8431 return !((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1); 8432 } 8433 8434 // Otherwise, if we know what the bases are, and they aren't identical, then 8435 // we know they cannot alias. 8436 if ((isFrameIndex1 || CV1 || GV1) && (isFrameIndex2 || CV2 || GV2)) 8437 return false; 8438 8439 // If we know required SrcValue1 and SrcValue2 have relatively large alignment 8440 // compared to the size and offset of the access, we may be able to prove they 8441 // do not alias. This check is conservative for now to catch cases created by 8442 // splitting vector types. 8443 if ((SrcValueAlign1 == SrcValueAlign2) && 8444 (SrcValueOffset1 != SrcValueOffset2) && 8445 (Size1 == Size2) && (SrcValueAlign1 > Size1)) { 8446 int64_t OffAlign1 = SrcValueOffset1 % SrcValueAlign1; 8447 int64_t OffAlign2 = SrcValueOffset2 % SrcValueAlign1; 8448 8449 // There is no overlap between these relatively aligned accesses of similar 8450 // size, return no alias. 8451 if ((OffAlign1 + Size1) <= OffAlign2 || (OffAlign2 + Size2) <= OffAlign1) 8452 return false; 8453 } 8454 8455 if (CombinerGlobalAA) { 8456 // Use alias analysis information. 8457 int64_t MinOffset = std::min(SrcValueOffset1, SrcValueOffset2); 8458 int64_t Overlap1 = Size1 + SrcValueOffset1 - MinOffset; 8459 int64_t Overlap2 = Size2 + SrcValueOffset2 - MinOffset; 8460 AliasAnalysis::AliasResult AAResult = 8461 AA.alias(AliasAnalysis::Location(SrcValue1, Overlap1, TBAAInfo1), 8462 AliasAnalysis::Location(SrcValue2, Overlap2, TBAAInfo2)); 8463 if (AAResult == AliasAnalysis::NoAlias) 8464 return false; 8465 } 8466 8467 // Otherwise we have to assume they alias. 8468 return true; 8469} 8470 8471/// FindAliasInfo - Extracts the relevant alias information from the memory 8472/// node. Returns true if the operand was a load. 8473bool DAGCombiner::FindAliasInfo(SDNode *N, 8474 SDValue &Ptr, int64_t &Size, 8475 const Value *&SrcValue, 8476 int &SrcValueOffset, 8477 unsigned &SrcValueAlign, 8478 const MDNode *&TBAAInfo) const { 8479 LSBaseSDNode *LS = cast<LSBaseSDNode>(N); 8480 8481 Ptr = LS->getBasePtr(); 8482 Size = LS->getMemoryVT().getSizeInBits() >> 3; 8483 SrcValue = LS->getSrcValue(); 8484 SrcValueOffset = LS->getSrcValueOffset(); 8485 SrcValueAlign = LS->getOriginalAlignment(); 8486 TBAAInfo = LS->getTBAAInfo(); 8487 return isa<LoadSDNode>(LS); 8488} 8489 8490/// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 8491/// looking for aliasing nodes and adding them to the Aliases vector. 8492void DAGCombiner::GatherAllAliases(SDNode *N, SDValue OriginalChain, 8493 SmallVector<SDValue, 8> &Aliases) { 8494 SmallVector<SDValue, 8> Chains; // List of chains to visit. 8495 SmallPtrSet<SDNode *, 16> Visited; // Visited node set. 8496 8497 // Get alias information for node. 8498 SDValue Ptr; 8499 int64_t Size; 8500 const Value *SrcValue; 8501 int SrcValueOffset; 8502 unsigned SrcValueAlign; 8503 const MDNode *SrcTBAAInfo; 8504 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset, 8505 SrcValueAlign, SrcTBAAInfo); 8506 8507 // Starting off. 8508 Chains.push_back(OriginalChain); 8509 unsigned Depth = 0; 8510 8511 // Look at each chain and determine if it is an alias. If so, add it to the 8512 // aliases list. If not, then continue up the chain looking for the next 8513 // candidate. 8514 while (!Chains.empty()) { 8515 SDValue Chain = Chains.back(); 8516 Chains.pop_back(); 8517 8518 // For TokenFactor nodes, look at each operand and only continue up the 8519 // chain until we find two aliases. If we've seen two aliases, assume we'll 8520 // find more and revert to original chain since the xform is unlikely to be 8521 // profitable. 8522 // 8523 // FIXME: The depth check could be made to return the last non-aliasing 8524 // chain we found before we hit a tokenfactor rather than the original 8525 // chain. 8526 if (Depth > 6 || Aliases.size() == 2) { 8527 Aliases.clear(); 8528 Aliases.push_back(OriginalChain); 8529 break; 8530 } 8531 8532 // Don't bother if we've been before. 8533 if (!Visited.insert(Chain.getNode())) 8534 continue; 8535 8536 switch (Chain.getOpcode()) { 8537 case ISD::EntryToken: 8538 // Entry token is ideal chain operand, but handled in FindBetterChain. 8539 break; 8540 8541 case ISD::LOAD: 8542 case ISD::STORE: { 8543 // Get alias information for Chain. 8544 SDValue OpPtr; 8545 int64_t OpSize; 8546 const Value *OpSrcValue; 8547 int OpSrcValueOffset; 8548 unsigned OpSrcValueAlign; 8549 const MDNode *OpSrcTBAAInfo; 8550 bool IsOpLoad = FindAliasInfo(Chain.getNode(), OpPtr, OpSize, 8551 OpSrcValue, OpSrcValueOffset, 8552 OpSrcValueAlign, 8553 OpSrcTBAAInfo); 8554 8555 // If chain is alias then stop here. 8556 if (!(IsLoad && IsOpLoad) && 8557 isAlias(Ptr, Size, SrcValue, SrcValueOffset, SrcValueAlign, 8558 SrcTBAAInfo, 8559 OpPtr, OpSize, OpSrcValue, OpSrcValueOffset, 8560 OpSrcValueAlign, OpSrcTBAAInfo)) { 8561 Aliases.push_back(Chain); 8562 } else { 8563 // Look further up the chain. 8564 Chains.push_back(Chain.getOperand(0)); 8565 ++Depth; 8566 } 8567 break; 8568 } 8569 8570 case ISD::TokenFactor: 8571 // We have to check each of the operands of the token factor for "small" 8572 // token factors, so we queue them up. Adding the operands to the queue 8573 // (stack) in reverse order maintains the original order and increases the 8574 // likelihood that getNode will find a matching token factor (CSE.) 8575 if (Chain.getNumOperands() > 16) { 8576 Aliases.push_back(Chain); 8577 break; 8578 } 8579 for (unsigned n = Chain.getNumOperands(); n;) 8580 Chains.push_back(Chain.getOperand(--n)); 8581 ++Depth; 8582 break; 8583 8584 default: 8585 // For all other instructions we will just have to take what we can get. 8586 Aliases.push_back(Chain); 8587 break; 8588 } 8589 } 8590} 8591 8592/// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking 8593/// for a better chain (aliasing node.) 8594SDValue DAGCombiner::FindBetterChain(SDNode *N, SDValue OldChain) { 8595 SmallVector<SDValue, 8> Aliases; // Ops for replacing token factor. 8596 8597 // Accumulate all the aliases to this node. 8598 GatherAllAliases(N, OldChain, Aliases); 8599 8600 // If no operands then chain to entry token. 8601 if (Aliases.size() == 0) 8602 return DAG.getEntryNode(); 8603 8604 // If a single operand then chain to it. We don't need to revisit it. 8605 if (Aliases.size() == 1) 8606 return Aliases[0]; 8607 8608 // Construct a custom tailored token factor. 8609 return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, 8610 &Aliases[0], Aliases.size()); 8611} 8612 8613// SelectionDAG::Combine - This is the entry point for the file. 8614// 8615void SelectionDAG::Combine(CombineLevel Level, AliasAnalysis &AA, 8616 CodeGenOpt::Level OptLevel) { 8617 /// run - This is the main entry point to this class. 8618 /// 8619 DAGCombiner(*this, AA, OptLevel).Run(Level); 8620} 8621