DAGCombiner.cpp revision 78d12644b905dc54cf6cf984af02a49d30d29744
1//===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run 11// both before and after the DAG is legalized. 12// 13// This pass is not a substitute for the LLVM IR instcombine pass. This pass is 14// primarily intended to handle simplification opportunities that are implicit 15// in the LLVM IR and exposed by the various codegen lowering phases. 16// 17//===----------------------------------------------------------------------===// 18 19#define DEBUG_TYPE "dagcombine" 20#include "llvm/CodeGen/SelectionDAG.h" 21#include "llvm/DerivedTypes.h" 22#include "llvm/LLVMContext.h" 23#include "llvm/CodeGen/MachineFunction.h" 24#include "llvm/CodeGen/MachineFrameInfo.h" 25#include "llvm/CodeGen/PseudoSourceValue.h" 26#include "llvm/Analysis/AliasAnalysis.h" 27#include "llvm/Target/TargetData.h" 28#include "llvm/Target/TargetFrameInfo.h" 29#include "llvm/Target/TargetLowering.h" 30#include "llvm/Target/TargetMachine.h" 31#include "llvm/Target/TargetOptions.h" 32#include "llvm/ADT/SmallPtrSet.h" 33#include "llvm/ADT/Statistic.h" 34#include "llvm/Support/Compiler.h" 35#include "llvm/Support/CommandLine.h" 36#include "llvm/Support/Debug.h" 37#include "llvm/Support/ErrorHandling.h" 38#include "llvm/Support/MathExtras.h" 39#include <algorithm> 40#include <set> 41using namespace llvm; 42 43STATISTIC(NodesCombined , "Number of dag nodes combined"); 44STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created"); 45STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created"); 46STATISTIC(OpsNarrowed , "Number of load/op/store narrowed"); 47 48namespace { 49 static cl::opt<bool> 50 CombinerAA("combiner-alias-analysis", cl::Hidden, 51 cl::desc("Turn on alias analysis during testing")); 52 53 static cl::opt<bool> 54 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden, 55 cl::desc("Include global information in alias analysis")); 56 57//------------------------------ DAGCombiner ---------------------------------// 58 59 class VISIBILITY_HIDDEN DAGCombiner { 60 SelectionDAG &DAG; 61 const TargetLowering &TLI; 62 CombineLevel Level; 63 CodeGenOpt::Level OptLevel; 64 bool LegalOperations; 65 bool LegalTypes; 66 67 // Worklist of all of the nodes that need to be simplified. 68 std::vector<SDNode*> WorkList; 69 70 // AA - Used for DAG load/store alias analysis. 71 AliasAnalysis &AA; 72 73 /// AddUsersToWorkList - When an instruction is simplified, add all users of 74 /// the instruction to the work lists because they might get more simplified 75 /// now. 76 /// 77 void AddUsersToWorkList(SDNode *N) { 78 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 79 UI != UE; ++UI) 80 AddToWorkList(*UI); 81 } 82 83 /// visit - call the node-specific routine that knows how to fold each 84 /// particular type of node. 85 SDValue visit(SDNode *N); 86 87 public: 88 /// AddToWorkList - Add to the work list making sure it's instance is at the 89 /// the back (next to be processed.) 90 void AddToWorkList(SDNode *N) { 91 removeFromWorkList(N); 92 WorkList.push_back(N); 93 } 94 95 /// removeFromWorkList - remove all instances of N from the worklist. 96 /// 97 void removeFromWorkList(SDNode *N) { 98 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N), 99 WorkList.end()); 100 } 101 102 SDValue CombineTo(SDNode *N, const SDValue *To, unsigned NumTo, 103 bool AddTo = true); 104 105 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true) { 106 return CombineTo(N, &Res, 1, AddTo); 107 } 108 109 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, 110 bool AddTo = true) { 111 SDValue To[] = { Res0, Res1 }; 112 return CombineTo(N, To, 2, AddTo); 113 } 114 115 void CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO); 116 117 private: 118 119 /// SimplifyDemandedBits - Check the specified integer node value to see if 120 /// it can be simplified or if things it uses can be simplified by bit 121 /// propagation. If so, return true. 122 bool SimplifyDemandedBits(SDValue Op) { 123 APInt Demanded = APInt::getAllOnesValue(Op.getValueSizeInBits()); 124 return SimplifyDemandedBits(Op, Demanded); 125 } 126 127 bool SimplifyDemandedBits(SDValue Op, const APInt &Demanded); 128 129 bool CombineToPreIndexedLoadStore(SDNode *N); 130 bool CombineToPostIndexedLoadStore(SDNode *N); 131 132 133 /// combine - call the node-specific routine that knows how to fold each 134 /// particular type of node. If that doesn't do anything, try the 135 /// target-specific DAG combines. 136 SDValue combine(SDNode *N); 137 138 // Visitation implementation - Implement dag node combining for different 139 // node types. The semantics are as follows: 140 // Return Value: 141 // SDValue.getNode() == 0 - No change was made 142 // SDValue.getNode() == N - N was replaced, is dead and has been handled. 143 // otherwise - N should be replaced by the returned Operand. 144 // 145 SDValue visitTokenFactor(SDNode *N); 146 SDValue visitMERGE_VALUES(SDNode *N); 147 SDValue visitADD(SDNode *N); 148 SDValue visitSUB(SDNode *N); 149 SDValue visitADDC(SDNode *N); 150 SDValue visitADDE(SDNode *N); 151 SDValue visitMUL(SDNode *N); 152 SDValue visitSDIV(SDNode *N); 153 SDValue visitUDIV(SDNode *N); 154 SDValue visitSREM(SDNode *N); 155 SDValue visitUREM(SDNode *N); 156 SDValue visitMULHU(SDNode *N); 157 SDValue visitMULHS(SDNode *N); 158 SDValue visitSMUL_LOHI(SDNode *N); 159 SDValue visitUMUL_LOHI(SDNode *N); 160 SDValue visitSDIVREM(SDNode *N); 161 SDValue visitUDIVREM(SDNode *N); 162 SDValue visitAND(SDNode *N); 163 SDValue visitOR(SDNode *N); 164 SDValue visitXOR(SDNode *N); 165 SDValue SimplifyVBinOp(SDNode *N); 166 SDValue visitSHL(SDNode *N); 167 SDValue visitSRA(SDNode *N); 168 SDValue visitSRL(SDNode *N); 169 SDValue visitCTLZ(SDNode *N); 170 SDValue visitCTTZ(SDNode *N); 171 SDValue visitCTPOP(SDNode *N); 172 SDValue visitSELECT(SDNode *N); 173 SDValue visitSELECT_CC(SDNode *N); 174 SDValue visitSETCC(SDNode *N); 175 SDValue visitSIGN_EXTEND(SDNode *N); 176 SDValue visitZERO_EXTEND(SDNode *N); 177 SDValue visitANY_EXTEND(SDNode *N); 178 SDValue visitSIGN_EXTEND_INREG(SDNode *N); 179 SDValue visitTRUNCATE(SDNode *N); 180 SDValue visitBIT_CONVERT(SDNode *N); 181 SDValue visitBUILD_PAIR(SDNode *N); 182 SDValue visitFADD(SDNode *N); 183 SDValue visitFSUB(SDNode *N); 184 SDValue visitFMUL(SDNode *N); 185 SDValue visitFDIV(SDNode *N); 186 SDValue visitFREM(SDNode *N); 187 SDValue visitFCOPYSIGN(SDNode *N); 188 SDValue visitSINT_TO_FP(SDNode *N); 189 SDValue visitUINT_TO_FP(SDNode *N); 190 SDValue visitFP_TO_SINT(SDNode *N); 191 SDValue visitFP_TO_UINT(SDNode *N); 192 SDValue visitFP_ROUND(SDNode *N); 193 SDValue visitFP_ROUND_INREG(SDNode *N); 194 SDValue visitFP_EXTEND(SDNode *N); 195 SDValue visitFNEG(SDNode *N); 196 SDValue visitFABS(SDNode *N); 197 SDValue visitBRCOND(SDNode *N); 198 SDValue visitBR_CC(SDNode *N); 199 SDValue visitLOAD(SDNode *N); 200 SDValue visitSTORE(SDNode *N); 201 SDValue visitINSERT_VECTOR_ELT(SDNode *N); 202 SDValue visitEXTRACT_VECTOR_ELT(SDNode *N); 203 SDValue visitBUILD_VECTOR(SDNode *N); 204 SDValue visitCONCAT_VECTORS(SDNode *N); 205 SDValue visitVECTOR_SHUFFLE(SDNode *N); 206 207 SDValue XformToShuffleWithZero(SDNode *N); 208 SDValue ReassociateOps(unsigned Opc, DebugLoc DL, SDValue LHS, SDValue RHS); 209 210 SDValue visitShiftByConstant(SDNode *N, unsigned Amt); 211 212 bool SimplifySelectOps(SDNode *SELECT, SDValue LHS, SDValue RHS); 213 SDValue SimplifyBinOpWithSameOpcodeHands(SDNode *N); 214 SDValue SimplifySelect(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2); 215 SDValue SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2, 216 SDValue N3, ISD::CondCode CC, 217 bool NotExtCompare = false); 218 SDValue SimplifySetCC(MVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond, 219 DebugLoc DL, bool foldBooleans = true); 220 SDValue SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 221 unsigned HiOp); 222 SDValue CombineConsecutiveLoads(SDNode *N, MVT VT); 223 SDValue ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *, MVT); 224 SDValue BuildSDIV(SDNode *N); 225 SDValue BuildUDIV(SDNode *N); 226 SDNode *MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL); 227 SDValue ReduceLoadWidth(SDNode *N); 228 SDValue ReduceLoadOpStoreWidth(SDNode *N); 229 230 SDValue GetDemandedBits(SDValue V, const APInt &Mask); 231 232 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 233 /// looking for aliasing nodes and adding them to the Aliases vector. 234 void GatherAllAliases(SDNode *N, SDValue OriginalChain, 235 SmallVector<SDValue, 8> &Aliases); 236 237 /// isAlias - Return true if there is any possibility that the two addresses 238 /// overlap. 239 bool isAlias(SDValue Ptr1, int64_t Size1, 240 const Value *SrcValue1, int SrcValueOffset1, 241 SDValue Ptr2, int64_t Size2, 242 const Value *SrcValue2, int SrcValueOffset2) const; 243 244 /// FindAliasInfo - Extracts the relevant alias information from the memory 245 /// node. Returns true if the operand was a load. 246 bool FindAliasInfo(SDNode *N, 247 SDValue &Ptr, int64_t &Size, 248 const Value *&SrcValue, int &SrcValueOffset) const; 249 250 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, 251 /// looking for a better chain (aliasing node.) 252 SDValue FindBetterChain(SDNode *N, SDValue Chain); 253 254 /// getShiftAmountTy - Returns a type large enough to hold any valid 255 /// shift amount - before type legalization these can be huge. 256 MVT getShiftAmountTy() { 257 return LegalTypes ? TLI.getShiftAmountTy() : TLI.getPointerTy(); 258 } 259 260public: 261 DAGCombiner(SelectionDAG &D, AliasAnalysis &A, CodeGenOpt::Level OL) 262 : DAG(D), 263 TLI(D.getTargetLoweringInfo()), 264 Level(Unrestricted), 265 OptLevel(OL), 266 LegalOperations(false), 267 LegalTypes(false), 268 AA(A) {} 269 270 /// Run - runs the dag combiner on all nodes in the work list 271 void Run(CombineLevel AtLevel); 272 }; 273} 274 275 276namespace { 277/// WorkListRemover - This class is a DAGUpdateListener that removes any deleted 278/// nodes from the worklist. 279class VISIBILITY_HIDDEN WorkListRemover : 280 public SelectionDAG::DAGUpdateListener { 281 DAGCombiner &DC; 282public: 283 explicit WorkListRemover(DAGCombiner &dc) : DC(dc) {} 284 285 virtual void NodeDeleted(SDNode *N, SDNode *E) { 286 DC.removeFromWorkList(N); 287 } 288 289 virtual void NodeUpdated(SDNode *N) { 290 // Ignore updates. 291 } 292}; 293} 294 295//===----------------------------------------------------------------------===// 296// TargetLowering::DAGCombinerInfo implementation 297//===----------------------------------------------------------------------===// 298 299void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) { 300 ((DAGCombiner*)DC)->AddToWorkList(N); 301} 302 303SDValue TargetLowering::DAGCombinerInfo:: 304CombineTo(SDNode *N, const std::vector<SDValue> &To, bool AddTo) { 305 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size(), AddTo); 306} 307 308SDValue TargetLowering::DAGCombinerInfo:: 309CombineTo(SDNode *N, SDValue Res, bool AddTo) { 310 return ((DAGCombiner*)DC)->CombineTo(N, Res, AddTo); 311} 312 313 314SDValue TargetLowering::DAGCombinerInfo:: 315CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo) { 316 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1, AddTo); 317} 318 319void TargetLowering::DAGCombinerInfo:: 320CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) { 321 return ((DAGCombiner*)DC)->CommitTargetLoweringOpt(TLO); 322} 323 324//===----------------------------------------------------------------------===// 325// Helper Functions 326//===----------------------------------------------------------------------===// 327 328/// isNegatibleForFree - Return 1 if we can compute the negated form of the 329/// specified expression for the same cost as the expression itself, or 2 if we 330/// can compute the negated form more cheaply than the expression itself. 331static char isNegatibleForFree(SDValue Op, bool LegalOperations, 332 unsigned Depth = 0) { 333 // No compile time optimizations on this type. 334 if (Op.getValueType() == MVT::ppcf128) 335 return 0; 336 337 // fneg is removable even if it has multiple uses. 338 if (Op.getOpcode() == ISD::FNEG) return 2; 339 340 // Don't allow anything with multiple uses. 341 if (!Op.hasOneUse()) return 0; 342 343 // Don't recurse exponentially. 344 if (Depth > 6) return 0; 345 346 switch (Op.getOpcode()) { 347 default: return false; 348 case ISD::ConstantFP: 349 // Don't invert constant FP values after legalize. The negated constant 350 // isn't necessarily legal. 351 return LegalOperations ? 0 : 1; 352 case ISD::FADD: 353 // FIXME: determine better conditions for this xform. 354 if (!UnsafeFPMath) return 0; 355 356 // fold (fsub (fadd A, B)) -> (fsub (fneg A), B) 357 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 358 return V; 359 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A) 360 return isNegatibleForFree(Op.getOperand(1), LegalOperations, Depth+1); 361 case ISD::FSUB: 362 // We can't turn -(A-B) into B-A when we honor signed zeros. 363 if (!UnsafeFPMath) return 0; 364 365 // fold (fneg (fsub A, B)) -> (fsub B, A) 366 return 1; 367 368 case ISD::FMUL: 369 case ISD::FDIV: 370 if (HonorSignDependentRoundingFPMath()) return 0; 371 372 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) or (fmul X, (fneg Y)) 373 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 374 return V; 375 376 return isNegatibleForFree(Op.getOperand(1), LegalOperations, Depth+1); 377 378 case ISD::FP_EXTEND: 379 case ISD::FP_ROUND: 380 case ISD::FSIN: 381 return isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1); 382 } 383} 384 385/// GetNegatedExpression - If isNegatibleForFree returns true, this function 386/// returns the newly negated expression. 387static SDValue GetNegatedExpression(SDValue Op, SelectionDAG &DAG, 388 bool LegalOperations, unsigned Depth = 0) { 389 // fneg is removable even if it has multiple uses. 390 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0); 391 392 // Don't allow anything with multiple uses. 393 assert(Op.hasOneUse() && "Unknown reuse!"); 394 395 assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree"); 396 switch (Op.getOpcode()) { 397 default: llvm_unreachable("Unknown code"); 398 case ISD::ConstantFP: { 399 APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF(); 400 V.changeSign(); 401 return DAG.getConstantFP(V, Op.getValueType()); 402 } 403 case ISD::FADD: 404 // FIXME: determine better conditions for this xform. 405 assert(UnsafeFPMath); 406 407 // fold (fneg (fadd A, B)) -> (fsub (fneg A), B) 408 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 409 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 410 GetNegatedExpression(Op.getOperand(0), DAG, 411 LegalOperations, Depth+1), 412 Op.getOperand(1)); 413 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A) 414 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 415 GetNegatedExpression(Op.getOperand(1), DAG, 416 LegalOperations, Depth+1), 417 Op.getOperand(0)); 418 case ISD::FSUB: 419 // We can't turn -(A-B) into B-A when we honor signed zeros. 420 assert(UnsafeFPMath); 421 422 // fold (fneg (fsub 0, B)) -> B 423 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(Op.getOperand(0))) 424 if (N0CFP->getValueAPF().isZero()) 425 return Op.getOperand(1); 426 427 // fold (fneg (fsub A, B)) -> (fsub B, A) 428 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 429 Op.getOperand(1), Op.getOperand(0)); 430 431 case ISD::FMUL: 432 case ISD::FDIV: 433 assert(!HonorSignDependentRoundingFPMath()); 434 435 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) 436 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 437 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 438 GetNegatedExpression(Op.getOperand(0), DAG, 439 LegalOperations, Depth+1), 440 Op.getOperand(1)); 441 442 // fold (fneg (fmul X, Y)) -> (fmul X, (fneg Y)) 443 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 444 Op.getOperand(0), 445 GetNegatedExpression(Op.getOperand(1), DAG, 446 LegalOperations, Depth+1)); 447 448 case ISD::FP_EXTEND: 449 case ISD::FSIN: 450 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 451 GetNegatedExpression(Op.getOperand(0), DAG, 452 LegalOperations, Depth+1)); 453 case ISD::FP_ROUND: 454 return DAG.getNode(ISD::FP_ROUND, Op.getDebugLoc(), Op.getValueType(), 455 GetNegatedExpression(Op.getOperand(0), DAG, 456 LegalOperations, Depth+1), 457 Op.getOperand(1)); 458 } 459} 460 461 462// isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc 463// that selects between the values 1 and 0, making it equivalent to a setcc. 464// Also, set the incoming LHS, RHS, and CC references to the appropriate 465// nodes based on the type of node we are checking. This simplifies life a 466// bit for the callers. 467static bool isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS, 468 SDValue &CC) { 469 if (N.getOpcode() == ISD::SETCC) { 470 LHS = N.getOperand(0); 471 RHS = N.getOperand(1); 472 CC = N.getOperand(2); 473 return true; 474 } 475 if (N.getOpcode() == ISD::SELECT_CC && 476 N.getOperand(2).getOpcode() == ISD::Constant && 477 N.getOperand(3).getOpcode() == ISD::Constant && 478 cast<ConstantSDNode>(N.getOperand(2))->getAPIntValue() == 1 && 479 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) { 480 LHS = N.getOperand(0); 481 RHS = N.getOperand(1); 482 CC = N.getOperand(4); 483 return true; 484 } 485 return false; 486} 487 488// isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only 489// one use. If this is true, it allows the users to invert the operation for 490// free when it is profitable to do so. 491static bool isOneUseSetCC(SDValue N) { 492 SDValue N0, N1, N2; 493 if (isSetCCEquivalent(N, N0, N1, N2) && N.getNode()->hasOneUse()) 494 return true; 495 return false; 496} 497 498SDValue DAGCombiner::ReassociateOps(unsigned Opc, DebugLoc DL, 499 SDValue N0, SDValue N1) { 500 MVT VT = N0.getValueType(); 501 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) { 502 if (isa<ConstantSDNode>(N1)) { 503 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2)) 504 SDValue OpNode = 505 DAG.FoldConstantArithmetic(Opc, VT, 506 cast<ConstantSDNode>(N0.getOperand(1)), 507 cast<ConstantSDNode>(N1)); 508 return DAG.getNode(Opc, DL, VT, N0.getOperand(0), OpNode); 509 } else if (N0.hasOneUse()) { 510 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use 511 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT, 512 N0.getOperand(0), N1); 513 AddToWorkList(OpNode.getNode()); 514 return DAG.getNode(Opc, DL, VT, OpNode, N0.getOperand(1)); 515 } 516 } 517 518 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) { 519 if (isa<ConstantSDNode>(N0)) { 520 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2)) 521 SDValue OpNode = 522 DAG.FoldConstantArithmetic(Opc, VT, 523 cast<ConstantSDNode>(N1.getOperand(1)), 524 cast<ConstantSDNode>(N0)); 525 return DAG.getNode(Opc, DL, VT, N1.getOperand(0), OpNode); 526 } else if (N1.hasOneUse()) { 527 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use 528 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT, 529 N1.getOperand(0), N0); 530 AddToWorkList(OpNode.getNode()); 531 return DAG.getNode(Opc, DL, VT, OpNode, N1.getOperand(1)); 532 } 533 } 534 535 return SDValue(); 536} 537 538SDValue DAGCombiner::CombineTo(SDNode *N, const SDValue *To, unsigned NumTo, 539 bool AddTo) { 540 assert(N->getNumValues() == NumTo && "Broken CombineTo call!"); 541 ++NodesCombined; 542 DOUT << "\nReplacing.1 "; DEBUG(N->dump(&DAG)); 543 DOUT << "\nWith: "; DEBUG(To[0].getNode()->dump(&DAG)); 544 DOUT << " and " << NumTo-1 << " other values\n"; 545 DEBUG(for (unsigned i = 0, e = NumTo; i != e; ++i) 546 assert(N->getValueType(i) == To[i].getValueType() && 547 "Cannot combine value to value of different type!")); 548 WorkListRemover DeadNodes(*this); 549 DAG.ReplaceAllUsesWith(N, To, &DeadNodes); 550 551 if (AddTo) { 552 // Push the new nodes and any users onto the worklist 553 for (unsigned i = 0, e = NumTo; i != e; ++i) { 554 if (To[i].getNode()) { 555 AddToWorkList(To[i].getNode()); 556 AddUsersToWorkList(To[i].getNode()); 557 } 558 } 559 } 560 561 // Finally, if the node is now dead, remove it from the graph. The node 562 // may not be dead if the replacement process recursively simplified to 563 // something else needing this node. 564 if (N->use_empty()) { 565 // Nodes can be reintroduced into the worklist. Make sure we do not 566 // process a node that has been replaced. 567 removeFromWorkList(N); 568 569 // Finally, since the node is now dead, remove it from the graph. 570 DAG.DeleteNode(N); 571 } 572 return SDValue(N, 0); 573} 574 575void 576DAGCombiner::CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt & 577 TLO) { 578 // Replace all uses. If any nodes become isomorphic to other nodes and 579 // are deleted, make sure to remove them from our worklist. 580 WorkListRemover DeadNodes(*this); 581 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &DeadNodes); 582 583 // Push the new node and any (possibly new) users onto the worklist. 584 AddToWorkList(TLO.New.getNode()); 585 AddUsersToWorkList(TLO.New.getNode()); 586 587 // Finally, if the node is now dead, remove it from the graph. The node 588 // may not be dead if the replacement process recursively simplified to 589 // something else needing this node. 590 if (TLO.Old.getNode()->use_empty()) { 591 removeFromWorkList(TLO.Old.getNode()); 592 593 // If the operands of this node are only used by the node, they will now 594 // be dead. Make sure to visit them first to delete dead nodes early. 595 for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands(); i != e; ++i) 596 if (TLO.Old.getNode()->getOperand(i).getNode()->hasOneUse()) 597 AddToWorkList(TLO.Old.getNode()->getOperand(i).getNode()); 598 599 DAG.DeleteNode(TLO.Old.getNode()); 600 } 601} 602 603/// SimplifyDemandedBits - Check the specified integer node value to see if 604/// it can be simplified or if things it uses can be simplified by bit 605/// propagation. If so, return true. 606bool DAGCombiner::SimplifyDemandedBits(SDValue Op, const APInt &Demanded) { 607 TargetLowering::TargetLoweringOpt TLO(DAG); 608 APInt KnownZero, KnownOne; 609 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO)) 610 return false; 611 612 // Revisit the node. 613 AddToWorkList(Op.getNode()); 614 615 // Replace the old value with the new one. 616 ++NodesCombined; 617 DOUT << "\nReplacing.2 "; DEBUG(TLO.Old.getNode()->dump(&DAG)); 618 DOUT << "\nWith: "; DEBUG(TLO.New.getNode()->dump(&DAG)); 619 DOUT << '\n'; 620 621 CommitTargetLoweringOpt(TLO); 622 return true; 623} 624 625//===----------------------------------------------------------------------===// 626// Main DAG Combiner implementation 627//===----------------------------------------------------------------------===// 628 629void DAGCombiner::Run(CombineLevel AtLevel) { 630 // set the instance variables, so that the various visit routines may use it. 631 Level = AtLevel; 632 LegalOperations = Level >= NoIllegalOperations; 633 LegalTypes = Level >= NoIllegalTypes; 634 635 // Add all the dag nodes to the worklist. 636 WorkList.reserve(DAG.allnodes_size()); 637 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 638 E = DAG.allnodes_end(); I != E; ++I) 639 WorkList.push_back(I); 640 641 // Create a dummy node (which is not added to allnodes), that adds a reference 642 // to the root node, preventing it from being deleted, and tracking any 643 // changes of the root. 644 HandleSDNode Dummy(DAG.getRoot()); 645 646 // The root of the dag may dangle to deleted nodes until the dag combiner is 647 // done. Set it to null to avoid confusion. 648 DAG.setRoot(SDValue()); 649 650 // while the worklist isn't empty, inspect the node on the end of it and 651 // try and combine it. 652 while (!WorkList.empty()) { 653 SDNode *N = WorkList.back(); 654 WorkList.pop_back(); 655 656 // If N has no uses, it is dead. Make sure to revisit all N's operands once 657 // N is deleted from the DAG, since they too may now be dead or may have a 658 // reduced number of uses, allowing other xforms. 659 if (N->use_empty() && N != &Dummy) { 660 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 661 AddToWorkList(N->getOperand(i).getNode()); 662 663 DAG.DeleteNode(N); 664 continue; 665 } 666 667 SDValue RV = combine(N); 668 669 if (RV.getNode() == 0) 670 continue; 671 672 ++NodesCombined; 673 674 // If we get back the same node we passed in, rather than a new node or 675 // zero, we know that the node must have defined multiple values and 676 // CombineTo was used. Since CombineTo takes care of the worklist 677 // mechanics for us, we have no work to do in this case. 678 if (RV.getNode() == N) 679 continue; 680 681 assert(N->getOpcode() != ISD::DELETED_NODE && 682 RV.getNode()->getOpcode() != ISD::DELETED_NODE && 683 "Node was deleted but visit returned new node!"); 684 685 DOUT << "\nReplacing.3 "; DEBUG(N->dump(&DAG)); 686 DOUT << "\nWith: "; DEBUG(RV.getNode()->dump(&DAG)); 687 DOUT << '\n'; 688 WorkListRemover DeadNodes(*this); 689 if (N->getNumValues() == RV.getNode()->getNumValues()) 690 DAG.ReplaceAllUsesWith(N, RV.getNode(), &DeadNodes); 691 else { 692 assert(N->getValueType(0) == RV.getValueType() && 693 N->getNumValues() == 1 && "Type mismatch"); 694 SDValue OpV = RV; 695 DAG.ReplaceAllUsesWith(N, &OpV, &DeadNodes); 696 } 697 698 // Push the new node and any users onto the worklist 699 AddToWorkList(RV.getNode()); 700 AddUsersToWorkList(RV.getNode()); 701 702 // Add any uses of the old node to the worklist in case this node is the 703 // last one that uses them. They may become dead after this node is 704 // deleted. 705 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 706 AddToWorkList(N->getOperand(i).getNode()); 707 708 // Finally, if the node is now dead, remove it from the graph. The node 709 // may not be dead if the replacement process recursively simplified to 710 // something else needing this node. 711 if (N->use_empty()) { 712 // Nodes can be reintroduced into the worklist. Make sure we do not 713 // process a node that has been replaced. 714 removeFromWorkList(N); 715 716 // Finally, since the node is now dead, remove it from the graph. 717 DAG.DeleteNode(N); 718 } 719 } 720 721 // If the root changed (e.g. it was a dead load, update the root). 722 DAG.setRoot(Dummy.getValue()); 723} 724 725SDValue DAGCombiner::visit(SDNode *N) { 726 switch(N->getOpcode()) { 727 default: break; 728 case ISD::TokenFactor: return visitTokenFactor(N); 729 case ISD::MERGE_VALUES: return visitMERGE_VALUES(N); 730 case ISD::ADD: return visitADD(N); 731 case ISD::SUB: return visitSUB(N); 732 case ISD::ADDC: return visitADDC(N); 733 case ISD::ADDE: return visitADDE(N); 734 case ISD::MUL: return visitMUL(N); 735 case ISD::SDIV: return visitSDIV(N); 736 case ISD::UDIV: return visitUDIV(N); 737 case ISD::SREM: return visitSREM(N); 738 case ISD::UREM: return visitUREM(N); 739 case ISD::MULHU: return visitMULHU(N); 740 case ISD::MULHS: return visitMULHS(N); 741 case ISD::SMUL_LOHI: return visitSMUL_LOHI(N); 742 case ISD::UMUL_LOHI: return visitUMUL_LOHI(N); 743 case ISD::SDIVREM: return visitSDIVREM(N); 744 case ISD::UDIVREM: return visitUDIVREM(N); 745 case ISD::AND: return visitAND(N); 746 case ISD::OR: return visitOR(N); 747 case ISD::XOR: return visitXOR(N); 748 case ISD::SHL: return visitSHL(N); 749 case ISD::SRA: return visitSRA(N); 750 case ISD::SRL: return visitSRL(N); 751 case ISD::CTLZ: return visitCTLZ(N); 752 case ISD::CTTZ: return visitCTTZ(N); 753 case ISD::CTPOP: return visitCTPOP(N); 754 case ISD::SELECT: return visitSELECT(N); 755 case ISD::SELECT_CC: return visitSELECT_CC(N); 756 case ISD::SETCC: return visitSETCC(N); 757 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N); 758 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N); 759 case ISD::ANY_EXTEND: return visitANY_EXTEND(N); 760 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N); 761 case ISD::TRUNCATE: return visitTRUNCATE(N); 762 case ISD::BIT_CONVERT: return visitBIT_CONVERT(N); 763 case ISD::BUILD_PAIR: return visitBUILD_PAIR(N); 764 case ISD::FADD: return visitFADD(N); 765 case ISD::FSUB: return visitFSUB(N); 766 case ISD::FMUL: return visitFMUL(N); 767 case ISD::FDIV: return visitFDIV(N); 768 case ISD::FREM: return visitFREM(N); 769 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N); 770 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N); 771 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N); 772 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N); 773 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N); 774 case ISD::FP_ROUND: return visitFP_ROUND(N); 775 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N); 776 case ISD::FP_EXTEND: return visitFP_EXTEND(N); 777 case ISD::FNEG: return visitFNEG(N); 778 case ISD::FABS: return visitFABS(N); 779 case ISD::BRCOND: return visitBRCOND(N); 780 case ISD::BR_CC: return visitBR_CC(N); 781 case ISD::LOAD: return visitLOAD(N); 782 case ISD::STORE: return visitSTORE(N); 783 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N); 784 case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N); 785 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N); 786 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N); 787 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N); 788 } 789 return SDValue(); 790} 791 792SDValue DAGCombiner::combine(SDNode *N) { 793 SDValue RV = visit(N); 794 795 // If nothing happened, try a target-specific DAG combine. 796 if (RV.getNode() == 0) { 797 assert(N->getOpcode() != ISD::DELETED_NODE && 798 "Node was deleted but visit returned NULL!"); 799 800 if (N->getOpcode() >= ISD::BUILTIN_OP_END || 801 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) { 802 803 // Expose the DAG combiner to the target combiner impls. 804 TargetLowering::DAGCombinerInfo 805 DagCombineInfo(DAG, !LegalTypes, !LegalOperations, false, this); 806 807 RV = TLI.PerformDAGCombine(N, DagCombineInfo); 808 } 809 } 810 811 // If N is a commutative binary node, try commuting it to enable more 812 // sdisel CSE. 813 if (RV.getNode() == 0 && 814 SelectionDAG::isCommutativeBinOp(N->getOpcode()) && 815 N->getNumValues() == 1) { 816 SDValue N0 = N->getOperand(0); 817 SDValue N1 = N->getOperand(1); 818 819 // Constant operands are canonicalized to RHS. 820 if (isa<ConstantSDNode>(N0) || !isa<ConstantSDNode>(N1)) { 821 SDValue Ops[] = { N1, N0 }; 822 SDNode *CSENode = DAG.getNodeIfExists(N->getOpcode(), N->getVTList(), 823 Ops, 2); 824 if (CSENode) 825 return SDValue(CSENode, 0); 826 } 827 } 828 829 return RV; 830} 831 832/// getInputChainForNode - Given a node, return its input chain if it has one, 833/// otherwise return a null sd operand. 834static SDValue getInputChainForNode(SDNode *N) { 835 if (unsigned NumOps = N->getNumOperands()) { 836 if (N->getOperand(0).getValueType() == MVT::Other) 837 return N->getOperand(0); 838 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other) 839 return N->getOperand(NumOps-1); 840 for (unsigned i = 1; i < NumOps-1; ++i) 841 if (N->getOperand(i).getValueType() == MVT::Other) 842 return N->getOperand(i); 843 } 844 return SDValue(); 845} 846 847SDValue DAGCombiner::visitTokenFactor(SDNode *N) { 848 // If N has two operands, where one has an input chain equal to the other, 849 // the 'other' chain is redundant. 850 if (N->getNumOperands() == 2) { 851 if (getInputChainForNode(N->getOperand(0).getNode()) == N->getOperand(1)) 852 return N->getOperand(0); 853 if (getInputChainForNode(N->getOperand(1).getNode()) == N->getOperand(0)) 854 return N->getOperand(1); 855 } 856 857 SmallVector<SDNode *, 8> TFs; // List of token factors to visit. 858 SmallVector<SDValue, 8> Ops; // Ops for replacing token factor. 859 SmallPtrSet<SDNode*, 16> SeenOps; 860 bool Changed = false; // If we should replace this token factor. 861 862 // Start out with this token factor. 863 TFs.push_back(N); 864 865 // Iterate through token factors. The TFs grows when new token factors are 866 // encountered. 867 for (unsigned i = 0; i < TFs.size(); ++i) { 868 SDNode *TF = TFs[i]; 869 870 // Check each of the operands. 871 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) { 872 SDValue Op = TF->getOperand(i); 873 874 switch (Op.getOpcode()) { 875 case ISD::EntryToken: 876 // Entry tokens don't need to be added to the list. They are 877 // rededundant. 878 Changed = true; 879 break; 880 881 case ISD::TokenFactor: 882 if ((CombinerAA || Op.hasOneUse()) && 883 std::find(TFs.begin(), TFs.end(), Op.getNode()) == TFs.end()) { 884 // Queue up for processing. 885 TFs.push_back(Op.getNode()); 886 // Clean up in case the token factor is removed. 887 AddToWorkList(Op.getNode()); 888 Changed = true; 889 break; 890 } 891 // Fall thru 892 893 default: 894 // Only add if it isn't already in the list. 895 if (SeenOps.insert(Op.getNode())) 896 Ops.push_back(Op); 897 else 898 Changed = true; 899 break; 900 } 901 } 902 } 903 904 SDValue Result; 905 906 // If we've change things around then replace token factor. 907 if (Changed) { 908 if (Ops.empty()) { 909 // The entry token is the only possible outcome. 910 Result = DAG.getEntryNode(); 911 } else { 912 // New and improved token factor. 913 Result = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 914 MVT::Other, &Ops[0], Ops.size()); 915 } 916 917 // Don't add users to work list. 918 return CombineTo(N, Result, false); 919 } 920 921 return Result; 922} 923 924/// MERGE_VALUES can always be eliminated. 925SDValue DAGCombiner::visitMERGE_VALUES(SDNode *N) { 926 WorkListRemover DeadNodes(*this); 927 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 928 DAG.ReplaceAllUsesOfValueWith(SDValue(N, i), N->getOperand(i), 929 &DeadNodes); 930 removeFromWorkList(N); 931 DAG.DeleteNode(N); 932 return SDValue(N, 0); // Return N so it doesn't get rechecked! 933} 934 935static 936SDValue combineShlAddConstant(DebugLoc DL, SDValue N0, SDValue N1, 937 SelectionDAG &DAG) { 938 MVT VT = N0.getValueType(); 939 SDValue N00 = N0.getOperand(0); 940 SDValue N01 = N0.getOperand(1); 941 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01); 942 943 if (N01C && N00.getOpcode() == ISD::ADD && N00.getNode()->hasOneUse() && 944 isa<ConstantSDNode>(N00.getOperand(1))) { 945 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 946 N0 = DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, 947 DAG.getNode(ISD::SHL, N00.getDebugLoc(), VT, 948 N00.getOperand(0), N01), 949 DAG.getNode(ISD::SHL, N01.getDebugLoc(), VT, 950 N00.getOperand(1), N01)); 951 return DAG.getNode(ISD::ADD, DL, VT, N0, N1); 952 } 953 954 return SDValue(); 955} 956 957SDValue DAGCombiner::visitADD(SDNode *N) { 958 SDValue N0 = N->getOperand(0); 959 SDValue N1 = N->getOperand(1); 960 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 961 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 962 MVT VT = N0.getValueType(); 963 964 // fold vector ops 965 if (VT.isVector()) { 966 SDValue FoldedVOp = SimplifyVBinOp(N); 967 if (FoldedVOp.getNode()) return FoldedVOp; 968 } 969 970 // fold (add x, undef) -> undef 971 if (N0.getOpcode() == ISD::UNDEF) 972 return N0; 973 if (N1.getOpcode() == ISD::UNDEF) 974 return N1; 975 // fold (add c1, c2) -> c1+c2 976 if (N0C && N1C) 977 return DAG.FoldConstantArithmetic(ISD::ADD, VT, N0C, N1C); 978 // canonicalize constant to RHS 979 if (N0C && !N1C) 980 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0); 981 // fold (add x, 0) -> x 982 if (N1C && N1C->isNullValue()) 983 return N0; 984 // fold (add Sym, c) -> Sym+c 985 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0)) 986 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA) && N1C && 987 GA->getOpcode() == ISD::GlobalAddress) 988 return DAG.getGlobalAddress(GA->getGlobal(), VT, 989 GA->getOffset() + 990 (uint64_t)N1C->getSExtValue()); 991 // fold ((c1-A)+c2) -> (c1+c2)-A 992 if (N1C && N0.getOpcode() == ISD::SUB) 993 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0))) 994 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 995 DAG.getConstant(N1C->getAPIntValue()+ 996 N0C->getAPIntValue(), VT), 997 N0.getOperand(1)); 998 // reassociate add 999 SDValue RADD = ReassociateOps(ISD::ADD, N->getDebugLoc(), N0, N1); 1000 if (RADD.getNode() != 0) 1001 return RADD; 1002 // fold ((0-A) + B) -> B-A 1003 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) && 1004 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue()) 1005 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1, N0.getOperand(1)); 1006 // fold (A + (0-B)) -> A-B 1007 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) && 1008 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue()) 1009 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, N1.getOperand(1)); 1010 // fold (A+(B-A)) -> B 1011 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1)) 1012 return N1.getOperand(0); 1013 // fold ((B-A)+A) -> B 1014 if (N0.getOpcode() == ISD::SUB && N1 == N0.getOperand(1)) 1015 return N0.getOperand(0); 1016 // fold (A+(B-(A+C))) to (B-C) 1017 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD && 1018 N0 == N1.getOperand(1).getOperand(0)) 1019 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0), 1020 N1.getOperand(1).getOperand(1)); 1021 // fold (A+(B-(C+A))) to (B-C) 1022 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD && 1023 N0 == N1.getOperand(1).getOperand(1)) 1024 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0), 1025 N1.getOperand(1).getOperand(0)); 1026 // fold (A+((B-A)+or-C)) to (B+or-C) 1027 if ((N1.getOpcode() == ISD::SUB || N1.getOpcode() == ISD::ADD) && 1028 N1.getOperand(0).getOpcode() == ISD::SUB && 1029 N0 == N1.getOperand(0).getOperand(1)) 1030 return DAG.getNode(N1.getOpcode(), N->getDebugLoc(), VT, 1031 N1.getOperand(0).getOperand(0), N1.getOperand(1)); 1032 1033 // fold (A-B)+(C-D) to (A+C)-(B+D) when A or C is constant 1034 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB) { 1035 SDValue N00 = N0.getOperand(0); 1036 SDValue N01 = N0.getOperand(1); 1037 SDValue N10 = N1.getOperand(0); 1038 SDValue N11 = N1.getOperand(1); 1039 1040 if (isa<ConstantSDNode>(N00) || isa<ConstantSDNode>(N10)) 1041 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1042 DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, N00, N10), 1043 DAG.getNode(ISD::ADD, N1.getDebugLoc(), VT, N01, N11)); 1044 } 1045 1046 if (!VT.isVector() && SimplifyDemandedBits(SDValue(N, 0))) 1047 return SDValue(N, 0); 1048 1049 // fold (a+b) -> (a|b) iff a and b share no bits. 1050 if (VT.isInteger() && !VT.isVector()) { 1051 APInt LHSZero, LHSOne; 1052 APInt RHSZero, RHSOne; 1053 APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits()); 1054 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 1055 1056 if (LHSZero.getBoolValue()) { 1057 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 1058 1059 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1060 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1061 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 1062 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 1063 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1); 1064 } 1065 } 1066 1067 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 1068 if (N0.getOpcode() == ISD::SHL && N0.getNode()->hasOneUse()) { 1069 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N0, N1, DAG); 1070 if (Result.getNode()) return Result; 1071 } 1072 if (N1.getOpcode() == ISD::SHL && N1.getNode()->hasOneUse()) { 1073 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N1, N0, DAG); 1074 if (Result.getNode()) return Result; 1075 } 1076 1077 return SDValue(); 1078} 1079 1080SDValue DAGCombiner::visitADDC(SDNode *N) { 1081 SDValue N0 = N->getOperand(0); 1082 SDValue N1 = N->getOperand(1); 1083 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1084 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1085 MVT VT = N0.getValueType(); 1086 1087 // If the flag result is dead, turn this into an ADD. 1088 if (N->hasNUsesOfValue(0, 1)) 1089 return CombineTo(N, DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0), 1090 DAG.getNode(ISD::CARRY_FALSE, 1091 N->getDebugLoc(), MVT::Flag)); 1092 1093 // canonicalize constant to RHS. 1094 if (N0C && !N1C) 1095 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0); 1096 1097 // fold (addc x, 0) -> x + no carry out 1098 if (N1C && N1C->isNullValue()) 1099 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, 1100 N->getDebugLoc(), MVT::Flag)); 1101 1102 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits. 1103 APInt LHSZero, LHSOne; 1104 APInt RHSZero, RHSOne; 1105 APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits()); 1106 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 1107 1108 if (LHSZero.getBoolValue()) { 1109 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 1110 1111 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1112 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1113 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 1114 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 1115 return CombineTo(N, DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1), 1116 DAG.getNode(ISD::CARRY_FALSE, 1117 N->getDebugLoc(), MVT::Flag)); 1118 } 1119 1120 return SDValue(); 1121} 1122 1123SDValue DAGCombiner::visitADDE(SDNode *N) { 1124 SDValue N0 = N->getOperand(0); 1125 SDValue N1 = N->getOperand(1); 1126 SDValue CarryIn = N->getOperand(2); 1127 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1128 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1129 1130 // canonicalize constant to RHS 1131 if (N0C && !N1C) 1132 return DAG.getNode(ISD::ADDE, N->getDebugLoc(), N->getVTList(), 1133 N1, N0, CarryIn); 1134 1135 // fold (adde x, y, false) -> (addc x, y) 1136 if (CarryIn.getOpcode() == ISD::CARRY_FALSE) 1137 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0); 1138 1139 return SDValue(); 1140} 1141 1142SDValue DAGCombiner::visitSUB(SDNode *N) { 1143 SDValue N0 = N->getOperand(0); 1144 SDValue N1 = N->getOperand(1); 1145 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1146 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1147 MVT VT = N0.getValueType(); 1148 1149 // fold vector ops 1150 if (VT.isVector()) { 1151 SDValue FoldedVOp = SimplifyVBinOp(N); 1152 if (FoldedVOp.getNode()) return FoldedVOp; 1153 } 1154 1155 // fold (sub x, x) -> 0 1156 if (N0 == N1) 1157 return DAG.getConstant(0, N->getValueType(0)); 1158 // fold (sub c1, c2) -> c1-c2 1159 if (N0C && N1C) 1160 return DAG.FoldConstantArithmetic(ISD::SUB, VT, N0C, N1C); 1161 // fold (sub x, c) -> (add x, -c) 1162 if (N1C) 1163 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, 1164 DAG.getConstant(-N1C->getAPIntValue(), VT)); 1165 // fold (A+B)-A -> B 1166 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1) 1167 return N0.getOperand(1); 1168 // fold (A+B)-B -> A 1169 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1) 1170 return N0.getOperand(0); 1171 // fold ((A+(B+or-C))-B) -> A+or-C 1172 if (N0.getOpcode() == ISD::ADD && 1173 (N0.getOperand(1).getOpcode() == ISD::SUB || 1174 N0.getOperand(1).getOpcode() == ISD::ADD) && 1175 N0.getOperand(1).getOperand(0) == N1) 1176 return DAG.getNode(N0.getOperand(1).getOpcode(), N->getDebugLoc(), VT, 1177 N0.getOperand(0), N0.getOperand(1).getOperand(1)); 1178 // fold ((A+(C+B))-B) -> A+C 1179 if (N0.getOpcode() == ISD::ADD && 1180 N0.getOperand(1).getOpcode() == ISD::ADD && 1181 N0.getOperand(1).getOperand(1) == N1) 1182 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, 1183 N0.getOperand(0), N0.getOperand(1).getOperand(0)); 1184 // fold ((A-(B-C))-C) -> A-B 1185 if (N0.getOpcode() == ISD::SUB && 1186 N0.getOperand(1).getOpcode() == ISD::SUB && 1187 N0.getOperand(1).getOperand(1) == N1) 1188 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1189 N0.getOperand(0), N0.getOperand(1).getOperand(0)); 1190 1191 // If either operand of a sub is undef, the result is undef 1192 if (N0.getOpcode() == ISD::UNDEF) 1193 return N0; 1194 if (N1.getOpcode() == ISD::UNDEF) 1195 return N1; 1196 1197 // If the relocation model supports it, consider symbol offsets. 1198 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0)) 1199 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA)) { 1200 // fold (sub Sym, c) -> Sym-c 1201 if (N1C && GA->getOpcode() == ISD::GlobalAddress) 1202 return DAG.getGlobalAddress(GA->getGlobal(), VT, 1203 GA->getOffset() - 1204 (uint64_t)N1C->getSExtValue()); 1205 // fold (sub Sym+c1, Sym+c2) -> c1-c2 1206 if (GlobalAddressSDNode *GB = dyn_cast<GlobalAddressSDNode>(N1)) 1207 if (GA->getGlobal() == GB->getGlobal()) 1208 return DAG.getConstant((uint64_t)GA->getOffset() - GB->getOffset(), 1209 VT); 1210 } 1211 1212 return SDValue(); 1213} 1214 1215SDValue DAGCombiner::visitMUL(SDNode *N) { 1216 SDValue N0 = N->getOperand(0); 1217 SDValue N1 = N->getOperand(1); 1218 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1219 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1220 MVT VT = N0.getValueType(); 1221 1222 // fold vector ops 1223 if (VT.isVector()) { 1224 SDValue FoldedVOp = SimplifyVBinOp(N); 1225 if (FoldedVOp.getNode()) return FoldedVOp; 1226 } 1227 1228 // fold (mul x, undef) -> 0 1229 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1230 return DAG.getConstant(0, VT); 1231 // fold (mul c1, c2) -> c1*c2 1232 if (N0C && N1C) 1233 return DAG.FoldConstantArithmetic(ISD::MUL, VT, N0C, N1C); 1234 // canonicalize constant to RHS 1235 if (N0C && !N1C) 1236 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, N1, N0); 1237 // fold (mul x, 0) -> 0 1238 if (N1C && N1C->isNullValue()) 1239 return N1; 1240 // fold (mul x, -1) -> 0-x 1241 if (N1C && N1C->isAllOnesValue()) 1242 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1243 DAG.getConstant(0, VT), N0); 1244 // fold (mul x, (1 << c)) -> x << c 1245 if (N1C && N1C->getAPIntValue().isPowerOf2()) 1246 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 1247 DAG.getConstant(N1C->getAPIntValue().logBase2(), 1248 getShiftAmountTy())); 1249 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c 1250 if (N1C && (-N1C->getAPIntValue()).isPowerOf2()) { 1251 unsigned Log2Val = (-N1C->getAPIntValue()).logBase2(); 1252 // FIXME: If the input is something that is easily negated (e.g. a 1253 // single-use add), we should put the negate there. 1254 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1255 DAG.getConstant(0, VT), 1256 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 1257 DAG.getConstant(Log2Val, getShiftAmountTy()))); 1258 } 1259 // (mul (shl X, c1), c2) -> (mul X, c2 << c1) 1260 if (N1C && N0.getOpcode() == ISD::SHL && 1261 isa<ConstantSDNode>(N0.getOperand(1))) { 1262 SDValue C3 = DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1263 N1, N0.getOperand(1)); 1264 AddToWorkList(C3.getNode()); 1265 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1266 N0.getOperand(0), C3); 1267 } 1268 1269 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one 1270 // use. 1271 { 1272 SDValue Sh(0,0), Y(0,0); 1273 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)). 1274 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) && 1275 N0.getNode()->hasOneUse()) { 1276 Sh = N0; Y = N1; 1277 } else if (N1.getOpcode() == ISD::SHL && 1278 isa<ConstantSDNode>(N1.getOperand(1)) && 1279 N1.getNode()->hasOneUse()) { 1280 Sh = N1; Y = N0; 1281 } 1282 1283 if (Sh.getNode()) { 1284 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1285 Sh.getOperand(0), Y); 1286 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1287 Mul, Sh.getOperand(1)); 1288 } 1289 } 1290 1291 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2) 1292 if (N1C && N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse() && 1293 isa<ConstantSDNode>(N0.getOperand(1))) 1294 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, 1295 DAG.getNode(ISD::MUL, N0.getDebugLoc(), VT, 1296 N0.getOperand(0), N1), 1297 DAG.getNode(ISD::MUL, N1.getDebugLoc(), VT, 1298 N0.getOperand(1), N1)); 1299 1300 // reassociate mul 1301 SDValue RMUL = ReassociateOps(ISD::MUL, N->getDebugLoc(), N0, N1); 1302 if (RMUL.getNode() != 0) 1303 return RMUL; 1304 1305 return SDValue(); 1306} 1307 1308SDValue DAGCombiner::visitSDIV(SDNode *N) { 1309 SDValue N0 = N->getOperand(0); 1310 SDValue N1 = N->getOperand(1); 1311 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1312 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1313 MVT VT = N->getValueType(0); 1314 1315 // fold vector ops 1316 if (VT.isVector()) { 1317 SDValue FoldedVOp = SimplifyVBinOp(N); 1318 if (FoldedVOp.getNode()) return FoldedVOp; 1319 } 1320 1321 // fold (sdiv c1, c2) -> c1/c2 1322 if (N0C && N1C && !N1C->isNullValue()) 1323 return DAG.FoldConstantArithmetic(ISD::SDIV, VT, N0C, N1C); 1324 // fold (sdiv X, 1) -> X 1325 if (N1C && N1C->getSExtValue() == 1LL) 1326 return N0; 1327 // fold (sdiv X, -1) -> 0-X 1328 if (N1C && N1C->isAllOnesValue()) 1329 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1330 DAG.getConstant(0, VT), N0); 1331 // If we know the sign bits of both operands are zero, strength reduce to a 1332 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2 1333 if (!VT.isVector()) { 1334 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 1335 return DAG.getNode(ISD::UDIV, N->getDebugLoc(), N1.getValueType(), 1336 N0, N1); 1337 } 1338 // fold (sdiv X, pow2) -> simple ops after legalize 1339 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap() && 1340 (isPowerOf2_64(N1C->getSExtValue()) || 1341 isPowerOf2_64(-N1C->getSExtValue()))) { 1342 // If dividing by powers of two is cheap, then don't perform the following 1343 // fold. 1344 if (TLI.isPow2DivCheap()) 1345 return SDValue(); 1346 1347 int64_t pow2 = N1C->getSExtValue(); 1348 int64_t abs2 = pow2 > 0 ? pow2 : -pow2; 1349 unsigned lg2 = Log2_64(abs2); 1350 1351 // Splat the sign bit into the register 1352 SDValue SGN = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0, 1353 DAG.getConstant(VT.getSizeInBits()-1, 1354 getShiftAmountTy())); 1355 AddToWorkList(SGN.getNode()); 1356 1357 // Add (N0 < 0) ? abs2 - 1 : 0; 1358 SDValue SRL = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, SGN, 1359 DAG.getConstant(VT.getSizeInBits() - lg2, 1360 getShiftAmountTy())); 1361 SDValue ADD = DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, SRL); 1362 AddToWorkList(SRL.getNode()); 1363 AddToWorkList(ADD.getNode()); // Divide by pow2 1364 SDValue SRA = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, ADD, 1365 DAG.getConstant(lg2, getShiftAmountTy())); 1366 1367 // If we're dividing by a positive value, we're done. Otherwise, we must 1368 // negate the result. 1369 if (pow2 > 0) 1370 return SRA; 1371 1372 AddToWorkList(SRA.getNode()); 1373 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1374 DAG.getConstant(0, VT), SRA); 1375 } 1376 1377 // if integer divide is expensive and we satisfy the requirements, emit an 1378 // alternate sequence. 1379 if (N1C && (N1C->getSExtValue() < -1 || N1C->getSExtValue() > 1) && 1380 !TLI.isIntDivCheap()) { 1381 SDValue Op = BuildSDIV(N); 1382 if (Op.getNode()) return Op; 1383 } 1384 1385 // undef / X -> 0 1386 if (N0.getOpcode() == ISD::UNDEF) 1387 return DAG.getConstant(0, VT); 1388 // X / undef -> undef 1389 if (N1.getOpcode() == ISD::UNDEF) 1390 return N1; 1391 1392 return SDValue(); 1393} 1394 1395SDValue DAGCombiner::visitUDIV(SDNode *N) { 1396 SDValue N0 = N->getOperand(0); 1397 SDValue N1 = N->getOperand(1); 1398 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1399 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1400 MVT VT = N->getValueType(0); 1401 1402 // fold vector ops 1403 if (VT.isVector()) { 1404 SDValue FoldedVOp = SimplifyVBinOp(N); 1405 if (FoldedVOp.getNode()) return FoldedVOp; 1406 } 1407 1408 // fold (udiv c1, c2) -> c1/c2 1409 if (N0C && N1C && !N1C->isNullValue()) 1410 return DAG.FoldConstantArithmetic(ISD::UDIV, VT, N0C, N1C); 1411 // fold (udiv x, (1 << c)) -> x >>u c 1412 if (N1C && N1C->getAPIntValue().isPowerOf2()) 1413 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, 1414 DAG.getConstant(N1C->getAPIntValue().logBase2(), 1415 getShiftAmountTy())); 1416 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2 1417 if (N1.getOpcode() == ISD::SHL) { 1418 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1419 if (SHC->getAPIntValue().isPowerOf2()) { 1420 MVT ADDVT = N1.getOperand(1).getValueType(); 1421 SDValue Add = DAG.getNode(ISD::ADD, N->getDebugLoc(), ADDVT, 1422 N1.getOperand(1), 1423 DAG.getConstant(SHC->getAPIntValue() 1424 .logBase2(), 1425 ADDVT)); 1426 AddToWorkList(Add.getNode()); 1427 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, Add); 1428 } 1429 } 1430 } 1431 // fold (udiv x, c) -> alternate 1432 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) { 1433 SDValue Op = BuildUDIV(N); 1434 if (Op.getNode()) return Op; 1435 } 1436 1437 // undef / X -> 0 1438 if (N0.getOpcode() == ISD::UNDEF) 1439 return DAG.getConstant(0, VT); 1440 // X / undef -> undef 1441 if (N1.getOpcode() == ISD::UNDEF) 1442 return N1; 1443 1444 return SDValue(); 1445} 1446 1447SDValue DAGCombiner::visitSREM(SDNode *N) { 1448 SDValue N0 = N->getOperand(0); 1449 SDValue N1 = N->getOperand(1); 1450 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1451 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1452 MVT VT = N->getValueType(0); 1453 1454 // fold (srem c1, c2) -> c1%c2 1455 if (N0C && N1C && !N1C->isNullValue()) 1456 return DAG.FoldConstantArithmetic(ISD::SREM, VT, N0C, N1C); 1457 // If we know the sign bits of both operands are zero, strength reduce to a 1458 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15 1459 if (!VT.isVector()) { 1460 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 1461 return DAG.getNode(ISD::UREM, N->getDebugLoc(), VT, N0, N1); 1462 } 1463 1464 // If X/C can be simplified by the division-by-constant logic, lower 1465 // X%C to the equivalent of X-X/C*C. 1466 if (N1C && !N1C->isNullValue()) { 1467 SDValue Div = DAG.getNode(ISD::SDIV, N->getDebugLoc(), VT, N0, N1); 1468 AddToWorkList(Div.getNode()); 1469 SDValue OptimizedDiv = combine(Div.getNode()); 1470 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) { 1471 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1472 OptimizedDiv, N1); 1473 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul); 1474 AddToWorkList(Mul.getNode()); 1475 return Sub; 1476 } 1477 } 1478 1479 // undef % X -> 0 1480 if (N0.getOpcode() == ISD::UNDEF) 1481 return DAG.getConstant(0, VT); 1482 // X % undef -> undef 1483 if (N1.getOpcode() == ISD::UNDEF) 1484 return N1; 1485 1486 return SDValue(); 1487} 1488 1489SDValue DAGCombiner::visitUREM(SDNode *N) { 1490 SDValue N0 = N->getOperand(0); 1491 SDValue N1 = N->getOperand(1); 1492 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1493 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1494 MVT VT = N->getValueType(0); 1495 1496 // fold (urem c1, c2) -> c1%c2 1497 if (N0C && N1C && !N1C->isNullValue()) 1498 return DAG.FoldConstantArithmetic(ISD::UREM, VT, N0C, N1C); 1499 // fold (urem x, pow2) -> (and x, pow2-1) 1500 if (N1C && !N1C->isNullValue() && N1C->getAPIntValue().isPowerOf2()) 1501 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, 1502 DAG.getConstant(N1C->getAPIntValue()-1,VT)); 1503 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1)) 1504 if (N1.getOpcode() == ISD::SHL) { 1505 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1506 if (SHC->getAPIntValue().isPowerOf2()) { 1507 SDValue Add = 1508 DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, 1509 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), 1510 VT)); 1511 AddToWorkList(Add.getNode()); 1512 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, Add); 1513 } 1514 } 1515 } 1516 1517 // If X/C can be simplified by the division-by-constant logic, lower 1518 // X%C to the equivalent of X-X/C*C. 1519 if (N1C && !N1C->isNullValue()) { 1520 SDValue Div = DAG.getNode(ISD::UDIV, N->getDebugLoc(), VT, N0, N1); 1521 AddToWorkList(Div.getNode()); 1522 SDValue OptimizedDiv = combine(Div.getNode()); 1523 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) { 1524 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1525 OptimizedDiv, N1); 1526 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul); 1527 AddToWorkList(Mul.getNode()); 1528 return Sub; 1529 } 1530 } 1531 1532 // undef % X -> 0 1533 if (N0.getOpcode() == ISD::UNDEF) 1534 return DAG.getConstant(0, VT); 1535 // X % undef -> undef 1536 if (N1.getOpcode() == ISD::UNDEF) 1537 return N1; 1538 1539 return SDValue(); 1540} 1541 1542SDValue DAGCombiner::visitMULHS(SDNode *N) { 1543 SDValue N0 = N->getOperand(0); 1544 SDValue N1 = N->getOperand(1); 1545 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1546 MVT VT = N->getValueType(0); 1547 1548 // fold (mulhs x, 0) -> 0 1549 if (N1C && N1C->isNullValue()) 1550 return N1; 1551 // fold (mulhs x, 1) -> (sra x, size(x)-1) 1552 if (N1C && N1C->getAPIntValue() == 1) 1553 return DAG.getNode(ISD::SRA, N->getDebugLoc(), N0.getValueType(), N0, 1554 DAG.getConstant(N0.getValueType().getSizeInBits() - 1, 1555 getShiftAmountTy())); 1556 // fold (mulhs x, undef) -> 0 1557 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1558 return DAG.getConstant(0, VT); 1559 1560 return SDValue(); 1561} 1562 1563SDValue DAGCombiner::visitMULHU(SDNode *N) { 1564 SDValue N0 = N->getOperand(0); 1565 SDValue N1 = N->getOperand(1); 1566 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1567 MVT VT = N->getValueType(0); 1568 1569 // fold (mulhu x, 0) -> 0 1570 if (N1C && N1C->isNullValue()) 1571 return N1; 1572 // fold (mulhu x, 1) -> 0 1573 if (N1C && N1C->getAPIntValue() == 1) 1574 return DAG.getConstant(0, N0.getValueType()); 1575 // fold (mulhu x, undef) -> 0 1576 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1577 return DAG.getConstant(0, VT); 1578 1579 return SDValue(); 1580} 1581 1582/// SimplifyNodeWithTwoResults - Perform optimizations common to nodes that 1583/// compute two values. LoOp and HiOp give the opcodes for the two computations 1584/// that are being performed. Return true if a simplification was made. 1585/// 1586SDValue DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 1587 unsigned HiOp) { 1588 // If the high half is not needed, just compute the low half. 1589 bool HiExists = N->hasAnyUseOfValue(1); 1590 if (!HiExists && 1591 (!LegalOperations || 1592 TLI.isOperationLegal(LoOp, N->getValueType(0)))) { 1593 SDValue Res = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0), 1594 N->op_begin(), N->getNumOperands()); 1595 return CombineTo(N, Res, Res); 1596 } 1597 1598 // If the low half is not needed, just compute the high half. 1599 bool LoExists = N->hasAnyUseOfValue(0); 1600 if (!LoExists && 1601 (!LegalOperations || 1602 TLI.isOperationLegal(HiOp, N->getValueType(1)))) { 1603 SDValue Res = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1), 1604 N->op_begin(), N->getNumOperands()); 1605 return CombineTo(N, Res, Res); 1606 } 1607 1608 // If both halves are used, return as it is. 1609 if (LoExists && HiExists) 1610 return SDValue(); 1611 1612 // If the two computed results can be simplified separately, separate them. 1613 if (LoExists) { 1614 SDValue Lo = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0), 1615 N->op_begin(), N->getNumOperands()); 1616 AddToWorkList(Lo.getNode()); 1617 SDValue LoOpt = combine(Lo.getNode()); 1618 if (LoOpt.getNode() && LoOpt.getNode() != Lo.getNode() && 1619 (!LegalOperations || 1620 TLI.isOperationLegal(LoOpt.getOpcode(), LoOpt.getValueType()))) 1621 return CombineTo(N, LoOpt, LoOpt); 1622 } 1623 1624 if (HiExists) { 1625 SDValue Hi = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1), 1626 N->op_begin(), N->getNumOperands()); 1627 AddToWorkList(Hi.getNode()); 1628 SDValue HiOpt = combine(Hi.getNode()); 1629 if (HiOpt.getNode() && HiOpt != Hi && 1630 (!LegalOperations || 1631 TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType()))) 1632 return CombineTo(N, HiOpt, HiOpt); 1633 } 1634 1635 return SDValue(); 1636} 1637 1638SDValue DAGCombiner::visitSMUL_LOHI(SDNode *N) { 1639 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS); 1640 if (Res.getNode()) return Res; 1641 1642 return SDValue(); 1643} 1644 1645SDValue DAGCombiner::visitUMUL_LOHI(SDNode *N) { 1646 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU); 1647 if (Res.getNode()) return Res; 1648 1649 return SDValue(); 1650} 1651 1652SDValue DAGCombiner::visitSDIVREM(SDNode *N) { 1653 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM); 1654 if (Res.getNode()) return Res; 1655 1656 return SDValue(); 1657} 1658 1659SDValue DAGCombiner::visitUDIVREM(SDNode *N) { 1660 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM); 1661 if (Res.getNode()) return Res; 1662 1663 return SDValue(); 1664} 1665 1666/// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with 1667/// two operands of the same opcode, try to simplify it. 1668SDValue DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) { 1669 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1); 1670 MVT VT = N0.getValueType(); 1671 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!"); 1672 1673 // For each of OP in AND/OR/XOR: 1674 // fold (OP (zext x), (zext y)) -> (zext (OP x, y)) 1675 // fold (OP (sext x), (sext y)) -> (sext (OP x, y)) 1676 // fold (OP (aext x), (aext y)) -> (aext (OP x, y)) 1677 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y)) (if trunc isn't free) 1678 if ((N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND|| 1679 N0.getOpcode() == ISD::SIGN_EXTEND || 1680 (N0.getOpcode() == ISD::TRUNCATE && 1681 !TLI.isTruncateFree(N0.getOperand(0).getValueType(), VT))) && 1682 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) { 1683 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(), 1684 N0.getOperand(0).getValueType(), 1685 N0.getOperand(0), N1.getOperand(0)); 1686 AddToWorkList(ORNode.getNode()); 1687 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, ORNode); 1688 } 1689 1690 // For each of OP in SHL/SRL/SRA/AND... 1691 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z) 1692 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z) 1693 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z) 1694 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL || 1695 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) && 1696 N0.getOperand(1) == N1.getOperand(1)) { 1697 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(), 1698 N0.getOperand(0).getValueType(), 1699 N0.getOperand(0), N1.getOperand(0)); 1700 AddToWorkList(ORNode.getNode()); 1701 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, 1702 ORNode, N0.getOperand(1)); 1703 } 1704 1705 return SDValue(); 1706} 1707 1708SDValue DAGCombiner::visitAND(SDNode *N) { 1709 SDValue N0 = N->getOperand(0); 1710 SDValue N1 = N->getOperand(1); 1711 SDValue LL, LR, RL, RR, CC0, CC1; 1712 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1713 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1714 MVT VT = N1.getValueType(); 1715 unsigned BitWidth = VT.getSizeInBits(); 1716 1717 // fold vector ops 1718 if (VT.isVector()) { 1719 SDValue FoldedVOp = SimplifyVBinOp(N); 1720 if (FoldedVOp.getNode()) return FoldedVOp; 1721 } 1722 1723 // fold (and x, undef) -> 0 1724 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1725 return DAG.getConstant(0, VT); 1726 // fold (and c1, c2) -> c1&c2 1727 if (N0C && N1C) 1728 return DAG.FoldConstantArithmetic(ISD::AND, VT, N0C, N1C); 1729 // canonicalize constant to RHS 1730 if (N0C && !N1C) 1731 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N1, N0); 1732 // fold (and x, -1) -> x 1733 if (N1C && N1C->isAllOnesValue()) 1734 return N0; 1735 // if (and x, c) is known to be zero, return 0 1736 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0), 1737 APInt::getAllOnesValue(BitWidth))) 1738 return DAG.getConstant(0, VT); 1739 // reassociate and 1740 SDValue RAND = ReassociateOps(ISD::AND, N->getDebugLoc(), N0, N1); 1741 if (RAND.getNode() != 0) 1742 return RAND; 1743 // fold (and (or x, 0xFFFF), 0xFF) -> 0xFF 1744 if (N1C && N0.getOpcode() == ISD::OR) 1745 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 1746 if ((ORI->getAPIntValue() & N1C->getAPIntValue()) == N1C->getAPIntValue()) 1747 return N1; 1748 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits. 1749 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 1750 SDValue N0Op0 = N0.getOperand(0); 1751 APInt Mask = ~N1C->getAPIntValue(); 1752 Mask.trunc(N0Op0.getValueSizeInBits()); 1753 if (DAG.MaskedValueIsZero(N0Op0, Mask)) { 1754 SDValue Zext = DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), 1755 N0.getValueType(), N0Op0); 1756 1757 // Replace uses of the AND with uses of the Zero extend node. 1758 CombineTo(N, Zext); 1759 1760 // We actually want to replace all uses of the any_extend with the 1761 // zero_extend, to avoid duplicating things. This will later cause this 1762 // AND to be folded. 1763 CombineTo(N0.getNode(), Zext); 1764 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1765 } 1766 } 1767 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y)) 1768 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 1769 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 1770 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 1771 1772 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 1773 LL.getValueType().isInteger()) { 1774 // fold (and (seteq X, 0), (seteq Y, 0)) -> (seteq (or X, Y), 0) 1775 if (cast<ConstantSDNode>(LR)->isNullValue() && Op1 == ISD::SETEQ) { 1776 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(), 1777 LR.getValueType(), LL, RL); 1778 AddToWorkList(ORNode.getNode()); 1779 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 1780 } 1781 // fold (and (seteq X, -1), (seteq Y, -1)) -> (seteq (and X, Y), -1) 1782 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) { 1783 SDValue ANDNode = DAG.getNode(ISD::AND, N0.getDebugLoc(), 1784 LR.getValueType(), LL, RL); 1785 AddToWorkList(ANDNode.getNode()); 1786 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1); 1787 } 1788 // fold (and (setgt X, -1), (setgt Y, -1)) -> (setgt (or X, Y), -1) 1789 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) { 1790 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(), 1791 LR.getValueType(), LL, RL); 1792 AddToWorkList(ORNode.getNode()); 1793 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 1794 } 1795 } 1796 // canonicalize equivalent to ll == rl 1797 if (LL == RR && LR == RL) { 1798 Op1 = ISD::getSetCCSwappedOperands(Op1); 1799 std::swap(RL, RR); 1800 } 1801 if (LL == RL && LR == RR) { 1802 bool isInteger = LL.getValueType().isInteger(); 1803 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger); 1804 if (Result != ISD::SETCC_INVALID && 1805 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType()))) 1806 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(), 1807 LL, LR, Result); 1808 } 1809 } 1810 1811 // Simplify: (and (op x...), (op y...)) -> (op (and x, y)) 1812 if (N0.getOpcode() == N1.getOpcode()) { 1813 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 1814 if (Tmp.getNode()) return Tmp; 1815 } 1816 1817 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1) 1818 // fold (and (sra)) -> (and (srl)) when possible. 1819 if (!VT.isVector() && 1820 SimplifyDemandedBits(SDValue(N, 0))) 1821 return SDValue(N, 0); 1822 // fold (zext_inreg (extload x)) -> (zextload x) 1823 if (ISD::isEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode())) { 1824 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1825 MVT EVT = LN0->getMemoryVT(); 1826 // If we zero all the possible extended bits, then we can turn this into 1827 // a zextload if we are running before legalize or the operation is legal. 1828 unsigned BitWidth = N1.getValueSizeInBits(); 1829 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 1830 BitWidth - EVT.getSizeInBits())) && 1831 ((!LegalOperations && !LN0->isVolatile()) || 1832 TLI.isLoadExtLegal(ISD::ZEXTLOAD, EVT))) { 1833 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT, 1834 LN0->getChain(), LN0->getBasePtr(), 1835 LN0->getSrcValue(), 1836 LN0->getSrcValueOffset(), EVT, 1837 LN0->isVolatile(), LN0->getAlignment()); 1838 AddToWorkList(N); 1839 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 1840 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1841 } 1842 } 1843 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use 1844 if (ISD::isSEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 1845 N0.hasOneUse()) { 1846 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1847 MVT EVT = LN0->getMemoryVT(); 1848 // If we zero all the possible extended bits, then we can turn this into 1849 // a zextload if we are running before legalize or the operation is legal. 1850 unsigned BitWidth = N1.getValueSizeInBits(); 1851 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 1852 BitWidth - EVT.getSizeInBits())) && 1853 ((!LegalOperations && !LN0->isVolatile()) || 1854 TLI.isLoadExtLegal(ISD::ZEXTLOAD, EVT))) { 1855 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT, 1856 LN0->getChain(), 1857 LN0->getBasePtr(), LN0->getSrcValue(), 1858 LN0->getSrcValueOffset(), EVT, 1859 LN0->isVolatile(), LN0->getAlignment()); 1860 AddToWorkList(N); 1861 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 1862 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1863 } 1864 } 1865 1866 // fold (and (load x), 255) -> (zextload x, i8) 1867 // fold (and (extload x, i16), 255) -> (zextload x, i8) 1868 if (N1C && N0.getOpcode() == ISD::LOAD) { 1869 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1870 if (LN0->getExtensionType() != ISD::SEXTLOAD && 1871 LN0->isUnindexed() && N0.hasOneUse() && 1872 // Do not change the width of a volatile load. 1873 !LN0->isVolatile()) { 1874 MVT EVT = MVT::Other; 1875 uint32_t ActiveBits = N1C->getAPIntValue().getActiveBits(); 1876 if (ActiveBits > 0 && APIntOps::isMask(ActiveBits, N1C->getAPIntValue())) 1877 EVT = MVT::getIntegerVT(ActiveBits); 1878 1879 MVT LoadedVT = LN0->getMemoryVT(); 1880 1881 // Do not generate loads of non-round integer types since these can 1882 // be expensive (and would be wrong if the type is not byte sized). 1883 if (EVT != MVT::Other && LoadedVT.bitsGT(EVT) && EVT.isRound() && 1884 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, EVT))) { 1885 MVT PtrType = N0.getOperand(1).getValueType(); 1886 1887 // For big endian targets, we need to add an offset to the pointer to 1888 // load the correct bytes. For little endian systems, we merely need to 1889 // read fewer bytes from the same pointer. 1890 unsigned LVTStoreBytes = LoadedVT.getStoreSizeInBits()/8; 1891 unsigned EVTStoreBytes = EVT.getStoreSizeInBits()/8; 1892 unsigned PtrOff = LVTStoreBytes - EVTStoreBytes; 1893 unsigned Alignment = LN0->getAlignment(); 1894 SDValue NewPtr = LN0->getBasePtr(); 1895 1896 if (TLI.isBigEndian()) { 1897 NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(), PtrType, 1898 NewPtr, DAG.getConstant(PtrOff, PtrType)); 1899 Alignment = MinAlign(Alignment, PtrOff); 1900 } 1901 1902 AddToWorkList(NewPtr.getNode()); 1903 SDValue Load = 1904 DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), VT, LN0->getChain(), 1905 NewPtr, LN0->getSrcValue(), LN0->getSrcValueOffset(), 1906 EVT, LN0->isVolatile(), Alignment); 1907 AddToWorkList(N); 1908 CombineTo(N0.getNode(), Load, Load.getValue(1)); 1909 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1910 } 1911 } 1912 } 1913 1914 return SDValue(); 1915} 1916 1917SDValue DAGCombiner::visitOR(SDNode *N) { 1918 SDValue N0 = N->getOperand(0); 1919 SDValue N1 = N->getOperand(1); 1920 SDValue LL, LR, RL, RR, CC0, CC1; 1921 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1922 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1923 MVT VT = N1.getValueType(); 1924 1925 // fold vector ops 1926 if (VT.isVector()) { 1927 SDValue FoldedVOp = SimplifyVBinOp(N); 1928 if (FoldedVOp.getNode()) return FoldedVOp; 1929 } 1930 1931 // fold (or x, undef) -> -1 1932 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1933 return DAG.getConstant(~0ULL, VT); 1934 // fold (or c1, c2) -> c1|c2 1935 if (N0C && N1C) 1936 return DAG.FoldConstantArithmetic(ISD::OR, VT, N0C, N1C); 1937 // canonicalize constant to RHS 1938 if (N0C && !N1C) 1939 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N1, N0); 1940 // fold (or x, 0) -> x 1941 if (N1C && N1C->isNullValue()) 1942 return N0; 1943 // fold (or x, -1) -> -1 1944 if (N1C && N1C->isAllOnesValue()) 1945 return N1; 1946 // fold (or x, c) -> c iff (x & ~c) == 0 1947 if (N1C && DAG.MaskedValueIsZero(N0, ~N1C->getAPIntValue())) 1948 return N1; 1949 // reassociate or 1950 SDValue ROR = ReassociateOps(ISD::OR, N->getDebugLoc(), N0, N1); 1951 if (ROR.getNode() != 0) 1952 return ROR; 1953 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2) 1954 if (N1C && N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() && 1955 isa<ConstantSDNode>(N0.getOperand(1))) { 1956 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1)); 1957 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 1958 DAG.getNode(ISD::OR, N0.getDebugLoc(), VT, 1959 N0.getOperand(0), N1), 1960 DAG.FoldConstantArithmetic(ISD::OR, VT, N1C, C1)); 1961 } 1962 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y)) 1963 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 1964 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 1965 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 1966 1967 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 1968 LL.getValueType().isInteger()) { 1969 // fold (or (setne X, 0), (setne Y, 0)) -> (setne (or X, Y), 0) 1970 // fold (or (setlt X, 0), (setlt Y, 0)) -> (setne (or X, Y), 0) 1971 if (cast<ConstantSDNode>(LR)->isNullValue() && 1972 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) { 1973 SDValue ORNode = DAG.getNode(ISD::OR, LR.getDebugLoc(), 1974 LR.getValueType(), LL, RL); 1975 AddToWorkList(ORNode.getNode()); 1976 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 1977 } 1978 // fold (or (setne X, -1), (setne Y, -1)) -> (setne (and X, Y), -1) 1979 // fold (or (setgt X, -1), (setgt Y -1)) -> (setgt (and X, Y), -1) 1980 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && 1981 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) { 1982 SDValue ANDNode = DAG.getNode(ISD::AND, LR.getDebugLoc(), 1983 LR.getValueType(), LL, RL); 1984 AddToWorkList(ANDNode.getNode()); 1985 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1); 1986 } 1987 } 1988 // canonicalize equivalent to ll == rl 1989 if (LL == RR && LR == RL) { 1990 Op1 = ISD::getSetCCSwappedOperands(Op1); 1991 std::swap(RL, RR); 1992 } 1993 if (LL == RL && LR == RR) { 1994 bool isInteger = LL.getValueType().isInteger(); 1995 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger); 1996 if (Result != ISD::SETCC_INVALID && 1997 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType()))) 1998 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(), 1999 LL, LR, Result); 2000 } 2001 } 2002 2003 // Simplify: (or (op x...), (op y...)) -> (op (or x, y)) 2004 if (N0.getOpcode() == N1.getOpcode()) { 2005 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 2006 if (Tmp.getNode()) return Tmp; 2007 } 2008 2009 // (or (and X, C1), (and Y, C2)) -> (and (or X, Y), C3) if possible. 2010 if (N0.getOpcode() == ISD::AND && 2011 N1.getOpcode() == ISD::AND && 2012 N0.getOperand(1).getOpcode() == ISD::Constant && 2013 N1.getOperand(1).getOpcode() == ISD::Constant && 2014 // Don't increase # computations. 2015 (N0.getNode()->hasOneUse() || N1.getNode()->hasOneUse())) { 2016 // We can only do this xform if we know that bits from X that are set in C2 2017 // but not in C1 are already zero. Likewise for Y. 2018 const APInt &LHSMask = 2019 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 2020 const APInt &RHSMask = 2021 cast<ConstantSDNode>(N1.getOperand(1))->getAPIntValue(); 2022 2023 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) && 2024 DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) { 2025 SDValue X = DAG.getNode(ISD::OR, N0.getDebugLoc(), VT, 2026 N0.getOperand(0), N1.getOperand(0)); 2027 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, X, 2028 DAG.getConstant(LHSMask | RHSMask, VT)); 2029 } 2030 } 2031 2032 // See if this is some rotate idiom. 2033 if (SDNode *Rot = MatchRotate(N0, N1, N->getDebugLoc())) 2034 return SDValue(Rot, 0); 2035 2036 return SDValue(); 2037} 2038 2039/// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present. 2040static bool MatchRotateHalf(SDValue Op, SDValue &Shift, SDValue &Mask) { 2041 if (Op.getOpcode() == ISD::AND) { 2042 if (isa<ConstantSDNode>(Op.getOperand(1))) { 2043 Mask = Op.getOperand(1); 2044 Op = Op.getOperand(0); 2045 } else { 2046 return false; 2047 } 2048 } 2049 2050 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) { 2051 Shift = Op; 2052 return true; 2053 } 2054 2055 return false; 2056} 2057 2058// MatchRotate - Handle an 'or' of two operands. If this is one of the many 2059// idioms for rotate, and if the target supports rotation instructions, generate 2060// a rot[lr]. 2061SDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL) { 2062 // Must be a legal type. Expanded 'n promoted things won't work with rotates. 2063 MVT VT = LHS.getValueType(); 2064 if (!TLI.isTypeLegal(VT)) return 0; 2065 2066 // The target must have at least one rotate flavor. 2067 bool HasROTL = TLI.isOperationLegalOrCustom(ISD::ROTL, VT); 2068 bool HasROTR = TLI.isOperationLegalOrCustom(ISD::ROTR, VT); 2069 if (!HasROTL && !HasROTR) return 0; 2070 2071 // Match "(X shl/srl V1) & V2" where V2 may not be present. 2072 SDValue LHSShift; // The shift. 2073 SDValue LHSMask; // AND value if any. 2074 if (!MatchRotateHalf(LHS, LHSShift, LHSMask)) 2075 return 0; // Not part of a rotate. 2076 2077 SDValue RHSShift; // The shift. 2078 SDValue RHSMask; // AND value if any. 2079 if (!MatchRotateHalf(RHS, RHSShift, RHSMask)) 2080 return 0; // Not part of a rotate. 2081 2082 if (LHSShift.getOperand(0) != RHSShift.getOperand(0)) 2083 return 0; // Not shifting the same value. 2084 2085 if (LHSShift.getOpcode() == RHSShift.getOpcode()) 2086 return 0; // Shifts must disagree. 2087 2088 // Canonicalize shl to left side in a shl/srl pair. 2089 if (RHSShift.getOpcode() == ISD::SHL) { 2090 std::swap(LHS, RHS); 2091 std::swap(LHSShift, RHSShift); 2092 std::swap(LHSMask , RHSMask ); 2093 } 2094 2095 unsigned OpSizeInBits = VT.getSizeInBits(); 2096 SDValue LHSShiftArg = LHSShift.getOperand(0); 2097 SDValue LHSShiftAmt = LHSShift.getOperand(1); 2098 SDValue RHSShiftAmt = RHSShift.getOperand(1); 2099 2100 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1) 2101 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2) 2102 if (LHSShiftAmt.getOpcode() == ISD::Constant && 2103 RHSShiftAmt.getOpcode() == ISD::Constant) { 2104 uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getZExtValue(); 2105 uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getZExtValue(); 2106 if ((LShVal + RShVal) != OpSizeInBits) 2107 return 0; 2108 2109 SDValue Rot; 2110 if (HasROTL) 2111 Rot = DAG.getNode(ISD::ROTL, DL, VT, LHSShiftArg, LHSShiftAmt); 2112 else 2113 Rot = DAG.getNode(ISD::ROTR, DL, VT, LHSShiftArg, RHSShiftAmt); 2114 2115 // If there is an AND of either shifted operand, apply it to the result. 2116 if (LHSMask.getNode() || RHSMask.getNode()) { 2117 APInt Mask = APInt::getAllOnesValue(OpSizeInBits); 2118 2119 if (LHSMask.getNode()) { 2120 APInt RHSBits = APInt::getLowBitsSet(OpSizeInBits, LShVal); 2121 Mask &= cast<ConstantSDNode>(LHSMask)->getAPIntValue() | RHSBits; 2122 } 2123 if (RHSMask.getNode()) { 2124 APInt LHSBits = APInt::getHighBitsSet(OpSizeInBits, RShVal); 2125 Mask &= cast<ConstantSDNode>(RHSMask)->getAPIntValue() | LHSBits; 2126 } 2127 2128 Rot = DAG.getNode(ISD::AND, DL, VT, Rot, DAG.getConstant(Mask, VT)); 2129 } 2130 2131 return Rot.getNode(); 2132 } 2133 2134 // If there is a mask here, and we have a variable shift, we can't be sure 2135 // that we're masking out the right stuff. 2136 if (LHSMask.getNode() || RHSMask.getNode()) 2137 return 0; 2138 2139 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y) 2140 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y)) 2141 if (RHSShiftAmt.getOpcode() == ISD::SUB && 2142 LHSShiftAmt == RHSShiftAmt.getOperand(1)) { 2143 if (ConstantSDNode *SUBC = 2144 dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) { 2145 if (SUBC->getAPIntValue() == OpSizeInBits) { 2146 if (HasROTL) 2147 return DAG.getNode(ISD::ROTL, DL, VT, 2148 LHSShiftArg, LHSShiftAmt).getNode(); 2149 else 2150 return DAG.getNode(ISD::ROTR, DL, VT, 2151 LHSShiftArg, RHSShiftAmt).getNode(); 2152 } 2153 } 2154 } 2155 2156 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y) 2157 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y)) 2158 if (LHSShiftAmt.getOpcode() == ISD::SUB && 2159 RHSShiftAmt == LHSShiftAmt.getOperand(1)) { 2160 if (ConstantSDNode *SUBC = 2161 dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) { 2162 if (SUBC->getAPIntValue() == OpSizeInBits) { 2163 if (HasROTR) 2164 return DAG.getNode(ISD::ROTR, DL, VT, 2165 LHSShiftArg, RHSShiftAmt).getNode(); 2166 else 2167 return DAG.getNode(ISD::ROTL, DL, VT, 2168 LHSShiftArg, LHSShiftAmt).getNode(); 2169 } 2170 } 2171 } 2172 2173 // Look for sign/zext/any-extended or truncate cases: 2174 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 2175 || LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 2176 || LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND 2177 || LHSShiftAmt.getOpcode() == ISD::TRUNCATE) && 2178 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 2179 || RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 2180 || RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND 2181 || RHSShiftAmt.getOpcode() == ISD::TRUNCATE)) { 2182 SDValue LExtOp0 = LHSShiftAmt.getOperand(0); 2183 SDValue RExtOp0 = RHSShiftAmt.getOperand(0); 2184 if (RExtOp0.getOpcode() == ISD::SUB && 2185 RExtOp0.getOperand(1) == LExtOp0) { 2186 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 2187 // (rotl x, y) 2188 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 2189 // (rotr x, (sub 32, y)) 2190 if (ConstantSDNode *SUBC = 2191 dyn_cast<ConstantSDNode>(RExtOp0.getOperand(0))) { 2192 if (SUBC->getAPIntValue() == OpSizeInBits) { 2193 return DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT, 2194 LHSShiftArg, 2195 HasROTL ? LHSShiftAmt : RHSShiftAmt).getNode(); 2196 } 2197 } 2198 } else if (LExtOp0.getOpcode() == ISD::SUB && 2199 RExtOp0 == LExtOp0.getOperand(1)) { 2200 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) -> 2201 // (rotr x, y) 2202 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) -> 2203 // (rotl x, (sub 32, y)) 2204 if (ConstantSDNode *SUBC = 2205 dyn_cast<ConstantSDNode>(LExtOp0.getOperand(0))) { 2206 if (SUBC->getAPIntValue() == OpSizeInBits) { 2207 return DAG.getNode(HasROTR ? ISD::ROTR : ISD::ROTL, DL, VT, 2208 LHSShiftArg, 2209 HasROTR ? RHSShiftAmt : LHSShiftAmt).getNode(); 2210 } 2211 } 2212 } 2213 } 2214 2215 return 0; 2216} 2217 2218SDValue DAGCombiner::visitXOR(SDNode *N) { 2219 SDValue N0 = N->getOperand(0); 2220 SDValue N1 = N->getOperand(1); 2221 SDValue LHS, RHS, CC; 2222 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2223 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2224 MVT VT = N0.getValueType(); 2225 2226 // fold vector ops 2227 if (VT.isVector()) { 2228 SDValue FoldedVOp = SimplifyVBinOp(N); 2229 if (FoldedVOp.getNode()) return FoldedVOp; 2230 } 2231 2232 // fold (xor undef, undef) -> 0. This is a common idiom (misuse). 2233 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF) 2234 return DAG.getConstant(0, VT); 2235 // fold (xor x, undef) -> undef 2236 if (N0.getOpcode() == ISD::UNDEF) 2237 return N0; 2238 if (N1.getOpcode() == ISD::UNDEF) 2239 return N1; 2240 // fold (xor c1, c2) -> c1^c2 2241 if (N0C && N1C) 2242 return DAG.FoldConstantArithmetic(ISD::XOR, VT, N0C, N1C); 2243 // canonicalize constant to RHS 2244 if (N0C && !N1C) 2245 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0); 2246 // fold (xor x, 0) -> x 2247 if (N1C && N1C->isNullValue()) 2248 return N0; 2249 // reassociate xor 2250 SDValue RXOR = ReassociateOps(ISD::XOR, N->getDebugLoc(), N0, N1); 2251 if (RXOR.getNode() != 0) 2252 return RXOR; 2253 2254 // fold !(x cc y) -> (x !cc y) 2255 if (N1C && N1C->getAPIntValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) { 2256 bool isInt = LHS.getValueType().isInteger(); 2257 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(), 2258 isInt); 2259 2260 if (!LegalOperations || TLI.isCondCodeLegal(NotCC, LHS.getValueType())) { 2261 switch (N0.getOpcode()) { 2262 default: 2263 llvm_unreachable("Unhandled SetCC Equivalent!"); 2264 case ISD::SETCC: 2265 return DAG.getSetCC(N->getDebugLoc(), VT, LHS, RHS, NotCC); 2266 case ISD::SELECT_CC: 2267 return DAG.getSelectCC(N->getDebugLoc(), LHS, RHS, N0.getOperand(2), 2268 N0.getOperand(3), NotCC); 2269 } 2270 } 2271 } 2272 2273 // fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y))) 2274 if (N1C && N1C->getAPIntValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND && 2275 N0.getNode()->hasOneUse() && 2276 isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){ 2277 SDValue V = N0.getOperand(0); 2278 V = DAG.getNode(ISD::XOR, N0.getDebugLoc(), V.getValueType(), V, 2279 DAG.getConstant(1, V.getValueType())); 2280 AddToWorkList(V.getNode()); 2281 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, V); 2282 } 2283 2284 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are setcc 2285 if (N1C && N1C->getAPIntValue() == 1 && VT == MVT::i1 && 2286 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 2287 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1); 2288 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) { 2289 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 2290 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS 2291 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS 2292 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode()); 2293 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS); 2294 } 2295 } 2296 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are constants 2297 if (N1C && N1C->isAllOnesValue() && 2298 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 2299 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1); 2300 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) { 2301 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 2302 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS 2303 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS 2304 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode()); 2305 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS); 2306 } 2307 } 2308 // fold (xor (xor x, c1), c2) -> (xor x, (xor c1, c2)) 2309 if (N1C && N0.getOpcode() == ISD::XOR) { 2310 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0)); 2311 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2312 if (N00C) 2313 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(1), 2314 DAG.getConstant(N1C->getAPIntValue() ^ 2315 N00C->getAPIntValue(), VT)); 2316 if (N01C) 2317 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(0), 2318 DAG.getConstant(N1C->getAPIntValue() ^ 2319 N01C->getAPIntValue(), VT)); 2320 } 2321 // fold (xor x, x) -> 0 2322 if (N0 == N1) { 2323 if (!VT.isVector()) { 2324 return DAG.getConstant(0, VT); 2325 } else if (!LegalOperations || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)){ 2326 // Produce a vector of zeros. 2327 SDValue El = DAG.getConstant(0, VT.getVectorElementType()); 2328 std::vector<SDValue> Ops(VT.getVectorNumElements(), El); 2329 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT, 2330 &Ops[0], Ops.size()); 2331 } 2332 } 2333 2334 // Simplify: xor (op x...), (op y...) -> (op (xor x, y)) 2335 if (N0.getOpcode() == N1.getOpcode()) { 2336 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 2337 if (Tmp.getNode()) return Tmp; 2338 } 2339 2340 // Simplify the expression using non-local knowledge. 2341 if (!VT.isVector() && 2342 SimplifyDemandedBits(SDValue(N, 0))) 2343 return SDValue(N, 0); 2344 2345 return SDValue(); 2346} 2347 2348/// visitShiftByConstant - Handle transforms common to the three shifts, when 2349/// the shift amount is a constant. 2350SDValue DAGCombiner::visitShiftByConstant(SDNode *N, unsigned Amt) { 2351 SDNode *LHS = N->getOperand(0).getNode(); 2352 if (!LHS->hasOneUse()) return SDValue(); 2353 2354 // We want to pull some binops through shifts, so that we have (and (shift)) 2355 // instead of (shift (and)), likewise for add, or, xor, etc. This sort of 2356 // thing happens with address calculations, so it's important to canonicalize 2357 // it. 2358 bool HighBitSet = false; // Can we transform this if the high bit is set? 2359 2360 switch (LHS->getOpcode()) { 2361 default: return SDValue(); 2362 case ISD::OR: 2363 case ISD::XOR: 2364 HighBitSet = false; // We can only transform sra if the high bit is clear. 2365 break; 2366 case ISD::AND: 2367 HighBitSet = true; // We can only transform sra if the high bit is set. 2368 break; 2369 case ISD::ADD: 2370 if (N->getOpcode() != ISD::SHL) 2371 return SDValue(); // only shl(add) not sr[al](add). 2372 HighBitSet = false; // We can only transform sra if the high bit is clear. 2373 break; 2374 } 2375 2376 // We require the RHS of the binop to be a constant as well. 2377 ConstantSDNode *BinOpCst = dyn_cast<ConstantSDNode>(LHS->getOperand(1)); 2378 if (!BinOpCst) return SDValue(); 2379 2380 // FIXME: disable this unless the input to the binop is a shift by a constant. 2381 // If it is not a shift, it pessimizes some common cases like: 2382 // 2383 // void foo(int *X, int i) { X[i & 1235] = 1; } 2384 // int bar(int *X, int i) { return X[i & 255]; } 2385 SDNode *BinOpLHSVal = LHS->getOperand(0).getNode(); 2386 if ((BinOpLHSVal->getOpcode() != ISD::SHL && 2387 BinOpLHSVal->getOpcode() != ISD::SRA && 2388 BinOpLHSVal->getOpcode() != ISD::SRL) || 2389 !isa<ConstantSDNode>(BinOpLHSVal->getOperand(1))) 2390 return SDValue(); 2391 2392 MVT VT = N->getValueType(0); 2393 2394 // If this is a signed shift right, and the high bit is modified by the 2395 // logical operation, do not perform the transformation. The highBitSet 2396 // boolean indicates the value of the high bit of the constant which would 2397 // cause it to be modified for this operation. 2398 if (N->getOpcode() == ISD::SRA) { 2399 bool BinOpRHSSignSet = BinOpCst->getAPIntValue().isNegative(); 2400 if (BinOpRHSSignSet != HighBitSet) 2401 return SDValue(); 2402 } 2403 2404 // Fold the constants, shifting the binop RHS by the shift amount. 2405 SDValue NewRHS = DAG.getNode(N->getOpcode(), LHS->getOperand(1).getDebugLoc(), 2406 N->getValueType(0), 2407 LHS->getOperand(1), N->getOperand(1)); 2408 2409 // Create the new shift. 2410 SDValue NewShift = DAG.getNode(N->getOpcode(), LHS->getOperand(0).getDebugLoc(), 2411 VT, LHS->getOperand(0), N->getOperand(1)); 2412 2413 // Create the new binop. 2414 return DAG.getNode(LHS->getOpcode(), N->getDebugLoc(), VT, NewShift, NewRHS); 2415} 2416 2417SDValue DAGCombiner::visitSHL(SDNode *N) { 2418 SDValue N0 = N->getOperand(0); 2419 SDValue N1 = N->getOperand(1); 2420 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2421 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2422 MVT VT = N0.getValueType(); 2423 unsigned OpSizeInBits = VT.getSizeInBits(); 2424 2425 // fold (shl c1, c2) -> c1<<c2 2426 if (N0C && N1C) 2427 return DAG.FoldConstantArithmetic(ISD::SHL, VT, N0C, N1C); 2428 // fold (shl 0, x) -> 0 2429 if (N0C && N0C->isNullValue()) 2430 return N0; 2431 // fold (shl x, c >= size(x)) -> undef 2432 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 2433 return DAG.getUNDEF(VT); 2434 // fold (shl x, 0) -> x 2435 if (N1C && N1C->isNullValue()) 2436 return N0; 2437 // if (shl x, c) is known to be zero, return 0 2438 if (DAG.MaskedValueIsZero(SDValue(N, 0), 2439 APInt::getAllOnesValue(VT.getSizeInBits()))) 2440 return DAG.getConstant(0, VT); 2441 // fold (shl x, (trunc (and y, c))) -> (shl x, (and (trunc y), (trunc c))). 2442 if (N1.getOpcode() == ISD::TRUNCATE && 2443 N1.getOperand(0).getOpcode() == ISD::AND && 2444 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 2445 SDValue N101 = N1.getOperand(0).getOperand(1); 2446 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 2447 MVT TruncVT = N1.getValueType(); 2448 SDValue N100 = N1.getOperand(0).getOperand(0); 2449 APInt TruncC = N101C->getAPIntValue(); 2450 TruncC.trunc(TruncVT.getSizeInBits()); 2451 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 2452 DAG.getNode(ISD::AND, N->getDebugLoc(), TruncVT, 2453 DAG.getNode(ISD::TRUNCATE, 2454 N->getDebugLoc(), 2455 TruncVT, N100), 2456 DAG.getConstant(TruncC, TruncVT))); 2457 } 2458 } 2459 2460 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 2461 return SDValue(N, 0); 2462 2463 // fold (shl (shl x, c1), c2) -> 0 or (shl x, (add c1, c2)) 2464 if (N1C && N0.getOpcode() == ISD::SHL && 2465 N0.getOperand(1).getOpcode() == ISD::Constant) { 2466 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 2467 uint64_t c2 = N1C->getZExtValue(); 2468 if (c1 + c2 > OpSizeInBits) 2469 return DAG.getConstant(0, VT); 2470 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0.getOperand(0), 2471 DAG.getConstant(c1 + c2, N1.getValueType())); 2472 } 2473 // fold (shl (srl x, c1), c2) -> (shl (and x, (shl -1, c1)), (sub c2, c1)) or 2474 // (srl (and x, (shl -1, c1)), (sub c1, c2)) 2475 if (N1C && N0.getOpcode() == ISD::SRL && 2476 N0.getOperand(1).getOpcode() == ISD::Constant) { 2477 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 2478 if (c1 < VT.getSizeInBits()) { 2479 uint64_t c2 = N1C->getZExtValue(); 2480 SDValue Mask = DAG.getNode(ISD::AND, N0.getDebugLoc(), VT, 2481 N0.getOperand(0), 2482 DAG.getConstant(~0ULL << c1, VT)); 2483 if (c2 > c1) 2484 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, Mask, 2485 DAG.getConstant(c2-c1, N1.getValueType())); 2486 else 2487 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, Mask, 2488 DAG.getConstant(c1-c2, N1.getValueType())); 2489 } 2490 } 2491 // fold (shl (sra x, c1), c1) -> (and x, (shl -1, c1)) 2492 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) 2493 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0), 2494 DAG.getConstant(~0ULL << N1C->getZExtValue(), VT)); 2495 2496 return N1C ? visitShiftByConstant(N, N1C->getZExtValue()) : SDValue(); 2497} 2498 2499SDValue DAGCombiner::visitSRA(SDNode *N) { 2500 SDValue N0 = N->getOperand(0); 2501 SDValue N1 = N->getOperand(1); 2502 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2503 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2504 MVT VT = N0.getValueType(); 2505 2506 // fold (sra c1, c2) -> (sra c1, c2) 2507 if (N0C && N1C) 2508 return DAG.FoldConstantArithmetic(ISD::SRA, VT, N0C, N1C); 2509 // fold (sra 0, x) -> 0 2510 if (N0C && N0C->isNullValue()) 2511 return N0; 2512 // fold (sra -1, x) -> -1 2513 if (N0C && N0C->isAllOnesValue()) 2514 return N0; 2515 // fold (sra x, (setge c, size(x))) -> undef 2516 if (N1C && N1C->getZExtValue() >= VT.getSizeInBits()) 2517 return DAG.getUNDEF(VT); 2518 // fold (sra x, 0) -> x 2519 if (N1C && N1C->isNullValue()) 2520 return N0; 2521 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports 2522 // sext_inreg. 2523 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) { 2524 unsigned LowBits = VT.getSizeInBits() - (unsigned)N1C->getZExtValue(); 2525 MVT EVT = MVT::getIntegerVT(LowBits); 2526 if ((!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, EVT))) 2527 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, 2528 N0.getOperand(0), DAG.getValueType(EVT)); 2529 } 2530 2531 // fold (sra (sra x, c1), c2) -> (sra x, (add c1, c2)) 2532 if (N1C && N0.getOpcode() == ISD::SRA) { 2533 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 2534 unsigned Sum = N1C->getZExtValue() + C1->getZExtValue(); 2535 if (Sum >= VT.getSizeInBits()) Sum = VT.getSizeInBits()-1; 2536 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0.getOperand(0), 2537 DAG.getConstant(Sum, N1C->getValueType(0))); 2538 } 2539 } 2540 2541 // fold (sra (shl X, m), (sub result_size, n)) 2542 // -> (sign_extend (trunc (shl X, (sub (sub result_size, n), m)))) for 2543 // result_size - n != m. 2544 // If truncate is free for the target sext(shl) is likely to result in better 2545 // code. 2546 if (N0.getOpcode() == ISD::SHL) { 2547 // Get the two constanst of the shifts, CN0 = m, CN = n. 2548 const ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2549 if (N01C && N1C) { 2550 // Determine what the truncate's result bitsize and type would be. 2551 unsigned VTValSize = VT.getSizeInBits(); 2552 MVT TruncVT = 2553 MVT::getIntegerVT(VTValSize - N1C->getZExtValue()); 2554 // Determine the residual right-shift amount. 2555 signed ShiftAmt = N1C->getZExtValue() - N01C->getZExtValue(); 2556 2557 // If the shift is not a no-op (in which case this should be just a sign 2558 // extend already), the truncated to type is legal, sign_extend is legal 2559 // on that type, and the the truncate to that type is both legal and free, 2560 // perform the transform. 2561 if ((ShiftAmt > 0) && 2562 TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND, TruncVT) && 2563 TLI.isOperationLegalOrCustom(ISD::TRUNCATE, VT) && 2564 TLI.isTruncateFree(VT, TruncVT)) { 2565 2566 SDValue Amt = DAG.getConstant(ShiftAmt, getShiftAmountTy()); 2567 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, 2568 N0.getOperand(0), Amt); 2569 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), TruncVT, 2570 Shift); 2571 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), 2572 N->getValueType(0), Trunc); 2573 } 2574 } 2575 } 2576 2577 // fold (sra x, (trunc (and y, c))) -> (sra x, (and (trunc y), (trunc c))). 2578 if (N1.getOpcode() == ISD::TRUNCATE && 2579 N1.getOperand(0).getOpcode() == ISD::AND && 2580 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 2581 SDValue N101 = N1.getOperand(0).getOperand(1); 2582 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 2583 MVT TruncVT = N1.getValueType(); 2584 SDValue N100 = N1.getOperand(0).getOperand(0); 2585 APInt TruncC = N101C->getAPIntValue(); 2586 TruncC.trunc(TruncVT.getSizeInBits()); 2587 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0, 2588 DAG.getNode(ISD::AND, N->getDebugLoc(), 2589 TruncVT, 2590 DAG.getNode(ISD::TRUNCATE, 2591 N->getDebugLoc(), 2592 TruncVT, N100), 2593 DAG.getConstant(TruncC, TruncVT))); 2594 } 2595 } 2596 2597 // Simplify, based on bits shifted out of the LHS. 2598 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 2599 return SDValue(N, 0); 2600 2601 2602 // If the sign bit is known to be zero, switch this to a SRL. 2603 if (DAG.SignBitIsZero(N0)) 2604 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, N1); 2605 2606 return N1C ? visitShiftByConstant(N, N1C->getZExtValue()) : SDValue(); 2607} 2608 2609SDValue DAGCombiner::visitSRL(SDNode *N) { 2610 SDValue N0 = N->getOperand(0); 2611 SDValue N1 = N->getOperand(1); 2612 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2613 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2614 MVT VT = N0.getValueType(); 2615 unsigned OpSizeInBits = VT.getSizeInBits(); 2616 2617 // fold (srl c1, c2) -> c1 >>u c2 2618 if (N0C && N1C) 2619 return DAG.FoldConstantArithmetic(ISD::SRL, VT, N0C, N1C); 2620 // fold (srl 0, x) -> 0 2621 if (N0C && N0C->isNullValue()) 2622 return N0; 2623 // fold (srl x, c >= size(x)) -> undef 2624 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 2625 return DAG.getUNDEF(VT); 2626 // fold (srl x, 0) -> x 2627 if (N1C && N1C->isNullValue()) 2628 return N0; 2629 // if (srl x, c) is known to be zero, return 0 2630 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0), 2631 APInt::getAllOnesValue(OpSizeInBits))) 2632 return DAG.getConstant(0, VT); 2633 2634 // fold (srl (srl x, c1), c2) -> 0 or (srl x, (add c1, c2)) 2635 if (N1C && N0.getOpcode() == ISD::SRL && 2636 N0.getOperand(1).getOpcode() == ISD::Constant) { 2637 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 2638 uint64_t c2 = N1C->getZExtValue(); 2639 if (c1 + c2 > OpSizeInBits) 2640 return DAG.getConstant(0, VT); 2641 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), 2642 DAG.getConstant(c1 + c2, N1.getValueType())); 2643 } 2644 2645 // fold (srl (anyextend x), c) -> (anyextend (srl x, c)) 2646 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 2647 // Shifting in all undef bits? 2648 MVT SmallVT = N0.getOperand(0).getValueType(); 2649 if (N1C->getZExtValue() >= SmallVT.getSizeInBits()) 2650 return DAG.getUNDEF(VT); 2651 2652 SDValue SmallShift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), SmallVT, 2653 N0.getOperand(0), N1); 2654 AddToWorkList(SmallShift.getNode()); 2655 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, SmallShift); 2656 } 2657 2658 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign 2659 // bit, which is unmodified by sra. 2660 if (N1C && N1C->getZExtValue() + 1 == VT.getSizeInBits()) { 2661 if (N0.getOpcode() == ISD::SRA) 2662 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), N1); 2663 } 2664 2665 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit). 2666 if (N1C && N0.getOpcode() == ISD::CTLZ && 2667 N1C->getAPIntValue() == Log2_32(VT.getSizeInBits())) { 2668 APInt KnownZero, KnownOne; 2669 APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits()); 2670 DAG.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne); 2671 2672 // If any of the input bits are KnownOne, then the input couldn't be all 2673 // zeros, thus the result of the srl will always be zero. 2674 if (KnownOne.getBoolValue()) return DAG.getConstant(0, VT); 2675 2676 // If all of the bits input the to ctlz node are known to be zero, then 2677 // the result of the ctlz is "32" and the result of the shift is one. 2678 APInt UnknownBits = ~KnownZero & Mask; 2679 if (UnknownBits == 0) return DAG.getConstant(1, VT); 2680 2681 // Otherwise, check to see if there is exactly one bit input to the ctlz. 2682 if ((UnknownBits & (UnknownBits - 1)) == 0) { 2683 // Okay, we know that only that the single bit specified by UnknownBits 2684 // could be set on input to the CTLZ node. If this bit is set, the SRL 2685 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair 2686 // to an SRL/XOR pair, which is likely to simplify more. 2687 unsigned ShAmt = UnknownBits.countTrailingZeros(); 2688 SDValue Op = N0.getOperand(0); 2689 2690 if (ShAmt) { 2691 Op = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, Op, 2692 DAG.getConstant(ShAmt, getShiftAmountTy())); 2693 AddToWorkList(Op.getNode()); 2694 } 2695 2696 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, 2697 Op, DAG.getConstant(1, VT)); 2698 } 2699 } 2700 2701 // fold (srl x, (trunc (and y, c))) -> (srl x, (and (trunc y), (trunc c))). 2702 if (N1.getOpcode() == ISD::TRUNCATE && 2703 N1.getOperand(0).getOpcode() == ISD::AND && 2704 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 2705 SDValue N101 = N1.getOperand(0).getOperand(1); 2706 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 2707 MVT TruncVT = N1.getValueType(); 2708 SDValue N100 = N1.getOperand(0).getOperand(0); 2709 APInt TruncC = N101C->getAPIntValue(); 2710 TruncC.trunc(TruncVT.getSizeInBits()); 2711 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, 2712 DAG.getNode(ISD::AND, N->getDebugLoc(), 2713 TruncVT, 2714 DAG.getNode(ISD::TRUNCATE, 2715 N->getDebugLoc(), 2716 TruncVT, N100), 2717 DAG.getConstant(TruncC, TruncVT))); 2718 } 2719 } 2720 2721 // fold operands of srl based on knowledge that the low bits are not 2722 // demanded. 2723 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 2724 return SDValue(N, 0); 2725 2726 return N1C ? visitShiftByConstant(N, N1C->getZExtValue()) : SDValue(); 2727} 2728 2729SDValue DAGCombiner::visitCTLZ(SDNode *N) { 2730 SDValue N0 = N->getOperand(0); 2731 MVT VT = N->getValueType(0); 2732 2733 // fold (ctlz c1) -> c2 2734 if (isa<ConstantSDNode>(N0)) 2735 return DAG.getNode(ISD::CTLZ, N->getDebugLoc(), VT, N0); 2736 return SDValue(); 2737} 2738 2739SDValue DAGCombiner::visitCTTZ(SDNode *N) { 2740 SDValue N0 = N->getOperand(0); 2741 MVT VT = N->getValueType(0); 2742 2743 // fold (cttz c1) -> c2 2744 if (isa<ConstantSDNode>(N0)) 2745 return DAG.getNode(ISD::CTTZ, N->getDebugLoc(), VT, N0); 2746 return SDValue(); 2747} 2748 2749SDValue DAGCombiner::visitCTPOP(SDNode *N) { 2750 SDValue N0 = N->getOperand(0); 2751 MVT VT = N->getValueType(0); 2752 2753 // fold (ctpop c1) -> c2 2754 if (isa<ConstantSDNode>(N0)) 2755 return DAG.getNode(ISD::CTPOP, N->getDebugLoc(), VT, N0); 2756 return SDValue(); 2757} 2758 2759SDValue DAGCombiner::visitSELECT(SDNode *N) { 2760 SDValue N0 = N->getOperand(0); 2761 SDValue N1 = N->getOperand(1); 2762 SDValue N2 = N->getOperand(2); 2763 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2764 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2765 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2); 2766 MVT VT = N->getValueType(0); 2767 MVT VT0 = N0.getValueType(); 2768 2769 // fold (select C, X, X) -> X 2770 if (N1 == N2) 2771 return N1; 2772 // fold (select true, X, Y) -> X 2773 if (N0C && !N0C->isNullValue()) 2774 return N1; 2775 // fold (select false, X, Y) -> Y 2776 if (N0C && N0C->isNullValue()) 2777 return N2; 2778 // fold (select C, 1, X) -> (or C, X) 2779 if (VT == MVT::i1 && N1C && N1C->getAPIntValue() == 1) 2780 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2); 2781 // fold (select C, 0, 1) -> (xor C, 1) 2782 if (VT.isInteger() && 2783 (VT0 == MVT::i1 || 2784 (VT0.isInteger() && 2785 TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent)) && 2786 N1C && N2C && N1C->isNullValue() && N2C->getAPIntValue() == 1) { 2787 SDValue XORNode; 2788 if (VT == VT0) 2789 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT0, 2790 N0, DAG.getConstant(1, VT0)); 2791 XORNode = DAG.getNode(ISD::XOR, N0.getDebugLoc(), VT0, 2792 N0, DAG.getConstant(1, VT0)); 2793 AddToWorkList(XORNode.getNode()); 2794 if (VT.bitsGT(VT0)) 2795 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, XORNode); 2796 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, XORNode); 2797 } 2798 // fold (select C, 0, X) -> (and (not C), X) 2799 if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) { 2800 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT); 2801 AddToWorkList(NOTNode.getNode()); 2802 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, NOTNode, N2); 2803 } 2804 // fold (select C, X, 1) -> (or (not C), X) 2805 if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getAPIntValue() == 1) { 2806 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT); 2807 AddToWorkList(NOTNode.getNode()); 2808 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, NOTNode, N1); 2809 } 2810 // fold (select C, X, 0) -> (and C, X) 2811 if (VT == MVT::i1 && N2C && N2C->isNullValue()) 2812 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1); 2813 // fold (select X, X, Y) -> (or X, Y) 2814 // fold (select X, 1, Y) -> (or X, Y) 2815 if (VT == MVT::i1 && (N0 == N1 || (N1C && N1C->getAPIntValue() == 1))) 2816 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2); 2817 // fold (select X, Y, X) -> (and X, Y) 2818 // fold (select X, Y, 0) -> (and X, Y) 2819 if (VT == MVT::i1 && (N0 == N2 || (N2C && N2C->getAPIntValue() == 0))) 2820 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1); 2821 2822 // If we can fold this based on the true/false value, do so. 2823 if (SimplifySelectOps(N, N1, N2)) 2824 return SDValue(N, 0); // Don't revisit N. 2825 2826 // fold selects based on a setcc into other things, such as min/max/abs 2827 if (N0.getOpcode() == ISD::SETCC) { 2828 // FIXME: 2829 // Check against MVT::Other for SELECT_CC, which is a workaround for targets 2830 // having to say they don't support SELECT_CC on every type the DAG knows 2831 // about, since there is no way to mark an opcode illegal at all value types 2832 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other)) 2833 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT, 2834 N0.getOperand(0), N0.getOperand(1), 2835 N1, N2, N0.getOperand(2)); 2836 return SimplifySelect(N->getDebugLoc(), N0, N1, N2); 2837 } 2838 2839 return SDValue(); 2840} 2841 2842SDValue DAGCombiner::visitSELECT_CC(SDNode *N) { 2843 SDValue N0 = N->getOperand(0); 2844 SDValue N1 = N->getOperand(1); 2845 SDValue N2 = N->getOperand(2); 2846 SDValue N3 = N->getOperand(3); 2847 SDValue N4 = N->getOperand(4); 2848 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get(); 2849 2850 // fold select_cc lhs, rhs, x, x, cc -> x 2851 if (N2 == N3) 2852 return N2; 2853 2854 // Determine if the condition we're dealing with is constant 2855 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()), 2856 N0, N1, CC, N->getDebugLoc(), false); 2857 if (SCC.getNode()) AddToWorkList(SCC.getNode()); 2858 2859 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode())) { 2860 if (!SCCC->isNullValue()) 2861 return N2; // cond always true -> true val 2862 else 2863 return N3; // cond always false -> false val 2864 } 2865 2866 // Fold to a simpler select_cc 2867 if (SCC.getNode() && SCC.getOpcode() == ISD::SETCC) 2868 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), N2.getValueType(), 2869 SCC.getOperand(0), SCC.getOperand(1), N2, N3, 2870 SCC.getOperand(2)); 2871 2872 // If we can fold this based on the true/false value, do so. 2873 if (SimplifySelectOps(N, N2, N3)) 2874 return SDValue(N, 0); // Don't revisit N. 2875 2876 // fold select_cc into other things, such as min/max/abs 2877 return SimplifySelectCC(N->getDebugLoc(), N0, N1, N2, N3, CC); 2878} 2879 2880SDValue DAGCombiner::visitSETCC(SDNode *N) { 2881 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1), 2882 cast<CondCodeSDNode>(N->getOperand(2))->get(), 2883 N->getDebugLoc()); 2884} 2885 2886// ExtendUsesToFormExtLoad - Trying to extend uses of a load to enable this: 2887// "fold ({s|z|a}ext (load x)) -> ({s|z|a}ext (truncate ({s|z|a}extload x)))" 2888// transformation. Returns true if extension are possible and the above 2889// mentioned transformation is profitable. 2890static bool ExtendUsesToFormExtLoad(SDNode *N, SDValue N0, 2891 unsigned ExtOpc, 2892 SmallVector<SDNode*, 4> &ExtendNodes, 2893 const TargetLowering &TLI) { 2894 bool HasCopyToRegUses = false; 2895 bool isTruncFree = TLI.isTruncateFree(N->getValueType(0), N0.getValueType()); 2896 for (SDNode::use_iterator UI = N0.getNode()->use_begin(), 2897 UE = N0.getNode()->use_end(); 2898 UI != UE; ++UI) { 2899 SDNode *User = *UI; 2900 if (User == N) 2901 continue; 2902 if (UI.getUse().getResNo() != N0.getResNo()) 2903 continue; 2904 // FIXME: Only extend SETCC N, N and SETCC N, c for now. 2905 if (ExtOpc != ISD::ANY_EXTEND && User->getOpcode() == ISD::SETCC) { 2906 ISD::CondCode CC = cast<CondCodeSDNode>(User->getOperand(2))->get(); 2907 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC)) 2908 // Sign bits will be lost after a zext. 2909 return false; 2910 bool Add = false; 2911 for (unsigned i = 0; i != 2; ++i) { 2912 SDValue UseOp = User->getOperand(i); 2913 if (UseOp == N0) 2914 continue; 2915 if (!isa<ConstantSDNode>(UseOp)) 2916 return false; 2917 Add = true; 2918 } 2919 if (Add) 2920 ExtendNodes.push_back(User); 2921 continue; 2922 } 2923 // If truncates aren't free and there are users we can't 2924 // extend, it isn't worthwhile. 2925 if (!isTruncFree) 2926 return false; 2927 // Remember if this value is live-out. 2928 if (User->getOpcode() == ISD::CopyToReg) 2929 HasCopyToRegUses = true; 2930 } 2931 2932 if (HasCopyToRegUses) { 2933 bool BothLiveOut = false; 2934 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 2935 UI != UE; ++UI) { 2936 SDUse &Use = UI.getUse(); 2937 if (Use.getResNo() == 0 && Use.getUser()->getOpcode() == ISD::CopyToReg) { 2938 BothLiveOut = true; 2939 break; 2940 } 2941 } 2942 if (BothLiveOut) 2943 // Both unextended and extended values are live out. There had better be 2944 // good a reason for the transformation. 2945 return ExtendNodes.size(); 2946 } 2947 return true; 2948} 2949 2950SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) { 2951 SDValue N0 = N->getOperand(0); 2952 MVT VT = N->getValueType(0); 2953 2954 // fold (sext c1) -> c1 2955 if (isa<ConstantSDNode>(N0)) 2956 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N0); 2957 2958 // fold (sext (sext x)) -> (sext x) 2959 // fold (sext (aext x)) -> (sext x) 2960 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 2961 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, 2962 N0.getOperand(0)); 2963 2964 if (N0.getOpcode() == ISD::TRUNCATE) { 2965 // fold (sext (truncate (load x))) -> (sext (smaller load x)) 2966 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n))) 2967 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 2968 if (NarrowLoad.getNode()) { 2969 if (NarrowLoad.getNode() != N0.getNode()) 2970 CombineTo(N0.getNode(), NarrowLoad); 2971 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2972 } 2973 2974 // See if the value being truncated is already sign extended. If so, just 2975 // eliminate the trunc/sext pair. 2976 SDValue Op = N0.getOperand(0); 2977 unsigned OpBits = Op.getValueType().getSizeInBits(); 2978 unsigned MidBits = N0.getValueType().getSizeInBits(); 2979 unsigned DestBits = VT.getSizeInBits(); 2980 unsigned NumSignBits = DAG.ComputeNumSignBits(Op); 2981 2982 if (OpBits == DestBits) { 2983 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign 2984 // bits, it is already ready. 2985 if (NumSignBits > DestBits-MidBits) 2986 return Op; 2987 } else if (OpBits < DestBits) { 2988 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign 2989 // bits, just sext from i32. 2990 if (NumSignBits > OpBits-MidBits) 2991 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, Op); 2992 } else { 2993 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign 2994 // bits, just truncate to i32. 2995 if (NumSignBits > OpBits-MidBits) 2996 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op); 2997 } 2998 2999 // fold (sext (truncate x)) -> (sextinreg x). 3000 if (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, 3001 N0.getValueType())) { 3002 if (Op.getValueType().bitsLT(VT)) 3003 Op = DAG.getNode(ISD::ANY_EXTEND, N0.getDebugLoc(), VT, Op); 3004 else if (Op.getValueType().bitsGT(VT)) 3005 Op = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), VT, Op); 3006 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, Op, 3007 DAG.getValueType(N0.getValueType())); 3008 } 3009 } 3010 3011 // fold (sext (load x)) -> (sext (truncate (sextload x))) 3012 if (ISD::isNON_EXTLoad(N0.getNode()) && 3013 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3014 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()))) { 3015 bool DoXform = true; 3016 SmallVector<SDNode*, 4> SetCCs; 3017 if (!N0.hasOneUse()) 3018 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::SIGN_EXTEND, SetCCs, TLI); 3019 if (DoXform) { 3020 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3021 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 3022 LN0->getChain(), 3023 LN0->getBasePtr(), LN0->getSrcValue(), 3024 LN0->getSrcValueOffset(), 3025 N0.getValueType(), 3026 LN0->isVolatile(), LN0->getAlignment()); 3027 CombineTo(N, ExtLoad); 3028 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3029 N0.getValueType(), ExtLoad); 3030 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 3031 3032 // Extend SetCC uses if necessary. 3033 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 3034 SDNode *SetCC = SetCCs[i]; 3035 SmallVector<SDValue, 4> Ops; 3036 3037 for (unsigned j = 0; j != 2; ++j) { 3038 SDValue SOp = SetCC->getOperand(j); 3039 if (SOp == Trunc) 3040 Ops.push_back(ExtLoad); 3041 else 3042 Ops.push_back(DAG.getNode(ISD::SIGN_EXTEND, 3043 N->getDebugLoc(), VT, SOp)); 3044 } 3045 3046 Ops.push_back(SetCC->getOperand(2)); 3047 CombineTo(SetCC, DAG.getNode(ISD::SETCC, N->getDebugLoc(), 3048 SetCC->getValueType(0), 3049 &Ops[0], Ops.size())); 3050 } 3051 3052 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3053 } 3054 } 3055 3056 // fold (sext (sextload x)) -> (sext (truncate (sextload x))) 3057 // fold (sext ( extload x)) -> (sext (truncate (sextload x))) 3058 if ((ISD::isSEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) && 3059 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) { 3060 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3061 MVT EVT = LN0->getMemoryVT(); 3062 if ((!LegalOperations && !LN0->isVolatile()) || 3063 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT)) { 3064 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 3065 LN0->getChain(), 3066 LN0->getBasePtr(), LN0->getSrcValue(), 3067 LN0->getSrcValueOffset(), EVT, 3068 LN0->isVolatile(), LN0->getAlignment()); 3069 CombineTo(N, ExtLoad); 3070 CombineTo(N0.getNode(), 3071 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3072 N0.getValueType(), ExtLoad), 3073 ExtLoad.getValue(1)); 3074 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3075 } 3076 } 3077 3078 if (N0.getOpcode() == ISD::SETCC) { 3079 // sext(setcc) -> sext_in_reg(vsetcc) for vectors. 3080 if (VT.isVector() && 3081 // We know that the # elements of the results is the same as the 3082 // # elements of the compare (and the # elements of the compare result 3083 // for that matter). Check to see that they are the same size. If so, 3084 // we know that the element size of the sext'd result matches the 3085 // element size of the compare operands. 3086 VT.getSizeInBits() == N0.getOperand(0).getValueType().getSizeInBits() && 3087 3088 // Only do this before legalize for now. 3089 !LegalOperations) { 3090 return DAG.getVSetCC(N->getDebugLoc(), VT, N0.getOperand(0), 3091 N0.getOperand(1), 3092 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 3093 } 3094 3095 // sext(setcc x, y, cc) -> (select_cc x, y, -1, 0, cc) 3096 SDValue SCC = 3097 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 3098 DAG.getConstant(~0ULL, VT), DAG.getConstant(0, VT), 3099 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 3100 if (SCC.getNode()) return SCC; 3101 } 3102 3103 3104 3105 // fold (sext x) -> (zext x) if the sign bit is known zero. 3106 if ((!LegalOperations || TLI.isOperationLegal(ISD::ZERO_EXTEND, VT)) && 3107 DAG.SignBitIsZero(N0)) 3108 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0); 3109 3110 return SDValue(); 3111} 3112 3113SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) { 3114 SDValue N0 = N->getOperand(0); 3115 MVT VT = N->getValueType(0); 3116 3117 // fold (zext c1) -> c1 3118 if (isa<ConstantSDNode>(N0)) 3119 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0); 3120 // fold (zext (zext x)) -> (zext x) 3121 // fold (zext (aext x)) -> (zext x) 3122 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 3123 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, 3124 N0.getOperand(0)); 3125 3126 // fold (zext (truncate (load x))) -> (zext (smaller load x)) 3127 // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n))) 3128 if (N0.getOpcode() == ISD::TRUNCATE) { 3129 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 3130 if (NarrowLoad.getNode()) { 3131 if (NarrowLoad.getNode() != N0.getNode()) 3132 CombineTo(N0.getNode(), NarrowLoad); 3133 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, NarrowLoad); 3134 } 3135 } 3136 3137 // fold (zext (truncate x)) -> (and x, mask) 3138 if (N0.getOpcode() == ISD::TRUNCATE && 3139 (!LegalOperations || TLI.isOperationLegal(ISD::AND, VT))) { 3140 SDValue Op = N0.getOperand(0); 3141 if (Op.getValueType().bitsLT(VT)) { 3142 Op = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, Op); 3143 } else if (Op.getValueType().bitsGT(VT)) { 3144 Op = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op); 3145 } 3146 return DAG.getZeroExtendInReg(Op, N->getDebugLoc(), N0.getValueType()); 3147 } 3148 3149 // Fold (zext (and (trunc x), cst)) -> (and x, cst), 3150 // if either of the casts is not free. 3151 if (N0.getOpcode() == ISD::AND && 3152 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 3153 N0.getOperand(1).getOpcode() == ISD::Constant && 3154 (!TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(), 3155 N0.getValueType()) || 3156 !TLI.isZExtFree(N0.getValueType(), VT))) { 3157 SDValue X = N0.getOperand(0).getOperand(0); 3158 if (X.getValueType().bitsLT(VT)) { 3159 X = DAG.getNode(ISD::ANY_EXTEND, X.getDebugLoc(), VT, X); 3160 } else if (X.getValueType().bitsGT(VT)) { 3161 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X); 3162 } 3163 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 3164 Mask.zext(VT.getSizeInBits()); 3165 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 3166 X, DAG.getConstant(Mask, VT)); 3167 } 3168 3169 // fold (zext (load x)) -> (zext (truncate (zextload x))) 3170 if (ISD::isNON_EXTLoad(N0.getNode()) && 3171 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3172 TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()))) { 3173 bool DoXform = true; 3174 SmallVector<SDNode*, 4> SetCCs; 3175 if (!N0.hasOneUse()) 3176 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ZERO_EXTEND, SetCCs, TLI); 3177 if (DoXform) { 3178 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3179 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT, 3180 LN0->getChain(), 3181 LN0->getBasePtr(), LN0->getSrcValue(), 3182 LN0->getSrcValueOffset(), 3183 N0.getValueType(), 3184 LN0->isVolatile(), LN0->getAlignment()); 3185 CombineTo(N, ExtLoad); 3186 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3187 N0.getValueType(), ExtLoad); 3188 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 3189 3190 // Extend SetCC uses if necessary. 3191 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 3192 SDNode *SetCC = SetCCs[i]; 3193 SmallVector<SDValue, 4> Ops; 3194 3195 for (unsigned j = 0; j != 2; ++j) { 3196 SDValue SOp = SetCC->getOperand(j); 3197 if (SOp == Trunc) 3198 Ops.push_back(ExtLoad); 3199 else 3200 Ops.push_back(DAG.getNode(ISD::ZERO_EXTEND, 3201 N->getDebugLoc(), VT, SOp)); 3202 } 3203 3204 Ops.push_back(SetCC->getOperand(2)); 3205 CombineTo(SetCC, DAG.getNode(ISD::SETCC, N->getDebugLoc(), 3206 SetCC->getValueType(0), 3207 &Ops[0], Ops.size())); 3208 } 3209 3210 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3211 } 3212 } 3213 3214 // fold (zext (zextload x)) -> (zext (truncate (zextload x))) 3215 // fold (zext ( extload x)) -> (zext (truncate (zextload x))) 3216 if ((ISD::isZEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) && 3217 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) { 3218 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3219 MVT EVT = LN0->getMemoryVT(); 3220 if ((!LegalOperations && !LN0->isVolatile()) || 3221 TLI.isLoadExtLegal(ISD::ZEXTLOAD, EVT)) { 3222 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT, 3223 LN0->getChain(), 3224 LN0->getBasePtr(), LN0->getSrcValue(), 3225 LN0->getSrcValueOffset(), EVT, 3226 LN0->isVolatile(), LN0->getAlignment()); 3227 CombineTo(N, ExtLoad); 3228 CombineTo(N0.getNode(), 3229 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), N0.getValueType(), 3230 ExtLoad), 3231 ExtLoad.getValue(1)); 3232 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3233 } 3234 } 3235 3236 // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 3237 if (N0.getOpcode() == ISD::SETCC) { 3238 SDValue SCC = 3239 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 3240 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 3241 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 3242 if (SCC.getNode()) return SCC; 3243 } 3244 3245 return SDValue(); 3246} 3247 3248SDValue DAGCombiner::visitANY_EXTEND(SDNode *N) { 3249 SDValue N0 = N->getOperand(0); 3250 MVT VT = N->getValueType(0); 3251 3252 // fold (aext c1) -> c1 3253 if (isa<ConstantSDNode>(N0)) 3254 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, N0); 3255 // fold (aext (aext x)) -> (aext x) 3256 // fold (aext (zext x)) -> (zext x) 3257 // fold (aext (sext x)) -> (sext x) 3258 if (N0.getOpcode() == ISD::ANY_EXTEND || 3259 N0.getOpcode() == ISD::ZERO_EXTEND || 3260 N0.getOpcode() == ISD::SIGN_EXTEND) 3261 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, N0.getOperand(0)); 3262 3263 // fold (aext (truncate (load x))) -> (aext (smaller load x)) 3264 // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n))) 3265 if (N0.getOpcode() == ISD::TRUNCATE) { 3266 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 3267 if (NarrowLoad.getNode()) { 3268 if (NarrowLoad.getNode() != N0.getNode()) 3269 CombineTo(N0.getNode(), NarrowLoad); 3270 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, NarrowLoad); 3271 } 3272 } 3273 3274 // fold (aext (truncate x)) 3275 if (N0.getOpcode() == ISD::TRUNCATE) { 3276 SDValue TruncOp = N0.getOperand(0); 3277 if (TruncOp.getValueType() == VT) 3278 return TruncOp; // x iff x size == zext size. 3279 if (TruncOp.getValueType().bitsGT(VT)) 3280 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, TruncOp); 3281 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, TruncOp); 3282 } 3283 3284 // Fold (aext (and (trunc x), cst)) -> (and x, cst) 3285 // if the trunc is not free. 3286 if (N0.getOpcode() == ISD::AND && 3287 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 3288 N0.getOperand(1).getOpcode() == ISD::Constant && 3289 !TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(), 3290 N0.getValueType())) { 3291 SDValue X = N0.getOperand(0).getOperand(0); 3292 if (X.getValueType().bitsLT(VT)) { 3293 X = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, X); 3294 } else if (X.getValueType().bitsGT(VT)) { 3295 X = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, X); 3296 } 3297 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 3298 Mask.zext(VT.getSizeInBits()); 3299 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 3300 X, DAG.getConstant(Mask, VT)); 3301 } 3302 3303 // fold (aext (load x)) -> (aext (truncate (extload x))) 3304 if (ISD::isNON_EXTLoad(N0.getNode()) && 3305 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3306 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) { 3307 bool DoXform = true; 3308 SmallVector<SDNode*, 4> SetCCs; 3309 if (!N0.hasOneUse()) 3310 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ANY_EXTEND, SetCCs, TLI); 3311 if (DoXform) { 3312 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3313 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT, 3314 LN0->getChain(), 3315 LN0->getBasePtr(), LN0->getSrcValue(), 3316 LN0->getSrcValueOffset(), 3317 N0.getValueType(), 3318 LN0->isVolatile(), LN0->getAlignment()); 3319 CombineTo(N, ExtLoad); 3320 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3321 N0.getValueType(), ExtLoad); 3322 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 3323 3324 // Extend SetCC uses if necessary. 3325 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 3326 SDNode *SetCC = SetCCs[i]; 3327 SmallVector<SDValue, 4> Ops; 3328 3329 for (unsigned j = 0; j != 2; ++j) { 3330 SDValue SOp = SetCC->getOperand(j); 3331 if (SOp == Trunc) 3332 Ops.push_back(ExtLoad); 3333 else 3334 Ops.push_back(DAG.getNode(ISD::ANY_EXTEND, 3335 N->getDebugLoc(), VT, SOp)); 3336 } 3337 3338 Ops.push_back(SetCC->getOperand(2)); 3339 CombineTo(SetCC, DAG.getNode(ISD::SETCC, N->getDebugLoc(), 3340 SetCC->getValueType(0), 3341 &Ops[0], Ops.size())); 3342 } 3343 3344 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3345 } 3346 } 3347 3348 // fold (aext (zextload x)) -> (aext (truncate (zextload x))) 3349 // fold (aext (sextload x)) -> (aext (truncate (sextload x))) 3350 // fold (aext ( extload x)) -> (aext (truncate (extload x))) 3351 if (N0.getOpcode() == ISD::LOAD && 3352 !ISD::isNON_EXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 3353 N0.hasOneUse()) { 3354 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3355 MVT EVT = LN0->getMemoryVT(); 3356 SDValue ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), N->getDebugLoc(), 3357 VT, LN0->getChain(), LN0->getBasePtr(), 3358 LN0->getSrcValue(), 3359 LN0->getSrcValueOffset(), EVT, 3360 LN0->isVolatile(), LN0->getAlignment()); 3361 CombineTo(N, ExtLoad); 3362 CombineTo(N0.getNode(), 3363 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3364 N0.getValueType(), ExtLoad), 3365 ExtLoad.getValue(1)); 3366 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3367 } 3368 3369 // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 3370 if (N0.getOpcode() == ISD::SETCC) { 3371 SDValue SCC = 3372 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 3373 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 3374 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 3375 if (SCC.getNode()) 3376 return SCC; 3377 } 3378 3379 return SDValue(); 3380} 3381 3382/// GetDemandedBits - See if the specified operand can be simplified with the 3383/// knowledge that only the bits specified by Mask are used. If so, return the 3384/// simpler operand, otherwise return a null SDValue. 3385SDValue DAGCombiner::GetDemandedBits(SDValue V, const APInt &Mask) { 3386 switch (V.getOpcode()) { 3387 default: break; 3388 case ISD::OR: 3389 case ISD::XOR: 3390 // If the LHS or RHS don't contribute bits to the or, drop them. 3391 if (DAG.MaskedValueIsZero(V.getOperand(0), Mask)) 3392 return V.getOperand(1); 3393 if (DAG.MaskedValueIsZero(V.getOperand(1), Mask)) 3394 return V.getOperand(0); 3395 break; 3396 case ISD::SRL: 3397 // Only look at single-use SRLs. 3398 if (!V.getNode()->hasOneUse()) 3399 break; 3400 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(V.getOperand(1))) { 3401 // See if we can recursively simplify the LHS. 3402 unsigned Amt = RHSC->getZExtValue(); 3403 3404 // Watch out for shift count overflow though. 3405 if (Amt >= Mask.getBitWidth()) break; 3406 APInt NewMask = Mask << Amt; 3407 SDValue SimplifyLHS = GetDemandedBits(V.getOperand(0), NewMask); 3408 if (SimplifyLHS.getNode()) 3409 return DAG.getNode(ISD::SRL, V.getDebugLoc(), V.getValueType(), 3410 SimplifyLHS, V.getOperand(1)); 3411 } 3412 } 3413 return SDValue(); 3414} 3415 3416/// ReduceLoadWidth - If the result of a wider load is shifted to right of N 3417/// bits and then truncated to a narrower type and where N is a multiple 3418/// of number of bits of the narrower type, transform it to a narrower load 3419/// from address + N / num of bits of new type. If the result is to be 3420/// extended, also fold the extension to form a extending load. 3421SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) { 3422 unsigned Opc = N->getOpcode(); 3423 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD; 3424 SDValue N0 = N->getOperand(0); 3425 MVT VT = N->getValueType(0); 3426 MVT EVT = VT; 3427 3428 // This transformation isn't valid for vector loads. 3429 if (VT.isVector()) 3430 return SDValue(); 3431 3432 // Special case: SIGN_EXTEND_INREG is basically truncating to EVT then 3433 // extended to VT. 3434 if (Opc == ISD::SIGN_EXTEND_INREG) { 3435 ExtType = ISD::SEXTLOAD; 3436 EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 3437 if (LegalOperations && !TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT)) 3438 return SDValue(); 3439 } 3440 3441 unsigned EVTBits = EVT.getSizeInBits(); 3442 unsigned ShAmt = 0; 3443 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) { 3444 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 3445 ShAmt = N01->getZExtValue(); 3446 // Is the shift amount a multiple of size of VT? 3447 if ((ShAmt & (EVTBits-1)) == 0) { 3448 N0 = N0.getOperand(0); 3449 if (N0.getValueType().getSizeInBits() <= EVTBits) 3450 return SDValue(); 3451 } 3452 } 3453 } 3454 3455 // Do not generate loads of non-round integer types since these can 3456 // be expensive (and would be wrong if the type is not byte sized). 3457 if (isa<LoadSDNode>(N0) && N0.hasOneUse() && EVT.isRound() && 3458 cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits() > EVTBits && 3459 // Do not change the width of a volatile load. 3460 !cast<LoadSDNode>(N0)->isVolatile()) { 3461 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3462 MVT PtrType = N0.getOperand(1).getValueType(); 3463 3464 // For big endian targets, we need to adjust the offset to the pointer to 3465 // load the correct bytes. 3466 if (TLI.isBigEndian()) { 3467 unsigned LVTStoreBits = LN0->getMemoryVT().getStoreSizeInBits(); 3468 unsigned EVTStoreBits = EVT.getStoreSizeInBits(); 3469 ShAmt = LVTStoreBits - EVTStoreBits - ShAmt; 3470 } 3471 3472 uint64_t PtrOff = ShAmt / 8; 3473 unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff); 3474 SDValue NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(), 3475 PtrType, LN0->getBasePtr(), 3476 DAG.getConstant(PtrOff, PtrType)); 3477 AddToWorkList(NewPtr.getNode()); 3478 3479 SDValue Load = (ExtType == ISD::NON_EXTLOAD) 3480 ? DAG.getLoad(VT, N0.getDebugLoc(), LN0->getChain(), NewPtr, 3481 LN0->getSrcValue(), LN0->getSrcValueOffset() + PtrOff, 3482 LN0->isVolatile(), NewAlign) 3483 : DAG.getExtLoad(ExtType, N0.getDebugLoc(), VT, LN0->getChain(), NewPtr, 3484 LN0->getSrcValue(), LN0->getSrcValueOffset() + PtrOff, 3485 EVT, LN0->isVolatile(), NewAlign); 3486 3487 // Replace the old load's chain with the new load's chain. 3488 WorkListRemover DeadNodes(*this); 3489 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1), 3490 &DeadNodes); 3491 3492 // Return the new loaded value. 3493 return Load; 3494 } 3495 3496 return SDValue(); 3497} 3498 3499SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) { 3500 SDValue N0 = N->getOperand(0); 3501 SDValue N1 = N->getOperand(1); 3502 MVT VT = N->getValueType(0); 3503 MVT EVT = cast<VTSDNode>(N1)->getVT(); 3504 unsigned VTBits = VT.getSizeInBits(); 3505 unsigned EVTBits = EVT.getSizeInBits(); 3506 3507 // fold (sext_in_reg c1) -> c1 3508 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF) 3509 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, N0, N1); 3510 3511 // If the input is already sign extended, just drop the extension. 3512 if (DAG.ComputeNumSignBits(N0) >= VT.getSizeInBits()-EVTBits+1) 3513 return N0; 3514 3515 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2 3516 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 3517 EVT.bitsLT(cast<VTSDNode>(N0.getOperand(1))->getVT())) { 3518 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, 3519 N0.getOperand(0), N1); 3520 } 3521 3522 // fold (sext_in_reg (sext x)) -> (sext x) 3523 // fold (sext_in_reg (aext x)) -> (sext x) 3524 // if x is small enough. 3525 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) { 3526 SDValue N00 = N0.getOperand(0); 3527 if (N00.getValueType().getSizeInBits() < EVTBits) 3528 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N00, N1); 3529 } 3530 3531 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero. 3532 if (DAG.MaskedValueIsZero(N0, APInt::getBitsSet(VTBits, EVTBits-1, EVTBits))) 3533 return DAG.getZeroExtendInReg(N0, N->getDebugLoc(), EVT); 3534 3535 // fold operands of sext_in_reg based on knowledge that the top bits are not 3536 // demanded. 3537 if (SimplifyDemandedBits(SDValue(N, 0))) 3538 return SDValue(N, 0); 3539 3540 // fold (sext_in_reg (load x)) -> (smaller sextload x) 3541 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits)) 3542 SDValue NarrowLoad = ReduceLoadWidth(N); 3543 if (NarrowLoad.getNode()) 3544 return NarrowLoad; 3545 3546 // fold (sext_in_reg (srl X, 24), i8) -> (sra X, 24) 3547 // fold (sext_in_reg (srl X, 23), i8) -> (sra X, 23) iff possible. 3548 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above. 3549 if (N0.getOpcode() == ISD::SRL) { 3550 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 3551 if (ShAmt->getZExtValue()+EVTBits <= VT.getSizeInBits()) { 3552 // We can turn this into an SRA iff the input to the SRL is already sign 3553 // extended enough. 3554 unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0)); 3555 if (VT.getSizeInBits()-(ShAmt->getZExtValue()+EVTBits) < InSignBits) 3556 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, 3557 N0.getOperand(0), N0.getOperand(1)); 3558 } 3559 } 3560 3561 // fold (sext_inreg (extload x)) -> (sextload x) 3562 if (ISD::isEXTLoad(N0.getNode()) && 3563 ISD::isUNINDEXEDLoad(N0.getNode()) && 3564 EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 3565 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3566 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) { 3567 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3568 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 3569 LN0->getChain(), 3570 LN0->getBasePtr(), LN0->getSrcValue(), 3571 LN0->getSrcValueOffset(), EVT, 3572 LN0->isVolatile(), LN0->getAlignment()); 3573 CombineTo(N, ExtLoad); 3574 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 3575 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3576 } 3577 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use 3578 if (ISD::isZEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 3579 N0.hasOneUse() && 3580 EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 3581 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3582 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) { 3583 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3584 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 3585 LN0->getChain(), 3586 LN0->getBasePtr(), LN0->getSrcValue(), 3587 LN0->getSrcValueOffset(), EVT, 3588 LN0->isVolatile(), LN0->getAlignment()); 3589 CombineTo(N, ExtLoad); 3590 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 3591 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3592 } 3593 return SDValue(); 3594} 3595 3596SDValue DAGCombiner::visitTRUNCATE(SDNode *N) { 3597 SDValue N0 = N->getOperand(0); 3598 MVT VT = N->getValueType(0); 3599 3600 // noop truncate 3601 if (N0.getValueType() == N->getValueType(0)) 3602 return N0; 3603 // fold (truncate c1) -> c1 3604 if (isa<ConstantSDNode>(N0)) 3605 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0); 3606 // fold (truncate (truncate x)) -> (truncate x) 3607 if (N0.getOpcode() == ISD::TRUNCATE) 3608 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0)); 3609 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x 3610 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::SIGN_EXTEND|| 3611 N0.getOpcode() == ISD::ANY_EXTEND) { 3612 if (N0.getOperand(0).getValueType().bitsLT(VT)) 3613 // if the source is smaller than the dest, we still need an extend 3614 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, 3615 N0.getOperand(0)); 3616 else if (N0.getOperand(0).getValueType().bitsGT(VT)) 3617 // if the source is larger than the dest, than we just need the truncate 3618 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0)); 3619 else 3620 // if the source and dest are the same type, we can drop both the extend 3621 // and the truncate 3622 return N0.getOperand(0); 3623 } 3624 3625 // See if we can simplify the input to this truncate through knowledge that 3626 // only the low bits are being used. For example "trunc (or (shl x, 8), y)" 3627 // -> trunc y 3628 SDValue Shorter = 3629 GetDemandedBits(N0, APInt::getLowBitsSet(N0.getValueSizeInBits(), 3630 VT.getSizeInBits())); 3631 if (Shorter.getNode()) 3632 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Shorter); 3633 3634 // fold (truncate (load x)) -> (smaller load x) 3635 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits)) 3636 return ReduceLoadWidth(N); 3637} 3638 3639static SDNode *getBuildPairElt(SDNode *N, unsigned i) { 3640 SDValue Elt = N->getOperand(i); 3641 if (Elt.getOpcode() != ISD::MERGE_VALUES) 3642 return Elt.getNode(); 3643 return Elt.getOperand(Elt.getResNo()).getNode(); 3644} 3645 3646/// CombineConsecutiveLoads - build_pair (load, load) -> load 3647/// if load locations are consecutive. 3648SDValue DAGCombiner::CombineConsecutiveLoads(SDNode *N, MVT VT) { 3649 assert(N->getOpcode() == ISD::BUILD_PAIR); 3650 3651 LoadSDNode *LD1 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 0)); 3652 LoadSDNode *LD2 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 1)); 3653 if (!LD1 || !LD2 || !ISD::isNON_EXTLoad(LD1) || !LD1->hasOneUse()) 3654 return SDValue(); 3655 MVT LD1VT = LD1->getValueType(0); 3656 const MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 3657 3658 if (ISD::isNON_EXTLoad(LD2) && 3659 LD2->hasOneUse() && 3660 // If both are volatile this would reduce the number of volatile loads. 3661 // If one is volatile it might be ok, but play conservative and bail out. 3662 !LD1->isVolatile() && 3663 !LD2->isVolatile() && 3664 TLI.isConsecutiveLoad(LD2, LD1, LD1VT.getSizeInBits()/8, 1, MFI)) { 3665 unsigned Align = LD1->getAlignment(); 3666 unsigned NewAlign = TLI.getTargetData()-> 3667 getABITypeAlignment(VT.getTypeForMVT(*DAG.getContext())); 3668 3669 if (NewAlign <= Align && 3670 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) 3671 return DAG.getLoad(VT, N->getDebugLoc(), LD1->getChain(), 3672 LD1->getBasePtr(), LD1->getSrcValue(), 3673 LD1->getSrcValueOffset(), false, Align); 3674 } 3675 3676 return SDValue(); 3677} 3678 3679SDValue DAGCombiner::visitBIT_CONVERT(SDNode *N) { 3680 SDValue N0 = N->getOperand(0); 3681 MVT VT = N->getValueType(0); 3682 3683 // If the input is a BUILD_VECTOR with all constant elements, fold this now. 3684 // Only do this before legalize, since afterward the target may be depending 3685 // on the bitconvert. 3686 // First check to see if this is all constant. 3687 if (!LegalTypes && 3688 N0.getOpcode() == ISD::BUILD_VECTOR && N0.getNode()->hasOneUse() && 3689 VT.isVector()) { 3690 bool isSimple = true; 3691 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i) 3692 if (N0.getOperand(i).getOpcode() != ISD::UNDEF && 3693 N0.getOperand(i).getOpcode() != ISD::Constant && 3694 N0.getOperand(i).getOpcode() != ISD::ConstantFP) { 3695 isSimple = false; 3696 break; 3697 } 3698 3699 MVT DestEltVT = N->getValueType(0).getVectorElementType(); 3700 assert(!DestEltVT.isVector() && 3701 "Element type of vector ValueType must not be vector!"); 3702 if (isSimple) 3703 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(N0.getNode(), DestEltVT); 3704 } 3705 3706 // If the input is a constant, let getNode fold it. 3707 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) { 3708 SDValue Res = DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT, N0); 3709 if (Res.getNode() != N) return Res; 3710 } 3711 3712 // (conv (conv x, t1), t2) -> (conv x, t2) 3713 if (N0.getOpcode() == ISD::BIT_CONVERT) 3714 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT, 3715 N0.getOperand(0)); 3716 3717 // fold (conv (load x)) -> (load (conv*)x) 3718 // If the resultant load doesn't need a higher alignment than the original! 3719 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() && 3720 // Do not change the width of a volatile load. 3721 !cast<LoadSDNode>(N0)->isVolatile() && 3722 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) { 3723 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3724 unsigned Align = TLI.getTargetData()-> 3725 getABITypeAlignment(VT.getTypeForMVT(*DAG.getContext())); 3726 unsigned OrigAlign = LN0->getAlignment(); 3727 3728 if (Align <= OrigAlign) { 3729 SDValue Load = DAG.getLoad(VT, N->getDebugLoc(), LN0->getChain(), 3730 LN0->getBasePtr(), 3731 LN0->getSrcValue(), LN0->getSrcValueOffset(), 3732 LN0->isVolatile(), OrigAlign); 3733 AddToWorkList(N); 3734 CombineTo(N0.getNode(), 3735 DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(), 3736 N0.getValueType(), Load), 3737 Load.getValue(1)); 3738 return Load; 3739 } 3740 } 3741 3742 // fold (bitconvert (fneg x)) -> (xor (bitconvert x), signbit) 3743 // fold (bitconvert (fabs x)) -> (and (bitconvert x), (not signbit)) 3744 // This often reduces constant pool loads. 3745 if ((N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FABS) && 3746 N0.getNode()->hasOneUse() && VT.isInteger() && !VT.isVector()) { 3747 SDValue NewConv = DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(), VT, 3748 N0.getOperand(0)); 3749 AddToWorkList(NewConv.getNode()); 3750 3751 APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); 3752 if (N0.getOpcode() == ISD::FNEG) 3753 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, 3754 NewConv, DAG.getConstant(SignBit, VT)); 3755 assert(N0.getOpcode() == ISD::FABS); 3756 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 3757 NewConv, DAG.getConstant(~SignBit, VT)); 3758 } 3759 3760 // fold (bitconvert (fcopysign cst, x)) -> 3761 // (or (and (bitconvert x), sign), (and cst, (not sign))) 3762 // Note that we don't handle (copysign x, cst) because this can always be 3763 // folded to an fneg or fabs. 3764 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse() && 3765 isa<ConstantFPSDNode>(N0.getOperand(0)) && 3766 VT.isInteger() && !VT.isVector()) { 3767 unsigned OrigXWidth = N0.getOperand(1).getValueType().getSizeInBits(); 3768 MVT IntXVT = MVT::getIntegerVT(OrigXWidth); 3769 if (TLI.isTypeLegal(IntXVT) || !LegalTypes) { 3770 SDValue X = DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(), 3771 IntXVT, N0.getOperand(1)); 3772 AddToWorkList(X.getNode()); 3773 3774 // If X has a different width than the result/lhs, sext it or truncate it. 3775 unsigned VTWidth = VT.getSizeInBits(); 3776 if (OrigXWidth < VTWidth) { 3777 X = DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, X); 3778 AddToWorkList(X.getNode()); 3779 } else if (OrigXWidth > VTWidth) { 3780 // To get the sign bit in the right place, we have to shift it right 3781 // before truncating. 3782 X = DAG.getNode(ISD::SRL, X.getDebugLoc(), 3783 X.getValueType(), X, 3784 DAG.getConstant(OrigXWidth-VTWidth, X.getValueType())); 3785 AddToWorkList(X.getNode()); 3786 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X); 3787 AddToWorkList(X.getNode()); 3788 } 3789 3790 APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); 3791 X = DAG.getNode(ISD::AND, X.getDebugLoc(), VT, 3792 X, DAG.getConstant(SignBit, VT)); 3793 AddToWorkList(X.getNode()); 3794 3795 SDValue Cst = DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(), 3796 VT, N0.getOperand(0)); 3797 Cst = DAG.getNode(ISD::AND, Cst.getDebugLoc(), VT, 3798 Cst, DAG.getConstant(~SignBit, VT)); 3799 AddToWorkList(Cst.getNode()); 3800 3801 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, X, Cst); 3802 } 3803 } 3804 3805 // bitconvert(build_pair(ld, ld)) -> ld iff load locations are consecutive. 3806 if (N0.getOpcode() == ISD::BUILD_PAIR) { 3807 SDValue CombineLD = CombineConsecutiveLoads(N0.getNode(), VT); 3808 if (CombineLD.getNode()) 3809 return CombineLD; 3810 } 3811 3812 return SDValue(); 3813} 3814 3815SDValue DAGCombiner::visitBUILD_PAIR(SDNode *N) { 3816 MVT VT = N->getValueType(0); 3817 return CombineConsecutiveLoads(N, VT); 3818} 3819 3820/// ConstantFoldBIT_CONVERTofBUILD_VECTOR - We know that BV is a build_vector 3821/// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the 3822/// destination element value type. 3823SDValue DAGCombiner:: 3824ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *BV, MVT DstEltVT) { 3825 MVT SrcEltVT = BV->getValueType(0).getVectorElementType(); 3826 3827 // If this is already the right type, we're done. 3828 if (SrcEltVT == DstEltVT) return SDValue(BV, 0); 3829 3830 unsigned SrcBitSize = SrcEltVT.getSizeInBits(); 3831 unsigned DstBitSize = DstEltVT.getSizeInBits(); 3832 3833 // If this is a conversion of N elements of one type to N elements of another 3834 // type, convert each element. This handles FP<->INT cases. 3835 if (SrcBitSize == DstBitSize) { 3836 SmallVector<SDValue, 8> Ops; 3837 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 3838 SDValue Op = BV->getOperand(i); 3839 // If the vector element type is not legal, the BUILD_VECTOR operands 3840 // are promoted and implicitly truncated. Make that explicit here. 3841 if (Op.getValueType() != SrcEltVT) 3842 Op = DAG.getNode(ISD::TRUNCATE, BV->getDebugLoc(), SrcEltVT, Op); 3843 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, BV->getDebugLoc(), 3844 DstEltVT, Op)); 3845 AddToWorkList(Ops.back().getNode()); 3846 } 3847 MVT VT = MVT::getVectorVT(DstEltVT, 3848 BV->getValueType(0).getVectorNumElements()); 3849 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 3850 &Ops[0], Ops.size()); 3851 } 3852 3853 // Otherwise, we're growing or shrinking the elements. To avoid having to 3854 // handle annoying details of growing/shrinking FP values, we convert them to 3855 // int first. 3856 if (SrcEltVT.isFloatingPoint()) { 3857 // Convert the input float vector to a int vector where the elements are the 3858 // same sizes. 3859 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!"); 3860 MVT IntVT = MVT::getIntegerVT(SrcEltVT.getSizeInBits()); 3861 BV = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, IntVT).getNode(); 3862 SrcEltVT = IntVT; 3863 } 3864 3865 // Now we know the input is an integer vector. If the output is a FP type, 3866 // convert to integer first, then to FP of the right size. 3867 if (DstEltVT.isFloatingPoint()) { 3868 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!"); 3869 MVT TmpVT = MVT::getIntegerVT(DstEltVT.getSizeInBits()); 3870 SDNode *Tmp = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, TmpVT).getNode(); 3871 3872 // Next, convert to FP elements of the same size. 3873 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(Tmp, DstEltVT); 3874 } 3875 3876 // Okay, we know the src/dst types are both integers of differing types. 3877 // Handling growing first. 3878 assert(SrcEltVT.isInteger() && DstEltVT.isInteger()); 3879 if (SrcBitSize < DstBitSize) { 3880 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize; 3881 3882 SmallVector<SDValue, 8> Ops; 3883 for (unsigned i = 0, e = BV->getNumOperands(); i != e; 3884 i += NumInputsPerOutput) { 3885 bool isLE = TLI.isLittleEndian(); 3886 APInt NewBits = APInt(DstBitSize, 0); 3887 bool EltIsUndef = true; 3888 for (unsigned j = 0; j != NumInputsPerOutput; ++j) { 3889 // Shift the previously computed bits over. 3890 NewBits <<= SrcBitSize; 3891 SDValue Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j)); 3892 if (Op.getOpcode() == ISD::UNDEF) continue; 3893 EltIsUndef = false; 3894 3895 NewBits |= (APInt(cast<ConstantSDNode>(Op)->getAPIntValue()). 3896 zextOrTrunc(SrcBitSize).zext(DstBitSize)); 3897 } 3898 3899 if (EltIsUndef) 3900 Ops.push_back(DAG.getUNDEF(DstEltVT)); 3901 else 3902 Ops.push_back(DAG.getConstant(NewBits, DstEltVT)); 3903 } 3904 3905 MVT VT = MVT::getVectorVT(DstEltVT, Ops.size()); 3906 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 3907 &Ops[0], Ops.size()); 3908 } 3909 3910 // Finally, this must be the case where we are shrinking elements: each input 3911 // turns into multiple outputs. 3912 bool isS2V = ISD::isScalarToVector(BV); 3913 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize; 3914 MVT VT = MVT::getVectorVT(DstEltVT, NumOutputsPerInput*BV->getNumOperands()); 3915 SmallVector<SDValue, 8> Ops; 3916 3917 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 3918 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) { 3919 for (unsigned j = 0; j != NumOutputsPerInput; ++j) 3920 Ops.push_back(DAG.getUNDEF(DstEltVT)); 3921 continue; 3922 } 3923 3924 APInt OpVal = APInt(cast<ConstantSDNode>(BV->getOperand(i))-> 3925 getAPIntValue()).zextOrTrunc(SrcBitSize); 3926 3927 for (unsigned j = 0; j != NumOutputsPerInput; ++j) { 3928 APInt ThisVal = APInt(OpVal).trunc(DstBitSize); 3929 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT)); 3930 if (isS2V && i == 0 && j == 0 && APInt(ThisVal).zext(SrcBitSize) == OpVal) 3931 // Simply turn this into a SCALAR_TO_VECTOR of the new type. 3932 return DAG.getNode(ISD::SCALAR_TO_VECTOR, BV->getDebugLoc(), VT, 3933 Ops[0]); 3934 OpVal = OpVal.lshr(DstBitSize); 3935 } 3936 3937 // For big endian targets, swap the order of the pieces of each element. 3938 if (TLI.isBigEndian()) 3939 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end()); 3940 } 3941 3942 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 3943 &Ops[0], Ops.size()); 3944} 3945 3946SDValue DAGCombiner::visitFADD(SDNode *N) { 3947 SDValue N0 = N->getOperand(0); 3948 SDValue N1 = N->getOperand(1); 3949 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3950 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3951 MVT VT = N->getValueType(0); 3952 3953 // fold vector ops 3954 if (VT.isVector()) { 3955 SDValue FoldedVOp = SimplifyVBinOp(N); 3956 if (FoldedVOp.getNode()) return FoldedVOp; 3957 } 3958 3959 // fold (fadd c1, c2) -> (fadd c1, c2) 3960 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3961 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N1); 3962 // canonicalize constant to RHS 3963 if (N0CFP && !N1CFP) 3964 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N1, N0); 3965 // fold (fadd A, 0) -> A 3966 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero()) 3967 return N0; 3968 // fold (fadd A, (fneg B)) -> (fsub A, B) 3969 if (isNegatibleForFree(N1, LegalOperations) == 2) 3970 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, 3971 GetNegatedExpression(N1, DAG, LegalOperations)); 3972 // fold (fadd (fneg A), B) -> (fsub B, A) 3973 if (isNegatibleForFree(N0, LegalOperations) == 2) 3974 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N1, 3975 GetNegatedExpression(N0, DAG, LegalOperations)); 3976 3977 // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2)) 3978 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FADD && 3979 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 3980 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0.getOperand(0), 3981 DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, 3982 N0.getOperand(1), N1)); 3983 3984 return SDValue(); 3985} 3986 3987SDValue DAGCombiner::visitFSUB(SDNode *N) { 3988 SDValue N0 = N->getOperand(0); 3989 SDValue N1 = N->getOperand(1); 3990 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3991 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3992 MVT VT = N->getValueType(0); 3993 3994 // fold vector ops 3995 if (VT.isVector()) { 3996 SDValue FoldedVOp = SimplifyVBinOp(N); 3997 if (FoldedVOp.getNode()) return FoldedVOp; 3998 } 3999 4000 // fold (fsub c1, c2) -> c1-c2 4001 if (N0CFP && N1CFP && VT != MVT::ppcf128) 4002 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, N1); 4003 // fold (fsub A, 0) -> A 4004 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero()) 4005 return N0; 4006 // fold (fsub 0, B) -> -B 4007 if (UnsafeFPMath && N0CFP && N0CFP->getValueAPF().isZero()) { 4008 if (isNegatibleForFree(N1, LegalOperations)) 4009 return GetNegatedExpression(N1, DAG, LegalOperations); 4010 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 4011 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N1); 4012 } 4013 // fold (fsub A, (fneg B)) -> (fadd A, B) 4014 if (isNegatibleForFree(N1, LegalOperations)) 4015 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, 4016 GetNegatedExpression(N1, DAG, LegalOperations)); 4017 4018 return SDValue(); 4019} 4020 4021SDValue DAGCombiner::visitFMUL(SDNode *N) { 4022 SDValue N0 = N->getOperand(0); 4023 SDValue N1 = N->getOperand(1); 4024 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4025 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4026 MVT VT = N->getValueType(0); 4027 4028 // fold vector ops 4029 if (VT.isVector()) { 4030 SDValue FoldedVOp = SimplifyVBinOp(N); 4031 if (FoldedVOp.getNode()) return FoldedVOp; 4032 } 4033 4034 // fold (fmul c1, c2) -> c1*c2 4035 if (N0CFP && N1CFP && VT != MVT::ppcf128) 4036 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0, N1); 4037 // canonicalize constant to RHS 4038 if (N0CFP && !N1CFP) 4039 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N1, N0); 4040 // fold (fmul A, 0) -> 0 4041 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero()) 4042 return N1; 4043 // fold (fmul A, 0) -> 0, vector edition. 4044 if (UnsafeFPMath && ISD::isBuildVectorAllZeros(N1.getNode())) 4045 return N1; 4046 // fold (fmul X, 2.0) -> (fadd X, X) 4047 if (N1CFP && N1CFP->isExactlyValue(+2.0)) 4048 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N0); 4049 // fold (fmul X, (fneg 1.0)) -> (fneg X) 4050 if (N1CFP && N1CFP->isExactlyValue(-1.0)) 4051 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 4052 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N0); 4053 4054 // fold (fmul (fneg X), (fneg Y)) -> (fmul X, Y) 4055 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations)) { 4056 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations)) { 4057 // Both can be negated for free, check to see if at least one is cheaper 4058 // negated. 4059 if (LHSNeg == 2 || RHSNeg == 2) 4060 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 4061 GetNegatedExpression(N0, DAG, LegalOperations), 4062 GetNegatedExpression(N1, DAG, LegalOperations)); 4063 } 4064 } 4065 4066 // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2)) 4067 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FMUL && 4068 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 4069 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0.getOperand(0), 4070 DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 4071 N0.getOperand(1), N1)); 4072 4073 return SDValue(); 4074} 4075 4076SDValue DAGCombiner::visitFDIV(SDNode *N) { 4077 SDValue N0 = N->getOperand(0); 4078 SDValue N1 = N->getOperand(1); 4079 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4080 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4081 MVT VT = N->getValueType(0); 4082 4083 // fold vector ops 4084 if (VT.isVector()) { 4085 SDValue FoldedVOp = SimplifyVBinOp(N); 4086 if (FoldedVOp.getNode()) return FoldedVOp; 4087 } 4088 4089 // fold (fdiv c1, c2) -> c1/c2 4090 if (N0CFP && N1CFP && VT != MVT::ppcf128) 4091 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, N0, N1); 4092 4093 4094 // (fdiv (fneg X), (fneg Y)) -> (fdiv X, Y) 4095 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations)) { 4096 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations)) { 4097 // Both can be negated for free, check to see if at least one is cheaper 4098 // negated. 4099 if (LHSNeg == 2 || RHSNeg == 2) 4100 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, 4101 GetNegatedExpression(N0, DAG, LegalOperations), 4102 GetNegatedExpression(N1, DAG, LegalOperations)); 4103 } 4104 } 4105 4106 return SDValue(); 4107} 4108 4109SDValue DAGCombiner::visitFREM(SDNode *N) { 4110 SDValue N0 = N->getOperand(0); 4111 SDValue N1 = N->getOperand(1); 4112 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4113 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4114 MVT VT = N->getValueType(0); 4115 4116 // fold (frem c1, c2) -> fmod(c1,c2) 4117 if (N0CFP && N1CFP && VT != MVT::ppcf128) 4118 return DAG.getNode(ISD::FREM, N->getDebugLoc(), VT, N0, N1); 4119 4120 return SDValue(); 4121} 4122 4123SDValue DAGCombiner::visitFCOPYSIGN(SDNode *N) { 4124 SDValue N0 = N->getOperand(0); 4125 SDValue N1 = N->getOperand(1); 4126 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4127 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4128 MVT VT = N->getValueType(0); 4129 4130 if (N0CFP && N1CFP && VT != MVT::ppcf128) // Constant fold 4131 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, N0, N1); 4132 4133 if (N1CFP) { 4134 const APFloat& V = N1CFP->getValueAPF(); 4135 // copysign(x, c1) -> fabs(x) iff ispos(c1) 4136 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1) 4137 if (!V.isNegative()) { 4138 if (!LegalOperations || TLI.isOperationLegal(ISD::FABS, VT)) 4139 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 4140 } else { 4141 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 4142 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, 4143 DAG.getNode(ISD::FABS, N0.getDebugLoc(), VT, N0)); 4144 } 4145 } 4146 4147 // copysign(fabs(x), y) -> copysign(x, y) 4148 // copysign(fneg(x), y) -> copysign(x, y) 4149 // copysign(copysign(x,z), y) -> copysign(x, y) 4150 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG || 4151 N0.getOpcode() == ISD::FCOPYSIGN) 4152 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 4153 N0.getOperand(0), N1); 4154 4155 // copysign(x, abs(y)) -> abs(x) 4156 if (N1.getOpcode() == ISD::FABS) 4157 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 4158 4159 // copysign(x, copysign(y,z)) -> copysign(x, z) 4160 if (N1.getOpcode() == ISD::FCOPYSIGN) 4161 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 4162 N0, N1.getOperand(1)); 4163 4164 // copysign(x, fp_extend(y)) -> copysign(x, y) 4165 // copysign(x, fp_round(y)) -> copysign(x, y) 4166 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND) 4167 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 4168 N0, N1.getOperand(0)); 4169 4170 return SDValue(); 4171} 4172 4173SDValue DAGCombiner::visitSINT_TO_FP(SDNode *N) { 4174 SDValue N0 = N->getOperand(0); 4175 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 4176 MVT VT = N->getValueType(0); 4177 MVT OpVT = N0.getValueType(); 4178 4179 // fold (sint_to_fp c1) -> c1fp 4180 if (N0C && OpVT != MVT::ppcf128) 4181 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0); 4182 4183 // If the input is a legal type, and SINT_TO_FP is not legal on this target, 4184 // but UINT_TO_FP is legal on this target, try to convert. 4185 if (!TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT) && 4186 TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT)) { 4187 // If the sign bit is known to be zero, we can change this to UINT_TO_FP. 4188 if (DAG.SignBitIsZero(N0)) 4189 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0); 4190 } 4191 4192 return SDValue(); 4193} 4194 4195SDValue DAGCombiner::visitUINT_TO_FP(SDNode *N) { 4196 SDValue N0 = N->getOperand(0); 4197 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 4198 MVT VT = N->getValueType(0); 4199 MVT OpVT = N0.getValueType(); 4200 4201 // fold (uint_to_fp c1) -> c1fp 4202 if (N0C && OpVT != MVT::ppcf128) 4203 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0); 4204 4205 // If the input is a legal type, and UINT_TO_FP is not legal on this target, 4206 // but SINT_TO_FP is legal on this target, try to convert. 4207 if (!TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT) && 4208 TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT)) { 4209 // If the sign bit is known to be zero, we can change this to SINT_TO_FP. 4210 if (DAG.SignBitIsZero(N0)) 4211 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0); 4212 } 4213 4214 return SDValue(); 4215} 4216 4217SDValue DAGCombiner::visitFP_TO_SINT(SDNode *N) { 4218 SDValue N0 = N->getOperand(0); 4219 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4220 MVT VT = N->getValueType(0); 4221 4222 // fold (fp_to_sint c1fp) -> c1 4223 if (N0CFP) 4224 return DAG.getNode(ISD::FP_TO_SINT, N->getDebugLoc(), VT, N0); 4225 4226 return SDValue(); 4227} 4228 4229SDValue DAGCombiner::visitFP_TO_UINT(SDNode *N) { 4230 SDValue N0 = N->getOperand(0); 4231 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4232 MVT VT = N->getValueType(0); 4233 4234 // fold (fp_to_uint c1fp) -> c1 4235 if (N0CFP && VT != MVT::ppcf128) 4236 return DAG.getNode(ISD::FP_TO_UINT, N->getDebugLoc(), VT, N0); 4237 4238 return SDValue(); 4239} 4240 4241SDValue DAGCombiner::visitFP_ROUND(SDNode *N) { 4242 SDValue N0 = N->getOperand(0); 4243 SDValue N1 = N->getOperand(1); 4244 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4245 MVT VT = N->getValueType(0); 4246 4247 // fold (fp_round c1fp) -> c1fp 4248 if (N0CFP && N0.getValueType() != MVT::ppcf128) 4249 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0, N1); 4250 4251 // fold (fp_round (fp_extend x)) -> x 4252 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType()) 4253 return N0.getOperand(0); 4254 4255 // fold (fp_round (fp_round x)) -> (fp_round x) 4256 if (N0.getOpcode() == ISD::FP_ROUND) { 4257 // This is a value preserving truncation if both round's are. 4258 bool IsTrunc = N->getConstantOperandVal(1) == 1 && 4259 N0.getNode()->getConstantOperandVal(1) == 1; 4260 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0.getOperand(0), 4261 DAG.getIntPtrConstant(IsTrunc)); 4262 } 4263 4264 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y) 4265 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse()) { 4266 SDValue Tmp = DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(), VT, 4267 N0.getOperand(0), N1); 4268 AddToWorkList(Tmp.getNode()); 4269 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 4270 Tmp, N0.getOperand(1)); 4271 } 4272 4273 return SDValue(); 4274} 4275 4276SDValue DAGCombiner::visitFP_ROUND_INREG(SDNode *N) { 4277 SDValue N0 = N->getOperand(0); 4278 MVT VT = N->getValueType(0); 4279 MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 4280 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4281 4282 // fold (fp_round_inreg c1fp) -> c1fp 4283 if (N0CFP && (TLI.isTypeLegal(EVT) || !LegalTypes)) { 4284 SDValue Round = DAG.getConstantFP(*N0CFP->getConstantFPValue(), EVT); 4285 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, Round); 4286 } 4287 4288 return SDValue(); 4289} 4290 4291SDValue DAGCombiner::visitFP_EXTEND(SDNode *N) { 4292 SDValue N0 = N->getOperand(0); 4293 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4294 MVT VT = N->getValueType(0); 4295 4296 // If this is fp_round(fpextend), don't fold it, allow ourselves to be folded. 4297 if (N->hasOneUse() && 4298 N->use_begin()->getOpcode() == ISD::FP_ROUND) 4299 return SDValue(); 4300 4301 // fold (fp_extend c1fp) -> c1fp 4302 if (N0CFP && VT != MVT::ppcf128) 4303 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, N0); 4304 4305 // Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't affect the 4306 // value of X. 4307 if (N0.getOpcode() == ISD::FP_ROUND 4308 && N0.getNode()->getConstantOperandVal(1) == 1) { 4309 SDValue In = N0.getOperand(0); 4310 if (In.getValueType() == VT) return In; 4311 if (VT.bitsLT(In.getValueType())) 4312 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, 4313 In, N0.getOperand(1)); 4314 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, In); 4315 } 4316 4317 // fold (fpext (load x)) -> (fpext (fptrunc (extload x))) 4318 if (ISD::isNON_EXTLoad(N0.getNode()) && N0.hasOneUse() && 4319 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 4320 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) { 4321 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4322 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT, 4323 LN0->getChain(), 4324 LN0->getBasePtr(), LN0->getSrcValue(), 4325 LN0->getSrcValueOffset(), 4326 N0.getValueType(), 4327 LN0->isVolatile(), LN0->getAlignment()); 4328 CombineTo(N, ExtLoad); 4329 CombineTo(N0.getNode(), 4330 DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(), 4331 N0.getValueType(), ExtLoad, DAG.getIntPtrConstant(1)), 4332 ExtLoad.getValue(1)); 4333 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4334 } 4335 4336 return SDValue(); 4337} 4338 4339SDValue DAGCombiner::visitFNEG(SDNode *N) { 4340 SDValue N0 = N->getOperand(0); 4341 4342 if (isNegatibleForFree(N0, LegalOperations)) 4343 return GetNegatedExpression(N0, DAG, LegalOperations); 4344 4345 // Transform fneg(bitconvert(x)) -> bitconvert(x^sign) to avoid loading 4346 // constant pool values. 4347 if (N0.getOpcode() == ISD::BIT_CONVERT && N0.getNode()->hasOneUse() && 4348 N0.getOperand(0).getValueType().isInteger() && 4349 !N0.getOperand(0).getValueType().isVector()) { 4350 SDValue Int = N0.getOperand(0); 4351 MVT IntVT = Int.getValueType(); 4352 if (IntVT.isInteger() && !IntVT.isVector()) { 4353 Int = DAG.getNode(ISD::XOR, N0.getDebugLoc(), IntVT, Int, 4354 DAG.getConstant(APInt::getSignBit(IntVT.getSizeInBits()), IntVT)); 4355 AddToWorkList(Int.getNode()); 4356 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), 4357 N->getValueType(0), Int); 4358 } 4359 } 4360 4361 return SDValue(); 4362} 4363 4364SDValue DAGCombiner::visitFABS(SDNode *N) { 4365 SDValue N0 = N->getOperand(0); 4366 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4367 MVT VT = N->getValueType(0); 4368 4369 // fold (fabs c1) -> fabs(c1) 4370 if (N0CFP && VT != MVT::ppcf128) 4371 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 4372 // fold (fabs (fabs x)) -> (fabs x) 4373 if (N0.getOpcode() == ISD::FABS) 4374 return N->getOperand(0); 4375 // fold (fabs (fneg x)) -> (fabs x) 4376 // fold (fabs (fcopysign x, y)) -> (fabs x) 4377 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN) 4378 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0.getOperand(0)); 4379 4380 // Transform fabs(bitconvert(x)) -> bitconvert(x&~sign) to avoid loading 4381 // constant pool values. 4382 if (N0.getOpcode() == ISD::BIT_CONVERT && N0.getNode()->hasOneUse() && 4383 N0.getOperand(0).getValueType().isInteger() && 4384 !N0.getOperand(0).getValueType().isVector()) { 4385 SDValue Int = N0.getOperand(0); 4386 MVT IntVT = Int.getValueType(); 4387 if (IntVT.isInteger() && !IntVT.isVector()) { 4388 Int = DAG.getNode(ISD::AND, N0.getDebugLoc(), IntVT, Int, 4389 DAG.getConstant(~APInt::getSignBit(IntVT.getSizeInBits()), IntVT)); 4390 AddToWorkList(Int.getNode()); 4391 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), 4392 N->getValueType(0), Int); 4393 } 4394 } 4395 4396 return SDValue(); 4397} 4398 4399SDValue DAGCombiner::visitBRCOND(SDNode *N) { 4400 SDValue Chain = N->getOperand(0); 4401 SDValue N1 = N->getOperand(1); 4402 SDValue N2 = N->getOperand(2); 4403 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 4404 4405 // never taken branch, fold to chain 4406 if (N1C && N1C->isNullValue()) 4407 return Chain; 4408 // unconditional branch 4409 if (N1C && N1C->getAPIntValue() == 1) 4410 return DAG.getNode(ISD::BR, N->getDebugLoc(), MVT::Other, Chain, N2); 4411 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal 4412 // on the target. 4413 if (N1.getOpcode() == ISD::SETCC && 4414 TLI.isOperationLegalOrCustom(ISD::BR_CC, MVT::Other)) { 4415 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other, 4416 Chain, N1.getOperand(2), 4417 N1.getOperand(0), N1.getOperand(1), N2); 4418 } 4419 4420 if (N1.hasOneUse() && N1.getOpcode() == ISD::SRL) { 4421 // Match this pattern so that we can generate simpler code: 4422 // 4423 // %a = ... 4424 // %b = and i32 %a, 2 4425 // %c = srl i32 %b, 1 4426 // brcond i32 %c ... 4427 // 4428 // into 4429 // 4430 // %a = ... 4431 // %b = and %a, 2 4432 // %c = setcc eq %b, 0 4433 // brcond %c ... 4434 // 4435 // This applies only when the AND constant value has one bit set and the 4436 // SRL constant is equal to the log2 of the AND constant. The back-end is 4437 // smart enough to convert the result into a TEST/JMP sequence. 4438 SDValue Op0 = N1.getOperand(0); 4439 SDValue Op1 = N1.getOperand(1); 4440 4441 if (Op0.getOpcode() == ISD::AND && 4442 Op0.hasOneUse() && 4443 Op1.getOpcode() == ISD::Constant) { 4444 SDValue AndOp0 = Op0.getOperand(0); 4445 SDValue AndOp1 = Op0.getOperand(1); 4446 4447 if (AndOp1.getOpcode() == ISD::Constant) { 4448 const APInt &AndConst = cast<ConstantSDNode>(AndOp1)->getAPIntValue(); 4449 4450 if (AndConst.isPowerOf2() && 4451 cast<ConstantSDNode>(Op1)->getAPIntValue()==AndConst.logBase2()) { 4452 SDValue SetCC = 4453 DAG.getSetCC(N->getDebugLoc(), 4454 TLI.getSetCCResultType(Op0.getValueType()), 4455 Op0, DAG.getConstant(0, Op0.getValueType()), 4456 ISD::SETNE); 4457 4458 // Replace the uses of SRL with SETCC 4459 DAG.ReplaceAllUsesOfValueWith(N1, SetCC); 4460 removeFromWorkList(N1.getNode()); 4461 DAG.DeleteNode(N1.getNode()); 4462 return DAG.getNode(ISD::BRCOND, N->getDebugLoc(), 4463 MVT::Other, Chain, SetCC, N2); 4464 } 4465 } 4466 } 4467 } 4468 4469 return SDValue(); 4470} 4471 4472// Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB. 4473// 4474SDValue DAGCombiner::visitBR_CC(SDNode *N) { 4475 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1)); 4476 SDValue CondLHS = N->getOperand(2), CondRHS = N->getOperand(3); 4477 4478 // Use SimplifySetCC to simplify SETCC's. 4479 SDValue Simp = SimplifySetCC(TLI.getSetCCResultType(CondLHS.getValueType()), 4480 CondLHS, CondRHS, CC->get(), N->getDebugLoc(), 4481 false); 4482 if (Simp.getNode()) AddToWorkList(Simp.getNode()); 4483 4484 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(Simp.getNode()); 4485 4486 // fold br_cc true, dest -> br dest (unconditional branch) 4487 if (SCCC && !SCCC->isNullValue()) 4488 return DAG.getNode(ISD::BR, N->getDebugLoc(), MVT::Other, 4489 N->getOperand(0), N->getOperand(4)); 4490 // fold br_cc false, dest -> unconditional fall through 4491 if (SCCC && SCCC->isNullValue()) 4492 return N->getOperand(0); 4493 4494 // fold to a simpler setcc 4495 if (Simp.getNode() && Simp.getOpcode() == ISD::SETCC) 4496 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other, 4497 N->getOperand(0), Simp.getOperand(2), 4498 Simp.getOperand(0), Simp.getOperand(1), 4499 N->getOperand(4)); 4500 4501 return SDValue(); 4502} 4503 4504/// CombineToPreIndexedLoadStore - Try turning a load / store into a 4505/// pre-indexed load / store when the base pointer is an add or subtract 4506/// and it has other uses besides the load / store. After the 4507/// transformation, the new indexed load / store has effectively folded 4508/// the add / subtract in and all of its other uses are redirected to the 4509/// new load / store. 4510bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) { 4511 if (!LegalOperations) 4512 return false; 4513 4514 bool isLoad = true; 4515 SDValue Ptr; 4516 MVT VT; 4517 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 4518 if (LD->isIndexed()) 4519 return false; 4520 VT = LD->getMemoryVT(); 4521 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) && 4522 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT)) 4523 return false; 4524 Ptr = LD->getBasePtr(); 4525 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 4526 if (ST->isIndexed()) 4527 return false; 4528 VT = ST->getMemoryVT(); 4529 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) && 4530 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT)) 4531 return false; 4532 Ptr = ST->getBasePtr(); 4533 isLoad = false; 4534 } else { 4535 return false; 4536 } 4537 4538 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail 4539 // out. There is no reason to make this a preinc/predec. 4540 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) || 4541 Ptr.getNode()->hasOneUse()) 4542 return false; 4543 4544 // Ask the target to do addressing mode selection. 4545 SDValue BasePtr; 4546 SDValue Offset; 4547 ISD::MemIndexedMode AM = ISD::UNINDEXED; 4548 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG)) 4549 return false; 4550 // Don't create a indexed load / store with zero offset. 4551 if (isa<ConstantSDNode>(Offset) && 4552 cast<ConstantSDNode>(Offset)->isNullValue()) 4553 return false; 4554 4555 // Try turning it into a pre-indexed load / store except when: 4556 // 1) The new base ptr is a frame index. 4557 // 2) If N is a store and the new base ptr is either the same as or is a 4558 // predecessor of the value being stored. 4559 // 3) Another use of old base ptr is a predecessor of N. If ptr is folded 4560 // that would create a cycle. 4561 // 4) All uses are load / store ops that use it as old base ptr. 4562 4563 // Check #1. Preinc'ing a frame index would require copying the stack pointer 4564 // (plus the implicit offset) to a register to preinc anyway. 4565 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr)) 4566 return false; 4567 4568 // Check #2. 4569 if (!isLoad) { 4570 SDValue Val = cast<StoreSDNode>(N)->getValue(); 4571 if (Val == BasePtr || BasePtr.getNode()->isPredecessorOf(Val.getNode())) 4572 return false; 4573 } 4574 4575 // Now check for #3 and #4. 4576 bool RealUse = false; 4577 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(), 4578 E = Ptr.getNode()->use_end(); I != E; ++I) { 4579 SDNode *Use = *I; 4580 if (Use == N) 4581 continue; 4582 if (Use->isPredecessorOf(N)) 4583 return false; 4584 4585 if (!((Use->getOpcode() == ISD::LOAD && 4586 cast<LoadSDNode>(Use)->getBasePtr() == Ptr) || 4587 (Use->getOpcode() == ISD::STORE && 4588 cast<StoreSDNode>(Use)->getBasePtr() == Ptr))) 4589 RealUse = true; 4590 } 4591 4592 if (!RealUse) 4593 return false; 4594 4595 SDValue Result; 4596 if (isLoad) 4597 Result = DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(), 4598 BasePtr, Offset, AM); 4599 else 4600 Result = DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(), 4601 BasePtr, Offset, AM); 4602 ++PreIndexedNodes; 4603 ++NodesCombined; 4604 DOUT << "\nReplacing.4 "; DEBUG(N->dump(&DAG)); 4605 DOUT << "\nWith: "; DEBUG(Result.getNode()->dump(&DAG)); 4606 DOUT << '\n'; 4607 WorkListRemover DeadNodes(*this); 4608 if (isLoad) { 4609 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0), 4610 &DeadNodes); 4611 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2), 4612 &DeadNodes); 4613 } else { 4614 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1), 4615 &DeadNodes); 4616 } 4617 4618 // Finally, since the node is now dead, remove it from the graph. 4619 DAG.DeleteNode(N); 4620 4621 // Replace the uses of Ptr with uses of the updated base value. 4622 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0), 4623 &DeadNodes); 4624 removeFromWorkList(Ptr.getNode()); 4625 DAG.DeleteNode(Ptr.getNode()); 4626 4627 return true; 4628} 4629 4630/// CombineToPostIndexedLoadStore - Try to combine a load / store with a 4631/// add / sub of the base pointer node into a post-indexed load / store. 4632/// The transformation folded the add / subtract into the new indexed 4633/// load / store effectively and all of its uses are redirected to the 4634/// new load / store. 4635bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) { 4636 if (!LegalOperations) 4637 return false; 4638 4639 bool isLoad = true; 4640 SDValue Ptr; 4641 MVT VT; 4642 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 4643 if (LD->isIndexed()) 4644 return false; 4645 VT = LD->getMemoryVT(); 4646 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) && 4647 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT)) 4648 return false; 4649 Ptr = LD->getBasePtr(); 4650 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 4651 if (ST->isIndexed()) 4652 return false; 4653 VT = ST->getMemoryVT(); 4654 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) && 4655 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT)) 4656 return false; 4657 Ptr = ST->getBasePtr(); 4658 isLoad = false; 4659 } else { 4660 return false; 4661 } 4662 4663 if (Ptr.getNode()->hasOneUse()) 4664 return false; 4665 4666 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(), 4667 E = Ptr.getNode()->use_end(); I != E; ++I) { 4668 SDNode *Op = *I; 4669 if (Op == N || 4670 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB)) 4671 continue; 4672 4673 SDValue BasePtr; 4674 SDValue Offset; 4675 ISD::MemIndexedMode AM = ISD::UNINDEXED; 4676 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) { 4677 if (Ptr == Offset) 4678 std::swap(BasePtr, Offset); 4679 if (Ptr != BasePtr) 4680 continue; 4681 // Don't create a indexed load / store with zero offset. 4682 if (isa<ConstantSDNode>(Offset) && 4683 cast<ConstantSDNode>(Offset)->isNullValue()) 4684 continue; 4685 4686 // Try turning it into a post-indexed load / store except when 4687 // 1) All uses are load / store ops that use it as base ptr. 4688 // 2) Op must be independent of N, i.e. Op is neither a predecessor 4689 // nor a successor of N. Otherwise, if Op is folded that would 4690 // create a cycle. 4691 4692 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr)) 4693 continue; 4694 4695 // Check for #1. 4696 bool TryNext = false; 4697 for (SDNode::use_iterator II = BasePtr.getNode()->use_begin(), 4698 EE = BasePtr.getNode()->use_end(); II != EE; ++II) { 4699 SDNode *Use = *II; 4700 if (Use == Ptr.getNode()) 4701 continue; 4702 4703 // If all the uses are load / store addresses, then don't do the 4704 // transformation. 4705 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){ 4706 bool RealUse = false; 4707 for (SDNode::use_iterator III = Use->use_begin(), 4708 EEE = Use->use_end(); III != EEE; ++III) { 4709 SDNode *UseUse = *III; 4710 if (!((UseUse->getOpcode() == ISD::LOAD && 4711 cast<LoadSDNode>(UseUse)->getBasePtr().getNode() == Use) || 4712 (UseUse->getOpcode() == ISD::STORE && 4713 cast<StoreSDNode>(UseUse)->getBasePtr().getNode() == Use))) 4714 RealUse = true; 4715 } 4716 4717 if (!RealUse) { 4718 TryNext = true; 4719 break; 4720 } 4721 } 4722 } 4723 4724 if (TryNext) 4725 continue; 4726 4727 // Check for #2 4728 if (!Op->isPredecessorOf(N) && !N->isPredecessorOf(Op)) { 4729 SDValue Result = isLoad 4730 ? DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(), 4731 BasePtr, Offset, AM) 4732 : DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(), 4733 BasePtr, Offset, AM); 4734 ++PostIndexedNodes; 4735 ++NodesCombined; 4736 DOUT << "\nReplacing.5 "; DEBUG(N->dump(&DAG)); 4737 DOUT << "\nWith: "; DEBUG(Result.getNode()->dump(&DAG)); 4738 DOUT << '\n'; 4739 WorkListRemover DeadNodes(*this); 4740 if (isLoad) { 4741 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0), 4742 &DeadNodes); 4743 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2), 4744 &DeadNodes); 4745 } else { 4746 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1), 4747 &DeadNodes); 4748 } 4749 4750 // Finally, since the node is now dead, remove it from the graph. 4751 DAG.DeleteNode(N); 4752 4753 // Replace the uses of Use with uses of the updated base value. 4754 DAG.ReplaceAllUsesOfValueWith(SDValue(Op, 0), 4755 Result.getValue(isLoad ? 1 : 0), 4756 &DeadNodes); 4757 removeFromWorkList(Op); 4758 DAG.DeleteNode(Op); 4759 return true; 4760 } 4761 } 4762 } 4763 4764 return false; 4765} 4766 4767/// InferAlignment - If we can infer some alignment information from this 4768/// pointer, return it. 4769static unsigned InferAlignment(SDValue Ptr, SelectionDAG &DAG) { 4770 // If this is a direct reference to a stack slot, use information about the 4771 // stack slot's alignment. 4772 int FrameIdx = 1 << 31; 4773 int64_t FrameOffset = 0; 4774 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Ptr)) { 4775 FrameIdx = FI->getIndex(); 4776 } else if (Ptr.getOpcode() == ISD::ADD && 4777 isa<ConstantSDNode>(Ptr.getOperand(1)) && 4778 isa<FrameIndexSDNode>(Ptr.getOperand(0))) { 4779 FrameIdx = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex(); 4780 FrameOffset = Ptr.getConstantOperandVal(1); 4781 } 4782 4783 if (FrameIdx != (1 << 31)) { 4784 // FIXME: Handle FI+CST. 4785 const MachineFrameInfo &MFI = *DAG.getMachineFunction().getFrameInfo(); 4786 if (MFI.isFixedObjectIndex(FrameIdx)) { 4787 int64_t ObjectOffset = MFI.getObjectOffset(FrameIdx) + FrameOffset; 4788 4789 // The alignment of the frame index can be determined from its offset from 4790 // the incoming frame position. If the frame object is at offset 32 and 4791 // the stack is guaranteed to be 16-byte aligned, then we know that the 4792 // object is 16-byte aligned. 4793 unsigned StackAlign = DAG.getTarget().getFrameInfo()->getStackAlignment(); 4794 unsigned Align = MinAlign(ObjectOffset, StackAlign); 4795 4796 // Finally, the frame object itself may have a known alignment. Factor 4797 // the alignment + offset into a new alignment. For example, if we know 4798 // the FI is 8 byte aligned, but the pointer is 4 off, we really have a 4799 // 4-byte alignment of the resultant pointer. Likewise align 4 + 4-byte 4800 // offset = 4-byte alignment, align 4 + 1-byte offset = align 1, etc. 4801 unsigned FIInfoAlign = MinAlign(MFI.getObjectAlignment(FrameIdx), 4802 FrameOffset); 4803 return std::max(Align, FIInfoAlign); 4804 } 4805 } 4806 4807 return 0; 4808} 4809 4810SDValue DAGCombiner::visitLOAD(SDNode *N) { 4811 LoadSDNode *LD = cast<LoadSDNode>(N); 4812 SDValue Chain = LD->getChain(); 4813 SDValue Ptr = LD->getBasePtr(); 4814 4815 // Try to infer better alignment information than the load already has. 4816 if (OptLevel != CodeGenOpt::None && LD->isUnindexed()) { 4817 if (unsigned Align = InferAlignment(Ptr, DAG)) { 4818 if (Align > LD->getAlignment()) 4819 return DAG.getExtLoad(LD->getExtensionType(), N->getDebugLoc(), 4820 LD->getValueType(0), 4821 Chain, Ptr, LD->getSrcValue(), 4822 LD->getSrcValueOffset(), LD->getMemoryVT(), 4823 LD->isVolatile(), Align); 4824 } 4825 } 4826 4827 // If load is not volatile and there are no uses of the loaded value (and 4828 // the updated indexed value in case of indexed loads), change uses of the 4829 // chain value into uses of the chain input (i.e. delete the dead load). 4830 if (!LD->isVolatile()) { 4831 if (N->getValueType(1) == MVT::Other) { 4832 // Unindexed loads. 4833 if (N->hasNUsesOfValue(0, 0)) { 4834 // It's not safe to use the two value CombineTo variant here. e.g. 4835 // v1, chain2 = load chain1, loc 4836 // v2, chain3 = load chain2, loc 4837 // v3 = add v2, c 4838 // Now we replace use of chain2 with chain1. This makes the second load 4839 // isomorphic to the one we are deleting, and thus makes this load live. 4840 DOUT << "\nReplacing.6 "; DEBUG(N->dump(&DAG)); 4841 DOUT << "\nWith chain: "; DEBUG(Chain.getNode()->dump(&DAG)); 4842 DOUT << "\n"; 4843 WorkListRemover DeadNodes(*this); 4844 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Chain, &DeadNodes); 4845 4846 if (N->use_empty()) { 4847 removeFromWorkList(N); 4848 DAG.DeleteNode(N); 4849 } 4850 4851 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4852 } 4853 } else { 4854 // Indexed loads. 4855 assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?"); 4856 if (N->hasNUsesOfValue(0, 0) && N->hasNUsesOfValue(0, 1)) { 4857 SDValue Undef = DAG.getUNDEF(N->getValueType(0)); 4858 DOUT << "\nReplacing.6 "; DEBUG(N->dump(&DAG)); 4859 DOUT << "\nWith: "; DEBUG(Undef.getNode()->dump(&DAG)); 4860 DOUT << " and 2 other values\n"; 4861 WorkListRemover DeadNodes(*this); 4862 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Undef, &DeadNodes); 4863 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), 4864 DAG.getUNDEF(N->getValueType(1)), 4865 &DeadNodes); 4866 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 2), Chain, &DeadNodes); 4867 removeFromWorkList(N); 4868 DAG.DeleteNode(N); 4869 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4870 } 4871 } 4872 } 4873 4874 // If this load is directly stored, replace the load value with the stored 4875 // value. 4876 // TODO: Handle store large -> read small portion. 4877 // TODO: Handle TRUNCSTORE/LOADEXT 4878 if (LD->getExtensionType() == ISD::NON_EXTLOAD && 4879 !LD->isVolatile()) { 4880 if (ISD::isNON_TRUNCStore(Chain.getNode())) { 4881 StoreSDNode *PrevST = cast<StoreSDNode>(Chain); 4882 if (PrevST->getBasePtr() == Ptr && 4883 PrevST->getValue().getValueType() == N->getValueType(0)) 4884 return CombineTo(N, Chain.getOperand(1), Chain); 4885 } 4886 } 4887 4888 if (CombinerAA) { 4889 // Walk up chain skipping non-aliasing memory nodes. 4890 SDValue BetterChain = FindBetterChain(N, Chain); 4891 4892 // If there is a better chain. 4893 if (Chain != BetterChain) { 4894 SDValue ReplLoad; 4895 4896 // Replace the chain to void dependency. 4897 if (LD->getExtensionType() == ISD::NON_EXTLOAD) { 4898 ReplLoad = DAG.getLoad(N->getValueType(0), LD->getDebugLoc(), 4899 BetterChain, Ptr, 4900 LD->getSrcValue(), LD->getSrcValueOffset(), 4901 LD->isVolatile(), LD->getAlignment()); 4902 } else { 4903 ReplLoad = DAG.getExtLoad(LD->getExtensionType(), LD->getDebugLoc(), 4904 LD->getValueType(0), 4905 BetterChain, Ptr, LD->getSrcValue(), 4906 LD->getSrcValueOffset(), 4907 LD->getMemoryVT(), 4908 LD->isVolatile(), 4909 LD->getAlignment()); 4910 } 4911 4912 // Create token factor to keep old chain connected. 4913 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 4914 MVT::Other, Chain, ReplLoad.getValue(1)); 4915 4916 // Replace uses with load result and token factor. Don't add users 4917 // to work list. 4918 return CombineTo(N, ReplLoad.getValue(0), Token, false); 4919 } 4920 } 4921 4922 // Try transforming N to an indexed load. 4923 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 4924 return SDValue(N, 0); 4925 4926 return SDValue(); 4927} 4928 4929 4930/// ReduceLoadOpStoreWidth - Look for sequence of load / op / store where op is 4931/// one of 'or', 'xor', and 'and' of immediates. If 'op' is only touching some 4932/// of the loaded bits, try narrowing the load and store if it would end up 4933/// being a win for performance or code size. 4934SDValue DAGCombiner::ReduceLoadOpStoreWidth(SDNode *N) { 4935 StoreSDNode *ST = cast<StoreSDNode>(N); 4936 if (ST->isVolatile()) 4937 return SDValue(); 4938 4939 SDValue Chain = ST->getChain(); 4940 SDValue Value = ST->getValue(); 4941 SDValue Ptr = ST->getBasePtr(); 4942 MVT VT = Value.getValueType(); 4943 4944 if (ST->isTruncatingStore() || VT.isVector() || !Value.hasOneUse()) 4945 return SDValue(); 4946 4947 unsigned Opc = Value.getOpcode(); 4948 if ((Opc != ISD::OR && Opc != ISD::XOR && Opc != ISD::AND) || 4949 Value.getOperand(1).getOpcode() != ISD::Constant) 4950 return SDValue(); 4951 4952 SDValue N0 = Value.getOperand(0); 4953 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse()) { 4954 LoadSDNode *LD = cast<LoadSDNode>(N0); 4955 if (LD->getBasePtr() != Ptr) 4956 return SDValue(); 4957 4958 // Find the type to narrow it the load / op / store to. 4959 SDValue N1 = Value.getOperand(1); 4960 unsigned BitWidth = N1.getValueSizeInBits(); 4961 APInt Imm = cast<ConstantSDNode>(N1)->getAPIntValue(); 4962 if (Opc == ISD::AND) 4963 Imm ^= APInt::getAllOnesValue(BitWidth); 4964 if (Imm == 0 || Imm.isAllOnesValue()) 4965 return SDValue(); 4966 unsigned ShAmt = Imm.countTrailingZeros(); 4967 unsigned MSB = BitWidth - Imm.countLeadingZeros() - 1; 4968 unsigned NewBW = NextPowerOf2(MSB - ShAmt); 4969 MVT NewVT = MVT::getIntegerVT(NewBW); 4970 while (NewBW < BitWidth && 4971 !(TLI.isOperationLegalOrCustom(Opc, NewVT) && 4972 TLI.isNarrowingProfitable(VT, NewVT))) { 4973 NewBW = NextPowerOf2(NewBW); 4974 NewVT = MVT::getIntegerVT(NewBW); 4975 } 4976 if (NewBW >= BitWidth) 4977 return SDValue(); 4978 4979 // If the lsb changed does not start at the type bitwidth boundary, 4980 // start at the previous one. 4981 if (ShAmt % NewBW) 4982 ShAmt = (((ShAmt + NewBW - 1) / NewBW) * NewBW) - NewBW; 4983 APInt Mask = APInt::getBitsSet(BitWidth, ShAmt, ShAmt + NewBW); 4984 if ((Imm & Mask) == Imm) { 4985 APInt NewImm = (Imm & Mask).lshr(ShAmt).trunc(NewBW); 4986 if (Opc == ISD::AND) 4987 NewImm ^= APInt::getAllOnesValue(NewBW); 4988 uint64_t PtrOff = ShAmt / 8; 4989 // For big endian targets, we need to adjust the offset to the pointer to 4990 // load the correct bytes. 4991 if (TLI.isBigEndian()) 4992 PtrOff = (BitWidth + 7 - NewBW) / 8 - PtrOff; 4993 4994 unsigned NewAlign = MinAlign(LD->getAlignment(), PtrOff); 4995 if (NewAlign < 4996 TLI.getTargetData()->getABITypeAlignment(NewVT.getTypeForMVT( 4997 *DAG.getContext()))) 4998 return SDValue(); 4999 5000 SDValue NewPtr = DAG.getNode(ISD::ADD, LD->getDebugLoc(), 5001 Ptr.getValueType(), Ptr, 5002 DAG.getConstant(PtrOff, Ptr.getValueType())); 5003 SDValue NewLD = DAG.getLoad(NewVT, N0.getDebugLoc(), 5004 LD->getChain(), NewPtr, 5005 LD->getSrcValue(), LD->getSrcValueOffset(), 5006 LD->isVolatile(), NewAlign); 5007 SDValue NewVal = DAG.getNode(Opc, Value.getDebugLoc(), NewVT, NewLD, 5008 DAG.getConstant(NewImm, NewVT)); 5009 SDValue NewST = DAG.getStore(Chain, N->getDebugLoc(), 5010 NewVal, NewPtr, 5011 ST->getSrcValue(), ST->getSrcValueOffset(), 5012 false, NewAlign); 5013 5014 AddToWorkList(NewPtr.getNode()); 5015 AddToWorkList(NewLD.getNode()); 5016 AddToWorkList(NewVal.getNode()); 5017 WorkListRemover DeadNodes(*this); 5018 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), NewLD.getValue(1), 5019 &DeadNodes); 5020 ++OpsNarrowed; 5021 return NewST; 5022 } 5023 } 5024 5025 return SDValue(); 5026} 5027 5028SDValue DAGCombiner::visitSTORE(SDNode *N) { 5029 StoreSDNode *ST = cast<StoreSDNode>(N); 5030 SDValue Chain = ST->getChain(); 5031 SDValue Value = ST->getValue(); 5032 SDValue Ptr = ST->getBasePtr(); 5033 5034 // Try to infer better alignment information than the store already has. 5035 if (OptLevel != CodeGenOpt::None && ST->isUnindexed()) { 5036 if (unsigned Align = InferAlignment(Ptr, DAG)) { 5037 if (Align > ST->getAlignment()) 5038 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value, 5039 Ptr, ST->getSrcValue(), 5040 ST->getSrcValueOffset(), ST->getMemoryVT(), 5041 ST->isVolatile(), Align); 5042 } 5043 } 5044 5045 // If this is a store of a bit convert, store the input value if the 5046 // resultant store does not need a higher alignment than the original. 5047 if (Value.getOpcode() == ISD::BIT_CONVERT && !ST->isTruncatingStore() && 5048 ST->isUnindexed()) { 5049 unsigned OrigAlign = ST->getAlignment(); 5050 MVT SVT = Value.getOperand(0).getValueType(); 5051 unsigned Align = TLI.getTargetData()-> 5052 getABITypeAlignment(SVT.getTypeForMVT(*DAG.getContext())); 5053 if (Align <= OrigAlign && 5054 ((!LegalOperations && !ST->isVolatile()) || 5055 TLI.isOperationLegalOrCustom(ISD::STORE, SVT))) 5056 return DAG.getStore(Chain, N->getDebugLoc(), Value.getOperand(0), 5057 Ptr, ST->getSrcValue(), 5058 ST->getSrcValueOffset(), ST->isVolatile(), OrigAlign); 5059 } 5060 5061 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 5062 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) { 5063 // NOTE: If the original store is volatile, this transform must not increase 5064 // the number of stores. For example, on x86-32 an f64 can be stored in one 5065 // processor operation but an i64 (which is not legal) requires two. So the 5066 // transform should not be done in this case. 5067 if (Value.getOpcode() != ISD::TargetConstantFP) { 5068 SDValue Tmp; 5069 switch (CFP->getValueType(0).getSimpleVT()) { 5070 default: llvm_unreachable("Unknown FP type"); 5071 case MVT::f80: // We don't do this for these yet. 5072 case MVT::f128: 5073 case MVT::ppcf128: 5074 break; 5075 case MVT::f32: 5076 if (((TLI.isTypeLegal(MVT::i32) || !LegalTypes) && !LegalOperations && 5077 !ST->isVolatile()) || 5078 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) { 5079 Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF(). 5080 bitcastToAPInt().getZExtValue(), MVT::i32); 5081 return DAG.getStore(Chain, N->getDebugLoc(), Tmp, 5082 Ptr, ST->getSrcValue(), 5083 ST->getSrcValueOffset(), ST->isVolatile(), 5084 ST->getAlignment()); 5085 } 5086 break; 5087 case MVT::f64: 5088 if (((TLI.isTypeLegal(MVT::i64) || !LegalTypes) && !LegalOperations && 5089 !ST->isVolatile()) || 5090 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i64)) { 5091 Tmp = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt(). 5092 getZExtValue(), MVT::i64); 5093 return DAG.getStore(Chain, N->getDebugLoc(), Tmp, 5094 Ptr, ST->getSrcValue(), 5095 ST->getSrcValueOffset(), ST->isVolatile(), 5096 ST->getAlignment()); 5097 } else if (!ST->isVolatile() && 5098 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) { 5099 // Many FP stores are not made apparent until after legalize, e.g. for 5100 // argument passing. Since this is so common, custom legalize the 5101 // 64-bit integer store into two 32-bit stores. 5102 uint64_t Val = CFP->getValueAPF().bitcastToAPInt().getZExtValue(); 5103 SDValue Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32); 5104 SDValue Hi = DAG.getConstant(Val >> 32, MVT::i32); 5105 if (TLI.isBigEndian()) std::swap(Lo, Hi); 5106 5107 int SVOffset = ST->getSrcValueOffset(); 5108 unsigned Alignment = ST->getAlignment(); 5109 bool isVolatile = ST->isVolatile(); 5110 5111 SDValue St0 = DAG.getStore(Chain, ST->getDebugLoc(), Lo, 5112 Ptr, ST->getSrcValue(), 5113 ST->getSrcValueOffset(), 5114 isVolatile, ST->getAlignment()); 5115 Ptr = DAG.getNode(ISD::ADD, N->getDebugLoc(), Ptr.getValueType(), Ptr, 5116 DAG.getConstant(4, Ptr.getValueType())); 5117 SVOffset += 4; 5118 Alignment = MinAlign(Alignment, 4U); 5119 SDValue St1 = DAG.getStore(Chain, ST->getDebugLoc(), Hi, 5120 Ptr, ST->getSrcValue(), 5121 SVOffset, isVolatile, Alignment); 5122 return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, 5123 St0, St1); 5124 } 5125 5126 break; 5127 } 5128 } 5129 } 5130 5131 if (CombinerAA) { 5132 // Walk up chain skipping non-aliasing memory nodes. 5133 SDValue BetterChain = FindBetterChain(N, Chain); 5134 5135 // If there is a better chain. 5136 if (Chain != BetterChain) { 5137 // Replace the chain to avoid dependency. 5138 SDValue ReplStore; 5139 if (ST->isTruncatingStore()) { 5140 ReplStore = DAG.getTruncStore(BetterChain, N->getDebugLoc(), Value, Ptr, 5141 ST->getSrcValue(),ST->getSrcValueOffset(), 5142 ST->getMemoryVT(), 5143 ST->isVolatile(), ST->getAlignment()); 5144 } else { 5145 ReplStore = DAG.getStore(BetterChain, N->getDebugLoc(), Value, Ptr, 5146 ST->getSrcValue(), ST->getSrcValueOffset(), 5147 ST->isVolatile(), ST->getAlignment()); 5148 } 5149 5150 // Create token to keep both nodes around. 5151 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 5152 MVT::Other, Chain, ReplStore); 5153 5154 // Don't add users to work list. 5155 return CombineTo(N, Token, false); 5156 } 5157 } 5158 5159 // Try transforming N to an indexed store. 5160 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 5161 return SDValue(N, 0); 5162 5163 // FIXME: is there such a thing as a truncating indexed store? 5164 if (ST->isTruncatingStore() && ST->isUnindexed() && 5165 Value.getValueType().isInteger()) { 5166 // See if we can simplify the input to this truncstore with knowledge that 5167 // only the low bits are being used. For example: 5168 // "truncstore (or (shl x, 8), y), i8" -> "truncstore y, i8" 5169 SDValue Shorter = 5170 GetDemandedBits(Value, 5171 APInt::getLowBitsSet(Value.getValueSizeInBits(), 5172 ST->getMemoryVT().getSizeInBits())); 5173 AddToWorkList(Value.getNode()); 5174 if (Shorter.getNode()) 5175 return DAG.getTruncStore(Chain, N->getDebugLoc(), Shorter, 5176 Ptr, ST->getSrcValue(), 5177 ST->getSrcValueOffset(), ST->getMemoryVT(), 5178 ST->isVolatile(), ST->getAlignment()); 5179 5180 // Otherwise, see if we can simplify the operation with 5181 // SimplifyDemandedBits, which only works if the value has a single use. 5182 if (SimplifyDemandedBits(Value, 5183 APInt::getLowBitsSet( 5184 Value.getValueSizeInBits(), 5185 ST->getMemoryVT().getSizeInBits()))) 5186 return SDValue(N, 0); 5187 } 5188 5189 // If this is a load followed by a store to the same location, then the store 5190 // is dead/noop. 5191 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Value)) { 5192 if (Ld->getBasePtr() == Ptr && ST->getMemoryVT() == Ld->getMemoryVT() && 5193 ST->isUnindexed() && !ST->isVolatile() && 5194 // There can't be any side effects between the load and store, such as 5195 // a call or store. 5196 Chain.reachesChainWithoutSideEffects(SDValue(Ld, 1))) { 5197 // The store is dead, remove it. 5198 return Chain; 5199 } 5200 } 5201 5202 // If this is an FP_ROUND or TRUNC followed by a store, fold this into a 5203 // truncating store. We can do this even if this is already a truncstore. 5204 if ((Value.getOpcode() == ISD::FP_ROUND || Value.getOpcode() == ISD::TRUNCATE) 5205 && Value.getNode()->hasOneUse() && ST->isUnindexed() && 5206 TLI.isTruncStoreLegal(Value.getOperand(0).getValueType(), 5207 ST->getMemoryVT())) { 5208 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value.getOperand(0), 5209 Ptr, ST->getSrcValue(), 5210 ST->getSrcValueOffset(), ST->getMemoryVT(), 5211 ST->isVolatile(), ST->getAlignment()); 5212 } 5213 5214 return ReduceLoadOpStoreWidth(N); 5215} 5216 5217SDValue DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) { 5218 SDValue InVec = N->getOperand(0); 5219 SDValue InVal = N->getOperand(1); 5220 SDValue EltNo = N->getOperand(2); 5221 5222 // If the invec is a BUILD_VECTOR and if EltNo is a constant, build a new 5223 // vector with the inserted element. 5224 if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) { 5225 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 5226 SmallVector<SDValue, 8> Ops(InVec.getNode()->op_begin(), 5227 InVec.getNode()->op_end()); 5228 if (Elt < Ops.size()) 5229 Ops[Elt] = InVal; 5230 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 5231 InVec.getValueType(), &Ops[0], Ops.size()); 5232 } 5233 // If the invec is an UNDEF and if EltNo is a constant, create a new 5234 // BUILD_VECTOR with undef elements and the inserted element. 5235 if (!LegalOperations && InVec.getOpcode() == ISD::UNDEF && 5236 isa<ConstantSDNode>(EltNo)) { 5237 MVT VT = InVec.getValueType(); 5238 MVT EVT = VT.getVectorElementType(); 5239 unsigned NElts = VT.getVectorNumElements(); 5240 SmallVector<SDValue, 8> Ops(NElts, DAG.getUNDEF(EVT)); 5241 5242 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 5243 if (Elt < Ops.size()) 5244 Ops[Elt] = InVal; 5245 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 5246 InVec.getValueType(), &Ops[0], Ops.size()); 5247 } 5248 return SDValue(); 5249} 5250 5251SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) { 5252 // (vextract (scalar_to_vector val, 0) -> val 5253 SDValue InVec = N->getOperand(0); 5254 5255 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) { 5256 // If the operand is wider than the vector element type then it is implicitly 5257 // truncated. Make that explicit here. 5258 MVT EltVT = InVec.getValueType().getVectorElementType(); 5259 SDValue InOp = InVec.getOperand(0); 5260 if (InOp.getValueType() != EltVT) 5261 return DAG.getNode(ISD::TRUNCATE, InVec.getDebugLoc(), EltVT, InOp); 5262 return InOp; 5263 } 5264 5265 // Perform only after legalization to ensure build_vector / vector_shuffle 5266 // optimizations have already been done. 5267 if (!LegalOperations) return SDValue(); 5268 5269 // (vextract (v4f32 load $addr), c) -> (f32 load $addr+c*size) 5270 // (vextract (v4f32 s2v (f32 load $addr)), c) -> (f32 load $addr+c*size) 5271 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), 0) -> (f32 load $addr) 5272 SDValue EltNo = N->getOperand(1); 5273 5274 if (isa<ConstantSDNode>(EltNo)) { 5275 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 5276 bool NewLoad = false; 5277 bool BCNumEltsChanged = false; 5278 MVT VT = InVec.getValueType(); 5279 MVT EVT = VT.getVectorElementType(); 5280 MVT LVT = EVT; 5281 5282 if (InVec.getOpcode() == ISD::BIT_CONVERT) { 5283 MVT BCVT = InVec.getOperand(0).getValueType(); 5284 if (!BCVT.isVector() || EVT.bitsGT(BCVT.getVectorElementType())) 5285 return SDValue(); 5286 if (VT.getVectorNumElements() != BCVT.getVectorNumElements()) 5287 BCNumEltsChanged = true; 5288 InVec = InVec.getOperand(0); 5289 EVT = BCVT.getVectorElementType(); 5290 NewLoad = true; 5291 } 5292 5293 LoadSDNode *LN0 = NULL; 5294 const ShuffleVectorSDNode *SVN = NULL; 5295 if (ISD::isNormalLoad(InVec.getNode())) { 5296 LN0 = cast<LoadSDNode>(InVec); 5297 } else if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR && 5298 InVec.getOperand(0).getValueType() == EVT && 5299 ISD::isNormalLoad(InVec.getOperand(0).getNode())) { 5300 LN0 = cast<LoadSDNode>(InVec.getOperand(0)); 5301 } else if ((SVN = dyn_cast<ShuffleVectorSDNode>(InVec))) { 5302 // (vextract (vector_shuffle (load $addr), v2, <1, u, u, u>), 1) 5303 // => 5304 // (load $addr+1*size) 5305 5306 // If the bit convert changed the number of elements, it is unsafe 5307 // to examine the mask. 5308 if (BCNumEltsChanged) 5309 return SDValue(); 5310 5311 // Select the input vector, guarding against out of range extract vector. 5312 unsigned NumElems = VT.getVectorNumElements(); 5313 int Idx = (Elt > NumElems) ? -1 : SVN->getMaskElt(Elt); 5314 InVec = (Idx < (int)NumElems) ? InVec.getOperand(0) : InVec.getOperand(1); 5315 5316 if (InVec.getOpcode() == ISD::BIT_CONVERT) 5317 InVec = InVec.getOperand(0); 5318 if (ISD::isNormalLoad(InVec.getNode())) { 5319 LN0 = cast<LoadSDNode>(InVec); 5320 Elt = (Idx < (int)NumElems) ? Idx : Idx - NumElems; 5321 } 5322 } 5323 5324 if (!LN0 || !LN0->hasOneUse() || LN0->isVolatile()) 5325 return SDValue(); 5326 5327 unsigned Align = LN0->getAlignment(); 5328 if (NewLoad) { 5329 // Check the resultant load doesn't need a higher alignment than the 5330 // original load. 5331 unsigned NewAlign = 5332 TLI.getTargetData()->getABITypeAlignment(LVT.getTypeForMVT( 5333 *DAG.getContext())); 5334 5335 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, LVT)) 5336 return SDValue(); 5337 5338 Align = NewAlign; 5339 } 5340 5341 SDValue NewPtr = LN0->getBasePtr(); 5342 if (Elt) { 5343 unsigned PtrOff = LVT.getSizeInBits() * Elt / 8; 5344 MVT PtrType = NewPtr.getValueType(); 5345 if (TLI.isBigEndian()) 5346 PtrOff = VT.getSizeInBits() / 8 - PtrOff; 5347 NewPtr = DAG.getNode(ISD::ADD, N->getDebugLoc(), PtrType, NewPtr, 5348 DAG.getConstant(PtrOff, PtrType)); 5349 } 5350 5351 return DAG.getLoad(LVT, N->getDebugLoc(), LN0->getChain(), NewPtr, 5352 LN0->getSrcValue(), LN0->getSrcValueOffset(), 5353 LN0->isVolatile(), Align); 5354 } 5355 5356 return SDValue(); 5357} 5358 5359SDValue DAGCombiner::visitBUILD_VECTOR(SDNode *N) { 5360 unsigned NumInScalars = N->getNumOperands(); 5361 MVT VT = N->getValueType(0); 5362 MVT EltType = VT.getVectorElementType(); 5363 5364 // Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT 5365 // operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from 5366 // at most two distinct vectors, turn this into a shuffle node. 5367 SDValue VecIn1, VecIn2; 5368 for (unsigned i = 0; i != NumInScalars; ++i) { 5369 // Ignore undef inputs. 5370 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 5371 5372 // If this input is something other than a EXTRACT_VECTOR_ELT with a 5373 // constant index, bail out. 5374 if (N->getOperand(i).getOpcode() != ISD::EXTRACT_VECTOR_ELT || 5375 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) { 5376 VecIn1 = VecIn2 = SDValue(0, 0); 5377 break; 5378 } 5379 5380 // If the input vector type disagrees with the result of the build_vector, 5381 // we can't make a shuffle. 5382 SDValue ExtractedFromVec = N->getOperand(i).getOperand(0); 5383 if (ExtractedFromVec.getValueType() != VT) { 5384 VecIn1 = VecIn2 = SDValue(0, 0); 5385 break; 5386 } 5387 5388 // Otherwise, remember this. We allow up to two distinct input vectors. 5389 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2) 5390 continue; 5391 5392 if (VecIn1.getNode() == 0) { 5393 VecIn1 = ExtractedFromVec; 5394 } else if (VecIn2.getNode() == 0) { 5395 VecIn2 = ExtractedFromVec; 5396 } else { 5397 // Too many inputs. 5398 VecIn1 = VecIn2 = SDValue(0, 0); 5399 break; 5400 } 5401 } 5402 5403 // If everything is good, we can make a shuffle operation. 5404 if (VecIn1.getNode()) { 5405 SmallVector<int, 8> Mask; 5406 for (unsigned i = 0; i != NumInScalars; ++i) { 5407 if (N->getOperand(i).getOpcode() == ISD::UNDEF) { 5408 Mask.push_back(-1); 5409 continue; 5410 } 5411 5412 // If extracting from the first vector, just use the index directly. 5413 SDValue Extract = N->getOperand(i); 5414 SDValue ExtVal = Extract.getOperand(1); 5415 if (Extract.getOperand(0) == VecIn1) { 5416 unsigned ExtIndex = cast<ConstantSDNode>(ExtVal)->getZExtValue(); 5417 if (ExtIndex > VT.getVectorNumElements()) 5418 return SDValue(); 5419 5420 Mask.push_back(ExtIndex); 5421 continue; 5422 } 5423 5424 // Otherwise, use InIdx + VecSize 5425 unsigned Idx = cast<ConstantSDNode>(ExtVal)->getZExtValue(); 5426 Mask.push_back(Idx+NumInScalars); 5427 } 5428 5429 // Add count and size info. 5430 if (!TLI.isTypeLegal(VT) && LegalTypes) 5431 return SDValue(); 5432 5433 // Return the new VECTOR_SHUFFLE node. 5434 SDValue Ops[2]; 5435 Ops[0] = VecIn1; 5436 Ops[1] = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT); 5437 return DAG.getVectorShuffle(VT, N->getDebugLoc(), Ops[0], Ops[1], &Mask[0]); 5438 } 5439 5440 return SDValue(); 5441} 5442 5443SDValue DAGCombiner::visitCONCAT_VECTORS(SDNode *N) { 5444 // TODO: Check to see if this is a CONCAT_VECTORS of a bunch of 5445 // EXTRACT_SUBVECTOR operations. If so, and if the EXTRACT_SUBVECTOR vector 5446 // inputs come from at most two distinct vectors, turn this into a shuffle 5447 // node. 5448 5449 // If we only have one input vector, we don't need to do any concatenation. 5450 if (N->getNumOperands() == 1) 5451 return N->getOperand(0); 5452 5453 return SDValue(); 5454} 5455 5456SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) { 5457 return SDValue(); 5458 5459 MVT VT = N->getValueType(0); 5460 unsigned NumElts = VT.getVectorNumElements(); 5461 5462 SDValue N0 = N->getOperand(0); 5463 SDValue N1 = N->getOperand(1); 5464 5465 assert(N0.getValueType().getVectorNumElements() == NumElts && 5466 "Vector shuffle must be normalized in DAG"); 5467 5468 // FIXME: implement canonicalizations from DAG.getVectorShuffle() 5469 5470 // If it is a splat, check if the argument vector is a build_vector with 5471 // all scalar elements the same. 5472 if (cast<ShuffleVectorSDNode>(N)->isSplat()) { 5473 SDNode *V = N0.getNode(); 5474 5475 5476 // If this is a bit convert that changes the element type of the vector but 5477 // not the number of vector elements, look through it. Be careful not to 5478 // look though conversions that change things like v4f32 to v2f64. 5479 if (V->getOpcode() == ISD::BIT_CONVERT) { 5480 SDValue ConvInput = V->getOperand(0); 5481 if (ConvInput.getValueType().isVector() && 5482 ConvInput.getValueType().getVectorNumElements() == NumElts) 5483 V = ConvInput.getNode(); 5484 } 5485 5486 if (V->getOpcode() == ISD::BUILD_VECTOR) { 5487 unsigned NumElems = V->getNumOperands(); 5488 unsigned BaseIdx = cast<ShuffleVectorSDNode>(N)->getSplatIndex(); 5489 if (NumElems > BaseIdx) { 5490 SDValue Base; 5491 bool AllSame = true; 5492 for (unsigned i = 0; i != NumElems; ++i) { 5493 if (V->getOperand(i).getOpcode() != ISD::UNDEF) { 5494 Base = V->getOperand(i); 5495 break; 5496 } 5497 } 5498 // Splat of <u, u, u, u>, return <u, u, u, u> 5499 if (!Base.getNode()) 5500 return N0; 5501 for (unsigned i = 0; i != NumElems; ++i) { 5502 if (V->getOperand(i) != Base) { 5503 AllSame = false; 5504 break; 5505 } 5506 } 5507 // Splat of <x, x, x, x>, return <x, x, x, x> 5508 if (AllSame) 5509 return N0; 5510 } 5511 } 5512 } 5513 return SDValue(); 5514} 5515 5516/// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform 5517/// an AND to a vector_shuffle with the destination vector and a zero vector. 5518/// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==> 5519/// vector_shuffle V, Zero, <0, 4, 2, 4> 5520SDValue DAGCombiner::XformToShuffleWithZero(SDNode *N) { 5521 MVT VT = N->getValueType(0); 5522 DebugLoc dl = N->getDebugLoc(); 5523 SDValue LHS = N->getOperand(0); 5524 SDValue RHS = N->getOperand(1); 5525 if (N->getOpcode() == ISD::AND) { 5526 if (RHS.getOpcode() == ISD::BIT_CONVERT) 5527 RHS = RHS.getOperand(0); 5528 if (RHS.getOpcode() == ISD::BUILD_VECTOR) { 5529 SmallVector<int, 8> Indices; 5530 unsigned NumElts = RHS.getNumOperands(); 5531 for (unsigned i = 0; i != NumElts; ++i) { 5532 SDValue Elt = RHS.getOperand(i); 5533 if (!isa<ConstantSDNode>(Elt)) 5534 return SDValue(); 5535 else if (cast<ConstantSDNode>(Elt)->isAllOnesValue()) 5536 Indices.push_back(i); 5537 else if (cast<ConstantSDNode>(Elt)->isNullValue()) 5538 Indices.push_back(NumElts); 5539 else 5540 return SDValue(); 5541 } 5542 5543 // Let's see if the target supports this vector_shuffle. 5544 MVT RVT = RHS.getValueType(); 5545 if (!TLI.isVectorClearMaskLegal(Indices, RVT)) 5546 return SDValue(); 5547 5548 // Return the new VECTOR_SHUFFLE node. 5549 MVT EVT = RVT.getVectorElementType(); 5550 SmallVector<SDValue,8> ZeroOps(RVT.getVectorNumElements(), 5551 DAG.getConstant(0, EVT)); 5552 SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 5553 RVT, &ZeroOps[0], ZeroOps.size()); 5554 LHS = DAG.getNode(ISD::BIT_CONVERT, dl, RVT, LHS); 5555 SDValue Shuf = DAG.getVectorShuffle(RVT, dl, LHS, Zero, &Indices[0]); 5556 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Shuf); 5557 } 5558 } 5559 5560 return SDValue(); 5561} 5562 5563/// SimplifyVBinOp - Visit a binary vector operation, like ADD. 5564SDValue DAGCombiner::SimplifyVBinOp(SDNode *N) { 5565 // After legalize, the target may be depending on adds and other 5566 // binary ops to provide legal ways to construct constants or other 5567 // things. Simplifying them may result in a loss of legality. 5568 if (LegalOperations) return SDValue(); 5569 5570 MVT VT = N->getValueType(0); 5571 assert(VT.isVector() && "SimplifyVBinOp only works on vectors!"); 5572 5573 MVT EltType = VT.getVectorElementType(); 5574 SDValue LHS = N->getOperand(0); 5575 SDValue RHS = N->getOperand(1); 5576 SDValue Shuffle = XformToShuffleWithZero(N); 5577 if (Shuffle.getNode()) return Shuffle; 5578 5579 // If the LHS and RHS are BUILD_VECTOR nodes, see if we can constant fold 5580 // this operation. 5581 if (LHS.getOpcode() == ISD::BUILD_VECTOR && 5582 RHS.getOpcode() == ISD::BUILD_VECTOR) { 5583 SmallVector<SDValue, 8> Ops; 5584 for (unsigned i = 0, e = LHS.getNumOperands(); i != e; ++i) { 5585 SDValue LHSOp = LHS.getOperand(i); 5586 SDValue RHSOp = RHS.getOperand(i); 5587 // If these two elements can't be folded, bail out. 5588 if ((LHSOp.getOpcode() != ISD::UNDEF && 5589 LHSOp.getOpcode() != ISD::Constant && 5590 LHSOp.getOpcode() != ISD::ConstantFP) || 5591 (RHSOp.getOpcode() != ISD::UNDEF && 5592 RHSOp.getOpcode() != ISD::Constant && 5593 RHSOp.getOpcode() != ISD::ConstantFP)) 5594 break; 5595 5596 // Can't fold divide by zero. 5597 if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV || 5598 N->getOpcode() == ISD::FDIV) { 5599 if ((RHSOp.getOpcode() == ISD::Constant && 5600 cast<ConstantSDNode>(RHSOp.getNode())->isNullValue()) || 5601 (RHSOp.getOpcode() == ISD::ConstantFP && 5602 cast<ConstantFPSDNode>(RHSOp.getNode())->getValueAPF().isZero())) 5603 break; 5604 } 5605 5606 Ops.push_back(DAG.getNode(N->getOpcode(), LHS.getDebugLoc(), 5607 EltType, LHSOp, RHSOp)); 5608 AddToWorkList(Ops.back().getNode()); 5609 assert((Ops.back().getOpcode() == ISD::UNDEF || 5610 Ops.back().getOpcode() == ISD::Constant || 5611 Ops.back().getOpcode() == ISD::ConstantFP) && 5612 "Scalar binop didn't fold!"); 5613 } 5614 5615 if (Ops.size() == LHS.getNumOperands()) { 5616 MVT VT = LHS.getValueType(); 5617 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT, 5618 &Ops[0], Ops.size()); 5619 } 5620 } 5621 5622 return SDValue(); 5623} 5624 5625SDValue DAGCombiner::SimplifySelect(DebugLoc DL, SDValue N0, 5626 SDValue N1, SDValue N2){ 5627 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!"); 5628 5629 SDValue SCC = SimplifySelectCC(DL, N0.getOperand(0), N0.getOperand(1), N1, N2, 5630 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 5631 5632 // If we got a simplified select_cc node back from SimplifySelectCC, then 5633 // break it down into a new SETCC node, and a new SELECT node, and then return 5634 // the SELECT node, since we were called with a SELECT node. 5635 if (SCC.getNode()) { 5636 // Check to see if we got a select_cc back (to turn into setcc/select). 5637 // Otherwise, just return whatever node we got back, like fabs. 5638 if (SCC.getOpcode() == ISD::SELECT_CC) { 5639 SDValue SETCC = DAG.getNode(ISD::SETCC, N0.getDebugLoc(), 5640 N0.getValueType(), 5641 SCC.getOperand(0), SCC.getOperand(1), 5642 SCC.getOperand(4)); 5643 AddToWorkList(SETCC.getNode()); 5644 return DAG.getNode(ISD::SELECT, SCC.getDebugLoc(), SCC.getValueType(), 5645 SCC.getOperand(2), SCC.getOperand(3), SETCC); 5646 } 5647 5648 return SCC; 5649 } 5650 return SDValue(); 5651} 5652 5653/// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS 5654/// are the two values being selected between, see if we can simplify the 5655/// select. Callers of this should assume that TheSelect is deleted if this 5656/// returns true. As such, they should return the appropriate thing (e.g. the 5657/// node) back to the top-level of the DAG combiner loop to avoid it being 5658/// looked at. 5659bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDValue LHS, 5660 SDValue RHS) { 5661 5662 // If this is a select from two identical things, try to pull the operation 5663 // through the select. 5664 if (LHS.getOpcode() == RHS.getOpcode() && LHS.hasOneUse() && RHS.hasOneUse()){ 5665 // If this is a load and the token chain is identical, replace the select 5666 // of two loads with a load through a select of the address to load from. 5667 // This triggers in things like "select bool X, 10.0, 123.0" after the FP 5668 // constants have been dropped into the constant pool. 5669 if (LHS.getOpcode() == ISD::LOAD && 5670 // Do not let this transformation reduce the number of volatile loads. 5671 !cast<LoadSDNode>(LHS)->isVolatile() && 5672 !cast<LoadSDNode>(RHS)->isVolatile() && 5673 // Token chains must be identical. 5674 LHS.getOperand(0) == RHS.getOperand(0)) { 5675 LoadSDNode *LLD = cast<LoadSDNode>(LHS); 5676 LoadSDNode *RLD = cast<LoadSDNode>(RHS); 5677 5678 // If this is an EXTLOAD, the VT's must match. 5679 if (LLD->getMemoryVT() == RLD->getMemoryVT()) { 5680 // FIXME: this conflates two src values, discarding one. This is not 5681 // the right thing to do, but nothing uses srcvalues now. When they do, 5682 // turn SrcValue into a list of locations. 5683 SDValue Addr; 5684 if (TheSelect->getOpcode() == ISD::SELECT) { 5685 // Check that the condition doesn't reach either load. If so, folding 5686 // this will induce a cycle into the DAG. 5687 if (!LLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) && 5688 !RLD->isPredecessorOf(TheSelect->getOperand(0).getNode())) { 5689 Addr = DAG.getNode(ISD::SELECT, TheSelect->getDebugLoc(), 5690 LLD->getBasePtr().getValueType(), 5691 TheSelect->getOperand(0), LLD->getBasePtr(), 5692 RLD->getBasePtr()); 5693 } 5694 } else { 5695 // Check that the condition doesn't reach either load. If so, folding 5696 // this will induce a cycle into the DAG. 5697 if (!LLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) && 5698 !RLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) && 5699 !LLD->isPredecessorOf(TheSelect->getOperand(1).getNode()) && 5700 !RLD->isPredecessorOf(TheSelect->getOperand(1).getNode())) { 5701 Addr = DAG.getNode(ISD::SELECT_CC, TheSelect->getDebugLoc(), 5702 LLD->getBasePtr().getValueType(), 5703 TheSelect->getOperand(0), 5704 TheSelect->getOperand(1), 5705 LLD->getBasePtr(), RLD->getBasePtr(), 5706 TheSelect->getOperand(4)); 5707 } 5708 } 5709 5710 if (Addr.getNode()) { 5711 SDValue Load; 5712 if (LLD->getExtensionType() == ISD::NON_EXTLOAD) { 5713 Load = DAG.getLoad(TheSelect->getValueType(0), 5714 TheSelect->getDebugLoc(), 5715 LLD->getChain(), 5716 Addr,LLD->getSrcValue(), 5717 LLD->getSrcValueOffset(), 5718 LLD->isVolatile(), 5719 LLD->getAlignment()); 5720 } else { 5721 Load = DAG.getExtLoad(LLD->getExtensionType(), 5722 TheSelect->getDebugLoc(), 5723 TheSelect->getValueType(0), 5724 LLD->getChain(), Addr, LLD->getSrcValue(), 5725 LLD->getSrcValueOffset(), 5726 LLD->getMemoryVT(), 5727 LLD->isVolatile(), 5728 LLD->getAlignment()); 5729 } 5730 5731 // Users of the select now use the result of the load. 5732 CombineTo(TheSelect, Load); 5733 5734 // Users of the old loads now use the new load's chain. We know the 5735 // old-load value is dead now. 5736 CombineTo(LHS.getNode(), Load.getValue(0), Load.getValue(1)); 5737 CombineTo(RHS.getNode(), Load.getValue(0), Load.getValue(1)); 5738 return true; 5739 } 5740 } 5741 } 5742 } 5743 5744 return false; 5745} 5746 5747/// SimplifySelectCC - Simplify an expression of the form (N0 cond N1) ? N2 : N3 5748/// where 'cond' is the comparison specified by CC. 5749SDValue DAGCombiner::SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, 5750 SDValue N2, SDValue N3, 5751 ISD::CondCode CC, bool NotExtCompare) { 5752 // (x ? y : y) -> y. 5753 if (N2 == N3) return N2; 5754 5755 MVT VT = N2.getValueType(); 5756 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 5757 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode()); 5758 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.getNode()); 5759 5760 // Determine if the condition we're dealing with is constant 5761 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()), 5762 N0, N1, CC, DL, false); 5763 if (SCC.getNode()) AddToWorkList(SCC.getNode()); 5764 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode()); 5765 5766 // fold select_cc true, x, y -> x 5767 if (SCCC && !SCCC->isNullValue()) 5768 return N2; 5769 // fold select_cc false, x, y -> y 5770 if (SCCC && SCCC->isNullValue()) 5771 return N3; 5772 5773 // Check to see if we can simplify the select into an fabs node 5774 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) { 5775 // Allow either -0.0 or 0.0 5776 if (CFP->getValueAPF().isZero()) { 5777 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs 5778 if ((CC == ISD::SETGE || CC == ISD::SETGT) && 5779 N0 == N2 && N3.getOpcode() == ISD::FNEG && 5780 N2 == N3.getOperand(0)) 5781 return DAG.getNode(ISD::FABS, DL, VT, N0); 5782 5783 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs 5784 if ((CC == ISD::SETLT || CC == ISD::SETLE) && 5785 N0 == N3 && N2.getOpcode() == ISD::FNEG && 5786 N2.getOperand(0) == N3) 5787 return DAG.getNode(ISD::FABS, DL, VT, N3); 5788 } 5789 } 5790 5791 // Turn "(a cond b) ? 1.0f : 2.0f" into "load (tmp + ((a cond b) ? 0 : 4)" 5792 // where "tmp" is a constant pool entry containing an array with 1.0 and 2.0 5793 // in it. This is a win when the constant is not otherwise available because 5794 // it replaces two constant pool loads with one. We only do this if the FP 5795 // type is known to be legal, because if it isn't, then we are before legalize 5796 // types an we want the other legalization to happen first (e.g. to avoid 5797 // messing with soft float) and if the ConstantFP is not legal, because if 5798 // it is legal, we may not need to store the FP constant in a constant pool. 5799 if (ConstantFPSDNode *TV = dyn_cast<ConstantFPSDNode>(N2)) 5800 if (ConstantFPSDNode *FV = dyn_cast<ConstantFPSDNode>(N3)) { 5801 if (TLI.isTypeLegal(N2.getValueType()) && 5802 (TLI.getOperationAction(ISD::ConstantFP, N2.getValueType()) != 5803 TargetLowering::Legal) && 5804 // If both constants have multiple uses, then we won't need to do an 5805 // extra load, they are likely around in registers for other users. 5806 (TV->hasOneUse() || FV->hasOneUse())) { 5807 Constant *Elts[] = { 5808 const_cast<ConstantFP*>(FV->getConstantFPValue()), 5809 const_cast<ConstantFP*>(TV->getConstantFPValue()) 5810 }; 5811 const Type *FPTy = Elts[0]->getType(); 5812 const TargetData &TD = *TLI.getTargetData(); 5813 5814 // Create a ConstantArray of the two constants. 5815 Constant *CA = DAG.getContext()->getConstantArray( 5816 DAG.getContext()->getArrayType(FPTy, 2), Elts, 2); 5817 SDValue CPIdx = DAG.getConstantPool(CA, TLI.getPointerTy(), 5818 TD.getPrefTypeAlignment(FPTy)); 5819 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 5820 5821 // Get the offsets to the 0 and 1 element of the array so that we can 5822 // select between them. 5823 SDValue Zero = DAG.getIntPtrConstant(0); 5824 unsigned EltSize = (unsigned)TD.getTypeAllocSize(Elts[0]->getType()); 5825 SDValue One = DAG.getIntPtrConstant(EltSize); 5826 5827 SDValue Cond = DAG.getSetCC(DL, 5828 TLI.getSetCCResultType(N0.getValueType()), 5829 N0, N1, CC); 5830 SDValue CstOffset = DAG.getNode(ISD::SELECT, DL, Zero.getValueType(), 5831 Cond, One, Zero); 5832 CPIdx = DAG.getNode(ISD::ADD, DL, TLI.getPointerTy(), CPIdx, 5833 CstOffset); 5834 return DAG.getLoad(TV->getValueType(0), DL, DAG.getEntryNode(), CPIdx, 5835 PseudoSourceValue::getConstantPool(), 0, false, 5836 Alignment); 5837 5838 } 5839 } 5840 5841 // Check to see if we can perform the "gzip trick", transforming 5842 // (select_cc setlt X, 0, A, 0) -> (and (sra X, (sub size(X), 1), A) 5843 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT && 5844 N0.getValueType().isInteger() && 5845 N2.getValueType().isInteger() && 5846 (N1C->isNullValue() || // (a < 0) ? b : 0 5847 (N1C->getAPIntValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0 5848 MVT XType = N0.getValueType(); 5849 MVT AType = N2.getValueType(); 5850 if (XType.bitsGE(AType)) { 5851 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a 5852 // single-bit constant. 5853 if (N2C && ((N2C->getAPIntValue() & (N2C->getAPIntValue()-1)) == 0)) { 5854 unsigned ShCtV = N2C->getAPIntValue().logBase2(); 5855 ShCtV = XType.getSizeInBits()-ShCtV-1; 5856 SDValue ShCt = DAG.getConstant(ShCtV, getShiftAmountTy()); 5857 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), 5858 XType, N0, ShCt); 5859 AddToWorkList(Shift.getNode()); 5860 5861 if (XType.bitsGT(AType)) { 5862 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift); 5863 AddToWorkList(Shift.getNode()); 5864 } 5865 5866 return DAG.getNode(ISD::AND, DL, AType, Shift, N2); 5867 } 5868 5869 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), 5870 XType, N0, 5871 DAG.getConstant(XType.getSizeInBits()-1, 5872 getShiftAmountTy())); 5873 AddToWorkList(Shift.getNode()); 5874 5875 if (XType.bitsGT(AType)) { 5876 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift); 5877 AddToWorkList(Shift.getNode()); 5878 } 5879 5880 return DAG.getNode(ISD::AND, DL, AType, Shift, N2); 5881 } 5882 } 5883 5884 // fold select C, 16, 0 -> shl C, 4 5885 if (N2C && N3C && N3C->isNullValue() && N2C->getAPIntValue().isPowerOf2() && 5886 TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent) { 5887 5888 // If the caller doesn't want us to simplify this into a zext of a compare, 5889 // don't do it. 5890 if (NotExtCompare && N2C->getAPIntValue() == 1) 5891 return SDValue(); 5892 5893 // Get a SetCC of the condition 5894 // FIXME: Should probably make sure that setcc is legal if we ever have a 5895 // target where it isn't. 5896 SDValue Temp, SCC; 5897 // cast from setcc result type to select result type 5898 if (LegalTypes) { 5899 SCC = DAG.getSetCC(DL, TLI.getSetCCResultType(N0.getValueType()), 5900 N0, N1, CC); 5901 if (N2.getValueType().bitsLT(SCC.getValueType())) 5902 Temp = DAG.getZeroExtendInReg(SCC, N2.getDebugLoc(), N2.getValueType()); 5903 else 5904 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(), 5905 N2.getValueType(), SCC); 5906 } else { 5907 SCC = DAG.getSetCC(N0.getDebugLoc(), MVT::i1, N0, N1, CC); 5908 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(), 5909 N2.getValueType(), SCC); 5910 } 5911 5912 AddToWorkList(SCC.getNode()); 5913 AddToWorkList(Temp.getNode()); 5914 5915 if (N2C->getAPIntValue() == 1) 5916 return Temp; 5917 5918 // shl setcc result by log2 n2c 5919 return DAG.getNode(ISD::SHL, DL, N2.getValueType(), Temp, 5920 DAG.getConstant(N2C->getAPIntValue().logBase2(), 5921 getShiftAmountTy())); 5922 } 5923 5924 // Check to see if this is the equivalent of setcc 5925 // FIXME: Turn all of these into setcc if setcc if setcc is legal 5926 // otherwise, go ahead with the folds. 5927 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getAPIntValue() == 1ULL)) { 5928 MVT XType = N0.getValueType(); 5929 if (!LegalOperations || 5930 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(XType))) { 5931 SDValue Res = DAG.getSetCC(DL, TLI.getSetCCResultType(XType), N0, N1, CC); 5932 if (Res.getValueType() != VT) 5933 Res = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, Res); 5934 return Res; 5935 } 5936 5937 // fold (seteq X, 0) -> (srl (ctlz X, log2(size(X)))) 5938 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ && 5939 (!LegalOperations || 5940 TLI.isOperationLegal(ISD::CTLZ, XType))) { 5941 SDValue Ctlz = DAG.getNode(ISD::CTLZ, N0.getDebugLoc(), XType, N0); 5942 return DAG.getNode(ISD::SRL, DL, XType, Ctlz, 5943 DAG.getConstant(Log2_32(XType.getSizeInBits()), 5944 getShiftAmountTy())); 5945 } 5946 // fold (setgt X, 0) -> (srl (and (-X, ~X), size(X)-1)) 5947 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) { 5948 SDValue NegN0 = DAG.getNode(ISD::SUB, N0.getDebugLoc(), 5949 XType, DAG.getConstant(0, XType), N0); 5950 SDValue NotN0 = DAG.getNOT(N0.getDebugLoc(), N0, XType); 5951 return DAG.getNode(ISD::SRL, DL, XType, 5952 DAG.getNode(ISD::AND, DL, XType, NegN0, NotN0), 5953 DAG.getConstant(XType.getSizeInBits()-1, 5954 getShiftAmountTy())); 5955 } 5956 // fold (setgt X, -1) -> (xor (srl (X, size(X)-1), 1)) 5957 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) { 5958 SDValue Sign = DAG.getNode(ISD::SRL, N0.getDebugLoc(), XType, N0, 5959 DAG.getConstant(XType.getSizeInBits()-1, 5960 getShiftAmountTy())); 5961 return DAG.getNode(ISD::XOR, DL, XType, Sign, DAG.getConstant(1, XType)); 5962 } 5963 } 5964 5965 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X -> 5966 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 5967 if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) && 5968 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1) && 5969 N2.getOperand(0) == N1 && N0.getValueType().isInteger()) { 5970 MVT XType = N0.getValueType(); 5971 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), XType, N0, 5972 DAG.getConstant(XType.getSizeInBits()-1, 5973 getShiftAmountTy())); 5974 SDValue Add = DAG.getNode(ISD::ADD, N0.getDebugLoc(), XType, 5975 N0, Shift); 5976 AddToWorkList(Shift.getNode()); 5977 AddToWorkList(Add.getNode()); 5978 return DAG.getNode(ISD::XOR, DL, XType, Add, Shift); 5979 } 5980 // Check to see if this is an integer abs. select_cc setgt X, -1, X, -X -> 5981 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 5982 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT && 5983 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1)) { 5984 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0))) { 5985 MVT XType = N0.getValueType(); 5986 if (SubC->isNullValue() && XType.isInteger()) { 5987 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), XType, 5988 N0, 5989 DAG.getConstant(XType.getSizeInBits()-1, 5990 getShiftAmountTy())); 5991 SDValue Add = DAG.getNode(ISD::ADD, N0.getDebugLoc(), 5992 XType, N0, Shift); 5993 AddToWorkList(Shift.getNode()); 5994 AddToWorkList(Add.getNode()); 5995 return DAG.getNode(ISD::XOR, DL, XType, Add, Shift); 5996 } 5997 } 5998 } 5999 6000 return SDValue(); 6001} 6002 6003/// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC. 6004SDValue DAGCombiner::SimplifySetCC(MVT VT, SDValue N0, 6005 SDValue N1, ISD::CondCode Cond, 6006 DebugLoc DL, bool foldBooleans) { 6007 TargetLowering::DAGCombinerInfo 6008 DagCombineInfo(DAG, !LegalTypes, !LegalOperations, false, this); 6009 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo, DL); 6010} 6011 6012/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 6013/// return a DAG expression to select that will generate the same value by 6014/// multiplying by a magic number. See: 6015/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 6016SDValue DAGCombiner::BuildSDIV(SDNode *N) { 6017 std::vector<SDNode*> Built; 6018 SDValue S = TLI.BuildSDIV(N, DAG, &Built); 6019 6020 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 6021 ii != ee; ++ii) 6022 AddToWorkList(*ii); 6023 return S; 6024} 6025 6026/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 6027/// return a DAG expression to select that will generate the same value by 6028/// multiplying by a magic number. See: 6029/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 6030SDValue DAGCombiner::BuildUDIV(SDNode *N) { 6031 std::vector<SDNode*> Built; 6032 SDValue S = TLI.BuildUDIV(N, DAG, &Built); 6033 6034 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 6035 ii != ee; ++ii) 6036 AddToWorkList(*ii); 6037 return S; 6038} 6039 6040/// FindBaseOffset - Return true if base is known not to alias with anything 6041/// but itself. Provides base object and offset as results. 6042static bool FindBaseOffset(SDValue Ptr, SDValue &Base, int64_t &Offset) { 6043 // Assume it is a primitive operation. 6044 Base = Ptr; Offset = 0; 6045 6046 // If it's an adding a simple constant then integrate the offset. 6047 if (Base.getOpcode() == ISD::ADD) { 6048 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) { 6049 Base = Base.getOperand(0); 6050 Offset += C->getZExtValue(); 6051 } 6052 } 6053 6054 // If it's any of the following then it can't alias with anything but itself. 6055 return isa<FrameIndexSDNode>(Base) || 6056 isa<ConstantPoolSDNode>(Base) || 6057 isa<GlobalAddressSDNode>(Base); 6058} 6059 6060/// isAlias - Return true if there is any possibility that the two addresses 6061/// overlap. 6062bool DAGCombiner::isAlias(SDValue Ptr1, int64_t Size1, 6063 const Value *SrcValue1, int SrcValueOffset1, 6064 SDValue Ptr2, int64_t Size2, 6065 const Value *SrcValue2, int SrcValueOffset2) const { 6066 // If they are the same then they must be aliases. 6067 if (Ptr1 == Ptr2) return true; 6068 6069 // Gather base node and offset information. 6070 SDValue Base1, Base2; 6071 int64_t Offset1, Offset2; 6072 bool KnownBase1 = FindBaseOffset(Ptr1, Base1, Offset1); 6073 bool KnownBase2 = FindBaseOffset(Ptr2, Base2, Offset2); 6074 6075 // If they have a same base address then... 6076 if (Base1 == Base2) 6077 // Check to see if the addresses overlap. 6078 return !((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1); 6079 6080 // If we know both bases then they can't alias. 6081 if (KnownBase1 && KnownBase2) return false; 6082 6083 if (CombinerGlobalAA) { 6084 // Use alias analysis information. 6085 int64_t MinOffset = std::min(SrcValueOffset1, SrcValueOffset2); 6086 int64_t Overlap1 = Size1 + SrcValueOffset1 - MinOffset; 6087 int64_t Overlap2 = Size2 + SrcValueOffset2 - MinOffset; 6088 AliasAnalysis::AliasResult AAResult = 6089 AA.alias(SrcValue1, Overlap1, SrcValue2, Overlap2); 6090 if (AAResult == AliasAnalysis::NoAlias) 6091 return false; 6092 } 6093 6094 // Otherwise we have to assume they alias. 6095 return true; 6096} 6097 6098/// FindAliasInfo - Extracts the relevant alias information from the memory 6099/// node. Returns true if the operand was a load. 6100bool DAGCombiner::FindAliasInfo(SDNode *N, 6101 SDValue &Ptr, int64_t &Size, 6102 const Value *&SrcValue, int &SrcValueOffset) const { 6103 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 6104 Ptr = LD->getBasePtr(); 6105 Size = LD->getMemoryVT().getSizeInBits() >> 3; 6106 SrcValue = LD->getSrcValue(); 6107 SrcValueOffset = LD->getSrcValueOffset(); 6108 return true; 6109 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 6110 Ptr = ST->getBasePtr(); 6111 Size = ST->getMemoryVT().getSizeInBits() >> 3; 6112 SrcValue = ST->getSrcValue(); 6113 SrcValueOffset = ST->getSrcValueOffset(); 6114 } else { 6115 llvm_unreachable("FindAliasInfo expected a memory operand"); 6116 } 6117 6118 return false; 6119} 6120 6121/// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 6122/// looking for aliasing nodes and adding them to the Aliases vector. 6123void DAGCombiner::GatherAllAliases(SDNode *N, SDValue OriginalChain, 6124 SmallVector<SDValue, 8> &Aliases) { 6125 SmallVector<SDValue, 8> Chains; // List of chains to visit. 6126 std::set<SDNode *> Visited; // Visited node set. 6127 6128 // Get alias information for node. 6129 SDValue Ptr; 6130 int64_t Size = 0; 6131 const Value *SrcValue = 0; 6132 int SrcValueOffset = 0; 6133 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset); 6134 6135 // Starting off. 6136 Chains.push_back(OriginalChain); 6137 6138 // Look at each chain and determine if it is an alias. If so, add it to the 6139 // aliases list. If not, then continue up the chain looking for the next 6140 // candidate. 6141 while (!Chains.empty()) { 6142 SDValue Chain = Chains.back(); 6143 Chains.pop_back(); 6144 6145 // Don't bother if we've been before. 6146 if (Visited.find(Chain.getNode()) != Visited.end()) continue; 6147 Visited.insert(Chain.getNode()); 6148 6149 switch (Chain.getOpcode()) { 6150 case ISD::EntryToken: 6151 // Entry token is ideal chain operand, but handled in FindBetterChain. 6152 break; 6153 6154 case ISD::LOAD: 6155 case ISD::STORE: { 6156 // Get alias information for Chain. 6157 SDValue OpPtr; 6158 int64_t OpSize = 0; 6159 const Value *OpSrcValue = 0; 6160 int OpSrcValueOffset = 0; 6161 bool IsOpLoad = FindAliasInfo(Chain.getNode(), OpPtr, OpSize, 6162 OpSrcValue, OpSrcValueOffset); 6163 6164 // If chain is alias then stop here. 6165 if (!(IsLoad && IsOpLoad) && 6166 isAlias(Ptr, Size, SrcValue, SrcValueOffset, 6167 OpPtr, OpSize, OpSrcValue, OpSrcValueOffset)) { 6168 Aliases.push_back(Chain); 6169 } else { 6170 // Look further up the chain. 6171 Chains.push_back(Chain.getOperand(0)); 6172 // Clean up old chain. 6173 AddToWorkList(Chain.getNode()); 6174 } 6175 break; 6176 } 6177 6178 case ISD::TokenFactor: 6179 // We have to check each of the operands of the token factor, so we queue 6180 // then up. Adding the operands to the queue (stack) in reverse order 6181 // maintains the original order and increases the likelihood that getNode 6182 // will find a matching token factor (CSE.) 6183 for (unsigned n = Chain.getNumOperands(); n;) 6184 Chains.push_back(Chain.getOperand(--n)); 6185 // Eliminate the token factor if we can. 6186 AddToWorkList(Chain.getNode()); 6187 break; 6188 6189 default: 6190 // For all other instructions we will just have to take what we can get. 6191 Aliases.push_back(Chain); 6192 break; 6193 } 6194 } 6195} 6196 6197/// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking 6198/// for a better chain (aliasing node.) 6199SDValue DAGCombiner::FindBetterChain(SDNode *N, SDValue OldChain) { 6200 SmallVector<SDValue, 8> Aliases; // Ops for replacing token factor. 6201 6202 // Accumulate all the aliases to this node. 6203 GatherAllAliases(N, OldChain, Aliases); 6204 6205 if (Aliases.size() == 0) { 6206 // If no operands then chain to entry token. 6207 return DAG.getEntryNode(); 6208 } else if (Aliases.size() == 1) { 6209 // If a single operand then chain to it. We don't need to revisit it. 6210 return Aliases[0]; 6211 } 6212 6213 // Construct a custom tailored token factor. 6214 SDValue NewChain = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, 6215 &Aliases[0], Aliases.size()); 6216 6217 // Make sure the old chain gets cleaned up. 6218 if (NewChain != OldChain) AddToWorkList(OldChain.getNode()); 6219 6220 return NewChain; 6221} 6222 6223// SelectionDAG::Combine - This is the entry point for the file. 6224// 6225void SelectionDAG::Combine(CombineLevel Level, AliasAnalysis &AA, 6226 CodeGenOpt::Level OptLevel) { 6227 /// run - This is the main entry point to this class. 6228 /// 6229 DAGCombiner(*this, AA, OptLevel).Run(Level); 6230} 6231