DAGCombiner.cpp revision 85d63bbff740d23fae631ec1ecf5c7603e4b321d
1//===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by Nate Begeman and is distributed under the 6// University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run 11// both before and after the DAG is legalized. 12// 13// FIXME: Missing folds 14// sdiv, udiv, srem, urem (X, const) where X is an integer can be expanded into 15// a sequence of multiplies, shifts, and adds. This should be controlled by 16// some kind of hint from the target that int div is expensive. 17// various folds of mulh[s,u] by constants such as -1, powers of 2, etc. 18// 19// FIXME: Should add a corresponding version of fold AND with 20// ZERO_EXTEND/SIGN_EXTEND by converting them to an ANY_EXTEND node which 21// we don't have yet. 22// 23// FIXME: select C, pow2, pow2 -> something smart 24// FIXME: trunc(select X, Y, Z) -> select X, trunc(Y), trunc(Z) 25// FIXME: (select C, load A, load B) -> load (select C, A, B) 26// FIXME: Dead stores -> nuke 27// FIXME: shr X, (and Y,31) -> shr X, Y 28// FIXME: TRUNC (LOAD) -> EXT_LOAD/LOAD(smaller) 29// FIXME: mul (x, const) -> shifts + adds 30// FIXME: undef values 31// FIXME: make truncate see through SIGN_EXTEND and AND 32// FIXME: (sra (sra x, c1), c2) -> (sra x, c1+c2) 33// FIXME: verify that getNode can't return extends with an operand whose type 34// is >= to that of the extend. 35// FIXME: divide by zero is currently left unfolded. do we want to turn this 36// into an undef? 37// FIXME: select ne (select cc, 1, 0), 0, true, false -> select cc, true, false 38// FIXME: reassociate (X+C)+Y into (X+Y)+C if the inner expression has one use 39// 40//===----------------------------------------------------------------------===// 41 42#define DEBUG_TYPE "dagcombine" 43#include "llvm/ADT/Statistic.h" 44#include "llvm/CodeGen/SelectionDAG.h" 45#include "llvm/Support/Debug.h" 46#include "llvm/Support/MathExtras.h" 47#include "llvm/Target/TargetLowering.h" 48#include <algorithm> 49#include <cmath> 50using namespace llvm; 51 52namespace { 53 Statistic<> NodesCombined ("dagcombiner", "Number of dag nodes combined"); 54 55 class DAGCombiner { 56 SelectionDAG &DAG; 57 TargetLowering &TLI; 58 bool AfterLegalize; 59 60 // Worklist of all of the nodes that need to be simplified. 61 std::vector<SDNode*> WorkList; 62 63 /// AddUsersToWorkList - When an instruction is simplified, add all users of 64 /// the instruction to the work lists because they might get more simplified 65 /// now. 66 /// 67 void AddUsersToWorkList(SDNode *N) { 68 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 69 UI != UE; ++UI) 70 WorkList.push_back(*UI); 71 } 72 73 /// removeFromWorkList - remove all instances of N from the worklist. 74 void removeFromWorkList(SDNode *N) { 75 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N), 76 WorkList.end()); 77 } 78 79 SDOperand CombineTo(SDNode *N, const std::vector<SDOperand> &To) { 80 ++NodesCombined; 81 DEBUG(std::cerr << "\nReplacing "; N->dump(); 82 std::cerr << "\nWith: "; To[0].Val->dump(); 83 std::cerr << " and " << To.size()-1 << " other values\n"); 84 std::vector<SDNode*> NowDead; 85 DAG.ReplaceAllUsesWith(N, To, &NowDead); 86 87 // Push the new nodes and any users onto the worklist 88 for (unsigned i = 0, e = To.size(); i != e; ++i) { 89 WorkList.push_back(To[i].Val); 90 AddUsersToWorkList(To[i].Val); 91 } 92 93 // Nodes can end up on the worklist more than once. Make sure we do 94 // not process a node that has been replaced. 95 removeFromWorkList(N); 96 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 97 removeFromWorkList(NowDead[i]); 98 99 // Finally, since the node is now dead, remove it from the graph. 100 DAG.DeleteNode(N); 101 return SDOperand(N, 0); 102 } 103 104 SDOperand CombineTo(SDNode *N, SDOperand Res) { 105 std::vector<SDOperand> To; 106 To.push_back(Res); 107 return CombineTo(N, To); 108 } 109 110 SDOperand CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1) { 111 std::vector<SDOperand> To; 112 To.push_back(Res0); 113 To.push_back(Res1); 114 return CombineTo(N, To); 115 } 116 117 /// visit - call the node-specific routine that knows how to fold each 118 /// particular type of node. 119 SDOperand visit(SDNode *N); 120 121 // Visitation implementation - Implement dag node combining for different 122 // node types. The semantics are as follows: 123 // Return Value: 124 // SDOperand.Val == 0 - No change was made 125 // SDOperand.Val == N - N was replaced, is dead, and is already handled. 126 // otherwise - N should be replaced by the returned Operand. 127 // 128 SDOperand visitTokenFactor(SDNode *N); 129 SDOperand visitADD(SDNode *N); 130 SDOperand visitSUB(SDNode *N); 131 SDOperand visitMUL(SDNode *N); 132 SDOperand visitSDIV(SDNode *N); 133 SDOperand visitUDIV(SDNode *N); 134 SDOperand visitSREM(SDNode *N); 135 SDOperand visitUREM(SDNode *N); 136 SDOperand visitMULHU(SDNode *N); 137 SDOperand visitMULHS(SDNode *N); 138 SDOperand visitAND(SDNode *N); 139 SDOperand visitOR(SDNode *N); 140 SDOperand visitXOR(SDNode *N); 141 SDOperand visitSHL(SDNode *N); 142 SDOperand visitSRA(SDNode *N); 143 SDOperand visitSRL(SDNode *N); 144 SDOperand visitCTLZ(SDNode *N); 145 SDOperand visitCTTZ(SDNode *N); 146 SDOperand visitCTPOP(SDNode *N); 147 SDOperand visitSELECT(SDNode *N); 148 SDOperand visitSELECT_CC(SDNode *N); 149 SDOperand visitSETCC(SDNode *N); 150 SDOperand visitADD_PARTS(SDNode *N); 151 SDOperand visitSUB_PARTS(SDNode *N); 152 SDOperand visitSIGN_EXTEND(SDNode *N); 153 SDOperand visitZERO_EXTEND(SDNode *N); 154 SDOperand visitSIGN_EXTEND_INREG(SDNode *N); 155 SDOperand visitTRUNCATE(SDNode *N); 156 157 SDOperand visitFADD(SDNode *N); 158 SDOperand visitFSUB(SDNode *N); 159 SDOperand visitFMUL(SDNode *N); 160 SDOperand visitFDIV(SDNode *N); 161 SDOperand visitFREM(SDNode *N); 162 SDOperand visitSINT_TO_FP(SDNode *N); 163 SDOperand visitUINT_TO_FP(SDNode *N); 164 SDOperand visitFP_TO_SINT(SDNode *N); 165 SDOperand visitFP_TO_UINT(SDNode *N); 166 SDOperand visitFP_ROUND(SDNode *N); 167 SDOperand visitFP_ROUND_INREG(SDNode *N); 168 SDOperand visitFP_EXTEND(SDNode *N); 169 SDOperand visitFNEG(SDNode *N); 170 SDOperand visitFABS(SDNode *N); 171 SDOperand visitBRCOND(SDNode *N); 172 SDOperand visitBRCONDTWOWAY(SDNode *N); 173 SDOperand visitBR_CC(SDNode *N); 174 SDOperand visitBRTWOWAY_CC(SDNode *N); 175 176 SDOperand visitLOAD(SDNode *N); 177 SDOperand visitSTORE(SDNode *N); 178 179 SDOperand SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2); 180 SDOperand SimplifySelectCC(SDOperand N0, SDOperand N1, SDOperand N2, 181 SDOperand N3, ISD::CondCode CC); 182 SDOperand SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1, 183 ISD::CondCode Cond, bool foldBooleans = true); 184public: 185 DAGCombiner(SelectionDAG &D) 186 : DAG(D), TLI(D.getTargetLoweringInfo()), AfterLegalize(false) {} 187 188 /// Run - runs the dag combiner on all nodes in the work list 189 void Run(bool RunningAfterLegalize); 190 }; 191} 192 193/// MaskedValueIsZero - Return true if 'Op & Mask' is known to be zero. We use 194/// this predicate to simplify operations downstream. Op and Mask are known to 195/// be the same type. 196static bool MaskedValueIsZero(const SDOperand &Op, uint64_t Mask, 197 const TargetLowering &TLI) { 198 unsigned SrcBits; 199 if (Mask == 0) return true; 200 201 // If we know the result of a setcc has the top bits zero, use this info. 202 switch (Op.getOpcode()) { 203 case ISD::Constant: 204 return (cast<ConstantSDNode>(Op)->getValue() & Mask) == 0; 205 case ISD::SETCC: 206 return ((Mask & 1) == 0) && 207 TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult; 208 case ISD::ZEXTLOAD: 209 SrcBits = MVT::getSizeInBits(cast<VTSDNode>(Op.getOperand(3))->getVT()); 210 return (Mask & ((1ULL << SrcBits)-1)) == 0; // Returning only the zext bits. 211 case ISD::ZERO_EXTEND: 212 SrcBits = MVT::getSizeInBits(Op.getOperand(0).getValueType()); 213 return MaskedValueIsZero(Op.getOperand(0),Mask & ((1ULL << SrcBits)-1),TLI); 214 case ISD::AssertZext: 215 SrcBits = MVT::getSizeInBits(cast<VTSDNode>(Op.getOperand(1))->getVT()); 216 return (Mask & ((1ULL << SrcBits)-1)) == 0; // Returning only the zext bits. 217 case ISD::AND: 218 // If either of the operands has zero bits, the result will too. 219 if (MaskedValueIsZero(Op.getOperand(1), Mask, TLI) || 220 MaskedValueIsZero(Op.getOperand(0), Mask, TLI)) 221 return true; 222 // (X & C1) & C2 == 0 iff C1 & C2 == 0. 223 if (ConstantSDNode *AndRHS = dyn_cast<ConstantSDNode>(Op.getOperand(1))) 224 return MaskedValueIsZero(Op.getOperand(0),AndRHS->getValue() & Mask, TLI); 225 return false; 226 case ISD::OR: 227 case ISD::XOR: 228 return MaskedValueIsZero(Op.getOperand(0), Mask, TLI) && 229 MaskedValueIsZero(Op.getOperand(1), Mask, TLI); 230 case ISD::SELECT: 231 return MaskedValueIsZero(Op.getOperand(1), Mask, TLI) && 232 MaskedValueIsZero(Op.getOperand(2), Mask, TLI); 233 case ISD::SELECT_CC: 234 return MaskedValueIsZero(Op.getOperand(2), Mask, TLI) && 235 MaskedValueIsZero(Op.getOperand(3), Mask, TLI); 236 case ISD::SRL: 237 // (ushr X, C1) & C2 == 0 iff X & (C2 << C1) == 0 238 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 239 uint64_t NewVal = Mask << ShAmt->getValue(); 240 SrcBits = MVT::getSizeInBits(Op.getValueType()); 241 if (SrcBits != 64) NewVal &= (1ULL << SrcBits)-1; 242 return MaskedValueIsZero(Op.getOperand(0), NewVal, TLI); 243 } 244 return false; 245 case ISD::SHL: 246 // (ushl X, C1) & C2 == 0 iff X & (C2 >> C1) == 0 247 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 248 uint64_t NewVal = Mask >> ShAmt->getValue(); 249 return MaskedValueIsZero(Op.getOperand(0), NewVal, TLI); 250 } 251 return false; 252 case ISD::ADD: 253 // (add X, Y) & C == 0 iff (X&C)|(Y&C) == 0 and all bits are low bits. 254 if ((Mask&(Mask+1)) == 0) { // All low bits 255 if (MaskedValueIsZero(Op.getOperand(0), Mask, TLI) && 256 MaskedValueIsZero(Op.getOperand(1), Mask, TLI)) 257 return true; 258 } 259 break; 260 case ISD::SUB: 261 if (ConstantSDNode *CLHS = dyn_cast<ConstantSDNode>(Op.getOperand(0))) { 262 // We know that the top bits of C-X are clear if X contains less bits 263 // than C (i.e. no wrap-around can happen). For example, 20-X is 264 // positive if we can prove that X is >= 0 and < 16. 265 unsigned Bits = MVT::getSizeInBits(CLHS->getValueType(0)); 266 if ((CLHS->getValue() & (1 << (Bits-1))) == 0) { // sign bit clear 267 unsigned NLZ = CountLeadingZeros_64(CLHS->getValue()+1); 268 uint64_t MaskV = (1ULL << (63-NLZ))-1; 269 if (MaskedValueIsZero(Op.getOperand(1), ~MaskV, TLI)) { 270 // High bits are clear this value is known to be >= C. 271 unsigned NLZ2 = CountLeadingZeros_64(CLHS->getValue()); 272 if ((Mask & ((1ULL << (64-NLZ2))-1)) == 0) 273 return true; 274 } 275 } 276 } 277 break; 278 case ISD::CTTZ: 279 case ISD::CTLZ: 280 case ISD::CTPOP: 281 // Bit counting instructions can not set the high bits of the result 282 // register. The max number of bits sets depends on the input. 283 return (Mask & (MVT::getSizeInBits(Op.getValueType())*2-1)) == 0; 284 default: break; 285 } 286 return false; 287} 288 289// isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc 290// that selects between the values 1 and 0, making it equivalent to a setcc. 291// Also, set the incoming LHS, RHS, and CC references to the appropriate 292// nodes based on the type of node we are checking. This simplifies life a 293// bit for the callers. 294static bool isSetCCEquivalent(SDOperand N, SDOperand &LHS, SDOperand &RHS, 295 SDOperand &CC) { 296 if (N.getOpcode() == ISD::SETCC) { 297 LHS = N.getOperand(0); 298 RHS = N.getOperand(1); 299 CC = N.getOperand(2); 300 return true; 301 } 302 if (N.getOpcode() == ISD::SELECT_CC && 303 N.getOperand(2).getOpcode() == ISD::Constant && 304 N.getOperand(3).getOpcode() == ISD::Constant && 305 cast<ConstantSDNode>(N.getOperand(2))->getValue() == 1 && 306 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) { 307 LHS = N.getOperand(0); 308 RHS = N.getOperand(1); 309 CC = N.getOperand(4); 310 return true; 311 } 312 return false; 313} 314 315// isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only 316// one use. If this is true, it allows the users to invert the operation for 317// free when it is profitable to do so. 318static bool isOneUseSetCC(SDOperand N) { 319 SDOperand N0, N1, N2; 320 if (isSetCCEquivalent(N, N0, N1, N2) && N.Val->hasOneUse()) 321 return true; 322 return false; 323} 324 325// FIXME: This should probably go in the ISD class rather than being duplicated 326// in several files. 327static bool isCommutativeBinOp(unsigned Opcode) { 328 switch (Opcode) { 329 case ISD::ADD: 330 case ISD::MUL: 331 case ISD::AND: 332 case ISD::OR: 333 case ISD::XOR: return true; 334 default: return false; // FIXME: Need commutative info for user ops! 335 } 336} 337 338void DAGCombiner::Run(bool RunningAfterLegalize) { 339 // set the instance variable, so that the various visit routines may use it. 340 AfterLegalize = RunningAfterLegalize; 341 342 // Add all the dag nodes to the worklist. 343 WorkList.insert(WorkList.end(), DAG.allnodes_begin(), DAG.allnodes_end()); 344 345 // Create a dummy node (which is not added to allnodes), that adds a reference 346 // to the root node, preventing it from being deleted, and tracking any 347 // changes of the root. 348 HandleSDNode Dummy(DAG.getRoot()); 349 350 // while the worklist isn't empty, inspect the node on the end of it and 351 // try and combine it. 352 while (!WorkList.empty()) { 353 SDNode *N = WorkList.back(); 354 WorkList.pop_back(); 355 356 // If N has no uses, it is dead. Make sure to revisit all N's operands once 357 // N is deleted from the DAG, since they too may now be dead or may have a 358 // reduced number of uses, allowing other xforms. 359 if (N->use_empty() && N != &Dummy) { 360 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 361 WorkList.push_back(N->getOperand(i).Val); 362 363 removeFromWorkList(N); 364 DAG.DeleteNode(N); 365 continue; 366 } 367 368 SDOperand RV = visit(N); 369 if (RV.Val) { 370 ++NodesCombined; 371 // If we get back the same node we passed in, rather than a new node or 372 // zero, we know that the node must have defined multiple values and 373 // CombineTo was used. Since CombineTo takes care of the worklist 374 // mechanics for us, we have no work to do in this case. 375 if (RV.Val != N) { 376 DEBUG(std::cerr << "\nReplacing "; N->dump(); 377 std::cerr << "\nWith: "; RV.Val->dump(); 378 std::cerr << '\n'); 379 std::vector<SDNode*> NowDead; 380 DAG.ReplaceAllUsesWith(N, std::vector<SDOperand>(1, RV), &NowDead); 381 382 // Push the new node and any users onto the worklist 383 WorkList.push_back(RV.Val); 384 AddUsersToWorkList(RV.Val); 385 386 // Nodes can end up on the worklist more than once. Make sure we do 387 // not process a node that has been replaced. 388 removeFromWorkList(N); 389 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 390 removeFromWorkList(NowDead[i]); 391 392 // Finally, since the node is now dead, remove it from the graph. 393 DAG.DeleteNode(N); 394 } 395 } 396 } 397 398 // If the root changed (e.g. it was a dead load, update the root). 399 DAG.setRoot(Dummy.getValue()); 400} 401 402SDOperand DAGCombiner::visit(SDNode *N) { 403 switch(N->getOpcode()) { 404 default: break; 405 case ISD::TokenFactor: return visitTokenFactor(N); 406 case ISD::ADD: return visitADD(N); 407 case ISD::SUB: return visitSUB(N); 408 case ISD::MUL: return visitMUL(N); 409 case ISD::SDIV: return visitSDIV(N); 410 case ISD::UDIV: return visitUDIV(N); 411 case ISD::SREM: return visitSREM(N); 412 case ISD::UREM: return visitUREM(N); 413 case ISD::MULHU: return visitMULHU(N); 414 case ISD::MULHS: return visitMULHS(N); 415 case ISD::AND: return visitAND(N); 416 case ISD::OR: return visitOR(N); 417 case ISD::XOR: return visitXOR(N); 418 case ISD::SHL: return visitSHL(N); 419 case ISD::SRA: return visitSRA(N); 420 case ISD::SRL: return visitSRL(N); 421 case ISD::CTLZ: return visitCTLZ(N); 422 case ISD::CTTZ: return visitCTTZ(N); 423 case ISD::CTPOP: return visitCTPOP(N); 424 case ISD::SELECT: return visitSELECT(N); 425 case ISD::SELECT_CC: return visitSELECT_CC(N); 426 case ISD::SETCC: return visitSETCC(N); 427 case ISD::ADD_PARTS: return visitADD_PARTS(N); 428 case ISD::SUB_PARTS: return visitSUB_PARTS(N); 429 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N); 430 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N); 431 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N); 432 case ISD::TRUNCATE: return visitTRUNCATE(N); 433 case ISD::FADD: return visitFADD(N); 434 case ISD::FSUB: return visitFSUB(N); 435 case ISD::FMUL: return visitFMUL(N); 436 case ISD::FDIV: return visitFDIV(N); 437 case ISD::FREM: return visitFREM(N); 438 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N); 439 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N); 440 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N); 441 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N); 442 case ISD::FP_ROUND: return visitFP_ROUND(N); 443 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N); 444 case ISD::FP_EXTEND: return visitFP_EXTEND(N); 445 case ISD::FNEG: return visitFNEG(N); 446 case ISD::FABS: return visitFABS(N); 447 case ISD::BRCOND: return visitBRCOND(N); 448 case ISD::BRCONDTWOWAY: return visitBRCONDTWOWAY(N); 449 case ISD::BR_CC: return visitBR_CC(N); 450 case ISD::BRTWOWAY_CC: return visitBRTWOWAY_CC(N); 451 case ISD::LOAD: return visitLOAD(N); 452 case ISD::STORE: return visitSTORE(N); 453 } 454 return SDOperand(); 455} 456 457SDOperand DAGCombiner::visitTokenFactor(SDNode *N) { 458 std::vector<SDOperand> Ops; 459 bool Changed = false; 460 461 // If the token factor has two operands and one is the entry token, replace 462 // the token factor with the other operand. 463 if (N->getNumOperands() == 2) { 464 if (N->getOperand(0).getOpcode() == ISD::EntryToken) 465 return N->getOperand(1); 466 if (N->getOperand(1).getOpcode() == ISD::EntryToken) 467 return N->getOperand(0); 468 } 469 470 // fold (tokenfactor (tokenfactor)) -> tokenfactor 471 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { 472 SDOperand Op = N->getOperand(i); 473 if (Op.getOpcode() == ISD::TokenFactor && Op.hasOneUse()) { 474 Changed = true; 475 for (unsigned j = 0, e = Op.getNumOperands(); j != e; ++j) 476 Ops.push_back(Op.getOperand(j)); 477 } else { 478 Ops.push_back(Op); 479 } 480 } 481 if (Changed) 482 return DAG.getNode(ISD::TokenFactor, MVT::Other, Ops); 483 return SDOperand(); 484} 485 486SDOperand DAGCombiner::visitADD(SDNode *N) { 487 SDOperand N0 = N->getOperand(0); 488 SDOperand N1 = N->getOperand(1); 489 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 490 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 491 MVT::ValueType VT = N0.getValueType(); 492 493 // fold (add c1, c2) -> c1+c2 494 if (N0C && N1C) 495 return DAG.getConstant(N0C->getValue() + N1C->getValue(), VT); 496 // canonicalize constant to RHS 497 if (N0C && !N1C) { 498 std::swap(N0, N1); 499 std::swap(N0C, N1C); 500 } 501 // fold (add x, 0) -> x 502 if (N1C && N1C->isNullValue()) 503 return N0; 504 // fold (add (add x, c1), c2) -> (add x, c1+c2) 505 if (N1C && N0.getOpcode() == ISD::ADD) { 506 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0)); 507 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 508 if (N00C) 509 return DAG.getNode(ISD::ADD, VT, N0.getOperand(1), 510 DAG.getConstant(N1C->getValue()+N00C->getValue(), VT)); 511 if (N01C) 512 return DAG.getNode(ISD::ADD, VT, N0.getOperand(0), 513 DAG.getConstant(N1C->getValue()+N01C->getValue(), VT)); 514 } 515 // fold ((0-A) + B) -> B-A 516 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) && 517 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue()) 518 return DAG.getNode(ISD::SUB, VT, N1, N0.getOperand(1)); 519 // fold (A + (0-B)) -> A-B 520 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) && 521 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue()) 522 return DAG.getNode(ISD::SUB, VT, N0, N1.getOperand(1)); 523 // fold (A+(B-A)) -> B 524 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1)) 525 return N1.getOperand(0); 526 return SDOperand(); 527} 528 529SDOperand DAGCombiner::visitSUB(SDNode *N) { 530 SDOperand N0 = N->getOperand(0); 531 SDOperand N1 = N->getOperand(1); 532 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 533 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 534 535 // fold (sub c1, c2) -> c1-c2 536 if (N0C && N1C) 537 return DAG.getConstant(N0C->getValue() - N1C->getValue(), 538 N->getValueType(0)); 539 // fold (sub x, c) -> (add x, -c) 540 if (N1C) 541 return DAG.getNode(ISD::ADD, N0.getValueType(), N0, 542 DAG.getConstant(-N1C->getValue(), N0.getValueType())); 543 544 // fold (A+B)-A -> B 545 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1) 546 return N0.getOperand(1); 547 // fold (A+B)-B -> A 548 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1) 549 return N0.getOperand(0); 550 return SDOperand(); 551} 552 553SDOperand DAGCombiner::visitMUL(SDNode *N) { 554 SDOperand N0 = N->getOperand(0); 555 SDOperand N1 = N->getOperand(1); 556 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 557 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 558 MVT::ValueType VT = N0.getValueType(); 559 560 // fold (mul c1, c2) -> c1*c2 561 if (N0C && N1C) 562 return DAG.getConstant(N0C->getValue() * N1C->getValue(), 563 N->getValueType(0)); 564 // canonicalize constant to RHS 565 if (N0C && !N1C) { 566 std::swap(N0, N1); 567 std::swap(N0C, N1C); 568 } 569 // fold (mul x, 0) -> 0 570 if (N1C && N1C->isNullValue()) 571 return N1; 572 // fold (mul x, -1) -> 0-x 573 if (N1C && N1C->isAllOnesValue()) 574 return DAG.getNode(ISD::SUB, N->getValueType(0), 575 DAG.getConstant(0, N->getValueType(0)), N0); 576 // fold (mul x, (1 << c)) -> x << c 577 if (N1C && isPowerOf2_64(N1C->getValue())) 578 return DAG.getNode(ISD::SHL, N->getValueType(0), N0, 579 DAG.getConstant(Log2_64(N1C->getValue()), 580 TLI.getShiftAmountTy())); 581 // fold (mul (mul x, c1), c2) -> (mul x, c1*c2) 582 if (N1C && N0.getOpcode() == ISD::MUL) { 583 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0)); 584 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 585 if (N00C) 586 return DAG.getNode(ISD::MUL, VT, N0.getOperand(1), 587 DAG.getConstant(N1C->getValue()*N00C->getValue(), VT)); 588 if (N01C) 589 return DAG.getNode(ISD::MUL, VT, N0.getOperand(0), 590 DAG.getConstant(N1C->getValue()*N01C->getValue(), VT)); 591 } 592 return SDOperand(); 593} 594 595SDOperand DAGCombiner::visitSDIV(SDNode *N) { 596 SDOperand N0 = N->getOperand(0); 597 SDOperand N1 = N->getOperand(1); 598 MVT::ValueType VT = N->getValueType(0); 599 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 600 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 601 602 // fold (sdiv c1, c2) -> c1/c2 603 if (N0C && N1C && !N1C->isNullValue()) 604 return DAG.getConstant(N0C->getSignExtended() / N1C->getSignExtended(), 605 N->getValueType(0)); 606 // If we know the sign bits of both operands are zero, strength reduce to a 607 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2 608 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1); 609 if (MaskedValueIsZero(N1, SignBit, TLI) && 610 MaskedValueIsZero(N0, SignBit, TLI)) 611 return DAG.getNode(ISD::UDIV, N1.getValueType(), N0, N1); 612 return SDOperand(); 613} 614 615SDOperand DAGCombiner::visitUDIV(SDNode *N) { 616 SDOperand N0 = N->getOperand(0); 617 SDOperand N1 = N->getOperand(1); 618 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 619 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 620 621 // fold (udiv c1, c2) -> c1/c2 622 if (N0C && N1C && !N1C->isNullValue()) 623 return DAG.getConstant(N0C->getValue() / N1C->getValue(), 624 N->getValueType(0)); 625 // fold (udiv x, (1 << c)) -> x >>u c 626 if (N1C && isPowerOf2_64(N1C->getValue())) 627 return DAG.getNode(ISD::SRL, N->getValueType(0), N0, 628 DAG.getConstant(Log2_64(N1C->getValue()), 629 TLI.getShiftAmountTy())); 630 return SDOperand(); 631} 632 633SDOperand DAGCombiner::visitSREM(SDNode *N) { 634 SDOperand N0 = N->getOperand(0); 635 SDOperand N1 = N->getOperand(1); 636 MVT::ValueType VT = N->getValueType(0); 637 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 638 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 639 640 // fold (srem c1, c2) -> c1%c2 641 if (N0C && N1C && !N1C->isNullValue()) 642 return DAG.getConstant(N0C->getSignExtended() % N1C->getSignExtended(), 643 N->getValueType(0)); 644 // If we know the sign bits of both operands are zero, strength reduce to a 645 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15 646 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1); 647 if (MaskedValueIsZero(N1, SignBit, TLI) && 648 MaskedValueIsZero(N0, SignBit, TLI)) 649 return DAG.getNode(ISD::UREM, N1.getValueType(), N0, N1); 650 return SDOperand(); 651} 652 653SDOperand DAGCombiner::visitUREM(SDNode *N) { 654 SDOperand N0 = N->getOperand(0); 655 SDOperand N1 = N->getOperand(1); 656 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 657 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 658 659 // fold (urem c1, c2) -> c1%c2 660 if (N0C && N1C && !N1C->isNullValue()) 661 return DAG.getConstant(N0C->getValue() % N1C->getValue(), 662 N->getValueType(0)); 663 // fold (urem x, pow2) -> (and x, pow2-1) 664 if (N1C && !N1C->isNullValue() && isPowerOf2_64(N1C->getValue())) 665 return DAG.getNode(ISD::AND, N0.getValueType(), N0, 666 DAG.getConstant(N1C->getValue()-1, N1.getValueType())); 667 return SDOperand(); 668} 669 670SDOperand DAGCombiner::visitMULHS(SDNode *N) { 671 SDOperand N0 = N->getOperand(0); 672 SDOperand N1 = N->getOperand(1); 673 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 674 675 // fold (mulhs x, 0) -> 0 676 if (N1C && N1C->isNullValue()) 677 return N1; 678 // fold (mulhs x, 1) -> (sra x, size(x)-1) 679 if (N1C && N1C->getValue() == 1) 680 return DAG.getNode(ISD::SRA, N0.getValueType(), N0, 681 DAG.getConstant(MVT::getSizeInBits(N0.getValueType())-1, 682 TLI.getShiftAmountTy())); 683 return SDOperand(); 684} 685 686SDOperand DAGCombiner::visitMULHU(SDNode *N) { 687 SDOperand N0 = N->getOperand(0); 688 SDOperand N1 = N->getOperand(1); 689 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 690 691 // fold (mulhu x, 0) -> 0 692 if (N1C && N1C->isNullValue()) 693 return N1; 694 // fold (mulhu x, 1) -> 0 695 if (N1C && N1C->getValue() == 1) 696 return DAG.getConstant(0, N0.getValueType()); 697 return SDOperand(); 698} 699 700SDOperand DAGCombiner::visitAND(SDNode *N) { 701 SDOperand N0 = N->getOperand(0); 702 SDOperand N1 = N->getOperand(1); 703 SDOperand LL, LR, RL, RR, CC0, CC1; 704 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 705 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 706 MVT::ValueType VT = N1.getValueType(); 707 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 708 709 // fold (and c1, c2) -> c1&c2 710 if (N0C && N1C) 711 return DAG.getConstant(N0C->getValue() & N1C->getValue(), VT); 712 // canonicalize constant to RHS 713 if (N0C && !N1C) { 714 std::swap(N0, N1); 715 std::swap(N0C, N1C); 716 } 717 // fold (and x, -1) -> x 718 if (N1C && N1C->isAllOnesValue()) 719 return N0; 720 // if (and x, c) is known to be zero, return 0 721 if (N1C && MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits),TLI)) 722 return DAG.getConstant(0, VT); 723 // fold (and x, c) -> x iff (x & ~c) == 0 724 if (N1C && MaskedValueIsZero(N0,~N1C->getValue() & (~0ULL>>(64-OpSizeInBits)), 725 TLI)) 726 return N0; 727 // fold (and (and x, c1), c2) -> (and x, c1^c2) 728 if (N1C && N0.getOpcode() == ISD::AND) { 729 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0)); 730 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 731 if (N00C) 732 return DAG.getNode(ISD::AND, VT, N0.getOperand(1), 733 DAG.getConstant(N1C->getValue()&N00C->getValue(), VT)); 734 if (N01C) 735 return DAG.getNode(ISD::AND, VT, N0.getOperand(0), 736 DAG.getConstant(N1C->getValue()&N01C->getValue(), VT)); 737 } 738 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1) 739 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG) { 740 unsigned ExtendBits = 741 MVT::getSizeInBits(cast<VTSDNode>(N0.getOperand(1))->getVT()); 742 if ((N1C->getValue() & (~0ULL << ExtendBits)) == 0) 743 return DAG.getNode(ISD::AND, VT, N0.getOperand(0), N1); 744 } 745 // fold (and (or x, 0xFFFF), 0xFF) -> 0xFF 746 if (N0.getOpcode() == ISD::OR && N1C) 747 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 748 if ((ORI->getValue() & N1C->getValue()) == N1C->getValue()) 749 return N1; 750 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y)) 751 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 752 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 753 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 754 755 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 756 MVT::isInteger(LL.getValueType())) { 757 // fold (X == 0) & (Y == 0) -> (X|Y == 0) 758 if (cast<ConstantSDNode>(LR)->getValue() == 0 && Op1 == ISD::SETEQ) { 759 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 760 WorkList.push_back(ORNode.Val); 761 return DAG.getSetCC(VT, ORNode, LR, Op1); 762 } 763 // fold (X == -1) & (Y == -1) -> (X&Y == -1) 764 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) { 765 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL); 766 WorkList.push_back(ANDNode.Val); 767 return DAG.getSetCC(VT, ANDNode, LR, Op1); 768 } 769 // fold (X > -1) & (Y > -1) -> (X|Y > -1) 770 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) { 771 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 772 WorkList.push_back(ORNode.Val); 773 return DAG.getSetCC(VT, ORNode, LR, Op1); 774 } 775 } 776 // canonicalize equivalent to ll == rl 777 if (LL == RR && LR == RL) { 778 Op1 = ISD::getSetCCSwappedOperands(Op1); 779 std::swap(RL, RR); 780 } 781 if (LL == RL && LR == RR) { 782 bool isInteger = MVT::isInteger(LL.getValueType()); 783 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger); 784 if (Result != ISD::SETCC_INVALID) 785 return DAG.getSetCC(N0.getValueType(), LL, LR, Result); 786 } 787 } 788 // fold (and (zext x), (zext y)) -> (zext (and x, y)) 789 if (N0.getOpcode() == ISD::ZERO_EXTEND && 790 N1.getOpcode() == ISD::ZERO_EXTEND && 791 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) { 792 SDOperand ANDNode = DAG.getNode(ISD::AND, N0.getOperand(0).getValueType(), 793 N0.getOperand(0), N1.getOperand(0)); 794 WorkList.push_back(ANDNode.Val); 795 return DAG.getNode(ISD::ZERO_EXTEND, VT, ANDNode); 796 } 797 // fold (and (shl/srl x), (shl/srl y)) -> (shl/srl (and x, y)) 798 if (((N0.getOpcode() == ISD::SHL && N1.getOpcode() == ISD::SHL) || 799 (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SRL)) && 800 N0.getOperand(1) == N1.getOperand(1)) { 801 SDOperand ANDNode = DAG.getNode(ISD::AND, N0.getOperand(0).getValueType(), 802 N0.getOperand(0), N1.getOperand(0)); 803 WorkList.push_back(ANDNode.Val); 804 return DAG.getNode(N0.getOpcode(), VT, ANDNode, N0.getOperand(1)); 805 } 806 // fold (and (sra)) -> (and (srl)) when possible. 807 if (N0.getOpcode() == ISD::SRA && N0.Val->hasOneUse()) 808 if (ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 809 // If the RHS of the AND has zeros where the sign bits of the SRA will 810 // land, turn the SRA into an SRL. 811 if (MaskedValueIsZero(N1, (~0ULL << N01C->getValue()) & 812 (~0ULL>>(64-OpSizeInBits)), TLI)) { 813 WorkList.push_back(N); 814 CombineTo(N0.Val, DAG.getNode(ISD::SRL, VT, N0.getOperand(0), 815 N0.getOperand(1))); 816 return SDOperand(); 817 } 818 } 819 820 // fold (zext_inreg (extload x)) -> (zextload x) 821 if (N0.getOpcode() == ISD::EXTLOAD) { 822 MVT::ValueType EVT = cast<VTSDNode>(N0.getOperand(3))->getVT(); 823 // If we zero all the possible extended bits, then we can turn this into 824 // a zextload if we are running before legalize or the operation is legal. 825 if (MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT), TLI) && 826 (!AfterLegalize || TLI.isOperationLegal(ISD::ZEXTLOAD, EVT))) { 827 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0), 828 N0.getOperand(1), N0.getOperand(2), 829 EVT); 830 WorkList.push_back(N); 831 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 832 return SDOperand(); 833 } 834 } 835 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use 836 if (N0.getOpcode() == ISD::SEXTLOAD && N0.Val->hasNUsesOfValue(1, 0)) { 837 MVT::ValueType EVT = cast<VTSDNode>(N0.getOperand(3))->getVT(); 838 // If we zero all the possible extended bits, then we can turn this into 839 // a zextload if we are running before legalize or the operation is legal. 840 if (MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT), TLI) && 841 (!AfterLegalize || TLI.isOperationLegal(ISD::ZEXTLOAD, EVT))) { 842 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0), 843 N0.getOperand(1), N0.getOperand(2), 844 EVT); 845 WorkList.push_back(N); 846 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 847 return SDOperand(); 848 } 849 } 850 return SDOperand(); 851} 852 853SDOperand DAGCombiner::visitOR(SDNode *N) { 854 SDOperand N0 = N->getOperand(0); 855 SDOperand N1 = N->getOperand(1); 856 SDOperand LL, LR, RL, RR, CC0, CC1; 857 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 858 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 859 MVT::ValueType VT = N1.getValueType(); 860 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 861 862 // fold (or c1, c2) -> c1|c2 863 if (N0C && N1C) 864 return DAG.getConstant(N0C->getValue() | N1C->getValue(), 865 N->getValueType(0)); 866 // canonicalize constant to RHS 867 if (N0C && !N1C) { 868 std::swap(N0, N1); 869 std::swap(N0C, N1C); 870 } 871 // fold (or x, 0) -> x 872 if (N1C && N1C->isNullValue()) 873 return N0; 874 // fold (or x, -1) -> -1 875 if (N1C && N1C->isAllOnesValue()) 876 return N1; 877 // fold (or x, c) -> c iff (x & ~c) == 0 878 if (N1C && MaskedValueIsZero(N0,~N1C->getValue() & (~0ULL>>(64-OpSizeInBits)), 879 TLI)) 880 return N1; 881 // fold (or (or x, c1), c2) -> (or x, c1|c2) 882 if (N1C && N0.getOpcode() == ISD::OR) { 883 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0)); 884 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 885 if (N00C) 886 return DAG.getNode(ISD::OR, VT, N0.getOperand(1), 887 DAG.getConstant(N1C->getValue()|N00C->getValue(), VT)); 888 if (N01C) 889 return DAG.getNode(ISD::OR, VT, N0.getOperand(0), 890 DAG.getConstant(N1C->getValue()|N01C->getValue(), VT)); 891 } 892 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y)) 893 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 894 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 895 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 896 897 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 898 MVT::isInteger(LL.getValueType())) { 899 // fold (X != 0) | (Y != 0) -> (X|Y != 0) 900 // fold (X < 0) | (Y < 0) -> (X|Y < 0) 901 if (cast<ConstantSDNode>(LR)->getValue() == 0 && 902 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) { 903 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 904 WorkList.push_back(ORNode.Val); 905 return DAG.getSetCC(VT, ORNode, LR, Op1); 906 } 907 // fold (X != -1) | (Y != -1) -> (X&Y != -1) 908 // fold (X > -1) | (Y > -1) -> (X&Y > -1) 909 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && 910 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) { 911 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL); 912 WorkList.push_back(ANDNode.Val); 913 return DAG.getSetCC(VT, ANDNode, LR, Op1); 914 } 915 } 916 // canonicalize equivalent to ll == rl 917 if (LL == RR && LR == RL) { 918 Op1 = ISD::getSetCCSwappedOperands(Op1); 919 std::swap(RL, RR); 920 } 921 if (LL == RL && LR == RR) { 922 bool isInteger = MVT::isInteger(LL.getValueType()); 923 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger); 924 if (Result != ISD::SETCC_INVALID) 925 return DAG.getSetCC(N0.getValueType(), LL, LR, Result); 926 } 927 } 928 // fold (or (zext x), (zext y)) -> (zext (or x, y)) 929 if (N0.getOpcode() == ISD::ZERO_EXTEND && 930 N1.getOpcode() == ISD::ZERO_EXTEND && 931 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) { 932 SDOperand ORNode = DAG.getNode(ISD::OR, N0.getOperand(0).getValueType(), 933 N0.getOperand(0), N1.getOperand(0)); 934 WorkList.push_back(ORNode.Val); 935 return DAG.getNode(ISD::ZERO_EXTEND, VT, ORNode); 936 } 937 return SDOperand(); 938} 939 940SDOperand DAGCombiner::visitXOR(SDNode *N) { 941 SDOperand N0 = N->getOperand(0); 942 SDOperand N1 = N->getOperand(1); 943 SDOperand LHS, RHS, CC; 944 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 945 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 946 MVT::ValueType VT = N0.getValueType(); 947 948 // fold (xor c1, c2) -> c1^c2 949 if (N0C && N1C) 950 return DAG.getConstant(N0C->getValue() ^ N1C->getValue(), VT); 951 // canonicalize constant to RHS 952 if (N0C && !N1C) { 953 std::swap(N0, N1); 954 std::swap(N0C, N1C); 955 } 956 // fold (xor x, 0) -> x 957 if (N1C && N1C->isNullValue()) 958 return N0; 959 // fold !(x cc y) -> (x !cc y) 960 if (N1C && N1C->getValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) { 961 bool isInt = MVT::isInteger(LHS.getValueType()); 962 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(), 963 isInt); 964 if (N0.getOpcode() == ISD::SETCC) 965 return DAG.getSetCC(VT, LHS, RHS, NotCC); 966 if (N0.getOpcode() == ISD::SELECT_CC) 967 return DAG.getSelectCC(LHS, RHS, N0.getOperand(2),N0.getOperand(3),NotCC); 968 assert(0 && "Unhandled SetCC Equivalent!"); 969 abort(); 970 } 971 // fold !(x or y) -> (!x and !y) iff x or y are setcc 972 if (N1C && N1C->getValue() == 1 && 973 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 974 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1); 975 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) { 976 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 977 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS 978 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS 979 WorkList.push_back(LHS.Val); WorkList.push_back(RHS.Val); 980 return DAG.getNode(NewOpcode, VT, LHS, RHS); 981 } 982 } 983 // fold !(x or y) -> (!x and !y) iff x or y are constants 984 if (N1C && N1C->isAllOnesValue() && 985 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 986 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1); 987 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) { 988 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 989 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS 990 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS 991 WorkList.push_back(LHS.Val); WorkList.push_back(RHS.Val); 992 return DAG.getNode(NewOpcode, VT, LHS, RHS); 993 } 994 } 995 // fold (xor (xor x, c1), c2) -> (xor x, c1^c2) 996 if (N1C && N0.getOpcode() == ISD::XOR) { 997 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0)); 998 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 999 if (N00C) 1000 return DAG.getNode(ISD::XOR, VT, N0.getOperand(1), 1001 DAG.getConstant(N1C->getValue()^N00C->getValue(), VT)); 1002 if (N01C) 1003 return DAG.getNode(ISD::XOR, VT, N0.getOperand(0), 1004 DAG.getConstant(N1C->getValue()^N01C->getValue(), VT)); 1005 } 1006 // fold (xor x, x) -> 0 1007 if (N0 == N1) 1008 return DAG.getConstant(0, VT); 1009 // fold (xor (zext x), (zext y)) -> (zext (xor x, y)) 1010 if (N0.getOpcode() == ISD::ZERO_EXTEND && 1011 N1.getOpcode() == ISD::ZERO_EXTEND && 1012 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) { 1013 SDOperand XORNode = DAG.getNode(ISD::XOR, N0.getOperand(0).getValueType(), 1014 N0.getOperand(0), N1.getOperand(0)); 1015 WorkList.push_back(XORNode.Val); 1016 return DAG.getNode(ISD::ZERO_EXTEND, VT, XORNode); 1017 } 1018 return SDOperand(); 1019} 1020 1021SDOperand DAGCombiner::visitSHL(SDNode *N) { 1022 SDOperand N0 = N->getOperand(0); 1023 SDOperand N1 = N->getOperand(1); 1024 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1025 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1026 MVT::ValueType VT = N0.getValueType(); 1027 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 1028 1029 // fold (shl c1, c2) -> c1<<c2 1030 if (N0C && N1C) 1031 return DAG.getConstant(N0C->getValue() << N1C->getValue(), VT); 1032 // fold (shl 0, x) -> 0 1033 if (N0C && N0C->isNullValue()) 1034 return N0; 1035 // fold (shl x, c >= size(x)) -> undef 1036 if (N1C && N1C->getValue() >= OpSizeInBits) 1037 return DAG.getNode(ISD::UNDEF, VT); 1038 // fold (shl x, 0) -> x 1039 if (N1C && N1C->isNullValue()) 1040 return N0; 1041 // if (shl x, c) is known to be zero, return 0 1042 if (N1C && MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits),TLI)) 1043 return DAG.getConstant(0, VT); 1044 // fold (shl (shl x, c1), c2) -> 0 or (shl x, c1+c2) 1045 if (N1C && N0.getOpcode() == ISD::SHL && 1046 N0.getOperand(1).getOpcode() == ISD::Constant) { 1047 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 1048 uint64_t c2 = N1C->getValue(); 1049 if (c1 + c2 > OpSizeInBits) 1050 return DAG.getConstant(0, VT); 1051 return DAG.getNode(ISD::SHL, VT, N0.getOperand(0), 1052 DAG.getConstant(c1 + c2, N1.getValueType())); 1053 } 1054 // fold (shl (srl x, c1), c2) -> (shl (and x, -1 << c1), c2-c1) or 1055 // (srl (and x, -1 << c1), c1-c2) 1056 if (N1C && N0.getOpcode() == ISD::SRL && 1057 N0.getOperand(1).getOpcode() == ISD::Constant) { 1058 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 1059 uint64_t c2 = N1C->getValue(); 1060 SDOperand Mask = DAG.getNode(ISD::AND, VT, N0.getOperand(0), 1061 DAG.getConstant(~0ULL << c1, VT)); 1062 if (c2 > c1) 1063 return DAG.getNode(ISD::SHL, VT, Mask, 1064 DAG.getConstant(c2-c1, N1.getValueType())); 1065 else 1066 return DAG.getNode(ISD::SRL, VT, Mask, 1067 DAG.getConstant(c1-c2, N1.getValueType())); 1068 } 1069 // fold (shl (sra x, c1), c1) -> (and x, -1 << c1) 1070 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) 1071 return DAG.getNode(ISD::AND, VT, N0.getOperand(0), 1072 DAG.getConstant(~0ULL << N1C->getValue(), VT)); 1073 return SDOperand(); 1074} 1075 1076SDOperand DAGCombiner::visitSRA(SDNode *N) { 1077 SDOperand N0 = N->getOperand(0); 1078 SDOperand N1 = N->getOperand(1); 1079 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1080 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1081 MVT::ValueType VT = N0.getValueType(); 1082 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 1083 1084 // fold (sra c1, c2) -> c1>>c2 1085 if (N0C && N1C) 1086 return DAG.getConstant(N0C->getSignExtended() >> N1C->getValue(), VT); 1087 // fold (sra 0, x) -> 0 1088 if (N0C && N0C->isNullValue()) 1089 return N0; 1090 // fold (sra -1, x) -> -1 1091 if (N0C && N0C->isAllOnesValue()) 1092 return N0; 1093 // fold (sra x, c >= size(x)) -> undef 1094 if (N1C && N1C->getValue() >= OpSizeInBits) 1095 return DAG.getNode(ISD::UNDEF, VT); 1096 // fold (sra x, 0) -> x 1097 if (N1C && N1C->isNullValue()) 1098 return N0; 1099 // If the sign bit is known to be zero, switch this to a SRL. 1100 if (MaskedValueIsZero(N0, (1ULL << (OpSizeInBits-1)), TLI)) 1101 return DAG.getNode(ISD::SRL, VT, N0, N1); 1102 return SDOperand(); 1103} 1104 1105SDOperand DAGCombiner::visitSRL(SDNode *N) { 1106 SDOperand N0 = N->getOperand(0); 1107 SDOperand N1 = N->getOperand(1); 1108 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1109 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1110 MVT::ValueType VT = N0.getValueType(); 1111 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 1112 1113 // fold (srl c1, c2) -> c1 >>u c2 1114 if (N0C && N1C) 1115 return DAG.getConstant(N0C->getValue() >> N1C->getValue(), VT); 1116 // fold (srl 0, x) -> 0 1117 if (N0C && N0C->isNullValue()) 1118 return N0; 1119 // fold (srl x, c >= size(x)) -> undef 1120 if (N1C && N1C->getValue() >= OpSizeInBits) 1121 return DAG.getNode(ISD::UNDEF, VT); 1122 // fold (srl x, 0) -> x 1123 if (N1C && N1C->isNullValue()) 1124 return N0; 1125 // if (srl x, c) is known to be zero, return 0 1126 if (N1C && MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits),TLI)) 1127 return DAG.getConstant(0, VT); 1128 // fold (srl (srl x, c1), c2) -> 0 or (srl x, c1+c2) 1129 if (N1C && N0.getOpcode() == ISD::SRL && 1130 N0.getOperand(1).getOpcode() == ISD::Constant) { 1131 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 1132 uint64_t c2 = N1C->getValue(); 1133 if (c1 + c2 > OpSizeInBits) 1134 return DAG.getConstant(0, VT); 1135 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0), 1136 DAG.getConstant(c1 + c2, N1.getValueType())); 1137 } 1138 return SDOperand(); 1139} 1140 1141SDOperand DAGCombiner::visitCTLZ(SDNode *N) { 1142 SDOperand N0 = N->getOperand(0); 1143 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1144 1145 // fold (ctlz c1) -> c2 1146 if (N0C) 1147 return DAG.getConstant(CountLeadingZeros_64(N0C->getValue()), 1148 N0.getValueType()); 1149 return SDOperand(); 1150} 1151 1152SDOperand DAGCombiner::visitCTTZ(SDNode *N) { 1153 SDOperand N0 = N->getOperand(0); 1154 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1155 1156 // fold (cttz c1) -> c2 1157 if (N0C) 1158 return DAG.getConstant(CountTrailingZeros_64(N0C->getValue()), 1159 N0.getValueType()); 1160 return SDOperand(); 1161} 1162 1163SDOperand DAGCombiner::visitCTPOP(SDNode *N) { 1164 SDOperand N0 = N->getOperand(0); 1165 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1166 1167 // fold (ctpop c1) -> c2 1168 if (N0C) 1169 return DAG.getConstant(CountPopulation_64(N0C->getValue()), 1170 N0.getValueType()); 1171 return SDOperand(); 1172} 1173 1174SDOperand DAGCombiner::visitSELECT(SDNode *N) { 1175 SDOperand N0 = N->getOperand(0); 1176 SDOperand N1 = N->getOperand(1); 1177 SDOperand N2 = N->getOperand(2); 1178 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1179 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1180 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2); 1181 MVT::ValueType VT = N->getValueType(0); 1182 1183 // fold select C, X, X -> X 1184 if (N1 == N2) 1185 return N1; 1186 // fold select true, X, Y -> X 1187 if (N0C && !N0C->isNullValue()) 1188 return N1; 1189 // fold select false, X, Y -> Y 1190 if (N0C && N0C->isNullValue()) 1191 return N2; 1192 // fold select C, 1, X -> C | X 1193 if (MVT::i1 == VT && N1C && N1C->getValue() == 1) 1194 return DAG.getNode(ISD::OR, VT, N0, N2); 1195 // fold select C, 0, X -> ~C & X 1196 // FIXME: this should check for C type == X type, not i1? 1197 if (MVT::i1 == VT && N1C && N1C->isNullValue()) { 1198 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT)); 1199 WorkList.push_back(XORNode.Val); 1200 return DAG.getNode(ISD::AND, VT, XORNode, N2); 1201 } 1202 // fold select C, X, 1 -> ~C | X 1203 if (MVT::i1 == VT && N2C && N2C->getValue() == 1) { 1204 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT)); 1205 WorkList.push_back(XORNode.Val); 1206 return DAG.getNode(ISD::OR, VT, XORNode, N1); 1207 } 1208 // fold select C, X, 0 -> C & X 1209 // FIXME: this should check for C type == X type, not i1? 1210 if (MVT::i1 == VT && N2C && N2C->isNullValue()) 1211 return DAG.getNode(ISD::AND, VT, N0, N1); 1212 // fold X ? X : Y --> X ? 1 : Y --> X | Y 1213 if (MVT::i1 == VT && N0 == N1) 1214 return DAG.getNode(ISD::OR, VT, N0, N2); 1215 // fold X ? Y : X --> X ? Y : 0 --> X & Y 1216 if (MVT::i1 == VT && N0 == N2) 1217 return DAG.getNode(ISD::AND, VT, N0, N1); 1218 // fold selects based on a setcc into other things, such as min/max/abs 1219 if (N0.getOpcode() == ISD::SETCC) 1220 return SimplifySelect(N0, N1, N2); 1221 return SDOperand(); 1222} 1223 1224SDOperand DAGCombiner::visitSELECT_CC(SDNode *N) { 1225 SDOperand N0 = N->getOperand(0); 1226 SDOperand N1 = N->getOperand(1); 1227 SDOperand N2 = N->getOperand(2); 1228 SDOperand N3 = N->getOperand(3); 1229 SDOperand N4 = N->getOperand(4); 1230 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1231 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1232 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2); 1233 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get(); 1234 1235 // Determine if the condition we're dealing with is constant 1236 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false); 1237 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val); 1238 1239 // fold select_cc lhs, rhs, x, x, cc -> x 1240 if (N2 == N3) 1241 return N2; 1242 // fold select_cc into other things, such as min/max/abs 1243 return SimplifySelectCC(N0, N1, N2, N3, CC); 1244} 1245 1246SDOperand DAGCombiner::visitSETCC(SDNode *N) { 1247 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1), 1248 cast<CondCodeSDNode>(N->getOperand(2))->get()); 1249} 1250 1251SDOperand DAGCombiner::visitADD_PARTS(SDNode *N) { 1252 SDOperand LHSLo = N->getOperand(0); 1253 SDOperand RHSLo = N->getOperand(2); 1254 MVT::ValueType VT = LHSLo.getValueType(); 1255 1256 // fold (a_Hi, 0) + (b_Hi, b_Lo) -> (b_Hi + a_Hi, b_Lo) 1257 if (MaskedValueIsZero(LHSLo, (1ULL << MVT::getSizeInBits(VT))-1, TLI)) { 1258 SDOperand Hi = DAG.getNode(ISD::ADD, VT, N->getOperand(1), 1259 N->getOperand(3)); 1260 WorkList.push_back(Hi.Val); 1261 CombineTo(N, RHSLo, Hi); 1262 return SDOperand(); 1263 } 1264 // fold (a_Hi, a_Lo) + (b_Hi, 0) -> (a_Hi + b_Hi, a_Lo) 1265 if (MaskedValueIsZero(RHSLo, (1ULL << MVT::getSizeInBits(VT))-1, TLI)) { 1266 SDOperand Hi = DAG.getNode(ISD::ADD, VT, N->getOperand(1), 1267 N->getOperand(3)); 1268 WorkList.push_back(Hi.Val); 1269 CombineTo(N, LHSLo, Hi); 1270 return SDOperand(); 1271 } 1272 return SDOperand(); 1273} 1274 1275SDOperand DAGCombiner::visitSUB_PARTS(SDNode *N) { 1276 SDOperand LHSLo = N->getOperand(0); 1277 SDOperand RHSLo = N->getOperand(2); 1278 MVT::ValueType VT = LHSLo.getValueType(); 1279 1280 // fold (a_Hi, a_Lo) - (b_Hi, 0) -> (a_Hi - b_Hi, a_Lo) 1281 if (MaskedValueIsZero(RHSLo, (1ULL << MVT::getSizeInBits(VT))-1, TLI)) { 1282 SDOperand Hi = DAG.getNode(ISD::SUB, VT, N->getOperand(1), 1283 N->getOperand(3)); 1284 WorkList.push_back(Hi.Val); 1285 CombineTo(N, LHSLo, Hi); 1286 return SDOperand(); 1287 } 1288 return SDOperand(); 1289} 1290 1291SDOperand DAGCombiner::visitSIGN_EXTEND(SDNode *N) { 1292 SDOperand N0 = N->getOperand(0); 1293 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1294 MVT::ValueType VT = N->getValueType(0); 1295 1296 // fold (sext c1) -> c1 1297 if (N0C) 1298 return DAG.getConstant(N0C->getSignExtended(), VT); 1299 // fold (sext (sext x)) -> (sext x) 1300 if (N0.getOpcode() == ISD::SIGN_EXTEND) 1301 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0.getOperand(0)); 1302 // fold (sext (sextload x)) -> (sextload x) 1303 if (N0.getOpcode() == ISD::SEXTLOAD && VT == N0.getValueType()) 1304 return N0; 1305 // fold (sext (load x)) -> (sextload x) 1306 if (N0.getOpcode() == ISD::LOAD && N0.Val->hasNUsesOfValue(1, 0)) { 1307 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N0.getOperand(0), 1308 N0.getOperand(1), N0.getOperand(2), 1309 N0.getValueType()); 1310 WorkList.push_back(N); 1311 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 1312 ExtLoad.getValue(1)); 1313 return SDOperand(); 1314 } 1315 return SDOperand(); 1316} 1317 1318SDOperand DAGCombiner::visitZERO_EXTEND(SDNode *N) { 1319 SDOperand N0 = N->getOperand(0); 1320 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1321 MVT::ValueType VT = N->getValueType(0); 1322 1323 // fold (zext c1) -> c1 1324 if (N0C) 1325 return DAG.getConstant(N0C->getValue(), VT); 1326 // fold (zext (zext x)) -> (zext x) 1327 if (N0.getOpcode() == ISD::ZERO_EXTEND) 1328 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0.getOperand(0)); 1329 return SDOperand(); 1330} 1331 1332SDOperand DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) { 1333 SDOperand N0 = N->getOperand(0); 1334 SDOperand N1 = N->getOperand(1); 1335 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1336 MVT::ValueType VT = N->getValueType(0); 1337 MVT::ValueType EVT = cast<VTSDNode>(N1)->getVT(); 1338 unsigned EVTBits = MVT::getSizeInBits(EVT); 1339 1340 // fold (sext_in_reg c1) -> c1 1341 if (N0C) { 1342 SDOperand Truncate = DAG.getConstant(N0C->getValue(), EVT); 1343 return DAG.getNode(ISD::SIGN_EXTEND, VT, Truncate); 1344 } 1345 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt1 1346 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 1347 cast<VTSDNode>(N0.getOperand(1))->getVT() <= EVT) { 1348 return N0; 1349 } 1350 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2 1351 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 1352 EVT < cast<VTSDNode>(N0.getOperand(1))->getVT()) { 1353 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), N1); 1354 } 1355 // fold (sext_in_reg (assert_sext x)) -> (assert_sext x) 1356 if (N0.getOpcode() == ISD::AssertSext && 1357 cast<VTSDNode>(N0.getOperand(1))->getVT() <= EVT) { 1358 return N0; 1359 } 1360 // fold (sext_in_reg (sextload x)) -> (sextload x) 1361 if (N0.getOpcode() == ISD::SEXTLOAD && 1362 cast<VTSDNode>(N0.getOperand(3))->getVT() <= EVT) { 1363 return N0; 1364 } 1365 // fold (sext_in_reg (setcc x)) -> setcc x iff (setcc x) == 0 or -1 1366 if (N0.getOpcode() == ISD::SETCC && 1367 TLI.getSetCCResultContents() == 1368 TargetLowering::ZeroOrNegativeOneSetCCResult) 1369 return N0; 1370 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is zero 1371 if (MaskedValueIsZero(N0, 1ULL << (EVTBits-1), TLI)) 1372 return DAG.getNode(ISD::AND, N0.getValueType(), N0, 1373 DAG.getConstant(~0ULL >> (64-EVTBits), VT)); 1374 // fold (sext_in_reg (srl x)) -> sra x 1375 if (N0.getOpcode() == ISD::SRL && 1376 N0.getOperand(1).getOpcode() == ISD::Constant && 1377 cast<ConstantSDNode>(N0.getOperand(1))->getValue() == EVTBits) { 1378 return DAG.getNode(ISD::SRA, N0.getValueType(), N0.getOperand(0), 1379 N0.getOperand(1)); 1380 } 1381 // fold (sext_inreg (extload x)) -> (sextload x) 1382 if (N0.getOpcode() == ISD::EXTLOAD && 1383 EVT == cast<VTSDNode>(N0.getOperand(3))->getVT() && 1384 (!AfterLegalize || TLI.isOperationLegal(ISD::SEXTLOAD, EVT))) { 1385 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N0.getOperand(0), 1386 N0.getOperand(1), N0.getOperand(2), 1387 EVT); 1388 WorkList.push_back(N); 1389 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 1390 return SDOperand(); 1391 } 1392 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use 1393 if (N0.getOpcode() == ISD::ZEXTLOAD && N0.Val->hasNUsesOfValue(1, 0) && 1394 EVT == cast<VTSDNode>(N0.getOperand(3))->getVT() && 1395 (!AfterLegalize || TLI.isOperationLegal(ISD::SEXTLOAD, EVT))) { 1396 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N0.getOperand(0), 1397 N0.getOperand(1), N0.getOperand(2), 1398 EVT); 1399 WorkList.push_back(N); 1400 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 1401 return SDOperand(); 1402 } 1403 return SDOperand(); 1404} 1405 1406SDOperand DAGCombiner::visitTRUNCATE(SDNode *N) { 1407 SDOperand N0 = N->getOperand(0); 1408 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1409 MVT::ValueType VT = N->getValueType(0); 1410 1411 // noop truncate 1412 if (N0.getValueType() == N->getValueType(0)) 1413 return N0; 1414 // fold (truncate c1) -> c1 1415 if (N0C) 1416 return DAG.getConstant(N0C->getValue(), VT); 1417 // fold (truncate (truncate x)) -> (truncate x) 1418 if (N0.getOpcode() == ISD::TRUNCATE) 1419 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0)); 1420 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x 1421 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::SIGN_EXTEND){ 1422 if (N0.getValueType() < VT) 1423 // if the source is smaller than the dest, we still need an extend 1424 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0)); 1425 else if (N0.getValueType() > VT) 1426 // if the source is larger than the dest, than we just need the truncate 1427 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0)); 1428 else 1429 // if the source and dest are the same type, we can drop both the extend 1430 // and the truncate 1431 return N0.getOperand(0); 1432 } 1433 // fold (truncate (load x)) -> (smaller load x) 1434 if (N0.getOpcode() == ISD::LOAD && N0.Val->hasNUsesOfValue(1, 0)) { 1435 assert(MVT::getSizeInBits(N0.getValueType()) > MVT::getSizeInBits(VT) && 1436 "Cannot truncate to larger type!"); 1437 MVT::ValueType PtrType = N0.getOperand(1).getValueType(); 1438 // For big endian targets, we need to add an offset to the pointer to load 1439 // the correct bytes. For little endian systems, we merely need to read 1440 // fewer bytes from the same pointer. 1441 uint64_t PtrOff = 1442 (MVT::getSizeInBits(N0.getValueType()) - MVT::getSizeInBits(VT)) / 8; 1443 SDOperand NewPtr = TLI.isLittleEndian() ? N0.getOperand(1) : 1444 DAG.getNode(ISD::ADD, PtrType, N0.getOperand(1), 1445 DAG.getConstant(PtrOff, PtrType)); 1446 WorkList.push_back(NewPtr.Val); 1447 SDOperand Load = DAG.getLoad(VT, N0.getOperand(0), NewPtr,N0.getOperand(2)); 1448 WorkList.push_back(N); 1449 CombineTo(N0.Val, Load, Load.getValue(1)); 1450 return SDOperand(); 1451 } 1452 return SDOperand(); 1453} 1454 1455SDOperand DAGCombiner::visitFADD(SDNode *N) { 1456 SDOperand N0 = N->getOperand(0); 1457 SDOperand N1 = N->getOperand(1); 1458 MVT::ValueType VT = N->getValueType(0); 1459 1460 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0)) 1461 if (ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1)) { 1462 // fold floating point (fadd c1, c2) 1463 return DAG.getConstantFP(N0CFP->getValue() + N1CFP->getValue(), 1464 N->getValueType(0)); 1465 } 1466 // fold (A + (-B)) -> A-B 1467 if (N1.getOpcode() == ISD::FNEG) 1468 return DAG.getNode(ISD::FSUB, VT, N0, N1.getOperand(0)); 1469 1470 // fold ((-A) + B) -> B-A 1471 if (N0.getOpcode() == ISD::FNEG) 1472 return DAG.getNode(ISD::FSUB, VT, N1, N0.getOperand(0)); 1473 1474 return SDOperand(); 1475} 1476 1477SDOperand DAGCombiner::visitFSUB(SDNode *N) { 1478 SDOperand N0 = N->getOperand(0); 1479 SDOperand N1 = N->getOperand(1); 1480 MVT::ValueType VT = N->getValueType(0); 1481 1482 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0)) 1483 if (ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1)) { 1484 // fold floating point (fsub c1, c2) 1485 return DAG.getConstantFP(N0CFP->getValue() - N1CFP->getValue(), 1486 N->getValueType(0)); 1487 } 1488 // fold (A-(-B)) -> A+B 1489 if (N1.getOpcode() == ISD::FNEG) 1490 return DAG.getNode(ISD::FADD, N0.getValueType(), N0, N1.getOperand(0)); 1491 1492 return SDOperand(); 1493} 1494 1495SDOperand DAGCombiner::visitFMUL(SDNode *N) { 1496 SDOperand N0 = N->getOperand(0); 1497 SDOperand N1 = N->getOperand(1); 1498 MVT::ValueType VT = N->getValueType(0); 1499 1500 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0)) 1501 if (ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1)) { 1502 // fold floating point (fmul c1, c2) 1503 return DAG.getConstantFP(N0CFP->getValue() * N1CFP->getValue(), 1504 N->getValueType(0)); 1505 } 1506 return SDOperand(); 1507} 1508 1509SDOperand DAGCombiner::visitFDIV(SDNode *N) { 1510 SDOperand N0 = N->getOperand(0); 1511 SDOperand N1 = N->getOperand(1); 1512 MVT::ValueType VT = N->getValueType(0); 1513 1514 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0)) 1515 if (ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1)) { 1516 // fold floating point (fdiv c1, c2) 1517 return DAG.getConstantFP(N0CFP->getValue() / N1CFP->getValue(), 1518 N->getValueType(0)); 1519 } 1520 return SDOperand(); 1521} 1522 1523SDOperand DAGCombiner::visitFREM(SDNode *N) { 1524 SDOperand N0 = N->getOperand(0); 1525 SDOperand N1 = N->getOperand(1); 1526 MVT::ValueType VT = N->getValueType(0); 1527 1528 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0)) 1529 if (ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1)) { 1530 // fold floating point (frem c1, c2) -> fmod(c1, c2) 1531 return DAG.getConstantFP(fmod(N0CFP->getValue(),N1CFP->getValue()), 1532 N->getValueType(0)); 1533 } 1534 return SDOperand(); 1535} 1536 1537 1538SDOperand DAGCombiner::visitSINT_TO_FP(SDNode *N) { 1539 SDOperand N0 = N->getOperand(0); 1540 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1541 1542 // fold (sint_to_fp c1) -> c1fp 1543 if (N0C) 1544 return DAG.getConstantFP(N0C->getSignExtended(), N->getValueType(0)); 1545 return SDOperand(); 1546} 1547 1548SDOperand DAGCombiner::visitUINT_TO_FP(SDNode *N) { 1549 SDOperand N0 = N->getOperand(0); 1550 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1551 1552 // fold (uint_to_fp c1) -> c1fp 1553 if (N0C) 1554 return DAG.getConstantFP(N0C->getValue(), N->getValueType(0)); 1555 return SDOperand(); 1556} 1557 1558SDOperand DAGCombiner::visitFP_TO_SINT(SDNode *N) { 1559 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0)); 1560 1561 // fold (fp_to_sint c1fp) -> c1 1562 if (N0CFP) 1563 return DAG.getConstant((int64_t)N0CFP->getValue(), N->getValueType(0)); 1564 return SDOperand(); 1565} 1566 1567SDOperand DAGCombiner::visitFP_TO_UINT(SDNode *N) { 1568 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0)); 1569 1570 // fold (fp_to_uint c1fp) -> c1 1571 if (N0CFP) 1572 return DAG.getConstant((uint64_t)N0CFP->getValue(), N->getValueType(0)); 1573 return SDOperand(); 1574} 1575 1576SDOperand DAGCombiner::visitFP_ROUND(SDNode *N) { 1577 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0)); 1578 1579 // fold (fp_round c1fp) -> c1fp 1580 if (N0CFP) 1581 return DAG.getConstantFP(N0CFP->getValue(), N->getValueType(0)); 1582 return SDOperand(); 1583} 1584 1585SDOperand DAGCombiner::visitFP_ROUND_INREG(SDNode *N) { 1586 SDOperand N0 = N->getOperand(0); 1587 MVT::ValueType VT = N->getValueType(0); 1588 MVT::ValueType EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 1589 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 1590 1591 // fold (fp_round_inreg c1fp) -> c1fp 1592 if (N0CFP) { 1593 SDOperand Round = DAG.getConstantFP(N0CFP->getValue(), EVT); 1594 return DAG.getNode(ISD::FP_EXTEND, VT, Round); 1595 } 1596 return SDOperand(); 1597} 1598 1599SDOperand DAGCombiner::visitFP_EXTEND(SDNode *N) { 1600 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0)); 1601 1602 // fold (fp_extend c1fp) -> c1fp 1603 if (N0CFP) 1604 return DAG.getConstantFP(N0CFP->getValue(), N->getValueType(0)); 1605 return SDOperand(); 1606} 1607 1608SDOperand DAGCombiner::visitFNEG(SDNode *N) { 1609 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0)); 1610 // fold (neg c1) -> -c1 1611 if (N0CFP) 1612 return DAG.getConstantFP(-N0CFP->getValue(), N->getValueType(0)); 1613 // fold (neg (sub x, y)) -> (sub y, x) 1614 if (N->getOperand(0).getOpcode() == ISD::SUB) 1615 return DAG.getNode(ISD::SUB, N->getValueType(0), N->getOperand(1), 1616 N->getOperand(0)); 1617 // fold (neg (neg x)) -> x 1618 if (N->getOperand(0).getOpcode() == ISD::FNEG) 1619 return N->getOperand(0).getOperand(0); 1620 return SDOperand(); 1621} 1622 1623SDOperand DAGCombiner::visitFABS(SDNode *N) { 1624 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0)); 1625 // fold (fabs c1) -> fabs(c1) 1626 if (N0CFP) 1627 return DAG.getConstantFP(fabs(N0CFP->getValue()), N->getValueType(0)); 1628 // fold (fabs (fabs x)) -> (fabs x) 1629 if (N->getOperand(0).getOpcode() == ISD::FABS) 1630 return N->getOperand(0); 1631 // fold (fabs (fneg x)) -> (fabs x) 1632 if (N->getOperand(0).getOpcode() == ISD::FNEG) 1633 return DAG.getNode(ISD::FABS, N->getValueType(0), 1634 N->getOperand(0).getOperand(0)); 1635 return SDOperand(); 1636} 1637 1638SDOperand DAGCombiner::visitBRCOND(SDNode *N) { 1639 SDOperand Chain = N->getOperand(0); 1640 SDOperand N1 = N->getOperand(1); 1641 SDOperand N2 = N->getOperand(2); 1642 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1643 1644 // never taken branch, fold to chain 1645 if (N1C && N1C->isNullValue()) 1646 return Chain; 1647 // unconditional branch 1648 if (N1C && N1C->getValue() == 1) 1649 return DAG.getNode(ISD::BR, MVT::Other, Chain, N2); 1650 return SDOperand(); 1651} 1652 1653SDOperand DAGCombiner::visitBRCONDTWOWAY(SDNode *N) { 1654 SDOperand Chain = N->getOperand(0); 1655 SDOperand N1 = N->getOperand(1); 1656 SDOperand N2 = N->getOperand(2); 1657 SDOperand N3 = N->getOperand(3); 1658 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1659 1660 // unconditional branch to true mbb 1661 if (N1C && N1C->getValue() == 1) 1662 return DAG.getNode(ISD::BR, MVT::Other, Chain, N2); 1663 // unconditional branch to false mbb 1664 if (N1C && N1C->isNullValue()) 1665 return DAG.getNode(ISD::BR, MVT::Other, Chain, N3); 1666 return SDOperand(); 1667} 1668 1669// Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB. 1670// 1671SDOperand DAGCombiner::visitBR_CC(SDNode *N) { 1672 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1)); 1673 SDOperand CondLHS = N->getOperand(2), CondRHS = N->getOperand(3); 1674 1675 // Use SimplifySetCC to simplify SETCC's. 1676 SDOperand Simp = SimplifySetCC(MVT::i1, CondLHS, CondRHS, CC->get(), false); 1677 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(Simp.Val); 1678 1679 // fold br_cc true, dest -> br dest (unconditional branch) 1680 if (SCCC && SCCC->getValue()) 1681 return DAG.getNode(ISD::BR, MVT::Other, N->getOperand(0), 1682 N->getOperand(4)); 1683 // fold br_cc false, dest -> unconditional fall through 1684 if (SCCC && SCCC->isNullValue()) 1685 return N->getOperand(0); 1686 // fold to a simpler setcc 1687 if (Simp.Val && Simp.getOpcode() == ISD::SETCC) 1688 return DAG.getNode(ISD::BR_CC, MVT::Other, N->getOperand(0), 1689 Simp.getOperand(2), Simp.getOperand(0), 1690 Simp.getOperand(1), N->getOperand(4)); 1691 return SDOperand(); 1692} 1693 1694SDOperand DAGCombiner::visitBRTWOWAY_CC(SDNode *N) { 1695 SDOperand Chain = N->getOperand(0); 1696 SDOperand CCN = N->getOperand(1); 1697 SDOperand LHS = N->getOperand(2); 1698 SDOperand RHS = N->getOperand(3); 1699 SDOperand N4 = N->getOperand(4); 1700 SDOperand N5 = N->getOperand(5); 1701 1702 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), LHS, RHS, 1703 cast<CondCodeSDNode>(CCN)->get(), false); 1704 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val); 1705 1706 // fold select_cc lhs, rhs, x, x, cc -> x 1707 if (N4 == N5) 1708 return DAG.getNode(ISD::BR, MVT::Other, Chain, N4); 1709 // fold select_cc true, x, y -> x 1710 if (SCCC && SCCC->getValue()) 1711 return DAG.getNode(ISD::BR, MVT::Other, Chain, N4); 1712 // fold select_cc false, x, y -> y 1713 if (SCCC && SCCC->isNullValue()) 1714 return DAG.getNode(ISD::BR, MVT::Other, Chain, N5); 1715 // fold to a simpler setcc 1716 if (SCC.Val && SCC.getOpcode() == ISD::SETCC) 1717 return DAG.getBR2Way_CC(Chain, SCC.getOperand(2), SCC.getOperand(0), 1718 SCC.getOperand(1), N4, N5); 1719 return SDOperand(); 1720} 1721 1722SDOperand DAGCombiner::visitLOAD(SDNode *N) { 1723 SDOperand Chain = N->getOperand(0); 1724 SDOperand Ptr = N->getOperand(1); 1725 SDOperand SrcValue = N->getOperand(2); 1726 1727 // If this load is directly stored, replace the load value with the stored 1728 // value. 1729 // TODO: Handle store large -> read small portion. 1730 // TODO: Handle TRUNCSTORE/EXTLOAD 1731 if (Chain.getOpcode() == ISD::STORE && Chain.getOperand(2) == Ptr && 1732 Chain.getOperand(1).getValueType() == N->getValueType(0)) 1733 return CombineTo(N, Chain.getOperand(1), Chain); 1734 1735 return SDOperand(); 1736} 1737 1738SDOperand DAGCombiner::visitSTORE(SDNode *N) { 1739 SDOperand Chain = N->getOperand(0); 1740 SDOperand Value = N->getOperand(1); 1741 SDOperand Ptr = N->getOperand(2); 1742 SDOperand SrcValue = N->getOperand(3); 1743 1744 // If this is a store that kills a previous store, remove the previous store. 1745 if (Chain.getOpcode() == ISD::STORE && Chain.getOperand(2) == Ptr && 1746 Chain.Val->hasOneUse() /* Avoid introducing DAG cycles */) { 1747 // Create a new store of Value that replaces both stores. 1748 SDNode *PrevStore = Chain.Val; 1749 if (PrevStore->getOperand(1) == Value) // Same value multiply stored. 1750 return Chain; 1751 SDOperand NewStore = DAG.getNode(ISD::STORE, MVT::Other, 1752 PrevStore->getOperand(0), Value, Ptr, 1753 SrcValue); 1754 CombineTo(N, NewStore); // Nuke this store. 1755 CombineTo(PrevStore, NewStore); // Nuke the previous store. 1756 return SDOperand(N, 0); 1757 } 1758 1759 return SDOperand(); 1760} 1761 1762SDOperand DAGCombiner::SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2){ 1763 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!"); 1764 1765 SDOperand SCC = SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), N1, N2, 1766 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 1767 // If we got a simplified select_cc node back from SimplifySelectCC, then 1768 // break it down into a new SETCC node, and a new SELECT node, and then return 1769 // the SELECT node, since we were called with a SELECT node. 1770 if (SCC.Val) { 1771 // Check to see if we got a select_cc back (to turn into setcc/select). 1772 // Otherwise, just return whatever node we got back, like fabs. 1773 if (SCC.getOpcode() == ISD::SELECT_CC) { 1774 SDOperand SETCC = DAG.getNode(ISD::SETCC, N0.getValueType(), 1775 SCC.getOperand(0), SCC.getOperand(1), 1776 SCC.getOperand(4)); 1777 WorkList.push_back(SETCC.Val); 1778 return DAG.getNode(ISD::SELECT, SCC.getValueType(), SCC.getOperand(2), 1779 SCC.getOperand(3), SETCC); 1780 } 1781 return SCC; 1782 } 1783 return SDOperand(); 1784} 1785 1786SDOperand DAGCombiner::SimplifySelectCC(SDOperand N0, SDOperand N1, 1787 SDOperand N2, SDOperand N3, 1788 ISD::CondCode CC) { 1789 1790 MVT::ValueType VT = N2.getValueType(); 1791 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 1792 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 1793 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val); 1794 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.Val); 1795 1796 // Determine if the condition we're dealing with is constant 1797 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false); 1798 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val); 1799 1800 // fold select_cc true, x, y -> x 1801 if (SCCC && SCCC->getValue()) 1802 return N2; 1803 // fold select_cc false, x, y -> y 1804 if (SCCC && SCCC->getValue() == 0) 1805 return N3; 1806 1807 // Check to see if we can simplify the select into an fabs node 1808 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) { 1809 // Allow either -0.0 or 0.0 1810 if (CFP->getValue() == 0.0) { 1811 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs 1812 if ((CC == ISD::SETGE || CC == ISD::SETGT) && 1813 N0 == N2 && N3.getOpcode() == ISD::FNEG && 1814 N2 == N3.getOperand(0)) 1815 return DAG.getNode(ISD::FABS, VT, N0); 1816 1817 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs 1818 if ((CC == ISD::SETLT || CC == ISD::SETLE) && 1819 N0 == N3 && N2.getOpcode() == ISD::FNEG && 1820 N2.getOperand(0) == N3) 1821 return DAG.getNode(ISD::FABS, VT, N3); 1822 } 1823 } 1824 1825 // Check to see if we can perform the "gzip trick", transforming 1826 // select_cc setlt X, 0, A, 0 -> and (sra X, size(X)-1), A 1827 if (N1C && N1C->isNullValue() && N3C && N3C->isNullValue() && 1828 MVT::isInteger(N0.getValueType()) && 1829 MVT::isInteger(N2.getValueType()) && CC == ISD::SETLT) { 1830 MVT::ValueType XType = N0.getValueType(); 1831 MVT::ValueType AType = N2.getValueType(); 1832 if (XType >= AType) { 1833 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a 1834 // single-bit constant. 1835 if (N2C && ((N2C->getValue() & (N2C->getValue()-1)) == 0)) { 1836 unsigned ShCtV = Log2_64(N2C->getValue()); 1837 ShCtV = MVT::getSizeInBits(XType)-ShCtV-1; 1838 SDOperand ShCt = DAG.getConstant(ShCtV, TLI.getShiftAmountTy()); 1839 SDOperand Shift = DAG.getNode(ISD::SRL, XType, N0, ShCt); 1840 WorkList.push_back(Shift.Val); 1841 if (XType > AType) { 1842 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift); 1843 WorkList.push_back(Shift.Val); 1844 } 1845 return DAG.getNode(ISD::AND, AType, Shift, N2); 1846 } 1847 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0, 1848 DAG.getConstant(MVT::getSizeInBits(XType)-1, 1849 TLI.getShiftAmountTy())); 1850 WorkList.push_back(Shift.Val); 1851 if (XType > AType) { 1852 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift); 1853 WorkList.push_back(Shift.Val); 1854 } 1855 return DAG.getNode(ISD::AND, AType, Shift, N2); 1856 } 1857 } 1858 1859 // fold select C, 16, 0 -> shl C, 4 1860 if (N2C && N3C && N3C->isNullValue() && isPowerOf2_64(N2C->getValue()) && 1861 TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult) { 1862 // Get a SetCC of the condition 1863 // FIXME: Should probably make sure that setcc is legal if we ever have a 1864 // target where it isn't. 1865 SDOperand Temp, SCC = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC); 1866 WorkList.push_back(SCC.Val); 1867 // cast from setcc result type to select result type 1868 if (AfterLegalize) 1869 Temp = DAG.getZeroExtendInReg(SCC, N2.getValueType()); 1870 else 1871 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC); 1872 WorkList.push_back(Temp.Val); 1873 // shl setcc result by log2 n2c 1874 return DAG.getNode(ISD::SHL, N2.getValueType(), Temp, 1875 DAG.getConstant(Log2_64(N2C->getValue()), 1876 TLI.getShiftAmountTy())); 1877 } 1878 1879 // Check to see if this is the equivalent of setcc 1880 // FIXME: Turn all of these into setcc if setcc if setcc is legal 1881 // otherwise, go ahead with the folds. 1882 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getValue() == 1ULL)) { 1883 MVT::ValueType XType = N0.getValueType(); 1884 if (TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultTy())) { 1885 SDOperand Res = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC); 1886 if (Res.getValueType() != VT) 1887 Res = DAG.getNode(ISD::ZERO_EXTEND, VT, Res); 1888 return Res; 1889 } 1890 1891 // seteq X, 0 -> srl (ctlz X, log2(size(X))) 1892 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ && 1893 TLI.isOperationLegal(ISD::CTLZ, XType)) { 1894 SDOperand Ctlz = DAG.getNode(ISD::CTLZ, XType, N0); 1895 return DAG.getNode(ISD::SRL, XType, Ctlz, 1896 DAG.getConstant(Log2_32(MVT::getSizeInBits(XType)), 1897 TLI.getShiftAmountTy())); 1898 } 1899 // setgt X, 0 -> srl (and (-X, ~X), size(X)-1) 1900 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) { 1901 SDOperand NegN0 = DAG.getNode(ISD::SUB, XType, DAG.getConstant(0, XType), 1902 N0); 1903 SDOperand NotN0 = DAG.getNode(ISD::XOR, XType, N0, 1904 DAG.getConstant(~0ULL, XType)); 1905 return DAG.getNode(ISD::SRL, XType, 1906 DAG.getNode(ISD::AND, XType, NegN0, NotN0), 1907 DAG.getConstant(MVT::getSizeInBits(XType)-1, 1908 TLI.getShiftAmountTy())); 1909 } 1910 // setgt X, -1 -> xor (srl (X, size(X)-1), 1) 1911 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) { 1912 SDOperand Sign = DAG.getNode(ISD::SRL, XType, N0, 1913 DAG.getConstant(MVT::getSizeInBits(XType)-1, 1914 TLI.getShiftAmountTy())); 1915 return DAG.getNode(ISD::XOR, XType, Sign, DAG.getConstant(1, XType)); 1916 } 1917 } 1918 1919 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X -> 1920 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 1921 if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) && 1922 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1)) { 1923 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N2.getOperand(0))) { 1924 MVT::ValueType XType = N0.getValueType(); 1925 if (SubC->isNullValue() && MVT::isInteger(XType)) { 1926 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0, 1927 DAG.getConstant(MVT::getSizeInBits(XType)-1, 1928 TLI.getShiftAmountTy())); 1929 SDOperand Add = DAG.getNode(ISD::ADD, XType, N0, Shift); 1930 WorkList.push_back(Shift.Val); 1931 WorkList.push_back(Add.Val); 1932 return DAG.getNode(ISD::XOR, XType, Add, Shift); 1933 } 1934 } 1935 } 1936 1937 return SDOperand(); 1938} 1939 1940SDOperand DAGCombiner::SimplifySetCC(MVT::ValueType VT, SDOperand N0, 1941 SDOperand N1, ISD::CondCode Cond, 1942 bool foldBooleans) { 1943 // These setcc operations always fold. 1944 switch (Cond) { 1945 default: break; 1946 case ISD::SETFALSE: 1947 case ISD::SETFALSE2: return DAG.getConstant(0, VT); 1948 case ISD::SETTRUE: 1949 case ISD::SETTRUE2: return DAG.getConstant(1, VT); 1950 } 1951 1952 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val)) { 1953 uint64_t C1 = N1C->getValue(); 1954 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val)) { 1955 uint64_t C0 = N0C->getValue(); 1956 1957 // Sign extend the operands if required 1958 if (ISD::isSignedIntSetCC(Cond)) { 1959 C0 = N0C->getSignExtended(); 1960 C1 = N1C->getSignExtended(); 1961 } 1962 1963 switch (Cond) { 1964 default: assert(0 && "Unknown integer setcc!"); 1965 case ISD::SETEQ: return DAG.getConstant(C0 == C1, VT); 1966 case ISD::SETNE: return DAG.getConstant(C0 != C1, VT); 1967 case ISD::SETULT: return DAG.getConstant(C0 < C1, VT); 1968 case ISD::SETUGT: return DAG.getConstant(C0 > C1, VT); 1969 case ISD::SETULE: return DAG.getConstant(C0 <= C1, VT); 1970 case ISD::SETUGE: return DAG.getConstant(C0 >= C1, VT); 1971 case ISD::SETLT: return DAG.getConstant((int64_t)C0 < (int64_t)C1, VT); 1972 case ISD::SETGT: return DAG.getConstant((int64_t)C0 > (int64_t)C1, VT); 1973 case ISD::SETLE: return DAG.getConstant((int64_t)C0 <= (int64_t)C1, VT); 1974 case ISD::SETGE: return DAG.getConstant((int64_t)C0 >= (int64_t)C1, VT); 1975 } 1976 } else { 1977 // If the LHS is a ZERO_EXTEND, perform the comparison on the input. 1978 if (N0.getOpcode() == ISD::ZERO_EXTEND) { 1979 unsigned InSize = MVT::getSizeInBits(N0.getOperand(0).getValueType()); 1980 1981 // If the comparison constant has bits in the upper part, the 1982 // zero-extended value could never match. 1983 if (C1 & (~0ULL << InSize)) { 1984 unsigned VSize = MVT::getSizeInBits(N0.getValueType()); 1985 switch (Cond) { 1986 case ISD::SETUGT: 1987 case ISD::SETUGE: 1988 case ISD::SETEQ: return DAG.getConstant(0, VT); 1989 case ISD::SETULT: 1990 case ISD::SETULE: 1991 case ISD::SETNE: return DAG.getConstant(1, VT); 1992 case ISD::SETGT: 1993 case ISD::SETGE: 1994 // True if the sign bit of C1 is set. 1995 return DAG.getConstant((C1 & (1ULL << VSize)) != 0, VT); 1996 case ISD::SETLT: 1997 case ISD::SETLE: 1998 // True if the sign bit of C1 isn't set. 1999 return DAG.getConstant((C1 & (1ULL << VSize)) == 0, VT); 2000 default: 2001 break; 2002 } 2003 } 2004 2005 // Otherwise, we can perform the comparison with the low bits. 2006 switch (Cond) { 2007 case ISD::SETEQ: 2008 case ISD::SETNE: 2009 case ISD::SETUGT: 2010 case ISD::SETUGE: 2011 case ISD::SETULT: 2012 case ISD::SETULE: 2013 return DAG.getSetCC(VT, N0.getOperand(0), 2014 DAG.getConstant(C1, N0.getOperand(0).getValueType()), 2015 Cond); 2016 default: 2017 break; // todo, be more careful with signed comparisons 2018 } 2019 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 2020 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { 2021 MVT::ValueType ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT(); 2022 unsigned ExtSrcTyBits = MVT::getSizeInBits(ExtSrcTy); 2023 MVT::ValueType ExtDstTy = N0.getValueType(); 2024 unsigned ExtDstTyBits = MVT::getSizeInBits(ExtDstTy); 2025 2026 // If the extended part has any inconsistent bits, it cannot ever 2027 // compare equal. In other words, they have to be all ones or all 2028 // zeros. 2029 uint64_t ExtBits = 2030 (~0ULL >> (64-ExtSrcTyBits)) & (~0ULL << (ExtDstTyBits-1)); 2031 if ((C1 & ExtBits) != 0 && (C1 & ExtBits) != ExtBits) 2032 return DAG.getConstant(Cond == ISD::SETNE, VT); 2033 2034 SDOperand ZextOp; 2035 MVT::ValueType Op0Ty = N0.getOperand(0).getValueType(); 2036 if (Op0Ty == ExtSrcTy) { 2037 ZextOp = N0.getOperand(0); 2038 } else { 2039 int64_t Imm = ~0ULL >> (64-ExtSrcTyBits); 2040 ZextOp = DAG.getNode(ISD::AND, Op0Ty, N0.getOperand(0), 2041 DAG.getConstant(Imm, Op0Ty)); 2042 } 2043 WorkList.push_back(ZextOp.Val); 2044 // Otherwise, make this a use of a zext. 2045 return DAG.getSetCC(VT, ZextOp, 2046 DAG.getConstant(C1 & (~0ULL>>(64-ExtSrcTyBits)), 2047 ExtDstTy), 2048 Cond); 2049 } 2050 2051 uint64_t MinVal, MaxVal; 2052 unsigned OperandBitSize = MVT::getSizeInBits(N1C->getValueType(0)); 2053 if (ISD::isSignedIntSetCC(Cond)) { 2054 MinVal = 1ULL << (OperandBitSize-1); 2055 if (OperandBitSize != 1) // Avoid X >> 64, which is undefined. 2056 MaxVal = ~0ULL >> (65-OperandBitSize); 2057 else 2058 MaxVal = 0; 2059 } else { 2060 MinVal = 0; 2061 MaxVal = ~0ULL >> (64-OperandBitSize); 2062 } 2063 2064 // Canonicalize GE/LE comparisons to use GT/LT comparisons. 2065 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) { 2066 if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true 2067 --C1; // X >= C0 --> X > (C0-1) 2068 return DAG.getSetCC(VT, N0, DAG.getConstant(C1, N1.getValueType()), 2069 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT); 2070 } 2071 2072 if (Cond == ISD::SETLE || Cond == ISD::SETULE) { 2073 if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true 2074 ++C1; // X <= C0 --> X < (C0+1) 2075 return DAG.getSetCC(VT, N0, DAG.getConstant(C1, N1.getValueType()), 2076 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT); 2077 } 2078 2079 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal) 2080 return DAG.getConstant(0, VT); // X < MIN --> false 2081 2082 // Canonicalize setgt X, Min --> setne X, Min 2083 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal) 2084 return DAG.getSetCC(VT, N0, N1, ISD::SETNE); 2085 2086 // If we have setult X, 1, turn it into seteq X, 0 2087 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1) 2088 return DAG.getSetCC(VT, N0, DAG.getConstant(MinVal, N0.getValueType()), 2089 ISD::SETEQ); 2090 // If we have setugt X, Max-1, turn it into seteq X, Max 2091 else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1) 2092 return DAG.getSetCC(VT, N0, DAG.getConstant(MaxVal, N0.getValueType()), 2093 ISD::SETEQ); 2094 2095 // If we have "setcc X, C0", check to see if we can shrink the immediate 2096 // by changing cc. 2097 2098 // SETUGT X, SINTMAX -> SETLT X, 0 2099 if (Cond == ISD::SETUGT && OperandBitSize != 1 && 2100 C1 == (~0ULL >> (65-OperandBitSize))) 2101 return DAG.getSetCC(VT, N0, DAG.getConstant(0, N1.getValueType()), 2102 ISD::SETLT); 2103 2104 // FIXME: Implement the rest of these. 2105 2106 // Fold bit comparisons when we can. 2107 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 2108 VT == N0.getValueType() && N0.getOpcode() == ISD::AND) 2109 if (ConstantSDNode *AndRHS = 2110 dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 2111 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3 2112 // Perform the xform if the AND RHS is a single bit. 2113 if ((AndRHS->getValue() & (AndRHS->getValue()-1)) == 0) { 2114 return DAG.getNode(ISD::SRL, VT, N0, 2115 DAG.getConstant(Log2_64(AndRHS->getValue()), 2116 TLI.getShiftAmountTy())); 2117 } 2118 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getValue()) { 2119 // (X & 8) == 8 --> (X & 8) >> 3 2120 // Perform the xform if C1 is a single bit. 2121 if ((C1 & (C1-1)) == 0) { 2122 return DAG.getNode(ISD::SRL, VT, N0, 2123 DAG.getConstant(Log2_64(C1),TLI.getShiftAmountTy())); 2124 } 2125 } 2126 } 2127 } 2128 } else if (isa<ConstantSDNode>(N0.Val)) { 2129 // Ensure that the constant occurs on the RHS. 2130 return DAG.getSetCC(VT, N1, N0, ISD::getSetCCSwappedOperands(Cond)); 2131 } 2132 2133 if (ConstantFPSDNode *N0C = dyn_cast<ConstantFPSDNode>(N0.Val)) 2134 if (ConstantFPSDNode *N1C = dyn_cast<ConstantFPSDNode>(N1.Val)) { 2135 double C0 = N0C->getValue(), C1 = N1C->getValue(); 2136 2137 switch (Cond) { 2138 default: break; // FIXME: Implement the rest of these! 2139 case ISD::SETEQ: return DAG.getConstant(C0 == C1, VT); 2140 case ISD::SETNE: return DAG.getConstant(C0 != C1, VT); 2141 case ISD::SETLT: return DAG.getConstant(C0 < C1, VT); 2142 case ISD::SETGT: return DAG.getConstant(C0 > C1, VT); 2143 case ISD::SETLE: return DAG.getConstant(C0 <= C1, VT); 2144 case ISD::SETGE: return DAG.getConstant(C0 >= C1, VT); 2145 } 2146 } else { 2147 // Ensure that the constant occurs on the RHS. 2148 return DAG.getSetCC(VT, N1, N0, ISD::getSetCCSwappedOperands(Cond)); 2149 } 2150 2151 if (N0 == N1) { 2152 // We can always fold X == Y for integer setcc's. 2153 if (MVT::isInteger(N0.getValueType())) 2154 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT); 2155 unsigned UOF = ISD::getUnorderedFlavor(Cond); 2156 if (UOF == 2) // FP operators that are undefined on NaNs. 2157 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT); 2158 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond))) 2159 return DAG.getConstant(UOF, VT); 2160 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO 2161 // if it is not already. 2162 ISD::CondCode NewCond = UOF == 0 ? ISD::SETUO : ISD::SETO; 2163 if (NewCond != Cond) 2164 return DAG.getSetCC(VT, N0, N1, NewCond); 2165 } 2166 2167 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 2168 MVT::isInteger(N0.getValueType())) { 2169 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB || 2170 N0.getOpcode() == ISD::XOR) { 2171 // Simplify (X+Y) == (X+Z) --> Y == Z 2172 if (N0.getOpcode() == N1.getOpcode()) { 2173 if (N0.getOperand(0) == N1.getOperand(0)) 2174 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(1), Cond); 2175 if (N0.getOperand(1) == N1.getOperand(1)) 2176 return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(0), Cond); 2177 if (isCommutativeBinOp(N0.getOpcode())) { 2178 // If X op Y == Y op X, try other combinations. 2179 if (N0.getOperand(0) == N1.getOperand(1)) 2180 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(0), Cond); 2181 if (N0.getOperand(1) == N1.getOperand(0)) 2182 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(1), Cond); 2183 } 2184 } 2185 2186 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0. Common for condcodes. 2187 if (N0.getOpcode() == ISD::XOR) 2188 if (ConstantSDNode *XORC = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 2189 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) { 2190 // If we know that all of the inverted bits are zero, don't bother 2191 // performing the inversion. 2192 if (MaskedValueIsZero(N0.getOperand(0), ~XORC->getValue(), TLI)) 2193 return DAG.getSetCC(VT, N0.getOperand(0), 2194 DAG.getConstant(XORC->getValue()^RHSC->getValue(), 2195 N0.getValueType()), Cond); 2196 } 2197 2198 // Simplify (X+Z) == X --> Z == 0 2199 if (N0.getOperand(0) == N1) 2200 return DAG.getSetCC(VT, N0.getOperand(1), 2201 DAG.getConstant(0, N0.getValueType()), Cond); 2202 if (N0.getOperand(1) == N1) { 2203 if (isCommutativeBinOp(N0.getOpcode())) 2204 return DAG.getSetCC(VT, N0.getOperand(0), 2205 DAG.getConstant(0, N0.getValueType()), Cond); 2206 else { 2207 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!"); 2208 // (Z-X) == X --> Z == X<<1 2209 SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(), 2210 N1, 2211 DAG.getConstant(1,TLI.getShiftAmountTy())); 2212 WorkList.push_back(SH.Val); 2213 return DAG.getSetCC(VT, N0.getOperand(0), SH, Cond); 2214 } 2215 } 2216 } 2217 2218 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB || 2219 N1.getOpcode() == ISD::XOR) { 2220 // Simplify X == (X+Z) --> Z == 0 2221 if (N1.getOperand(0) == N0) { 2222 return DAG.getSetCC(VT, N1.getOperand(1), 2223 DAG.getConstant(0, N1.getValueType()), Cond); 2224 } else if (N1.getOperand(1) == N0) { 2225 if (isCommutativeBinOp(N1.getOpcode())) { 2226 return DAG.getSetCC(VT, N1.getOperand(0), 2227 DAG.getConstant(0, N1.getValueType()), Cond); 2228 } else { 2229 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!"); 2230 // X == (Z-X) --> X<<1 == Z 2231 SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(), N0, 2232 DAG.getConstant(1,TLI.getShiftAmountTy())); 2233 WorkList.push_back(SH.Val); 2234 return DAG.getSetCC(VT, SH, N1.getOperand(0), Cond); 2235 } 2236 } 2237 } 2238 } 2239 2240 // Fold away ALL boolean setcc's. 2241 SDOperand Temp; 2242 if (N0.getValueType() == MVT::i1 && foldBooleans) { 2243 switch (Cond) { 2244 default: assert(0 && "Unknown integer setcc!"); 2245 case ISD::SETEQ: // X == Y -> (X^Y)^1 2246 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, N1); 2247 N0 = DAG.getNode(ISD::XOR, MVT::i1, Temp, DAG.getConstant(1, MVT::i1)); 2248 WorkList.push_back(Temp.Val); 2249 break; 2250 case ISD::SETNE: // X != Y --> (X^Y) 2251 N0 = DAG.getNode(ISD::XOR, MVT::i1, N0, N1); 2252 break; 2253 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> X^1 & Y 2254 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> X^1 & Y 2255 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1)); 2256 N0 = DAG.getNode(ISD::AND, MVT::i1, N1, Temp); 2257 WorkList.push_back(Temp.Val); 2258 break; 2259 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> Y^1 & X 2260 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> Y^1 & X 2261 Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1)); 2262 N0 = DAG.getNode(ISD::AND, MVT::i1, N0, Temp); 2263 WorkList.push_back(Temp.Val); 2264 break; 2265 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> X^1 | Y 2266 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> X^1 | Y 2267 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1)); 2268 N0 = DAG.getNode(ISD::OR, MVT::i1, N1, Temp); 2269 WorkList.push_back(Temp.Val); 2270 break; 2271 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> Y^1 | X 2272 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> Y^1 | X 2273 Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1)); 2274 N0 = DAG.getNode(ISD::OR, MVT::i1, N0, Temp); 2275 break; 2276 } 2277 if (VT != MVT::i1) { 2278 WorkList.push_back(N0.Val); 2279 // FIXME: If running after legalize, we probably can't do this. 2280 N0 = DAG.getNode(ISD::ZERO_EXTEND, VT, N0); 2281 } 2282 return N0; 2283 } 2284 2285 // Could not fold it. 2286 return SDOperand(); 2287} 2288 2289// SelectionDAG::Combine - This is the entry point for the file. 2290// 2291void SelectionDAG::Combine(bool RunningAfterLegalize) { 2292 /// run - This is the main entry point to this class. 2293 /// 2294 DAGCombiner(*this).Run(RunningAfterLegalize); 2295} 2296