DAGCombiner.cpp revision 91153686f04bafe3b10c99edb1735444953f7517
1//===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by Nate Begeman and is distributed under the 6// University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run 11// both before and after the DAG is legalized. 12// 13// FIXME: Missing folds 14// sdiv, udiv, srem, urem (X, const) where X is an integer can be expanded into 15// a sequence of multiplies, shifts, and adds. This should be controlled by 16// some kind of hint from the target that int div is expensive. 17// various folds of mulh[s,u] by constants such as -1, powers of 2, etc. 18// 19// FIXME: select C, pow2, pow2 -> something smart 20// FIXME: trunc(select X, Y, Z) -> select X, trunc(Y), trunc(Z) 21// FIXME: Dead stores -> nuke 22// FIXME: shr X, (and Y,31) -> shr X, Y (TRICKY!) 23// FIXME: mul (x, const) -> shifts + adds 24// FIXME: undef values 25// FIXME: divide by zero is currently left unfolded. do we want to turn this 26// into an undef? 27// FIXME: select ne (select cc, 1, 0), 0, true, false -> select cc, true, false 28// 29//===----------------------------------------------------------------------===// 30 31#define DEBUG_TYPE "dagcombine" 32#include "llvm/ADT/Statistic.h" 33#include "llvm/Analysis/AliasAnalysis.h" 34#include "llvm/CodeGen/SelectionDAG.h" 35#include "llvm/Support/Debug.h" 36#include "llvm/Support/MathExtras.h" 37#include "llvm/Target/TargetLowering.h" 38#include "llvm/Target/TargetOptions.h" 39#include "llvm/Support/Compiler.h" 40#include "llvm/Support/CommandLine.h" 41#include <algorithm> 42using namespace llvm; 43 44STATISTIC(NodesCombined , "Number of dag nodes combined"); 45STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created"); 46STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created"); 47 48namespace { 49#ifndef NDEBUG 50 static cl::opt<bool> 51 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden, 52 cl::desc("Pop up a window to show dags before the first " 53 "dag combine pass")); 54 static cl::opt<bool> 55 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden, 56 cl::desc("Pop up a window to show dags before the second " 57 "dag combine pass")); 58#else 59 static const bool ViewDAGCombine1 = false; 60 static const bool ViewDAGCombine2 = false; 61#endif 62 63 static cl::opt<bool> 64 CombinerAA("combiner-alias-analysis", cl::Hidden, 65 cl::desc("Turn on alias analysis during testing")); 66 67 static cl::opt<bool> 68 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden, 69 cl::desc("Include global information in alias analysis")); 70 71//------------------------------ DAGCombiner ---------------------------------// 72 73 class VISIBILITY_HIDDEN DAGCombiner { 74 SelectionDAG &DAG; 75 TargetLowering &TLI; 76 bool AfterLegalize; 77 78 // Worklist of all of the nodes that need to be simplified. 79 std::vector<SDNode*> WorkList; 80 81 // AA - Used for DAG load/store alias analysis. 82 AliasAnalysis &AA; 83 84 /// AddUsersToWorkList - When an instruction is simplified, add all users of 85 /// the instruction to the work lists because they might get more simplified 86 /// now. 87 /// 88 void AddUsersToWorkList(SDNode *N) { 89 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 90 UI != UE; ++UI) 91 AddToWorkList(*UI); 92 } 93 94 /// removeFromWorkList - remove all instances of N from the worklist. 95 /// 96 void removeFromWorkList(SDNode *N) { 97 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N), 98 WorkList.end()); 99 } 100 101 public: 102 /// AddToWorkList - Add to the work list making sure it's instance is at the 103 /// the back (next to be processed.) 104 void AddToWorkList(SDNode *N) { 105 removeFromWorkList(N); 106 WorkList.push_back(N); 107 } 108 109 SDOperand CombineTo(SDNode *N, const SDOperand *To, unsigned NumTo, 110 bool AddTo = true) { 111 assert(N->getNumValues() == NumTo && "Broken CombineTo call!"); 112 ++NodesCombined; 113 DOUT << "\nReplacing.1 "; DEBUG(N->dump()); 114 DOUT << "\nWith: "; DEBUG(To[0].Val->dump(&DAG)); 115 DOUT << " and " << NumTo-1 << " other values\n"; 116 std::vector<SDNode*> NowDead; 117 DAG.ReplaceAllUsesWith(N, To, &NowDead); 118 119 if (AddTo) { 120 // Push the new nodes and any users onto the worklist 121 for (unsigned i = 0, e = NumTo; i != e; ++i) { 122 AddToWorkList(To[i].Val); 123 AddUsersToWorkList(To[i].Val); 124 } 125 } 126 127 // Nodes can be reintroduced into the worklist. Make sure we do not 128 // process a node that has been replaced. 129 removeFromWorkList(N); 130 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 131 removeFromWorkList(NowDead[i]); 132 133 // Finally, since the node is now dead, remove it from the graph. 134 DAG.DeleteNode(N); 135 return SDOperand(N, 0); 136 } 137 138 SDOperand CombineTo(SDNode *N, SDOperand Res, bool AddTo = true) { 139 return CombineTo(N, &Res, 1, AddTo); 140 } 141 142 SDOperand CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1, 143 bool AddTo = true) { 144 SDOperand To[] = { Res0, Res1 }; 145 return CombineTo(N, To, 2, AddTo); 146 } 147 private: 148 149 /// SimplifyDemandedBits - Check the specified integer node value to see if 150 /// it can be simplified or if things it uses can be simplified by bit 151 /// propagation. If so, return true. 152 bool SimplifyDemandedBits(SDOperand Op) { 153 TargetLowering::TargetLoweringOpt TLO(DAG); 154 uint64_t KnownZero, KnownOne; 155 uint64_t Demanded = MVT::getIntVTBitMask(Op.getValueType()); 156 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO)) 157 return false; 158 159 // Revisit the node. 160 AddToWorkList(Op.Val); 161 162 // Replace the old value with the new one. 163 ++NodesCombined; 164 DOUT << "\nReplacing.2 "; DEBUG(TLO.Old.Val->dump()); 165 DOUT << "\nWith: "; DEBUG(TLO.New.Val->dump(&DAG)); 166 DOUT << '\n'; 167 168 std::vector<SDNode*> NowDead; 169 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, NowDead); 170 171 // Push the new node and any (possibly new) users onto the worklist. 172 AddToWorkList(TLO.New.Val); 173 AddUsersToWorkList(TLO.New.Val); 174 175 // Nodes can end up on the worklist more than once. Make sure we do 176 // not process a node that has been replaced. 177 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 178 removeFromWorkList(NowDead[i]); 179 180 // Finally, if the node is now dead, remove it from the graph. The node 181 // may not be dead if the replacement process recursively simplified to 182 // something else needing this node. 183 if (TLO.Old.Val->use_empty()) { 184 removeFromWorkList(TLO.Old.Val); 185 DAG.DeleteNode(TLO.Old.Val); 186 } 187 return true; 188 } 189 190 bool CombineToPreIndexedLoadStore(SDNode *N); 191 bool CombineToPostIndexedLoadStore(SDNode *N); 192 193 194 /// visit - call the node-specific routine that knows how to fold each 195 /// particular type of node. 196 SDOperand visit(SDNode *N); 197 198 // Visitation implementation - Implement dag node combining for different 199 // node types. The semantics are as follows: 200 // Return Value: 201 // SDOperand.Val == 0 - No change was made 202 // SDOperand.Val == N - N was replaced, is dead, and is already handled. 203 // otherwise - N should be replaced by the returned Operand. 204 // 205 SDOperand visitTokenFactor(SDNode *N); 206 SDOperand visitADD(SDNode *N); 207 SDOperand visitSUB(SDNode *N); 208 SDOperand visitADDC(SDNode *N); 209 SDOperand visitADDE(SDNode *N); 210 SDOperand visitMUL(SDNode *N); 211 SDOperand visitSDIV(SDNode *N); 212 SDOperand visitUDIV(SDNode *N); 213 SDOperand visitSREM(SDNode *N); 214 SDOperand visitUREM(SDNode *N); 215 SDOperand visitMULHU(SDNode *N); 216 SDOperand visitMULHS(SDNode *N); 217 SDOperand visitAND(SDNode *N); 218 SDOperand visitOR(SDNode *N); 219 SDOperand visitXOR(SDNode *N); 220 SDOperand visitVBinOp(SDNode *N, ISD::NodeType IntOp, ISD::NodeType FPOp); 221 SDOperand visitSHL(SDNode *N); 222 SDOperand visitSRA(SDNode *N); 223 SDOperand visitSRL(SDNode *N); 224 SDOperand visitCTLZ(SDNode *N); 225 SDOperand visitCTTZ(SDNode *N); 226 SDOperand visitCTPOP(SDNode *N); 227 SDOperand visitSELECT(SDNode *N); 228 SDOperand visitSELECT_CC(SDNode *N); 229 SDOperand visitSETCC(SDNode *N); 230 SDOperand visitSIGN_EXTEND(SDNode *N); 231 SDOperand visitZERO_EXTEND(SDNode *N); 232 SDOperand visitANY_EXTEND(SDNode *N); 233 SDOperand visitSIGN_EXTEND_INREG(SDNode *N); 234 SDOperand visitTRUNCATE(SDNode *N); 235 SDOperand visitBIT_CONVERT(SDNode *N); 236 SDOperand visitVBIT_CONVERT(SDNode *N); 237 SDOperand visitFADD(SDNode *N); 238 SDOperand visitFSUB(SDNode *N); 239 SDOperand visitFMUL(SDNode *N); 240 SDOperand visitFDIV(SDNode *N); 241 SDOperand visitFREM(SDNode *N); 242 SDOperand visitFCOPYSIGN(SDNode *N); 243 SDOperand visitSINT_TO_FP(SDNode *N); 244 SDOperand visitUINT_TO_FP(SDNode *N); 245 SDOperand visitFP_TO_SINT(SDNode *N); 246 SDOperand visitFP_TO_UINT(SDNode *N); 247 SDOperand visitFP_ROUND(SDNode *N); 248 SDOperand visitFP_ROUND_INREG(SDNode *N); 249 SDOperand visitFP_EXTEND(SDNode *N); 250 SDOperand visitFNEG(SDNode *N); 251 SDOperand visitFABS(SDNode *N); 252 SDOperand visitBRCOND(SDNode *N); 253 SDOperand visitBR_CC(SDNode *N); 254 SDOperand visitLOAD(SDNode *N); 255 SDOperand visitSTORE(SDNode *N); 256 SDOperand visitINSERT_VECTOR_ELT(SDNode *N); 257 SDOperand visitVINSERT_VECTOR_ELT(SDNode *N); 258 SDOperand visitVBUILD_VECTOR(SDNode *N); 259 SDOperand visitVECTOR_SHUFFLE(SDNode *N); 260 SDOperand visitVVECTOR_SHUFFLE(SDNode *N); 261 262 SDOperand XformToShuffleWithZero(SDNode *N); 263 SDOperand ReassociateOps(unsigned Opc, SDOperand LHS, SDOperand RHS); 264 265 bool SimplifySelectOps(SDNode *SELECT, SDOperand LHS, SDOperand RHS); 266 SDOperand SimplifyBinOpWithSameOpcodeHands(SDNode *N); 267 SDOperand SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2); 268 SDOperand SimplifySelectCC(SDOperand N0, SDOperand N1, SDOperand N2, 269 SDOperand N3, ISD::CondCode CC); 270 SDOperand SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1, 271 ISD::CondCode Cond, bool foldBooleans = true); 272 SDOperand ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(SDNode *, MVT::ValueType); 273 SDOperand BuildSDIV(SDNode *N); 274 SDOperand BuildUDIV(SDNode *N); 275 SDNode *MatchRotate(SDOperand LHS, SDOperand RHS); 276 277 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 278 /// looking for aliasing nodes and adding them to the Aliases vector. 279 void GatherAllAliases(SDNode *N, SDOperand OriginalChain, 280 SmallVector<SDOperand, 8> &Aliases); 281 282 /// isAlias - Return true if there is any possibility that the two addresses 283 /// overlap. 284 bool isAlias(SDOperand Ptr1, int64_t Size1, 285 const Value *SrcValue1, int SrcValueOffset1, 286 SDOperand Ptr2, int64_t Size2, 287 const Value *SrcValue2, int SrcValueOffset2); 288 289 /// FindAliasInfo - Extracts the relevant alias information from the memory 290 /// node. Returns true if the operand was a load. 291 bool FindAliasInfo(SDNode *N, 292 SDOperand &Ptr, int64_t &Size, 293 const Value *&SrcValue, int &SrcValueOffset); 294 295 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, 296 /// looking for a better chain (aliasing node.) 297 SDOperand FindBetterChain(SDNode *N, SDOperand Chain); 298 299public: 300 DAGCombiner(SelectionDAG &D, AliasAnalysis &A) 301 : DAG(D), 302 TLI(D.getTargetLoweringInfo()), 303 AfterLegalize(false), 304 AA(A) {} 305 306 /// Run - runs the dag combiner on all nodes in the work list 307 void Run(bool RunningAfterLegalize); 308 }; 309} 310 311//===----------------------------------------------------------------------===// 312// TargetLowering::DAGCombinerInfo implementation 313//===----------------------------------------------------------------------===// 314 315void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) { 316 ((DAGCombiner*)DC)->AddToWorkList(N); 317} 318 319SDOperand TargetLowering::DAGCombinerInfo:: 320CombineTo(SDNode *N, const std::vector<SDOperand> &To) { 321 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size()); 322} 323 324SDOperand TargetLowering::DAGCombinerInfo:: 325CombineTo(SDNode *N, SDOperand Res) { 326 return ((DAGCombiner*)DC)->CombineTo(N, Res); 327} 328 329 330SDOperand TargetLowering::DAGCombinerInfo:: 331CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1) { 332 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1); 333} 334 335 336 337 338//===----------------------------------------------------------------------===// 339 340 341// isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc 342// that selects between the values 1 and 0, making it equivalent to a setcc. 343// Also, set the incoming LHS, RHS, and CC references to the appropriate 344// nodes based on the type of node we are checking. This simplifies life a 345// bit for the callers. 346static bool isSetCCEquivalent(SDOperand N, SDOperand &LHS, SDOperand &RHS, 347 SDOperand &CC) { 348 if (N.getOpcode() == ISD::SETCC) { 349 LHS = N.getOperand(0); 350 RHS = N.getOperand(1); 351 CC = N.getOperand(2); 352 return true; 353 } 354 if (N.getOpcode() == ISD::SELECT_CC && 355 N.getOperand(2).getOpcode() == ISD::Constant && 356 N.getOperand(3).getOpcode() == ISD::Constant && 357 cast<ConstantSDNode>(N.getOperand(2))->getValue() == 1 && 358 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) { 359 LHS = N.getOperand(0); 360 RHS = N.getOperand(1); 361 CC = N.getOperand(4); 362 return true; 363 } 364 return false; 365} 366 367// isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only 368// one use. If this is true, it allows the users to invert the operation for 369// free when it is profitable to do so. 370static bool isOneUseSetCC(SDOperand N) { 371 SDOperand N0, N1, N2; 372 if (isSetCCEquivalent(N, N0, N1, N2) && N.Val->hasOneUse()) 373 return true; 374 return false; 375} 376 377SDOperand DAGCombiner::ReassociateOps(unsigned Opc, SDOperand N0, SDOperand N1){ 378 MVT::ValueType VT = N0.getValueType(); 379 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use 380 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2)) 381 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) { 382 if (isa<ConstantSDNode>(N1)) { 383 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(1), N1); 384 AddToWorkList(OpNode.Val); 385 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(0)); 386 } else if (N0.hasOneUse()) { 387 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(0), N1); 388 AddToWorkList(OpNode.Val); 389 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(1)); 390 } 391 } 392 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use 393 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2)) 394 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) { 395 if (isa<ConstantSDNode>(N0)) { 396 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(1), N0); 397 AddToWorkList(OpNode.Val); 398 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(0)); 399 } else if (N1.hasOneUse()) { 400 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(0), N0); 401 AddToWorkList(OpNode.Val); 402 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(1)); 403 } 404 } 405 return SDOperand(); 406} 407 408void DAGCombiner::Run(bool RunningAfterLegalize) { 409 // set the instance variable, so that the various visit routines may use it. 410 AfterLegalize = RunningAfterLegalize; 411 412 // Add all the dag nodes to the worklist. 413 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 414 E = DAG.allnodes_end(); I != E; ++I) 415 WorkList.push_back(I); 416 417 // Create a dummy node (which is not added to allnodes), that adds a reference 418 // to the root node, preventing it from being deleted, and tracking any 419 // changes of the root. 420 HandleSDNode Dummy(DAG.getRoot()); 421 422 // The root of the dag may dangle to deleted nodes until the dag combiner is 423 // done. Set it to null to avoid confusion. 424 DAG.setRoot(SDOperand()); 425 426 /// DagCombineInfo - Expose the DAG combiner to the target combiner impls. 427 TargetLowering::DAGCombinerInfo 428 DagCombineInfo(DAG, !RunningAfterLegalize, false, this); 429 430 // while the worklist isn't empty, inspect the node on the end of it and 431 // try and combine it. 432 while (!WorkList.empty()) { 433 SDNode *N = WorkList.back(); 434 WorkList.pop_back(); 435 436 // If N has no uses, it is dead. Make sure to revisit all N's operands once 437 // N is deleted from the DAG, since they too may now be dead or may have a 438 // reduced number of uses, allowing other xforms. 439 if (N->use_empty() && N != &Dummy) { 440 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 441 AddToWorkList(N->getOperand(i).Val); 442 443 DAG.DeleteNode(N); 444 continue; 445 } 446 447 SDOperand RV = visit(N); 448 449 // If nothing happened, try a target-specific DAG combine. 450 if (RV.Val == 0) { 451 assert(N->getOpcode() != ISD::DELETED_NODE && 452 "Node was deleted but visit returned NULL!"); 453 if (N->getOpcode() >= ISD::BUILTIN_OP_END || 454 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) 455 RV = TLI.PerformDAGCombine(N, DagCombineInfo); 456 } 457 458 if (RV.Val) { 459 ++NodesCombined; 460 // If we get back the same node we passed in, rather than a new node or 461 // zero, we know that the node must have defined multiple values and 462 // CombineTo was used. Since CombineTo takes care of the worklist 463 // mechanics for us, we have no work to do in this case. 464 if (RV.Val != N) { 465 assert(N->getOpcode() != ISD::DELETED_NODE && 466 RV.Val->getOpcode() != ISD::DELETED_NODE && 467 "Node was deleted but visit returned new node!"); 468 469 DOUT << "\nReplacing.3 "; DEBUG(N->dump()); 470 DOUT << "\nWith: "; DEBUG(RV.Val->dump(&DAG)); 471 DOUT << '\n'; 472 std::vector<SDNode*> NowDead; 473 if (N->getNumValues() == RV.Val->getNumValues()) 474 DAG.ReplaceAllUsesWith(N, RV.Val, &NowDead); 475 else { 476 assert(N->getValueType(0) == RV.getValueType() && "Type mismatch"); 477 SDOperand OpV = RV; 478 DAG.ReplaceAllUsesWith(N, &OpV, &NowDead); 479 } 480 481 // Push the new node and any users onto the worklist 482 AddToWorkList(RV.Val); 483 AddUsersToWorkList(RV.Val); 484 485 // Nodes can be reintroduced into the worklist. Make sure we do not 486 // process a node that has been replaced. 487 removeFromWorkList(N); 488 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 489 removeFromWorkList(NowDead[i]); 490 491 // Finally, since the node is now dead, remove it from the graph. 492 DAG.DeleteNode(N); 493 } 494 } 495 } 496 497 // If the root changed (e.g. it was a dead load, update the root). 498 DAG.setRoot(Dummy.getValue()); 499} 500 501SDOperand DAGCombiner::visit(SDNode *N) { 502 switch(N->getOpcode()) { 503 default: break; 504 case ISD::TokenFactor: return visitTokenFactor(N); 505 case ISD::ADD: return visitADD(N); 506 case ISD::SUB: return visitSUB(N); 507 case ISD::ADDC: return visitADDC(N); 508 case ISD::ADDE: return visitADDE(N); 509 case ISD::MUL: return visitMUL(N); 510 case ISD::SDIV: return visitSDIV(N); 511 case ISD::UDIV: return visitUDIV(N); 512 case ISD::SREM: return visitSREM(N); 513 case ISD::UREM: return visitUREM(N); 514 case ISD::MULHU: return visitMULHU(N); 515 case ISD::MULHS: return visitMULHS(N); 516 case ISD::AND: return visitAND(N); 517 case ISD::OR: return visitOR(N); 518 case ISD::XOR: return visitXOR(N); 519 case ISD::SHL: return visitSHL(N); 520 case ISD::SRA: return visitSRA(N); 521 case ISD::SRL: return visitSRL(N); 522 case ISD::CTLZ: return visitCTLZ(N); 523 case ISD::CTTZ: return visitCTTZ(N); 524 case ISD::CTPOP: return visitCTPOP(N); 525 case ISD::SELECT: return visitSELECT(N); 526 case ISD::SELECT_CC: return visitSELECT_CC(N); 527 case ISD::SETCC: return visitSETCC(N); 528 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N); 529 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N); 530 case ISD::ANY_EXTEND: return visitANY_EXTEND(N); 531 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N); 532 case ISD::TRUNCATE: return visitTRUNCATE(N); 533 case ISD::BIT_CONVERT: return visitBIT_CONVERT(N); 534 case ISD::VBIT_CONVERT: return visitVBIT_CONVERT(N); 535 case ISD::FADD: return visitFADD(N); 536 case ISD::FSUB: return visitFSUB(N); 537 case ISD::FMUL: return visitFMUL(N); 538 case ISD::FDIV: return visitFDIV(N); 539 case ISD::FREM: return visitFREM(N); 540 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N); 541 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N); 542 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N); 543 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N); 544 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N); 545 case ISD::FP_ROUND: return visitFP_ROUND(N); 546 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N); 547 case ISD::FP_EXTEND: return visitFP_EXTEND(N); 548 case ISD::FNEG: return visitFNEG(N); 549 case ISD::FABS: return visitFABS(N); 550 case ISD::BRCOND: return visitBRCOND(N); 551 case ISD::BR_CC: return visitBR_CC(N); 552 case ISD::LOAD: return visitLOAD(N); 553 case ISD::STORE: return visitSTORE(N); 554 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N); 555 case ISD::VINSERT_VECTOR_ELT: return visitVINSERT_VECTOR_ELT(N); 556 case ISD::VBUILD_VECTOR: return visitVBUILD_VECTOR(N); 557 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N); 558 case ISD::VVECTOR_SHUFFLE: return visitVVECTOR_SHUFFLE(N); 559 case ISD::VADD: return visitVBinOp(N, ISD::ADD , ISD::FADD); 560 case ISD::VSUB: return visitVBinOp(N, ISD::SUB , ISD::FSUB); 561 case ISD::VMUL: return visitVBinOp(N, ISD::MUL , ISD::FMUL); 562 case ISD::VSDIV: return visitVBinOp(N, ISD::SDIV, ISD::FDIV); 563 case ISD::VUDIV: return visitVBinOp(N, ISD::UDIV, ISD::UDIV); 564 case ISD::VAND: return visitVBinOp(N, ISD::AND , ISD::AND); 565 case ISD::VOR: return visitVBinOp(N, ISD::OR , ISD::OR); 566 case ISD::VXOR: return visitVBinOp(N, ISD::XOR , ISD::XOR); 567 } 568 return SDOperand(); 569} 570 571/// getInputChainForNode - Given a node, return its input chain if it has one, 572/// otherwise return a null sd operand. 573static SDOperand getInputChainForNode(SDNode *N) { 574 if (unsigned NumOps = N->getNumOperands()) { 575 if (N->getOperand(0).getValueType() == MVT::Other) 576 return N->getOperand(0); 577 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other) 578 return N->getOperand(NumOps-1); 579 for (unsigned i = 1; i < NumOps-1; ++i) 580 if (N->getOperand(i).getValueType() == MVT::Other) 581 return N->getOperand(i); 582 } 583 return SDOperand(0, 0); 584} 585 586SDOperand DAGCombiner::visitTokenFactor(SDNode *N) { 587 // If N has two operands, where one has an input chain equal to the other, 588 // the 'other' chain is redundant. 589 if (N->getNumOperands() == 2) { 590 if (getInputChainForNode(N->getOperand(0).Val) == N->getOperand(1)) 591 return N->getOperand(0); 592 if (getInputChainForNode(N->getOperand(1).Val) == N->getOperand(0)) 593 return N->getOperand(1); 594 } 595 596 597 SmallVector<SDNode *, 8> TFs; // List of token factors to visit. 598 SmallVector<SDOperand, 8> Ops; // Ops for replacing token factor. 599 bool Changed = false; // If we should replace this token factor. 600 601 // Start out with this token factor. 602 TFs.push_back(N); 603 604 // Iterate through token factors. The TFs grows when new token factors are 605 // encountered. 606 for (unsigned i = 0; i < TFs.size(); ++i) { 607 SDNode *TF = TFs[i]; 608 609 // Check each of the operands. 610 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) { 611 SDOperand Op = TF->getOperand(i); 612 613 switch (Op.getOpcode()) { 614 case ISD::EntryToken: 615 // Entry tokens don't need to be added to the list. They are 616 // rededundant. 617 Changed = true; 618 break; 619 620 case ISD::TokenFactor: 621 if ((CombinerAA || Op.hasOneUse()) && 622 std::find(TFs.begin(), TFs.end(), Op.Val) == TFs.end()) { 623 // Queue up for processing. 624 TFs.push_back(Op.Val); 625 // Clean up in case the token factor is removed. 626 AddToWorkList(Op.Val); 627 Changed = true; 628 break; 629 } 630 // Fall thru 631 632 default: 633 // Only add if not there prior. 634 if (std::find(Ops.begin(), Ops.end(), Op) == Ops.end()) 635 Ops.push_back(Op); 636 break; 637 } 638 } 639 } 640 641 SDOperand Result; 642 643 // If we've change things around then replace token factor. 644 if (Changed) { 645 if (Ops.size() == 0) { 646 // The entry token is the only possible outcome. 647 Result = DAG.getEntryNode(); 648 } else { 649 // New and improved token factor. 650 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, &Ops[0], Ops.size()); 651 } 652 653 // Don't add users to work list. 654 return CombineTo(N, Result, false); 655 } 656 657 return Result; 658} 659 660static 661SDOperand combineShlAddConstant(SDOperand N0, SDOperand N1, SelectionDAG &DAG) { 662 MVT::ValueType VT = N0.getValueType(); 663 SDOperand N00 = N0.getOperand(0); 664 SDOperand N01 = N0.getOperand(1); 665 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01); 666 if (N01C && N00.getOpcode() == ISD::ADD && N00.Val->hasOneUse() && 667 isa<ConstantSDNode>(N00.getOperand(1))) { 668 N0 = DAG.getNode(ISD::ADD, VT, 669 DAG.getNode(ISD::SHL, VT, N00.getOperand(0), N01), 670 DAG.getNode(ISD::SHL, VT, N00.getOperand(1), N01)); 671 return DAG.getNode(ISD::ADD, VT, N0, N1); 672 } 673 return SDOperand(); 674} 675 676SDOperand DAGCombiner::visitADD(SDNode *N) { 677 SDOperand N0 = N->getOperand(0); 678 SDOperand N1 = N->getOperand(1); 679 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 680 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 681 MVT::ValueType VT = N0.getValueType(); 682 683 // fold (add c1, c2) -> c1+c2 684 if (N0C && N1C) 685 return DAG.getNode(ISD::ADD, VT, N0, N1); 686 // canonicalize constant to RHS 687 if (N0C && !N1C) 688 return DAG.getNode(ISD::ADD, VT, N1, N0); 689 // fold (add x, 0) -> x 690 if (N1C && N1C->isNullValue()) 691 return N0; 692 // fold ((c1-A)+c2) -> (c1+c2)-A 693 if (N1C && N0.getOpcode() == ISD::SUB) 694 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0))) 695 return DAG.getNode(ISD::SUB, VT, 696 DAG.getConstant(N1C->getValue()+N0C->getValue(), VT), 697 N0.getOperand(1)); 698 // reassociate add 699 SDOperand RADD = ReassociateOps(ISD::ADD, N0, N1); 700 if (RADD.Val != 0) 701 return RADD; 702 // fold ((0-A) + B) -> B-A 703 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) && 704 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue()) 705 return DAG.getNode(ISD::SUB, VT, N1, N0.getOperand(1)); 706 // fold (A + (0-B)) -> A-B 707 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) && 708 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue()) 709 return DAG.getNode(ISD::SUB, VT, N0, N1.getOperand(1)); 710 // fold (A+(B-A)) -> B 711 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1)) 712 return N1.getOperand(0); 713 714 if (!MVT::isVector(VT) && SimplifyDemandedBits(SDOperand(N, 0))) 715 return SDOperand(N, 0); 716 717 // fold (a+b) -> (a|b) iff a and b share no bits. 718 if (MVT::isInteger(VT) && !MVT::isVector(VT)) { 719 uint64_t LHSZero, LHSOne; 720 uint64_t RHSZero, RHSOne; 721 uint64_t Mask = MVT::getIntVTBitMask(VT); 722 TLI.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 723 if (LHSZero) { 724 TLI.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 725 726 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 727 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 728 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 729 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 730 return DAG.getNode(ISD::OR, VT, N0, N1); 731 } 732 } 733 734 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 735 if (N0.getOpcode() == ISD::SHL && N0.Val->hasOneUse()) { 736 SDOperand Result = combineShlAddConstant(N0, N1, DAG); 737 if (Result.Val) return Result; 738 } 739 if (N1.getOpcode() == ISD::SHL && N1.Val->hasOneUse()) { 740 SDOperand Result = combineShlAddConstant(N1, N0, DAG); 741 if (Result.Val) return Result; 742 } 743 744 return SDOperand(); 745} 746 747SDOperand DAGCombiner::visitADDC(SDNode *N) { 748 SDOperand N0 = N->getOperand(0); 749 SDOperand N1 = N->getOperand(1); 750 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 751 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 752 MVT::ValueType VT = N0.getValueType(); 753 754 // If the flag result is dead, turn this into an ADD. 755 if (N->hasNUsesOfValue(0, 1)) 756 return CombineTo(N, DAG.getNode(ISD::ADD, VT, N1, N0), 757 SDOperand(N, 1)); 758 759 // canonicalize constant to RHS. 760 if (N0C && !N1C) 761 return DAG.getNode(ISD::ADDC, VT, N1, N0); 762 763 // fold (add x, 0) -> x + no carry out 764 //if (N1C && N1C->isNullValue()) 765 // return N0; 766 767 return SDOperand(); 768} 769 770SDOperand DAGCombiner::visitADDE(SDNode *N) { 771 SDOperand N0 = N->getOperand(0); 772 SDOperand N1 = N->getOperand(1); 773 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 774 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 775 MVT::ValueType VT = N0.getValueType(); 776 777 // canonicalize constant to RHS 778 if (N0C && !N1C) 779 return DAG.getNode(ISD::ADDE, VT, N1, N0, N->getOperand(2)); 780 781 // fold (add x, 0) -> x 782 //if (N1C && N1C->isNullValue()) 783 // return N0; 784 785 return SDOperand(); 786} 787 788 789 790SDOperand DAGCombiner::visitSUB(SDNode *N) { 791 SDOperand N0 = N->getOperand(0); 792 SDOperand N1 = N->getOperand(1); 793 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 794 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 795 MVT::ValueType VT = N0.getValueType(); 796 797 // fold (sub x, x) -> 0 798 if (N0 == N1) 799 return DAG.getConstant(0, N->getValueType(0)); 800 // fold (sub c1, c2) -> c1-c2 801 if (N0C && N1C) 802 return DAG.getNode(ISD::SUB, VT, N0, N1); 803 // fold (sub x, c) -> (add x, -c) 804 if (N1C) 805 return DAG.getNode(ISD::ADD, VT, N0, DAG.getConstant(-N1C->getValue(), VT)); 806 // fold (A+B)-A -> B 807 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1) 808 return N0.getOperand(1); 809 // fold (A+B)-B -> A 810 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1) 811 return N0.getOperand(0); 812 return SDOperand(); 813} 814 815SDOperand DAGCombiner::visitMUL(SDNode *N) { 816 SDOperand N0 = N->getOperand(0); 817 SDOperand N1 = N->getOperand(1); 818 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 819 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 820 MVT::ValueType VT = N0.getValueType(); 821 822 // fold (mul c1, c2) -> c1*c2 823 if (N0C && N1C) 824 return DAG.getNode(ISD::MUL, VT, N0, N1); 825 // canonicalize constant to RHS 826 if (N0C && !N1C) 827 return DAG.getNode(ISD::MUL, VT, N1, N0); 828 // fold (mul x, 0) -> 0 829 if (N1C && N1C->isNullValue()) 830 return N1; 831 // fold (mul x, -1) -> 0-x 832 if (N1C && N1C->isAllOnesValue()) 833 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0); 834 // fold (mul x, (1 << c)) -> x << c 835 if (N1C && isPowerOf2_64(N1C->getValue())) 836 return DAG.getNode(ISD::SHL, VT, N0, 837 DAG.getConstant(Log2_64(N1C->getValue()), 838 TLI.getShiftAmountTy())); 839 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c 840 if (N1C && isPowerOf2_64(-N1C->getSignExtended())) { 841 // FIXME: If the input is something that is easily negated (e.g. a 842 // single-use add), we should put the negate there. 843 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), 844 DAG.getNode(ISD::SHL, VT, N0, 845 DAG.getConstant(Log2_64(-N1C->getSignExtended()), 846 TLI.getShiftAmountTy()))); 847 } 848 849 // (mul (shl X, c1), c2) -> (mul X, c2 << c1) 850 if (N1C && N0.getOpcode() == ISD::SHL && 851 isa<ConstantSDNode>(N0.getOperand(1))) { 852 SDOperand C3 = DAG.getNode(ISD::SHL, VT, N1, N0.getOperand(1)); 853 AddToWorkList(C3.Val); 854 return DAG.getNode(ISD::MUL, VT, N0.getOperand(0), C3); 855 } 856 857 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one 858 // use. 859 { 860 SDOperand Sh(0,0), Y(0,0); 861 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)). 862 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) && 863 N0.Val->hasOneUse()) { 864 Sh = N0; Y = N1; 865 } else if (N1.getOpcode() == ISD::SHL && 866 isa<ConstantSDNode>(N1.getOperand(1)) && N1.Val->hasOneUse()) { 867 Sh = N1; Y = N0; 868 } 869 if (Sh.Val) { 870 SDOperand Mul = DAG.getNode(ISD::MUL, VT, Sh.getOperand(0), Y); 871 return DAG.getNode(ISD::SHL, VT, Mul, Sh.getOperand(1)); 872 } 873 } 874 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2) 875 if (N1C && N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse() && 876 isa<ConstantSDNode>(N0.getOperand(1))) { 877 return DAG.getNode(ISD::ADD, VT, 878 DAG.getNode(ISD::MUL, VT, N0.getOperand(0), N1), 879 DAG.getNode(ISD::MUL, VT, N0.getOperand(1), N1)); 880 } 881 882 // reassociate mul 883 SDOperand RMUL = ReassociateOps(ISD::MUL, N0, N1); 884 if (RMUL.Val != 0) 885 return RMUL; 886 return SDOperand(); 887} 888 889SDOperand DAGCombiner::visitSDIV(SDNode *N) { 890 SDOperand N0 = N->getOperand(0); 891 SDOperand N1 = N->getOperand(1); 892 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 893 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 894 MVT::ValueType VT = N->getValueType(0); 895 896 // fold (sdiv c1, c2) -> c1/c2 897 if (N0C && N1C && !N1C->isNullValue()) 898 return DAG.getNode(ISD::SDIV, VT, N0, N1); 899 // fold (sdiv X, 1) -> X 900 if (N1C && N1C->getSignExtended() == 1LL) 901 return N0; 902 // fold (sdiv X, -1) -> 0-X 903 if (N1C && N1C->isAllOnesValue()) 904 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0); 905 // If we know the sign bits of both operands are zero, strength reduce to a 906 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2 907 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1); 908 if (TLI.MaskedValueIsZero(N1, SignBit) && 909 TLI.MaskedValueIsZero(N0, SignBit)) 910 return DAG.getNode(ISD::UDIV, N1.getValueType(), N0, N1); 911 // fold (sdiv X, pow2) -> simple ops after legalize 912 if (N1C && N1C->getValue() && !TLI.isIntDivCheap() && 913 (isPowerOf2_64(N1C->getSignExtended()) || 914 isPowerOf2_64(-N1C->getSignExtended()))) { 915 // If dividing by powers of two is cheap, then don't perform the following 916 // fold. 917 if (TLI.isPow2DivCheap()) 918 return SDOperand(); 919 int64_t pow2 = N1C->getSignExtended(); 920 int64_t abs2 = pow2 > 0 ? pow2 : -pow2; 921 unsigned lg2 = Log2_64(abs2); 922 // Splat the sign bit into the register 923 SDOperand SGN = DAG.getNode(ISD::SRA, VT, N0, 924 DAG.getConstant(MVT::getSizeInBits(VT)-1, 925 TLI.getShiftAmountTy())); 926 AddToWorkList(SGN.Val); 927 // Add (N0 < 0) ? abs2 - 1 : 0; 928 SDOperand SRL = DAG.getNode(ISD::SRL, VT, SGN, 929 DAG.getConstant(MVT::getSizeInBits(VT)-lg2, 930 TLI.getShiftAmountTy())); 931 SDOperand ADD = DAG.getNode(ISD::ADD, VT, N0, SRL); 932 AddToWorkList(SRL.Val); 933 AddToWorkList(ADD.Val); // Divide by pow2 934 SDOperand SRA = DAG.getNode(ISD::SRA, VT, ADD, 935 DAG.getConstant(lg2, TLI.getShiftAmountTy())); 936 // If we're dividing by a positive value, we're done. Otherwise, we must 937 // negate the result. 938 if (pow2 > 0) 939 return SRA; 940 AddToWorkList(SRA.Val); 941 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), SRA); 942 } 943 // if integer divide is expensive and we satisfy the requirements, emit an 944 // alternate sequence. 945 if (N1C && (N1C->getSignExtended() < -1 || N1C->getSignExtended() > 1) && 946 !TLI.isIntDivCheap()) { 947 SDOperand Op = BuildSDIV(N); 948 if (Op.Val) return Op; 949 } 950 return SDOperand(); 951} 952 953SDOperand DAGCombiner::visitUDIV(SDNode *N) { 954 SDOperand N0 = N->getOperand(0); 955 SDOperand N1 = N->getOperand(1); 956 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 957 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 958 MVT::ValueType VT = N->getValueType(0); 959 960 // fold (udiv c1, c2) -> c1/c2 961 if (N0C && N1C && !N1C->isNullValue()) 962 return DAG.getNode(ISD::UDIV, VT, N0, N1); 963 // fold (udiv x, (1 << c)) -> x >>u c 964 if (N1C && isPowerOf2_64(N1C->getValue())) 965 return DAG.getNode(ISD::SRL, VT, N0, 966 DAG.getConstant(Log2_64(N1C->getValue()), 967 TLI.getShiftAmountTy())); 968 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2 969 if (N1.getOpcode() == ISD::SHL) { 970 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 971 if (isPowerOf2_64(SHC->getValue())) { 972 MVT::ValueType ADDVT = N1.getOperand(1).getValueType(); 973 SDOperand Add = DAG.getNode(ISD::ADD, ADDVT, N1.getOperand(1), 974 DAG.getConstant(Log2_64(SHC->getValue()), 975 ADDVT)); 976 AddToWorkList(Add.Val); 977 return DAG.getNode(ISD::SRL, VT, N0, Add); 978 } 979 } 980 } 981 // fold (udiv x, c) -> alternate 982 if (N1C && N1C->getValue() && !TLI.isIntDivCheap()) { 983 SDOperand Op = BuildUDIV(N); 984 if (Op.Val) return Op; 985 } 986 return SDOperand(); 987} 988 989SDOperand DAGCombiner::visitSREM(SDNode *N) { 990 SDOperand N0 = N->getOperand(0); 991 SDOperand N1 = N->getOperand(1); 992 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 993 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 994 MVT::ValueType VT = N->getValueType(0); 995 996 // fold (srem c1, c2) -> c1%c2 997 if (N0C && N1C && !N1C->isNullValue()) 998 return DAG.getNode(ISD::SREM, VT, N0, N1); 999 // If we know the sign bits of both operands are zero, strength reduce to a 1000 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15 1001 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1); 1002 if (TLI.MaskedValueIsZero(N1, SignBit) && 1003 TLI.MaskedValueIsZero(N0, SignBit)) 1004 return DAG.getNode(ISD::UREM, VT, N0, N1); 1005 1006 // Unconditionally lower X%C -> X-X/C*C. This allows the X/C logic to hack on 1007 // the remainder operation. 1008 if (N1C && !N1C->isNullValue()) { 1009 SDOperand Div = DAG.getNode(ISD::SDIV, VT, N0, N1); 1010 SDOperand Mul = DAG.getNode(ISD::MUL, VT, Div, N1); 1011 SDOperand Sub = DAG.getNode(ISD::SUB, VT, N0, Mul); 1012 AddToWorkList(Div.Val); 1013 AddToWorkList(Mul.Val); 1014 return Sub; 1015 } 1016 1017 return SDOperand(); 1018} 1019 1020SDOperand DAGCombiner::visitUREM(SDNode *N) { 1021 SDOperand N0 = N->getOperand(0); 1022 SDOperand N1 = N->getOperand(1); 1023 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1024 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1025 MVT::ValueType VT = N->getValueType(0); 1026 1027 // fold (urem c1, c2) -> c1%c2 1028 if (N0C && N1C && !N1C->isNullValue()) 1029 return DAG.getNode(ISD::UREM, VT, N0, N1); 1030 // fold (urem x, pow2) -> (and x, pow2-1) 1031 if (N1C && !N1C->isNullValue() && isPowerOf2_64(N1C->getValue())) 1032 return DAG.getNode(ISD::AND, VT, N0, DAG.getConstant(N1C->getValue()-1,VT)); 1033 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1)) 1034 if (N1.getOpcode() == ISD::SHL) { 1035 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1036 if (isPowerOf2_64(SHC->getValue())) { 1037 SDOperand Add = DAG.getNode(ISD::ADD, VT, N1,DAG.getConstant(~0ULL,VT)); 1038 AddToWorkList(Add.Val); 1039 return DAG.getNode(ISD::AND, VT, N0, Add); 1040 } 1041 } 1042 } 1043 1044 // Unconditionally lower X%C -> X-X/C*C. This allows the X/C logic to hack on 1045 // the remainder operation. 1046 if (N1C && !N1C->isNullValue()) { 1047 SDOperand Div = DAG.getNode(ISD::UDIV, VT, N0, N1); 1048 SDOperand Mul = DAG.getNode(ISD::MUL, VT, Div, N1); 1049 SDOperand Sub = DAG.getNode(ISD::SUB, VT, N0, Mul); 1050 AddToWorkList(Div.Val); 1051 AddToWorkList(Mul.Val); 1052 return Sub; 1053 } 1054 1055 return SDOperand(); 1056} 1057 1058SDOperand DAGCombiner::visitMULHS(SDNode *N) { 1059 SDOperand N0 = N->getOperand(0); 1060 SDOperand N1 = N->getOperand(1); 1061 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1062 1063 // fold (mulhs x, 0) -> 0 1064 if (N1C && N1C->isNullValue()) 1065 return N1; 1066 // fold (mulhs x, 1) -> (sra x, size(x)-1) 1067 if (N1C && N1C->getValue() == 1) 1068 return DAG.getNode(ISD::SRA, N0.getValueType(), N0, 1069 DAG.getConstant(MVT::getSizeInBits(N0.getValueType())-1, 1070 TLI.getShiftAmountTy())); 1071 return SDOperand(); 1072} 1073 1074SDOperand DAGCombiner::visitMULHU(SDNode *N) { 1075 SDOperand N0 = N->getOperand(0); 1076 SDOperand N1 = N->getOperand(1); 1077 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1078 1079 // fold (mulhu x, 0) -> 0 1080 if (N1C && N1C->isNullValue()) 1081 return N1; 1082 // fold (mulhu x, 1) -> 0 1083 if (N1C && N1C->getValue() == 1) 1084 return DAG.getConstant(0, N0.getValueType()); 1085 return SDOperand(); 1086} 1087 1088/// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with 1089/// two operands of the same opcode, try to simplify it. 1090SDOperand DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) { 1091 SDOperand N0 = N->getOperand(0), N1 = N->getOperand(1); 1092 MVT::ValueType VT = N0.getValueType(); 1093 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!"); 1094 1095 // For each of OP in AND/OR/XOR: 1096 // fold (OP (zext x), (zext y)) -> (zext (OP x, y)) 1097 // fold (OP (sext x), (sext y)) -> (sext (OP x, y)) 1098 // fold (OP (aext x), (aext y)) -> (aext (OP x, y)) 1099 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y)) 1100 if ((N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND|| 1101 N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::TRUNCATE) && 1102 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) { 1103 SDOperand ORNode = DAG.getNode(N->getOpcode(), 1104 N0.getOperand(0).getValueType(), 1105 N0.getOperand(0), N1.getOperand(0)); 1106 AddToWorkList(ORNode.Val); 1107 return DAG.getNode(N0.getOpcode(), VT, ORNode); 1108 } 1109 1110 // For each of OP in SHL/SRL/SRA/AND... 1111 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z) 1112 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z) 1113 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z) 1114 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL || 1115 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) && 1116 N0.getOperand(1) == N1.getOperand(1)) { 1117 SDOperand ORNode = DAG.getNode(N->getOpcode(), 1118 N0.getOperand(0).getValueType(), 1119 N0.getOperand(0), N1.getOperand(0)); 1120 AddToWorkList(ORNode.Val); 1121 return DAG.getNode(N0.getOpcode(), VT, ORNode, N0.getOperand(1)); 1122 } 1123 1124 return SDOperand(); 1125} 1126 1127SDOperand DAGCombiner::visitAND(SDNode *N) { 1128 SDOperand N0 = N->getOperand(0); 1129 SDOperand N1 = N->getOperand(1); 1130 SDOperand LL, LR, RL, RR, CC0, CC1; 1131 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1132 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1133 MVT::ValueType VT = N1.getValueType(); 1134 1135 // fold (and c1, c2) -> c1&c2 1136 if (N0C && N1C) 1137 return DAG.getNode(ISD::AND, VT, N0, N1); 1138 // canonicalize constant to RHS 1139 if (N0C && !N1C) 1140 return DAG.getNode(ISD::AND, VT, N1, N0); 1141 // fold (and x, -1) -> x 1142 if (N1C && N1C->isAllOnesValue()) 1143 return N0; 1144 // if (and x, c) is known to be zero, return 0 1145 if (N1C && TLI.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT))) 1146 return DAG.getConstant(0, VT); 1147 // reassociate and 1148 SDOperand RAND = ReassociateOps(ISD::AND, N0, N1); 1149 if (RAND.Val != 0) 1150 return RAND; 1151 // fold (and (or x, 0xFFFF), 0xFF) -> 0xFF 1152 if (N1C && N0.getOpcode() == ISD::OR) 1153 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 1154 if ((ORI->getValue() & N1C->getValue()) == N1C->getValue()) 1155 return N1; 1156 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits. 1157 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 1158 unsigned InMask = MVT::getIntVTBitMask(N0.getOperand(0).getValueType()); 1159 if (TLI.MaskedValueIsZero(N0.getOperand(0), 1160 ~N1C->getValue() & InMask)) { 1161 SDOperand Zext = DAG.getNode(ISD::ZERO_EXTEND, N0.getValueType(), 1162 N0.getOperand(0)); 1163 1164 // Replace uses of the AND with uses of the Zero extend node. 1165 CombineTo(N, Zext); 1166 1167 // We actually want to replace all uses of the any_extend with the 1168 // zero_extend, to avoid duplicating things. This will later cause this 1169 // AND to be folded. 1170 CombineTo(N0.Val, Zext); 1171 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1172 } 1173 } 1174 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y)) 1175 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 1176 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 1177 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 1178 1179 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 1180 MVT::isInteger(LL.getValueType())) { 1181 // fold (X == 0) & (Y == 0) -> (X|Y == 0) 1182 if (cast<ConstantSDNode>(LR)->getValue() == 0 && Op1 == ISD::SETEQ) { 1183 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 1184 AddToWorkList(ORNode.Val); 1185 return DAG.getSetCC(VT, ORNode, LR, Op1); 1186 } 1187 // fold (X == -1) & (Y == -1) -> (X&Y == -1) 1188 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) { 1189 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL); 1190 AddToWorkList(ANDNode.Val); 1191 return DAG.getSetCC(VT, ANDNode, LR, Op1); 1192 } 1193 // fold (X > -1) & (Y > -1) -> (X|Y > -1) 1194 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) { 1195 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 1196 AddToWorkList(ORNode.Val); 1197 return DAG.getSetCC(VT, ORNode, LR, Op1); 1198 } 1199 } 1200 // canonicalize equivalent to ll == rl 1201 if (LL == RR && LR == RL) { 1202 Op1 = ISD::getSetCCSwappedOperands(Op1); 1203 std::swap(RL, RR); 1204 } 1205 if (LL == RL && LR == RR) { 1206 bool isInteger = MVT::isInteger(LL.getValueType()); 1207 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger); 1208 if (Result != ISD::SETCC_INVALID) 1209 return DAG.getSetCC(N0.getValueType(), LL, LR, Result); 1210 } 1211 } 1212 1213 // Simplify: and (op x...), (op y...) -> (op (and x, y)) 1214 if (N0.getOpcode() == N1.getOpcode()) { 1215 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N); 1216 if (Tmp.Val) return Tmp; 1217 } 1218 1219 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1) 1220 // fold (and (sra)) -> (and (srl)) when possible. 1221 if (!MVT::isVector(VT) && 1222 SimplifyDemandedBits(SDOperand(N, 0))) 1223 return SDOperand(N, 0); 1224 // fold (zext_inreg (extload x)) -> (zextload x) 1225 if (ISD::isEXTLoad(N0.Val)) { 1226 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1227 MVT::ValueType EVT = LN0->getLoadedVT(); 1228 // If we zero all the possible extended bits, then we can turn this into 1229 // a zextload if we are running before legalize or the operation is legal. 1230 if (TLI.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) && 1231 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) { 1232 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 1233 LN0->getBasePtr(), LN0->getSrcValue(), 1234 LN0->getSrcValueOffset(), EVT); 1235 AddToWorkList(N); 1236 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 1237 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1238 } 1239 } 1240 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use 1241 if (ISD::isSEXTLoad(N0.Val) && N0.hasOneUse()) { 1242 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1243 MVT::ValueType EVT = LN0->getLoadedVT(); 1244 // If we zero all the possible extended bits, then we can turn this into 1245 // a zextload if we are running before legalize or the operation is legal. 1246 if (TLI.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) && 1247 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) { 1248 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 1249 LN0->getBasePtr(), LN0->getSrcValue(), 1250 LN0->getSrcValueOffset(), EVT); 1251 AddToWorkList(N); 1252 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 1253 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1254 } 1255 } 1256 1257 // fold (and (load x), 255) -> (zextload x, i8) 1258 // fold (and (extload x, i16), 255) -> (zextload x, i8) 1259 if (N1C && N0.getOpcode() == ISD::LOAD) { 1260 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1261 if (LN0->getExtensionType() != ISD::SEXTLOAD && 1262 N0.hasOneUse()) { 1263 MVT::ValueType EVT, LoadedVT; 1264 if (N1C->getValue() == 255) 1265 EVT = MVT::i8; 1266 else if (N1C->getValue() == 65535) 1267 EVT = MVT::i16; 1268 else if (N1C->getValue() == ~0U) 1269 EVT = MVT::i32; 1270 else 1271 EVT = MVT::Other; 1272 1273 LoadedVT = LN0->getLoadedVT(); 1274 if (EVT != MVT::Other && LoadedVT > EVT && 1275 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) { 1276 MVT::ValueType PtrType = N0.getOperand(1).getValueType(); 1277 // For big endian targets, we need to add an offset to the pointer to 1278 // load the correct bytes. For little endian systems, we merely need to 1279 // read fewer bytes from the same pointer. 1280 unsigned PtrOff = 1281 (MVT::getSizeInBits(LoadedVT) - MVT::getSizeInBits(EVT)) / 8; 1282 SDOperand NewPtr = LN0->getBasePtr(); 1283 if (!TLI.isLittleEndian()) 1284 NewPtr = DAG.getNode(ISD::ADD, PtrType, NewPtr, 1285 DAG.getConstant(PtrOff, PtrType)); 1286 AddToWorkList(NewPtr.Val); 1287 SDOperand Load = 1288 DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), NewPtr, 1289 LN0->getSrcValue(), LN0->getSrcValueOffset(), EVT); 1290 AddToWorkList(N); 1291 CombineTo(N0.Val, Load, Load.getValue(1)); 1292 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1293 } 1294 } 1295 } 1296 1297 return SDOperand(); 1298} 1299 1300SDOperand DAGCombiner::visitOR(SDNode *N) { 1301 SDOperand N0 = N->getOperand(0); 1302 SDOperand N1 = N->getOperand(1); 1303 SDOperand LL, LR, RL, RR, CC0, CC1; 1304 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1305 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1306 MVT::ValueType VT = N1.getValueType(); 1307 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 1308 1309 // fold (or c1, c2) -> c1|c2 1310 if (N0C && N1C) 1311 return DAG.getNode(ISD::OR, VT, N0, N1); 1312 // canonicalize constant to RHS 1313 if (N0C && !N1C) 1314 return DAG.getNode(ISD::OR, VT, N1, N0); 1315 // fold (or x, 0) -> x 1316 if (N1C && N1C->isNullValue()) 1317 return N0; 1318 // fold (or x, -1) -> -1 1319 if (N1C && N1C->isAllOnesValue()) 1320 return N1; 1321 // fold (or x, c) -> c iff (x & ~c) == 0 1322 if (N1C && 1323 TLI.MaskedValueIsZero(N0,~N1C->getValue() & (~0ULL>>(64-OpSizeInBits)))) 1324 return N1; 1325 // reassociate or 1326 SDOperand ROR = ReassociateOps(ISD::OR, N0, N1); 1327 if (ROR.Val != 0) 1328 return ROR; 1329 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2) 1330 if (N1C && N0.getOpcode() == ISD::AND && N0.Val->hasOneUse() && 1331 isa<ConstantSDNode>(N0.getOperand(1))) { 1332 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1)); 1333 return DAG.getNode(ISD::AND, VT, DAG.getNode(ISD::OR, VT, N0.getOperand(0), 1334 N1), 1335 DAG.getConstant(N1C->getValue() | C1->getValue(), VT)); 1336 } 1337 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y)) 1338 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 1339 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 1340 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 1341 1342 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 1343 MVT::isInteger(LL.getValueType())) { 1344 // fold (X != 0) | (Y != 0) -> (X|Y != 0) 1345 // fold (X < 0) | (Y < 0) -> (X|Y < 0) 1346 if (cast<ConstantSDNode>(LR)->getValue() == 0 && 1347 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) { 1348 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 1349 AddToWorkList(ORNode.Val); 1350 return DAG.getSetCC(VT, ORNode, LR, Op1); 1351 } 1352 // fold (X != -1) | (Y != -1) -> (X&Y != -1) 1353 // fold (X > -1) | (Y > -1) -> (X&Y > -1) 1354 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && 1355 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) { 1356 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL); 1357 AddToWorkList(ANDNode.Val); 1358 return DAG.getSetCC(VT, ANDNode, LR, Op1); 1359 } 1360 } 1361 // canonicalize equivalent to ll == rl 1362 if (LL == RR && LR == RL) { 1363 Op1 = ISD::getSetCCSwappedOperands(Op1); 1364 std::swap(RL, RR); 1365 } 1366 if (LL == RL && LR == RR) { 1367 bool isInteger = MVT::isInteger(LL.getValueType()); 1368 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger); 1369 if (Result != ISD::SETCC_INVALID) 1370 return DAG.getSetCC(N0.getValueType(), LL, LR, Result); 1371 } 1372 } 1373 1374 // Simplify: or (op x...), (op y...) -> (op (or x, y)) 1375 if (N0.getOpcode() == N1.getOpcode()) { 1376 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N); 1377 if (Tmp.Val) return Tmp; 1378 } 1379 1380 // (X & C1) | (Y & C2) -> (X|Y) & C3 if possible. 1381 if (N0.getOpcode() == ISD::AND && 1382 N1.getOpcode() == ISD::AND && 1383 N0.getOperand(1).getOpcode() == ISD::Constant && 1384 N1.getOperand(1).getOpcode() == ISD::Constant && 1385 // Don't increase # computations. 1386 (N0.Val->hasOneUse() || N1.Val->hasOneUse())) { 1387 // We can only do this xform if we know that bits from X that are set in C2 1388 // but not in C1 are already zero. Likewise for Y. 1389 uint64_t LHSMask = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 1390 uint64_t RHSMask = cast<ConstantSDNode>(N1.getOperand(1))->getValue(); 1391 1392 if (TLI.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) && 1393 TLI.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) { 1394 SDOperand X =DAG.getNode(ISD::OR, VT, N0.getOperand(0), N1.getOperand(0)); 1395 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(LHSMask|RHSMask, VT)); 1396 } 1397 } 1398 1399 1400 // See if this is some rotate idiom. 1401 if (SDNode *Rot = MatchRotate(N0, N1)) 1402 return SDOperand(Rot, 0); 1403 1404 return SDOperand(); 1405} 1406 1407 1408/// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present. 1409static bool MatchRotateHalf(SDOperand Op, SDOperand &Shift, SDOperand &Mask) { 1410 if (Op.getOpcode() == ISD::AND) { 1411 if (isa<ConstantSDNode>(Op.getOperand(1))) { 1412 Mask = Op.getOperand(1); 1413 Op = Op.getOperand(0); 1414 } else { 1415 return false; 1416 } 1417 } 1418 1419 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) { 1420 Shift = Op; 1421 return true; 1422 } 1423 return false; 1424} 1425 1426 1427// MatchRotate - Handle an 'or' of two operands. If this is one of the many 1428// idioms for rotate, and if the target supports rotation instructions, generate 1429// a rot[lr]. 1430SDNode *DAGCombiner::MatchRotate(SDOperand LHS, SDOperand RHS) { 1431 // Must be a legal type. Expanded an promoted things won't work with rotates. 1432 MVT::ValueType VT = LHS.getValueType(); 1433 if (!TLI.isTypeLegal(VT)) return 0; 1434 1435 // The target must have at least one rotate flavor. 1436 bool HasROTL = TLI.isOperationLegal(ISD::ROTL, VT); 1437 bool HasROTR = TLI.isOperationLegal(ISD::ROTR, VT); 1438 if (!HasROTL && !HasROTR) return 0; 1439 1440 // Match "(X shl/srl V1) & V2" where V2 may not be present. 1441 SDOperand LHSShift; // The shift. 1442 SDOperand LHSMask; // AND value if any. 1443 if (!MatchRotateHalf(LHS, LHSShift, LHSMask)) 1444 return 0; // Not part of a rotate. 1445 1446 SDOperand RHSShift; // The shift. 1447 SDOperand RHSMask; // AND value if any. 1448 if (!MatchRotateHalf(RHS, RHSShift, RHSMask)) 1449 return 0; // Not part of a rotate. 1450 1451 if (LHSShift.getOperand(0) != RHSShift.getOperand(0)) 1452 return 0; // Not shifting the same value. 1453 1454 if (LHSShift.getOpcode() == RHSShift.getOpcode()) 1455 return 0; // Shifts must disagree. 1456 1457 // Canonicalize shl to left side in a shl/srl pair. 1458 if (RHSShift.getOpcode() == ISD::SHL) { 1459 std::swap(LHS, RHS); 1460 std::swap(LHSShift, RHSShift); 1461 std::swap(LHSMask , RHSMask ); 1462 } 1463 1464 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 1465 1466 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1) 1467 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2) 1468 if (LHSShift.getOperand(1).getOpcode() == ISD::Constant && 1469 RHSShift.getOperand(1).getOpcode() == ISD::Constant) { 1470 uint64_t LShVal = cast<ConstantSDNode>(LHSShift.getOperand(1))->getValue(); 1471 uint64_t RShVal = cast<ConstantSDNode>(RHSShift.getOperand(1))->getValue(); 1472 if ((LShVal + RShVal) != OpSizeInBits) 1473 return 0; 1474 1475 SDOperand Rot; 1476 if (HasROTL) 1477 Rot = DAG.getNode(ISD::ROTL, VT, LHSShift.getOperand(0), 1478 LHSShift.getOperand(1)); 1479 else 1480 Rot = DAG.getNode(ISD::ROTR, VT, LHSShift.getOperand(0), 1481 RHSShift.getOperand(1)); 1482 1483 // If there is an AND of either shifted operand, apply it to the result. 1484 if (LHSMask.Val || RHSMask.Val) { 1485 uint64_t Mask = MVT::getIntVTBitMask(VT); 1486 1487 if (LHSMask.Val) { 1488 uint64_t RHSBits = (1ULL << LShVal)-1; 1489 Mask &= cast<ConstantSDNode>(LHSMask)->getValue() | RHSBits; 1490 } 1491 if (RHSMask.Val) { 1492 uint64_t LHSBits = ~((1ULL << (OpSizeInBits-RShVal))-1); 1493 Mask &= cast<ConstantSDNode>(RHSMask)->getValue() | LHSBits; 1494 } 1495 1496 Rot = DAG.getNode(ISD::AND, VT, Rot, DAG.getConstant(Mask, VT)); 1497 } 1498 1499 return Rot.Val; 1500 } 1501 1502 // If there is a mask here, and we have a variable shift, we can't be sure 1503 // that we're masking out the right stuff. 1504 if (LHSMask.Val || RHSMask.Val) 1505 return 0; 1506 1507 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y) 1508 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y)) 1509 if (RHSShift.getOperand(1).getOpcode() == ISD::SUB && 1510 LHSShift.getOperand(1) == RHSShift.getOperand(1).getOperand(1)) { 1511 if (ConstantSDNode *SUBC = 1512 dyn_cast<ConstantSDNode>(RHSShift.getOperand(1).getOperand(0))) { 1513 if (SUBC->getValue() == OpSizeInBits) 1514 if (HasROTL) 1515 return DAG.getNode(ISD::ROTL, VT, LHSShift.getOperand(0), 1516 LHSShift.getOperand(1)).Val; 1517 else 1518 return DAG.getNode(ISD::ROTR, VT, LHSShift.getOperand(0), 1519 LHSShift.getOperand(1)).Val; 1520 } 1521 } 1522 1523 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y) 1524 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y)) 1525 if (LHSShift.getOperand(1).getOpcode() == ISD::SUB && 1526 RHSShift.getOperand(1) == LHSShift.getOperand(1).getOperand(1)) { 1527 if (ConstantSDNode *SUBC = 1528 dyn_cast<ConstantSDNode>(LHSShift.getOperand(1).getOperand(0))) { 1529 if (SUBC->getValue() == OpSizeInBits) 1530 if (HasROTL) 1531 return DAG.getNode(ISD::ROTL, VT, LHSShift.getOperand(0), 1532 LHSShift.getOperand(1)).Val; 1533 else 1534 return DAG.getNode(ISD::ROTR, VT, LHSShift.getOperand(0), 1535 RHSShift.getOperand(1)).Val; 1536 } 1537 } 1538 1539 return 0; 1540} 1541 1542 1543SDOperand DAGCombiner::visitXOR(SDNode *N) { 1544 SDOperand N0 = N->getOperand(0); 1545 SDOperand N1 = N->getOperand(1); 1546 SDOperand LHS, RHS, CC; 1547 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1548 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1549 MVT::ValueType VT = N0.getValueType(); 1550 1551 // fold (xor c1, c2) -> c1^c2 1552 if (N0C && N1C) 1553 return DAG.getNode(ISD::XOR, VT, N0, N1); 1554 // canonicalize constant to RHS 1555 if (N0C && !N1C) 1556 return DAG.getNode(ISD::XOR, VT, N1, N0); 1557 // fold (xor x, 0) -> x 1558 if (N1C && N1C->isNullValue()) 1559 return N0; 1560 // reassociate xor 1561 SDOperand RXOR = ReassociateOps(ISD::XOR, N0, N1); 1562 if (RXOR.Val != 0) 1563 return RXOR; 1564 // fold !(x cc y) -> (x !cc y) 1565 if (N1C && N1C->getValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) { 1566 bool isInt = MVT::isInteger(LHS.getValueType()); 1567 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(), 1568 isInt); 1569 if (N0.getOpcode() == ISD::SETCC) 1570 return DAG.getSetCC(VT, LHS, RHS, NotCC); 1571 if (N0.getOpcode() == ISD::SELECT_CC) 1572 return DAG.getSelectCC(LHS, RHS, N0.getOperand(2),N0.getOperand(3),NotCC); 1573 assert(0 && "Unhandled SetCC Equivalent!"); 1574 abort(); 1575 } 1576 // fold !(x or y) -> (!x and !y) iff x or y are setcc 1577 if (N1C && N1C->getValue() == 1 && VT == MVT::i1 && 1578 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 1579 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1); 1580 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) { 1581 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 1582 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS 1583 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS 1584 AddToWorkList(LHS.Val); AddToWorkList(RHS.Val); 1585 return DAG.getNode(NewOpcode, VT, LHS, RHS); 1586 } 1587 } 1588 // fold !(x or y) -> (!x and !y) iff x or y are constants 1589 if (N1C && N1C->isAllOnesValue() && 1590 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 1591 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1); 1592 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) { 1593 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 1594 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS 1595 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS 1596 AddToWorkList(LHS.Val); AddToWorkList(RHS.Val); 1597 return DAG.getNode(NewOpcode, VT, LHS, RHS); 1598 } 1599 } 1600 // fold (xor (xor x, c1), c2) -> (xor x, c1^c2) 1601 if (N1C && N0.getOpcode() == ISD::XOR) { 1602 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0)); 1603 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 1604 if (N00C) 1605 return DAG.getNode(ISD::XOR, VT, N0.getOperand(1), 1606 DAG.getConstant(N1C->getValue()^N00C->getValue(), VT)); 1607 if (N01C) 1608 return DAG.getNode(ISD::XOR, VT, N0.getOperand(0), 1609 DAG.getConstant(N1C->getValue()^N01C->getValue(), VT)); 1610 } 1611 // fold (xor x, x) -> 0 1612 if (N0 == N1) { 1613 if (!MVT::isVector(VT)) { 1614 return DAG.getConstant(0, VT); 1615 } else if (!AfterLegalize || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) { 1616 // Produce a vector of zeros. 1617 SDOperand El = DAG.getConstant(0, MVT::getVectorBaseType(VT)); 1618 std::vector<SDOperand> Ops(MVT::getVectorNumElements(VT), El); 1619 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 1620 } 1621 } 1622 1623 // Simplify: xor (op x...), (op y...) -> (op (xor x, y)) 1624 if (N0.getOpcode() == N1.getOpcode()) { 1625 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N); 1626 if (Tmp.Val) return Tmp; 1627 } 1628 1629 // Simplify the expression using non-local knowledge. 1630 if (!MVT::isVector(VT) && 1631 SimplifyDemandedBits(SDOperand(N, 0))) 1632 return SDOperand(N, 0); 1633 1634 return SDOperand(); 1635} 1636 1637SDOperand DAGCombiner::visitSHL(SDNode *N) { 1638 SDOperand N0 = N->getOperand(0); 1639 SDOperand N1 = N->getOperand(1); 1640 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1641 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1642 MVT::ValueType VT = N0.getValueType(); 1643 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 1644 1645 // fold (shl c1, c2) -> c1<<c2 1646 if (N0C && N1C) 1647 return DAG.getNode(ISD::SHL, VT, N0, N1); 1648 // fold (shl 0, x) -> 0 1649 if (N0C && N0C->isNullValue()) 1650 return N0; 1651 // fold (shl x, c >= size(x)) -> undef 1652 if (N1C && N1C->getValue() >= OpSizeInBits) 1653 return DAG.getNode(ISD::UNDEF, VT); 1654 // fold (shl x, 0) -> x 1655 if (N1C && N1C->isNullValue()) 1656 return N0; 1657 // if (shl x, c) is known to be zero, return 0 1658 if (TLI.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT))) 1659 return DAG.getConstant(0, VT); 1660 if (SimplifyDemandedBits(SDOperand(N, 0))) 1661 return SDOperand(N, 0); 1662 // fold (shl (shl x, c1), c2) -> 0 or (shl x, c1+c2) 1663 if (N1C && N0.getOpcode() == ISD::SHL && 1664 N0.getOperand(1).getOpcode() == ISD::Constant) { 1665 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 1666 uint64_t c2 = N1C->getValue(); 1667 if (c1 + c2 > OpSizeInBits) 1668 return DAG.getConstant(0, VT); 1669 return DAG.getNode(ISD::SHL, VT, N0.getOperand(0), 1670 DAG.getConstant(c1 + c2, N1.getValueType())); 1671 } 1672 // fold (shl (srl x, c1), c2) -> (shl (and x, -1 << c1), c2-c1) or 1673 // (srl (and x, -1 << c1), c1-c2) 1674 if (N1C && N0.getOpcode() == ISD::SRL && 1675 N0.getOperand(1).getOpcode() == ISD::Constant) { 1676 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 1677 uint64_t c2 = N1C->getValue(); 1678 SDOperand Mask = DAG.getNode(ISD::AND, VT, N0.getOperand(0), 1679 DAG.getConstant(~0ULL << c1, VT)); 1680 if (c2 > c1) 1681 return DAG.getNode(ISD::SHL, VT, Mask, 1682 DAG.getConstant(c2-c1, N1.getValueType())); 1683 else 1684 return DAG.getNode(ISD::SRL, VT, Mask, 1685 DAG.getConstant(c1-c2, N1.getValueType())); 1686 } 1687 // fold (shl (sra x, c1), c1) -> (and x, -1 << c1) 1688 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) 1689 return DAG.getNode(ISD::AND, VT, N0.getOperand(0), 1690 DAG.getConstant(~0ULL << N1C->getValue(), VT)); 1691 return SDOperand(); 1692} 1693 1694SDOperand DAGCombiner::visitSRA(SDNode *N) { 1695 SDOperand N0 = N->getOperand(0); 1696 SDOperand N1 = N->getOperand(1); 1697 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1698 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1699 MVT::ValueType VT = N0.getValueType(); 1700 1701 // fold (sra c1, c2) -> c1>>c2 1702 if (N0C && N1C) 1703 return DAG.getNode(ISD::SRA, VT, N0, N1); 1704 // fold (sra 0, x) -> 0 1705 if (N0C && N0C->isNullValue()) 1706 return N0; 1707 // fold (sra -1, x) -> -1 1708 if (N0C && N0C->isAllOnesValue()) 1709 return N0; 1710 // fold (sra x, c >= size(x)) -> undef 1711 if (N1C && N1C->getValue() >= MVT::getSizeInBits(VT)) 1712 return DAG.getNode(ISD::UNDEF, VT); 1713 // fold (sra x, 0) -> x 1714 if (N1C && N1C->isNullValue()) 1715 return N0; 1716 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports 1717 // sext_inreg. 1718 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) { 1719 unsigned LowBits = MVT::getSizeInBits(VT) - (unsigned)N1C->getValue(); 1720 MVT::ValueType EVT; 1721 switch (LowBits) { 1722 default: EVT = MVT::Other; break; 1723 case 1: EVT = MVT::i1; break; 1724 case 8: EVT = MVT::i8; break; 1725 case 16: EVT = MVT::i16; break; 1726 case 32: EVT = MVT::i32; break; 1727 } 1728 if (EVT > MVT::Other && TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, EVT)) 1729 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), 1730 DAG.getValueType(EVT)); 1731 } 1732 1733 // fold (sra (sra x, c1), c2) -> (sra x, c1+c2) 1734 if (N1C && N0.getOpcode() == ISD::SRA) { 1735 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 1736 unsigned Sum = N1C->getValue() + C1->getValue(); 1737 if (Sum >= MVT::getSizeInBits(VT)) Sum = MVT::getSizeInBits(VT)-1; 1738 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0), 1739 DAG.getConstant(Sum, N1C->getValueType(0))); 1740 } 1741 } 1742 1743 // Simplify, based on bits shifted out of the LHS. 1744 if (N1C && SimplifyDemandedBits(SDOperand(N, 0))) 1745 return SDOperand(N, 0); 1746 1747 1748 // If the sign bit is known to be zero, switch this to a SRL. 1749 if (TLI.MaskedValueIsZero(N0, MVT::getIntVTSignBit(VT))) 1750 return DAG.getNode(ISD::SRL, VT, N0, N1); 1751 return SDOperand(); 1752} 1753 1754SDOperand DAGCombiner::visitSRL(SDNode *N) { 1755 SDOperand N0 = N->getOperand(0); 1756 SDOperand N1 = N->getOperand(1); 1757 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1758 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1759 MVT::ValueType VT = N0.getValueType(); 1760 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 1761 1762 // fold (srl c1, c2) -> c1 >>u c2 1763 if (N0C && N1C) 1764 return DAG.getNode(ISD::SRL, VT, N0, N1); 1765 // fold (srl 0, x) -> 0 1766 if (N0C && N0C->isNullValue()) 1767 return N0; 1768 // fold (srl x, c >= size(x)) -> undef 1769 if (N1C && N1C->getValue() >= OpSizeInBits) 1770 return DAG.getNode(ISD::UNDEF, VT); 1771 // fold (srl x, 0) -> x 1772 if (N1C && N1C->isNullValue()) 1773 return N0; 1774 // if (srl x, c) is known to be zero, return 0 1775 if (N1C && TLI.MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits))) 1776 return DAG.getConstant(0, VT); 1777 // fold (srl (srl x, c1), c2) -> 0 or (srl x, c1+c2) 1778 if (N1C && N0.getOpcode() == ISD::SRL && 1779 N0.getOperand(1).getOpcode() == ISD::Constant) { 1780 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 1781 uint64_t c2 = N1C->getValue(); 1782 if (c1 + c2 > OpSizeInBits) 1783 return DAG.getConstant(0, VT); 1784 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0), 1785 DAG.getConstant(c1 + c2, N1.getValueType())); 1786 } 1787 1788 // fold (srl (anyextend x), c) -> (anyextend (srl x, c)) 1789 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 1790 // Shifting in all undef bits? 1791 MVT::ValueType SmallVT = N0.getOperand(0).getValueType(); 1792 if (N1C->getValue() >= MVT::getSizeInBits(SmallVT)) 1793 return DAG.getNode(ISD::UNDEF, VT); 1794 1795 SDOperand SmallShift = DAG.getNode(ISD::SRL, SmallVT, N0.getOperand(0), N1); 1796 AddToWorkList(SmallShift.Val); 1797 return DAG.getNode(ISD::ANY_EXTEND, VT, SmallShift); 1798 } 1799 1800 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign 1801 // bit, which is unmodified by sra. 1802 if (N1C && N1C->getValue()+1 == MVT::getSizeInBits(VT)) { 1803 if (N0.getOpcode() == ISD::SRA) 1804 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0), N1); 1805 } 1806 1807 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit). 1808 if (N1C && N0.getOpcode() == ISD::CTLZ && 1809 N1C->getValue() == Log2_32(MVT::getSizeInBits(VT))) { 1810 uint64_t KnownZero, KnownOne, Mask = MVT::getIntVTBitMask(VT); 1811 TLI.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne); 1812 1813 // If any of the input bits are KnownOne, then the input couldn't be all 1814 // zeros, thus the result of the srl will always be zero. 1815 if (KnownOne) return DAG.getConstant(0, VT); 1816 1817 // If all of the bits input the to ctlz node are known to be zero, then 1818 // the result of the ctlz is "32" and the result of the shift is one. 1819 uint64_t UnknownBits = ~KnownZero & Mask; 1820 if (UnknownBits == 0) return DAG.getConstant(1, VT); 1821 1822 // Otherwise, check to see if there is exactly one bit input to the ctlz. 1823 if ((UnknownBits & (UnknownBits-1)) == 0) { 1824 // Okay, we know that only that the single bit specified by UnknownBits 1825 // could be set on input to the CTLZ node. If this bit is set, the SRL 1826 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair 1827 // to an SRL,XOR pair, which is likely to simplify more. 1828 unsigned ShAmt = CountTrailingZeros_64(UnknownBits); 1829 SDOperand Op = N0.getOperand(0); 1830 if (ShAmt) { 1831 Op = DAG.getNode(ISD::SRL, VT, Op, 1832 DAG.getConstant(ShAmt, TLI.getShiftAmountTy())); 1833 AddToWorkList(Op.Val); 1834 } 1835 return DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(1, VT)); 1836 } 1837 } 1838 1839 return SDOperand(); 1840} 1841 1842SDOperand DAGCombiner::visitCTLZ(SDNode *N) { 1843 SDOperand N0 = N->getOperand(0); 1844 MVT::ValueType VT = N->getValueType(0); 1845 1846 // fold (ctlz c1) -> c2 1847 if (isa<ConstantSDNode>(N0)) 1848 return DAG.getNode(ISD::CTLZ, VT, N0); 1849 return SDOperand(); 1850} 1851 1852SDOperand DAGCombiner::visitCTTZ(SDNode *N) { 1853 SDOperand N0 = N->getOperand(0); 1854 MVT::ValueType VT = N->getValueType(0); 1855 1856 // fold (cttz c1) -> c2 1857 if (isa<ConstantSDNode>(N0)) 1858 return DAG.getNode(ISD::CTTZ, VT, N0); 1859 return SDOperand(); 1860} 1861 1862SDOperand DAGCombiner::visitCTPOP(SDNode *N) { 1863 SDOperand N0 = N->getOperand(0); 1864 MVT::ValueType VT = N->getValueType(0); 1865 1866 // fold (ctpop c1) -> c2 1867 if (isa<ConstantSDNode>(N0)) 1868 return DAG.getNode(ISD::CTPOP, VT, N0); 1869 return SDOperand(); 1870} 1871 1872SDOperand DAGCombiner::visitSELECT(SDNode *N) { 1873 SDOperand N0 = N->getOperand(0); 1874 SDOperand N1 = N->getOperand(1); 1875 SDOperand N2 = N->getOperand(2); 1876 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1877 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1878 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2); 1879 MVT::ValueType VT = N->getValueType(0); 1880 1881 // fold select C, X, X -> X 1882 if (N1 == N2) 1883 return N1; 1884 // fold select true, X, Y -> X 1885 if (N0C && !N0C->isNullValue()) 1886 return N1; 1887 // fold select false, X, Y -> Y 1888 if (N0C && N0C->isNullValue()) 1889 return N2; 1890 // fold select C, 1, X -> C | X 1891 if (MVT::i1 == VT && N1C && N1C->getValue() == 1) 1892 return DAG.getNode(ISD::OR, VT, N0, N2); 1893 // fold select C, 0, X -> ~C & X 1894 // FIXME: this should check for C type == X type, not i1? 1895 if (MVT::i1 == VT && N1C && N1C->isNullValue()) { 1896 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT)); 1897 AddToWorkList(XORNode.Val); 1898 return DAG.getNode(ISD::AND, VT, XORNode, N2); 1899 } 1900 // fold select C, X, 1 -> ~C | X 1901 if (MVT::i1 == VT && N2C && N2C->getValue() == 1) { 1902 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT)); 1903 AddToWorkList(XORNode.Val); 1904 return DAG.getNode(ISD::OR, VT, XORNode, N1); 1905 } 1906 // fold select C, X, 0 -> C & X 1907 // FIXME: this should check for C type == X type, not i1? 1908 if (MVT::i1 == VT && N2C && N2C->isNullValue()) 1909 return DAG.getNode(ISD::AND, VT, N0, N1); 1910 // fold X ? X : Y --> X ? 1 : Y --> X | Y 1911 if (MVT::i1 == VT && N0 == N1) 1912 return DAG.getNode(ISD::OR, VT, N0, N2); 1913 // fold X ? Y : X --> X ? Y : 0 --> X & Y 1914 if (MVT::i1 == VT && N0 == N2) 1915 return DAG.getNode(ISD::AND, VT, N0, N1); 1916 1917 // If we can fold this based on the true/false value, do so. 1918 if (SimplifySelectOps(N, N1, N2)) 1919 return SDOperand(N, 0); // Don't revisit N. 1920 1921 // fold selects based on a setcc into other things, such as min/max/abs 1922 if (N0.getOpcode() == ISD::SETCC) 1923 // FIXME: 1924 // Check against MVT::Other for SELECT_CC, which is a workaround for targets 1925 // having to say they don't support SELECT_CC on every type the DAG knows 1926 // about, since there is no way to mark an opcode illegal at all value types 1927 if (TLI.isOperationLegal(ISD::SELECT_CC, MVT::Other)) 1928 return DAG.getNode(ISD::SELECT_CC, VT, N0.getOperand(0), N0.getOperand(1), 1929 N1, N2, N0.getOperand(2)); 1930 else 1931 return SimplifySelect(N0, N1, N2); 1932 return SDOperand(); 1933} 1934 1935SDOperand DAGCombiner::visitSELECT_CC(SDNode *N) { 1936 SDOperand N0 = N->getOperand(0); 1937 SDOperand N1 = N->getOperand(1); 1938 SDOperand N2 = N->getOperand(2); 1939 SDOperand N3 = N->getOperand(3); 1940 SDOperand N4 = N->getOperand(4); 1941 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get(); 1942 1943 // fold select_cc lhs, rhs, x, x, cc -> x 1944 if (N2 == N3) 1945 return N2; 1946 1947 // Determine if the condition we're dealing with is constant 1948 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false); 1949 if (SCC.Val) AddToWorkList(SCC.Val); 1950 1951 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val)) { 1952 if (SCCC->getValue()) 1953 return N2; // cond always true -> true val 1954 else 1955 return N3; // cond always false -> false val 1956 } 1957 1958 // Fold to a simpler select_cc 1959 if (SCC.Val && SCC.getOpcode() == ISD::SETCC) 1960 return DAG.getNode(ISD::SELECT_CC, N2.getValueType(), 1961 SCC.getOperand(0), SCC.getOperand(1), N2, N3, 1962 SCC.getOperand(2)); 1963 1964 // If we can fold this based on the true/false value, do so. 1965 if (SimplifySelectOps(N, N2, N3)) 1966 return SDOperand(N, 0); // Don't revisit N. 1967 1968 // fold select_cc into other things, such as min/max/abs 1969 return SimplifySelectCC(N0, N1, N2, N3, CC); 1970} 1971 1972SDOperand DAGCombiner::visitSETCC(SDNode *N) { 1973 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1), 1974 cast<CondCodeSDNode>(N->getOperand(2))->get()); 1975} 1976 1977SDOperand DAGCombiner::visitSIGN_EXTEND(SDNode *N) { 1978 SDOperand N0 = N->getOperand(0); 1979 MVT::ValueType VT = N->getValueType(0); 1980 1981 // fold (sext c1) -> c1 1982 if (isa<ConstantSDNode>(N0)) 1983 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0); 1984 1985 // fold (sext (sext x)) -> (sext x) 1986 // fold (sext (aext x)) -> (sext x) 1987 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 1988 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0.getOperand(0)); 1989 1990 if (N0.getOpcode() == ISD::TRUNCATE) { 1991 // See if the value being truncated is already sign extended. If so, just 1992 // eliminate the trunc/sext pair. 1993 SDOperand Op = N0.getOperand(0); 1994 unsigned OpBits = MVT::getSizeInBits(Op.getValueType()); 1995 unsigned MidBits = MVT::getSizeInBits(N0.getValueType()); 1996 unsigned DestBits = MVT::getSizeInBits(VT); 1997 unsigned NumSignBits = TLI.ComputeNumSignBits(Op); 1998 1999 if (OpBits == DestBits) { 2000 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign 2001 // bits, it is already ready. 2002 if (NumSignBits > DestBits-MidBits) 2003 return Op; 2004 } else if (OpBits < DestBits) { 2005 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign 2006 // bits, just sext from i32. 2007 if (NumSignBits > OpBits-MidBits) 2008 return DAG.getNode(ISD::SIGN_EXTEND, VT, Op); 2009 } else { 2010 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign 2011 // bits, just truncate to i32. 2012 if (NumSignBits > OpBits-MidBits) 2013 return DAG.getNode(ISD::TRUNCATE, VT, Op); 2014 } 2015 2016 // fold (sext (truncate x)) -> (sextinreg x). 2017 if (!AfterLegalize || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, 2018 N0.getValueType())) { 2019 if (Op.getValueType() < VT) 2020 Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op); 2021 else if (Op.getValueType() > VT) 2022 Op = DAG.getNode(ISD::TRUNCATE, VT, Op); 2023 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, Op, 2024 DAG.getValueType(N0.getValueType())); 2025 } 2026 } 2027 2028 // fold (sext (load x)) -> (sext (truncate (sextload x))) 2029 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() && 2030 (!AfterLegalize||TLI.isLoadXLegal(ISD::SEXTLOAD, N0.getValueType()))){ 2031 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2032 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 2033 LN0->getBasePtr(), LN0->getSrcValue(), 2034 LN0->getSrcValueOffset(), 2035 N0.getValueType()); 2036 CombineTo(N, ExtLoad); 2037 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 2038 ExtLoad.getValue(1)); 2039 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2040 } 2041 2042 // fold (sext (sextload x)) -> (sext (truncate (sextload x))) 2043 // fold (sext ( extload x)) -> (sext (truncate (sextload x))) 2044 if ((ISD::isSEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) && N0.hasOneUse()) { 2045 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2046 MVT::ValueType EVT = LN0->getLoadedVT(); 2047 if (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT)) { 2048 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 2049 LN0->getBasePtr(), LN0->getSrcValue(), 2050 LN0->getSrcValueOffset(), EVT); 2051 CombineTo(N, ExtLoad); 2052 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 2053 ExtLoad.getValue(1)); 2054 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2055 } 2056 } 2057 2058 return SDOperand(); 2059} 2060 2061SDOperand DAGCombiner::visitZERO_EXTEND(SDNode *N) { 2062 SDOperand N0 = N->getOperand(0); 2063 MVT::ValueType VT = N->getValueType(0); 2064 2065 // fold (zext c1) -> c1 2066 if (isa<ConstantSDNode>(N0)) 2067 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0); 2068 // fold (zext (zext x)) -> (zext x) 2069 // fold (zext (aext x)) -> (zext x) 2070 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 2071 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0.getOperand(0)); 2072 2073 // fold (zext (truncate x)) -> (and x, mask) 2074 if (N0.getOpcode() == ISD::TRUNCATE && 2075 (!AfterLegalize || TLI.isOperationLegal(ISD::AND, VT))) { 2076 SDOperand Op = N0.getOperand(0); 2077 if (Op.getValueType() < VT) { 2078 Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op); 2079 } else if (Op.getValueType() > VT) { 2080 Op = DAG.getNode(ISD::TRUNCATE, VT, Op); 2081 } 2082 return DAG.getZeroExtendInReg(Op, N0.getValueType()); 2083 } 2084 2085 // fold (zext (and (trunc x), cst)) -> (and x, cst). 2086 if (N0.getOpcode() == ISD::AND && 2087 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 2088 N0.getOperand(1).getOpcode() == ISD::Constant) { 2089 SDOperand X = N0.getOperand(0).getOperand(0); 2090 if (X.getValueType() < VT) { 2091 X = DAG.getNode(ISD::ANY_EXTEND, VT, X); 2092 } else if (X.getValueType() > VT) { 2093 X = DAG.getNode(ISD::TRUNCATE, VT, X); 2094 } 2095 uint64_t Mask = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 2096 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT)); 2097 } 2098 2099 // fold (zext (load x)) -> (zext (truncate (zextload x))) 2100 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() && 2101 (!AfterLegalize||TLI.isLoadXLegal(ISD::ZEXTLOAD, N0.getValueType()))) { 2102 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2103 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 2104 LN0->getBasePtr(), LN0->getSrcValue(), 2105 LN0->getSrcValueOffset(), 2106 N0.getValueType()); 2107 CombineTo(N, ExtLoad); 2108 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 2109 ExtLoad.getValue(1)); 2110 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2111 } 2112 2113 // fold (zext (zextload x)) -> (zext (truncate (zextload x))) 2114 // fold (zext ( extload x)) -> (zext (truncate (zextload x))) 2115 if ((ISD::isZEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) && N0.hasOneUse()) { 2116 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2117 MVT::ValueType EVT = LN0->getLoadedVT(); 2118 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 2119 LN0->getBasePtr(), LN0->getSrcValue(), 2120 LN0->getSrcValueOffset(), EVT); 2121 CombineTo(N, ExtLoad); 2122 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 2123 ExtLoad.getValue(1)); 2124 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2125 } 2126 return SDOperand(); 2127} 2128 2129SDOperand DAGCombiner::visitANY_EXTEND(SDNode *N) { 2130 SDOperand N0 = N->getOperand(0); 2131 MVT::ValueType VT = N->getValueType(0); 2132 2133 // fold (aext c1) -> c1 2134 if (isa<ConstantSDNode>(N0)) 2135 return DAG.getNode(ISD::ANY_EXTEND, VT, N0); 2136 // fold (aext (aext x)) -> (aext x) 2137 // fold (aext (zext x)) -> (zext x) 2138 // fold (aext (sext x)) -> (sext x) 2139 if (N0.getOpcode() == ISD::ANY_EXTEND || 2140 N0.getOpcode() == ISD::ZERO_EXTEND || 2141 N0.getOpcode() == ISD::SIGN_EXTEND) 2142 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0)); 2143 2144 // fold (aext (truncate x)) 2145 if (N0.getOpcode() == ISD::TRUNCATE) { 2146 SDOperand TruncOp = N0.getOperand(0); 2147 if (TruncOp.getValueType() == VT) 2148 return TruncOp; // x iff x size == zext size. 2149 if (TruncOp.getValueType() > VT) 2150 return DAG.getNode(ISD::TRUNCATE, VT, TruncOp); 2151 return DAG.getNode(ISD::ANY_EXTEND, VT, TruncOp); 2152 } 2153 2154 // fold (aext (and (trunc x), cst)) -> (and x, cst). 2155 if (N0.getOpcode() == ISD::AND && 2156 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 2157 N0.getOperand(1).getOpcode() == ISD::Constant) { 2158 SDOperand X = N0.getOperand(0).getOperand(0); 2159 if (X.getValueType() < VT) { 2160 X = DAG.getNode(ISD::ANY_EXTEND, VT, X); 2161 } else if (X.getValueType() > VT) { 2162 X = DAG.getNode(ISD::TRUNCATE, VT, X); 2163 } 2164 uint64_t Mask = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 2165 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT)); 2166 } 2167 2168 // fold (aext (load x)) -> (aext (truncate (extload x))) 2169 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() && 2170 (!AfterLegalize||TLI.isLoadXLegal(ISD::EXTLOAD, N0.getValueType()))) { 2171 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2172 SDOperand ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, LN0->getChain(), 2173 LN0->getBasePtr(), LN0->getSrcValue(), 2174 LN0->getSrcValueOffset(), 2175 N0.getValueType()); 2176 CombineTo(N, ExtLoad); 2177 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 2178 ExtLoad.getValue(1)); 2179 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2180 } 2181 2182 // fold (aext (zextload x)) -> (aext (truncate (zextload x))) 2183 // fold (aext (sextload x)) -> (aext (truncate (sextload x))) 2184 // fold (aext ( extload x)) -> (aext (truncate (extload x))) 2185 if (N0.getOpcode() == ISD::LOAD && !ISD::isNON_EXTLoad(N0.Val) && 2186 N0.hasOneUse()) { 2187 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2188 MVT::ValueType EVT = LN0->getLoadedVT(); 2189 SDOperand ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), VT, 2190 LN0->getChain(), LN0->getBasePtr(), 2191 LN0->getSrcValue(), 2192 LN0->getSrcValueOffset(), EVT); 2193 CombineTo(N, ExtLoad); 2194 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 2195 ExtLoad.getValue(1)); 2196 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2197 } 2198 return SDOperand(); 2199} 2200 2201 2202SDOperand DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) { 2203 SDOperand N0 = N->getOperand(0); 2204 SDOperand N1 = N->getOperand(1); 2205 MVT::ValueType VT = N->getValueType(0); 2206 MVT::ValueType EVT = cast<VTSDNode>(N1)->getVT(); 2207 unsigned EVTBits = MVT::getSizeInBits(EVT); 2208 2209 // fold (sext_in_reg c1) -> c1 2210 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF) 2211 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0, N1); 2212 2213 // If the input is already sign extended, just drop the extension. 2214 if (TLI.ComputeNumSignBits(N0) >= MVT::getSizeInBits(VT)-EVTBits+1) 2215 return N0; 2216 2217 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2 2218 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 2219 EVT < cast<VTSDNode>(N0.getOperand(1))->getVT()) { 2220 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), N1); 2221 } 2222 2223 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is zero 2224 if (TLI.MaskedValueIsZero(N0, 1ULL << (EVTBits-1))) 2225 return DAG.getZeroExtendInReg(N0, EVT); 2226 2227 // fold (sext_in_reg (srl X, 24), i8) -> sra X, 24 2228 // fold (sext_in_reg (srl X, 23), i8) -> sra X, 23 iff possible. 2229 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above. 2230 if (N0.getOpcode() == ISD::SRL) { 2231 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 2232 if (ShAmt->getValue()+EVTBits <= MVT::getSizeInBits(VT)) { 2233 // We can turn this into an SRA iff the input to the SRL is already sign 2234 // extended enough. 2235 unsigned InSignBits = TLI.ComputeNumSignBits(N0.getOperand(0)); 2236 if (MVT::getSizeInBits(VT)-(ShAmt->getValue()+EVTBits) < InSignBits) 2237 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0), N0.getOperand(1)); 2238 } 2239 } 2240 2241 // fold (sext_inreg (extload x)) -> (sextload x) 2242 if (ISD::isEXTLoad(N0.Val) && 2243 EVT == cast<LoadSDNode>(N0)->getLoadedVT() && 2244 (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))) { 2245 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2246 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 2247 LN0->getBasePtr(), LN0->getSrcValue(), 2248 LN0->getSrcValueOffset(), EVT); 2249 CombineTo(N, ExtLoad); 2250 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 2251 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2252 } 2253 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use 2254 if (ISD::isZEXTLoad(N0.Val) && N0.hasOneUse() && 2255 EVT == cast<LoadSDNode>(N0)->getLoadedVT() && 2256 (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))) { 2257 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2258 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 2259 LN0->getBasePtr(), LN0->getSrcValue(), 2260 LN0->getSrcValueOffset(), EVT); 2261 CombineTo(N, ExtLoad); 2262 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 2263 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2264 } 2265 return SDOperand(); 2266} 2267 2268SDOperand DAGCombiner::visitTRUNCATE(SDNode *N) { 2269 SDOperand N0 = N->getOperand(0); 2270 MVT::ValueType VT = N->getValueType(0); 2271 2272 // noop truncate 2273 if (N0.getValueType() == N->getValueType(0)) 2274 return N0; 2275 // fold (truncate c1) -> c1 2276 if (isa<ConstantSDNode>(N0)) 2277 return DAG.getNode(ISD::TRUNCATE, VT, N0); 2278 // fold (truncate (truncate x)) -> (truncate x) 2279 if (N0.getOpcode() == ISD::TRUNCATE) 2280 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0)); 2281 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x 2282 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::SIGN_EXTEND|| 2283 N0.getOpcode() == ISD::ANY_EXTEND) { 2284 if (N0.getOperand(0).getValueType() < VT) 2285 // if the source is smaller than the dest, we still need an extend 2286 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0)); 2287 else if (N0.getOperand(0).getValueType() > VT) 2288 // if the source is larger than the dest, than we just need the truncate 2289 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0)); 2290 else 2291 // if the source and dest are the same type, we can drop both the extend 2292 // and the truncate 2293 return N0.getOperand(0); 2294 } 2295 // fold (truncate (load x)) -> (smaller load x) 2296 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() && 2297 // Do not allow folding to i1 here. i1 is implicitly stored in memory in 2298 // zero extended form: by shrinking the load, we lose track of the fact 2299 // that it is already zero extended. 2300 // FIXME: This should be reevaluated. 2301 VT != MVT::i1) { 2302 assert(MVT::getSizeInBits(N0.getValueType()) > MVT::getSizeInBits(VT) && 2303 "Cannot truncate to larger type!"); 2304 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2305 MVT::ValueType PtrType = N0.getOperand(1).getValueType(); 2306 // For big endian targets, we need to add an offset to the pointer to load 2307 // the correct bytes. For little endian systems, we merely need to read 2308 // fewer bytes from the same pointer. 2309 uint64_t PtrOff = 2310 (MVT::getSizeInBits(N0.getValueType()) - MVT::getSizeInBits(VT)) / 8; 2311 SDOperand NewPtr = TLI.isLittleEndian() ? LN0->getBasePtr() : 2312 DAG.getNode(ISD::ADD, PtrType, LN0->getBasePtr(), 2313 DAG.getConstant(PtrOff, PtrType)); 2314 AddToWorkList(NewPtr.Val); 2315 SDOperand Load = DAG.getLoad(VT, LN0->getChain(), NewPtr, 2316 LN0->getSrcValue(), LN0->getSrcValueOffset()); 2317 AddToWorkList(N); 2318 CombineTo(N0.Val, Load, Load.getValue(1)); 2319 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2320 } 2321 return SDOperand(); 2322} 2323 2324SDOperand DAGCombiner::visitBIT_CONVERT(SDNode *N) { 2325 SDOperand N0 = N->getOperand(0); 2326 MVT::ValueType VT = N->getValueType(0); 2327 2328 // If the input is a constant, let getNode() fold it. 2329 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) { 2330 SDOperand Res = DAG.getNode(ISD::BIT_CONVERT, VT, N0); 2331 if (Res.Val != N) return Res; 2332 } 2333 2334 if (N0.getOpcode() == ISD::BIT_CONVERT) // conv(conv(x,t1),t2) -> conv(x,t2) 2335 return DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0)); 2336 2337 // fold (conv (load x)) -> (load (conv*)x) 2338 // FIXME: These xforms need to know that the resultant load doesn't need a 2339 // higher alignment than the original! 2340 if (0 && ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse()) { 2341 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2342 SDOperand Load = DAG.getLoad(VT, LN0->getChain(), LN0->getBasePtr(), 2343 LN0->getSrcValue(), LN0->getSrcValueOffset()); 2344 AddToWorkList(N); 2345 CombineTo(N0.Val, DAG.getNode(ISD::BIT_CONVERT, N0.getValueType(), Load), 2346 Load.getValue(1)); 2347 return Load; 2348 } 2349 2350 return SDOperand(); 2351} 2352 2353SDOperand DAGCombiner::visitVBIT_CONVERT(SDNode *N) { 2354 SDOperand N0 = N->getOperand(0); 2355 MVT::ValueType VT = N->getValueType(0); 2356 2357 // If the input is a VBUILD_VECTOR with all constant elements, fold this now. 2358 // First check to see if this is all constant. 2359 if (N0.getOpcode() == ISD::VBUILD_VECTOR && N0.Val->hasOneUse() && 2360 VT == MVT::Vector) { 2361 bool isSimple = true; 2362 for (unsigned i = 0, e = N0.getNumOperands()-2; i != e; ++i) 2363 if (N0.getOperand(i).getOpcode() != ISD::UNDEF && 2364 N0.getOperand(i).getOpcode() != ISD::Constant && 2365 N0.getOperand(i).getOpcode() != ISD::ConstantFP) { 2366 isSimple = false; 2367 break; 2368 } 2369 2370 MVT::ValueType DestEltVT = cast<VTSDNode>(N->getOperand(2))->getVT(); 2371 if (isSimple && !MVT::isVector(DestEltVT)) { 2372 return ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(N0.Val, DestEltVT); 2373 } 2374 } 2375 2376 return SDOperand(); 2377} 2378 2379/// ConstantFoldVBIT_CONVERTofVBUILD_VECTOR - We know that BV is a vbuild_vector 2380/// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the 2381/// destination element value type. 2382SDOperand DAGCombiner:: 2383ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(SDNode *BV, MVT::ValueType DstEltVT) { 2384 MVT::ValueType SrcEltVT = BV->getOperand(0).getValueType(); 2385 2386 // If this is already the right type, we're done. 2387 if (SrcEltVT == DstEltVT) return SDOperand(BV, 0); 2388 2389 unsigned SrcBitSize = MVT::getSizeInBits(SrcEltVT); 2390 unsigned DstBitSize = MVT::getSizeInBits(DstEltVT); 2391 2392 // If this is a conversion of N elements of one type to N elements of another 2393 // type, convert each element. This handles FP<->INT cases. 2394 if (SrcBitSize == DstBitSize) { 2395 SmallVector<SDOperand, 8> Ops; 2396 for (unsigned i = 0, e = BV->getNumOperands()-2; i != e; ++i) { 2397 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, DstEltVT, BV->getOperand(i))); 2398 AddToWorkList(Ops.back().Val); 2399 } 2400 Ops.push_back(*(BV->op_end()-2)); // Add num elements. 2401 Ops.push_back(DAG.getValueType(DstEltVT)); 2402 return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &Ops[0], Ops.size()); 2403 } 2404 2405 // Otherwise, we're growing or shrinking the elements. To avoid having to 2406 // handle annoying details of growing/shrinking FP values, we convert them to 2407 // int first. 2408 if (MVT::isFloatingPoint(SrcEltVT)) { 2409 // Convert the input float vector to a int vector where the elements are the 2410 // same sizes. 2411 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!"); 2412 MVT::ValueType IntVT = SrcEltVT == MVT::f32 ? MVT::i32 : MVT::i64; 2413 BV = ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(BV, IntVT).Val; 2414 SrcEltVT = IntVT; 2415 } 2416 2417 // Now we know the input is an integer vector. If the output is a FP type, 2418 // convert to integer first, then to FP of the right size. 2419 if (MVT::isFloatingPoint(DstEltVT)) { 2420 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!"); 2421 MVT::ValueType TmpVT = DstEltVT == MVT::f32 ? MVT::i32 : MVT::i64; 2422 SDNode *Tmp = ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(BV, TmpVT).Val; 2423 2424 // Next, convert to FP elements of the same size. 2425 return ConstantFoldVBIT_CONVERTofVBUILD_VECTOR(Tmp, DstEltVT); 2426 } 2427 2428 // Okay, we know the src/dst types are both integers of differing types. 2429 // Handling growing first. 2430 assert(MVT::isInteger(SrcEltVT) && MVT::isInteger(DstEltVT)); 2431 if (SrcBitSize < DstBitSize) { 2432 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize; 2433 2434 SmallVector<SDOperand, 8> Ops; 2435 for (unsigned i = 0, e = BV->getNumOperands()-2; i != e; 2436 i += NumInputsPerOutput) { 2437 bool isLE = TLI.isLittleEndian(); 2438 uint64_t NewBits = 0; 2439 bool EltIsUndef = true; 2440 for (unsigned j = 0; j != NumInputsPerOutput; ++j) { 2441 // Shift the previously computed bits over. 2442 NewBits <<= SrcBitSize; 2443 SDOperand Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j)); 2444 if (Op.getOpcode() == ISD::UNDEF) continue; 2445 EltIsUndef = false; 2446 2447 NewBits |= cast<ConstantSDNode>(Op)->getValue(); 2448 } 2449 2450 if (EltIsUndef) 2451 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT)); 2452 else 2453 Ops.push_back(DAG.getConstant(NewBits, DstEltVT)); 2454 } 2455 2456 Ops.push_back(DAG.getConstant(Ops.size(), MVT::i32)); // Add num elements. 2457 Ops.push_back(DAG.getValueType(DstEltVT)); // Add element size. 2458 return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &Ops[0], Ops.size()); 2459 } 2460 2461 // Finally, this must be the case where we are shrinking elements: each input 2462 // turns into multiple outputs. 2463 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize; 2464 SmallVector<SDOperand, 8> Ops; 2465 for (unsigned i = 0, e = BV->getNumOperands()-2; i != e; ++i) { 2466 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) { 2467 for (unsigned j = 0; j != NumOutputsPerInput; ++j) 2468 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT)); 2469 continue; 2470 } 2471 uint64_t OpVal = cast<ConstantSDNode>(BV->getOperand(i))->getValue(); 2472 2473 for (unsigned j = 0; j != NumOutputsPerInput; ++j) { 2474 unsigned ThisVal = OpVal & ((1ULL << DstBitSize)-1); 2475 OpVal >>= DstBitSize; 2476 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT)); 2477 } 2478 2479 // For big endian targets, swap the order of the pieces of each element. 2480 if (!TLI.isLittleEndian()) 2481 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end()); 2482 } 2483 Ops.push_back(DAG.getConstant(Ops.size(), MVT::i32)); // Add num elements. 2484 Ops.push_back(DAG.getValueType(DstEltVT)); // Add element size. 2485 return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &Ops[0], Ops.size()); 2486} 2487 2488 2489 2490SDOperand DAGCombiner::visitFADD(SDNode *N) { 2491 SDOperand N0 = N->getOperand(0); 2492 SDOperand N1 = N->getOperand(1); 2493 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2494 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 2495 MVT::ValueType VT = N->getValueType(0); 2496 2497 // fold (fadd c1, c2) -> c1+c2 2498 if (N0CFP && N1CFP) 2499 return DAG.getNode(ISD::FADD, VT, N0, N1); 2500 // canonicalize constant to RHS 2501 if (N0CFP && !N1CFP) 2502 return DAG.getNode(ISD::FADD, VT, N1, N0); 2503 // fold (A + (-B)) -> A-B 2504 if (N1.getOpcode() == ISD::FNEG) 2505 return DAG.getNode(ISD::FSUB, VT, N0, N1.getOperand(0)); 2506 // fold ((-A) + B) -> B-A 2507 if (N0.getOpcode() == ISD::FNEG) 2508 return DAG.getNode(ISD::FSUB, VT, N1, N0.getOperand(0)); 2509 2510 // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2)) 2511 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FADD && 2512 N0.Val->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 2513 return DAG.getNode(ISD::FADD, VT, N0.getOperand(0), 2514 DAG.getNode(ISD::FADD, VT, N0.getOperand(1), N1)); 2515 2516 return SDOperand(); 2517} 2518 2519SDOperand DAGCombiner::visitFSUB(SDNode *N) { 2520 SDOperand N0 = N->getOperand(0); 2521 SDOperand N1 = N->getOperand(1); 2522 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2523 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 2524 MVT::ValueType VT = N->getValueType(0); 2525 2526 // fold (fsub c1, c2) -> c1-c2 2527 if (N0CFP && N1CFP) 2528 return DAG.getNode(ISD::FSUB, VT, N0, N1); 2529 // fold (A-(-B)) -> A+B 2530 if (N1.getOpcode() == ISD::FNEG) 2531 return DAG.getNode(ISD::FADD, VT, N0, N1.getOperand(0)); 2532 return SDOperand(); 2533} 2534 2535SDOperand DAGCombiner::visitFMUL(SDNode *N) { 2536 SDOperand N0 = N->getOperand(0); 2537 SDOperand N1 = N->getOperand(1); 2538 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2539 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 2540 MVT::ValueType VT = N->getValueType(0); 2541 2542 // fold (fmul c1, c2) -> c1*c2 2543 if (N0CFP && N1CFP) 2544 return DAG.getNode(ISD::FMUL, VT, N0, N1); 2545 // canonicalize constant to RHS 2546 if (N0CFP && !N1CFP) 2547 return DAG.getNode(ISD::FMUL, VT, N1, N0); 2548 // fold (fmul X, 2.0) -> (fadd X, X) 2549 if (N1CFP && N1CFP->isExactlyValue(+2.0)) 2550 return DAG.getNode(ISD::FADD, VT, N0, N0); 2551 2552 // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2)) 2553 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FMUL && 2554 N0.Val->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 2555 return DAG.getNode(ISD::FMUL, VT, N0.getOperand(0), 2556 DAG.getNode(ISD::FMUL, VT, N0.getOperand(1), N1)); 2557 2558 return SDOperand(); 2559} 2560 2561SDOperand DAGCombiner::visitFDIV(SDNode *N) { 2562 SDOperand N0 = N->getOperand(0); 2563 SDOperand N1 = N->getOperand(1); 2564 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2565 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 2566 MVT::ValueType VT = N->getValueType(0); 2567 2568 // fold (fdiv c1, c2) -> c1/c2 2569 if (N0CFP && N1CFP) 2570 return DAG.getNode(ISD::FDIV, VT, N0, N1); 2571 return SDOperand(); 2572} 2573 2574SDOperand DAGCombiner::visitFREM(SDNode *N) { 2575 SDOperand N0 = N->getOperand(0); 2576 SDOperand N1 = N->getOperand(1); 2577 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2578 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 2579 MVT::ValueType VT = N->getValueType(0); 2580 2581 // fold (frem c1, c2) -> fmod(c1,c2) 2582 if (N0CFP && N1CFP) 2583 return DAG.getNode(ISD::FREM, VT, N0, N1); 2584 return SDOperand(); 2585} 2586 2587SDOperand DAGCombiner::visitFCOPYSIGN(SDNode *N) { 2588 SDOperand N0 = N->getOperand(0); 2589 SDOperand N1 = N->getOperand(1); 2590 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2591 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 2592 MVT::ValueType VT = N->getValueType(0); 2593 2594 if (N0CFP && N1CFP) // Constant fold 2595 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1); 2596 2597 if (N1CFP) { 2598 // copysign(x, c1) -> fabs(x) iff ispos(c1) 2599 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1) 2600 union { 2601 double d; 2602 int64_t i; 2603 } u; 2604 u.d = N1CFP->getValue(); 2605 if (u.i >= 0) 2606 return DAG.getNode(ISD::FABS, VT, N0); 2607 else 2608 return DAG.getNode(ISD::FNEG, VT, DAG.getNode(ISD::FABS, VT, N0)); 2609 } 2610 2611 // copysign(fabs(x), y) -> copysign(x, y) 2612 // copysign(fneg(x), y) -> copysign(x, y) 2613 // copysign(copysign(x,z), y) -> copysign(x, y) 2614 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG || 2615 N0.getOpcode() == ISD::FCOPYSIGN) 2616 return DAG.getNode(ISD::FCOPYSIGN, VT, N0.getOperand(0), N1); 2617 2618 // copysign(x, abs(y)) -> abs(x) 2619 if (N1.getOpcode() == ISD::FABS) 2620 return DAG.getNode(ISD::FABS, VT, N0); 2621 2622 // copysign(x, copysign(y,z)) -> copysign(x, z) 2623 if (N1.getOpcode() == ISD::FCOPYSIGN) 2624 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(1)); 2625 2626 // copysign(x, fp_extend(y)) -> copysign(x, y) 2627 // copysign(x, fp_round(y)) -> copysign(x, y) 2628 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND) 2629 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(0)); 2630 2631 return SDOperand(); 2632} 2633 2634 2635 2636SDOperand DAGCombiner::visitSINT_TO_FP(SDNode *N) { 2637 SDOperand N0 = N->getOperand(0); 2638 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2639 MVT::ValueType VT = N->getValueType(0); 2640 2641 // fold (sint_to_fp c1) -> c1fp 2642 if (N0C) 2643 return DAG.getNode(ISD::SINT_TO_FP, VT, N0); 2644 return SDOperand(); 2645} 2646 2647SDOperand DAGCombiner::visitUINT_TO_FP(SDNode *N) { 2648 SDOperand N0 = N->getOperand(0); 2649 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2650 MVT::ValueType VT = N->getValueType(0); 2651 2652 // fold (uint_to_fp c1) -> c1fp 2653 if (N0C) 2654 return DAG.getNode(ISD::UINT_TO_FP, VT, N0); 2655 return SDOperand(); 2656} 2657 2658SDOperand DAGCombiner::visitFP_TO_SINT(SDNode *N) { 2659 SDOperand N0 = N->getOperand(0); 2660 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2661 MVT::ValueType VT = N->getValueType(0); 2662 2663 // fold (fp_to_sint c1fp) -> c1 2664 if (N0CFP) 2665 return DAG.getNode(ISD::FP_TO_SINT, VT, N0); 2666 return SDOperand(); 2667} 2668 2669SDOperand DAGCombiner::visitFP_TO_UINT(SDNode *N) { 2670 SDOperand N0 = N->getOperand(0); 2671 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2672 MVT::ValueType VT = N->getValueType(0); 2673 2674 // fold (fp_to_uint c1fp) -> c1 2675 if (N0CFP) 2676 return DAG.getNode(ISD::FP_TO_UINT, VT, N0); 2677 return SDOperand(); 2678} 2679 2680SDOperand DAGCombiner::visitFP_ROUND(SDNode *N) { 2681 SDOperand N0 = N->getOperand(0); 2682 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2683 MVT::ValueType VT = N->getValueType(0); 2684 2685 // fold (fp_round c1fp) -> c1fp 2686 if (N0CFP) 2687 return DAG.getNode(ISD::FP_ROUND, VT, N0); 2688 2689 // fold (fp_round (fp_extend x)) -> x 2690 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType()) 2691 return N0.getOperand(0); 2692 2693 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y) 2694 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.Val->hasOneUse()) { 2695 SDOperand Tmp = DAG.getNode(ISD::FP_ROUND, VT, N0.getOperand(0)); 2696 AddToWorkList(Tmp.Val); 2697 return DAG.getNode(ISD::FCOPYSIGN, VT, Tmp, N0.getOperand(1)); 2698 } 2699 2700 return SDOperand(); 2701} 2702 2703SDOperand DAGCombiner::visitFP_ROUND_INREG(SDNode *N) { 2704 SDOperand N0 = N->getOperand(0); 2705 MVT::ValueType VT = N->getValueType(0); 2706 MVT::ValueType EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 2707 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2708 2709 // fold (fp_round_inreg c1fp) -> c1fp 2710 if (N0CFP) { 2711 SDOperand Round = DAG.getConstantFP(N0CFP->getValue(), EVT); 2712 return DAG.getNode(ISD::FP_EXTEND, VT, Round); 2713 } 2714 return SDOperand(); 2715} 2716 2717SDOperand DAGCombiner::visitFP_EXTEND(SDNode *N) { 2718 SDOperand N0 = N->getOperand(0); 2719 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2720 MVT::ValueType VT = N->getValueType(0); 2721 2722 // fold (fp_extend c1fp) -> c1fp 2723 if (N0CFP) 2724 return DAG.getNode(ISD::FP_EXTEND, VT, N0); 2725 2726 // fold (fpext (load x)) -> (fpext (fpround (extload x))) 2727 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() && 2728 (!AfterLegalize||TLI.isLoadXLegal(ISD::EXTLOAD, N0.getValueType()))) { 2729 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2730 SDOperand ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, LN0->getChain(), 2731 LN0->getBasePtr(), LN0->getSrcValue(), 2732 LN0->getSrcValueOffset(), 2733 N0.getValueType()); 2734 CombineTo(N, ExtLoad); 2735 CombineTo(N0.Val, DAG.getNode(ISD::FP_ROUND, N0.getValueType(), ExtLoad), 2736 ExtLoad.getValue(1)); 2737 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2738 } 2739 2740 2741 return SDOperand(); 2742} 2743 2744SDOperand DAGCombiner::visitFNEG(SDNode *N) { 2745 SDOperand N0 = N->getOperand(0); 2746 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2747 MVT::ValueType VT = N->getValueType(0); 2748 2749 // fold (fneg c1) -> -c1 2750 if (N0CFP) 2751 return DAG.getNode(ISD::FNEG, VT, N0); 2752 // fold (fneg (sub x, y)) -> (sub y, x) 2753 if (N0.getOpcode() == ISD::SUB) 2754 return DAG.getNode(ISD::SUB, VT, N0.getOperand(1), N0.getOperand(0)); 2755 // fold (fneg (fneg x)) -> x 2756 if (N0.getOpcode() == ISD::FNEG) 2757 return N0.getOperand(0); 2758 return SDOperand(); 2759} 2760 2761SDOperand DAGCombiner::visitFABS(SDNode *N) { 2762 SDOperand N0 = N->getOperand(0); 2763 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 2764 MVT::ValueType VT = N->getValueType(0); 2765 2766 // fold (fabs c1) -> fabs(c1) 2767 if (N0CFP) 2768 return DAG.getNode(ISD::FABS, VT, N0); 2769 // fold (fabs (fabs x)) -> (fabs x) 2770 if (N0.getOpcode() == ISD::FABS) 2771 return N->getOperand(0); 2772 // fold (fabs (fneg x)) -> (fabs x) 2773 // fold (fabs (fcopysign x, y)) -> (fabs x) 2774 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN) 2775 return DAG.getNode(ISD::FABS, VT, N0.getOperand(0)); 2776 2777 return SDOperand(); 2778} 2779 2780SDOperand DAGCombiner::visitBRCOND(SDNode *N) { 2781 SDOperand Chain = N->getOperand(0); 2782 SDOperand N1 = N->getOperand(1); 2783 SDOperand N2 = N->getOperand(2); 2784 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2785 2786 // never taken branch, fold to chain 2787 if (N1C && N1C->isNullValue()) 2788 return Chain; 2789 // unconditional branch 2790 if (N1C && N1C->getValue() == 1) 2791 return DAG.getNode(ISD::BR, MVT::Other, Chain, N2); 2792 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal 2793 // on the target. 2794 if (N1.getOpcode() == ISD::SETCC && 2795 TLI.isOperationLegal(ISD::BR_CC, MVT::Other)) { 2796 return DAG.getNode(ISD::BR_CC, MVT::Other, Chain, N1.getOperand(2), 2797 N1.getOperand(0), N1.getOperand(1), N2); 2798 } 2799 return SDOperand(); 2800} 2801 2802// Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB. 2803// 2804SDOperand DAGCombiner::visitBR_CC(SDNode *N) { 2805 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1)); 2806 SDOperand CondLHS = N->getOperand(2), CondRHS = N->getOperand(3); 2807 2808 // Use SimplifySetCC to simplify SETCC's. 2809 SDOperand Simp = SimplifySetCC(MVT::i1, CondLHS, CondRHS, CC->get(), false); 2810 if (Simp.Val) AddToWorkList(Simp.Val); 2811 2812 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(Simp.Val); 2813 2814 // fold br_cc true, dest -> br dest (unconditional branch) 2815 if (SCCC && SCCC->getValue()) 2816 return DAG.getNode(ISD::BR, MVT::Other, N->getOperand(0), 2817 N->getOperand(4)); 2818 // fold br_cc false, dest -> unconditional fall through 2819 if (SCCC && SCCC->isNullValue()) 2820 return N->getOperand(0); 2821 2822 // fold to a simpler setcc 2823 if (Simp.Val && Simp.getOpcode() == ISD::SETCC) 2824 return DAG.getNode(ISD::BR_CC, MVT::Other, N->getOperand(0), 2825 Simp.getOperand(2), Simp.getOperand(0), 2826 Simp.getOperand(1), N->getOperand(4)); 2827 return SDOperand(); 2828} 2829 2830 2831/// CombineToPreIndexedLoadStore - Try turning a load / store and a 2832/// pre-indexed load / store when the base pointer is a add or subtract 2833/// and it has other uses besides the load / store. After the 2834/// transformation, the new indexed load / store has effectively folded 2835/// the add / subtract in and all of its other uses are redirected to the 2836/// new load / store. 2837bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) { 2838 if (!AfterLegalize) 2839 return false; 2840 2841 bool isLoad = true; 2842 SDOperand Ptr; 2843 MVT::ValueType VT; 2844 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 2845 if (LD->getAddressingMode() != ISD::UNINDEXED) 2846 return false; 2847 VT = LD->getLoadedVT(); 2848 if (LD->getAddressingMode() != ISD::UNINDEXED && 2849 !TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) && 2850 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT)) 2851 return false; 2852 Ptr = LD->getBasePtr(); 2853 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 2854 if (ST->getAddressingMode() != ISD::UNINDEXED) 2855 return false; 2856 VT = ST->getStoredVT(); 2857 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) && 2858 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT)) 2859 return false; 2860 Ptr = ST->getBasePtr(); 2861 isLoad = false; 2862 } else 2863 return false; 2864 2865 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail 2866 // out. There is no reason to make this a preinc/predec. 2867 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) || 2868 Ptr.Val->hasOneUse()) 2869 return false; 2870 2871 // Ask the target to do addressing mode selection. 2872 SDOperand BasePtr; 2873 SDOperand Offset; 2874 ISD::MemIndexedMode AM = ISD::UNINDEXED; 2875 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG)) 2876 return false; 2877 2878 // Try turning it into a pre-indexed load / store except when: 2879 // 1) The base is a frame index. 2880 // 2) If N is a store and the ptr is either the same as or is a 2881 // predecessor of the value being stored. 2882 // 3) Another use of base ptr is a predecessor of N. If ptr is folded 2883 // that would create a cycle. 2884 // 4) All uses are load / store ops that use it as base ptr. 2885 2886 // Check #1. Preinc'ing a frame index would require copying the stack pointer 2887 // (plus the implicit offset) to a register to preinc anyway. 2888 if (isa<FrameIndexSDNode>(BasePtr)) 2889 return false; 2890 2891 // Check #2. 2892 if (!isLoad) { 2893 SDOperand Val = cast<StoreSDNode>(N)->getValue(); 2894 if (Val == Ptr || Ptr.Val->isPredecessor(Val.Val)) 2895 return false; 2896 } 2897 2898 // Now check for #2 and #3. 2899 bool RealUse = false; 2900 for (SDNode::use_iterator I = Ptr.Val->use_begin(), 2901 E = Ptr.Val->use_end(); I != E; ++I) { 2902 SDNode *Use = *I; 2903 if (Use == N) 2904 continue; 2905 if (Use->isPredecessor(N)) 2906 return false; 2907 2908 if (!((Use->getOpcode() == ISD::LOAD && 2909 cast<LoadSDNode>(Use)->getBasePtr() == Ptr) || 2910 (Use->getOpcode() == ISD::STORE) && 2911 cast<StoreSDNode>(Use)->getBasePtr() == Ptr)) 2912 RealUse = true; 2913 } 2914 if (!RealUse) 2915 return false; 2916 2917 SDOperand Result; 2918 if (isLoad) 2919 Result = DAG.getIndexedLoad(SDOperand(N,0), BasePtr, Offset, AM); 2920 else 2921 Result = DAG.getIndexedStore(SDOperand(N,0), BasePtr, Offset, AM); 2922 ++PreIndexedNodes; 2923 ++NodesCombined; 2924 DOUT << "\nReplacing.4 "; DEBUG(N->dump()); 2925 DOUT << "\nWith: "; DEBUG(Result.Val->dump(&DAG)); 2926 DOUT << '\n'; 2927 std::vector<SDNode*> NowDead; 2928 if (isLoad) { 2929 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(0), 2930 NowDead); 2931 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1), Result.getValue(2), 2932 NowDead); 2933 } else { 2934 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(1), 2935 NowDead); 2936 } 2937 2938 // Nodes can end up on the worklist more than once. Make sure we do 2939 // not process a node that has been replaced. 2940 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 2941 removeFromWorkList(NowDead[i]); 2942 // Finally, since the node is now dead, remove it from the graph. 2943 DAG.DeleteNode(N); 2944 2945 // Replace the uses of Ptr with uses of the updated base value. 2946 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0), 2947 NowDead); 2948 removeFromWorkList(Ptr.Val); 2949 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 2950 removeFromWorkList(NowDead[i]); 2951 DAG.DeleteNode(Ptr.Val); 2952 2953 return true; 2954} 2955 2956/// CombineToPostIndexedLoadStore - Try combine a load / store with a 2957/// add / sub of the base pointer node into a post-indexed load / store. 2958/// The transformation folded the add / subtract into the new indexed 2959/// load / store effectively and all of its uses are redirected to the 2960/// new load / store. 2961bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) { 2962 if (!AfterLegalize) 2963 return false; 2964 2965 bool isLoad = true; 2966 SDOperand Ptr; 2967 MVT::ValueType VT; 2968 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 2969 if (LD->getAddressingMode() != ISD::UNINDEXED) 2970 return false; 2971 VT = LD->getLoadedVT(); 2972 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) && 2973 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT)) 2974 return false; 2975 Ptr = LD->getBasePtr(); 2976 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 2977 if (ST->getAddressingMode() != ISD::UNINDEXED) 2978 return false; 2979 VT = ST->getStoredVT(); 2980 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) && 2981 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT)) 2982 return false; 2983 Ptr = ST->getBasePtr(); 2984 isLoad = false; 2985 } else 2986 return false; 2987 2988 if (Ptr.Val->hasOneUse()) 2989 return false; 2990 2991 for (SDNode::use_iterator I = Ptr.Val->use_begin(), 2992 E = Ptr.Val->use_end(); I != E; ++I) { 2993 SDNode *Op = *I; 2994 if (Op == N || 2995 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB)) 2996 continue; 2997 2998 SDOperand BasePtr; 2999 SDOperand Offset; 3000 ISD::MemIndexedMode AM = ISD::UNINDEXED; 3001 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) { 3002 if (Ptr == Offset) 3003 std::swap(BasePtr, Offset); 3004 if (Ptr != BasePtr) 3005 continue; 3006 3007 // Try turning it into a post-indexed load / store except when 3008 // 1) All uses are load / store ops that use it as base ptr. 3009 // 2) Op must be independent of N, i.e. Op is neither a predecessor 3010 // nor a successor of N. Otherwise, if Op is folded that would 3011 // create a cycle. 3012 3013 // Check for #1. 3014 bool TryNext = false; 3015 for (SDNode::use_iterator II = BasePtr.Val->use_begin(), 3016 EE = BasePtr.Val->use_end(); II != EE; ++II) { 3017 SDNode *Use = *II; 3018 if (Use == Ptr.Val) 3019 continue; 3020 3021 // If all the uses are load / store addresses, then don't do the 3022 // transformation. 3023 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){ 3024 bool RealUse = false; 3025 for (SDNode::use_iterator III = Use->use_begin(), 3026 EEE = Use->use_end(); III != EEE; ++III) { 3027 SDNode *UseUse = *III; 3028 if (!((UseUse->getOpcode() == ISD::LOAD && 3029 cast<LoadSDNode>(UseUse)->getBasePtr().Val == Use) || 3030 (UseUse->getOpcode() == ISD::STORE) && 3031 cast<StoreSDNode>(UseUse)->getBasePtr().Val == Use)) 3032 RealUse = true; 3033 } 3034 3035 if (!RealUse) { 3036 TryNext = true; 3037 break; 3038 } 3039 } 3040 } 3041 if (TryNext) 3042 continue; 3043 3044 // Check for #2 3045 if (!Op->isPredecessor(N) && !N->isPredecessor(Op)) { 3046 SDOperand Result = isLoad 3047 ? DAG.getIndexedLoad(SDOperand(N,0), BasePtr, Offset, AM) 3048 : DAG.getIndexedStore(SDOperand(N,0), BasePtr, Offset, AM); 3049 ++PostIndexedNodes; 3050 ++NodesCombined; 3051 DOUT << "\nReplacing.5 "; DEBUG(N->dump()); 3052 DOUT << "\nWith: "; DEBUG(Result.Val->dump(&DAG)); 3053 DOUT << '\n'; 3054 std::vector<SDNode*> NowDead; 3055 if (isLoad) { 3056 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(0), 3057 NowDead); 3058 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1), Result.getValue(2), 3059 NowDead); 3060 } else { 3061 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(1), 3062 NowDead); 3063 } 3064 3065 // Nodes can end up on the worklist more than once. Make sure we do 3066 // not process a node that has been replaced. 3067 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 3068 removeFromWorkList(NowDead[i]); 3069 // Finally, since the node is now dead, remove it from the graph. 3070 DAG.DeleteNode(N); 3071 3072 // Replace the uses of Use with uses of the updated base value. 3073 DAG.ReplaceAllUsesOfValueWith(SDOperand(Op, 0), 3074 Result.getValue(isLoad ? 1 : 0), 3075 NowDead); 3076 removeFromWorkList(Op); 3077 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 3078 removeFromWorkList(NowDead[i]); 3079 DAG.DeleteNode(Op); 3080 3081 return true; 3082 } 3083 } 3084 } 3085 return false; 3086} 3087 3088 3089SDOperand DAGCombiner::visitLOAD(SDNode *N) { 3090 LoadSDNode *LD = cast<LoadSDNode>(N); 3091 SDOperand Chain = LD->getChain(); 3092 SDOperand Ptr = LD->getBasePtr(); 3093 3094 // If there are no uses of the loaded value, change uses of the chain value 3095 // into uses of the chain input (i.e. delete the dead load). 3096 if (N->hasNUsesOfValue(0, 0)) 3097 return CombineTo(N, DAG.getNode(ISD::UNDEF, N->getValueType(0)), Chain); 3098 3099 // If this load is directly stored, replace the load value with the stored 3100 // value. 3101 // TODO: Handle store large -> read small portion. 3102 // TODO: Handle TRUNCSTORE/LOADEXT 3103 if (LD->getExtensionType() == ISD::NON_EXTLOAD) { 3104 if (ISD::isNON_TRUNCStore(Chain.Val)) { 3105 StoreSDNode *PrevST = cast<StoreSDNode>(Chain); 3106 if (PrevST->getBasePtr() == Ptr && 3107 PrevST->getValue().getValueType() == N->getValueType(0)) 3108 return CombineTo(N, Chain.getOperand(1), Chain); 3109 } 3110 } 3111 3112 if (CombinerAA) { 3113 // Walk up chain skipping non-aliasing memory nodes. 3114 SDOperand BetterChain = FindBetterChain(N, Chain); 3115 3116 // If there is a better chain. 3117 if (Chain != BetterChain) { 3118 SDOperand ReplLoad; 3119 3120 // Replace the chain to void dependency. 3121 if (LD->getExtensionType() == ISD::NON_EXTLOAD) { 3122 ReplLoad = DAG.getLoad(N->getValueType(0), BetterChain, Ptr, 3123 LD->getSrcValue(), LD->getSrcValueOffset()); 3124 } else { 3125 ReplLoad = DAG.getExtLoad(LD->getExtensionType(), 3126 LD->getValueType(0), 3127 BetterChain, Ptr, LD->getSrcValue(), 3128 LD->getSrcValueOffset(), 3129 LD->getLoadedVT()); 3130 } 3131 3132 // Create token factor to keep old chain connected. 3133 SDOperand Token = DAG.getNode(ISD::TokenFactor, MVT::Other, 3134 Chain, ReplLoad.getValue(1)); 3135 3136 // Replace uses with load result and token factor. Don't add users 3137 // to work list. 3138 return CombineTo(N, ReplLoad.getValue(0), Token, false); 3139 } 3140 } 3141 3142 // Try transforming N to an indexed load. 3143 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 3144 return SDOperand(N, 0); 3145 3146 return SDOperand(); 3147} 3148 3149SDOperand DAGCombiner::visitSTORE(SDNode *N) { 3150 StoreSDNode *ST = cast<StoreSDNode>(N); 3151 SDOperand Chain = ST->getChain(); 3152 SDOperand Value = ST->getValue(); 3153 SDOperand Ptr = ST->getBasePtr(); 3154 3155 // If this is a store of a bit convert, store the input value. 3156 // FIXME: This needs to know that the resultant store does not need a 3157 // higher alignment than the original. 3158 if (0 && Value.getOpcode() == ISD::BIT_CONVERT) { 3159 return DAG.getStore(Chain, Value.getOperand(0), Ptr, ST->getSrcValue(), 3160 ST->getSrcValueOffset()); 3161 } 3162 3163 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 3164 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) { 3165 if (Value.getOpcode() != ISD::TargetConstantFP) { 3166 SDOperand Tmp; 3167 switch (CFP->getValueType(0)) { 3168 default: assert(0 && "Unknown FP type"); 3169 case MVT::f32: 3170 if (!AfterLegalize || TLI.isTypeLegal(MVT::i32)) { 3171 Tmp = DAG.getConstant(FloatToBits(CFP->getValue()), MVT::i32); 3172 return DAG.getStore(Chain, Tmp, Ptr, ST->getSrcValue(), 3173 ST->getSrcValueOffset()); 3174 } 3175 break; 3176 case MVT::f64: 3177 if (!AfterLegalize || TLI.isTypeLegal(MVT::i64)) { 3178 Tmp = DAG.getConstant(DoubleToBits(CFP->getValue()), MVT::i64); 3179 return DAG.getStore(Chain, Tmp, Ptr, ST->getSrcValue(), 3180 ST->getSrcValueOffset()); 3181 } else if (TLI.isTypeLegal(MVT::i32)) { 3182 // Many FP stores are not make apparent until after legalize, e.g. for 3183 // argument passing. Since this is so common, custom legalize the 3184 // 64-bit integer store into two 32-bit stores. 3185 uint64_t Val = DoubleToBits(CFP->getValue()); 3186 SDOperand Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32); 3187 SDOperand Hi = DAG.getConstant(Val >> 32, MVT::i32); 3188 if (!TLI.isLittleEndian()) std::swap(Lo, Hi); 3189 3190 SDOperand St0 = DAG.getStore(Chain, Lo, Ptr, ST->getSrcValue(), 3191 ST->getSrcValueOffset()); 3192 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 3193 DAG.getConstant(4, Ptr.getValueType())); 3194 SDOperand St1 = DAG.getStore(Chain, Hi, Ptr, ST->getSrcValue(), 3195 ST->getSrcValueOffset()+4); 3196 return DAG.getNode(ISD::TokenFactor, MVT::Other, St0, St1); 3197 } 3198 break; 3199 } 3200 } 3201 } 3202 3203 if (CombinerAA) { 3204 // Walk up chain skipping non-aliasing memory nodes. 3205 SDOperand BetterChain = FindBetterChain(N, Chain); 3206 3207 // If there is a better chain. 3208 if (Chain != BetterChain) { 3209 // Replace the chain to avoid dependency. 3210 SDOperand ReplStore; 3211 if (ST->isTruncatingStore()) { 3212 ReplStore = DAG.getTruncStore(BetterChain, Value, Ptr, 3213 ST->getSrcValue(),ST->getSrcValueOffset(), ST->getStoredVT()); 3214 } else { 3215 ReplStore = DAG.getStore(BetterChain, Value, Ptr, 3216 ST->getSrcValue(), ST->getSrcValueOffset()); 3217 } 3218 3219 // Create token to keep both nodes around. 3220 SDOperand Token = 3221 DAG.getNode(ISD::TokenFactor, MVT::Other, Chain, ReplStore); 3222 3223 // Don't add users to work list. 3224 return CombineTo(N, Token, false); 3225 } 3226 } 3227 3228 // Try transforming N to an indexed store. 3229 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 3230 return SDOperand(N, 0); 3231 3232 return SDOperand(); 3233} 3234 3235SDOperand DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) { 3236 SDOperand InVec = N->getOperand(0); 3237 SDOperand InVal = N->getOperand(1); 3238 SDOperand EltNo = N->getOperand(2); 3239 3240 // If the invec is a BUILD_VECTOR and if EltNo is a constant, build a new 3241 // vector with the inserted element. 3242 if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) { 3243 unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue(); 3244 SmallVector<SDOperand, 8> Ops(InVec.Val->op_begin(), InVec.Val->op_end()); 3245 if (Elt < Ops.size()) 3246 Ops[Elt] = InVal; 3247 return DAG.getNode(ISD::BUILD_VECTOR, InVec.getValueType(), 3248 &Ops[0], Ops.size()); 3249 } 3250 3251 return SDOperand(); 3252} 3253 3254SDOperand DAGCombiner::visitVINSERT_VECTOR_ELT(SDNode *N) { 3255 SDOperand InVec = N->getOperand(0); 3256 SDOperand InVal = N->getOperand(1); 3257 SDOperand EltNo = N->getOperand(2); 3258 SDOperand NumElts = N->getOperand(3); 3259 SDOperand EltType = N->getOperand(4); 3260 3261 // If the invec is a VBUILD_VECTOR and if EltNo is a constant, build a new 3262 // vector with the inserted element. 3263 if (InVec.getOpcode() == ISD::VBUILD_VECTOR && isa<ConstantSDNode>(EltNo)) { 3264 unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue(); 3265 SmallVector<SDOperand, 8> Ops(InVec.Val->op_begin(), InVec.Val->op_end()); 3266 if (Elt < Ops.size()-2) 3267 Ops[Elt] = InVal; 3268 return DAG.getNode(ISD::VBUILD_VECTOR, InVec.getValueType(), 3269 &Ops[0], Ops.size()); 3270 } 3271 3272 return SDOperand(); 3273} 3274 3275SDOperand DAGCombiner::visitVBUILD_VECTOR(SDNode *N) { 3276 unsigned NumInScalars = N->getNumOperands()-2; 3277 SDOperand NumElts = N->getOperand(NumInScalars); 3278 SDOperand EltType = N->getOperand(NumInScalars+1); 3279 3280 // Check to see if this is a VBUILD_VECTOR of a bunch of VEXTRACT_VECTOR_ELT 3281 // operations. If so, and if the EXTRACT_ELT vector inputs come from at most 3282 // two distinct vectors, turn this into a shuffle node. 3283 SDOperand VecIn1, VecIn2; 3284 for (unsigned i = 0; i != NumInScalars; ++i) { 3285 // Ignore undef inputs. 3286 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 3287 3288 // If this input is something other than a VEXTRACT_VECTOR_ELT with a 3289 // constant index, bail out. 3290 if (N->getOperand(i).getOpcode() != ISD::VEXTRACT_VECTOR_ELT || 3291 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) { 3292 VecIn1 = VecIn2 = SDOperand(0, 0); 3293 break; 3294 } 3295 3296 // If the input vector type disagrees with the result of the vbuild_vector, 3297 // we can't make a shuffle. 3298 SDOperand ExtractedFromVec = N->getOperand(i).getOperand(0); 3299 if (*(ExtractedFromVec.Val->op_end()-2) != NumElts || 3300 *(ExtractedFromVec.Val->op_end()-1) != EltType) { 3301 VecIn1 = VecIn2 = SDOperand(0, 0); 3302 break; 3303 } 3304 3305 // Otherwise, remember this. We allow up to two distinct input vectors. 3306 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2) 3307 continue; 3308 3309 if (VecIn1.Val == 0) { 3310 VecIn1 = ExtractedFromVec; 3311 } else if (VecIn2.Val == 0) { 3312 VecIn2 = ExtractedFromVec; 3313 } else { 3314 // Too many inputs. 3315 VecIn1 = VecIn2 = SDOperand(0, 0); 3316 break; 3317 } 3318 } 3319 3320 // If everything is good, we can make a shuffle operation. 3321 if (VecIn1.Val) { 3322 SmallVector<SDOperand, 8> BuildVecIndices; 3323 for (unsigned i = 0; i != NumInScalars; ++i) { 3324 if (N->getOperand(i).getOpcode() == ISD::UNDEF) { 3325 BuildVecIndices.push_back(DAG.getNode(ISD::UNDEF, TLI.getPointerTy())); 3326 continue; 3327 } 3328 3329 SDOperand Extract = N->getOperand(i); 3330 3331 // If extracting from the first vector, just use the index directly. 3332 if (Extract.getOperand(0) == VecIn1) { 3333 BuildVecIndices.push_back(Extract.getOperand(1)); 3334 continue; 3335 } 3336 3337 // Otherwise, use InIdx + VecSize 3338 unsigned Idx = cast<ConstantSDNode>(Extract.getOperand(1))->getValue(); 3339 BuildVecIndices.push_back(DAG.getConstant(Idx+NumInScalars, 3340 TLI.getPointerTy())); 3341 } 3342 3343 // Add count and size info. 3344 BuildVecIndices.push_back(NumElts); 3345 BuildVecIndices.push_back(DAG.getValueType(TLI.getPointerTy())); 3346 3347 // Return the new VVECTOR_SHUFFLE node. 3348 SDOperand Ops[5]; 3349 Ops[0] = VecIn1; 3350 if (VecIn2.Val) { 3351 Ops[1] = VecIn2; 3352 } else { 3353 // Use an undef vbuild_vector as input for the second operand. 3354 std::vector<SDOperand> UnOps(NumInScalars, 3355 DAG.getNode(ISD::UNDEF, 3356 cast<VTSDNode>(EltType)->getVT())); 3357 UnOps.push_back(NumElts); 3358 UnOps.push_back(EltType); 3359 Ops[1] = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, 3360 &UnOps[0], UnOps.size()); 3361 AddToWorkList(Ops[1].Val); 3362 } 3363 Ops[2] = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, 3364 &BuildVecIndices[0], BuildVecIndices.size()); 3365 Ops[3] = NumElts; 3366 Ops[4] = EltType; 3367 return DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector, Ops, 5); 3368 } 3369 3370 return SDOperand(); 3371} 3372 3373SDOperand DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) { 3374 SDOperand ShufMask = N->getOperand(2); 3375 unsigned NumElts = ShufMask.getNumOperands(); 3376 3377 // If the shuffle mask is an identity operation on the LHS, return the LHS. 3378 bool isIdentity = true; 3379 for (unsigned i = 0; i != NumElts; ++i) { 3380 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF && 3381 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i) { 3382 isIdentity = false; 3383 break; 3384 } 3385 } 3386 if (isIdentity) return N->getOperand(0); 3387 3388 // If the shuffle mask is an identity operation on the RHS, return the RHS. 3389 isIdentity = true; 3390 for (unsigned i = 0; i != NumElts; ++i) { 3391 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF && 3392 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i+NumElts) { 3393 isIdentity = false; 3394 break; 3395 } 3396 } 3397 if (isIdentity) return N->getOperand(1); 3398 3399 // Check if the shuffle is a unary shuffle, i.e. one of the vectors is not 3400 // needed at all. 3401 bool isUnary = true; 3402 bool isSplat = true; 3403 int VecNum = -1; 3404 unsigned BaseIdx = 0; 3405 for (unsigned i = 0; i != NumElts; ++i) 3406 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF) { 3407 unsigned Idx = cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue(); 3408 int V = (Idx < NumElts) ? 0 : 1; 3409 if (VecNum == -1) { 3410 VecNum = V; 3411 BaseIdx = Idx; 3412 } else { 3413 if (BaseIdx != Idx) 3414 isSplat = false; 3415 if (VecNum != V) { 3416 isUnary = false; 3417 break; 3418 } 3419 } 3420 } 3421 3422 SDOperand N0 = N->getOperand(0); 3423 SDOperand N1 = N->getOperand(1); 3424 // Normalize unary shuffle so the RHS is undef. 3425 if (isUnary && VecNum == 1) 3426 std::swap(N0, N1); 3427 3428 // If it is a splat, check if the argument vector is a build_vector with 3429 // all scalar elements the same. 3430 if (isSplat) { 3431 SDNode *V = N0.Val; 3432 if (V->getOpcode() == ISD::BIT_CONVERT) 3433 V = V->getOperand(0).Val; 3434 if (V->getOpcode() == ISD::BUILD_VECTOR) { 3435 unsigned NumElems = V->getNumOperands()-2; 3436 if (NumElems > BaseIdx) { 3437 SDOperand Base; 3438 bool AllSame = true; 3439 for (unsigned i = 0; i != NumElems; ++i) { 3440 if (V->getOperand(i).getOpcode() != ISD::UNDEF) { 3441 Base = V->getOperand(i); 3442 break; 3443 } 3444 } 3445 // Splat of <u, u, u, u>, return <u, u, u, u> 3446 if (!Base.Val) 3447 return N0; 3448 for (unsigned i = 0; i != NumElems; ++i) { 3449 if (V->getOperand(i).getOpcode() != ISD::UNDEF && 3450 V->getOperand(i) != Base) { 3451 AllSame = false; 3452 break; 3453 } 3454 } 3455 // Splat of <x, x, x, x>, return <x, x, x, x> 3456 if (AllSame) 3457 return N0; 3458 } 3459 } 3460 } 3461 3462 // If it is a unary or the LHS and the RHS are the same node, turn the RHS 3463 // into an undef. 3464 if (isUnary || N0 == N1) { 3465 if (N0.getOpcode() == ISD::UNDEF) 3466 return DAG.getNode(ISD::UNDEF, N->getValueType(0)); 3467 // Check the SHUFFLE mask, mapping any inputs from the 2nd operand into the 3468 // first operand. 3469 SmallVector<SDOperand, 8> MappedOps; 3470 for (unsigned i = 0, e = ShufMask.getNumOperands(); i != e; ++i) { 3471 if (ShufMask.getOperand(i).getOpcode() == ISD::UNDEF || 3472 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() < NumElts) { 3473 MappedOps.push_back(ShufMask.getOperand(i)); 3474 } else { 3475 unsigned NewIdx = 3476 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() - NumElts; 3477 MappedOps.push_back(DAG.getConstant(NewIdx, MVT::i32)); 3478 } 3479 } 3480 ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMask.getValueType(), 3481 &MappedOps[0], MappedOps.size()); 3482 AddToWorkList(ShufMask.Val); 3483 return DAG.getNode(ISD::VECTOR_SHUFFLE, N->getValueType(0), 3484 N0, 3485 DAG.getNode(ISD::UNDEF, N->getValueType(0)), 3486 ShufMask); 3487 } 3488 3489 return SDOperand(); 3490} 3491 3492SDOperand DAGCombiner::visitVVECTOR_SHUFFLE(SDNode *N) { 3493 SDOperand ShufMask = N->getOperand(2); 3494 unsigned NumElts = ShufMask.getNumOperands()-2; 3495 3496 // If the shuffle mask is an identity operation on the LHS, return the LHS. 3497 bool isIdentity = true; 3498 for (unsigned i = 0; i != NumElts; ++i) { 3499 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF && 3500 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i) { 3501 isIdentity = false; 3502 break; 3503 } 3504 } 3505 if (isIdentity) return N->getOperand(0); 3506 3507 // If the shuffle mask is an identity operation on the RHS, return the RHS. 3508 isIdentity = true; 3509 for (unsigned i = 0; i != NumElts; ++i) { 3510 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF && 3511 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i+NumElts) { 3512 isIdentity = false; 3513 break; 3514 } 3515 } 3516 if (isIdentity) return N->getOperand(1); 3517 3518 // Check if the shuffle is a unary shuffle, i.e. one of the vectors is not 3519 // needed at all. 3520 bool isUnary = true; 3521 bool isSplat = true; 3522 int VecNum = -1; 3523 unsigned BaseIdx = 0; 3524 for (unsigned i = 0; i != NumElts; ++i) 3525 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF) { 3526 unsigned Idx = cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue(); 3527 int V = (Idx < NumElts) ? 0 : 1; 3528 if (VecNum == -1) { 3529 VecNum = V; 3530 BaseIdx = Idx; 3531 } else { 3532 if (BaseIdx != Idx) 3533 isSplat = false; 3534 if (VecNum != V) { 3535 isUnary = false; 3536 break; 3537 } 3538 } 3539 } 3540 3541 SDOperand N0 = N->getOperand(0); 3542 SDOperand N1 = N->getOperand(1); 3543 // Normalize unary shuffle so the RHS is undef. 3544 if (isUnary && VecNum == 1) 3545 std::swap(N0, N1); 3546 3547 // If it is a splat, check if the argument vector is a build_vector with 3548 // all scalar elements the same. 3549 if (isSplat) { 3550 SDNode *V = N0.Val; 3551 3552 // If this is a vbit convert that changes the element type of the vector but 3553 // not the number of vector elements, look through it. Be careful not to 3554 // look though conversions that change things like v4f32 to v2f64. 3555 if (V->getOpcode() == ISD::VBIT_CONVERT) { 3556 SDOperand ConvInput = V->getOperand(0); 3557 if (ConvInput.getValueType() == MVT::Vector && 3558 NumElts == 3559 ConvInput.getConstantOperandVal(ConvInput.getNumOperands()-2)) 3560 V = ConvInput.Val; 3561 } 3562 3563 if (V->getOpcode() == ISD::VBUILD_VECTOR) { 3564 unsigned NumElems = V->getNumOperands()-2; 3565 if (NumElems > BaseIdx) { 3566 SDOperand Base; 3567 bool AllSame = true; 3568 for (unsigned i = 0; i != NumElems; ++i) { 3569 if (V->getOperand(i).getOpcode() != ISD::UNDEF) { 3570 Base = V->getOperand(i); 3571 break; 3572 } 3573 } 3574 // Splat of <u, u, u, u>, return <u, u, u, u> 3575 if (!Base.Val) 3576 return N0; 3577 for (unsigned i = 0; i != NumElems; ++i) { 3578 if (V->getOperand(i).getOpcode() != ISD::UNDEF && 3579 V->getOperand(i) != Base) { 3580 AllSame = false; 3581 break; 3582 } 3583 } 3584 // Splat of <x, x, x, x>, return <x, x, x, x> 3585 if (AllSame) 3586 return N0; 3587 } 3588 } 3589 } 3590 3591 // If it is a unary or the LHS and the RHS are the same node, turn the RHS 3592 // into an undef. 3593 if (isUnary || N0 == N1) { 3594 // Check the SHUFFLE mask, mapping any inputs from the 2nd operand into the 3595 // first operand. 3596 SmallVector<SDOperand, 8> MappedOps; 3597 for (unsigned i = 0; i != NumElts; ++i) { 3598 if (ShufMask.getOperand(i).getOpcode() == ISD::UNDEF || 3599 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() < NumElts) { 3600 MappedOps.push_back(ShufMask.getOperand(i)); 3601 } else { 3602 unsigned NewIdx = 3603 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() - NumElts; 3604 MappedOps.push_back(DAG.getConstant(NewIdx, MVT::i32)); 3605 } 3606 } 3607 // Add the type/#elts values. 3608 MappedOps.push_back(ShufMask.getOperand(NumElts)); 3609 MappedOps.push_back(ShufMask.getOperand(NumElts+1)); 3610 3611 ShufMask = DAG.getNode(ISD::VBUILD_VECTOR, ShufMask.getValueType(), 3612 &MappedOps[0], MappedOps.size()); 3613 AddToWorkList(ShufMask.Val); 3614 3615 // Build the undef vector. 3616 SDOperand UDVal = DAG.getNode(ISD::UNDEF, MappedOps[0].getValueType()); 3617 for (unsigned i = 0; i != NumElts; ++i) 3618 MappedOps[i] = UDVal; 3619 MappedOps[NumElts ] = *(N0.Val->op_end()-2); 3620 MappedOps[NumElts+1] = *(N0.Val->op_end()-1); 3621 UDVal = DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, 3622 &MappedOps[0], MappedOps.size()); 3623 3624 return DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector, 3625 N0, UDVal, ShufMask, 3626 MappedOps[NumElts], MappedOps[NumElts+1]); 3627 } 3628 3629 return SDOperand(); 3630} 3631 3632/// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform 3633/// a VAND to a vector_shuffle with the destination vector and a zero vector. 3634/// e.g. VAND V, <0xffffffff, 0, 0xffffffff, 0>. ==> 3635/// vector_shuffle V, Zero, <0, 4, 2, 4> 3636SDOperand DAGCombiner::XformToShuffleWithZero(SDNode *N) { 3637 SDOperand LHS = N->getOperand(0); 3638 SDOperand RHS = N->getOperand(1); 3639 if (N->getOpcode() == ISD::VAND) { 3640 SDOperand DstVecSize = *(LHS.Val->op_end()-2); 3641 SDOperand DstVecEVT = *(LHS.Val->op_end()-1); 3642 if (RHS.getOpcode() == ISD::VBIT_CONVERT) 3643 RHS = RHS.getOperand(0); 3644 if (RHS.getOpcode() == ISD::VBUILD_VECTOR) { 3645 std::vector<SDOperand> IdxOps; 3646 unsigned NumOps = RHS.getNumOperands(); 3647 unsigned NumElts = NumOps-2; 3648 MVT::ValueType EVT = cast<VTSDNode>(RHS.getOperand(NumOps-1))->getVT(); 3649 for (unsigned i = 0; i != NumElts; ++i) { 3650 SDOperand Elt = RHS.getOperand(i); 3651 if (!isa<ConstantSDNode>(Elt)) 3652 return SDOperand(); 3653 else if (cast<ConstantSDNode>(Elt)->isAllOnesValue()) 3654 IdxOps.push_back(DAG.getConstant(i, EVT)); 3655 else if (cast<ConstantSDNode>(Elt)->isNullValue()) 3656 IdxOps.push_back(DAG.getConstant(NumElts, EVT)); 3657 else 3658 return SDOperand(); 3659 } 3660 3661 // Let's see if the target supports this vector_shuffle. 3662 if (!TLI.isVectorClearMaskLegal(IdxOps, EVT, DAG)) 3663 return SDOperand(); 3664 3665 // Return the new VVECTOR_SHUFFLE node. 3666 SDOperand NumEltsNode = DAG.getConstant(NumElts, MVT::i32); 3667 SDOperand EVTNode = DAG.getValueType(EVT); 3668 std::vector<SDOperand> Ops; 3669 LHS = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, LHS, NumEltsNode, 3670 EVTNode); 3671 Ops.push_back(LHS); 3672 AddToWorkList(LHS.Val); 3673 std::vector<SDOperand> ZeroOps(NumElts, DAG.getConstant(0, EVT)); 3674 ZeroOps.push_back(NumEltsNode); 3675 ZeroOps.push_back(EVTNode); 3676 Ops.push_back(DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, 3677 &ZeroOps[0], ZeroOps.size())); 3678 IdxOps.push_back(NumEltsNode); 3679 IdxOps.push_back(EVTNode); 3680 Ops.push_back(DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, 3681 &IdxOps[0], IdxOps.size())); 3682 Ops.push_back(NumEltsNode); 3683 Ops.push_back(EVTNode); 3684 SDOperand Result = DAG.getNode(ISD::VVECTOR_SHUFFLE, MVT::Vector, 3685 &Ops[0], Ops.size()); 3686 if (NumEltsNode != DstVecSize || EVTNode != DstVecEVT) { 3687 Result = DAG.getNode(ISD::VBIT_CONVERT, MVT::Vector, Result, 3688 DstVecSize, DstVecEVT); 3689 } 3690 return Result; 3691 } 3692 } 3693 return SDOperand(); 3694} 3695 3696/// visitVBinOp - Visit a binary vector operation, like VADD. IntOp indicates 3697/// the scalar operation of the vop if it is operating on an integer vector 3698/// (e.g. ADD) and FPOp indicates the FP version (e.g. FADD). 3699SDOperand DAGCombiner::visitVBinOp(SDNode *N, ISD::NodeType IntOp, 3700 ISD::NodeType FPOp) { 3701 MVT::ValueType EltType = cast<VTSDNode>(*(N->op_end()-1))->getVT(); 3702 ISD::NodeType ScalarOp = MVT::isInteger(EltType) ? IntOp : FPOp; 3703 SDOperand LHS = N->getOperand(0); 3704 SDOperand RHS = N->getOperand(1); 3705 SDOperand Shuffle = XformToShuffleWithZero(N); 3706 if (Shuffle.Val) return Shuffle; 3707 3708 // If the LHS and RHS are VBUILD_VECTOR nodes, see if we can constant fold 3709 // this operation. 3710 if (LHS.getOpcode() == ISD::VBUILD_VECTOR && 3711 RHS.getOpcode() == ISD::VBUILD_VECTOR) { 3712 SmallVector<SDOperand, 8> Ops; 3713 for (unsigned i = 0, e = LHS.getNumOperands()-2; i != e; ++i) { 3714 SDOperand LHSOp = LHS.getOperand(i); 3715 SDOperand RHSOp = RHS.getOperand(i); 3716 // If these two elements can't be folded, bail out. 3717 if ((LHSOp.getOpcode() != ISD::UNDEF && 3718 LHSOp.getOpcode() != ISD::Constant && 3719 LHSOp.getOpcode() != ISD::ConstantFP) || 3720 (RHSOp.getOpcode() != ISD::UNDEF && 3721 RHSOp.getOpcode() != ISD::Constant && 3722 RHSOp.getOpcode() != ISD::ConstantFP)) 3723 break; 3724 // Can't fold divide by zero. 3725 if (N->getOpcode() == ISD::VSDIV || N->getOpcode() == ISD::VUDIV) { 3726 if ((RHSOp.getOpcode() == ISD::Constant && 3727 cast<ConstantSDNode>(RHSOp.Val)->isNullValue()) || 3728 (RHSOp.getOpcode() == ISD::ConstantFP && 3729 !cast<ConstantFPSDNode>(RHSOp.Val)->getValue())) 3730 break; 3731 } 3732 Ops.push_back(DAG.getNode(ScalarOp, EltType, LHSOp, RHSOp)); 3733 AddToWorkList(Ops.back().Val); 3734 assert((Ops.back().getOpcode() == ISD::UNDEF || 3735 Ops.back().getOpcode() == ISD::Constant || 3736 Ops.back().getOpcode() == ISD::ConstantFP) && 3737 "Scalar binop didn't fold!"); 3738 } 3739 3740 if (Ops.size() == LHS.getNumOperands()-2) { 3741 Ops.push_back(*(LHS.Val->op_end()-2)); 3742 Ops.push_back(*(LHS.Val->op_end()-1)); 3743 return DAG.getNode(ISD::VBUILD_VECTOR, MVT::Vector, &Ops[0], Ops.size()); 3744 } 3745 } 3746 3747 return SDOperand(); 3748} 3749 3750SDOperand DAGCombiner::SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2){ 3751 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!"); 3752 3753 SDOperand SCC = SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), N1, N2, 3754 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 3755 // If we got a simplified select_cc node back from SimplifySelectCC, then 3756 // break it down into a new SETCC node, and a new SELECT node, and then return 3757 // the SELECT node, since we were called with a SELECT node. 3758 if (SCC.Val) { 3759 // Check to see if we got a select_cc back (to turn into setcc/select). 3760 // Otherwise, just return whatever node we got back, like fabs. 3761 if (SCC.getOpcode() == ISD::SELECT_CC) { 3762 SDOperand SETCC = DAG.getNode(ISD::SETCC, N0.getValueType(), 3763 SCC.getOperand(0), SCC.getOperand(1), 3764 SCC.getOperand(4)); 3765 AddToWorkList(SETCC.Val); 3766 return DAG.getNode(ISD::SELECT, SCC.getValueType(), SCC.getOperand(2), 3767 SCC.getOperand(3), SETCC); 3768 } 3769 return SCC; 3770 } 3771 return SDOperand(); 3772} 3773 3774/// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS 3775/// are the two values being selected between, see if we can simplify the 3776/// select. Callers of this should assume that TheSelect is deleted if this 3777/// returns true. As such, they should return the appropriate thing (e.g. the 3778/// node) back to the top-level of the DAG combiner loop to avoid it being 3779/// looked at. 3780/// 3781bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDOperand LHS, 3782 SDOperand RHS) { 3783 3784 // If this is a select from two identical things, try to pull the operation 3785 // through the select. 3786 if (LHS.getOpcode() == RHS.getOpcode() && LHS.hasOneUse() && RHS.hasOneUse()){ 3787 // If this is a load and the token chain is identical, replace the select 3788 // of two loads with a load through a select of the address to load from. 3789 // This triggers in things like "select bool X, 10.0, 123.0" after the FP 3790 // constants have been dropped into the constant pool. 3791 if (LHS.getOpcode() == ISD::LOAD && 3792 // Token chains must be identical. 3793 LHS.getOperand(0) == RHS.getOperand(0)) { 3794 LoadSDNode *LLD = cast<LoadSDNode>(LHS); 3795 LoadSDNode *RLD = cast<LoadSDNode>(RHS); 3796 3797 // If this is an EXTLOAD, the VT's must match. 3798 if (LLD->getLoadedVT() == RLD->getLoadedVT()) { 3799 // FIXME: this conflates two src values, discarding one. This is not 3800 // the right thing to do, but nothing uses srcvalues now. When they do, 3801 // turn SrcValue into a list of locations. 3802 SDOperand Addr; 3803 if (TheSelect->getOpcode() == ISD::SELECT) { 3804 // Check that the condition doesn't reach either load. If so, folding 3805 // this will induce a cycle into the DAG. 3806 if (!LLD->isPredecessor(TheSelect->getOperand(0).Val) && 3807 !RLD->isPredecessor(TheSelect->getOperand(0).Val)) { 3808 Addr = DAG.getNode(ISD::SELECT, LLD->getBasePtr().getValueType(), 3809 TheSelect->getOperand(0), LLD->getBasePtr(), 3810 RLD->getBasePtr()); 3811 } 3812 } else { 3813 // Check that the condition doesn't reach either load. If so, folding 3814 // this will induce a cycle into the DAG. 3815 if (!LLD->isPredecessor(TheSelect->getOperand(0).Val) && 3816 !RLD->isPredecessor(TheSelect->getOperand(0).Val) && 3817 !LLD->isPredecessor(TheSelect->getOperand(1).Val) && 3818 !RLD->isPredecessor(TheSelect->getOperand(1).Val)) { 3819 Addr = DAG.getNode(ISD::SELECT_CC, LLD->getBasePtr().getValueType(), 3820 TheSelect->getOperand(0), 3821 TheSelect->getOperand(1), 3822 LLD->getBasePtr(), RLD->getBasePtr(), 3823 TheSelect->getOperand(4)); 3824 } 3825 } 3826 3827 if (Addr.Val) { 3828 SDOperand Load; 3829 if (LLD->getExtensionType() == ISD::NON_EXTLOAD) 3830 Load = DAG.getLoad(TheSelect->getValueType(0), LLD->getChain(), 3831 Addr,LLD->getSrcValue(), 3832 LLD->getSrcValueOffset()); 3833 else { 3834 Load = DAG.getExtLoad(LLD->getExtensionType(), 3835 TheSelect->getValueType(0), 3836 LLD->getChain(), Addr, LLD->getSrcValue(), 3837 LLD->getSrcValueOffset(), 3838 LLD->getLoadedVT()); 3839 } 3840 // Users of the select now use the result of the load. 3841 CombineTo(TheSelect, Load); 3842 3843 // Users of the old loads now use the new load's chain. We know the 3844 // old-load value is dead now. 3845 CombineTo(LHS.Val, Load.getValue(0), Load.getValue(1)); 3846 CombineTo(RHS.Val, Load.getValue(0), Load.getValue(1)); 3847 return true; 3848 } 3849 } 3850 } 3851 } 3852 3853 return false; 3854} 3855 3856SDOperand DAGCombiner::SimplifySelectCC(SDOperand N0, SDOperand N1, 3857 SDOperand N2, SDOperand N3, 3858 ISD::CondCode CC) { 3859 3860 MVT::ValueType VT = N2.getValueType(); 3861 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 3862 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val); 3863 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.Val); 3864 3865 // Determine if the condition we're dealing with is constant 3866 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false); 3867 if (SCC.Val) AddToWorkList(SCC.Val); 3868 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val); 3869 3870 // fold select_cc true, x, y -> x 3871 if (SCCC && SCCC->getValue()) 3872 return N2; 3873 // fold select_cc false, x, y -> y 3874 if (SCCC && SCCC->getValue() == 0) 3875 return N3; 3876 3877 // Check to see if we can simplify the select into an fabs node 3878 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) { 3879 // Allow either -0.0 or 0.0 3880 if (CFP->getValue() == 0.0) { 3881 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs 3882 if ((CC == ISD::SETGE || CC == ISD::SETGT) && 3883 N0 == N2 && N3.getOpcode() == ISD::FNEG && 3884 N2 == N3.getOperand(0)) 3885 return DAG.getNode(ISD::FABS, VT, N0); 3886 3887 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs 3888 if ((CC == ISD::SETLT || CC == ISD::SETLE) && 3889 N0 == N3 && N2.getOpcode() == ISD::FNEG && 3890 N2.getOperand(0) == N3) 3891 return DAG.getNode(ISD::FABS, VT, N3); 3892 } 3893 } 3894 3895 // Check to see if we can perform the "gzip trick", transforming 3896 // select_cc setlt X, 0, A, 0 -> and (sra X, size(X)-1), A 3897 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT && 3898 MVT::isInteger(N0.getValueType()) && 3899 MVT::isInteger(N2.getValueType()) && 3900 (N1C->isNullValue() || // (a < 0) ? b : 0 3901 (N1C->getValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0 3902 MVT::ValueType XType = N0.getValueType(); 3903 MVT::ValueType AType = N2.getValueType(); 3904 if (XType >= AType) { 3905 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a 3906 // single-bit constant. 3907 if (N2C && ((N2C->getValue() & (N2C->getValue()-1)) == 0)) { 3908 unsigned ShCtV = Log2_64(N2C->getValue()); 3909 ShCtV = MVT::getSizeInBits(XType)-ShCtV-1; 3910 SDOperand ShCt = DAG.getConstant(ShCtV, TLI.getShiftAmountTy()); 3911 SDOperand Shift = DAG.getNode(ISD::SRL, XType, N0, ShCt); 3912 AddToWorkList(Shift.Val); 3913 if (XType > AType) { 3914 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift); 3915 AddToWorkList(Shift.Val); 3916 } 3917 return DAG.getNode(ISD::AND, AType, Shift, N2); 3918 } 3919 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0, 3920 DAG.getConstant(MVT::getSizeInBits(XType)-1, 3921 TLI.getShiftAmountTy())); 3922 AddToWorkList(Shift.Val); 3923 if (XType > AType) { 3924 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift); 3925 AddToWorkList(Shift.Val); 3926 } 3927 return DAG.getNode(ISD::AND, AType, Shift, N2); 3928 } 3929 } 3930 3931 // fold select C, 16, 0 -> shl C, 4 3932 if (N2C && N3C && N3C->isNullValue() && isPowerOf2_64(N2C->getValue()) && 3933 TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult) { 3934 // Get a SetCC of the condition 3935 // FIXME: Should probably make sure that setcc is legal if we ever have a 3936 // target where it isn't. 3937 SDOperand Temp, SCC; 3938 // cast from setcc result type to select result type 3939 if (AfterLegalize) { 3940 SCC = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC); 3941 if (N2.getValueType() < SCC.getValueType()) 3942 Temp = DAG.getZeroExtendInReg(SCC, N2.getValueType()); 3943 else 3944 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC); 3945 } else { 3946 SCC = DAG.getSetCC(MVT::i1, N0, N1, CC); 3947 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC); 3948 } 3949 AddToWorkList(SCC.Val); 3950 AddToWorkList(Temp.Val); 3951 // shl setcc result by log2 n2c 3952 return DAG.getNode(ISD::SHL, N2.getValueType(), Temp, 3953 DAG.getConstant(Log2_64(N2C->getValue()), 3954 TLI.getShiftAmountTy())); 3955 } 3956 3957 // Check to see if this is the equivalent of setcc 3958 // FIXME: Turn all of these into setcc if setcc if setcc is legal 3959 // otherwise, go ahead with the folds. 3960 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getValue() == 1ULL)) { 3961 MVT::ValueType XType = N0.getValueType(); 3962 if (TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultTy())) { 3963 SDOperand Res = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC); 3964 if (Res.getValueType() != VT) 3965 Res = DAG.getNode(ISD::ZERO_EXTEND, VT, Res); 3966 return Res; 3967 } 3968 3969 // seteq X, 0 -> srl (ctlz X, log2(size(X))) 3970 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ && 3971 TLI.isOperationLegal(ISD::CTLZ, XType)) { 3972 SDOperand Ctlz = DAG.getNode(ISD::CTLZ, XType, N0); 3973 return DAG.getNode(ISD::SRL, XType, Ctlz, 3974 DAG.getConstant(Log2_32(MVT::getSizeInBits(XType)), 3975 TLI.getShiftAmountTy())); 3976 } 3977 // setgt X, 0 -> srl (and (-X, ~X), size(X)-1) 3978 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) { 3979 SDOperand NegN0 = DAG.getNode(ISD::SUB, XType, DAG.getConstant(0, XType), 3980 N0); 3981 SDOperand NotN0 = DAG.getNode(ISD::XOR, XType, N0, 3982 DAG.getConstant(~0ULL, XType)); 3983 return DAG.getNode(ISD::SRL, XType, 3984 DAG.getNode(ISD::AND, XType, NegN0, NotN0), 3985 DAG.getConstant(MVT::getSizeInBits(XType)-1, 3986 TLI.getShiftAmountTy())); 3987 } 3988 // setgt X, -1 -> xor (srl (X, size(X)-1), 1) 3989 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) { 3990 SDOperand Sign = DAG.getNode(ISD::SRL, XType, N0, 3991 DAG.getConstant(MVT::getSizeInBits(XType)-1, 3992 TLI.getShiftAmountTy())); 3993 return DAG.getNode(ISD::XOR, XType, Sign, DAG.getConstant(1, XType)); 3994 } 3995 } 3996 3997 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X -> 3998 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 3999 if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) && 4000 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1)) { 4001 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N2.getOperand(0))) { 4002 MVT::ValueType XType = N0.getValueType(); 4003 if (SubC->isNullValue() && MVT::isInteger(XType)) { 4004 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0, 4005 DAG.getConstant(MVT::getSizeInBits(XType)-1, 4006 TLI.getShiftAmountTy())); 4007 SDOperand Add = DAG.getNode(ISD::ADD, XType, N0, Shift); 4008 AddToWorkList(Shift.Val); 4009 AddToWorkList(Add.Val); 4010 return DAG.getNode(ISD::XOR, XType, Add, Shift); 4011 } 4012 } 4013 } 4014 4015 return SDOperand(); 4016} 4017 4018/// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC. 4019SDOperand DAGCombiner::SimplifySetCC(MVT::ValueType VT, SDOperand N0, 4020 SDOperand N1, ISD::CondCode Cond, 4021 bool foldBooleans) { 4022 TargetLowering::DAGCombinerInfo 4023 DagCombineInfo(DAG, !AfterLegalize, false, this); 4024 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo); 4025} 4026 4027/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 4028/// return a DAG expression to select that will generate the same value by 4029/// multiplying by a magic number. See: 4030/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 4031SDOperand DAGCombiner::BuildSDIV(SDNode *N) { 4032 std::vector<SDNode*> Built; 4033 SDOperand S = TLI.BuildSDIV(N, DAG, &Built); 4034 4035 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 4036 ii != ee; ++ii) 4037 AddToWorkList(*ii); 4038 return S; 4039} 4040 4041/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 4042/// return a DAG expression to select that will generate the same value by 4043/// multiplying by a magic number. See: 4044/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 4045SDOperand DAGCombiner::BuildUDIV(SDNode *N) { 4046 std::vector<SDNode*> Built; 4047 SDOperand S = TLI.BuildUDIV(N, DAG, &Built); 4048 4049 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 4050 ii != ee; ++ii) 4051 AddToWorkList(*ii); 4052 return S; 4053} 4054 4055/// FindBaseOffset - Return true if base is known not to alias with anything 4056/// but itself. Provides base object and offset as results. 4057static bool FindBaseOffset(SDOperand Ptr, SDOperand &Base, int64_t &Offset) { 4058 // Assume it is a primitive operation. 4059 Base = Ptr; Offset = 0; 4060 4061 // If it's an adding a simple constant then integrate the offset. 4062 if (Base.getOpcode() == ISD::ADD) { 4063 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) { 4064 Base = Base.getOperand(0); 4065 Offset += C->getValue(); 4066 } 4067 } 4068 4069 // If it's any of the following then it can't alias with anything but itself. 4070 return isa<FrameIndexSDNode>(Base) || 4071 isa<ConstantPoolSDNode>(Base) || 4072 isa<GlobalAddressSDNode>(Base); 4073} 4074 4075/// isAlias - Return true if there is any possibility that the two addresses 4076/// overlap. 4077bool DAGCombiner::isAlias(SDOperand Ptr1, int64_t Size1, 4078 const Value *SrcValue1, int SrcValueOffset1, 4079 SDOperand Ptr2, int64_t Size2, 4080 const Value *SrcValue2, int SrcValueOffset2) 4081{ 4082 // If they are the same then they must be aliases. 4083 if (Ptr1 == Ptr2) return true; 4084 4085 // Gather base node and offset information. 4086 SDOperand Base1, Base2; 4087 int64_t Offset1, Offset2; 4088 bool KnownBase1 = FindBaseOffset(Ptr1, Base1, Offset1); 4089 bool KnownBase2 = FindBaseOffset(Ptr2, Base2, Offset2); 4090 4091 // If they have a same base address then... 4092 if (Base1 == Base2) { 4093 // Check to see if the addresses overlap. 4094 return!((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1); 4095 } 4096 4097 // If we know both bases then they can't alias. 4098 if (KnownBase1 && KnownBase2) return false; 4099 4100 if (CombinerGlobalAA) { 4101 // Use alias analysis information. 4102 int Overlap1 = Size1 + SrcValueOffset1 + Offset1; 4103 int Overlap2 = Size2 + SrcValueOffset2 + Offset2; 4104 AliasAnalysis::AliasResult AAResult = 4105 AA.alias(SrcValue1, Overlap1, SrcValue2, Overlap2); 4106 if (AAResult == AliasAnalysis::NoAlias) 4107 return false; 4108 } 4109 4110 // Otherwise we have to assume they alias. 4111 return true; 4112} 4113 4114/// FindAliasInfo - Extracts the relevant alias information from the memory 4115/// node. Returns true if the operand was a load. 4116bool DAGCombiner::FindAliasInfo(SDNode *N, 4117 SDOperand &Ptr, int64_t &Size, 4118 const Value *&SrcValue, int &SrcValueOffset) { 4119 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 4120 Ptr = LD->getBasePtr(); 4121 Size = MVT::getSizeInBits(LD->getLoadedVT()) >> 3; 4122 SrcValue = LD->getSrcValue(); 4123 SrcValueOffset = LD->getSrcValueOffset(); 4124 return true; 4125 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 4126 Ptr = ST->getBasePtr(); 4127 Size = MVT::getSizeInBits(ST->getStoredVT()) >> 3; 4128 SrcValue = ST->getSrcValue(); 4129 SrcValueOffset = ST->getSrcValueOffset(); 4130 } else { 4131 assert(0 && "FindAliasInfo expected a memory operand"); 4132 } 4133 4134 return false; 4135} 4136 4137/// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 4138/// looking for aliasing nodes and adding them to the Aliases vector. 4139void DAGCombiner::GatherAllAliases(SDNode *N, SDOperand OriginalChain, 4140 SmallVector<SDOperand, 8> &Aliases) { 4141 SmallVector<SDOperand, 8> Chains; // List of chains to visit. 4142 std::set<SDNode *> Visited; // Visited node set. 4143 4144 // Get alias information for node. 4145 SDOperand Ptr; 4146 int64_t Size; 4147 const Value *SrcValue; 4148 int SrcValueOffset; 4149 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset); 4150 4151 // Starting off. 4152 Chains.push_back(OriginalChain); 4153 4154 // Look at each chain and determine if it is an alias. If so, add it to the 4155 // aliases list. If not, then continue up the chain looking for the next 4156 // candidate. 4157 while (!Chains.empty()) { 4158 SDOperand Chain = Chains.back(); 4159 Chains.pop_back(); 4160 4161 // Don't bother if we've been before. 4162 if (Visited.find(Chain.Val) != Visited.end()) continue; 4163 Visited.insert(Chain.Val); 4164 4165 switch (Chain.getOpcode()) { 4166 case ISD::EntryToken: 4167 // Entry token is ideal chain operand, but handled in FindBetterChain. 4168 break; 4169 4170 case ISD::LOAD: 4171 case ISD::STORE: { 4172 // Get alias information for Chain. 4173 SDOperand OpPtr; 4174 int64_t OpSize; 4175 const Value *OpSrcValue; 4176 int OpSrcValueOffset; 4177 bool IsOpLoad = FindAliasInfo(Chain.Val, OpPtr, OpSize, 4178 OpSrcValue, OpSrcValueOffset); 4179 4180 // If chain is alias then stop here. 4181 if (!(IsLoad && IsOpLoad) && 4182 isAlias(Ptr, Size, SrcValue, SrcValueOffset, 4183 OpPtr, OpSize, OpSrcValue, OpSrcValueOffset)) { 4184 Aliases.push_back(Chain); 4185 } else { 4186 // Look further up the chain. 4187 Chains.push_back(Chain.getOperand(0)); 4188 // Clean up old chain. 4189 AddToWorkList(Chain.Val); 4190 } 4191 break; 4192 } 4193 4194 case ISD::TokenFactor: 4195 // We have to check each of the operands of the token factor, so we queue 4196 // then up. Adding the operands to the queue (stack) in reverse order 4197 // maintains the original order and increases the likelihood that getNode 4198 // will find a matching token factor (CSE.) 4199 for (unsigned n = Chain.getNumOperands(); n;) 4200 Chains.push_back(Chain.getOperand(--n)); 4201 // Eliminate the token factor if we can. 4202 AddToWorkList(Chain.Val); 4203 break; 4204 4205 default: 4206 // For all other instructions we will just have to take what we can get. 4207 Aliases.push_back(Chain); 4208 break; 4209 } 4210 } 4211} 4212 4213/// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking 4214/// for a better chain (aliasing node.) 4215SDOperand DAGCombiner::FindBetterChain(SDNode *N, SDOperand OldChain) { 4216 SmallVector<SDOperand, 8> Aliases; // Ops for replacing token factor. 4217 4218 // Accumulate all the aliases to this node. 4219 GatherAllAliases(N, OldChain, Aliases); 4220 4221 if (Aliases.size() == 0) { 4222 // If no operands then chain to entry token. 4223 return DAG.getEntryNode(); 4224 } else if (Aliases.size() == 1) { 4225 // If a single operand then chain to it. We don't need to revisit it. 4226 return Aliases[0]; 4227 } 4228 4229 // Construct a custom tailored token factor. 4230 SDOperand NewChain = DAG.getNode(ISD::TokenFactor, MVT::Other, 4231 &Aliases[0], Aliases.size()); 4232 4233 // Make sure the old chain gets cleaned up. 4234 if (NewChain != OldChain) AddToWorkList(OldChain.Val); 4235 4236 return NewChain; 4237} 4238 4239// SelectionDAG::Combine - This is the entry point for the file. 4240// 4241void SelectionDAG::Combine(bool RunningAfterLegalize, AliasAnalysis &AA) { 4242 if (!RunningAfterLegalize && ViewDAGCombine1) 4243 viewGraph(); 4244 if (RunningAfterLegalize && ViewDAGCombine2) 4245 viewGraph(); 4246 /// run - This is the main entry point to this class. 4247 /// 4248 DAGCombiner(*this, AA).Run(RunningAfterLegalize); 4249} 4250