DAGCombiner.cpp revision 9a65a01eeb97cdc10ca6b97ade3f9f8aba11fa9f
1//===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run 11// both before and after the DAG is legalized. 12// 13// This pass is not a substitute for the LLVM IR instcombine pass. This pass is 14// primarily intended to handle simplification opportunities that are implicit 15// in the LLVM IR and exposed by the various codegen lowering phases. 16// 17//===----------------------------------------------------------------------===// 18 19#define DEBUG_TYPE "dagcombine" 20#include "llvm/CodeGen/SelectionDAG.h" 21#include "llvm/ADT/SmallPtrSet.h" 22#include "llvm/ADT/Statistic.h" 23#include "llvm/Analysis/AliasAnalysis.h" 24#include "llvm/CodeGen/MachineFrameInfo.h" 25#include "llvm/CodeGen/MachineFunction.h" 26#include "llvm/DataLayout.h" 27#include "llvm/DerivedTypes.h" 28#include "llvm/LLVMContext.h" 29#include "llvm/Support/CommandLine.h" 30#include "llvm/Support/Debug.h" 31#include "llvm/Support/ErrorHandling.h" 32#include "llvm/Support/MathExtras.h" 33#include "llvm/Support/raw_ostream.h" 34#include "llvm/Target/TargetLowering.h" 35#include "llvm/Target/TargetMachine.h" 36#include "llvm/Target/TargetOptions.h" 37#include <algorithm> 38using namespace llvm; 39 40STATISTIC(NodesCombined , "Number of dag nodes combined"); 41STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created"); 42STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created"); 43STATISTIC(OpsNarrowed , "Number of load/op/store narrowed"); 44STATISTIC(LdStFP2Int , "Number of fp load/store pairs transformed to int"); 45 46namespace { 47 static cl::opt<bool> 48 CombinerAA("combiner-alias-analysis", cl::Hidden, 49 cl::desc("Turn on alias analysis during testing")); 50 51 static cl::opt<bool> 52 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden, 53 cl::desc("Include global information in alias analysis")); 54 55//------------------------------ DAGCombiner ---------------------------------// 56 57 class DAGCombiner { 58 SelectionDAG &DAG; 59 const TargetLowering &TLI; 60 CombineLevel Level; 61 CodeGenOpt::Level OptLevel; 62 bool LegalOperations; 63 bool LegalTypes; 64 65 // Worklist of all of the nodes that need to be simplified. 66 // 67 // This has the semantics that when adding to the worklist, 68 // the item added must be next to be processed. It should 69 // also only appear once. The naive approach to this takes 70 // linear time. 71 // 72 // To reduce the insert/remove time to logarithmic, we use 73 // a set and a vector to maintain our worklist. 74 // 75 // The set contains the items on the worklist, but does not 76 // maintain the order they should be visited. 77 // 78 // The vector maintains the order nodes should be visited, but may 79 // contain duplicate or removed nodes. When choosing a node to 80 // visit, we pop off the order stack until we find an item that is 81 // also in the contents set. All operations are O(log N). 82 SmallPtrSet<SDNode*, 64> WorkListContents; 83 SmallVector<SDNode*, 64> WorkListOrder; 84 85 // AA - Used for DAG load/store alias analysis. 86 AliasAnalysis &AA; 87 88 /// AddUsersToWorkList - When an instruction is simplified, add all users of 89 /// the instruction to the work lists because they might get more simplified 90 /// now. 91 /// 92 void AddUsersToWorkList(SDNode *N) { 93 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 94 UI != UE; ++UI) 95 AddToWorkList(*UI); 96 } 97 98 /// visit - call the node-specific routine that knows how to fold each 99 /// particular type of node. 100 SDValue visit(SDNode *N); 101 102 public: 103 /// AddToWorkList - Add to the work list making sure its instance is at the 104 /// back (next to be processed.) 105 void AddToWorkList(SDNode *N) { 106 WorkListContents.insert(N); 107 WorkListOrder.push_back(N); 108 } 109 110 /// removeFromWorkList - remove all instances of N from the worklist. 111 /// 112 void removeFromWorkList(SDNode *N) { 113 WorkListContents.erase(N); 114 } 115 116 SDValue CombineTo(SDNode *N, const SDValue *To, unsigned NumTo, 117 bool AddTo = true); 118 119 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true) { 120 return CombineTo(N, &Res, 1, AddTo); 121 } 122 123 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, 124 bool AddTo = true) { 125 SDValue To[] = { Res0, Res1 }; 126 return CombineTo(N, To, 2, AddTo); 127 } 128 129 void CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO); 130 131 private: 132 133 /// SimplifyDemandedBits - Check the specified integer node value to see if 134 /// it can be simplified or if things it uses can be simplified by bit 135 /// propagation. If so, return true. 136 bool SimplifyDemandedBits(SDValue Op) { 137 unsigned BitWidth = Op.getValueType().getScalarType().getSizeInBits(); 138 APInt Demanded = APInt::getAllOnesValue(BitWidth); 139 return SimplifyDemandedBits(Op, Demanded); 140 } 141 142 bool SimplifyDemandedBits(SDValue Op, const APInt &Demanded); 143 144 bool CombineToPreIndexedLoadStore(SDNode *N); 145 bool CombineToPostIndexedLoadStore(SDNode *N); 146 147 void ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad); 148 SDValue PromoteOperand(SDValue Op, EVT PVT, bool &Replace); 149 SDValue SExtPromoteOperand(SDValue Op, EVT PVT); 150 SDValue ZExtPromoteOperand(SDValue Op, EVT PVT); 151 SDValue PromoteIntBinOp(SDValue Op); 152 SDValue PromoteIntShiftOp(SDValue Op); 153 SDValue PromoteExtend(SDValue Op); 154 bool PromoteLoad(SDValue Op); 155 156 void ExtendSetCCUses(SmallVector<SDNode*, 4> SetCCs, 157 SDValue Trunc, SDValue ExtLoad, DebugLoc DL, 158 ISD::NodeType ExtType); 159 160 /// combine - call the node-specific routine that knows how to fold each 161 /// particular type of node. If that doesn't do anything, try the 162 /// target-specific DAG combines. 163 SDValue combine(SDNode *N); 164 165 // Visitation implementation - Implement dag node combining for different 166 // node types. The semantics are as follows: 167 // Return Value: 168 // SDValue.getNode() == 0 - No change was made 169 // SDValue.getNode() == N - N was replaced, is dead and has been handled. 170 // otherwise - N should be replaced by the returned Operand. 171 // 172 SDValue visitTokenFactor(SDNode *N); 173 SDValue visitMERGE_VALUES(SDNode *N); 174 SDValue visitADD(SDNode *N); 175 SDValue visitSUB(SDNode *N); 176 SDValue visitADDC(SDNode *N); 177 SDValue visitSUBC(SDNode *N); 178 SDValue visitADDE(SDNode *N); 179 SDValue visitSUBE(SDNode *N); 180 SDValue visitMUL(SDNode *N); 181 SDValue visitSDIV(SDNode *N); 182 SDValue visitUDIV(SDNode *N); 183 SDValue visitSREM(SDNode *N); 184 SDValue visitUREM(SDNode *N); 185 SDValue visitMULHU(SDNode *N); 186 SDValue visitMULHS(SDNode *N); 187 SDValue visitSMUL_LOHI(SDNode *N); 188 SDValue visitUMUL_LOHI(SDNode *N); 189 SDValue visitSMULO(SDNode *N); 190 SDValue visitUMULO(SDNode *N); 191 SDValue visitSDIVREM(SDNode *N); 192 SDValue visitUDIVREM(SDNode *N); 193 SDValue visitAND(SDNode *N); 194 SDValue visitOR(SDNode *N); 195 SDValue visitXOR(SDNode *N); 196 SDValue SimplifyVBinOp(SDNode *N); 197 SDValue SimplifyVUnaryOp(SDNode *N); 198 SDValue visitSHL(SDNode *N); 199 SDValue visitSRA(SDNode *N); 200 SDValue visitSRL(SDNode *N); 201 SDValue visitCTLZ(SDNode *N); 202 SDValue visitCTLZ_ZERO_UNDEF(SDNode *N); 203 SDValue visitCTTZ(SDNode *N); 204 SDValue visitCTTZ_ZERO_UNDEF(SDNode *N); 205 SDValue visitCTPOP(SDNode *N); 206 SDValue visitSELECT(SDNode *N); 207 SDValue visitSELECT_CC(SDNode *N); 208 SDValue visitSETCC(SDNode *N); 209 SDValue visitSIGN_EXTEND(SDNode *N); 210 SDValue visitZERO_EXTEND(SDNode *N); 211 SDValue visitANY_EXTEND(SDNode *N); 212 SDValue visitSIGN_EXTEND_INREG(SDNode *N); 213 SDValue visitTRUNCATE(SDNode *N); 214 SDValue visitBITCAST(SDNode *N); 215 SDValue visitBUILD_PAIR(SDNode *N); 216 SDValue visitFADD(SDNode *N); 217 SDValue visitFSUB(SDNode *N); 218 SDValue visitFMUL(SDNode *N); 219 SDValue visitFMA(SDNode *N); 220 SDValue visitFDIV(SDNode *N); 221 SDValue visitFREM(SDNode *N); 222 SDValue visitFCOPYSIGN(SDNode *N); 223 SDValue visitSINT_TO_FP(SDNode *N); 224 SDValue visitUINT_TO_FP(SDNode *N); 225 SDValue visitFP_TO_SINT(SDNode *N); 226 SDValue visitFP_TO_UINT(SDNode *N); 227 SDValue visitFP_ROUND(SDNode *N); 228 SDValue visitFP_ROUND_INREG(SDNode *N); 229 SDValue visitFP_EXTEND(SDNode *N); 230 SDValue visitFNEG(SDNode *N); 231 SDValue visitFABS(SDNode *N); 232 SDValue visitFCEIL(SDNode *N); 233 SDValue visitFTRUNC(SDNode *N); 234 SDValue visitFFLOOR(SDNode *N); 235 SDValue visitBRCOND(SDNode *N); 236 SDValue visitBR_CC(SDNode *N); 237 SDValue visitLOAD(SDNode *N); 238 SDValue visitSTORE(SDNode *N); 239 SDValue visitINSERT_VECTOR_ELT(SDNode *N); 240 SDValue visitEXTRACT_VECTOR_ELT(SDNode *N); 241 SDValue visitBUILD_VECTOR(SDNode *N); 242 SDValue visitCONCAT_VECTORS(SDNode *N); 243 SDValue visitEXTRACT_SUBVECTOR(SDNode *N); 244 SDValue visitVECTOR_SHUFFLE(SDNode *N); 245 SDValue visitMEMBARRIER(SDNode *N); 246 247 SDValue XformToShuffleWithZero(SDNode *N); 248 SDValue ReassociateOps(unsigned Opc, DebugLoc DL, SDValue LHS, SDValue RHS); 249 250 SDValue visitShiftByConstant(SDNode *N, unsigned Amt); 251 252 bool SimplifySelectOps(SDNode *SELECT, SDValue LHS, SDValue RHS); 253 SDValue SimplifyBinOpWithSameOpcodeHands(SDNode *N); 254 SDValue SimplifySelect(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2); 255 SDValue SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2, 256 SDValue N3, ISD::CondCode CC, 257 bool NotExtCompare = false); 258 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond, 259 DebugLoc DL, bool foldBooleans = true); 260 SDValue SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 261 unsigned HiOp); 262 SDValue CombineConsecutiveLoads(SDNode *N, EVT VT); 263 SDValue ConstantFoldBITCASTofBUILD_VECTOR(SDNode *, EVT); 264 SDValue BuildSDIV(SDNode *N); 265 SDValue BuildUDIV(SDNode *N); 266 SDValue MatchBSwapHWordLow(SDNode *N, SDValue N0, SDValue N1, 267 bool DemandHighBits = true); 268 SDValue MatchBSwapHWord(SDNode *N, SDValue N0, SDValue N1); 269 SDNode *MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL); 270 SDValue ReduceLoadWidth(SDNode *N); 271 SDValue ReduceLoadOpStoreWidth(SDNode *N); 272 SDValue TransformFPLoadStorePair(SDNode *N); 273 SDValue reduceBuildVecExtToExtBuildVec(SDNode *N); 274 SDValue reduceBuildVecConvertToConvertBuildVec(SDNode *N); 275 276 SDValue GetDemandedBits(SDValue V, const APInt &Mask); 277 278 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 279 /// looking for aliasing nodes and adding them to the Aliases vector. 280 void GatherAllAliases(SDNode *N, SDValue OriginalChain, 281 SmallVector<SDValue, 8> &Aliases); 282 283 /// isAlias - Return true if there is any possibility that the two addresses 284 /// overlap. 285 bool isAlias(SDValue Ptr1, int64_t Size1, 286 const Value *SrcValue1, int SrcValueOffset1, 287 unsigned SrcValueAlign1, 288 const MDNode *TBAAInfo1, 289 SDValue Ptr2, int64_t Size2, 290 const Value *SrcValue2, int SrcValueOffset2, 291 unsigned SrcValueAlign2, 292 const MDNode *TBAAInfo2) const; 293 294 /// isAlias - Return true if there is any possibility that the two addresses 295 /// overlap. 296 bool isAlias(LSBaseSDNode *Op0, LSBaseSDNode *Op1); 297 298 /// FindAliasInfo - Extracts the relevant alias information from the memory 299 /// node. Returns true if the operand was a load. 300 bool FindAliasInfo(SDNode *N, 301 SDValue &Ptr, int64_t &Size, 302 const Value *&SrcValue, int &SrcValueOffset, 303 unsigned &SrcValueAlignment, 304 const MDNode *&TBAAInfo) const; 305 306 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, 307 /// looking for a better chain (aliasing node.) 308 SDValue FindBetterChain(SDNode *N, SDValue Chain); 309 310 /// Merge consecutive store operations into a wide store. 311 /// This optimization uses wide integers or vectors when possible. 312 /// \return True if some memory operations were changed. 313 bool MergeConsecutiveStores(StoreSDNode *N); 314 315 public: 316 DAGCombiner(SelectionDAG &D, AliasAnalysis &A, CodeGenOpt::Level OL) 317 : DAG(D), TLI(D.getTargetLoweringInfo()), Level(BeforeLegalizeTypes), 318 OptLevel(OL), LegalOperations(false), LegalTypes(false), AA(A) {} 319 320 /// Run - runs the dag combiner on all nodes in the work list 321 void Run(CombineLevel AtLevel); 322 323 SelectionDAG &getDAG() const { return DAG; } 324 325 /// getShiftAmountTy - Returns a type large enough to hold any valid 326 /// shift amount - before type legalization these can be huge. 327 EVT getShiftAmountTy(EVT LHSTy) { 328 return LegalTypes ? TLI.getShiftAmountTy(LHSTy) : TLI.getPointerTy(); 329 } 330 331 /// isTypeLegal - This method returns true if we are running before type 332 /// legalization or if the specified VT is legal. 333 bool isTypeLegal(const EVT &VT) { 334 if (!LegalTypes) return true; 335 return TLI.isTypeLegal(VT); 336 } 337 }; 338} 339 340 341namespace { 342/// WorkListRemover - This class is a DAGUpdateListener that removes any deleted 343/// nodes from the worklist. 344class WorkListRemover : public SelectionDAG::DAGUpdateListener { 345 DAGCombiner &DC; 346public: 347 explicit WorkListRemover(DAGCombiner &dc) 348 : SelectionDAG::DAGUpdateListener(dc.getDAG()), DC(dc) {} 349 350 virtual void NodeDeleted(SDNode *N, SDNode *E) { 351 DC.removeFromWorkList(N); 352 } 353}; 354} 355 356//===----------------------------------------------------------------------===// 357// TargetLowering::DAGCombinerInfo implementation 358//===----------------------------------------------------------------------===// 359 360void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) { 361 ((DAGCombiner*)DC)->AddToWorkList(N); 362} 363 364void TargetLowering::DAGCombinerInfo::RemoveFromWorklist(SDNode *N) { 365 ((DAGCombiner*)DC)->removeFromWorkList(N); 366} 367 368SDValue TargetLowering::DAGCombinerInfo:: 369CombineTo(SDNode *N, const std::vector<SDValue> &To, bool AddTo) { 370 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size(), AddTo); 371} 372 373SDValue TargetLowering::DAGCombinerInfo:: 374CombineTo(SDNode *N, SDValue Res, bool AddTo) { 375 return ((DAGCombiner*)DC)->CombineTo(N, Res, AddTo); 376} 377 378 379SDValue TargetLowering::DAGCombinerInfo:: 380CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo) { 381 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1, AddTo); 382} 383 384void TargetLowering::DAGCombinerInfo:: 385CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) { 386 return ((DAGCombiner*)DC)->CommitTargetLoweringOpt(TLO); 387} 388 389//===----------------------------------------------------------------------===// 390// Helper Functions 391//===----------------------------------------------------------------------===// 392 393/// isNegatibleForFree - Return 1 if we can compute the negated form of the 394/// specified expression for the same cost as the expression itself, or 2 if we 395/// can compute the negated form more cheaply than the expression itself. 396static char isNegatibleForFree(SDValue Op, bool LegalOperations, 397 const TargetLowering &TLI, 398 const TargetOptions *Options, 399 unsigned Depth = 0) { 400 // fneg is removable even if it has multiple uses. 401 if (Op.getOpcode() == ISD::FNEG) return 2; 402 403 // Don't allow anything with multiple uses. 404 if (!Op.hasOneUse()) return 0; 405 406 // Don't recurse exponentially. 407 if (Depth > 6) return 0; 408 409 switch (Op.getOpcode()) { 410 default: return false; 411 case ISD::ConstantFP: 412 // Don't invert constant FP values after legalize. The negated constant 413 // isn't necessarily legal. 414 return LegalOperations ? 0 : 1; 415 case ISD::FADD: 416 // FIXME: determine better conditions for this xform. 417 if (!Options->UnsafeFPMath) return 0; 418 419 // After operation legalization, it might not be legal to create new FSUBs. 420 if (LegalOperations && 421 !TLI.isOperationLegalOrCustom(ISD::FSUB, Op.getValueType())) 422 return 0; 423 424 // fold (fneg (fadd A, B)) -> (fsub (fneg A), B) 425 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI, 426 Options, Depth + 1)) 427 return V; 428 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A) 429 return isNegatibleForFree(Op.getOperand(1), LegalOperations, TLI, Options, 430 Depth + 1); 431 case ISD::FSUB: 432 // We can't turn -(A-B) into B-A when we honor signed zeros. 433 if (!Options->UnsafeFPMath) return 0; 434 435 // fold (fneg (fsub A, B)) -> (fsub B, A) 436 return 1; 437 438 case ISD::FMUL: 439 case ISD::FDIV: 440 if (Options->HonorSignDependentRoundingFPMath()) return 0; 441 442 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) or (fmul X, (fneg Y)) 443 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI, 444 Options, Depth + 1)) 445 return V; 446 447 return isNegatibleForFree(Op.getOperand(1), LegalOperations, TLI, Options, 448 Depth + 1); 449 450 case ISD::FP_EXTEND: 451 case ISD::FP_ROUND: 452 case ISD::FSIN: 453 return isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI, Options, 454 Depth + 1); 455 } 456} 457 458/// GetNegatedExpression - If isNegatibleForFree returns true, this function 459/// returns the newly negated expression. 460static SDValue GetNegatedExpression(SDValue Op, SelectionDAG &DAG, 461 bool LegalOperations, unsigned Depth = 0) { 462 // fneg is removable even if it has multiple uses. 463 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0); 464 465 // Don't allow anything with multiple uses. 466 assert(Op.hasOneUse() && "Unknown reuse!"); 467 468 assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree"); 469 switch (Op.getOpcode()) { 470 default: llvm_unreachable("Unknown code"); 471 case ISD::ConstantFP: { 472 APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF(); 473 V.changeSign(); 474 return DAG.getConstantFP(V, Op.getValueType()); 475 } 476 case ISD::FADD: 477 // FIXME: determine better conditions for this xform. 478 assert(DAG.getTarget().Options.UnsafeFPMath); 479 480 // fold (fneg (fadd A, B)) -> (fsub (fneg A), B) 481 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, 482 DAG.getTargetLoweringInfo(), 483 &DAG.getTarget().Options, Depth+1)) 484 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 485 GetNegatedExpression(Op.getOperand(0), DAG, 486 LegalOperations, Depth+1), 487 Op.getOperand(1)); 488 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A) 489 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 490 GetNegatedExpression(Op.getOperand(1), DAG, 491 LegalOperations, Depth+1), 492 Op.getOperand(0)); 493 case ISD::FSUB: 494 // We can't turn -(A-B) into B-A when we honor signed zeros. 495 assert(DAG.getTarget().Options.UnsafeFPMath); 496 497 // fold (fneg (fsub 0, B)) -> B 498 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(Op.getOperand(0))) 499 if (N0CFP->getValueAPF().isZero()) 500 return Op.getOperand(1); 501 502 // fold (fneg (fsub A, B)) -> (fsub B, A) 503 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 504 Op.getOperand(1), Op.getOperand(0)); 505 506 case ISD::FMUL: 507 case ISD::FDIV: 508 assert(!DAG.getTarget().Options.HonorSignDependentRoundingFPMath()); 509 510 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) 511 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, 512 DAG.getTargetLoweringInfo(), 513 &DAG.getTarget().Options, Depth+1)) 514 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 515 GetNegatedExpression(Op.getOperand(0), DAG, 516 LegalOperations, Depth+1), 517 Op.getOperand(1)); 518 519 // fold (fneg (fmul X, Y)) -> (fmul X, (fneg Y)) 520 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 521 Op.getOperand(0), 522 GetNegatedExpression(Op.getOperand(1), DAG, 523 LegalOperations, Depth+1)); 524 525 case ISD::FP_EXTEND: 526 case ISD::FSIN: 527 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 528 GetNegatedExpression(Op.getOperand(0), DAG, 529 LegalOperations, Depth+1)); 530 case ISD::FP_ROUND: 531 return DAG.getNode(ISD::FP_ROUND, Op.getDebugLoc(), Op.getValueType(), 532 GetNegatedExpression(Op.getOperand(0), DAG, 533 LegalOperations, Depth+1), 534 Op.getOperand(1)); 535 } 536} 537 538 539// isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc 540// that selects between the values 1 and 0, making it equivalent to a setcc. 541// Also, set the incoming LHS, RHS, and CC references to the appropriate 542// nodes based on the type of node we are checking. This simplifies life a 543// bit for the callers. 544static bool isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS, 545 SDValue &CC) { 546 if (N.getOpcode() == ISD::SETCC) { 547 LHS = N.getOperand(0); 548 RHS = N.getOperand(1); 549 CC = N.getOperand(2); 550 return true; 551 } 552 if (N.getOpcode() == ISD::SELECT_CC && 553 N.getOperand(2).getOpcode() == ISD::Constant && 554 N.getOperand(3).getOpcode() == ISD::Constant && 555 cast<ConstantSDNode>(N.getOperand(2))->getAPIntValue() == 1 && 556 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) { 557 LHS = N.getOperand(0); 558 RHS = N.getOperand(1); 559 CC = N.getOperand(4); 560 return true; 561 } 562 return false; 563} 564 565// isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only 566// one use. If this is true, it allows the users to invert the operation for 567// free when it is profitable to do so. 568static bool isOneUseSetCC(SDValue N) { 569 SDValue N0, N1, N2; 570 if (isSetCCEquivalent(N, N0, N1, N2) && N.getNode()->hasOneUse()) 571 return true; 572 return false; 573} 574 575SDValue DAGCombiner::ReassociateOps(unsigned Opc, DebugLoc DL, 576 SDValue N0, SDValue N1) { 577 EVT VT = N0.getValueType(); 578 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) { 579 if (isa<ConstantSDNode>(N1)) { 580 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2)) 581 SDValue OpNode = 582 DAG.FoldConstantArithmetic(Opc, VT, 583 cast<ConstantSDNode>(N0.getOperand(1)), 584 cast<ConstantSDNode>(N1)); 585 return DAG.getNode(Opc, DL, VT, N0.getOperand(0), OpNode); 586 } 587 if (N0.hasOneUse()) { 588 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use 589 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT, 590 N0.getOperand(0), N1); 591 AddToWorkList(OpNode.getNode()); 592 return DAG.getNode(Opc, DL, VT, OpNode, N0.getOperand(1)); 593 } 594 } 595 596 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) { 597 if (isa<ConstantSDNode>(N0)) { 598 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2)) 599 SDValue OpNode = 600 DAG.FoldConstantArithmetic(Opc, VT, 601 cast<ConstantSDNode>(N1.getOperand(1)), 602 cast<ConstantSDNode>(N0)); 603 return DAG.getNode(Opc, DL, VT, N1.getOperand(0), OpNode); 604 } 605 if (N1.hasOneUse()) { 606 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use 607 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT, 608 N1.getOperand(0), N0); 609 AddToWorkList(OpNode.getNode()); 610 return DAG.getNode(Opc, DL, VT, OpNode, N1.getOperand(1)); 611 } 612 } 613 614 return SDValue(); 615} 616 617SDValue DAGCombiner::CombineTo(SDNode *N, const SDValue *To, unsigned NumTo, 618 bool AddTo) { 619 assert(N->getNumValues() == NumTo && "Broken CombineTo call!"); 620 ++NodesCombined; 621 DEBUG(dbgs() << "\nReplacing.1 "; 622 N->dump(&DAG); 623 dbgs() << "\nWith: "; 624 To[0].getNode()->dump(&DAG); 625 dbgs() << " and " << NumTo-1 << " other values\n"; 626 for (unsigned i = 0, e = NumTo; i != e; ++i) 627 assert((!To[i].getNode() || 628 N->getValueType(i) == To[i].getValueType()) && 629 "Cannot combine value to value of different type!")); 630 WorkListRemover DeadNodes(*this); 631 DAG.ReplaceAllUsesWith(N, To); 632 if (AddTo) { 633 // Push the new nodes and any users onto the worklist 634 for (unsigned i = 0, e = NumTo; i != e; ++i) { 635 if (To[i].getNode()) { 636 AddToWorkList(To[i].getNode()); 637 AddUsersToWorkList(To[i].getNode()); 638 } 639 } 640 } 641 642 // Finally, if the node is now dead, remove it from the graph. The node 643 // may not be dead if the replacement process recursively simplified to 644 // something else needing this node. 645 if (N->use_empty()) { 646 // Nodes can be reintroduced into the worklist. Make sure we do not 647 // process a node that has been replaced. 648 removeFromWorkList(N); 649 650 // Finally, since the node is now dead, remove it from the graph. 651 DAG.DeleteNode(N); 652 } 653 return SDValue(N, 0); 654} 655 656void DAGCombiner:: 657CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) { 658 // Replace all uses. If any nodes become isomorphic to other nodes and 659 // are deleted, make sure to remove them from our worklist. 660 WorkListRemover DeadNodes(*this); 661 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New); 662 663 // Push the new node and any (possibly new) users onto the worklist. 664 AddToWorkList(TLO.New.getNode()); 665 AddUsersToWorkList(TLO.New.getNode()); 666 667 // Finally, if the node is now dead, remove it from the graph. The node 668 // may not be dead if the replacement process recursively simplified to 669 // something else needing this node. 670 if (TLO.Old.getNode()->use_empty()) { 671 removeFromWorkList(TLO.Old.getNode()); 672 673 // If the operands of this node are only used by the node, they will now 674 // be dead. Make sure to visit them first to delete dead nodes early. 675 for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands(); i != e; ++i) 676 if (TLO.Old.getNode()->getOperand(i).getNode()->hasOneUse()) 677 AddToWorkList(TLO.Old.getNode()->getOperand(i).getNode()); 678 679 DAG.DeleteNode(TLO.Old.getNode()); 680 } 681} 682 683/// SimplifyDemandedBits - Check the specified integer node value to see if 684/// it can be simplified or if things it uses can be simplified by bit 685/// propagation. If so, return true. 686bool DAGCombiner::SimplifyDemandedBits(SDValue Op, const APInt &Demanded) { 687 TargetLowering::TargetLoweringOpt TLO(DAG, LegalTypes, LegalOperations); 688 APInt KnownZero, KnownOne; 689 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO)) 690 return false; 691 692 // Revisit the node. 693 AddToWorkList(Op.getNode()); 694 695 // Replace the old value with the new one. 696 ++NodesCombined; 697 DEBUG(dbgs() << "\nReplacing.2 "; 698 TLO.Old.getNode()->dump(&DAG); 699 dbgs() << "\nWith: "; 700 TLO.New.getNode()->dump(&DAG); 701 dbgs() << '\n'); 702 703 CommitTargetLoweringOpt(TLO); 704 return true; 705} 706 707void DAGCombiner::ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad) { 708 DebugLoc dl = Load->getDebugLoc(); 709 EVT VT = Load->getValueType(0); 710 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, VT, SDValue(ExtLoad, 0)); 711 712 DEBUG(dbgs() << "\nReplacing.9 "; 713 Load->dump(&DAG); 714 dbgs() << "\nWith: "; 715 Trunc.getNode()->dump(&DAG); 716 dbgs() << '\n'); 717 WorkListRemover DeadNodes(*this); 718 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 0), Trunc); 719 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 1), SDValue(ExtLoad, 1)); 720 removeFromWorkList(Load); 721 DAG.DeleteNode(Load); 722 AddToWorkList(Trunc.getNode()); 723} 724 725SDValue DAGCombiner::PromoteOperand(SDValue Op, EVT PVT, bool &Replace) { 726 Replace = false; 727 DebugLoc dl = Op.getDebugLoc(); 728 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Op)) { 729 EVT MemVT = LD->getMemoryVT(); 730 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD) 731 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT) ? ISD::ZEXTLOAD 732 : ISD::EXTLOAD) 733 : LD->getExtensionType(); 734 Replace = true; 735 return DAG.getExtLoad(ExtType, dl, PVT, 736 LD->getChain(), LD->getBasePtr(), 737 LD->getPointerInfo(), 738 MemVT, LD->isVolatile(), 739 LD->isNonTemporal(), LD->getAlignment()); 740 } 741 742 unsigned Opc = Op.getOpcode(); 743 switch (Opc) { 744 default: break; 745 case ISD::AssertSext: 746 return DAG.getNode(ISD::AssertSext, dl, PVT, 747 SExtPromoteOperand(Op.getOperand(0), PVT), 748 Op.getOperand(1)); 749 case ISD::AssertZext: 750 return DAG.getNode(ISD::AssertZext, dl, PVT, 751 ZExtPromoteOperand(Op.getOperand(0), PVT), 752 Op.getOperand(1)); 753 case ISD::Constant: { 754 unsigned ExtOpc = 755 Op.getValueType().isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; 756 return DAG.getNode(ExtOpc, dl, PVT, Op); 757 } 758 } 759 760 if (!TLI.isOperationLegal(ISD::ANY_EXTEND, PVT)) 761 return SDValue(); 762 return DAG.getNode(ISD::ANY_EXTEND, dl, PVT, Op); 763} 764 765SDValue DAGCombiner::SExtPromoteOperand(SDValue Op, EVT PVT) { 766 if (!TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, PVT)) 767 return SDValue(); 768 EVT OldVT = Op.getValueType(); 769 DebugLoc dl = Op.getDebugLoc(); 770 bool Replace = false; 771 SDValue NewOp = PromoteOperand(Op, PVT, Replace); 772 if (NewOp.getNode() == 0) 773 return SDValue(); 774 AddToWorkList(NewOp.getNode()); 775 776 if (Replace) 777 ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode()); 778 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NewOp.getValueType(), NewOp, 779 DAG.getValueType(OldVT)); 780} 781 782SDValue DAGCombiner::ZExtPromoteOperand(SDValue Op, EVT PVT) { 783 EVT OldVT = Op.getValueType(); 784 DebugLoc dl = Op.getDebugLoc(); 785 bool Replace = false; 786 SDValue NewOp = PromoteOperand(Op, PVT, Replace); 787 if (NewOp.getNode() == 0) 788 return SDValue(); 789 AddToWorkList(NewOp.getNode()); 790 791 if (Replace) 792 ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode()); 793 return DAG.getZeroExtendInReg(NewOp, dl, OldVT); 794} 795 796/// PromoteIntBinOp - Promote the specified integer binary operation if the 797/// target indicates it is beneficial. e.g. On x86, it's usually better to 798/// promote i16 operations to i32 since i16 instructions are longer. 799SDValue DAGCombiner::PromoteIntBinOp(SDValue Op) { 800 if (!LegalOperations) 801 return SDValue(); 802 803 EVT VT = Op.getValueType(); 804 if (VT.isVector() || !VT.isInteger()) 805 return SDValue(); 806 807 // If operation type is 'undesirable', e.g. i16 on x86, consider 808 // promoting it. 809 unsigned Opc = Op.getOpcode(); 810 if (TLI.isTypeDesirableForOp(Opc, VT)) 811 return SDValue(); 812 813 EVT PVT = VT; 814 // Consult target whether it is a good idea to promote this operation and 815 // what's the right type to promote it to. 816 if (TLI.IsDesirableToPromoteOp(Op, PVT)) { 817 assert(PVT != VT && "Don't know what type to promote to!"); 818 819 bool Replace0 = false; 820 SDValue N0 = Op.getOperand(0); 821 SDValue NN0 = PromoteOperand(N0, PVT, Replace0); 822 if (NN0.getNode() == 0) 823 return SDValue(); 824 825 bool Replace1 = false; 826 SDValue N1 = Op.getOperand(1); 827 SDValue NN1; 828 if (N0 == N1) 829 NN1 = NN0; 830 else { 831 NN1 = PromoteOperand(N1, PVT, Replace1); 832 if (NN1.getNode() == 0) 833 return SDValue(); 834 } 835 836 AddToWorkList(NN0.getNode()); 837 if (NN1.getNode()) 838 AddToWorkList(NN1.getNode()); 839 840 if (Replace0) 841 ReplaceLoadWithPromotedLoad(N0.getNode(), NN0.getNode()); 842 if (Replace1) 843 ReplaceLoadWithPromotedLoad(N1.getNode(), NN1.getNode()); 844 845 DEBUG(dbgs() << "\nPromoting "; 846 Op.getNode()->dump(&DAG)); 847 DebugLoc dl = Op.getDebugLoc(); 848 return DAG.getNode(ISD::TRUNCATE, dl, VT, 849 DAG.getNode(Opc, dl, PVT, NN0, NN1)); 850 } 851 return SDValue(); 852} 853 854/// PromoteIntShiftOp - Promote the specified integer shift operation if the 855/// target indicates it is beneficial. e.g. On x86, it's usually better to 856/// promote i16 operations to i32 since i16 instructions are longer. 857SDValue DAGCombiner::PromoteIntShiftOp(SDValue Op) { 858 if (!LegalOperations) 859 return SDValue(); 860 861 EVT VT = Op.getValueType(); 862 if (VT.isVector() || !VT.isInteger()) 863 return SDValue(); 864 865 // If operation type is 'undesirable', e.g. i16 on x86, consider 866 // promoting it. 867 unsigned Opc = Op.getOpcode(); 868 if (TLI.isTypeDesirableForOp(Opc, VT)) 869 return SDValue(); 870 871 EVT PVT = VT; 872 // Consult target whether it is a good idea to promote this operation and 873 // what's the right type to promote it to. 874 if (TLI.IsDesirableToPromoteOp(Op, PVT)) { 875 assert(PVT != VT && "Don't know what type to promote to!"); 876 877 bool Replace = false; 878 SDValue N0 = Op.getOperand(0); 879 if (Opc == ISD::SRA) 880 N0 = SExtPromoteOperand(Op.getOperand(0), PVT); 881 else if (Opc == ISD::SRL) 882 N0 = ZExtPromoteOperand(Op.getOperand(0), PVT); 883 else 884 N0 = PromoteOperand(N0, PVT, Replace); 885 if (N0.getNode() == 0) 886 return SDValue(); 887 888 AddToWorkList(N0.getNode()); 889 if (Replace) 890 ReplaceLoadWithPromotedLoad(Op.getOperand(0).getNode(), N0.getNode()); 891 892 DEBUG(dbgs() << "\nPromoting "; 893 Op.getNode()->dump(&DAG)); 894 DebugLoc dl = Op.getDebugLoc(); 895 return DAG.getNode(ISD::TRUNCATE, dl, VT, 896 DAG.getNode(Opc, dl, PVT, N0, Op.getOperand(1))); 897 } 898 return SDValue(); 899} 900 901SDValue DAGCombiner::PromoteExtend(SDValue Op) { 902 if (!LegalOperations) 903 return SDValue(); 904 905 EVT VT = Op.getValueType(); 906 if (VT.isVector() || !VT.isInteger()) 907 return SDValue(); 908 909 // If operation type is 'undesirable', e.g. i16 on x86, consider 910 // promoting it. 911 unsigned Opc = Op.getOpcode(); 912 if (TLI.isTypeDesirableForOp(Opc, VT)) 913 return SDValue(); 914 915 EVT PVT = VT; 916 // Consult target whether it is a good idea to promote this operation and 917 // what's the right type to promote it to. 918 if (TLI.IsDesirableToPromoteOp(Op, PVT)) { 919 assert(PVT != VT && "Don't know what type to promote to!"); 920 // fold (aext (aext x)) -> (aext x) 921 // fold (aext (zext x)) -> (zext x) 922 // fold (aext (sext x)) -> (sext x) 923 DEBUG(dbgs() << "\nPromoting "; 924 Op.getNode()->dump(&DAG)); 925 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), VT, Op.getOperand(0)); 926 } 927 return SDValue(); 928} 929 930bool DAGCombiner::PromoteLoad(SDValue Op) { 931 if (!LegalOperations) 932 return false; 933 934 EVT VT = Op.getValueType(); 935 if (VT.isVector() || !VT.isInteger()) 936 return false; 937 938 // If operation type is 'undesirable', e.g. i16 on x86, consider 939 // promoting it. 940 unsigned Opc = Op.getOpcode(); 941 if (TLI.isTypeDesirableForOp(Opc, VT)) 942 return false; 943 944 EVT PVT = VT; 945 // Consult target whether it is a good idea to promote this operation and 946 // what's the right type to promote it to. 947 if (TLI.IsDesirableToPromoteOp(Op, PVT)) { 948 assert(PVT != VT && "Don't know what type to promote to!"); 949 950 DebugLoc dl = Op.getDebugLoc(); 951 SDNode *N = Op.getNode(); 952 LoadSDNode *LD = cast<LoadSDNode>(N); 953 EVT MemVT = LD->getMemoryVT(); 954 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD) 955 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT) ? ISD::ZEXTLOAD 956 : ISD::EXTLOAD) 957 : LD->getExtensionType(); 958 SDValue NewLD = DAG.getExtLoad(ExtType, dl, PVT, 959 LD->getChain(), LD->getBasePtr(), 960 LD->getPointerInfo(), 961 MemVT, LD->isVolatile(), 962 LD->isNonTemporal(), LD->getAlignment()); 963 SDValue Result = DAG.getNode(ISD::TRUNCATE, dl, VT, NewLD); 964 965 DEBUG(dbgs() << "\nPromoting "; 966 N->dump(&DAG); 967 dbgs() << "\nTo: "; 968 Result.getNode()->dump(&DAG); 969 dbgs() << '\n'); 970 WorkListRemover DeadNodes(*this); 971 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result); 972 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), NewLD.getValue(1)); 973 removeFromWorkList(N); 974 DAG.DeleteNode(N); 975 AddToWorkList(Result.getNode()); 976 return true; 977 } 978 return false; 979} 980 981 982//===----------------------------------------------------------------------===// 983// Main DAG Combiner implementation 984//===----------------------------------------------------------------------===// 985 986void DAGCombiner::Run(CombineLevel AtLevel) { 987 // set the instance variables, so that the various visit routines may use it. 988 Level = AtLevel; 989 LegalOperations = Level >= AfterLegalizeVectorOps; 990 LegalTypes = Level >= AfterLegalizeTypes; 991 992 // Add all the dag nodes to the worklist. 993 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 994 E = DAG.allnodes_end(); I != E; ++I) 995 AddToWorkList(I); 996 997 // Create a dummy node (which is not added to allnodes), that adds a reference 998 // to the root node, preventing it from being deleted, and tracking any 999 // changes of the root. 1000 HandleSDNode Dummy(DAG.getRoot()); 1001 1002 // The root of the dag may dangle to deleted nodes until the dag combiner is 1003 // done. Set it to null to avoid confusion. 1004 DAG.setRoot(SDValue()); 1005 1006 // while the worklist isn't empty, find a node and 1007 // try and combine it. 1008 while (!WorkListContents.empty()) { 1009 SDNode *N; 1010 // The WorkListOrder holds the SDNodes in order, but it may contain duplicates. 1011 // In order to avoid a linear scan, we use a set (O(log N)) to hold what the 1012 // worklist *should* contain, and check the node we want to visit is should 1013 // actually be visited. 1014 do { 1015 N = WorkListOrder.pop_back_val(); 1016 } while (!WorkListContents.erase(N)); 1017 1018 // If N has no uses, it is dead. Make sure to revisit all N's operands once 1019 // N is deleted from the DAG, since they too may now be dead or may have a 1020 // reduced number of uses, allowing other xforms. 1021 if (N->use_empty() && N != &Dummy) { 1022 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 1023 AddToWorkList(N->getOperand(i).getNode()); 1024 1025 DAG.DeleteNode(N); 1026 continue; 1027 } 1028 1029 SDValue RV = combine(N); 1030 1031 if (RV.getNode() == 0) 1032 continue; 1033 1034 ++NodesCombined; 1035 1036 // If we get back the same node we passed in, rather than a new node or 1037 // zero, we know that the node must have defined multiple values and 1038 // CombineTo was used. Since CombineTo takes care of the worklist 1039 // mechanics for us, we have no work to do in this case. 1040 if (RV.getNode() == N) 1041 continue; 1042 1043 assert(N->getOpcode() != ISD::DELETED_NODE && 1044 RV.getNode()->getOpcode() != ISD::DELETED_NODE && 1045 "Node was deleted but visit returned new node!"); 1046 1047 DEBUG(dbgs() << "\nReplacing.3 "; 1048 N->dump(&DAG); 1049 dbgs() << "\nWith: "; 1050 RV.getNode()->dump(&DAG); 1051 dbgs() << '\n'); 1052 1053 // Transfer debug value. 1054 DAG.TransferDbgValues(SDValue(N, 0), RV); 1055 WorkListRemover DeadNodes(*this); 1056 if (N->getNumValues() == RV.getNode()->getNumValues()) 1057 DAG.ReplaceAllUsesWith(N, RV.getNode()); 1058 else { 1059 assert(N->getValueType(0) == RV.getValueType() && 1060 N->getNumValues() == 1 && "Type mismatch"); 1061 SDValue OpV = RV; 1062 DAG.ReplaceAllUsesWith(N, &OpV); 1063 } 1064 1065 // Push the new node and any users onto the worklist 1066 AddToWorkList(RV.getNode()); 1067 AddUsersToWorkList(RV.getNode()); 1068 1069 // Add any uses of the old node to the worklist in case this node is the 1070 // last one that uses them. They may become dead after this node is 1071 // deleted. 1072 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 1073 AddToWorkList(N->getOperand(i).getNode()); 1074 1075 // Finally, if the node is now dead, remove it from the graph. The node 1076 // may not be dead if the replacement process recursively simplified to 1077 // something else needing this node. 1078 if (N->use_empty()) { 1079 // Nodes can be reintroduced into the worklist. Make sure we do not 1080 // process a node that has been replaced. 1081 removeFromWorkList(N); 1082 1083 // Finally, since the node is now dead, remove it from the graph. 1084 DAG.DeleteNode(N); 1085 } 1086 } 1087 1088 // If the root changed (e.g. it was a dead load, update the root). 1089 DAG.setRoot(Dummy.getValue()); 1090 DAG.RemoveDeadNodes(); 1091} 1092 1093SDValue DAGCombiner::visit(SDNode *N) { 1094 switch (N->getOpcode()) { 1095 default: break; 1096 case ISD::TokenFactor: return visitTokenFactor(N); 1097 case ISD::MERGE_VALUES: return visitMERGE_VALUES(N); 1098 case ISD::ADD: return visitADD(N); 1099 case ISD::SUB: return visitSUB(N); 1100 case ISD::ADDC: return visitADDC(N); 1101 case ISD::SUBC: return visitSUBC(N); 1102 case ISD::ADDE: return visitADDE(N); 1103 case ISD::SUBE: return visitSUBE(N); 1104 case ISD::MUL: return visitMUL(N); 1105 case ISD::SDIV: return visitSDIV(N); 1106 case ISD::UDIV: return visitUDIV(N); 1107 case ISD::SREM: return visitSREM(N); 1108 case ISD::UREM: return visitUREM(N); 1109 case ISD::MULHU: return visitMULHU(N); 1110 case ISD::MULHS: return visitMULHS(N); 1111 case ISD::SMUL_LOHI: return visitSMUL_LOHI(N); 1112 case ISD::UMUL_LOHI: return visitUMUL_LOHI(N); 1113 case ISD::SMULO: return visitSMULO(N); 1114 case ISD::UMULO: return visitUMULO(N); 1115 case ISD::SDIVREM: return visitSDIVREM(N); 1116 case ISD::UDIVREM: return visitUDIVREM(N); 1117 case ISD::AND: return visitAND(N); 1118 case ISD::OR: return visitOR(N); 1119 case ISD::XOR: return visitXOR(N); 1120 case ISD::SHL: return visitSHL(N); 1121 case ISD::SRA: return visitSRA(N); 1122 case ISD::SRL: return visitSRL(N); 1123 case ISD::CTLZ: return visitCTLZ(N); 1124 case ISD::CTLZ_ZERO_UNDEF: return visitCTLZ_ZERO_UNDEF(N); 1125 case ISD::CTTZ: return visitCTTZ(N); 1126 case ISD::CTTZ_ZERO_UNDEF: return visitCTTZ_ZERO_UNDEF(N); 1127 case ISD::CTPOP: return visitCTPOP(N); 1128 case ISD::SELECT: return visitSELECT(N); 1129 case ISD::SELECT_CC: return visitSELECT_CC(N); 1130 case ISD::SETCC: return visitSETCC(N); 1131 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N); 1132 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N); 1133 case ISD::ANY_EXTEND: return visitANY_EXTEND(N); 1134 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N); 1135 case ISD::TRUNCATE: return visitTRUNCATE(N); 1136 case ISD::BITCAST: return visitBITCAST(N); 1137 case ISD::BUILD_PAIR: return visitBUILD_PAIR(N); 1138 case ISD::FADD: return visitFADD(N); 1139 case ISD::FSUB: return visitFSUB(N); 1140 case ISD::FMUL: return visitFMUL(N); 1141 case ISD::FMA: return visitFMA(N); 1142 case ISD::FDIV: return visitFDIV(N); 1143 case ISD::FREM: return visitFREM(N); 1144 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N); 1145 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N); 1146 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N); 1147 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N); 1148 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N); 1149 case ISD::FP_ROUND: return visitFP_ROUND(N); 1150 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N); 1151 case ISD::FP_EXTEND: return visitFP_EXTEND(N); 1152 case ISD::FNEG: return visitFNEG(N); 1153 case ISD::FABS: return visitFABS(N); 1154 case ISD::FFLOOR: return visitFFLOOR(N); 1155 case ISD::FCEIL: return visitFCEIL(N); 1156 case ISD::FTRUNC: return visitFTRUNC(N); 1157 case ISD::BRCOND: return visitBRCOND(N); 1158 case ISD::BR_CC: return visitBR_CC(N); 1159 case ISD::LOAD: return visitLOAD(N); 1160 case ISD::STORE: return visitSTORE(N); 1161 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N); 1162 case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N); 1163 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N); 1164 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N); 1165 case ISD::EXTRACT_SUBVECTOR: return visitEXTRACT_SUBVECTOR(N); 1166 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N); 1167 case ISD::MEMBARRIER: return visitMEMBARRIER(N); 1168 } 1169 return SDValue(); 1170} 1171 1172SDValue DAGCombiner::combine(SDNode *N) { 1173 SDValue RV = visit(N); 1174 1175 // If nothing happened, try a target-specific DAG combine. 1176 if (RV.getNode() == 0) { 1177 assert(N->getOpcode() != ISD::DELETED_NODE && 1178 "Node was deleted but visit returned NULL!"); 1179 1180 if (N->getOpcode() >= ISD::BUILTIN_OP_END || 1181 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) { 1182 1183 // Expose the DAG combiner to the target combiner impls. 1184 TargetLowering::DAGCombinerInfo 1185 DagCombineInfo(DAG, !LegalTypes, !LegalOperations, false, this); 1186 1187 RV = TLI.PerformDAGCombine(N, DagCombineInfo); 1188 } 1189 } 1190 1191 // If nothing happened still, try promoting the operation. 1192 if (RV.getNode() == 0) { 1193 switch (N->getOpcode()) { 1194 default: break; 1195 case ISD::ADD: 1196 case ISD::SUB: 1197 case ISD::MUL: 1198 case ISD::AND: 1199 case ISD::OR: 1200 case ISD::XOR: 1201 RV = PromoteIntBinOp(SDValue(N, 0)); 1202 break; 1203 case ISD::SHL: 1204 case ISD::SRA: 1205 case ISD::SRL: 1206 RV = PromoteIntShiftOp(SDValue(N, 0)); 1207 break; 1208 case ISD::SIGN_EXTEND: 1209 case ISD::ZERO_EXTEND: 1210 case ISD::ANY_EXTEND: 1211 RV = PromoteExtend(SDValue(N, 0)); 1212 break; 1213 case ISD::LOAD: 1214 if (PromoteLoad(SDValue(N, 0))) 1215 RV = SDValue(N, 0); 1216 break; 1217 } 1218 } 1219 1220 // If N is a commutative binary node, try commuting it to enable more 1221 // sdisel CSE. 1222 if (RV.getNode() == 0 && 1223 SelectionDAG::isCommutativeBinOp(N->getOpcode()) && 1224 N->getNumValues() == 1) { 1225 SDValue N0 = N->getOperand(0); 1226 SDValue N1 = N->getOperand(1); 1227 1228 // Constant operands are canonicalized to RHS. 1229 if (isa<ConstantSDNode>(N0) || !isa<ConstantSDNode>(N1)) { 1230 SDValue Ops[] = { N1, N0 }; 1231 SDNode *CSENode = DAG.getNodeIfExists(N->getOpcode(), N->getVTList(), 1232 Ops, 2); 1233 if (CSENode) 1234 return SDValue(CSENode, 0); 1235 } 1236 } 1237 1238 return RV; 1239} 1240 1241/// getInputChainForNode - Given a node, return its input chain if it has one, 1242/// otherwise return a null sd operand. 1243static SDValue getInputChainForNode(SDNode *N) { 1244 if (unsigned NumOps = N->getNumOperands()) { 1245 if (N->getOperand(0).getValueType() == MVT::Other) 1246 return N->getOperand(0); 1247 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other) 1248 return N->getOperand(NumOps-1); 1249 for (unsigned i = 1; i < NumOps-1; ++i) 1250 if (N->getOperand(i).getValueType() == MVT::Other) 1251 return N->getOperand(i); 1252 } 1253 return SDValue(); 1254} 1255 1256SDValue DAGCombiner::visitTokenFactor(SDNode *N) { 1257 // If N has two operands, where one has an input chain equal to the other, 1258 // the 'other' chain is redundant. 1259 if (N->getNumOperands() == 2) { 1260 if (getInputChainForNode(N->getOperand(0).getNode()) == N->getOperand(1)) 1261 return N->getOperand(0); 1262 if (getInputChainForNode(N->getOperand(1).getNode()) == N->getOperand(0)) 1263 return N->getOperand(1); 1264 } 1265 1266 SmallVector<SDNode *, 8> TFs; // List of token factors to visit. 1267 SmallVector<SDValue, 8> Ops; // Ops for replacing token factor. 1268 SmallPtrSet<SDNode*, 16> SeenOps; 1269 bool Changed = false; // If we should replace this token factor. 1270 1271 // Start out with this token factor. 1272 TFs.push_back(N); 1273 1274 // Iterate through token factors. The TFs grows when new token factors are 1275 // encountered. 1276 for (unsigned i = 0; i < TFs.size(); ++i) { 1277 SDNode *TF = TFs[i]; 1278 1279 // Check each of the operands. 1280 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) { 1281 SDValue Op = TF->getOperand(i); 1282 1283 switch (Op.getOpcode()) { 1284 case ISD::EntryToken: 1285 // Entry tokens don't need to be added to the list. They are 1286 // rededundant. 1287 Changed = true; 1288 break; 1289 1290 case ISD::TokenFactor: 1291 if (Op.hasOneUse() && 1292 std::find(TFs.begin(), TFs.end(), Op.getNode()) == TFs.end()) { 1293 // Queue up for processing. 1294 TFs.push_back(Op.getNode()); 1295 // Clean up in case the token factor is removed. 1296 AddToWorkList(Op.getNode()); 1297 Changed = true; 1298 break; 1299 } 1300 // Fall thru 1301 1302 default: 1303 // Only add if it isn't already in the list. 1304 if (SeenOps.insert(Op.getNode())) 1305 Ops.push_back(Op); 1306 else 1307 Changed = true; 1308 break; 1309 } 1310 } 1311 } 1312 1313 SDValue Result; 1314 1315 // If we've change things around then replace token factor. 1316 if (Changed) { 1317 if (Ops.empty()) { 1318 // The entry token is the only possible outcome. 1319 Result = DAG.getEntryNode(); 1320 } else { 1321 // New and improved token factor. 1322 Result = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 1323 MVT::Other, &Ops[0], Ops.size()); 1324 } 1325 1326 // Don't add users to work list. 1327 return CombineTo(N, Result, false); 1328 } 1329 1330 return Result; 1331} 1332 1333/// MERGE_VALUES can always be eliminated. 1334SDValue DAGCombiner::visitMERGE_VALUES(SDNode *N) { 1335 WorkListRemover DeadNodes(*this); 1336 // Replacing results may cause a different MERGE_VALUES to suddenly 1337 // be CSE'd with N, and carry its uses with it. Iterate until no 1338 // uses remain, to ensure that the node can be safely deleted. 1339 // First add the users of this node to the work list so that they 1340 // can be tried again once they have new operands. 1341 AddUsersToWorkList(N); 1342 do { 1343 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 1344 DAG.ReplaceAllUsesOfValueWith(SDValue(N, i), N->getOperand(i)); 1345 } while (!N->use_empty()); 1346 removeFromWorkList(N); 1347 DAG.DeleteNode(N); 1348 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1349} 1350 1351static 1352SDValue combineShlAddConstant(DebugLoc DL, SDValue N0, SDValue N1, 1353 SelectionDAG &DAG) { 1354 EVT VT = N0.getValueType(); 1355 SDValue N00 = N0.getOperand(0); 1356 SDValue N01 = N0.getOperand(1); 1357 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01); 1358 1359 if (N01C && N00.getOpcode() == ISD::ADD && N00.getNode()->hasOneUse() && 1360 isa<ConstantSDNode>(N00.getOperand(1))) { 1361 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 1362 N0 = DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, 1363 DAG.getNode(ISD::SHL, N00.getDebugLoc(), VT, 1364 N00.getOperand(0), N01), 1365 DAG.getNode(ISD::SHL, N01.getDebugLoc(), VT, 1366 N00.getOperand(1), N01)); 1367 return DAG.getNode(ISD::ADD, DL, VT, N0, N1); 1368 } 1369 1370 return SDValue(); 1371} 1372 1373SDValue DAGCombiner::visitADD(SDNode *N) { 1374 SDValue N0 = N->getOperand(0); 1375 SDValue N1 = N->getOperand(1); 1376 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1377 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1378 EVT VT = N0.getValueType(); 1379 1380 // fold vector ops 1381 if (VT.isVector()) { 1382 SDValue FoldedVOp = SimplifyVBinOp(N); 1383 if (FoldedVOp.getNode()) return FoldedVOp; 1384 1385 // fold (add x, 0) -> x, vector edition 1386 if (ISD::isBuildVectorAllZeros(N1.getNode())) 1387 return N0; 1388 if (ISD::isBuildVectorAllZeros(N0.getNode())) 1389 return N1; 1390 } 1391 1392 // fold (add x, undef) -> undef 1393 if (N0.getOpcode() == ISD::UNDEF) 1394 return N0; 1395 if (N1.getOpcode() == ISD::UNDEF) 1396 return N1; 1397 // fold (add c1, c2) -> c1+c2 1398 if (N0C && N1C) 1399 return DAG.FoldConstantArithmetic(ISD::ADD, VT, N0C, N1C); 1400 // canonicalize constant to RHS 1401 if (N0C && !N1C) 1402 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0); 1403 // fold (add x, 0) -> x 1404 if (N1C && N1C->isNullValue()) 1405 return N0; 1406 // fold (add Sym, c) -> Sym+c 1407 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0)) 1408 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA) && N1C && 1409 GA->getOpcode() == ISD::GlobalAddress) 1410 return DAG.getGlobalAddress(GA->getGlobal(), N1C->getDebugLoc(), VT, 1411 GA->getOffset() + 1412 (uint64_t)N1C->getSExtValue()); 1413 // fold ((c1-A)+c2) -> (c1+c2)-A 1414 if (N1C && N0.getOpcode() == ISD::SUB) 1415 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0))) 1416 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1417 DAG.getConstant(N1C->getAPIntValue()+ 1418 N0C->getAPIntValue(), VT), 1419 N0.getOperand(1)); 1420 // reassociate add 1421 SDValue RADD = ReassociateOps(ISD::ADD, N->getDebugLoc(), N0, N1); 1422 if (RADD.getNode() != 0) 1423 return RADD; 1424 // fold ((0-A) + B) -> B-A 1425 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) && 1426 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue()) 1427 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1, N0.getOperand(1)); 1428 // fold (A + (0-B)) -> A-B 1429 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) && 1430 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue()) 1431 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, N1.getOperand(1)); 1432 // fold (A+(B-A)) -> B 1433 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1)) 1434 return N1.getOperand(0); 1435 // fold ((B-A)+A) -> B 1436 if (N0.getOpcode() == ISD::SUB && N1 == N0.getOperand(1)) 1437 return N0.getOperand(0); 1438 // fold (A+(B-(A+C))) to (B-C) 1439 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD && 1440 N0 == N1.getOperand(1).getOperand(0)) 1441 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0), 1442 N1.getOperand(1).getOperand(1)); 1443 // fold (A+(B-(C+A))) to (B-C) 1444 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD && 1445 N0 == N1.getOperand(1).getOperand(1)) 1446 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0), 1447 N1.getOperand(1).getOperand(0)); 1448 // fold (A+((B-A)+or-C)) to (B+or-C) 1449 if ((N1.getOpcode() == ISD::SUB || N1.getOpcode() == ISD::ADD) && 1450 N1.getOperand(0).getOpcode() == ISD::SUB && 1451 N0 == N1.getOperand(0).getOperand(1)) 1452 return DAG.getNode(N1.getOpcode(), N->getDebugLoc(), VT, 1453 N1.getOperand(0).getOperand(0), N1.getOperand(1)); 1454 1455 // fold (A-B)+(C-D) to (A+C)-(B+D) when A or C is constant 1456 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB) { 1457 SDValue N00 = N0.getOperand(0); 1458 SDValue N01 = N0.getOperand(1); 1459 SDValue N10 = N1.getOperand(0); 1460 SDValue N11 = N1.getOperand(1); 1461 1462 if (isa<ConstantSDNode>(N00) || isa<ConstantSDNode>(N10)) 1463 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1464 DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, N00, N10), 1465 DAG.getNode(ISD::ADD, N1.getDebugLoc(), VT, N01, N11)); 1466 } 1467 1468 if (!VT.isVector() && SimplifyDemandedBits(SDValue(N, 0))) 1469 return SDValue(N, 0); 1470 1471 // fold (a+b) -> (a|b) iff a and b share no bits. 1472 if (VT.isInteger() && !VT.isVector()) { 1473 APInt LHSZero, LHSOne; 1474 APInt RHSZero, RHSOne; 1475 DAG.ComputeMaskedBits(N0, LHSZero, LHSOne); 1476 1477 if (LHSZero.getBoolValue()) { 1478 DAG.ComputeMaskedBits(N1, RHSZero, RHSOne); 1479 1480 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1481 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1482 if ((RHSZero & ~LHSZero) == ~LHSZero || (LHSZero & ~RHSZero) == ~RHSZero) 1483 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1); 1484 } 1485 } 1486 1487 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 1488 if (N0.getOpcode() == ISD::SHL && N0.getNode()->hasOneUse()) { 1489 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N0, N1, DAG); 1490 if (Result.getNode()) return Result; 1491 } 1492 if (N1.getOpcode() == ISD::SHL && N1.getNode()->hasOneUse()) { 1493 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N1, N0, DAG); 1494 if (Result.getNode()) return Result; 1495 } 1496 1497 // fold (add x, shl(0 - y, n)) -> sub(x, shl(y, n)) 1498 if (N1.getOpcode() == ISD::SHL && 1499 N1.getOperand(0).getOpcode() == ISD::SUB) 1500 if (ConstantSDNode *C = 1501 dyn_cast<ConstantSDNode>(N1.getOperand(0).getOperand(0))) 1502 if (C->getAPIntValue() == 0) 1503 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, 1504 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1505 N1.getOperand(0).getOperand(1), 1506 N1.getOperand(1))); 1507 if (N0.getOpcode() == ISD::SHL && 1508 N0.getOperand(0).getOpcode() == ISD::SUB) 1509 if (ConstantSDNode *C = 1510 dyn_cast<ConstantSDNode>(N0.getOperand(0).getOperand(0))) 1511 if (C->getAPIntValue() == 0) 1512 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1, 1513 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1514 N0.getOperand(0).getOperand(1), 1515 N0.getOperand(1))); 1516 1517 if (N1.getOpcode() == ISD::AND) { 1518 SDValue AndOp0 = N1.getOperand(0); 1519 ConstantSDNode *AndOp1 = dyn_cast<ConstantSDNode>(N1->getOperand(1)); 1520 unsigned NumSignBits = DAG.ComputeNumSignBits(AndOp0); 1521 unsigned DestBits = VT.getScalarType().getSizeInBits(); 1522 1523 // (add z, (and (sbbl x, x), 1)) -> (sub z, (sbbl x, x)) 1524 // and similar xforms where the inner op is either ~0 or 0. 1525 if (NumSignBits == DestBits && AndOp1 && AndOp1->isOne()) { 1526 DebugLoc DL = N->getDebugLoc(); 1527 return DAG.getNode(ISD::SUB, DL, VT, N->getOperand(0), AndOp0); 1528 } 1529 } 1530 1531 // add (sext i1), X -> sub X, (zext i1) 1532 if (N0.getOpcode() == ISD::SIGN_EXTEND && 1533 N0.getOperand(0).getValueType() == MVT::i1 && 1534 !TLI.isOperationLegal(ISD::SIGN_EXTEND, MVT::i1)) { 1535 DebugLoc DL = N->getDebugLoc(); 1536 SDValue ZExt = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0)); 1537 return DAG.getNode(ISD::SUB, DL, VT, N1, ZExt); 1538 } 1539 1540 return SDValue(); 1541} 1542 1543SDValue DAGCombiner::visitADDC(SDNode *N) { 1544 SDValue N0 = N->getOperand(0); 1545 SDValue N1 = N->getOperand(1); 1546 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1547 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1548 EVT VT = N0.getValueType(); 1549 1550 // If the flag result is dead, turn this into an ADD. 1551 if (!N->hasAnyUseOfValue(1)) 1552 return CombineTo(N, DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, N1), 1553 DAG.getNode(ISD::CARRY_FALSE, 1554 N->getDebugLoc(), MVT::Glue)); 1555 1556 // canonicalize constant to RHS. 1557 if (N0C && !N1C) 1558 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0); 1559 1560 // fold (addc x, 0) -> x + no carry out 1561 if (N1C && N1C->isNullValue()) 1562 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, 1563 N->getDebugLoc(), MVT::Glue)); 1564 1565 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits. 1566 APInt LHSZero, LHSOne; 1567 APInt RHSZero, RHSOne; 1568 DAG.ComputeMaskedBits(N0, LHSZero, LHSOne); 1569 1570 if (LHSZero.getBoolValue()) { 1571 DAG.ComputeMaskedBits(N1, RHSZero, RHSOne); 1572 1573 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1574 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1575 if ((RHSZero & ~LHSZero) == ~LHSZero || (LHSZero & ~RHSZero) == ~RHSZero) 1576 return CombineTo(N, DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1), 1577 DAG.getNode(ISD::CARRY_FALSE, 1578 N->getDebugLoc(), MVT::Glue)); 1579 } 1580 1581 return SDValue(); 1582} 1583 1584SDValue DAGCombiner::visitADDE(SDNode *N) { 1585 SDValue N0 = N->getOperand(0); 1586 SDValue N1 = N->getOperand(1); 1587 SDValue CarryIn = N->getOperand(2); 1588 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1589 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1590 1591 // canonicalize constant to RHS 1592 if (N0C && !N1C) 1593 return DAG.getNode(ISD::ADDE, N->getDebugLoc(), N->getVTList(), 1594 N1, N0, CarryIn); 1595 1596 // fold (adde x, y, false) -> (addc x, y) 1597 if (CarryIn.getOpcode() == ISD::CARRY_FALSE) 1598 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N0, N1); 1599 1600 return SDValue(); 1601} 1602 1603// Since it may not be valid to emit a fold to zero for vector initializers 1604// check if we can before folding. 1605static SDValue tryFoldToZero(DebugLoc DL, const TargetLowering &TLI, EVT VT, 1606 SelectionDAG &DAG, bool LegalOperations) { 1607 if (!VT.isVector()) { 1608 return DAG.getConstant(0, VT); 1609 } 1610 if (!LegalOperations || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) { 1611 // Produce a vector of zeros. 1612 SDValue El = DAG.getConstant(0, VT.getVectorElementType()); 1613 std::vector<SDValue> Ops(VT.getVectorNumElements(), El); 1614 return DAG.getNode(ISD::BUILD_VECTOR, DL, VT, 1615 &Ops[0], Ops.size()); 1616 } 1617 return SDValue(); 1618} 1619 1620SDValue DAGCombiner::visitSUB(SDNode *N) { 1621 SDValue N0 = N->getOperand(0); 1622 SDValue N1 = N->getOperand(1); 1623 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1624 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1625 ConstantSDNode *N1C1 = N1.getOpcode() != ISD::ADD ? 0 : 1626 dyn_cast<ConstantSDNode>(N1.getOperand(1).getNode()); 1627 EVT VT = N0.getValueType(); 1628 1629 // fold vector ops 1630 if (VT.isVector()) { 1631 SDValue FoldedVOp = SimplifyVBinOp(N); 1632 if (FoldedVOp.getNode()) return FoldedVOp; 1633 1634 // fold (sub x, 0) -> x, vector edition 1635 if (ISD::isBuildVectorAllZeros(N1.getNode())) 1636 return N0; 1637 } 1638 1639 // fold (sub x, x) -> 0 1640 // FIXME: Refactor this and xor and other similar operations together. 1641 if (N0 == N1) 1642 return tryFoldToZero(N->getDebugLoc(), TLI, VT, DAG, LegalOperations); 1643 // fold (sub c1, c2) -> c1-c2 1644 if (N0C && N1C) 1645 return DAG.FoldConstantArithmetic(ISD::SUB, VT, N0C, N1C); 1646 // fold (sub x, c) -> (add x, -c) 1647 if (N1C) 1648 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, 1649 DAG.getConstant(-N1C->getAPIntValue(), VT)); 1650 // Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1) 1651 if (N0C && N0C->isAllOnesValue()) 1652 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0); 1653 // fold A-(A-B) -> B 1654 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(0)) 1655 return N1.getOperand(1); 1656 // fold (A+B)-A -> B 1657 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1) 1658 return N0.getOperand(1); 1659 // fold (A+B)-B -> A 1660 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1) 1661 return N0.getOperand(0); 1662 // fold C2-(A+C1) -> (C2-C1)-A 1663 if (N1.getOpcode() == ISD::ADD && N0C && N1C1) { 1664 SDValue NewC = DAG.getConstant(N0C->getAPIntValue() - N1C1->getAPIntValue(), 1665 VT); 1666 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, NewC, 1667 N1.getOperand(0)); 1668 } 1669 // fold ((A+(B+or-C))-B) -> A+or-C 1670 if (N0.getOpcode() == ISD::ADD && 1671 (N0.getOperand(1).getOpcode() == ISD::SUB || 1672 N0.getOperand(1).getOpcode() == ISD::ADD) && 1673 N0.getOperand(1).getOperand(0) == N1) 1674 return DAG.getNode(N0.getOperand(1).getOpcode(), N->getDebugLoc(), VT, 1675 N0.getOperand(0), N0.getOperand(1).getOperand(1)); 1676 // fold ((A+(C+B))-B) -> A+C 1677 if (N0.getOpcode() == ISD::ADD && 1678 N0.getOperand(1).getOpcode() == ISD::ADD && 1679 N0.getOperand(1).getOperand(1) == N1) 1680 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, 1681 N0.getOperand(0), N0.getOperand(1).getOperand(0)); 1682 // fold ((A-(B-C))-C) -> A-B 1683 if (N0.getOpcode() == ISD::SUB && 1684 N0.getOperand(1).getOpcode() == ISD::SUB && 1685 N0.getOperand(1).getOperand(1) == N1) 1686 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1687 N0.getOperand(0), N0.getOperand(1).getOperand(0)); 1688 1689 // If either operand of a sub is undef, the result is undef 1690 if (N0.getOpcode() == ISD::UNDEF) 1691 return N0; 1692 if (N1.getOpcode() == ISD::UNDEF) 1693 return N1; 1694 1695 // If the relocation model supports it, consider symbol offsets. 1696 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0)) 1697 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA)) { 1698 // fold (sub Sym, c) -> Sym-c 1699 if (N1C && GA->getOpcode() == ISD::GlobalAddress) 1700 return DAG.getGlobalAddress(GA->getGlobal(), N1C->getDebugLoc(), VT, 1701 GA->getOffset() - 1702 (uint64_t)N1C->getSExtValue()); 1703 // fold (sub Sym+c1, Sym+c2) -> c1-c2 1704 if (GlobalAddressSDNode *GB = dyn_cast<GlobalAddressSDNode>(N1)) 1705 if (GA->getGlobal() == GB->getGlobal()) 1706 return DAG.getConstant((uint64_t)GA->getOffset() - GB->getOffset(), 1707 VT); 1708 } 1709 1710 return SDValue(); 1711} 1712 1713SDValue DAGCombiner::visitSUBC(SDNode *N) { 1714 SDValue N0 = N->getOperand(0); 1715 SDValue N1 = N->getOperand(1); 1716 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1717 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1718 EVT VT = N0.getValueType(); 1719 1720 // If the flag result is dead, turn this into an SUB. 1721 if (!N->hasAnyUseOfValue(1)) 1722 return CombineTo(N, DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, N1), 1723 DAG.getNode(ISD::CARRY_FALSE, N->getDebugLoc(), 1724 MVT::Glue)); 1725 1726 // fold (subc x, x) -> 0 + no borrow 1727 if (N0 == N1) 1728 return CombineTo(N, DAG.getConstant(0, VT), 1729 DAG.getNode(ISD::CARRY_FALSE, N->getDebugLoc(), 1730 MVT::Glue)); 1731 1732 // fold (subc x, 0) -> x + no borrow 1733 if (N1C && N1C->isNullValue()) 1734 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, N->getDebugLoc(), 1735 MVT::Glue)); 1736 1737 // Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1) + no borrow 1738 if (N0C && N0C->isAllOnesValue()) 1739 return CombineTo(N, DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0), 1740 DAG.getNode(ISD::CARRY_FALSE, N->getDebugLoc(), 1741 MVT::Glue)); 1742 1743 return SDValue(); 1744} 1745 1746SDValue DAGCombiner::visitSUBE(SDNode *N) { 1747 SDValue N0 = N->getOperand(0); 1748 SDValue N1 = N->getOperand(1); 1749 SDValue CarryIn = N->getOperand(2); 1750 1751 // fold (sube x, y, false) -> (subc x, y) 1752 if (CarryIn.getOpcode() == ISD::CARRY_FALSE) 1753 return DAG.getNode(ISD::SUBC, N->getDebugLoc(), N->getVTList(), N0, N1); 1754 1755 return SDValue(); 1756} 1757 1758SDValue DAGCombiner::visitMUL(SDNode *N) { 1759 SDValue N0 = N->getOperand(0); 1760 SDValue N1 = N->getOperand(1); 1761 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1762 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1763 EVT VT = N0.getValueType(); 1764 1765 // fold vector ops 1766 if (VT.isVector()) { 1767 SDValue FoldedVOp = SimplifyVBinOp(N); 1768 if (FoldedVOp.getNode()) return FoldedVOp; 1769 } 1770 1771 // fold (mul x, undef) -> 0 1772 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1773 return DAG.getConstant(0, VT); 1774 // fold (mul c1, c2) -> c1*c2 1775 if (N0C && N1C) 1776 return DAG.FoldConstantArithmetic(ISD::MUL, VT, N0C, N1C); 1777 // canonicalize constant to RHS 1778 if (N0C && !N1C) 1779 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, N1, N0); 1780 // fold (mul x, 0) -> 0 1781 if (N1C && N1C->isNullValue()) 1782 return N1; 1783 // fold (mul x, -1) -> 0-x 1784 if (N1C && N1C->isAllOnesValue()) 1785 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1786 DAG.getConstant(0, VT), N0); 1787 // fold (mul x, (1 << c)) -> x << c 1788 if (N1C && N1C->getAPIntValue().isPowerOf2()) 1789 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 1790 DAG.getConstant(N1C->getAPIntValue().logBase2(), 1791 getShiftAmountTy(N0.getValueType()))); 1792 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c 1793 if (N1C && (-N1C->getAPIntValue()).isPowerOf2()) { 1794 unsigned Log2Val = (-N1C->getAPIntValue()).logBase2(); 1795 // FIXME: If the input is something that is easily negated (e.g. a 1796 // single-use add), we should put the negate there. 1797 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1798 DAG.getConstant(0, VT), 1799 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 1800 DAG.getConstant(Log2Val, 1801 getShiftAmountTy(N0.getValueType())))); 1802 } 1803 // (mul (shl X, c1), c2) -> (mul X, c2 << c1) 1804 if (N1C && N0.getOpcode() == ISD::SHL && 1805 isa<ConstantSDNode>(N0.getOperand(1))) { 1806 SDValue C3 = DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1807 N1, N0.getOperand(1)); 1808 AddToWorkList(C3.getNode()); 1809 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1810 N0.getOperand(0), C3); 1811 } 1812 1813 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one 1814 // use. 1815 { 1816 SDValue Sh(0,0), Y(0,0); 1817 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)). 1818 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) && 1819 N0.getNode()->hasOneUse()) { 1820 Sh = N0; Y = N1; 1821 } else if (N1.getOpcode() == ISD::SHL && 1822 isa<ConstantSDNode>(N1.getOperand(1)) && 1823 N1.getNode()->hasOneUse()) { 1824 Sh = N1; Y = N0; 1825 } 1826 1827 if (Sh.getNode()) { 1828 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1829 Sh.getOperand(0), Y); 1830 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1831 Mul, Sh.getOperand(1)); 1832 } 1833 } 1834 1835 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2) 1836 if (N1C && N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse() && 1837 isa<ConstantSDNode>(N0.getOperand(1))) 1838 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, 1839 DAG.getNode(ISD::MUL, N0.getDebugLoc(), VT, 1840 N0.getOperand(0), N1), 1841 DAG.getNode(ISD::MUL, N1.getDebugLoc(), VT, 1842 N0.getOperand(1), N1)); 1843 1844 // reassociate mul 1845 SDValue RMUL = ReassociateOps(ISD::MUL, N->getDebugLoc(), N0, N1); 1846 if (RMUL.getNode() != 0) 1847 return RMUL; 1848 1849 return SDValue(); 1850} 1851 1852SDValue DAGCombiner::visitSDIV(SDNode *N) { 1853 SDValue N0 = N->getOperand(0); 1854 SDValue N1 = N->getOperand(1); 1855 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1856 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1857 EVT VT = N->getValueType(0); 1858 1859 // fold vector ops 1860 if (VT.isVector()) { 1861 SDValue FoldedVOp = SimplifyVBinOp(N); 1862 if (FoldedVOp.getNode()) return FoldedVOp; 1863 } 1864 1865 // fold (sdiv c1, c2) -> c1/c2 1866 if (N0C && N1C && !N1C->isNullValue()) 1867 return DAG.FoldConstantArithmetic(ISD::SDIV, VT, N0C, N1C); 1868 // fold (sdiv X, 1) -> X 1869 if (N1C && N1C->getAPIntValue() == 1LL) 1870 return N0; 1871 // fold (sdiv X, -1) -> 0-X 1872 if (N1C && N1C->isAllOnesValue()) 1873 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1874 DAG.getConstant(0, VT), N0); 1875 // If we know the sign bits of both operands are zero, strength reduce to a 1876 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2 1877 if (!VT.isVector()) { 1878 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 1879 return DAG.getNode(ISD::UDIV, N->getDebugLoc(), N1.getValueType(), 1880 N0, N1); 1881 } 1882 // fold (sdiv X, pow2) -> simple ops after legalize 1883 if (N1C && !N1C->isNullValue() && 1884 (N1C->getAPIntValue().isPowerOf2() || 1885 (-N1C->getAPIntValue()).isPowerOf2())) { 1886 // If dividing by powers of two is cheap, then don't perform the following 1887 // fold. 1888 if (TLI.isPow2DivCheap()) 1889 return SDValue(); 1890 1891 unsigned lg2 = N1C->getAPIntValue().countTrailingZeros(); 1892 1893 // Splat the sign bit into the register 1894 SDValue SGN = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0, 1895 DAG.getConstant(VT.getSizeInBits()-1, 1896 getShiftAmountTy(N0.getValueType()))); 1897 AddToWorkList(SGN.getNode()); 1898 1899 // Add (N0 < 0) ? abs2 - 1 : 0; 1900 SDValue SRL = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, SGN, 1901 DAG.getConstant(VT.getSizeInBits() - lg2, 1902 getShiftAmountTy(SGN.getValueType()))); 1903 SDValue ADD = DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, SRL); 1904 AddToWorkList(SRL.getNode()); 1905 AddToWorkList(ADD.getNode()); // Divide by pow2 1906 SDValue SRA = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, ADD, 1907 DAG.getConstant(lg2, getShiftAmountTy(ADD.getValueType()))); 1908 1909 // If we're dividing by a positive value, we're done. Otherwise, we must 1910 // negate the result. 1911 if (N1C->getAPIntValue().isNonNegative()) 1912 return SRA; 1913 1914 AddToWorkList(SRA.getNode()); 1915 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1916 DAG.getConstant(0, VT), SRA); 1917 } 1918 1919 // if integer divide is expensive and we satisfy the requirements, emit an 1920 // alternate sequence. 1921 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) { 1922 SDValue Op = BuildSDIV(N); 1923 if (Op.getNode()) return Op; 1924 } 1925 1926 // undef / X -> 0 1927 if (N0.getOpcode() == ISD::UNDEF) 1928 return DAG.getConstant(0, VT); 1929 // X / undef -> undef 1930 if (N1.getOpcode() == ISD::UNDEF) 1931 return N1; 1932 1933 return SDValue(); 1934} 1935 1936SDValue DAGCombiner::visitUDIV(SDNode *N) { 1937 SDValue N0 = N->getOperand(0); 1938 SDValue N1 = N->getOperand(1); 1939 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1940 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1941 EVT VT = N->getValueType(0); 1942 1943 // fold vector ops 1944 if (VT.isVector()) { 1945 SDValue FoldedVOp = SimplifyVBinOp(N); 1946 if (FoldedVOp.getNode()) return FoldedVOp; 1947 } 1948 1949 // fold (udiv c1, c2) -> c1/c2 1950 if (N0C && N1C && !N1C->isNullValue()) 1951 return DAG.FoldConstantArithmetic(ISD::UDIV, VT, N0C, N1C); 1952 // fold (udiv x, (1 << c)) -> x >>u c 1953 if (N1C && N1C->getAPIntValue().isPowerOf2()) 1954 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, 1955 DAG.getConstant(N1C->getAPIntValue().logBase2(), 1956 getShiftAmountTy(N0.getValueType()))); 1957 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2 1958 if (N1.getOpcode() == ISD::SHL) { 1959 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1960 if (SHC->getAPIntValue().isPowerOf2()) { 1961 EVT ADDVT = N1.getOperand(1).getValueType(); 1962 SDValue Add = DAG.getNode(ISD::ADD, N->getDebugLoc(), ADDVT, 1963 N1.getOperand(1), 1964 DAG.getConstant(SHC->getAPIntValue() 1965 .logBase2(), 1966 ADDVT)); 1967 AddToWorkList(Add.getNode()); 1968 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, Add); 1969 } 1970 } 1971 } 1972 // fold (udiv x, c) -> alternate 1973 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) { 1974 SDValue Op = BuildUDIV(N); 1975 if (Op.getNode()) return Op; 1976 } 1977 1978 // undef / X -> 0 1979 if (N0.getOpcode() == ISD::UNDEF) 1980 return DAG.getConstant(0, VT); 1981 // X / undef -> undef 1982 if (N1.getOpcode() == ISD::UNDEF) 1983 return N1; 1984 1985 return SDValue(); 1986} 1987 1988SDValue DAGCombiner::visitSREM(SDNode *N) { 1989 SDValue N0 = N->getOperand(0); 1990 SDValue N1 = N->getOperand(1); 1991 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1992 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1993 EVT VT = N->getValueType(0); 1994 1995 // fold (srem c1, c2) -> c1%c2 1996 if (N0C && N1C && !N1C->isNullValue()) 1997 return DAG.FoldConstantArithmetic(ISD::SREM, VT, N0C, N1C); 1998 // If we know the sign bits of both operands are zero, strength reduce to a 1999 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15 2000 if (!VT.isVector()) { 2001 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 2002 return DAG.getNode(ISD::UREM, N->getDebugLoc(), VT, N0, N1); 2003 } 2004 2005 // If X/C can be simplified by the division-by-constant logic, lower 2006 // X%C to the equivalent of X-X/C*C. 2007 if (N1C && !N1C->isNullValue()) { 2008 SDValue Div = DAG.getNode(ISD::SDIV, N->getDebugLoc(), VT, N0, N1); 2009 AddToWorkList(Div.getNode()); 2010 SDValue OptimizedDiv = combine(Div.getNode()); 2011 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) { 2012 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 2013 OptimizedDiv, N1); 2014 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul); 2015 AddToWorkList(Mul.getNode()); 2016 return Sub; 2017 } 2018 } 2019 2020 // undef % X -> 0 2021 if (N0.getOpcode() == ISD::UNDEF) 2022 return DAG.getConstant(0, VT); 2023 // X % undef -> undef 2024 if (N1.getOpcode() == ISD::UNDEF) 2025 return N1; 2026 2027 return SDValue(); 2028} 2029 2030SDValue DAGCombiner::visitUREM(SDNode *N) { 2031 SDValue N0 = N->getOperand(0); 2032 SDValue N1 = N->getOperand(1); 2033 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2034 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2035 EVT VT = N->getValueType(0); 2036 2037 // fold (urem c1, c2) -> c1%c2 2038 if (N0C && N1C && !N1C->isNullValue()) 2039 return DAG.FoldConstantArithmetic(ISD::UREM, VT, N0C, N1C); 2040 // fold (urem x, pow2) -> (and x, pow2-1) 2041 if (N1C && !N1C->isNullValue() && N1C->getAPIntValue().isPowerOf2()) 2042 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, 2043 DAG.getConstant(N1C->getAPIntValue()-1,VT)); 2044 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1)) 2045 if (N1.getOpcode() == ISD::SHL) { 2046 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 2047 if (SHC->getAPIntValue().isPowerOf2()) { 2048 SDValue Add = 2049 DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, 2050 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), 2051 VT)); 2052 AddToWorkList(Add.getNode()); 2053 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, Add); 2054 } 2055 } 2056 } 2057 2058 // If X/C can be simplified by the division-by-constant logic, lower 2059 // X%C to the equivalent of X-X/C*C. 2060 if (N1C && !N1C->isNullValue()) { 2061 SDValue Div = DAG.getNode(ISD::UDIV, N->getDebugLoc(), VT, N0, N1); 2062 AddToWorkList(Div.getNode()); 2063 SDValue OptimizedDiv = combine(Div.getNode()); 2064 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) { 2065 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 2066 OptimizedDiv, N1); 2067 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul); 2068 AddToWorkList(Mul.getNode()); 2069 return Sub; 2070 } 2071 } 2072 2073 // undef % X -> 0 2074 if (N0.getOpcode() == ISD::UNDEF) 2075 return DAG.getConstant(0, VT); 2076 // X % undef -> undef 2077 if (N1.getOpcode() == ISD::UNDEF) 2078 return N1; 2079 2080 return SDValue(); 2081} 2082 2083SDValue DAGCombiner::visitMULHS(SDNode *N) { 2084 SDValue N0 = N->getOperand(0); 2085 SDValue N1 = N->getOperand(1); 2086 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2087 EVT VT = N->getValueType(0); 2088 DebugLoc DL = N->getDebugLoc(); 2089 2090 // fold (mulhs x, 0) -> 0 2091 if (N1C && N1C->isNullValue()) 2092 return N1; 2093 // fold (mulhs x, 1) -> (sra x, size(x)-1) 2094 if (N1C && N1C->getAPIntValue() == 1) 2095 return DAG.getNode(ISD::SRA, N->getDebugLoc(), N0.getValueType(), N0, 2096 DAG.getConstant(N0.getValueType().getSizeInBits() - 1, 2097 getShiftAmountTy(N0.getValueType()))); 2098 // fold (mulhs x, undef) -> 0 2099 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 2100 return DAG.getConstant(0, VT); 2101 2102 // If the type twice as wide is legal, transform the mulhs to a wider multiply 2103 // plus a shift. 2104 if (VT.isSimple() && !VT.isVector()) { 2105 MVT Simple = VT.getSimpleVT(); 2106 unsigned SimpleSize = Simple.getSizeInBits(); 2107 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2); 2108 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { 2109 N0 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N0); 2110 N1 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N1); 2111 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1); 2112 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1, 2113 DAG.getConstant(SimpleSize, getShiftAmountTy(N1.getValueType()))); 2114 return DAG.getNode(ISD::TRUNCATE, DL, VT, N1); 2115 } 2116 } 2117 2118 return SDValue(); 2119} 2120 2121SDValue DAGCombiner::visitMULHU(SDNode *N) { 2122 SDValue N0 = N->getOperand(0); 2123 SDValue N1 = N->getOperand(1); 2124 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2125 EVT VT = N->getValueType(0); 2126 DebugLoc DL = N->getDebugLoc(); 2127 2128 // fold (mulhu x, 0) -> 0 2129 if (N1C && N1C->isNullValue()) 2130 return N1; 2131 // fold (mulhu x, 1) -> 0 2132 if (N1C && N1C->getAPIntValue() == 1) 2133 return DAG.getConstant(0, N0.getValueType()); 2134 // fold (mulhu x, undef) -> 0 2135 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 2136 return DAG.getConstant(0, VT); 2137 2138 // If the type twice as wide is legal, transform the mulhu to a wider multiply 2139 // plus a shift. 2140 if (VT.isSimple() && !VT.isVector()) { 2141 MVT Simple = VT.getSimpleVT(); 2142 unsigned SimpleSize = Simple.getSizeInBits(); 2143 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2); 2144 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { 2145 N0 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N0); 2146 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N1); 2147 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1); 2148 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1, 2149 DAG.getConstant(SimpleSize, getShiftAmountTy(N1.getValueType()))); 2150 return DAG.getNode(ISD::TRUNCATE, DL, VT, N1); 2151 } 2152 } 2153 2154 return SDValue(); 2155} 2156 2157/// SimplifyNodeWithTwoResults - Perform optimizations common to nodes that 2158/// compute two values. LoOp and HiOp give the opcodes for the two computations 2159/// that are being performed. Return true if a simplification was made. 2160/// 2161SDValue DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 2162 unsigned HiOp) { 2163 // If the high half is not needed, just compute the low half. 2164 bool HiExists = N->hasAnyUseOfValue(1); 2165 if (!HiExists && 2166 (!LegalOperations || 2167 TLI.isOperationLegal(LoOp, N->getValueType(0)))) { 2168 SDValue Res = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0), 2169 N->op_begin(), N->getNumOperands()); 2170 return CombineTo(N, Res, Res); 2171 } 2172 2173 // If the low half is not needed, just compute the high half. 2174 bool LoExists = N->hasAnyUseOfValue(0); 2175 if (!LoExists && 2176 (!LegalOperations || 2177 TLI.isOperationLegal(HiOp, N->getValueType(1)))) { 2178 SDValue Res = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1), 2179 N->op_begin(), N->getNumOperands()); 2180 return CombineTo(N, Res, Res); 2181 } 2182 2183 // If both halves are used, return as it is. 2184 if (LoExists && HiExists) 2185 return SDValue(); 2186 2187 // If the two computed results can be simplified separately, separate them. 2188 if (LoExists) { 2189 SDValue Lo = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0), 2190 N->op_begin(), N->getNumOperands()); 2191 AddToWorkList(Lo.getNode()); 2192 SDValue LoOpt = combine(Lo.getNode()); 2193 if (LoOpt.getNode() && LoOpt.getNode() != Lo.getNode() && 2194 (!LegalOperations || 2195 TLI.isOperationLegal(LoOpt.getOpcode(), LoOpt.getValueType()))) 2196 return CombineTo(N, LoOpt, LoOpt); 2197 } 2198 2199 if (HiExists) { 2200 SDValue Hi = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1), 2201 N->op_begin(), N->getNumOperands()); 2202 AddToWorkList(Hi.getNode()); 2203 SDValue HiOpt = combine(Hi.getNode()); 2204 if (HiOpt.getNode() && HiOpt != Hi && 2205 (!LegalOperations || 2206 TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType()))) 2207 return CombineTo(N, HiOpt, HiOpt); 2208 } 2209 2210 return SDValue(); 2211} 2212 2213SDValue DAGCombiner::visitSMUL_LOHI(SDNode *N) { 2214 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS); 2215 if (Res.getNode()) return Res; 2216 2217 EVT VT = N->getValueType(0); 2218 DebugLoc DL = N->getDebugLoc(); 2219 2220 // If the type twice as wide is legal, transform the mulhu to a wider multiply 2221 // plus a shift. 2222 if (VT.isSimple() && !VT.isVector()) { 2223 MVT Simple = VT.getSimpleVT(); 2224 unsigned SimpleSize = Simple.getSizeInBits(); 2225 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2); 2226 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { 2227 SDValue Lo = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(0)); 2228 SDValue Hi = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(1)); 2229 Lo = DAG.getNode(ISD::MUL, DL, NewVT, Lo, Hi); 2230 // Compute the high part as N1. 2231 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo, 2232 DAG.getConstant(SimpleSize, getShiftAmountTy(Lo.getValueType()))); 2233 Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi); 2234 // Compute the low part as N0. 2235 Lo = DAG.getNode(ISD::TRUNCATE, DL, VT, Lo); 2236 return CombineTo(N, Lo, Hi); 2237 } 2238 } 2239 2240 return SDValue(); 2241} 2242 2243SDValue DAGCombiner::visitUMUL_LOHI(SDNode *N) { 2244 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU); 2245 if (Res.getNode()) return Res; 2246 2247 EVT VT = N->getValueType(0); 2248 DebugLoc DL = N->getDebugLoc(); 2249 2250 // If the type twice as wide is legal, transform the mulhu to a wider multiply 2251 // plus a shift. 2252 if (VT.isSimple() && !VT.isVector()) { 2253 MVT Simple = VT.getSimpleVT(); 2254 unsigned SimpleSize = Simple.getSizeInBits(); 2255 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2); 2256 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { 2257 SDValue Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(0)); 2258 SDValue Hi = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(1)); 2259 Lo = DAG.getNode(ISD::MUL, DL, NewVT, Lo, Hi); 2260 // Compute the high part as N1. 2261 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo, 2262 DAG.getConstant(SimpleSize, getShiftAmountTy(Lo.getValueType()))); 2263 Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi); 2264 // Compute the low part as N0. 2265 Lo = DAG.getNode(ISD::TRUNCATE, DL, VT, Lo); 2266 return CombineTo(N, Lo, Hi); 2267 } 2268 } 2269 2270 return SDValue(); 2271} 2272 2273SDValue DAGCombiner::visitSMULO(SDNode *N) { 2274 // (smulo x, 2) -> (saddo x, x) 2275 if (ConstantSDNode *C2 = dyn_cast<ConstantSDNode>(N->getOperand(1))) 2276 if (C2->getAPIntValue() == 2) 2277 return DAG.getNode(ISD::SADDO, N->getDebugLoc(), N->getVTList(), 2278 N->getOperand(0), N->getOperand(0)); 2279 2280 return SDValue(); 2281} 2282 2283SDValue DAGCombiner::visitUMULO(SDNode *N) { 2284 // (umulo x, 2) -> (uaddo x, x) 2285 if (ConstantSDNode *C2 = dyn_cast<ConstantSDNode>(N->getOperand(1))) 2286 if (C2->getAPIntValue() == 2) 2287 return DAG.getNode(ISD::UADDO, N->getDebugLoc(), N->getVTList(), 2288 N->getOperand(0), N->getOperand(0)); 2289 2290 return SDValue(); 2291} 2292 2293SDValue DAGCombiner::visitSDIVREM(SDNode *N) { 2294 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM); 2295 if (Res.getNode()) return Res; 2296 2297 return SDValue(); 2298} 2299 2300SDValue DAGCombiner::visitUDIVREM(SDNode *N) { 2301 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM); 2302 if (Res.getNode()) return Res; 2303 2304 return SDValue(); 2305} 2306 2307/// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with 2308/// two operands of the same opcode, try to simplify it. 2309SDValue DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) { 2310 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1); 2311 EVT VT = N0.getValueType(); 2312 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!"); 2313 2314 // Bail early if none of these transforms apply. 2315 if (N0.getNode()->getNumOperands() == 0) return SDValue(); 2316 2317 // For each of OP in AND/OR/XOR: 2318 // fold (OP (zext x), (zext y)) -> (zext (OP x, y)) 2319 // fold (OP (sext x), (sext y)) -> (sext (OP x, y)) 2320 // fold (OP (aext x), (aext y)) -> (aext (OP x, y)) 2321 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y)) (if trunc isn't free) 2322 // 2323 // do not sink logical op inside of a vector extend, since it may combine 2324 // into a vsetcc. 2325 EVT Op0VT = N0.getOperand(0).getValueType(); 2326 if ((N0.getOpcode() == ISD::ZERO_EXTEND || 2327 N0.getOpcode() == ISD::SIGN_EXTEND || 2328 // Avoid infinite looping with PromoteIntBinOp. 2329 (N0.getOpcode() == ISD::ANY_EXTEND && 2330 (!LegalTypes || TLI.isTypeDesirableForOp(N->getOpcode(), Op0VT))) || 2331 (N0.getOpcode() == ISD::TRUNCATE && 2332 (!TLI.isZExtFree(VT, Op0VT) || 2333 !TLI.isTruncateFree(Op0VT, VT)) && 2334 TLI.isTypeLegal(Op0VT))) && 2335 !VT.isVector() && 2336 Op0VT == N1.getOperand(0).getValueType() && 2337 (!LegalOperations || TLI.isOperationLegal(N->getOpcode(), Op0VT))) { 2338 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(), 2339 N0.getOperand(0).getValueType(), 2340 N0.getOperand(0), N1.getOperand(0)); 2341 AddToWorkList(ORNode.getNode()); 2342 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, ORNode); 2343 } 2344 2345 // For each of OP in SHL/SRL/SRA/AND... 2346 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z) 2347 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z) 2348 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z) 2349 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL || 2350 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) && 2351 N0.getOperand(1) == N1.getOperand(1)) { 2352 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(), 2353 N0.getOperand(0).getValueType(), 2354 N0.getOperand(0), N1.getOperand(0)); 2355 AddToWorkList(ORNode.getNode()); 2356 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, 2357 ORNode, N0.getOperand(1)); 2358 } 2359 2360 // Simplify xor/and/or (bitcast(A), bitcast(B)) -> bitcast(op (A,B)) 2361 // Only perform this optimization after type legalization and before 2362 // LegalizeVectorOprs. LegalizeVectorOprs promotes vector operations by 2363 // adding bitcasts. For example (xor v4i32) is promoted to (v2i64), and 2364 // we don't want to undo this promotion. 2365 // We also handle SCALAR_TO_VECTOR because xor/or/and operations are cheaper 2366 // on scalars. 2367 if ((N0.getOpcode() == ISD::BITCAST || 2368 N0.getOpcode() == ISD::SCALAR_TO_VECTOR) && 2369 Level == AfterLegalizeTypes) { 2370 SDValue In0 = N0.getOperand(0); 2371 SDValue In1 = N1.getOperand(0); 2372 EVT In0Ty = In0.getValueType(); 2373 EVT In1Ty = In1.getValueType(); 2374 DebugLoc DL = N->getDebugLoc(); 2375 // If both incoming values are integers, and the original types are the 2376 // same. 2377 if (In0Ty.isInteger() && In1Ty.isInteger() && In0Ty == In1Ty) { 2378 SDValue Op = DAG.getNode(N->getOpcode(), DL, In0Ty, In0, In1); 2379 SDValue BC = DAG.getNode(N0.getOpcode(), DL, VT, Op); 2380 AddToWorkList(Op.getNode()); 2381 return BC; 2382 } 2383 } 2384 2385 // Xor/and/or are indifferent to the swizzle operation (shuffle of one value). 2386 // Simplify xor/and/or (shuff(A), shuff(B)) -> shuff(op (A,B)) 2387 // If both shuffles use the same mask, and both shuffle within a single 2388 // vector, then it is worthwhile to move the swizzle after the operation. 2389 // The type-legalizer generates this pattern when loading illegal 2390 // vector types from memory. In many cases this allows additional shuffle 2391 // optimizations. 2392 if (N0.getOpcode() == ISD::VECTOR_SHUFFLE && Level < AfterLegalizeDAG && 2393 N0.getOperand(1).getOpcode() == ISD::UNDEF && 2394 N1.getOperand(1).getOpcode() == ISD::UNDEF) { 2395 ShuffleVectorSDNode *SVN0 = cast<ShuffleVectorSDNode>(N0); 2396 ShuffleVectorSDNode *SVN1 = cast<ShuffleVectorSDNode>(N1); 2397 2398 assert(N0.getOperand(0).getValueType() == N1.getOperand(1).getValueType() && 2399 "Inputs to shuffles are not the same type"); 2400 2401 unsigned NumElts = VT.getVectorNumElements(); 2402 2403 // Check that both shuffles use the same mask. The masks are known to be of 2404 // the same length because the result vector type is the same. 2405 bool SameMask = true; 2406 for (unsigned i = 0; i != NumElts; ++i) { 2407 int Idx0 = SVN0->getMaskElt(i); 2408 int Idx1 = SVN1->getMaskElt(i); 2409 if (Idx0 != Idx1) { 2410 SameMask = false; 2411 break; 2412 } 2413 } 2414 2415 if (SameMask) { 2416 SDValue Op = DAG.getNode(N->getOpcode(), N->getDebugLoc(), VT, 2417 N0.getOperand(0), N1.getOperand(0)); 2418 AddToWorkList(Op.getNode()); 2419 return DAG.getVectorShuffle(VT, N->getDebugLoc(), Op, 2420 DAG.getUNDEF(VT), &SVN0->getMask()[0]); 2421 } 2422 } 2423 2424 return SDValue(); 2425} 2426 2427SDValue DAGCombiner::visitAND(SDNode *N) { 2428 SDValue N0 = N->getOperand(0); 2429 SDValue N1 = N->getOperand(1); 2430 SDValue LL, LR, RL, RR, CC0, CC1; 2431 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2432 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2433 EVT VT = N1.getValueType(); 2434 unsigned BitWidth = VT.getScalarType().getSizeInBits(); 2435 2436 // fold vector ops 2437 if (VT.isVector()) { 2438 SDValue FoldedVOp = SimplifyVBinOp(N); 2439 if (FoldedVOp.getNode()) return FoldedVOp; 2440 2441 // fold (and x, 0) -> 0, vector edition 2442 if (ISD::isBuildVectorAllZeros(N0.getNode())) 2443 return N0; 2444 if (ISD::isBuildVectorAllZeros(N1.getNode())) 2445 return N1; 2446 2447 // fold (and x, -1) -> x, vector edition 2448 if (ISD::isBuildVectorAllOnes(N0.getNode())) 2449 return N1; 2450 if (ISD::isBuildVectorAllOnes(N1.getNode())) 2451 return N0; 2452 } 2453 2454 // fold (and x, undef) -> 0 2455 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 2456 return DAG.getConstant(0, VT); 2457 // fold (and c1, c2) -> c1&c2 2458 if (N0C && N1C) 2459 return DAG.FoldConstantArithmetic(ISD::AND, VT, N0C, N1C); 2460 // canonicalize constant to RHS 2461 if (N0C && !N1C) 2462 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N1, N0); 2463 // fold (and x, -1) -> x 2464 if (N1C && N1C->isAllOnesValue()) 2465 return N0; 2466 // if (and x, c) is known to be zero, return 0 2467 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0), 2468 APInt::getAllOnesValue(BitWidth))) 2469 return DAG.getConstant(0, VT); 2470 // reassociate and 2471 SDValue RAND = ReassociateOps(ISD::AND, N->getDebugLoc(), N0, N1); 2472 if (RAND.getNode() != 0) 2473 return RAND; 2474 // fold (and (or x, C), D) -> D if (C & D) == D 2475 if (N1C && N0.getOpcode() == ISD::OR) 2476 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 2477 if ((ORI->getAPIntValue() & N1C->getAPIntValue()) == N1C->getAPIntValue()) 2478 return N1; 2479 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits. 2480 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 2481 SDValue N0Op0 = N0.getOperand(0); 2482 APInt Mask = ~N1C->getAPIntValue(); 2483 Mask = Mask.trunc(N0Op0.getValueSizeInBits()); 2484 if (DAG.MaskedValueIsZero(N0Op0, Mask)) { 2485 SDValue Zext = DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), 2486 N0.getValueType(), N0Op0); 2487 2488 // Replace uses of the AND with uses of the Zero extend node. 2489 CombineTo(N, Zext); 2490 2491 // We actually want to replace all uses of the any_extend with the 2492 // zero_extend, to avoid duplicating things. This will later cause this 2493 // AND to be folded. 2494 CombineTo(N0.getNode(), Zext); 2495 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2496 } 2497 } 2498 // similarly fold (and (X (load ([non_ext|any_ext|zero_ext] V))), c) -> 2499 // (X (load ([non_ext|zero_ext] V))) if 'and' only clears top bits which must 2500 // already be zero by virtue of the width of the base type of the load. 2501 // 2502 // the 'X' node here can either be nothing or an extract_vector_elt to catch 2503 // more cases. 2504 if ((N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT && 2505 N0.getOperand(0).getOpcode() == ISD::LOAD) || 2506 N0.getOpcode() == ISD::LOAD) { 2507 LoadSDNode *Load = cast<LoadSDNode>( (N0.getOpcode() == ISD::LOAD) ? 2508 N0 : N0.getOperand(0) ); 2509 2510 // Get the constant (if applicable) the zero'th operand is being ANDed with. 2511 // This can be a pure constant or a vector splat, in which case we treat the 2512 // vector as a scalar and use the splat value. 2513 APInt Constant = APInt::getNullValue(1); 2514 if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(N1)) { 2515 Constant = C->getAPIntValue(); 2516 } else if (BuildVectorSDNode *Vector = dyn_cast<BuildVectorSDNode>(N1)) { 2517 APInt SplatValue, SplatUndef; 2518 unsigned SplatBitSize; 2519 bool HasAnyUndefs; 2520 bool IsSplat = Vector->isConstantSplat(SplatValue, SplatUndef, 2521 SplatBitSize, HasAnyUndefs); 2522 if (IsSplat) { 2523 // Undef bits can contribute to a possible optimisation if set, so 2524 // set them. 2525 SplatValue |= SplatUndef; 2526 2527 // The splat value may be something like "0x00FFFFFF", which means 0 for 2528 // the first vector value and FF for the rest, repeating. We need a mask 2529 // that will apply equally to all members of the vector, so AND all the 2530 // lanes of the constant together. 2531 EVT VT = Vector->getValueType(0); 2532 unsigned BitWidth = VT.getVectorElementType().getSizeInBits(); 2533 2534 // If the splat value has been compressed to a bitlength lower 2535 // than the size of the vector lane, we need to re-expand it to 2536 // the lane size. 2537 if (BitWidth > SplatBitSize) 2538 for (SplatValue = SplatValue.zextOrTrunc(BitWidth); 2539 SplatBitSize < BitWidth; 2540 SplatBitSize = SplatBitSize * 2) 2541 SplatValue |= SplatValue.shl(SplatBitSize); 2542 2543 Constant = APInt::getAllOnesValue(BitWidth); 2544 for (unsigned i = 0, n = SplatBitSize/BitWidth; i < n; ++i) 2545 Constant &= SplatValue.lshr(i*BitWidth).zextOrTrunc(BitWidth); 2546 } 2547 } 2548 2549 // If we want to change an EXTLOAD to a ZEXTLOAD, ensure a ZEXTLOAD is 2550 // actually legal and isn't going to get expanded, else this is a false 2551 // optimisation. 2552 bool CanZextLoadProfitably = TLI.isLoadExtLegal(ISD::ZEXTLOAD, 2553 Load->getMemoryVT()); 2554 2555 // Resize the constant to the same size as the original memory access before 2556 // extension. If it is still the AllOnesValue then this AND is completely 2557 // unneeded. 2558 Constant = 2559 Constant.zextOrTrunc(Load->getMemoryVT().getScalarType().getSizeInBits()); 2560 2561 bool B; 2562 switch (Load->getExtensionType()) { 2563 default: B = false; break; 2564 case ISD::EXTLOAD: B = CanZextLoadProfitably; break; 2565 case ISD::ZEXTLOAD: 2566 case ISD::NON_EXTLOAD: B = true; break; 2567 } 2568 2569 if (B && Constant.isAllOnesValue()) { 2570 // If the load type was an EXTLOAD, convert to ZEXTLOAD in order to 2571 // preserve semantics once we get rid of the AND. 2572 SDValue NewLoad(Load, 0); 2573 if (Load->getExtensionType() == ISD::EXTLOAD) { 2574 NewLoad = DAG.getLoad(Load->getAddressingMode(), ISD::ZEXTLOAD, 2575 Load->getValueType(0), Load->getDebugLoc(), 2576 Load->getChain(), Load->getBasePtr(), 2577 Load->getOffset(), Load->getMemoryVT(), 2578 Load->getMemOperand()); 2579 // Replace uses of the EXTLOAD with the new ZEXTLOAD. 2580 if (Load->getNumValues() == 3) { 2581 // PRE/POST_INC loads have 3 values. 2582 SDValue To[] = { NewLoad.getValue(0), NewLoad.getValue(1), 2583 NewLoad.getValue(2) }; 2584 CombineTo(Load, To, 3, true); 2585 } else { 2586 CombineTo(Load, NewLoad.getValue(0), NewLoad.getValue(1)); 2587 } 2588 } 2589 2590 // Fold the AND away, taking care not to fold to the old load node if we 2591 // replaced it. 2592 CombineTo(N, (N0.getNode() == Load) ? NewLoad : N0); 2593 2594 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2595 } 2596 } 2597 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y)) 2598 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 2599 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 2600 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 2601 2602 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 2603 LL.getValueType().isInteger()) { 2604 // fold (and (seteq X, 0), (seteq Y, 0)) -> (seteq (or X, Y), 0) 2605 if (cast<ConstantSDNode>(LR)->isNullValue() && Op1 == ISD::SETEQ) { 2606 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(), 2607 LR.getValueType(), LL, RL); 2608 AddToWorkList(ORNode.getNode()); 2609 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 2610 } 2611 // fold (and (seteq X, -1), (seteq Y, -1)) -> (seteq (and X, Y), -1) 2612 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) { 2613 SDValue ANDNode = DAG.getNode(ISD::AND, N0.getDebugLoc(), 2614 LR.getValueType(), LL, RL); 2615 AddToWorkList(ANDNode.getNode()); 2616 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1); 2617 } 2618 // fold (and (setgt X, -1), (setgt Y, -1)) -> (setgt (or X, Y), -1) 2619 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) { 2620 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(), 2621 LR.getValueType(), LL, RL); 2622 AddToWorkList(ORNode.getNode()); 2623 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 2624 } 2625 } 2626 // canonicalize equivalent to ll == rl 2627 if (LL == RR && LR == RL) { 2628 Op1 = ISD::getSetCCSwappedOperands(Op1); 2629 std::swap(RL, RR); 2630 } 2631 if (LL == RL && LR == RR) { 2632 bool isInteger = LL.getValueType().isInteger(); 2633 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger); 2634 if (Result != ISD::SETCC_INVALID && 2635 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType()))) 2636 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(), 2637 LL, LR, Result); 2638 } 2639 } 2640 2641 // Simplify: (and (op x...), (op y...)) -> (op (and x, y)) 2642 if (N0.getOpcode() == N1.getOpcode()) { 2643 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 2644 if (Tmp.getNode()) return Tmp; 2645 } 2646 2647 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1) 2648 // fold (and (sra)) -> (and (srl)) when possible. 2649 if (!VT.isVector() && 2650 SimplifyDemandedBits(SDValue(N, 0))) 2651 return SDValue(N, 0); 2652 2653 // fold (zext_inreg (extload x)) -> (zextload x) 2654 if (ISD::isEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode())) { 2655 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2656 EVT MemVT = LN0->getMemoryVT(); 2657 // If we zero all the possible extended bits, then we can turn this into 2658 // a zextload if we are running before legalize or the operation is legal. 2659 unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits(); 2660 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 2661 BitWidth - MemVT.getScalarType().getSizeInBits())) && 2662 ((!LegalOperations && !LN0->isVolatile()) || 2663 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) { 2664 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT, 2665 LN0->getChain(), LN0->getBasePtr(), 2666 LN0->getPointerInfo(), MemVT, 2667 LN0->isVolatile(), LN0->isNonTemporal(), 2668 LN0->getAlignment()); 2669 AddToWorkList(N); 2670 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 2671 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2672 } 2673 } 2674 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use 2675 if (ISD::isSEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 2676 N0.hasOneUse()) { 2677 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2678 EVT MemVT = LN0->getMemoryVT(); 2679 // If we zero all the possible extended bits, then we can turn this into 2680 // a zextload if we are running before legalize or the operation is legal. 2681 unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits(); 2682 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 2683 BitWidth - MemVT.getScalarType().getSizeInBits())) && 2684 ((!LegalOperations && !LN0->isVolatile()) || 2685 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) { 2686 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT, 2687 LN0->getChain(), 2688 LN0->getBasePtr(), LN0->getPointerInfo(), 2689 MemVT, 2690 LN0->isVolatile(), LN0->isNonTemporal(), 2691 LN0->getAlignment()); 2692 AddToWorkList(N); 2693 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 2694 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2695 } 2696 } 2697 2698 // fold (and (load x), 255) -> (zextload x, i8) 2699 // fold (and (extload x, i16), 255) -> (zextload x, i8) 2700 // fold (and (any_ext (extload x, i16)), 255) -> (zextload x, i8) 2701 if (N1C && (N0.getOpcode() == ISD::LOAD || 2702 (N0.getOpcode() == ISD::ANY_EXTEND && 2703 N0.getOperand(0).getOpcode() == ISD::LOAD))) { 2704 bool HasAnyExt = N0.getOpcode() == ISD::ANY_EXTEND; 2705 LoadSDNode *LN0 = HasAnyExt 2706 ? cast<LoadSDNode>(N0.getOperand(0)) 2707 : cast<LoadSDNode>(N0); 2708 if (LN0->getExtensionType() != ISD::SEXTLOAD && 2709 LN0->isUnindexed() && N0.hasOneUse() && LN0->hasOneUse()) { 2710 uint32_t ActiveBits = N1C->getAPIntValue().getActiveBits(); 2711 if (ActiveBits > 0 && APIntOps::isMask(ActiveBits, N1C->getAPIntValue())){ 2712 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), ActiveBits); 2713 EVT LoadedVT = LN0->getMemoryVT(); 2714 2715 if (ExtVT == LoadedVT && 2716 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) { 2717 EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT; 2718 2719 SDValue NewLoad = 2720 DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), LoadResultTy, 2721 LN0->getChain(), LN0->getBasePtr(), 2722 LN0->getPointerInfo(), 2723 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(), 2724 LN0->getAlignment()); 2725 AddToWorkList(N); 2726 CombineTo(LN0, NewLoad, NewLoad.getValue(1)); 2727 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2728 } 2729 2730 // Do not change the width of a volatile load. 2731 // Do not generate loads of non-round integer types since these can 2732 // be expensive (and would be wrong if the type is not byte sized). 2733 if (!LN0->isVolatile() && LoadedVT.bitsGT(ExtVT) && ExtVT.isRound() && 2734 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) { 2735 EVT PtrType = LN0->getOperand(1).getValueType(); 2736 2737 unsigned Alignment = LN0->getAlignment(); 2738 SDValue NewPtr = LN0->getBasePtr(); 2739 2740 // For big endian targets, we need to add an offset to the pointer 2741 // to load the correct bytes. For little endian systems, we merely 2742 // need to read fewer bytes from the same pointer. 2743 if (TLI.isBigEndian()) { 2744 unsigned LVTStoreBytes = LoadedVT.getStoreSize(); 2745 unsigned EVTStoreBytes = ExtVT.getStoreSize(); 2746 unsigned PtrOff = LVTStoreBytes - EVTStoreBytes; 2747 NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(), PtrType, 2748 NewPtr, DAG.getConstant(PtrOff, PtrType)); 2749 Alignment = MinAlign(Alignment, PtrOff); 2750 } 2751 2752 AddToWorkList(NewPtr.getNode()); 2753 2754 EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT; 2755 SDValue Load = 2756 DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), LoadResultTy, 2757 LN0->getChain(), NewPtr, 2758 LN0->getPointerInfo(), 2759 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(), 2760 Alignment); 2761 AddToWorkList(N); 2762 CombineTo(LN0, Load, Load.getValue(1)); 2763 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2764 } 2765 } 2766 } 2767 } 2768 2769 if (N0.getOpcode() == ISD::ADD && N1.getOpcode() == ISD::SRL && 2770 VT.getSizeInBits() <= 64) { 2771 if (ConstantSDNode *ADDI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 2772 APInt ADDC = ADDI->getAPIntValue(); 2773 if (!TLI.isLegalAddImmediate(ADDC.getSExtValue())) { 2774 // Look for (and (add x, c1), (lshr y, c2)). If C1 wasn't a legal 2775 // immediate for an add, but it is legal if its top c2 bits are set, 2776 // transform the ADD so the immediate doesn't need to be materialized 2777 // in a register. 2778 if (ConstantSDNode *SRLI = dyn_cast<ConstantSDNode>(N1.getOperand(1))) { 2779 APInt Mask = APInt::getHighBitsSet(VT.getSizeInBits(), 2780 SRLI->getZExtValue()); 2781 if (DAG.MaskedValueIsZero(N0.getOperand(1), Mask)) { 2782 ADDC |= Mask; 2783 if (TLI.isLegalAddImmediate(ADDC.getSExtValue())) { 2784 SDValue NewAdd = 2785 DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, 2786 N0.getOperand(0), DAG.getConstant(ADDC, VT)); 2787 CombineTo(N0.getNode(), NewAdd); 2788 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2789 } 2790 } 2791 } 2792 } 2793 } 2794 } 2795 2796 return SDValue(); 2797} 2798 2799/// MatchBSwapHWord - Match (a >> 8) | (a << 8) as (bswap a) >> 16 2800/// 2801SDValue DAGCombiner::MatchBSwapHWordLow(SDNode *N, SDValue N0, SDValue N1, 2802 bool DemandHighBits) { 2803 if (!LegalOperations) 2804 return SDValue(); 2805 2806 EVT VT = N->getValueType(0); 2807 if (VT != MVT::i64 && VT != MVT::i32 && VT != MVT::i16) 2808 return SDValue(); 2809 if (!TLI.isOperationLegal(ISD::BSWAP, VT)) 2810 return SDValue(); 2811 2812 // Recognize (and (shl a, 8), 0xff), (and (srl a, 8), 0xff00) 2813 bool LookPassAnd0 = false; 2814 bool LookPassAnd1 = false; 2815 if (N0.getOpcode() == ISD::AND && N0.getOperand(0).getOpcode() == ISD::SRL) 2816 std::swap(N0, N1); 2817 if (N1.getOpcode() == ISD::AND && N1.getOperand(0).getOpcode() == ISD::SHL) 2818 std::swap(N0, N1); 2819 if (N0.getOpcode() == ISD::AND) { 2820 if (!N0.getNode()->hasOneUse()) 2821 return SDValue(); 2822 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2823 if (!N01C || N01C->getZExtValue() != 0xFF00) 2824 return SDValue(); 2825 N0 = N0.getOperand(0); 2826 LookPassAnd0 = true; 2827 } 2828 2829 if (N1.getOpcode() == ISD::AND) { 2830 if (!N1.getNode()->hasOneUse()) 2831 return SDValue(); 2832 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1)); 2833 if (!N11C || N11C->getZExtValue() != 0xFF) 2834 return SDValue(); 2835 N1 = N1.getOperand(0); 2836 LookPassAnd1 = true; 2837 } 2838 2839 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL) 2840 std::swap(N0, N1); 2841 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL) 2842 return SDValue(); 2843 if (!N0.getNode()->hasOneUse() || 2844 !N1.getNode()->hasOneUse()) 2845 return SDValue(); 2846 2847 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2848 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1)); 2849 if (!N01C || !N11C) 2850 return SDValue(); 2851 if (N01C->getZExtValue() != 8 || N11C->getZExtValue() != 8) 2852 return SDValue(); 2853 2854 // Look for (shl (and a, 0xff), 8), (srl (and a, 0xff00), 8) 2855 SDValue N00 = N0->getOperand(0); 2856 if (!LookPassAnd0 && N00.getOpcode() == ISD::AND) { 2857 if (!N00.getNode()->hasOneUse()) 2858 return SDValue(); 2859 ConstantSDNode *N001C = dyn_cast<ConstantSDNode>(N00.getOperand(1)); 2860 if (!N001C || N001C->getZExtValue() != 0xFF) 2861 return SDValue(); 2862 N00 = N00.getOperand(0); 2863 LookPassAnd0 = true; 2864 } 2865 2866 SDValue N10 = N1->getOperand(0); 2867 if (!LookPassAnd1 && N10.getOpcode() == ISD::AND) { 2868 if (!N10.getNode()->hasOneUse()) 2869 return SDValue(); 2870 ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N10.getOperand(1)); 2871 if (!N101C || N101C->getZExtValue() != 0xFF00) 2872 return SDValue(); 2873 N10 = N10.getOperand(0); 2874 LookPassAnd1 = true; 2875 } 2876 2877 if (N00 != N10) 2878 return SDValue(); 2879 2880 // Make sure everything beyond the low halfword is zero since the SRL 16 2881 // will clear the top bits. 2882 unsigned OpSizeInBits = VT.getSizeInBits(); 2883 if (DemandHighBits && OpSizeInBits > 16 && 2884 (!LookPassAnd0 || !LookPassAnd1) && 2885 !DAG.MaskedValueIsZero(N10, APInt::getHighBitsSet(OpSizeInBits, 16))) 2886 return SDValue(); 2887 2888 SDValue Res = DAG.getNode(ISD::BSWAP, N->getDebugLoc(), VT, N00); 2889 if (OpSizeInBits > 16) 2890 Res = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, Res, 2891 DAG.getConstant(OpSizeInBits-16, getShiftAmountTy(VT))); 2892 return Res; 2893} 2894 2895/// isBSwapHWordElement - Return true if the specified node is an element 2896/// that makes up a 32-bit packed halfword byteswap. i.e. 2897/// ((x&0xff)<<8)|((x&0xff00)>>8)|((x&0x00ff0000)<<8)|((x&0xff000000)>>8) 2898static bool isBSwapHWordElement(SDValue N, SmallVector<SDNode*,4> &Parts) { 2899 if (!N.getNode()->hasOneUse()) 2900 return false; 2901 2902 unsigned Opc = N.getOpcode(); 2903 if (Opc != ISD::AND && Opc != ISD::SHL && Opc != ISD::SRL) 2904 return false; 2905 2906 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N.getOperand(1)); 2907 if (!N1C) 2908 return false; 2909 2910 unsigned Num; 2911 switch (N1C->getZExtValue()) { 2912 default: 2913 return false; 2914 case 0xFF: Num = 0; break; 2915 case 0xFF00: Num = 1; break; 2916 case 0xFF0000: Num = 2; break; 2917 case 0xFF000000: Num = 3; break; 2918 } 2919 2920 // Look for (x & 0xff) << 8 as well as ((x << 8) & 0xff00). 2921 SDValue N0 = N.getOperand(0); 2922 if (Opc == ISD::AND) { 2923 if (Num == 0 || Num == 2) { 2924 // (x >> 8) & 0xff 2925 // (x >> 8) & 0xff0000 2926 if (N0.getOpcode() != ISD::SRL) 2927 return false; 2928 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2929 if (!C || C->getZExtValue() != 8) 2930 return false; 2931 } else { 2932 // (x << 8) & 0xff00 2933 // (x << 8) & 0xff000000 2934 if (N0.getOpcode() != ISD::SHL) 2935 return false; 2936 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2937 if (!C || C->getZExtValue() != 8) 2938 return false; 2939 } 2940 } else if (Opc == ISD::SHL) { 2941 // (x & 0xff) << 8 2942 // (x & 0xff0000) << 8 2943 if (Num != 0 && Num != 2) 2944 return false; 2945 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N.getOperand(1)); 2946 if (!C || C->getZExtValue() != 8) 2947 return false; 2948 } else { // Opc == ISD::SRL 2949 // (x & 0xff00) >> 8 2950 // (x & 0xff000000) >> 8 2951 if (Num != 1 && Num != 3) 2952 return false; 2953 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N.getOperand(1)); 2954 if (!C || C->getZExtValue() != 8) 2955 return false; 2956 } 2957 2958 if (Parts[Num]) 2959 return false; 2960 2961 Parts[Num] = N0.getOperand(0).getNode(); 2962 return true; 2963} 2964 2965/// MatchBSwapHWord - Match a 32-bit packed halfword bswap. That is 2966/// ((x&0xff)<<8)|((x&0xff00)>>8)|((x&0x00ff0000)<<8)|((x&0xff000000)>>8) 2967/// => (rotl (bswap x), 16) 2968SDValue DAGCombiner::MatchBSwapHWord(SDNode *N, SDValue N0, SDValue N1) { 2969 if (!LegalOperations) 2970 return SDValue(); 2971 2972 EVT VT = N->getValueType(0); 2973 if (VT != MVT::i32) 2974 return SDValue(); 2975 if (!TLI.isOperationLegal(ISD::BSWAP, VT)) 2976 return SDValue(); 2977 2978 SmallVector<SDNode*,4> Parts(4, (SDNode*)0); 2979 // Look for either 2980 // (or (or (and), (and)), (or (and), (and))) 2981 // (or (or (or (and), (and)), (and)), (and)) 2982 if (N0.getOpcode() != ISD::OR) 2983 return SDValue(); 2984 SDValue N00 = N0.getOperand(0); 2985 SDValue N01 = N0.getOperand(1); 2986 2987 if (N1.getOpcode() == ISD::OR && 2988 N00.getNumOperands() == 2 && N01.getNumOperands() == 2) { 2989 // (or (or (and), (and)), (or (and), (and))) 2990 SDValue N000 = N00.getOperand(0); 2991 if (!isBSwapHWordElement(N000, Parts)) 2992 return SDValue(); 2993 2994 SDValue N001 = N00.getOperand(1); 2995 if (!isBSwapHWordElement(N001, Parts)) 2996 return SDValue(); 2997 SDValue N010 = N01.getOperand(0); 2998 if (!isBSwapHWordElement(N010, Parts)) 2999 return SDValue(); 3000 SDValue N011 = N01.getOperand(1); 3001 if (!isBSwapHWordElement(N011, Parts)) 3002 return SDValue(); 3003 } else { 3004 // (or (or (or (and), (and)), (and)), (and)) 3005 if (!isBSwapHWordElement(N1, Parts)) 3006 return SDValue(); 3007 if (!isBSwapHWordElement(N01, Parts)) 3008 return SDValue(); 3009 if (N00.getOpcode() != ISD::OR) 3010 return SDValue(); 3011 SDValue N000 = N00.getOperand(0); 3012 if (!isBSwapHWordElement(N000, Parts)) 3013 return SDValue(); 3014 SDValue N001 = N00.getOperand(1); 3015 if (!isBSwapHWordElement(N001, Parts)) 3016 return SDValue(); 3017 } 3018 3019 // Make sure the parts are all coming from the same node. 3020 if (Parts[0] != Parts[1] || Parts[0] != Parts[2] || Parts[0] != Parts[3]) 3021 return SDValue(); 3022 3023 SDValue BSwap = DAG.getNode(ISD::BSWAP, N->getDebugLoc(), VT, 3024 SDValue(Parts[0],0)); 3025 3026 // Result of the bswap should be rotated by 16. If it's not legal, than 3027 // do (x << 16) | (x >> 16). 3028 SDValue ShAmt = DAG.getConstant(16, getShiftAmountTy(VT)); 3029 if (TLI.isOperationLegalOrCustom(ISD::ROTL, VT)) 3030 return DAG.getNode(ISD::ROTL, N->getDebugLoc(), VT, BSwap, ShAmt); 3031 if (TLI.isOperationLegalOrCustom(ISD::ROTR, VT)) 3032 return DAG.getNode(ISD::ROTR, N->getDebugLoc(), VT, BSwap, ShAmt); 3033 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, 3034 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, BSwap, ShAmt), 3035 DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, BSwap, ShAmt)); 3036} 3037 3038SDValue DAGCombiner::visitOR(SDNode *N) { 3039 SDValue N0 = N->getOperand(0); 3040 SDValue N1 = N->getOperand(1); 3041 SDValue LL, LR, RL, RR, CC0, CC1; 3042 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3043 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3044 EVT VT = N1.getValueType(); 3045 3046 // fold vector ops 3047 if (VT.isVector()) { 3048 SDValue FoldedVOp = SimplifyVBinOp(N); 3049 if (FoldedVOp.getNode()) return FoldedVOp; 3050 3051 // fold (or x, 0) -> x, vector edition 3052 if (ISD::isBuildVectorAllZeros(N0.getNode())) 3053 return N1; 3054 if (ISD::isBuildVectorAllZeros(N1.getNode())) 3055 return N0; 3056 3057 // fold (or x, -1) -> -1, vector edition 3058 if (ISD::isBuildVectorAllOnes(N0.getNode())) 3059 return N0; 3060 if (ISD::isBuildVectorAllOnes(N1.getNode())) 3061 return N1; 3062 } 3063 3064 // fold (or x, undef) -> -1 3065 if (!LegalOperations && 3066 (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)) { 3067 EVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT; 3068 return DAG.getConstant(APInt::getAllOnesValue(EltVT.getSizeInBits()), VT); 3069 } 3070 // fold (or c1, c2) -> c1|c2 3071 if (N0C && N1C) 3072 return DAG.FoldConstantArithmetic(ISD::OR, VT, N0C, N1C); 3073 // canonicalize constant to RHS 3074 if (N0C && !N1C) 3075 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N1, N0); 3076 // fold (or x, 0) -> x 3077 if (N1C && N1C->isNullValue()) 3078 return N0; 3079 // fold (or x, -1) -> -1 3080 if (N1C && N1C->isAllOnesValue()) 3081 return N1; 3082 // fold (or x, c) -> c iff (x & ~c) == 0 3083 if (N1C && DAG.MaskedValueIsZero(N0, ~N1C->getAPIntValue())) 3084 return N1; 3085 3086 // Recognize halfword bswaps as (bswap + rotl 16) or (bswap + shl 16) 3087 SDValue BSwap = MatchBSwapHWord(N, N0, N1); 3088 if (BSwap.getNode() != 0) 3089 return BSwap; 3090 BSwap = MatchBSwapHWordLow(N, N0, N1); 3091 if (BSwap.getNode() != 0) 3092 return BSwap; 3093 3094 // reassociate or 3095 SDValue ROR = ReassociateOps(ISD::OR, N->getDebugLoc(), N0, N1); 3096 if (ROR.getNode() != 0) 3097 return ROR; 3098 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2) 3099 // iff (c1 & c2) == 0. 3100 if (N1C && N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() && 3101 isa<ConstantSDNode>(N0.getOperand(1))) { 3102 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1)); 3103 if ((C1->getAPIntValue() & N1C->getAPIntValue()) != 0) 3104 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 3105 DAG.getNode(ISD::OR, N0.getDebugLoc(), VT, 3106 N0.getOperand(0), N1), 3107 DAG.FoldConstantArithmetic(ISD::OR, VT, N1C, C1)); 3108 } 3109 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y)) 3110 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 3111 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 3112 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 3113 3114 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 3115 LL.getValueType().isInteger()) { 3116 // fold (or (setne X, 0), (setne Y, 0)) -> (setne (or X, Y), 0) 3117 // fold (or (setlt X, 0), (setlt Y, 0)) -> (setne (or X, Y), 0) 3118 if (cast<ConstantSDNode>(LR)->isNullValue() && 3119 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) { 3120 SDValue ORNode = DAG.getNode(ISD::OR, LR.getDebugLoc(), 3121 LR.getValueType(), LL, RL); 3122 AddToWorkList(ORNode.getNode()); 3123 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 3124 } 3125 // fold (or (setne X, -1), (setne Y, -1)) -> (setne (and X, Y), -1) 3126 // fold (or (setgt X, -1), (setgt Y -1)) -> (setgt (and X, Y), -1) 3127 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && 3128 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) { 3129 SDValue ANDNode = DAG.getNode(ISD::AND, LR.getDebugLoc(), 3130 LR.getValueType(), LL, RL); 3131 AddToWorkList(ANDNode.getNode()); 3132 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1); 3133 } 3134 } 3135 // canonicalize equivalent to ll == rl 3136 if (LL == RR && LR == RL) { 3137 Op1 = ISD::getSetCCSwappedOperands(Op1); 3138 std::swap(RL, RR); 3139 } 3140 if (LL == RL && LR == RR) { 3141 bool isInteger = LL.getValueType().isInteger(); 3142 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger); 3143 if (Result != ISD::SETCC_INVALID && 3144 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType()))) 3145 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(), 3146 LL, LR, Result); 3147 } 3148 } 3149 3150 // Simplify: (or (op x...), (op y...)) -> (op (or x, y)) 3151 if (N0.getOpcode() == N1.getOpcode()) { 3152 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 3153 if (Tmp.getNode()) return Tmp; 3154 } 3155 3156 // (or (and X, C1), (and Y, C2)) -> (and (or X, Y), C3) if possible. 3157 if (N0.getOpcode() == ISD::AND && 3158 N1.getOpcode() == ISD::AND && 3159 N0.getOperand(1).getOpcode() == ISD::Constant && 3160 N1.getOperand(1).getOpcode() == ISD::Constant && 3161 // Don't increase # computations. 3162 (N0.getNode()->hasOneUse() || N1.getNode()->hasOneUse())) { 3163 // We can only do this xform if we know that bits from X that are set in C2 3164 // but not in C1 are already zero. Likewise for Y. 3165 const APInt &LHSMask = 3166 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 3167 const APInt &RHSMask = 3168 cast<ConstantSDNode>(N1.getOperand(1))->getAPIntValue(); 3169 3170 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) && 3171 DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) { 3172 SDValue X = DAG.getNode(ISD::OR, N0.getDebugLoc(), VT, 3173 N0.getOperand(0), N1.getOperand(0)); 3174 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, X, 3175 DAG.getConstant(LHSMask | RHSMask, VT)); 3176 } 3177 } 3178 3179 // See if this is some rotate idiom. 3180 if (SDNode *Rot = MatchRotate(N0, N1, N->getDebugLoc())) 3181 return SDValue(Rot, 0); 3182 3183 // Simplify the operands using demanded-bits information. 3184 if (!VT.isVector() && 3185 SimplifyDemandedBits(SDValue(N, 0))) 3186 return SDValue(N, 0); 3187 3188 return SDValue(); 3189} 3190 3191/// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present. 3192static bool MatchRotateHalf(SDValue Op, SDValue &Shift, SDValue &Mask) { 3193 if (Op.getOpcode() == ISD::AND) { 3194 if (isa<ConstantSDNode>(Op.getOperand(1))) { 3195 Mask = Op.getOperand(1); 3196 Op = Op.getOperand(0); 3197 } else { 3198 return false; 3199 } 3200 } 3201 3202 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) { 3203 Shift = Op; 3204 return true; 3205 } 3206 3207 return false; 3208} 3209 3210// MatchRotate - Handle an 'or' of two operands. If this is one of the many 3211// idioms for rotate, and if the target supports rotation instructions, generate 3212// a rot[lr]. 3213SDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL) { 3214 // Must be a legal type. Expanded 'n promoted things won't work with rotates. 3215 EVT VT = LHS.getValueType(); 3216 if (!TLI.isTypeLegal(VT)) return 0; 3217 3218 // The target must have at least one rotate flavor. 3219 bool HasROTL = TLI.isOperationLegalOrCustom(ISD::ROTL, VT); 3220 bool HasROTR = TLI.isOperationLegalOrCustom(ISD::ROTR, VT); 3221 if (!HasROTL && !HasROTR) return 0; 3222 3223 // Match "(X shl/srl V1) & V2" where V2 may not be present. 3224 SDValue LHSShift; // The shift. 3225 SDValue LHSMask; // AND value if any. 3226 if (!MatchRotateHalf(LHS, LHSShift, LHSMask)) 3227 return 0; // Not part of a rotate. 3228 3229 SDValue RHSShift; // The shift. 3230 SDValue RHSMask; // AND value if any. 3231 if (!MatchRotateHalf(RHS, RHSShift, RHSMask)) 3232 return 0; // Not part of a rotate. 3233 3234 if (LHSShift.getOperand(0) != RHSShift.getOperand(0)) 3235 return 0; // Not shifting the same value. 3236 3237 if (LHSShift.getOpcode() == RHSShift.getOpcode()) 3238 return 0; // Shifts must disagree. 3239 3240 // Canonicalize shl to left side in a shl/srl pair. 3241 if (RHSShift.getOpcode() == ISD::SHL) { 3242 std::swap(LHS, RHS); 3243 std::swap(LHSShift, RHSShift); 3244 std::swap(LHSMask , RHSMask ); 3245 } 3246 3247 unsigned OpSizeInBits = VT.getSizeInBits(); 3248 SDValue LHSShiftArg = LHSShift.getOperand(0); 3249 SDValue LHSShiftAmt = LHSShift.getOperand(1); 3250 SDValue RHSShiftAmt = RHSShift.getOperand(1); 3251 3252 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1) 3253 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2) 3254 if (LHSShiftAmt.getOpcode() == ISD::Constant && 3255 RHSShiftAmt.getOpcode() == ISD::Constant) { 3256 uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getZExtValue(); 3257 uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getZExtValue(); 3258 if ((LShVal + RShVal) != OpSizeInBits) 3259 return 0; 3260 3261 SDValue Rot = DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT, 3262 LHSShiftArg, HasROTL ? LHSShiftAmt : RHSShiftAmt); 3263 3264 // If there is an AND of either shifted operand, apply it to the result. 3265 if (LHSMask.getNode() || RHSMask.getNode()) { 3266 APInt Mask = APInt::getAllOnesValue(OpSizeInBits); 3267 3268 if (LHSMask.getNode()) { 3269 APInt RHSBits = APInt::getLowBitsSet(OpSizeInBits, LShVal); 3270 Mask &= cast<ConstantSDNode>(LHSMask)->getAPIntValue() | RHSBits; 3271 } 3272 if (RHSMask.getNode()) { 3273 APInt LHSBits = APInt::getHighBitsSet(OpSizeInBits, RShVal); 3274 Mask &= cast<ConstantSDNode>(RHSMask)->getAPIntValue() | LHSBits; 3275 } 3276 3277 Rot = DAG.getNode(ISD::AND, DL, VT, Rot, DAG.getConstant(Mask, VT)); 3278 } 3279 3280 return Rot.getNode(); 3281 } 3282 3283 // If there is a mask here, and we have a variable shift, we can't be sure 3284 // that we're masking out the right stuff. 3285 if (LHSMask.getNode() || RHSMask.getNode()) 3286 return 0; 3287 3288 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y) 3289 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y)) 3290 if (RHSShiftAmt.getOpcode() == ISD::SUB && 3291 LHSShiftAmt == RHSShiftAmt.getOperand(1)) { 3292 if (ConstantSDNode *SUBC = 3293 dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) { 3294 if (SUBC->getAPIntValue() == OpSizeInBits) { 3295 return DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT, LHSShiftArg, 3296 HasROTL ? LHSShiftAmt : RHSShiftAmt).getNode(); 3297 } 3298 } 3299 } 3300 3301 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y) 3302 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y)) 3303 if (LHSShiftAmt.getOpcode() == ISD::SUB && 3304 RHSShiftAmt == LHSShiftAmt.getOperand(1)) { 3305 if (ConstantSDNode *SUBC = 3306 dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) { 3307 if (SUBC->getAPIntValue() == OpSizeInBits) { 3308 return DAG.getNode(HasROTR ? ISD::ROTR : ISD::ROTL, DL, VT, LHSShiftArg, 3309 HasROTR ? RHSShiftAmt : LHSShiftAmt).getNode(); 3310 } 3311 } 3312 } 3313 3314 // Look for sign/zext/any-extended or truncate cases: 3315 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND || 3316 LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND || 3317 LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND || 3318 LHSShiftAmt.getOpcode() == ISD::TRUNCATE) && 3319 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND || 3320 RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND || 3321 RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND || 3322 RHSShiftAmt.getOpcode() == ISD::TRUNCATE)) { 3323 SDValue LExtOp0 = LHSShiftAmt.getOperand(0); 3324 SDValue RExtOp0 = RHSShiftAmt.getOperand(0); 3325 if (RExtOp0.getOpcode() == ISD::SUB && 3326 RExtOp0.getOperand(1) == LExtOp0) { 3327 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 3328 // (rotl x, y) 3329 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 3330 // (rotr x, (sub 32, y)) 3331 if (ConstantSDNode *SUBC = 3332 dyn_cast<ConstantSDNode>(RExtOp0.getOperand(0))) { 3333 if (SUBC->getAPIntValue() == OpSizeInBits) { 3334 return DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT, 3335 LHSShiftArg, 3336 HasROTL ? LHSShiftAmt : RHSShiftAmt).getNode(); 3337 } 3338 } 3339 } else if (LExtOp0.getOpcode() == ISD::SUB && 3340 RExtOp0 == LExtOp0.getOperand(1)) { 3341 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) -> 3342 // (rotr x, y) 3343 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) -> 3344 // (rotl x, (sub 32, y)) 3345 if (ConstantSDNode *SUBC = 3346 dyn_cast<ConstantSDNode>(LExtOp0.getOperand(0))) { 3347 if (SUBC->getAPIntValue() == OpSizeInBits) { 3348 return DAG.getNode(HasROTR ? ISD::ROTR : ISD::ROTL, DL, VT, 3349 LHSShiftArg, 3350 HasROTR ? RHSShiftAmt : LHSShiftAmt).getNode(); 3351 } 3352 } 3353 } 3354 } 3355 3356 return 0; 3357} 3358 3359SDValue DAGCombiner::visitXOR(SDNode *N) { 3360 SDValue N0 = N->getOperand(0); 3361 SDValue N1 = N->getOperand(1); 3362 SDValue LHS, RHS, CC; 3363 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3364 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3365 EVT VT = N0.getValueType(); 3366 3367 // fold vector ops 3368 if (VT.isVector()) { 3369 SDValue FoldedVOp = SimplifyVBinOp(N); 3370 if (FoldedVOp.getNode()) return FoldedVOp; 3371 3372 // fold (xor x, 0) -> x, vector edition 3373 if (ISD::isBuildVectorAllZeros(N0.getNode())) 3374 return N1; 3375 if (ISD::isBuildVectorAllZeros(N1.getNode())) 3376 return N0; 3377 } 3378 3379 // fold (xor undef, undef) -> 0. This is a common idiom (misuse). 3380 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF) 3381 return DAG.getConstant(0, VT); 3382 // fold (xor x, undef) -> undef 3383 if (N0.getOpcode() == ISD::UNDEF) 3384 return N0; 3385 if (N1.getOpcode() == ISD::UNDEF) 3386 return N1; 3387 // fold (xor c1, c2) -> c1^c2 3388 if (N0C && N1C) 3389 return DAG.FoldConstantArithmetic(ISD::XOR, VT, N0C, N1C); 3390 // canonicalize constant to RHS 3391 if (N0C && !N1C) 3392 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0); 3393 // fold (xor x, 0) -> x 3394 if (N1C && N1C->isNullValue()) 3395 return N0; 3396 // reassociate xor 3397 SDValue RXOR = ReassociateOps(ISD::XOR, N->getDebugLoc(), N0, N1); 3398 if (RXOR.getNode() != 0) 3399 return RXOR; 3400 3401 // fold !(x cc y) -> (x !cc y) 3402 if (N1C && N1C->getAPIntValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) { 3403 bool isInt = LHS.getValueType().isInteger(); 3404 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(), 3405 isInt); 3406 3407 if (!LegalOperations || TLI.isCondCodeLegal(NotCC, LHS.getValueType())) { 3408 switch (N0.getOpcode()) { 3409 default: 3410 llvm_unreachable("Unhandled SetCC Equivalent!"); 3411 case ISD::SETCC: 3412 return DAG.getSetCC(N->getDebugLoc(), VT, LHS, RHS, NotCC); 3413 case ISD::SELECT_CC: 3414 return DAG.getSelectCC(N->getDebugLoc(), LHS, RHS, N0.getOperand(2), 3415 N0.getOperand(3), NotCC); 3416 } 3417 } 3418 } 3419 3420 // fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y))) 3421 if (N1C && N1C->getAPIntValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND && 3422 N0.getNode()->hasOneUse() && 3423 isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){ 3424 SDValue V = N0.getOperand(0); 3425 V = DAG.getNode(ISD::XOR, N0.getDebugLoc(), V.getValueType(), V, 3426 DAG.getConstant(1, V.getValueType())); 3427 AddToWorkList(V.getNode()); 3428 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, V); 3429 } 3430 3431 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are setcc 3432 if (N1C && N1C->getAPIntValue() == 1 && VT == MVT::i1 && 3433 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 3434 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1); 3435 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) { 3436 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 3437 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS 3438 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS 3439 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode()); 3440 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS); 3441 } 3442 } 3443 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are constants 3444 if (N1C && N1C->isAllOnesValue() && 3445 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 3446 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1); 3447 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) { 3448 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 3449 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS 3450 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS 3451 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode()); 3452 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS); 3453 } 3454 } 3455 // fold (xor (xor x, c1), c2) -> (xor x, (xor c1, c2)) 3456 if (N1C && N0.getOpcode() == ISD::XOR) { 3457 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0)); 3458 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 3459 if (N00C) 3460 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(1), 3461 DAG.getConstant(N1C->getAPIntValue() ^ 3462 N00C->getAPIntValue(), VT)); 3463 if (N01C) 3464 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(0), 3465 DAG.getConstant(N1C->getAPIntValue() ^ 3466 N01C->getAPIntValue(), VT)); 3467 } 3468 // fold (xor x, x) -> 0 3469 if (N0 == N1) 3470 return tryFoldToZero(N->getDebugLoc(), TLI, VT, DAG, LegalOperations); 3471 3472 // Simplify: xor (op x...), (op y...) -> (op (xor x, y)) 3473 if (N0.getOpcode() == N1.getOpcode()) { 3474 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 3475 if (Tmp.getNode()) return Tmp; 3476 } 3477 3478 // Simplify the expression using non-local knowledge. 3479 if (!VT.isVector() && 3480 SimplifyDemandedBits(SDValue(N, 0))) 3481 return SDValue(N, 0); 3482 3483 return SDValue(); 3484} 3485 3486/// visitShiftByConstant - Handle transforms common to the three shifts, when 3487/// the shift amount is a constant. 3488SDValue DAGCombiner::visitShiftByConstant(SDNode *N, unsigned Amt) { 3489 SDNode *LHS = N->getOperand(0).getNode(); 3490 if (!LHS->hasOneUse()) return SDValue(); 3491 3492 // We want to pull some binops through shifts, so that we have (and (shift)) 3493 // instead of (shift (and)), likewise for add, or, xor, etc. This sort of 3494 // thing happens with address calculations, so it's important to canonicalize 3495 // it. 3496 bool HighBitSet = false; // Can we transform this if the high bit is set? 3497 3498 switch (LHS->getOpcode()) { 3499 default: return SDValue(); 3500 case ISD::OR: 3501 case ISD::XOR: 3502 HighBitSet = false; // We can only transform sra if the high bit is clear. 3503 break; 3504 case ISD::AND: 3505 HighBitSet = true; // We can only transform sra if the high bit is set. 3506 break; 3507 case ISD::ADD: 3508 if (N->getOpcode() != ISD::SHL) 3509 return SDValue(); // only shl(add) not sr[al](add). 3510 HighBitSet = false; // We can only transform sra if the high bit is clear. 3511 break; 3512 } 3513 3514 // We require the RHS of the binop to be a constant as well. 3515 ConstantSDNode *BinOpCst = dyn_cast<ConstantSDNode>(LHS->getOperand(1)); 3516 if (!BinOpCst) return SDValue(); 3517 3518 // FIXME: disable this unless the input to the binop is a shift by a constant. 3519 // If it is not a shift, it pessimizes some common cases like: 3520 // 3521 // void foo(int *X, int i) { X[i & 1235] = 1; } 3522 // int bar(int *X, int i) { return X[i & 255]; } 3523 SDNode *BinOpLHSVal = LHS->getOperand(0).getNode(); 3524 if ((BinOpLHSVal->getOpcode() != ISD::SHL && 3525 BinOpLHSVal->getOpcode() != ISD::SRA && 3526 BinOpLHSVal->getOpcode() != ISD::SRL) || 3527 !isa<ConstantSDNode>(BinOpLHSVal->getOperand(1))) 3528 return SDValue(); 3529 3530 EVT VT = N->getValueType(0); 3531 3532 // If this is a signed shift right, and the high bit is modified by the 3533 // logical operation, do not perform the transformation. The highBitSet 3534 // boolean indicates the value of the high bit of the constant which would 3535 // cause it to be modified for this operation. 3536 if (N->getOpcode() == ISD::SRA) { 3537 bool BinOpRHSSignSet = BinOpCst->getAPIntValue().isNegative(); 3538 if (BinOpRHSSignSet != HighBitSet) 3539 return SDValue(); 3540 } 3541 3542 // Fold the constants, shifting the binop RHS by the shift amount. 3543 SDValue NewRHS = DAG.getNode(N->getOpcode(), LHS->getOperand(1).getDebugLoc(), 3544 N->getValueType(0), 3545 LHS->getOperand(1), N->getOperand(1)); 3546 3547 // Create the new shift. 3548 SDValue NewShift = DAG.getNode(N->getOpcode(), 3549 LHS->getOperand(0).getDebugLoc(), 3550 VT, LHS->getOperand(0), N->getOperand(1)); 3551 3552 // Create the new binop. 3553 return DAG.getNode(LHS->getOpcode(), N->getDebugLoc(), VT, NewShift, NewRHS); 3554} 3555 3556SDValue DAGCombiner::visitSHL(SDNode *N) { 3557 SDValue N0 = N->getOperand(0); 3558 SDValue N1 = N->getOperand(1); 3559 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3560 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3561 EVT VT = N0.getValueType(); 3562 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits(); 3563 3564 // fold (shl c1, c2) -> c1<<c2 3565 if (N0C && N1C) 3566 return DAG.FoldConstantArithmetic(ISD::SHL, VT, N0C, N1C); 3567 // fold (shl 0, x) -> 0 3568 if (N0C && N0C->isNullValue()) 3569 return N0; 3570 // fold (shl x, c >= size(x)) -> undef 3571 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 3572 return DAG.getUNDEF(VT); 3573 // fold (shl x, 0) -> x 3574 if (N1C && N1C->isNullValue()) 3575 return N0; 3576 // fold (shl undef, x) -> 0 3577 if (N0.getOpcode() == ISD::UNDEF) 3578 return DAG.getConstant(0, VT); 3579 // if (shl x, c) is known to be zero, return 0 3580 if (DAG.MaskedValueIsZero(SDValue(N, 0), 3581 APInt::getAllOnesValue(OpSizeInBits))) 3582 return DAG.getConstant(0, VT); 3583 // fold (shl x, (trunc (and y, c))) -> (shl x, (and (trunc y), (trunc c))). 3584 if (N1.getOpcode() == ISD::TRUNCATE && 3585 N1.getOperand(0).getOpcode() == ISD::AND && 3586 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 3587 SDValue N101 = N1.getOperand(0).getOperand(1); 3588 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 3589 EVT TruncVT = N1.getValueType(); 3590 SDValue N100 = N1.getOperand(0).getOperand(0); 3591 APInt TruncC = N101C->getAPIntValue(); 3592 TruncC = TruncC.trunc(TruncVT.getSizeInBits()); 3593 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 3594 DAG.getNode(ISD::AND, N->getDebugLoc(), TruncVT, 3595 DAG.getNode(ISD::TRUNCATE, 3596 N->getDebugLoc(), 3597 TruncVT, N100), 3598 DAG.getConstant(TruncC, TruncVT))); 3599 } 3600 } 3601 3602 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 3603 return SDValue(N, 0); 3604 3605 // fold (shl (shl x, c1), c2) -> 0 or (shl x, (add c1, c2)) 3606 if (N1C && N0.getOpcode() == ISD::SHL && 3607 N0.getOperand(1).getOpcode() == ISD::Constant) { 3608 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 3609 uint64_t c2 = N1C->getZExtValue(); 3610 if (c1 + c2 >= OpSizeInBits) 3611 return DAG.getConstant(0, VT); 3612 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0.getOperand(0), 3613 DAG.getConstant(c1 + c2, N1.getValueType())); 3614 } 3615 3616 // fold (shl (ext (shl x, c1)), c2) -> (ext (shl x, (add c1, c2))) 3617 // For this to be valid, the second form must not preserve any of the bits 3618 // that are shifted out by the inner shift in the first form. This means 3619 // the outer shift size must be >= the number of bits added by the ext. 3620 // As a corollary, we don't care what kind of ext it is. 3621 if (N1C && (N0.getOpcode() == ISD::ZERO_EXTEND || 3622 N0.getOpcode() == ISD::ANY_EXTEND || 3623 N0.getOpcode() == ISD::SIGN_EXTEND) && 3624 N0.getOperand(0).getOpcode() == ISD::SHL && 3625 isa<ConstantSDNode>(N0.getOperand(0)->getOperand(1))) { 3626 uint64_t c1 = 3627 cast<ConstantSDNode>(N0.getOperand(0)->getOperand(1))->getZExtValue(); 3628 uint64_t c2 = N1C->getZExtValue(); 3629 EVT InnerShiftVT = N0.getOperand(0).getValueType(); 3630 uint64_t InnerShiftSize = InnerShiftVT.getScalarType().getSizeInBits(); 3631 if (c2 >= OpSizeInBits - InnerShiftSize) { 3632 if (c1 + c2 >= OpSizeInBits) 3633 return DAG.getConstant(0, VT); 3634 return DAG.getNode(ISD::SHL, N0->getDebugLoc(), VT, 3635 DAG.getNode(N0.getOpcode(), N0->getDebugLoc(), VT, 3636 N0.getOperand(0)->getOperand(0)), 3637 DAG.getConstant(c1 + c2, N1.getValueType())); 3638 } 3639 } 3640 3641 // fold (shl (srl x, c1), c2) -> (and (shl x, (sub c2, c1), MASK) or 3642 // (and (srl x, (sub c1, c2), MASK) 3643 // Only fold this if the inner shift has no other uses -- if it does, folding 3644 // this will increase the total number of instructions. 3645 if (N1C && N0.getOpcode() == ISD::SRL && N0.hasOneUse() && 3646 N0.getOperand(1).getOpcode() == ISD::Constant) { 3647 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 3648 if (c1 < VT.getSizeInBits()) { 3649 uint64_t c2 = N1C->getZExtValue(); 3650 APInt Mask = APInt::getHighBitsSet(VT.getSizeInBits(), 3651 VT.getSizeInBits() - c1); 3652 SDValue Shift; 3653 if (c2 > c1) { 3654 Mask = Mask.shl(c2-c1); 3655 Shift = DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0.getOperand(0), 3656 DAG.getConstant(c2-c1, N1.getValueType())); 3657 } else { 3658 Mask = Mask.lshr(c1-c2); 3659 Shift = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), 3660 DAG.getConstant(c1-c2, N1.getValueType())); 3661 } 3662 return DAG.getNode(ISD::AND, N0.getDebugLoc(), VT, Shift, 3663 DAG.getConstant(Mask, VT)); 3664 } 3665 } 3666 // fold (shl (sra x, c1), c1) -> (and x, (shl -1, c1)) 3667 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) { 3668 SDValue HiBitsMask = 3669 DAG.getConstant(APInt::getHighBitsSet(VT.getSizeInBits(), 3670 VT.getSizeInBits() - 3671 N1C->getZExtValue()), 3672 VT); 3673 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0), 3674 HiBitsMask); 3675 } 3676 3677 if (N1C) { 3678 SDValue NewSHL = visitShiftByConstant(N, N1C->getZExtValue()); 3679 if (NewSHL.getNode()) 3680 return NewSHL; 3681 } 3682 3683 return SDValue(); 3684} 3685 3686SDValue DAGCombiner::visitSRA(SDNode *N) { 3687 SDValue N0 = N->getOperand(0); 3688 SDValue N1 = N->getOperand(1); 3689 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3690 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3691 EVT VT = N0.getValueType(); 3692 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits(); 3693 3694 // fold (sra c1, c2) -> (sra c1, c2) 3695 if (N0C && N1C) 3696 return DAG.FoldConstantArithmetic(ISD::SRA, VT, N0C, N1C); 3697 // fold (sra 0, x) -> 0 3698 if (N0C && N0C->isNullValue()) 3699 return N0; 3700 // fold (sra -1, x) -> -1 3701 if (N0C && N0C->isAllOnesValue()) 3702 return N0; 3703 // fold (sra x, (setge c, size(x))) -> undef 3704 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 3705 return DAG.getUNDEF(VT); 3706 // fold (sra x, 0) -> x 3707 if (N1C && N1C->isNullValue()) 3708 return N0; 3709 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports 3710 // sext_inreg. 3711 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) { 3712 unsigned LowBits = OpSizeInBits - (unsigned)N1C->getZExtValue(); 3713 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), LowBits); 3714 if (VT.isVector()) 3715 ExtVT = EVT::getVectorVT(*DAG.getContext(), 3716 ExtVT, VT.getVectorNumElements()); 3717 if ((!LegalOperations || 3718 TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, ExtVT))) 3719 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, 3720 N0.getOperand(0), DAG.getValueType(ExtVT)); 3721 } 3722 3723 // fold (sra (sra x, c1), c2) -> (sra x, (add c1, c2)) 3724 if (N1C && N0.getOpcode() == ISD::SRA) { 3725 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 3726 unsigned Sum = N1C->getZExtValue() + C1->getZExtValue(); 3727 if (Sum >= OpSizeInBits) Sum = OpSizeInBits-1; 3728 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0.getOperand(0), 3729 DAG.getConstant(Sum, N1C->getValueType(0))); 3730 } 3731 } 3732 3733 // fold (sra (shl X, m), (sub result_size, n)) 3734 // -> (sign_extend (trunc (shl X, (sub (sub result_size, n), m)))) for 3735 // result_size - n != m. 3736 // If truncate is free for the target sext(shl) is likely to result in better 3737 // code. 3738 if (N0.getOpcode() == ISD::SHL) { 3739 // Get the two constanst of the shifts, CN0 = m, CN = n. 3740 const ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 3741 if (N01C && N1C) { 3742 // Determine what the truncate's result bitsize and type would be. 3743 EVT TruncVT = 3744 EVT::getIntegerVT(*DAG.getContext(), 3745 OpSizeInBits - N1C->getZExtValue()); 3746 // Determine the residual right-shift amount. 3747 signed ShiftAmt = N1C->getZExtValue() - N01C->getZExtValue(); 3748 3749 // If the shift is not a no-op (in which case this should be just a sign 3750 // extend already), the truncated to type is legal, sign_extend is legal 3751 // on that type, and the truncate to that type is both legal and free, 3752 // perform the transform. 3753 if ((ShiftAmt > 0) && 3754 TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND, TruncVT) && 3755 TLI.isOperationLegalOrCustom(ISD::TRUNCATE, VT) && 3756 TLI.isTruncateFree(VT, TruncVT)) { 3757 3758 SDValue Amt = DAG.getConstant(ShiftAmt, 3759 getShiftAmountTy(N0.getOperand(0).getValueType())); 3760 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, 3761 N0.getOperand(0), Amt); 3762 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), TruncVT, 3763 Shift); 3764 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), 3765 N->getValueType(0), Trunc); 3766 } 3767 } 3768 } 3769 3770 // fold (sra x, (trunc (and y, c))) -> (sra x, (and (trunc y), (trunc c))). 3771 if (N1.getOpcode() == ISD::TRUNCATE && 3772 N1.getOperand(0).getOpcode() == ISD::AND && 3773 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 3774 SDValue N101 = N1.getOperand(0).getOperand(1); 3775 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 3776 EVT TruncVT = N1.getValueType(); 3777 SDValue N100 = N1.getOperand(0).getOperand(0); 3778 APInt TruncC = N101C->getAPIntValue(); 3779 TruncC = TruncC.trunc(TruncVT.getScalarType().getSizeInBits()); 3780 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0, 3781 DAG.getNode(ISD::AND, N->getDebugLoc(), 3782 TruncVT, 3783 DAG.getNode(ISD::TRUNCATE, 3784 N->getDebugLoc(), 3785 TruncVT, N100), 3786 DAG.getConstant(TruncC, TruncVT))); 3787 } 3788 } 3789 3790 // fold (sra (trunc (sr x, c1)), c2) -> (trunc (sra x, c1+c2)) 3791 // if c1 is equal to the number of bits the trunc removes 3792 if (N0.getOpcode() == ISD::TRUNCATE && 3793 (N0.getOperand(0).getOpcode() == ISD::SRL || 3794 N0.getOperand(0).getOpcode() == ISD::SRA) && 3795 N0.getOperand(0).hasOneUse() && 3796 N0.getOperand(0).getOperand(1).hasOneUse() && 3797 N1C && isa<ConstantSDNode>(N0.getOperand(0).getOperand(1))) { 3798 EVT LargeVT = N0.getOperand(0).getValueType(); 3799 ConstantSDNode *LargeShiftAmt = 3800 cast<ConstantSDNode>(N0.getOperand(0).getOperand(1)); 3801 3802 if (LargeVT.getScalarType().getSizeInBits() - OpSizeInBits == 3803 LargeShiftAmt->getZExtValue()) { 3804 SDValue Amt = 3805 DAG.getConstant(LargeShiftAmt->getZExtValue() + N1C->getZExtValue(), 3806 getShiftAmountTy(N0.getOperand(0).getOperand(0).getValueType())); 3807 SDValue SRA = DAG.getNode(ISD::SRA, N->getDebugLoc(), LargeVT, 3808 N0.getOperand(0).getOperand(0), Amt); 3809 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, SRA); 3810 } 3811 } 3812 3813 // Simplify, based on bits shifted out of the LHS. 3814 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 3815 return SDValue(N, 0); 3816 3817 3818 // If the sign bit is known to be zero, switch this to a SRL. 3819 if (DAG.SignBitIsZero(N0)) 3820 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, N1); 3821 3822 if (N1C) { 3823 SDValue NewSRA = visitShiftByConstant(N, N1C->getZExtValue()); 3824 if (NewSRA.getNode()) 3825 return NewSRA; 3826 } 3827 3828 return SDValue(); 3829} 3830 3831SDValue DAGCombiner::visitSRL(SDNode *N) { 3832 SDValue N0 = N->getOperand(0); 3833 SDValue N1 = N->getOperand(1); 3834 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3835 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3836 EVT VT = N0.getValueType(); 3837 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits(); 3838 3839 // fold (srl c1, c2) -> c1 >>u c2 3840 if (N0C && N1C) 3841 return DAG.FoldConstantArithmetic(ISD::SRL, VT, N0C, N1C); 3842 // fold (srl 0, x) -> 0 3843 if (N0C && N0C->isNullValue()) 3844 return N0; 3845 // fold (srl x, c >= size(x)) -> undef 3846 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 3847 return DAG.getUNDEF(VT); 3848 // fold (srl x, 0) -> x 3849 if (N1C && N1C->isNullValue()) 3850 return N0; 3851 // if (srl x, c) is known to be zero, return 0 3852 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0), 3853 APInt::getAllOnesValue(OpSizeInBits))) 3854 return DAG.getConstant(0, VT); 3855 3856 // fold (srl (srl x, c1), c2) -> 0 or (srl x, (add c1, c2)) 3857 if (N1C && N0.getOpcode() == ISD::SRL && 3858 N0.getOperand(1).getOpcode() == ISD::Constant) { 3859 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 3860 uint64_t c2 = N1C->getZExtValue(); 3861 if (c1 + c2 >= OpSizeInBits) 3862 return DAG.getConstant(0, VT); 3863 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), 3864 DAG.getConstant(c1 + c2, N1.getValueType())); 3865 } 3866 3867 // fold (srl (trunc (srl x, c1)), c2) -> 0 or (trunc (srl x, (add c1, c2))) 3868 if (N1C && N0.getOpcode() == ISD::TRUNCATE && 3869 N0.getOperand(0).getOpcode() == ISD::SRL && 3870 isa<ConstantSDNode>(N0.getOperand(0)->getOperand(1))) { 3871 uint64_t c1 = 3872 cast<ConstantSDNode>(N0.getOperand(0)->getOperand(1))->getZExtValue(); 3873 uint64_t c2 = N1C->getZExtValue(); 3874 EVT InnerShiftVT = N0.getOperand(0).getValueType(); 3875 EVT ShiftCountVT = N0.getOperand(0)->getOperand(1).getValueType(); 3876 uint64_t InnerShiftSize = InnerShiftVT.getScalarType().getSizeInBits(); 3877 // This is only valid if the OpSizeInBits + c1 = size of inner shift. 3878 if (c1 + OpSizeInBits == InnerShiftSize) { 3879 if (c1 + c2 >= InnerShiftSize) 3880 return DAG.getConstant(0, VT); 3881 return DAG.getNode(ISD::TRUNCATE, N0->getDebugLoc(), VT, 3882 DAG.getNode(ISD::SRL, N0->getDebugLoc(), InnerShiftVT, 3883 N0.getOperand(0)->getOperand(0), 3884 DAG.getConstant(c1 + c2, ShiftCountVT))); 3885 } 3886 } 3887 3888 // fold (srl (shl x, c), c) -> (and x, cst2) 3889 if (N1C && N0.getOpcode() == ISD::SHL && N0.getOperand(1) == N1 && 3890 N0.getValueSizeInBits() <= 64) { 3891 uint64_t ShAmt = N1C->getZExtValue()+64-N0.getValueSizeInBits(); 3892 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0), 3893 DAG.getConstant(~0ULL >> ShAmt, VT)); 3894 } 3895 3896 3897 // fold (srl (anyextend x), c) -> (anyextend (srl x, c)) 3898 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 3899 // Shifting in all undef bits? 3900 EVT SmallVT = N0.getOperand(0).getValueType(); 3901 if (N1C->getZExtValue() >= SmallVT.getSizeInBits()) 3902 return DAG.getUNDEF(VT); 3903 3904 if (!LegalTypes || TLI.isTypeDesirableForOp(ISD::SRL, SmallVT)) { 3905 uint64_t ShiftAmt = N1C->getZExtValue(); 3906 SDValue SmallShift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), SmallVT, 3907 N0.getOperand(0), 3908 DAG.getConstant(ShiftAmt, getShiftAmountTy(SmallVT))); 3909 AddToWorkList(SmallShift.getNode()); 3910 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, SmallShift); 3911 } 3912 } 3913 3914 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign 3915 // bit, which is unmodified by sra. 3916 if (N1C && N1C->getZExtValue() + 1 == VT.getSizeInBits()) { 3917 if (N0.getOpcode() == ISD::SRA) 3918 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), N1); 3919 } 3920 3921 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit). 3922 if (N1C && N0.getOpcode() == ISD::CTLZ && 3923 N1C->getAPIntValue() == Log2_32(VT.getSizeInBits())) { 3924 APInt KnownZero, KnownOne; 3925 DAG.ComputeMaskedBits(N0.getOperand(0), KnownZero, KnownOne); 3926 3927 // If any of the input bits are KnownOne, then the input couldn't be all 3928 // zeros, thus the result of the srl will always be zero. 3929 if (KnownOne.getBoolValue()) return DAG.getConstant(0, VT); 3930 3931 // If all of the bits input the to ctlz node are known to be zero, then 3932 // the result of the ctlz is "32" and the result of the shift is one. 3933 APInt UnknownBits = ~KnownZero; 3934 if (UnknownBits == 0) return DAG.getConstant(1, VT); 3935 3936 // Otherwise, check to see if there is exactly one bit input to the ctlz. 3937 if ((UnknownBits & (UnknownBits - 1)) == 0) { 3938 // Okay, we know that only that the single bit specified by UnknownBits 3939 // could be set on input to the CTLZ node. If this bit is set, the SRL 3940 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair 3941 // to an SRL/XOR pair, which is likely to simplify more. 3942 unsigned ShAmt = UnknownBits.countTrailingZeros(); 3943 SDValue Op = N0.getOperand(0); 3944 3945 if (ShAmt) { 3946 Op = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, Op, 3947 DAG.getConstant(ShAmt, getShiftAmountTy(Op.getValueType()))); 3948 AddToWorkList(Op.getNode()); 3949 } 3950 3951 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, 3952 Op, DAG.getConstant(1, VT)); 3953 } 3954 } 3955 3956 // fold (srl x, (trunc (and y, c))) -> (srl x, (and (trunc y), (trunc c))). 3957 if (N1.getOpcode() == ISD::TRUNCATE && 3958 N1.getOperand(0).getOpcode() == ISD::AND && 3959 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 3960 SDValue N101 = N1.getOperand(0).getOperand(1); 3961 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 3962 EVT TruncVT = N1.getValueType(); 3963 SDValue N100 = N1.getOperand(0).getOperand(0); 3964 APInt TruncC = N101C->getAPIntValue(); 3965 TruncC = TruncC.trunc(TruncVT.getSizeInBits()); 3966 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, 3967 DAG.getNode(ISD::AND, N->getDebugLoc(), 3968 TruncVT, 3969 DAG.getNode(ISD::TRUNCATE, 3970 N->getDebugLoc(), 3971 TruncVT, N100), 3972 DAG.getConstant(TruncC, TruncVT))); 3973 } 3974 } 3975 3976 // fold operands of srl based on knowledge that the low bits are not 3977 // demanded. 3978 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 3979 return SDValue(N, 0); 3980 3981 if (N1C) { 3982 SDValue NewSRL = visitShiftByConstant(N, N1C->getZExtValue()); 3983 if (NewSRL.getNode()) 3984 return NewSRL; 3985 } 3986 3987 // Attempt to convert a srl of a load into a narrower zero-extending load. 3988 SDValue NarrowLoad = ReduceLoadWidth(N); 3989 if (NarrowLoad.getNode()) 3990 return NarrowLoad; 3991 3992 // Here is a common situation. We want to optimize: 3993 // 3994 // %a = ... 3995 // %b = and i32 %a, 2 3996 // %c = srl i32 %b, 1 3997 // brcond i32 %c ... 3998 // 3999 // into 4000 // 4001 // %a = ... 4002 // %b = and %a, 2 4003 // %c = setcc eq %b, 0 4004 // brcond %c ... 4005 // 4006 // However when after the source operand of SRL is optimized into AND, the SRL 4007 // itself may not be optimized further. Look for it and add the BRCOND into 4008 // the worklist. 4009 if (N->hasOneUse()) { 4010 SDNode *Use = *N->use_begin(); 4011 if (Use->getOpcode() == ISD::BRCOND) 4012 AddToWorkList(Use); 4013 else if (Use->getOpcode() == ISD::TRUNCATE && Use->hasOneUse()) { 4014 // Also look pass the truncate. 4015 Use = *Use->use_begin(); 4016 if (Use->getOpcode() == ISD::BRCOND) 4017 AddToWorkList(Use); 4018 } 4019 } 4020 4021 return SDValue(); 4022} 4023 4024SDValue DAGCombiner::visitCTLZ(SDNode *N) { 4025 SDValue N0 = N->getOperand(0); 4026 EVT VT = N->getValueType(0); 4027 4028 // fold (ctlz c1) -> c2 4029 if (isa<ConstantSDNode>(N0)) 4030 return DAG.getNode(ISD::CTLZ, N->getDebugLoc(), VT, N0); 4031 return SDValue(); 4032} 4033 4034SDValue DAGCombiner::visitCTLZ_ZERO_UNDEF(SDNode *N) { 4035 SDValue N0 = N->getOperand(0); 4036 EVT VT = N->getValueType(0); 4037 4038 // fold (ctlz_zero_undef c1) -> c2 4039 if (isa<ConstantSDNode>(N0)) 4040 return DAG.getNode(ISD::CTLZ_ZERO_UNDEF, N->getDebugLoc(), VT, N0); 4041 return SDValue(); 4042} 4043 4044SDValue DAGCombiner::visitCTTZ(SDNode *N) { 4045 SDValue N0 = N->getOperand(0); 4046 EVT VT = N->getValueType(0); 4047 4048 // fold (cttz c1) -> c2 4049 if (isa<ConstantSDNode>(N0)) 4050 return DAG.getNode(ISD::CTTZ, N->getDebugLoc(), VT, N0); 4051 return SDValue(); 4052} 4053 4054SDValue DAGCombiner::visitCTTZ_ZERO_UNDEF(SDNode *N) { 4055 SDValue N0 = N->getOperand(0); 4056 EVT VT = N->getValueType(0); 4057 4058 // fold (cttz_zero_undef c1) -> c2 4059 if (isa<ConstantSDNode>(N0)) 4060 return DAG.getNode(ISD::CTTZ_ZERO_UNDEF, N->getDebugLoc(), VT, N0); 4061 return SDValue(); 4062} 4063 4064SDValue DAGCombiner::visitCTPOP(SDNode *N) { 4065 SDValue N0 = N->getOperand(0); 4066 EVT VT = N->getValueType(0); 4067 4068 // fold (ctpop c1) -> c2 4069 if (isa<ConstantSDNode>(N0)) 4070 return DAG.getNode(ISD::CTPOP, N->getDebugLoc(), VT, N0); 4071 return SDValue(); 4072} 4073 4074SDValue DAGCombiner::visitSELECT(SDNode *N) { 4075 SDValue N0 = N->getOperand(0); 4076 SDValue N1 = N->getOperand(1); 4077 SDValue N2 = N->getOperand(2); 4078 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 4079 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 4080 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2); 4081 EVT VT = N->getValueType(0); 4082 EVT VT0 = N0.getValueType(); 4083 4084 // fold (select C, X, X) -> X 4085 if (N1 == N2) 4086 return N1; 4087 // fold (select true, X, Y) -> X 4088 if (N0C && !N0C->isNullValue()) 4089 return N1; 4090 // fold (select false, X, Y) -> Y 4091 if (N0C && N0C->isNullValue()) 4092 return N2; 4093 // fold (select C, 1, X) -> (or C, X) 4094 if (VT == MVT::i1 && N1C && N1C->getAPIntValue() == 1) 4095 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2); 4096 // fold (select C, 0, 1) -> (xor C, 1) 4097 if (VT.isInteger() && 4098 (VT0 == MVT::i1 || 4099 (VT0.isInteger() && 4100 TLI.getBooleanContents(false) == 4101 TargetLowering::ZeroOrOneBooleanContent)) && 4102 N1C && N2C && N1C->isNullValue() && N2C->getAPIntValue() == 1) { 4103 SDValue XORNode; 4104 if (VT == VT0) 4105 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT0, 4106 N0, DAG.getConstant(1, VT0)); 4107 XORNode = DAG.getNode(ISD::XOR, N0.getDebugLoc(), VT0, 4108 N0, DAG.getConstant(1, VT0)); 4109 AddToWorkList(XORNode.getNode()); 4110 if (VT.bitsGT(VT0)) 4111 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, XORNode); 4112 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, XORNode); 4113 } 4114 // fold (select C, 0, X) -> (and (not C), X) 4115 if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) { 4116 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT); 4117 AddToWorkList(NOTNode.getNode()); 4118 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, NOTNode, N2); 4119 } 4120 // fold (select C, X, 1) -> (or (not C), X) 4121 if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getAPIntValue() == 1) { 4122 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT); 4123 AddToWorkList(NOTNode.getNode()); 4124 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, NOTNode, N1); 4125 } 4126 // fold (select C, X, 0) -> (and C, X) 4127 if (VT == MVT::i1 && N2C && N2C->isNullValue()) 4128 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1); 4129 // fold (select X, X, Y) -> (or X, Y) 4130 // fold (select X, 1, Y) -> (or X, Y) 4131 if (VT == MVT::i1 && (N0 == N1 || (N1C && N1C->getAPIntValue() == 1))) 4132 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2); 4133 // fold (select X, Y, X) -> (and X, Y) 4134 // fold (select X, Y, 0) -> (and X, Y) 4135 if (VT == MVT::i1 && (N0 == N2 || (N2C && N2C->getAPIntValue() == 0))) 4136 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1); 4137 4138 // If we can fold this based on the true/false value, do so. 4139 if (SimplifySelectOps(N, N1, N2)) 4140 return SDValue(N, 0); // Don't revisit N. 4141 4142 // fold selects based on a setcc into other things, such as min/max/abs 4143 if (N0.getOpcode() == ISD::SETCC) { 4144 // FIXME: 4145 // Check against MVT::Other for SELECT_CC, which is a workaround for targets 4146 // having to say they don't support SELECT_CC on every type the DAG knows 4147 // about, since there is no way to mark an opcode illegal at all value types 4148 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other) && 4149 TLI.isOperationLegalOrCustom(ISD::SELECT_CC, VT)) 4150 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT, 4151 N0.getOperand(0), N0.getOperand(1), 4152 N1, N2, N0.getOperand(2)); 4153 return SimplifySelect(N->getDebugLoc(), N0, N1, N2); 4154 } 4155 4156 return SDValue(); 4157} 4158 4159SDValue DAGCombiner::visitSELECT_CC(SDNode *N) { 4160 SDValue N0 = N->getOperand(0); 4161 SDValue N1 = N->getOperand(1); 4162 SDValue N2 = N->getOperand(2); 4163 SDValue N3 = N->getOperand(3); 4164 SDValue N4 = N->getOperand(4); 4165 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get(); 4166 4167 // fold select_cc lhs, rhs, x, x, cc -> x 4168 if (N2 == N3) 4169 return N2; 4170 4171 // Determine if the condition we're dealing with is constant 4172 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()), 4173 N0, N1, CC, N->getDebugLoc(), false); 4174 if (SCC.getNode()) AddToWorkList(SCC.getNode()); 4175 4176 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode())) { 4177 if (!SCCC->isNullValue()) 4178 return N2; // cond always true -> true val 4179 else 4180 return N3; // cond always false -> false val 4181 } 4182 4183 // Fold to a simpler select_cc 4184 if (SCC.getNode() && SCC.getOpcode() == ISD::SETCC) 4185 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), N2.getValueType(), 4186 SCC.getOperand(0), SCC.getOperand(1), N2, N3, 4187 SCC.getOperand(2)); 4188 4189 // If we can fold this based on the true/false value, do so. 4190 if (SimplifySelectOps(N, N2, N3)) 4191 return SDValue(N, 0); // Don't revisit N. 4192 4193 // fold select_cc into other things, such as min/max/abs 4194 return SimplifySelectCC(N->getDebugLoc(), N0, N1, N2, N3, CC); 4195} 4196 4197SDValue DAGCombiner::visitSETCC(SDNode *N) { 4198 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1), 4199 cast<CondCodeSDNode>(N->getOperand(2))->get(), 4200 N->getDebugLoc()); 4201} 4202 4203// ExtendUsesToFormExtLoad - Trying to extend uses of a load to enable this: 4204// "fold ({s|z|a}ext (load x)) -> ({s|z|a}ext (truncate ({s|z|a}extload x)))" 4205// transformation. Returns true if extension are possible and the above 4206// mentioned transformation is profitable. 4207static bool ExtendUsesToFormExtLoad(SDNode *N, SDValue N0, 4208 unsigned ExtOpc, 4209 SmallVector<SDNode*, 4> &ExtendNodes, 4210 const TargetLowering &TLI) { 4211 bool HasCopyToRegUses = false; 4212 bool isTruncFree = TLI.isTruncateFree(N->getValueType(0), N0.getValueType()); 4213 for (SDNode::use_iterator UI = N0.getNode()->use_begin(), 4214 UE = N0.getNode()->use_end(); 4215 UI != UE; ++UI) { 4216 SDNode *User = *UI; 4217 if (User == N) 4218 continue; 4219 if (UI.getUse().getResNo() != N0.getResNo()) 4220 continue; 4221 // FIXME: Only extend SETCC N, N and SETCC N, c for now. 4222 if (ExtOpc != ISD::ANY_EXTEND && User->getOpcode() == ISD::SETCC) { 4223 ISD::CondCode CC = cast<CondCodeSDNode>(User->getOperand(2))->get(); 4224 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC)) 4225 // Sign bits will be lost after a zext. 4226 return false; 4227 bool Add = false; 4228 for (unsigned i = 0; i != 2; ++i) { 4229 SDValue UseOp = User->getOperand(i); 4230 if (UseOp == N0) 4231 continue; 4232 if (!isa<ConstantSDNode>(UseOp)) 4233 return false; 4234 Add = true; 4235 } 4236 if (Add) 4237 ExtendNodes.push_back(User); 4238 continue; 4239 } 4240 // If truncates aren't free and there are users we can't 4241 // extend, it isn't worthwhile. 4242 if (!isTruncFree) 4243 return false; 4244 // Remember if this value is live-out. 4245 if (User->getOpcode() == ISD::CopyToReg) 4246 HasCopyToRegUses = true; 4247 } 4248 4249 if (HasCopyToRegUses) { 4250 bool BothLiveOut = false; 4251 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 4252 UI != UE; ++UI) { 4253 SDUse &Use = UI.getUse(); 4254 if (Use.getResNo() == 0 && Use.getUser()->getOpcode() == ISD::CopyToReg) { 4255 BothLiveOut = true; 4256 break; 4257 } 4258 } 4259 if (BothLiveOut) 4260 // Both unextended and extended values are live out. There had better be 4261 // a good reason for the transformation. 4262 return ExtendNodes.size(); 4263 } 4264 return true; 4265} 4266 4267void DAGCombiner::ExtendSetCCUses(SmallVector<SDNode*, 4> SetCCs, 4268 SDValue Trunc, SDValue ExtLoad, DebugLoc DL, 4269 ISD::NodeType ExtType) { 4270 // Extend SetCC uses if necessary. 4271 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 4272 SDNode *SetCC = SetCCs[i]; 4273 SmallVector<SDValue, 4> Ops; 4274 4275 for (unsigned j = 0; j != 2; ++j) { 4276 SDValue SOp = SetCC->getOperand(j); 4277 if (SOp == Trunc) 4278 Ops.push_back(ExtLoad); 4279 else 4280 Ops.push_back(DAG.getNode(ExtType, DL, ExtLoad->getValueType(0), SOp)); 4281 } 4282 4283 Ops.push_back(SetCC->getOperand(2)); 4284 CombineTo(SetCC, DAG.getNode(ISD::SETCC, DL, SetCC->getValueType(0), 4285 &Ops[0], Ops.size())); 4286 } 4287} 4288 4289SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) { 4290 SDValue N0 = N->getOperand(0); 4291 EVT VT = N->getValueType(0); 4292 4293 // fold (sext c1) -> c1 4294 if (isa<ConstantSDNode>(N0)) 4295 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N0); 4296 4297 // fold (sext (sext x)) -> (sext x) 4298 // fold (sext (aext x)) -> (sext x) 4299 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 4300 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, 4301 N0.getOperand(0)); 4302 4303 if (N0.getOpcode() == ISD::TRUNCATE) { 4304 // fold (sext (truncate (load x))) -> (sext (smaller load x)) 4305 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n))) 4306 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 4307 if (NarrowLoad.getNode()) { 4308 SDNode* oye = N0.getNode()->getOperand(0).getNode(); 4309 if (NarrowLoad.getNode() != N0.getNode()) { 4310 CombineTo(N0.getNode(), NarrowLoad); 4311 // CombineTo deleted the truncate, if needed, but not what's under it. 4312 AddToWorkList(oye); 4313 } 4314 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4315 } 4316 4317 // See if the value being truncated is already sign extended. If so, just 4318 // eliminate the trunc/sext pair. 4319 SDValue Op = N0.getOperand(0); 4320 unsigned OpBits = Op.getValueType().getScalarType().getSizeInBits(); 4321 unsigned MidBits = N0.getValueType().getScalarType().getSizeInBits(); 4322 unsigned DestBits = VT.getScalarType().getSizeInBits(); 4323 unsigned NumSignBits = DAG.ComputeNumSignBits(Op); 4324 4325 if (OpBits == DestBits) { 4326 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign 4327 // bits, it is already ready. 4328 if (NumSignBits > DestBits-MidBits) 4329 return Op; 4330 } else if (OpBits < DestBits) { 4331 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign 4332 // bits, just sext from i32. 4333 if (NumSignBits > OpBits-MidBits) 4334 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, Op); 4335 } else { 4336 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign 4337 // bits, just truncate to i32. 4338 if (NumSignBits > OpBits-MidBits) 4339 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op); 4340 } 4341 4342 // fold (sext (truncate x)) -> (sextinreg x). 4343 if (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, 4344 N0.getValueType())) { 4345 if (OpBits < DestBits) 4346 Op = DAG.getNode(ISD::ANY_EXTEND, N0.getDebugLoc(), VT, Op); 4347 else if (OpBits > DestBits) 4348 Op = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), VT, Op); 4349 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, Op, 4350 DAG.getValueType(N0.getValueType())); 4351 } 4352 } 4353 4354 // fold (sext (load x)) -> (sext (truncate (sextload x))) 4355 // None of the supported targets knows how to perform load and sign extend 4356 // on vectors in one instruction. We only perform this transformation on 4357 // scalars. 4358 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() && 4359 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 4360 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()))) { 4361 bool DoXform = true; 4362 SmallVector<SDNode*, 4> SetCCs; 4363 if (!N0.hasOneUse()) 4364 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::SIGN_EXTEND, SetCCs, TLI); 4365 if (DoXform) { 4366 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4367 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 4368 LN0->getChain(), 4369 LN0->getBasePtr(), LN0->getPointerInfo(), 4370 N0.getValueType(), 4371 LN0->isVolatile(), LN0->isNonTemporal(), 4372 LN0->getAlignment()); 4373 CombineTo(N, ExtLoad); 4374 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 4375 N0.getValueType(), ExtLoad); 4376 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 4377 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(), 4378 ISD::SIGN_EXTEND); 4379 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4380 } 4381 } 4382 4383 // fold (sext (sextload x)) -> (sext (truncate (sextload x))) 4384 // fold (sext ( extload x)) -> (sext (truncate (sextload x))) 4385 if ((ISD::isSEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) && 4386 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) { 4387 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4388 EVT MemVT = LN0->getMemoryVT(); 4389 if ((!LegalOperations && !LN0->isVolatile()) || 4390 TLI.isLoadExtLegal(ISD::SEXTLOAD, MemVT)) { 4391 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 4392 LN0->getChain(), 4393 LN0->getBasePtr(), LN0->getPointerInfo(), 4394 MemVT, 4395 LN0->isVolatile(), LN0->isNonTemporal(), 4396 LN0->getAlignment()); 4397 CombineTo(N, ExtLoad); 4398 CombineTo(N0.getNode(), 4399 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 4400 N0.getValueType(), ExtLoad), 4401 ExtLoad.getValue(1)); 4402 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4403 } 4404 } 4405 4406 // fold (sext (and/or/xor (load x), cst)) -> 4407 // (and/or/xor (sextload x), (sext cst)) 4408 if ((N0.getOpcode() == ISD::AND || N0.getOpcode() == ISD::OR || 4409 N0.getOpcode() == ISD::XOR) && 4410 isa<LoadSDNode>(N0.getOperand(0)) && 4411 N0.getOperand(1).getOpcode() == ISD::Constant && 4412 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()) && 4413 (!LegalOperations && TLI.isOperationLegal(N0.getOpcode(), VT))) { 4414 LoadSDNode *LN0 = cast<LoadSDNode>(N0.getOperand(0)); 4415 if (LN0->getExtensionType() != ISD::ZEXTLOAD) { 4416 bool DoXform = true; 4417 SmallVector<SDNode*, 4> SetCCs; 4418 if (!N0.hasOneUse()) 4419 DoXform = ExtendUsesToFormExtLoad(N, N0.getOperand(0), ISD::SIGN_EXTEND, 4420 SetCCs, TLI); 4421 if (DoXform) { 4422 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, LN0->getDebugLoc(), VT, 4423 LN0->getChain(), LN0->getBasePtr(), 4424 LN0->getPointerInfo(), 4425 LN0->getMemoryVT(), 4426 LN0->isVolatile(), 4427 LN0->isNonTemporal(), 4428 LN0->getAlignment()); 4429 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 4430 Mask = Mask.sext(VT.getSizeInBits()); 4431 SDValue And = DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, 4432 ExtLoad, DAG.getConstant(Mask, VT)); 4433 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, 4434 N0.getOperand(0).getDebugLoc(), 4435 N0.getOperand(0).getValueType(), ExtLoad); 4436 CombineTo(N, And); 4437 CombineTo(N0.getOperand(0).getNode(), Trunc, ExtLoad.getValue(1)); 4438 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(), 4439 ISD::SIGN_EXTEND); 4440 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4441 } 4442 } 4443 } 4444 4445 if (N0.getOpcode() == ISD::SETCC) { 4446 // sext(setcc) -> sext_in_reg(vsetcc) for vectors. 4447 // Only do this before legalize for now. 4448 if (VT.isVector() && !LegalOperations) { 4449 EVT N0VT = N0.getOperand(0).getValueType(); 4450 // On some architectures (such as SSE/NEON/etc) the SETCC result type is 4451 // of the same size as the compared operands. Only optimize sext(setcc()) 4452 // if this is the case. 4453 EVT SVT = TLI.getSetCCResultType(N0VT); 4454 4455 // We know that the # elements of the results is the same as the 4456 // # elements of the compare (and the # elements of the compare result 4457 // for that matter). Check to see that they are the same size. If so, 4458 // we know that the element size of the sext'd result matches the 4459 // element size of the compare operands. 4460 if (VT.getSizeInBits() == SVT.getSizeInBits()) 4461 return DAG.getSetCC(N->getDebugLoc(), VT, N0.getOperand(0), 4462 N0.getOperand(1), 4463 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 4464 // If the desired elements are smaller or larger than the source 4465 // elements we can use a matching integer vector type and then 4466 // truncate/sign extend 4467 EVT MatchingElementType = 4468 EVT::getIntegerVT(*DAG.getContext(), 4469 N0VT.getScalarType().getSizeInBits()); 4470 EVT MatchingVectorType = 4471 EVT::getVectorVT(*DAG.getContext(), MatchingElementType, 4472 N0VT.getVectorNumElements()); 4473 4474 if (SVT == MatchingVectorType) { 4475 SDValue VsetCC = DAG.getSetCC(N->getDebugLoc(), MatchingVectorType, 4476 N0.getOperand(0), N0.getOperand(1), 4477 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 4478 return DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT); 4479 } 4480 } 4481 4482 // sext(setcc x, y, cc) -> (select_cc x, y, -1, 0, cc) 4483 unsigned ElementWidth = VT.getScalarType().getSizeInBits(); 4484 SDValue NegOne = 4485 DAG.getConstant(APInt::getAllOnesValue(ElementWidth), VT); 4486 SDValue SCC = 4487 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 4488 NegOne, DAG.getConstant(0, VT), 4489 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 4490 if (SCC.getNode()) return SCC; 4491 if (!LegalOperations || 4492 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(VT))) 4493 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT, 4494 DAG.getSetCC(N->getDebugLoc(), 4495 TLI.getSetCCResultType(VT), 4496 N0.getOperand(0), N0.getOperand(1), 4497 cast<CondCodeSDNode>(N0.getOperand(2))->get()), 4498 NegOne, DAG.getConstant(0, VT)); 4499 } 4500 4501 // fold (sext x) -> (zext x) if the sign bit is known zero. 4502 if ((!LegalOperations || TLI.isOperationLegal(ISD::ZERO_EXTEND, VT)) && 4503 DAG.SignBitIsZero(N0)) 4504 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0); 4505 4506 return SDValue(); 4507} 4508 4509// isTruncateOf - If N is a truncate of some other value, return true, record 4510// the value being truncated in Op and which of Op's bits are zero in KnownZero. 4511// This function computes KnownZero to avoid a duplicated call to 4512// ComputeMaskedBits in the caller. 4513static bool isTruncateOf(SelectionDAG &DAG, SDValue N, SDValue &Op, 4514 APInt &KnownZero) { 4515 APInt KnownOne; 4516 if (N->getOpcode() == ISD::TRUNCATE) { 4517 Op = N->getOperand(0); 4518 DAG.ComputeMaskedBits(Op, KnownZero, KnownOne); 4519 return true; 4520 } 4521 4522 if (N->getOpcode() != ISD::SETCC || N->getValueType(0) != MVT::i1 || 4523 cast<CondCodeSDNode>(N->getOperand(2))->get() != ISD::SETNE) 4524 return false; 4525 4526 SDValue Op0 = N->getOperand(0); 4527 SDValue Op1 = N->getOperand(1); 4528 assert(Op0.getValueType() == Op1.getValueType()); 4529 4530 ConstantSDNode *COp0 = dyn_cast<ConstantSDNode>(Op0); 4531 ConstantSDNode *COp1 = dyn_cast<ConstantSDNode>(Op1); 4532 if (COp0 && COp0->isNullValue()) 4533 Op = Op1; 4534 else if (COp1 && COp1->isNullValue()) 4535 Op = Op0; 4536 else 4537 return false; 4538 4539 DAG.ComputeMaskedBits(Op, KnownZero, KnownOne); 4540 4541 if (!(KnownZero | APInt(Op.getValueSizeInBits(), 1)).isAllOnesValue()) 4542 return false; 4543 4544 return true; 4545} 4546 4547SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) { 4548 SDValue N0 = N->getOperand(0); 4549 EVT VT = N->getValueType(0); 4550 4551 // fold (zext c1) -> c1 4552 if (isa<ConstantSDNode>(N0)) 4553 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0); 4554 // fold (zext (zext x)) -> (zext x) 4555 // fold (zext (aext x)) -> (zext x) 4556 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 4557 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, 4558 N0.getOperand(0)); 4559 4560 // fold (zext (truncate x)) -> (zext x) or 4561 // (zext (truncate x)) -> (truncate x) 4562 // This is valid when the truncated bits of x are already zero. 4563 // FIXME: We should extend this to work for vectors too. 4564 SDValue Op; 4565 APInt KnownZero; 4566 if (!VT.isVector() && isTruncateOf(DAG, N0, Op, KnownZero)) { 4567 APInt TruncatedBits = 4568 (Op.getValueSizeInBits() == N0.getValueSizeInBits()) ? 4569 APInt(Op.getValueSizeInBits(), 0) : 4570 APInt::getBitsSet(Op.getValueSizeInBits(), 4571 N0.getValueSizeInBits(), 4572 std::min(Op.getValueSizeInBits(), 4573 VT.getSizeInBits())); 4574 if (TruncatedBits == (KnownZero & TruncatedBits)) { 4575 if (VT.bitsGT(Op.getValueType())) 4576 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, Op); 4577 if (VT.bitsLT(Op.getValueType())) 4578 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op); 4579 4580 return Op; 4581 } 4582 } 4583 4584 // fold (zext (truncate (load x))) -> (zext (smaller load x)) 4585 // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n))) 4586 if (N0.getOpcode() == ISD::TRUNCATE) { 4587 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 4588 if (NarrowLoad.getNode()) { 4589 SDNode* oye = N0.getNode()->getOperand(0).getNode(); 4590 if (NarrowLoad.getNode() != N0.getNode()) { 4591 CombineTo(N0.getNode(), NarrowLoad); 4592 // CombineTo deleted the truncate, if needed, but not what's under it. 4593 AddToWorkList(oye); 4594 } 4595 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4596 } 4597 } 4598 4599 // fold (zext (truncate x)) -> (and x, mask) 4600 if (N0.getOpcode() == ISD::TRUNCATE && 4601 (!LegalOperations || TLI.isOperationLegal(ISD::AND, VT))) { 4602 4603 // fold (zext (truncate (load x))) -> (zext (smaller load x)) 4604 // fold (zext (truncate (srl (load x), c))) -> (zext (smaller load (x+c/n))) 4605 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 4606 if (NarrowLoad.getNode()) { 4607 SDNode* oye = N0.getNode()->getOperand(0).getNode(); 4608 if (NarrowLoad.getNode() != N0.getNode()) { 4609 CombineTo(N0.getNode(), NarrowLoad); 4610 // CombineTo deleted the truncate, if needed, but not what's under it. 4611 AddToWorkList(oye); 4612 } 4613 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4614 } 4615 4616 SDValue Op = N0.getOperand(0); 4617 if (Op.getValueType().bitsLT(VT)) { 4618 Op = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, Op); 4619 AddToWorkList(Op.getNode()); 4620 } else if (Op.getValueType().bitsGT(VT)) { 4621 Op = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op); 4622 AddToWorkList(Op.getNode()); 4623 } 4624 return DAG.getZeroExtendInReg(Op, N->getDebugLoc(), 4625 N0.getValueType().getScalarType()); 4626 } 4627 4628 // Fold (zext (and (trunc x), cst)) -> (and x, cst), 4629 // if either of the casts is not free. 4630 if (N0.getOpcode() == ISD::AND && 4631 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 4632 N0.getOperand(1).getOpcode() == ISD::Constant && 4633 (!TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(), 4634 N0.getValueType()) || 4635 !TLI.isZExtFree(N0.getValueType(), VT))) { 4636 SDValue X = N0.getOperand(0).getOperand(0); 4637 if (X.getValueType().bitsLT(VT)) { 4638 X = DAG.getNode(ISD::ANY_EXTEND, X.getDebugLoc(), VT, X); 4639 } else if (X.getValueType().bitsGT(VT)) { 4640 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X); 4641 } 4642 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 4643 Mask = Mask.zext(VT.getSizeInBits()); 4644 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 4645 X, DAG.getConstant(Mask, VT)); 4646 } 4647 4648 // fold (zext (load x)) -> (zext (truncate (zextload x))) 4649 // None of the supported targets knows how to perform load and vector_zext 4650 // on vectors in one instruction. We only perform this transformation on 4651 // scalars. 4652 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() && 4653 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 4654 TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()))) { 4655 bool DoXform = true; 4656 SmallVector<SDNode*, 4> SetCCs; 4657 if (!N0.hasOneUse()) 4658 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ZERO_EXTEND, SetCCs, TLI); 4659 if (DoXform) { 4660 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4661 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT, 4662 LN0->getChain(), 4663 LN0->getBasePtr(), LN0->getPointerInfo(), 4664 N0.getValueType(), 4665 LN0->isVolatile(), LN0->isNonTemporal(), 4666 LN0->getAlignment()); 4667 CombineTo(N, ExtLoad); 4668 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 4669 N0.getValueType(), ExtLoad); 4670 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 4671 4672 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(), 4673 ISD::ZERO_EXTEND); 4674 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4675 } 4676 } 4677 4678 // fold (zext (and/or/xor (load x), cst)) -> 4679 // (and/or/xor (zextload x), (zext cst)) 4680 if ((N0.getOpcode() == ISD::AND || N0.getOpcode() == ISD::OR || 4681 N0.getOpcode() == ISD::XOR) && 4682 isa<LoadSDNode>(N0.getOperand(0)) && 4683 N0.getOperand(1).getOpcode() == ISD::Constant && 4684 TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()) && 4685 (!LegalOperations && TLI.isOperationLegal(N0.getOpcode(), VT))) { 4686 LoadSDNode *LN0 = cast<LoadSDNode>(N0.getOperand(0)); 4687 if (LN0->getExtensionType() != ISD::SEXTLOAD) { 4688 bool DoXform = true; 4689 SmallVector<SDNode*, 4> SetCCs; 4690 if (!N0.hasOneUse()) 4691 DoXform = ExtendUsesToFormExtLoad(N, N0.getOperand(0), ISD::ZERO_EXTEND, 4692 SetCCs, TLI); 4693 if (DoXform) { 4694 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), VT, 4695 LN0->getChain(), LN0->getBasePtr(), 4696 LN0->getPointerInfo(), 4697 LN0->getMemoryVT(), 4698 LN0->isVolatile(), 4699 LN0->isNonTemporal(), 4700 LN0->getAlignment()); 4701 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 4702 Mask = Mask.zext(VT.getSizeInBits()); 4703 SDValue And = DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, 4704 ExtLoad, DAG.getConstant(Mask, VT)); 4705 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, 4706 N0.getOperand(0).getDebugLoc(), 4707 N0.getOperand(0).getValueType(), ExtLoad); 4708 CombineTo(N, And); 4709 CombineTo(N0.getOperand(0).getNode(), Trunc, ExtLoad.getValue(1)); 4710 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(), 4711 ISD::ZERO_EXTEND); 4712 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4713 } 4714 } 4715 } 4716 4717 // fold (zext (zextload x)) -> (zext (truncate (zextload x))) 4718 // fold (zext ( extload x)) -> (zext (truncate (zextload x))) 4719 if ((ISD::isZEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) && 4720 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) { 4721 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4722 EVT MemVT = LN0->getMemoryVT(); 4723 if ((!LegalOperations && !LN0->isVolatile()) || 4724 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT)) { 4725 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT, 4726 LN0->getChain(), 4727 LN0->getBasePtr(), LN0->getPointerInfo(), 4728 MemVT, 4729 LN0->isVolatile(), LN0->isNonTemporal(), 4730 LN0->getAlignment()); 4731 CombineTo(N, ExtLoad); 4732 CombineTo(N0.getNode(), 4733 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), N0.getValueType(), 4734 ExtLoad), 4735 ExtLoad.getValue(1)); 4736 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4737 } 4738 } 4739 4740 if (N0.getOpcode() == ISD::SETCC) { 4741 if (!LegalOperations && VT.isVector()) { 4742 // zext(setcc) -> (and (vsetcc), (1, 1, ...) for vectors. 4743 // Only do this before legalize for now. 4744 EVT N0VT = N0.getOperand(0).getValueType(); 4745 EVT EltVT = VT.getVectorElementType(); 4746 SmallVector<SDValue,8> OneOps(VT.getVectorNumElements(), 4747 DAG.getConstant(1, EltVT)); 4748 if (VT.getSizeInBits() == N0VT.getSizeInBits()) 4749 // We know that the # elements of the results is the same as the 4750 // # elements of the compare (and the # elements of the compare result 4751 // for that matter). Check to see that they are the same size. If so, 4752 // we know that the element size of the sext'd result matches the 4753 // element size of the compare operands. 4754 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 4755 DAG.getSetCC(N->getDebugLoc(), VT, N0.getOperand(0), 4756 N0.getOperand(1), 4757 cast<CondCodeSDNode>(N0.getOperand(2))->get()), 4758 DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT, 4759 &OneOps[0], OneOps.size())); 4760 4761 // If the desired elements are smaller or larger than the source 4762 // elements we can use a matching integer vector type and then 4763 // truncate/sign extend 4764 EVT MatchingElementType = 4765 EVT::getIntegerVT(*DAG.getContext(), 4766 N0VT.getScalarType().getSizeInBits()); 4767 EVT MatchingVectorType = 4768 EVT::getVectorVT(*DAG.getContext(), MatchingElementType, 4769 N0VT.getVectorNumElements()); 4770 SDValue VsetCC = 4771 DAG.getSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0), 4772 N0.getOperand(1), 4773 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 4774 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 4775 DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT), 4776 DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT, 4777 &OneOps[0], OneOps.size())); 4778 } 4779 4780 // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 4781 SDValue SCC = 4782 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 4783 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 4784 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 4785 if (SCC.getNode()) return SCC; 4786 } 4787 4788 // (zext (shl (zext x), cst)) -> (shl (zext x), cst) 4789 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL) && 4790 isa<ConstantSDNode>(N0.getOperand(1)) && 4791 N0.getOperand(0).getOpcode() == ISD::ZERO_EXTEND && 4792 N0.hasOneUse()) { 4793 SDValue ShAmt = N0.getOperand(1); 4794 unsigned ShAmtVal = cast<ConstantSDNode>(ShAmt)->getZExtValue(); 4795 if (N0.getOpcode() == ISD::SHL) { 4796 SDValue InnerZExt = N0.getOperand(0); 4797 // If the original shl may be shifting out bits, do not perform this 4798 // transformation. 4799 unsigned KnownZeroBits = InnerZExt.getValueType().getSizeInBits() - 4800 InnerZExt.getOperand(0).getValueType().getSizeInBits(); 4801 if (ShAmtVal > KnownZeroBits) 4802 return SDValue(); 4803 } 4804 4805 DebugLoc DL = N->getDebugLoc(); 4806 4807 // Ensure that the shift amount is wide enough for the shifted value. 4808 if (VT.getSizeInBits() >= 256) 4809 ShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, ShAmt); 4810 4811 return DAG.getNode(N0.getOpcode(), DL, VT, 4812 DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0)), 4813 ShAmt); 4814 } 4815 4816 return SDValue(); 4817} 4818 4819SDValue DAGCombiner::visitANY_EXTEND(SDNode *N) { 4820 SDValue N0 = N->getOperand(0); 4821 EVT VT = N->getValueType(0); 4822 4823 // fold (aext c1) -> c1 4824 if (isa<ConstantSDNode>(N0)) 4825 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, N0); 4826 // fold (aext (aext x)) -> (aext x) 4827 // fold (aext (zext x)) -> (zext x) 4828 // fold (aext (sext x)) -> (sext x) 4829 if (N0.getOpcode() == ISD::ANY_EXTEND || 4830 N0.getOpcode() == ISD::ZERO_EXTEND || 4831 N0.getOpcode() == ISD::SIGN_EXTEND) 4832 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, N0.getOperand(0)); 4833 4834 // fold (aext (truncate (load x))) -> (aext (smaller load x)) 4835 // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n))) 4836 if (N0.getOpcode() == ISD::TRUNCATE) { 4837 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 4838 if (NarrowLoad.getNode()) { 4839 SDNode* oye = N0.getNode()->getOperand(0).getNode(); 4840 if (NarrowLoad.getNode() != N0.getNode()) { 4841 CombineTo(N0.getNode(), NarrowLoad); 4842 // CombineTo deleted the truncate, if needed, but not what's under it. 4843 AddToWorkList(oye); 4844 } 4845 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4846 } 4847 } 4848 4849 // fold (aext (truncate x)) 4850 if (N0.getOpcode() == ISD::TRUNCATE) { 4851 SDValue TruncOp = N0.getOperand(0); 4852 if (TruncOp.getValueType() == VT) 4853 return TruncOp; // x iff x size == zext size. 4854 if (TruncOp.getValueType().bitsGT(VT)) 4855 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, TruncOp); 4856 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, TruncOp); 4857 } 4858 4859 // Fold (aext (and (trunc x), cst)) -> (and x, cst) 4860 // if the trunc is not free. 4861 if (N0.getOpcode() == ISD::AND && 4862 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 4863 N0.getOperand(1).getOpcode() == ISD::Constant && 4864 !TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(), 4865 N0.getValueType())) { 4866 SDValue X = N0.getOperand(0).getOperand(0); 4867 if (X.getValueType().bitsLT(VT)) { 4868 X = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, X); 4869 } else if (X.getValueType().bitsGT(VT)) { 4870 X = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, X); 4871 } 4872 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 4873 Mask = Mask.zext(VT.getSizeInBits()); 4874 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 4875 X, DAG.getConstant(Mask, VT)); 4876 } 4877 4878 // fold (aext (load x)) -> (aext (truncate (extload x))) 4879 // None of the supported targets knows how to perform load and any_ext 4880 // on vectors in one instruction. We only perform this transformation on 4881 // scalars. 4882 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() && 4883 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 4884 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) { 4885 bool DoXform = true; 4886 SmallVector<SDNode*, 4> SetCCs; 4887 if (!N0.hasOneUse()) 4888 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ANY_EXTEND, SetCCs, TLI); 4889 if (DoXform) { 4890 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4891 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT, 4892 LN0->getChain(), 4893 LN0->getBasePtr(), LN0->getPointerInfo(), 4894 N0.getValueType(), 4895 LN0->isVolatile(), LN0->isNonTemporal(), 4896 LN0->getAlignment()); 4897 CombineTo(N, ExtLoad); 4898 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 4899 N0.getValueType(), ExtLoad); 4900 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 4901 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(), 4902 ISD::ANY_EXTEND); 4903 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4904 } 4905 } 4906 4907 // fold (aext (zextload x)) -> (aext (truncate (zextload x))) 4908 // fold (aext (sextload x)) -> (aext (truncate (sextload x))) 4909 // fold (aext ( extload x)) -> (aext (truncate (extload x))) 4910 if (N0.getOpcode() == ISD::LOAD && 4911 !ISD::isNON_EXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 4912 N0.hasOneUse()) { 4913 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4914 EVT MemVT = LN0->getMemoryVT(); 4915 SDValue ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), N->getDebugLoc(), 4916 VT, LN0->getChain(), LN0->getBasePtr(), 4917 LN0->getPointerInfo(), MemVT, 4918 LN0->isVolatile(), LN0->isNonTemporal(), 4919 LN0->getAlignment()); 4920 CombineTo(N, ExtLoad); 4921 CombineTo(N0.getNode(), 4922 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 4923 N0.getValueType(), ExtLoad), 4924 ExtLoad.getValue(1)); 4925 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4926 } 4927 4928 if (N0.getOpcode() == ISD::SETCC) { 4929 // aext(setcc) -> sext_in_reg(vsetcc) for vectors. 4930 // Only do this before legalize for now. 4931 if (VT.isVector() && !LegalOperations) { 4932 EVT N0VT = N0.getOperand(0).getValueType(); 4933 // We know that the # elements of the results is the same as the 4934 // # elements of the compare (and the # elements of the compare result 4935 // for that matter). Check to see that they are the same size. If so, 4936 // we know that the element size of the sext'd result matches the 4937 // element size of the compare operands. 4938 if (VT.getSizeInBits() == N0VT.getSizeInBits()) 4939 return DAG.getSetCC(N->getDebugLoc(), VT, N0.getOperand(0), 4940 N0.getOperand(1), 4941 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 4942 // If the desired elements are smaller or larger than the source 4943 // elements we can use a matching integer vector type and then 4944 // truncate/sign extend 4945 else { 4946 EVT MatchingElementType = 4947 EVT::getIntegerVT(*DAG.getContext(), 4948 N0VT.getScalarType().getSizeInBits()); 4949 EVT MatchingVectorType = 4950 EVT::getVectorVT(*DAG.getContext(), MatchingElementType, 4951 N0VT.getVectorNumElements()); 4952 SDValue VsetCC = 4953 DAG.getSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0), 4954 N0.getOperand(1), 4955 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 4956 return DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT); 4957 } 4958 } 4959 4960 // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 4961 SDValue SCC = 4962 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 4963 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 4964 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 4965 if (SCC.getNode()) 4966 return SCC; 4967 } 4968 4969 return SDValue(); 4970} 4971 4972/// GetDemandedBits - See if the specified operand can be simplified with the 4973/// knowledge that only the bits specified by Mask are used. If so, return the 4974/// simpler operand, otherwise return a null SDValue. 4975SDValue DAGCombiner::GetDemandedBits(SDValue V, const APInt &Mask) { 4976 switch (V.getOpcode()) { 4977 default: break; 4978 case ISD::Constant: { 4979 const ConstantSDNode *CV = cast<ConstantSDNode>(V.getNode()); 4980 assert(CV != 0 && "Const value should be ConstSDNode."); 4981 const APInt &CVal = CV->getAPIntValue(); 4982 APInt NewVal = CVal & Mask; 4983 if (NewVal != CVal) { 4984 return DAG.getConstant(NewVal, V.getValueType()); 4985 } 4986 break; 4987 } 4988 case ISD::OR: 4989 case ISD::XOR: 4990 // If the LHS or RHS don't contribute bits to the or, drop them. 4991 if (DAG.MaskedValueIsZero(V.getOperand(0), Mask)) 4992 return V.getOperand(1); 4993 if (DAG.MaskedValueIsZero(V.getOperand(1), Mask)) 4994 return V.getOperand(0); 4995 break; 4996 case ISD::SRL: 4997 // Only look at single-use SRLs. 4998 if (!V.getNode()->hasOneUse()) 4999 break; 5000 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(V.getOperand(1))) { 5001 // See if we can recursively simplify the LHS. 5002 unsigned Amt = RHSC->getZExtValue(); 5003 5004 // Watch out for shift count overflow though. 5005 if (Amt >= Mask.getBitWidth()) break; 5006 APInt NewMask = Mask << Amt; 5007 SDValue SimplifyLHS = GetDemandedBits(V.getOperand(0), NewMask); 5008 if (SimplifyLHS.getNode()) 5009 return DAG.getNode(ISD::SRL, V.getDebugLoc(), V.getValueType(), 5010 SimplifyLHS, V.getOperand(1)); 5011 } 5012 } 5013 return SDValue(); 5014} 5015 5016/// ReduceLoadWidth - If the result of a wider load is shifted to right of N 5017/// bits and then truncated to a narrower type and where N is a multiple 5018/// of number of bits of the narrower type, transform it to a narrower load 5019/// from address + N / num of bits of new type. If the result is to be 5020/// extended, also fold the extension to form a extending load. 5021SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) { 5022 unsigned Opc = N->getOpcode(); 5023 5024 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD; 5025 SDValue N0 = N->getOperand(0); 5026 EVT VT = N->getValueType(0); 5027 EVT ExtVT = VT; 5028 5029 // This transformation isn't valid for vector loads. 5030 if (VT.isVector()) 5031 return SDValue(); 5032 5033 // Special case: SIGN_EXTEND_INREG is basically truncating to ExtVT then 5034 // extended to VT. 5035 if (Opc == ISD::SIGN_EXTEND_INREG) { 5036 ExtType = ISD::SEXTLOAD; 5037 ExtVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 5038 } else if (Opc == ISD::SRL) { 5039 // Another special-case: SRL is basically zero-extending a narrower value. 5040 ExtType = ISD::ZEXTLOAD; 5041 N0 = SDValue(N, 0); 5042 ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 5043 if (!N01) return SDValue(); 5044 ExtVT = EVT::getIntegerVT(*DAG.getContext(), 5045 VT.getSizeInBits() - N01->getZExtValue()); 5046 } 5047 if (LegalOperations && !TLI.isLoadExtLegal(ExtType, ExtVT)) 5048 return SDValue(); 5049 5050 unsigned EVTBits = ExtVT.getSizeInBits(); 5051 5052 // Do not generate loads of non-round integer types since these can 5053 // be expensive (and would be wrong if the type is not byte sized). 5054 if (!ExtVT.isRound()) 5055 return SDValue(); 5056 5057 unsigned ShAmt = 0; 5058 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) { 5059 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 5060 ShAmt = N01->getZExtValue(); 5061 // Is the shift amount a multiple of size of VT? 5062 if ((ShAmt & (EVTBits-1)) == 0) { 5063 N0 = N0.getOperand(0); 5064 // Is the load width a multiple of size of VT? 5065 if ((N0.getValueType().getSizeInBits() & (EVTBits-1)) != 0) 5066 return SDValue(); 5067 } 5068 5069 // At this point, we must have a load or else we can't do the transform. 5070 if (!isa<LoadSDNode>(N0)) return SDValue(); 5071 5072 // Because a SRL must be assumed to *need* to zero-extend the high bits 5073 // (as opposed to anyext the high bits), we can't combine the zextload 5074 // lowering of SRL and an sextload. 5075 if (cast<LoadSDNode>(N0)->getExtensionType() == ISD::SEXTLOAD) 5076 return SDValue(); 5077 5078 // If the shift amount is larger than the input type then we're not 5079 // accessing any of the loaded bytes. If the load was a zextload/extload 5080 // then the result of the shift+trunc is zero/undef (handled elsewhere). 5081 if (ShAmt >= cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits()) 5082 return SDValue(); 5083 } 5084 } 5085 5086 // If the load is shifted left (and the result isn't shifted back right), 5087 // we can fold the truncate through the shift. 5088 unsigned ShLeftAmt = 0; 5089 if (ShAmt == 0 && N0.getOpcode() == ISD::SHL && N0.hasOneUse() && 5090 ExtVT == VT && TLI.isNarrowingProfitable(N0.getValueType(), VT)) { 5091 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 5092 ShLeftAmt = N01->getZExtValue(); 5093 N0 = N0.getOperand(0); 5094 } 5095 } 5096 5097 // If we haven't found a load, we can't narrow it. Don't transform one with 5098 // multiple uses, this would require adding a new load. 5099 if (!isa<LoadSDNode>(N0) || !N0.hasOneUse() || 5100 // Don't change the width of a volatile load. 5101 cast<LoadSDNode>(N0)->isVolatile()) 5102 return SDValue(); 5103 5104 // Verify that we are actually reducing a load width here. 5105 if (cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits() < EVTBits) 5106 return SDValue(); 5107 5108 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 5109 EVT PtrType = N0.getOperand(1).getValueType(); 5110 5111 if (PtrType == MVT::Untyped || PtrType.isExtended()) 5112 // It's not possible to generate a constant of extended or untyped type. 5113 return SDValue(); 5114 5115 // For big endian targets, we need to adjust the offset to the pointer to 5116 // load the correct bytes. 5117 if (TLI.isBigEndian()) { 5118 unsigned LVTStoreBits = LN0->getMemoryVT().getStoreSizeInBits(); 5119 unsigned EVTStoreBits = ExtVT.getStoreSizeInBits(); 5120 ShAmt = LVTStoreBits - EVTStoreBits - ShAmt; 5121 } 5122 5123 uint64_t PtrOff = ShAmt / 8; 5124 unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff); 5125 SDValue NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(), 5126 PtrType, LN0->getBasePtr(), 5127 DAG.getConstant(PtrOff, PtrType)); 5128 AddToWorkList(NewPtr.getNode()); 5129 5130 SDValue Load; 5131 if (ExtType == ISD::NON_EXTLOAD) 5132 Load = DAG.getLoad(VT, N0.getDebugLoc(), LN0->getChain(), NewPtr, 5133 LN0->getPointerInfo().getWithOffset(PtrOff), 5134 LN0->isVolatile(), LN0->isNonTemporal(), 5135 LN0->isInvariant(), NewAlign); 5136 else 5137 Load = DAG.getExtLoad(ExtType, N0.getDebugLoc(), VT, LN0->getChain(),NewPtr, 5138 LN0->getPointerInfo().getWithOffset(PtrOff), 5139 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(), 5140 NewAlign); 5141 5142 // Replace the old load's chain with the new load's chain. 5143 WorkListRemover DeadNodes(*this); 5144 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1)); 5145 5146 // Shift the result left, if we've swallowed a left shift. 5147 SDValue Result = Load; 5148 if (ShLeftAmt != 0) { 5149 EVT ShImmTy = getShiftAmountTy(Result.getValueType()); 5150 if (!isUIntN(ShImmTy.getSizeInBits(), ShLeftAmt)) 5151 ShImmTy = VT; 5152 Result = DAG.getNode(ISD::SHL, N0.getDebugLoc(), VT, 5153 Result, DAG.getConstant(ShLeftAmt, ShImmTy)); 5154 } 5155 5156 // Return the new loaded value. 5157 return Result; 5158} 5159 5160SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) { 5161 SDValue N0 = N->getOperand(0); 5162 SDValue N1 = N->getOperand(1); 5163 EVT VT = N->getValueType(0); 5164 EVT EVT = cast<VTSDNode>(N1)->getVT(); 5165 unsigned VTBits = VT.getScalarType().getSizeInBits(); 5166 unsigned EVTBits = EVT.getScalarType().getSizeInBits(); 5167 5168 // fold (sext_in_reg c1) -> c1 5169 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF) 5170 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, N0, N1); 5171 5172 // If the input is already sign extended, just drop the extension. 5173 if (DAG.ComputeNumSignBits(N0) >= VTBits-EVTBits+1) 5174 return N0; 5175 5176 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2 5177 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 5178 EVT.bitsLT(cast<VTSDNode>(N0.getOperand(1))->getVT())) { 5179 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, 5180 N0.getOperand(0), N1); 5181 } 5182 5183 // fold (sext_in_reg (sext x)) -> (sext x) 5184 // fold (sext_in_reg (aext x)) -> (sext x) 5185 // if x is small enough. 5186 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) { 5187 SDValue N00 = N0.getOperand(0); 5188 if (N00.getValueType().getScalarType().getSizeInBits() <= EVTBits && 5189 (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND, VT))) 5190 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N00, N1); 5191 } 5192 5193 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero. 5194 if (DAG.MaskedValueIsZero(N0, APInt::getBitsSet(VTBits, EVTBits-1, EVTBits))) 5195 return DAG.getZeroExtendInReg(N0, N->getDebugLoc(), EVT); 5196 5197 // fold operands of sext_in_reg based on knowledge that the top bits are not 5198 // demanded. 5199 if (SimplifyDemandedBits(SDValue(N, 0))) 5200 return SDValue(N, 0); 5201 5202 // fold (sext_in_reg (load x)) -> (smaller sextload x) 5203 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits)) 5204 SDValue NarrowLoad = ReduceLoadWidth(N); 5205 if (NarrowLoad.getNode()) 5206 return NarrowLoad; 5207 5208 // fold (sext_in_reg (srl X, 24), i8) -> (sra X, 24) 5209 // fold (sext_in_reg (srl X, 23), i8) -> (sra X, 23) iff possible. 5210 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above. 5211 if (N0.getOpcode() == ISD::SRL) { 5212 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 5213 if (ShAmt->getZExtValue()+EVTBits <= VTBits) { 5214 // We can turn this into an SRA iff the input to the SRL is already sign 5215 // extended enough. 5216 unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0)); 5217 if (VTBits-(ShAmt->getZExtValue()+EVTBits) < InSignBits) 5218 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, 5219 N0.getOperand(0), N0.getOperand(1)); 5220 } 5221 } 5222 5223 // fold (sext_inreg (extload x)) -> (sextload x) 5224 if (ISD::isEXTLoad(N0.getNode()) && 5225 ISD::isUNINDEXEDLoad(N0.getNode()) && 5226 EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 5227 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 5228 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) { 5229 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 5230 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 5231 LN0->getChain(), 5232 LN0->getBasePtr(), LN0->getPointerInfo(), 5233 EVT, 5234 LN0->isVolatile(), LN0->isNonTemporal(), 5235 LN0->getAlignment()); 5236 CombineTo(N, ExtLoad); 5237 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 5238 return SDValue(N, 0); // Return N so it doesn't get rechecked! 5239 } 5240 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use 5241 if (ISD::isZEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 5242 N0.hasOneUse() && 5243 EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 5244 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 5245 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) { 5246 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 5247 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 5248 LN0->getChain(), 5249 LN0->getBasePtr(), LN0->getPointerInfo(), 5250 EVT, 5251 LN0->isVolatile(), LN0->isNonTemporal(), 5252 LN0->getAlignment()); 5253 CombineTo(N, ExtLoad); 5254 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 5255 return SDValue(N, 0); // Return N so it doesn't get rechecked! 5256 } 5257 5258 // Form (sext_inreg (bswap >> 16)) or (sext_inreg (rotl (bswap) 16)) 5259 if (EVTBits <= 16 && N0.getOpcode() == ISD::OR) { 5260 SDValue BSwap = MatchBSwapHWordLow(N0.getNode(), N0.getOperand(0), 5261 N0.getOperand(1), false); 5262 if (BSwap.getNode() != 0) 5263 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, 5264 BSwap, N1); 5265 } 5266 5267 return SDValue(); 5268} 5269 5270SDValue DAGCombiner::visitTRUNCATE(SDNode *N) { 5271 SDValue N0 = N->getOperand(0); 5272 EVT VT = N->getValueType(0); 5273 bool isLE = TLI.isLittleEndian(); 5274 5275 // noop truncate 5276 if (N0.getValueType() == N->getValueType(0)) 5277 return N0; 5278 // fold (truncate c1) -> c1 5279 if (isa<ConstantSDNode>(N0)) 5280 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0); 5281 // fold (truncate (truncate x)) -> (truncate x) 5282 if (N0.getOpcode() == ISD::TRUNCATE) 5283 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0)); 5284 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x 5285 if (N0.getOpcode() == ISD::ZERO_EXTEND || 5286 N0.getOpcode() == ISD::SIGN_EXTEND || 5287 N0.getOpcode() == ISD::ANY_EXTEND) { 5288 if (N0.getOperand(0).getValueType().bitsLT(VT)) 5289 // if the source is smaller than the dest, we still need an extend 5290 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, 5291 N0.getOperand(0)); 5292 if (N0.getOperand(0).getValueType().bitsGT(VT)) 5293 // if the source is larger than the dest, than we just need the truncate 5294 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0)); 5295 // if the source and dest are the same type, we can drop both the extend 5296 // and the truncate. 5297 return N0.getOperand(0); 5298 } 5299 5300 // Fold extract-and-trunc into a narrow extract. For example: 5301 // i64 x = EXTRACT_VECTOR_ELT(v2i64 val, i32 1) 5302 // i32 y = TRUNCATE(i64 x) 5303 // -- becomes -- 5304 // v16i8 b = BITCAST (v2i64 val) 5305 // i8 x = EXTRACT_VECTOR_ELT(v16i8 b, i32 8) 5306 // 5307 // Note: We only run this optimization after type legalization (which often 5308 // creates this pattern) and before operation legalization after which 5309 // we need to be more careful about the vector instructions that we generate. 5310 if (N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT && 5311 LegalTypes && !LegalOperations && N0->hasOneUse()) { 5312 5313 EVT VecTy = N0.getOperand(0).getValueType(); 5314 EVT ExTy = N0.getValueType(); 5315 EVT TrTy = N->getValueType(0); 5316 5317 unsigned NumElem = VecTy.getVectorNumElements(); 5318 unsigned SizeRatio = ExTy.getSizeInBits()/TrTy.getSizeInBits(); 5319 5320 EVT NVT = EVT::getVectorVT(*DAG.getContext(), TrTy, SizeRatio * NumElem); 5321 assert(NVT.getSizeInBits() == VecTy.getSizeInBits() && "Invalid Size"); 5322 5323 SDValue EltNo = N0->getOperand(1); 5324 if (isa<ConstantSDNode>(EltNo) && isTypeLegal(NVT)) { 5325 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 5326 EVT IndexTy = N0->getOperand(1).getValueType(); 5327 int Index = isLE ? (Elt*SizeRatio) : (Elt*SizeRatio + (SizeRatio-1)); 5328 5329 SDValue V = DAG.getNode(ISD::BITCAST, N->getDebugLoc(), 5330 NVT, N0.getOperand(0)); 5331 5332 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, 5333 N->getDebugLoc(), TrTy, V, 5334 DAG.getConstant(Index, IndexTy)); 5335 } 5336 } 5337 5338 // See if we can simplify the input to this truncate through knowledge that 5339 // only the low bits are being used. 5340 // For example "trunc (or (shl x, 8), y)" // -> trunc y 5341 // Currently we only perform this optimization on scalars because vectors 5342 // may have different active low bits. 5343 if (!VT.isVector()) { 5344 SDValue Shorter = 5345 GetDemandedBits(N0, APInt::getLowBitsSet(N0.getValueSizeInBits(), 5346 VT.getSizeInBits())); 5347 if (Shorter.getNode()) 5348 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Shorter); 5349 } 5350 // fold (truncate (load x)) -> (smaller load x) 5351 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits)) 5352 if (!LegalTypes || TLI.isTypeDesirableForOp(N0.getOpcode(), VT)) { 5353 SDValue Reduced = ReduceLoadWidth(N); 5354 if (Reduced.getNode()) 5355 return Reduced; 5356 } 5357 // fold (trunc (concat ... x ...)) -> (concat ..., (trunc x), ...)), 5358 // where ... are all 'undef'. 5359 if (N0.getOpcode() == ISD::CONCAT_VECTORS && !LegalTypes) { 5360 SmallVector<EVT, 8> VTs; 5361 SDValue V; 5362 unsigned Idx = 0; 5363 unsigned NumDefs = 0; 5364 5365 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i) { 5366 SDValue X = N0.getOperand(i); 5367 if (X.getOpcode() != ISD::UNDEF) { 5368 V = X; 5369 Idx = i; 5370 NumDefs++; 5371 } 5372 // Stop if more than one members are non-undef. 5373 if (NumDefs > 1) 5374 break; 5375 VTs.push_back(EVT::getVectorVT(*DAG.getContext(), 5376 VT.getVectorElementType(), 5377 X.getValueType().getVectorNumElements())); 5378 } 5379 5380 if (NumDefs == 0) 5381 return DAG.getUNDEF(VT); 5382 5383 if (NumDefs == 1) { 5384 assert(V.getNode() && "The single defined operand is empty!"); 5385 SmallVector<SDValue, 8> Opnds; 5386 for (unsigned i = 0, e = VTs.size(); i != e; ++i) { 5387 if (i != Idx) { 5388 Opnds.push_back(DAG.getUNDEF(VTs[i])); 5389 continue; 5390 } 5391 SDValue NV = DAG.getNode(ISD::TRUNCATE, V.getDebugLoc(), VTs[i], V); 5392 AddToWorkList(NV.getNode()); 5393 Opnds.push_back(NV); 5394 } 5395 return DAG.getNode(ISD::CONCAT_VECTORS, N->getDebugLoc(), VT, 5396 &Opnds[0], Opnds.size()); 5397 } 5398 } 5399 5400 // Simplify the operands using demanded-bits information. 5401 if (!VT.isVector() && 5402 SimplifyDemandedBits(SDValue(N, 0))) 5403 return SDValue(N, 0); 5404 5405 return SDValue(); 5406} 5407 5408static SDNode *getBuildPairElt(SDNode *N, unsigned i) { 5409 SDValue Elt = N->getOperand(i); 5410 if (Elt.getOpcode() != ISD::MERGE_VALUES) 5411 return Elt.getNode(); 5412 return Elt.getOperand(Elt.getResNo()).getNode(); 5413} 5414 5415/// CombineConsecutiveLoads - build_pair (load, load) -> load 5416/// if load locations are consecutive. 5417SDValue DAGCombiner::CombineConsecutiveLoads(SDNode *N, EVT VT) { 5418 assert(N->getOpcode() == ISD::BUILD_PAIR); 5419 5420 LoadSDNode *LD1 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 0)); 5421 LoadSDNode *LD2 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 1)); 5422 if (!LD1 || !LD2 || !ISD::isNON_EXTLoad(LD1) || !LD1->hasOneUse() || 5423 LD1->getPointerInfo().getAddrSpace() != 5424 LD2->getPointerInfo().getAddrSpace()) 5425 return SDValue(); 5426 EVT LD1VT = LD1->getValueType(0); 5427 5428 if (ISD::isNON_EXTLoad(LD2) && 5429 LD2->hasOneUse() && 5430 // If both are volatile this would reduce the number of volatile loads. 5431 // If one is volatile it might be ok, but play conservative and bail out. 5432 !LD1->isVolatile() && 5433 !LD2->isVolatile() && 5434 DAG.isConsecutiveLoad(LD2, LD1, LD1VT.getSizeInBits()/8, 1)) { 5435 unsigned Align = LD1->getAlignment(); 5436 unsigned NewAlign = TLI.getDataLayout()-> 5437 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext())); 5438 5439 if (NewAlign <= Align && 5440 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) 5441 return DAG.getLoad(VT, N->getDebugLoc(), LD1->getChain(), 5442 LD1->getBasePtr(), LD1->getPointerInfo(), 5443 false, false, false, Align); 5444 } 5445 5446 return SDValue(); 5447} 5448 5449SDValue DAGCombiner::visitBITCAST(SDNode *N) { 5450 SDValue N0 = N->getOperand(0); 5451 EVT VT = N->getValueType(0); 5452 5453 // If the input is a BUILD_VECTOR with all constant elements, fold this now. 5454 // Only do this before legalize, since afterward the target may be depending 5455 // on the bitconvert. 5456 // First check to see if this is all constant. 5457 if (!LegalTypes && 5458 N0.getOpcode() == ISD::BUILD_VECTOR && N0.getNode()->hasOneUse() && 5459 VT.isVector()) { 5460 bool isSimple = true; 5461 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i) 5462 if (N0.getOperand(i).getOpcode() != ISD::UNDEF && 5463 N0.getOperand(i).getOpcode() != ISD::Constant && 5464 N0.getOperand(i).getOpcode() != ISD::ConstantFP) { 5465 isSimple = false; 5466 break; 5467 } 5468 5469 EVT DestEltVT = N->getValueType(0).getVectorElementType(); 5470 assert(!DestEltVT.isVector() && 5471 "Element type of vector ValueType must not be vector!"); 5472 if (isSimple) 5473 return ConstantFoldBITCASTofBUILD_VECTOR(N0.getNode(), DestEltVT); 5474 } 5475 5476 // If the input is a constant, let getNode fold it. 5477 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) { 5478 SDValue Res = DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, N0); 5479 if (Res.getNode() != N) { 5480 if (!LegalOperations || 5481 TLI.isOperationLegal(Res.getNode()->getOpcode(), VT)) 5482 return Res; 5483 5484 // Folding it resulted in an illegal node, and it's too late to 5485 // do that. Clean up the old node and forego the transformation. 5486 // Ideally this won't happen very often, because instcombine 5487 // and the earlier dagcombine runs (where illegal nodes are 5488 // permitted) should have folded most of them already. 5489 DAG.DeleteNode(Res.getNode()); 5490 } 5491 } 5492 5493 // (conv (conv x, t1), t2) -> (conv x, t2) 5494 if (N0.getOpcode() == ISD::BITCAST) 5495 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, 5496 N0.getOperand(0)); 5497 5498 // fold (conv (load x)) -> (load (conv*)x) 5499 // If the resultant load doesn't need a higher alignment than the original! 5500 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() && 5501 // Do not change the width of a volatile load. 5502 !cast<LoadSDNode>(N0)->isVolatile() && 5503 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) { 5504 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 5505 unsigned Align = TLI.getDataLayout()-> 5506 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext())); 5507 unsigned OrigAlign = LN0->getAlignment(); 5508 5509 if (Align <= OrigAlign) { 5510 SDValue Load = DAG.getLoad(VT, N->getDebugLoc(), LN0->getChain(), 5511 LN0->getBasePtr(), LN0->getPointerInfo(), 5512 LN0->isVolatile(), LN0->isNonTemporal(), 5513 LN0->isInvariant(), OrigAlign); 5514 AddToWorkList(N); 5515 CombineTo(N0.getNode(), 5516 DAG.getNode(ISD::BITCAST, N0.getDebugLoc(), 5517 N0.getValueType(), Load), 5518 Load.getValue(1)); 5519 return Load; 5520 } 5521 } 5522 5523 // fold (bitconvert (fneg x)) -> (xor (bitconvert x), signbit) 5524 // fold (bitconvert (fabs x)) -> (and (bitconvert x), (not signbit)) 5525 // This often reduces constant pool loads. 5526 if (((N0.getOpcode() == ISD::FNEG && !TLI.isFNegFree(VT)) || 5527 (N0.getOpcode() == ISD::FABS && !TLI.isFAbsFree(VT))) && 5528 N0.getNode()->hasOneUse() && VT.isInteger() && 5529 !VT.isVector() && !N0.getValueType().isVector()) { 5530 SDValue NewConv = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(), VT, 5531 N0.getOperand(0)); 5532 AddToWorkList(NewConv.getNode()); 5533 5534 APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); 5535 if (N0.getOpcode() == ISD::FNEG) 5536 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, 5537 NewConv, DAG.getConstant(SignBit, VT)); 5538 assert(N0.getOpcode() == ISD::FABS); 5539 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 5540 NewConv, DAG.getConstant(~SignBit, VT)); 5541 } 5542 5543 // fold (bitconvert (fcopysign cst, x)) -> 5544 // (or (and (bitconvert x), sign), (and cst, (not sign))) 5545 // Note that we don't handle (copysign x, cst) because this can always be 5546 // folded to an fneg or fabs. 5547 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse() && 5548 isa<ConstantFPSDNode>(N0.getOperand(0)) && 5549 VT.isInteger() && !VT.isVector()) { 5550 unsigned OrigXWidth = N0.getOperand(1).getValueType().getSizeInBits(); 5551 EVT IntXVT = EVT::getIntegerVT(*DAG.getContext(), OrigXWidth); 5552 if (isTypeLegal(IntXVT)) { 5553 SDValue X = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(), 5554 IntXVT, N0.getOperand(1)); 5555 AddToWorkList(X.getNode()); 5556 5557 // If X has a different width than the result/lhs, sext it or truncate it. 5558 unsigned VTWidth = VT.getSizeInBits(); 5559 if (OrigXWidth < VTWidth) { 5560 X = DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, X); 5561 AddToWorkList(X.getNode()); 5562 } else if (OrigXWidth > VTWidth) { 5563 // To get the sign bit in the right place, we have to shift it right 5564 // before truncating. 5565 X = DAG.getNode(ISD::SRL, X.getDebugLoc(), 5566 X.getValueType(), X, 5567 DAG.getConstant(OrigXWidth-VTWidth, X.getValueType())); 5568 AddToWorkList(X.getNode()); 5569 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X); 5570 AddToWorkList(X.getNode()); 5571 } 5572 5573 APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); 5574 X = DAG.getNode(ISD::AND, X.getDebugLoc(), VT, 5575 X, DAG.getConstant(SignBit, VT)); 5576 AddToWorkList(X.getNode()); 5577 5578 SDValue Cst = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(), 5579 VT, N0.getOperand(0)); 5580 Cst = DAG.getNode(ISD::AND, Cst.getDebugLoc(), VT, 5581 Cst, DAG.getConstant(~SignBit, VT)); 5582 AddToWorkList(Cst.getNode()); 5583 5584 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, X, Cst); 5585 } 5586 } 5587 5588 // bitconvert(build_pair(ld, ld)) -> ld iff load locations are consecutive. 5589 if (N0.getOpcode() == ISD::BUILD_PAIR) { 5590 SDValue CombineLD = CombineConsecutiveLoads(N0.getNode(), VT); 5591 if (CombineLD.getNode()) 5592 return CombineLD; 5593 } 5594 5595 return SDValue(); 5596} 5597 5598SDValue DAGCombiner::visitBUILD_PAIR(SDNode *N) { 5599 EVT VT = N->getValueType(0); 5600 return CombineConsecutiveLoads(N, VT); 5601} 5602 5603/// ConstantFoldBITCASTofBUILD_VECTOR - We know that BV is a build_vector 5604/// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the 5605/// destination element value type. 5606SDValue DAGCombiner:: 5607ConstantFoldBITCASTofBUILD_VECTOR(SDNode *BV, EVT DstEltVT) { 5608 EVT SrcEltVT = BV->getValueType(0).getVectorElementType(); 5609 5610 // If this is already the right type, we're done. 5611 if (SrcEltVT == DstEltVT) return SDValue(BV, 0); 5612 5613 unsigned SrcBitSize = SrcEltVT.getSizeInBits(); 5614 unsigned DstBitSize = DstEltVT.getSizeInBits(); 5615 5616 // If this is a conversion of N elements of one type to N elements of another 5617 // type, convert each element. This handles FP<->INT cases. 5618 if (SrcBitSize == DstBitSize) { 5619 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, 5620 BV->getValueType(0).getVectorNumElements()); 5621 5622 // Due to the FP element handling below calling this routine recursively, 5623 // we can end up with a scalar-to-vector node here. 5624 if (BV->getOpcode() == ISD::SCALAR_TO_VECTOR) 5625 return DAG.getNode(ISD::SCALAR_TO_VECTOR, BV->getDebugLoc(), VT, 5626 DAG.getNode(ISD::BITCAST, BV->getDebugLoc(), 5627 DstEltVT, BV->getOperand(0))); 5628 5629 SmallVector<SDValue, 8> Ops; 5630 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 5631 SDValue Op = BV->getOperand(i); 5632 // If the vector element type is not legal, the BUILD_VECTOR operands 5633 // are promoted and implicitly truncated. Make that explicit here. 5634 if (Op.getValueType() != SrcEltVT) 5635 Op = DAG.getNode(ISD::TRUNCATE, BV->getDebugLoc(), SrcEltVT, Op); 5636 Ops.push_back(DAG.getNode(ISD::BITCAST, BV->getDebugLoc(), 5637 DstEltVT, Op)); 5638 AddToWorkList(Ops.back().getNode()); 5639 } 5640 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 5641 &Ops[0], Ops.size()); 5642 } 5643 5644 // Otherwise, we're growing or shrinking the elements. To avoid having to 5645 // handle annoying details of growing/shrinking FP values, we convert them to 5646 // int first. 5647 if (SrcEltVT.isFloatingPoint()) { 5648 // Convert the input float vector to a int vector where the elements are the 5649 // same sizes. 5650 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!"); 5651 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), SrcEltVT.getSizeInBits()); 5652 BV = ConstantFoldBITCASTofBUILD_VECTOR(BV, IntVT).getNode(); 5653 SrcEltVT = IntVT; 5654 } 5655 5656 // Now we know the input is an integer vector. If the output is a FP type, 5657 // convert to integer first, then to FP of the right size. 5658 if (DstEltVT.isFloatingPoint()) { 5659 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!"); 5660 EVT TmpVT = EVT::getIntegerVT(*DAG.getContext(), DstEltVT.getSizeInBits()); 5661 SDNode *Tmp = ConstantFoldBITCASTofBUILD_VECTOR(BV, TmpVT).getNode(); 5662 5663 // Next, convert to FP elements of the same size. 5664 return ConstantFoldBITCASTofBUILD_VECTOR(Tmp, DstEltVT); 5665 } 5666 5667 // Okay, we know the src/dst types are both integers of differing types. 5668 // Handling growing first. 5669 assert(SrcEltVT.isInteger() && DstEltVT.isInteger()); 5670 if (SrcBitSize < DstBitSize) { 5671 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize; 5672 5673 SmallVector<SDValue, 8> Ops; 5674 for (unsigned i = 0, e = BV->getNumOperands(); i != e; 5675 i += NumInputsPerOutput) { 5676 bool isLE = TLI.isLittleEndian(); 5677 APInt NewBits = APInt(DstBitSize, 0); 5678 bool EltIsUndef = true; 5679 for (unsigned j = 0; j != NumInputsPerOutput; ++j) { 5680 // Shift the previously computed bits over. 5681 NewBits <<= SrcBitSize; 5682 SDValue Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j)); 5683 if (Op.getOpcode() == ISD::UNDEF) continue; 5684 EltIsUndef = false; 5685 5686 NewBits |= cast<ConstantSDNode>(Op)->getAPIntValue(). 5687 zextOrTrunc(SrcBitSize).zext(DstBitSize); 5688 } 5689 5690 if (EltIsUndef) 5691 Ops.push_back(DAG.getUNDEF(DstEltVT)); 5692 else 5693 Ops.push_back(DAG.getConstant(NewBits, DstEltVT)); 5694 } 5695 5696 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, Ops.size()); 5697 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 5698 &Ops[0], Ops.size()); 5699 } 5700 5701 // Finally, this must be the case where we are shrinking elements: each input 5702 // turns into multiple outputs. 5703 bool isS2V = ISD::isScalarToVector(BV); 5704 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize; 5705 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, 5706 NumOutputsPerInput*BV->getNumOperands()); 5707 SmallVector<SDValue, 8> Ops; 5708 5709 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 5710 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) { 5711 for (unsigned j = 0; j != NumOutputsPerInput; ++j) 5712 Ops.push_back(DAG.getUNDEF(DstEltVT)); 5713 continue; 5714 } 5715 5716 APInt OpVal = cast<ConstantSDNode>(BV->getOperand(i))-> 5717 getAPIntValue().zextOrTrunc(SrcBitSize); 5718 5719 for (unsigned j = 0; j != NumOutputsPerInput; ++j) { 5720 APInt ThisVal = OpVal.trunc(DstBitSize); 5721 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT)); 5722 if (isS2V && i == 0 && j == 0 && ThisVal.zext(SrcBitSize) == OpVal) 5723 // Simply turn this into a SCALAR_TO_VECTOR of the new type. 5724 return DAG.getNode(ISD::SCALAR_TO_VECTOR, BV->getDebugLoc(), VT, 5725 Ops[0]); 5726 OpVal = OpVal.lshr(DstBitSize); 5727 } 5728 5729 // For big endian targets, swap the order of the pieces of each element. 5730 if (TLI.isBigEndian()) 5731 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end()); 5732 } 5733 5734 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 5735 &Ops[0], Ops.size()); 5736} 5737 5738SDValue DAGCombiner::visitFADD(SDNode *N) { 5739 SDValue N0 = N->getOperand(0); 5740 SDValue N1 = N->getOperand(1); 5741 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5742 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 5743 EVT VT = N->getValueType(0); 5744 5745 // fold vector ops 5746 if (VT.isVector()) { 5747 SDValue FoldedVOp = SimplifyVBinOp(N); 5748 if (FoldedVOp.getNode()) return FoldedVOp; 5749 } 5750 5751 // fold (fadd c1, c2) -> c1 + c2 5752 if (N0CFP && N1CFP) 5753 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N1); 5754 // canonicalize constant to RHS 5755 if (N0CFP && !N1CFP) 5756 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N1, N0); 5757 // fold (fadd A, 0) -> A 5758 if (DAG.getTarget().Options.UnsafeFPMath && N1CFP && 5759 N1CFP->getValueAPF().isZero()) 5760 return N0; 5761 // fold (fadd A, (fneg B)) -> (fsub A, B) 5762 if ((!LegalOperations || TLI.isOperationLegalOrCustom(ISD::FSUB, VT)) && 5763 isNegatibleForFree(N1, LegalOperations, TLI, &DAG.getTarget().Options) == 2) 5764 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, 5765 GetNegatedExpression(N1, DAG, LegalOperations)); 5766 // fold (fadd (fneg A), B) -> (fsub B, A) 5767 if ((!LegalOperations || TLI.isOperationLegalOrCustom(ISD::FSUB, VT)) && 5768 isNegatibleForFree(N0, LegalOperations, TLI, &DAG.getTarget().Options) == 2) 5769 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N1, 5770 GetNegatedExpression(N0, DAG, LegalOperations)); 5771 5772 // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2)) 5773 if (DAG.getTarget().Options.UnsafeFPMath && N1CFP && 5774 N0.getOpcode() == ISD::FADD && N0.getNode()->hasOneUse() && 5775 isa<ConstantFPSDNode>(N0.getOperand(1))) 5776 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0.getOperand(0), 5777 DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, 5778 N0.getOperand(1), N1)); 5779 5780 // If allow, fold (fadd (fneg x), x) -> 0.0 5781 if (DAG.getTarget().Options.UnsafeFPMath && 5782 N0.getOpcode() == ISD::FNEG && N0.getOperand(0) == N1) { 5783 return DAG.getConstantFP(0.0, VT); 5784 } 5785 5786 // If allow, fold (fadd x, (fneg x)) -> 0.0 5787 if (DAG.getTarget().Options.UnsafeFPMath && 5788 N1.getOpcode() == ISD::FNEG && N1.getOperand(0) == N0) { 5789 return DAG.getConstantFP(0.0, VT); 5790 } 5791 5792 // In unsafe math mode, we can fold chains of FADD's of the same value 5793 // into multiplications. This transform is not safe in general because 5794 // we are reducing the number of rounding steps. 5795 if (DAG.getTarget().Options.UnsafeFPMath && 5796 TLI.isOperationLegalOrCustom(ISD::FMUL, VT) && 5797 !N0CFP && !N1CFP) { 5798 if (N0.getOpcode() == ISD::FMUL) { 5799 ConstantFPSDNode *CFP00 = dyn_cast<ConstantFPSDNode>(N0.getOperand(0)); 5800 ConstantFPSDNode *CFP01 = dyn_cast<ConstantFPSDNode>(N0.getOperand(1)); 5801 5802 // (fadd (fmul c, x), x) -> (fmul c+1, x) 5803 if (CFP00 && !CFP01 && N0.getOperand(1) == N1) { 5804 SDValue NewCFP = DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, 5805 SDValue(CFP00, 0), 5806 DAG.getConstantFP(1.0, VT)); 5807 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 5808 N1, NewCFP); 5809 } 5810 5811 // (fadd (fmul x, c), x) -> (fmul c+1, x) 5812 if (CFP01 && !CFP00 && N0.getOperand(0) == N1) { 5813 SDValue NewCFP = DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, 5814 SDValue(CFP01, 0), 5815 DAG.getConstantFP(1.0, VT)); 5816 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 5817 N1, NewCFP); 5818 } 5819 5820 // (fadd (fadd x, x), x) -> (fmul 3.0, x) 5821 if (!CFP00 && !CFP01 && N0.getOperand(0) == N0.getOperand(1) && 5822 N0.getOperand(0) == N1) { 5823 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 5824 N1, DAG.getConstantFP(3.0, VT)); 5825 } 5826 5827 // (fadd (fmul c, x), (fadd x, x)) -> (fmul c+2, x) 5828 if (CFP00 && !CFP01 && N1.getOpcode() == ISD::FADD && 5829 N1.getOperand(0) == N1.getOperand(1) && 5830 N0.getOperand(1) == N1.getOperand(0)) { 5831 SDValue NewCFP = DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, 5832 SDValue(CFP00, 0), 5833 DAG.getConstantFP(2.0, VT)); 5834 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 5835 N0.getOperand(1), NewCFP); 5836 } 5837 5838 // (fadd (fmul x, c), (fadd x, x)) -> (fmul c+2, x) 5839 if (CFP01 && !CFP00 && N1.getOpcode() == ISD::FADD && 5840 N1.getOperand(0) == N1.getOperand(1) && 5841 N0.getOperand(0) == N1.getOperand(0)) { 5842 SDValue NewCFP = DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, 5843 SDValue(CFP01, 0), 5844 DAG.getConstantFP(2.0, VT)); 5845 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 5846 N0.getOperand(0), NewCFP); 5847 } 5848 } 5849 5850 if (N1.getOpcode() == ISD::FMUL) { 5851 ConstantFPSDNode *CFP10 = dyn_cast<ConstantFPSDNode>(N1.getOperand(0)); 5852 ConstantFPSDNode *CFP11 = dyn_cast<ConstantFPSDNode>(N1.getOperand(1)); 5853 5854 // (fadd x, (fmul c, x)) -> (fmul c+1, x) 5855 if (CFP10 && !CFP11 && N1.getOperand(1) == N0) { 5856 SDValue NewCFP = DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, 5857 SDValue(CFP10, 0), 5858 DAG.getConstantFP(1.0, VT)); 5859 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 5860 N0, NewCFP); 5861 } 5862 5863 // (fadd x, (fmul x, c)) -> (fmul c+1, x) 5864 if (CFP11 && !CFP10 && N1.getOperand(0) == N0) { 5865 SDValue NewCFP = DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, 5866 SDValue(CFP11, 0), 5867 DAG.getConstantFP(1.0, VT)); 5868 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 5869 N0, NewCFP); 5870 } 5871 5872 // (fadd x, (fadd x, x)) -> (fmul 3.0, x) 5873 if (!CFP10 && !CFP11 && N1.getOperand(0) == N1.getOperand(1) && 5874 N1.getOperand(0) == N0) { 5875 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 5876 N0, DAG.getConstantFP(3.0, VT)); 5877 } 5878 5879 // (fadd (fadd x, x), (fmul c, x)) -> (fmul c+2, x) 5880 if (CFP10 && !CFP11 && N1.getOpcode() == ISD::FADD && 5881 N1.getOperand(0) == N1.getOperand(1) && 5882 N0.getOperand(1) == N1.getOperand(0)) { 5883 SDValue NewCFP = DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, 5884 SDValue(CFP10, 0), 5885 DAG.getConstantFP(2.0, VT)); 5886 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 5887 N0.getOperand(1), NewCFP); 5888 } 5889 5890 // (fadd (fadd x, x), (fmul x, c)) -> (fmul c+2, x) 5891 if (CFP11 && !CFP10 && N1.getOpcode() == ISD::FADD && 5892 N1.getOperand(0) == N1.getOperand(1) && 5893 N0.getOperand(0) == N1.getOperand(0)) { 5894 SDValue NewCFP = DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, 5895 SDValue(CFP11, 0), 5896 DAG.getConstantFP(2.0, VT)); 5897 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 5898 N0.getOperand(0), NewCFP); 5899 } 5900 } 5901 5902 // (fadd (fadd x, x), (fadd x, x)) -> (fmul 4.0, x) 5903 if (N0.getOpcode() == ISD::FADD && N1.getOpcode() == ISD::FADD && 5904 N0.getOperand(0) == N0.getOperand(1) && 5905 N1.getOperand(0) == N1.getOperand(1) && 5906 N0.getOperand(0) == N1.getOperand(0)) { 5907 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 5908 N0.getOperand(0), 5909 DAG.getConstantFP(4.0, VT)); 5910 } 5911 } 5912 5913 // FADD -> FMA combines: 5914 if ((DAG.getTarget().Options.AllowFPOpFusion == FPOpFusion::Fast || 5915 DAG.getTarget().Options.UnsafeFPMath) && 5916 DAG.getTarget().getTargetLowering()->isFMAFasterThanMulAndAdd(VT) && 5917 TLI.isOperationLegalOrCustom(ISD::FMA, VT)) { 5918 5919 // fold (fadd (fmul x, y), z) -> (fma x, y, z) 5920 if (N0.getOpcode() == ISD::FMUL && N0->hasOneUse()) { 5921 return DAG.getNode(ISD::FMA, N->getDebugLoc(), VT, 5922 N0.getOperand(0), N0.getOperand(1), N1); 5923 } 5924 5925 // fold (fadd x, (fmul y, z)) -> (fma y, z, x) 5926 // Note: Commutes FADD operands. 5927 if (N1.getOpcode() == ISD::FMUL && N1->hasOneUse()) { 5928 return DAG.getNode(ISD::FMA, N->getDebugLoc(), VT, 5929 N1.getOperand(0), N1.getOperand(1), N0); 5930 } 5931 } 5932 5933 return SDValue(); 5934} 5935 5936SDValue DAGCombiner::visitFSUB(SDNode *N) { 5937 SDValue N0 = N->getOperand(0); 5938 SDValue N1 = N->getOperand(1); 5939 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5940 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 5941 EVT VT = N->getValueType(0); 5942 DebugLoc dl = N->getDebugLoc(); 5943 5944 // fold vector ops 5945 if (VT.isVector()) { 5946 SDValue FoldedVOp = SimplifyVBinOp(N); 5947 if (FoldedVOp.getNode()) return FoldedVOp; 5948 } 5949 5950 // fold (fsub c1, c2) -> c1-c2 5951 if (N0CFP && N1CFP) 5952 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, N1); 5953 // fold (fsub A, 0) -> A 5954 if (DAG.getTarget().Options.UnsafeFPMath && 5955 N1CFP && N1CFP->getValueAPF().isZero()) 5956 return N0; 5957 // fold (fsub 0, B) -> -B 5958 if (DAG.getTarget().Options.UnsafeFPMath && 5959 N0CFP && N0CFP->getValueAPF().isZero()) { 5960 if (isNegatibleForFree(N1, LegalOperations, TLI, &DAG.getTarget().Options)) 5961 return GetNegatedExpression(N1, DAG, LegalOperations); 5962 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 5963 return DAG.getNode(ISD::FNEG, dl, VT, N1); 5964 } 5965 // fold (fsub A, (fneg B)) -> (fadd A, B) 5966 if (isNegatibleForFree(N1, LegalOperations, TLI, &DAG.getTarget().Options)) 5967 return DAG.getNode(ISD::FADD, dl, VT, N0, 5968 GetNegatedExpression(N1, DAG, LegalOperations)); 5969 5970 // If 'unsafe math' is enabled, fold 5971 // (fsub x, x) -> 0.0 & 5972 // (fsub x, (fadd x, y)) -> (fneg y) & 5973 // (fsub x, (fadd y, x)) -> (fneg y) 5974 if (DAG.getTarget().Options.UnsafeFPMath) { 5975 if (N0 == N1) 5976 return DAG.getConstantFP(0.0f, VT); 5977 5978 if (N1.getOpcode() == ISD::FADD) { 5979 SDValue N10 = N1->getOperand(0); 5980 SDValue N11 = N1->getOperand(1); 5981 5982 if (N10 == N0 && isNegatibleForFree(N11, LegalOperations, TLI, 5983 &DAG.getTarget().Options)) 5984 return GetNegatedExpression(N11, DAG, LegalOperations); 5985 else if (N11 == N0 && isNegatibleForFree(N10, LegalOperations, TLI, 5986 &DAG.getTarget().Options)) 5987 return GetNegatedExpression(N10, DAG, LegalOperations); 5988 } 5989 } 5990 5991 // FSUB -> FMA combines: 5992 if ((DAG.getTarget().Options.AllowFPOpFusion == FPOpFusion::Fast || 5993 DAG.getTarget().Options.UnsafeFPMath) && 5994 DAG.getTarget().getTargetLowering()->isFMAFasterThanMulAndAdd(VT) && 5995 TLI.isOperationLegalOrCustom(ISD::FMA, VT)) { 5996 5997 // fold (fsub (fmul x, y), z) -> (fma x, y, (fneg z)) 5998 if (N0.getOpcode() == ISD::FMUL && N0->hasOneUse()) { 5999 return DAG.getNode(ISD::FMA, dl, VT, 6000 N0.getOperand(0), N0.getOperand(1), 6001 DAG.getNode(ISD::FNEG, dl, VT, N1)); 6002 } 6003 6004 // fold (fsub x, (fmul y, z)) -> (fma (fneg y), z, x) 6005 // Note: Commutes FSUB operands. 6006 if (N1.getOpcode() == ISD::FMUL && N1->hasOneUse()) { 6007 return DAG.getNode(ISD::FMA, dl, VT, 6008 DAG.getNode(ISD::FNEG, dl, VT, 6009 N1.getOperand(0)), 6010 N1.getOperand(1), N0); 6011 } 6012 6013 // fold (fsub (-(fmul, x, y)), z) -> (fma (fneg x), y, (fneg z)) 6014 if (N0.getOpcode() == ISD::FNEG && 6015 N0.getOperand(0).getOpcode() == ISD::FMUL && 6016 N0->hasOneUse() && N0.getOperand(0).hasOneUse()) { 6017 SDValue N00 = N0.getOperand(0).getOperand(0); 6018 SDValue N01 = N0.getOperand(0).getOperand(1); 6019 return DAG.getNode(ISD::FMA, dl, VT, 6020 DAG.getNode(ISD::FNEG, dl, VT, N00), N01, 6021 DAG.getNode(ISD::FNEG, dl, VT, N1)); 6022 } 6023 } 6024 6025 return SDValue(); 6026} 6027 6028SDValue DAGCombiner::visitFMUL(SDNode *N) { 6029 SDValue N0 = N->getOperand(0); 6030 SDValue N1 = N->getOperand(1); 6031 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6032 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 6033 EVT VT = N->getValueType(0); 6034 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 6035 6036 // fold vector ops 6037 if (VT.isVector()) { 6038 SDValue FoldedVOp = SimplifyVBinOp(N); 6039 if (FoldedVOp.getNode()) return FoldedVOp; 6040 } 6041 6042 // fold (fmul c1, c2) -> c1*c2 6043 if (N0CFP && N1CFP) 6044 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0, N1); 6045 // canonicalize constant to RHS 6046 if (N0CFP && !N1CFP) 6047 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N1, N0); 6048 // fold (fmul A, 0) -> 0 6049 if (DAG.getTarget().Options.UnsafeFPMath && 6050 N1CFP && N1CFP->getValueAPF().isZero()) 6051 return N1; 6052 // fold (fmul A, 0) -> 0, vector edition. 6053 if (DAG.getTarget().Options.UnsafeFPMath && 6054 ISD::isBuildVectorAllZeros(N1.getNode())) 6055 return N1; 6056 // fold (fmul A, 1.0) -> A 6057 if (N1CFP && N1CFP->isExactlyValue(1.0)) 6058 return N0; 6059 // fold (fmul X, 2.0) -> (fadd X, X) 6060 if (N1CFP && N1CFP->isExactlyValue(+2.0)) 6061 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N0); 6062 // fold (fmul X, -1.0) -> (fneg X) 6063 if (N1CFP && N1CFP->isExactlyValue(-1.0)) 6064 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 6065 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N0); 6066 6067 // fold (fmul (fneg X), (fneg Y)) -> (fmul X, Y) 6068 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations, TLI, 6069 &DAG.getTarget().Options)) { 6070 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations, TLI, 6071 &DAG.getTarget().Options)) { 6072 // Both can be negated for free, check to see if at least one is cheaper 6073 // negated. 6074 if (LHSNeg == 2 || RHSNeg == 2) 6075 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 6076 GetNegatedExpression(N0, DAG, LegalOperations), 6077 GetNegatedExpression(N1, DAG, LegalOperations)); 6078 } 6079 } 6080 6081 // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2)) 6082 if (DAG.getTarget().Options.UnsafeFPMath && 6083 N1CFP && N0.getOpcode() == ISD::FMUL && 6084 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 6085 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0.getOperand(0), 6086 DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 6087 N0.getOperand(1), N1)); 6088 6089 return SDValue(); 6090} 6091 6092SDValue DAGCombiner::visitFMA(SDNode *N) { 6093 SDValue N0 = N->getOperand(0); 6094 SDValue N1 = N->getOperand(1); 6095 SDValue N2 = N->getOperand(2); 6096 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6097 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 6098 EVT VT = N->getValueType(0); 6099 DebugLoc dl = N->getDebugLoc(); 6100 6101 if (DAG.getTarget().Options.UnsafeFPMath) { 6102 if (N0CFP && N0CFP->isZero()) 6103 return N2; 6104 if (N1CFP && N1CFP->isZero()) 6105 return N2; 6106 } 6107 if (N0CFP && N0CFP->isExactlyValue(1.0)) 6108 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N1, N2); 6109 if (N1CFP && N1CFP->isExactlyValue(1.0)) 6110 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N2); 6111 6112 // Canonicalize (fma c, x, y) -> (fma x, c, y) 6113 if (N0CFP && !N1CFP) 6114 return DAG.getNode(ISD::FMA, N->getDebugLoc(), VT, N1, N0, N2); 6115 6116 // (fma x, c1, (fmul x, c2)) -> (fmul x, c1+c2) 6117 if (DAG.getTarget().Options.UnsafeFPMath && N1CFP && 6118 N2.getOpcode() == ISD::FMUL && 6119 N0 == N2.getOperand(0) && 6120 N2.getOperand(1).getOpcode() == ISD::ConstantFP) { 6121 return DAG.getNode(ISD::FMUL, dl, VT, N0, 6122 DAG.getNode(ISD::FADD, dl, VT, N1, N2.getOperand(1))); 6123 } 6124 6125 6126 // (fma (fmul x, c1), c2, y) -> (fma x, c1*c2, y) 6127 if (DAG.getTarget().Options.UnsafeFPMath && 6128 N0.getOpcode() == ISD::FMUL && N1CFP && 6129 N0.getOperand(1).getOpcode() == ISD::ConstantFP) { 6130 return DAG.getNode(ISD::FMA, dl, VT, 6131 N0.getOperand(0), 6132 DAG.getNode(ISD::FMUL, dl, VT, N1, N0.getOperand(1)), 6133 N2); 6134 } 6135 6136 // (fma x, 1, y) -> (fadd x, y) 6137 // (fma x, -1, y) -> (fadd (fneg x), y) 6138 if (N1CFP) { 6139 if (N1CFP->isExactlyValue(1.0)) 6140 return DAG.getNode(ISD::FADD, dl, VT, N0, N2); 6141 6142 if (N1CFP->isExactlyValue(-1.0) && 6143 (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))) { 6144 SDValue RHSNeg = DAG.getNode(ISD::FNEG, dl, VT, N0); 6145 AddToWorkList(RHSNeg.getNode()); 6146 return DAG.getNode(ISD::FADD, dl, VT, N2, RHSNeg); 6147 } 6148 } 6149 6150 // (fma x, c, x) -> (fmul x, (c+1)) 6151 if (DAG.getTarget().Options.UnsafeFPMath && N1CFP && N0 == N2) { 6152 return DAG.getNode(ISD::FMUL, dl, VT, 6153 N0, 6154 DAG.getNode(ISD::FADD, dl, VT, 6155 N1, DAG.getConstantFP(1.0, VT))); 6156 } 6157 6158 // (fma x, c, (fneg x)) -> (fmul x, (c-1)) 6159 if (DAG.getTarget().Options.UnsafeFPMath && N1CFP && 6160 N2.getOpcode() == ISD::FNEG && N2.getOperand(0) == N0) { 6161 return DAG.getNode(ISD::FMUL, dl, VT, 6162 N0, 6163 DAG.getNode(ISD::FADD, dl, VT, 6164 N1, DAG.getConstantFP(-1.0, VT))); 6165 } 6166 6167 6168 return SDValue(); 6169} 6170 6171SDValue DAGCombiner::visitFDIV(SDNode *N) { 6172 SDValue N0 = N->getOperand(0); 6173 SDValue N1 = N->getOperand(1); 6174 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6175 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 6176 EVT VT = N->getValueType(0); 6177 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 6178 6179 // fold vector ops 6180 if (VT.isVector()) { 6181 SDValue FoldedVOp = SimplifyVBinOp(N); 6182 if (FoldedVOp.getNode()) return FoldedVOp; 6183 } 6184 6185 // fold (fdiv c1, c2) -> c1/c2 6186 if (N0CFP && N1CFP) 6187 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, N0, N1); 6188 6189 // fold (fdiv X, c2) -> fmul X, 1/c2 if losing precision is acceptable. 6190 if (N1CFP && DAG.getTarget().Options.UnsafeFPMath) { 6191 // Compute the reciprocal 1.0 / c2. 6192 APFloat N1APF = N1CFP->getValueAPF(); 6193 APFloat Recip(N1APF.getSemantics(), 1); // 1.0 6194 APFloat::opStatus st = Recip.divide(N1APF, APFloat::rmNearestTiesToEven); 6195 // Only do the transform if the reciprocal is a legal fp immediate that 6196 // isn't too nasty (eg NaN, denormal, ...). 6197 if ((st == APFloat::opOK || st == APFloat::opInexact) && // Not too nasty 6198 (!LegalOperations || 6199 // FIXME: custom lowering of ConstantFP might fail (see e.g. ARM 6200 // backend)... we should handle this gracefully after Legalize. 6201 // TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT) || 6202 TLI.isOperationLegal(llvm::ISD::ConstantFP, VT) || 6203 TLI.isFPImmLegal(Recip, VT))) 6204 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0, 6205 DAG.getConstantFP(Recip, VT)); 6206 } 6207 6208 // (fdiv (fneg X), (fneg Y)) -> (fdiv X, Y) 6209 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations, TLI, 6210 &DAG.getTarget().Options)) { 6211 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations, TLI, 6212 &DAG.getTarget().Options)) { 6213 // Both can be negated for free, check to see if at least one is cheaper 6214 // negated. 6215 if (LHSNeg == 2 || RHSNeg == 2) 6216 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, 6217 GetNegatedExpression(N0, DAG, LegalOperations), 6218 GetNegatedExpression(N1, DAG, LegalOperations)); 6219 } 6220 } 6221 6222 return SDValue(); 6223} 6224 6225SDValue DAGCombiner::visitFREM(SDNode *N) { 6226 SDValue N0 = N->getOperand(0); 6227 SDValue N1 = N->getOperand(1); 6228 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6229 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 6230 EVT VT = N->getValueType(0); 6231 6232 // fold (frem c1, c2) -> fmod(c1,c2) 6233 if (N0CFP && N1CFP) 6234 return DAG.getNode(ISD::FREM, N->getDebugLoc(), VT, N0, N1); 6235 6236 return SDValue(); 6237} 6238 6239SDValue DAGCombiner::visitFCOPYSIGN(SDNode *N) { 6240 SDValue N0 = N->getOperand(0); 6241 SDValue N1 = N->getOperand(1); 6242 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6243 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 6244 EVT VT = N->getValueType(0); 6245 6246 if (N0CFP && N1CFP) // Constant fold 6247 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, N0, N1); 6248 6249 if (N1CFP) { 6250 const APFloat& V = N1CFP->getValueAPF(); 6251 // copysign(x, c1) -> fabs(x) iff ispos(c1) 6252 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1) 6253 if (!V.isNegative()) { 6254 if (!LegalOperations || TLI.isOperationLegal(ISD::FABS, VT)) 6255 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 6256 } else { 6257 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 6258 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, 6259 DAG.getNode(ISD::FABS, N0.getDebugLoc(), VT, N0)); 6260 } 6261 } 6262 6263 // copysign(fabs(x), y) -> copysign(x, y) 6264 // copysign(fneg(x), y) -> copysign(x, y) 6265 // copysign(copysign(x,z), y) -> copysign(x, y) 6266 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG || 6267 N0.getOpcode() == ISD::FCOPYSIGN) 6268 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 6269 N0.getOperand(0), N1); 6270 6271 // copysign(x, abs(y)) -> abs(x) 6272 if (N1.getOpcode() == ISD::FABS) 6273 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 6274 6275 // copysign(x, copysign(y,z)) -> copysign(x, z) 6276 if (N1.getOpcode() == ISD::FCOPYSIGN) 6277 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 6278 N0, N1.getOperand(1)); 6279 6280 // copysign(x, fp_extend(y)) -> copysign(x, y) 6281 // copysign(x, fp_round(y)) -> copysign(x, y) 6282 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND) 6283 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 6284 N0, N1.getOperand(0)); 6285 6286 return SDValue(); 6287} 6288 6289SDValue DAGCombiner::visitSINT_TO_FP(SDNode *N) { 6290 SDValue N0 = N->getOperand(0); 6291 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 6292 EVT VT = N->getValueType(0); 6293 EVT OpVT = N0.getValueType(); 6294 6295 // fold (sint_to_fp c1) -> c1fp 6296 if (N0C && 6297 // ...but only if the target supports immediate floating-point values 6298 (!LegalOperations || 6299 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT))) 6300 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0); 6301 6302 // If the input is a legal type, and SINT_TO_FP is not legal on this target, 6303 // but UINT_TO_FP is legal on this target, try to convert. 6304 if (!TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT) && 6305 TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT)) { 6306 // If the sign bit is known to be zero, we can change this to UINT_TO_FP. 6307 if (DAG.SignBitIsZero(N0)) 6308 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0); 6309 } 6310 6311 // The next optimizations are desireable only if SELECT_CC can be lowered. 6312 // Check against MVT::Other for SELECT_CC, which is a workaround for targets 6313 // having to say they don't support SELECT_CC on every type the DAG knows 6314 // about, since there is no way to mark an opcode illegal at all value types 6315 // (See also visitSELECT) 6316 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other)) { 6317 // fold (sint_to_fp (setcc x, y, cc)) -> (select_cc x, y, -1.0, 0.0,, cc) 6318 if (N0.getOpcode() == ISD::SETCC && N0.getValueType() == MVT::i1 && 6319 !VT.isVector() && 6320 (!LegalOperations || 6321 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT))) { 6322 SDValue Ops[] = 6323 { N0.getOperand(0), N0.getOperand(1), 6324 DAG.getConstantFP(-1.0, VT) , DAG.getConstantFP(0.0, VT), 6325 N0.getOperand(2) }; 6326 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT, Ops, 5); 6327 } 6328 6329 // fold (sint_to_fp (zext (setcc x, y, cc))) -> 6330 // (select_cc x, y, 1.0, 0.0,, cc) 6331 if (N0.getOpcode() == ISD::ZERO_EXTEND && 6332 N0.getOperand(0).getOpcode() == ISD::SETCC &&!VT.isVector() && 6333 (!LegalOperations || 6334 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT))) { 6335 SDValue Ops[] = 6336 { N0.getOperand(0).getOperand(0), N0.getOperand(0).getOperand(1), 6337 DAG.getConstantFP(1.0, VT) , DAG.getConstantFP(0.0, VT), 6338 N0.getOperand(0).getOperand(2) }; 6339 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT, Ops, 5); 6340 } 6341 } 6342 6343 return SDValue(); 6344} 6345 6346SDValue DAGCombiner::visitUINT_TO_FP(SDNode *N) { 6347 SDValue N0 = N->getOperand(0); 6348 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 6349 EVT VT = N->getValueType(0); 6350 EVT OpVT = N0.getValueType(); 6351 6352 // fold (uint_to_fp c1) -> c1fp 6353 if (N0C && 6354 // ...but only if the target supports immediate floating-point values 6355 (!LegalOperations || 6356 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT))) 6357 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0); 6358 6359 // If the input is a legal type, and UINT_TO_FP is not legal on this target, 6360 // but SINT_TO_FP is legal on this target, try to convert. 6361 if (!TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT) && 6362 TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT)) { 6363 // If the sign bit is known to be zero, we can change this to SINT_TO_FP. 6364 if (DAG.SignBitIsZero(N0)) 6365 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0); 6366 } 6367 6368 // The next optimizations are desireable only if SELECT_CC can be lowered. 6369 // Check against MVT::Other for SELECT_CC, which is a workaround for targets 6370 // having to say they don't support SELECT_CC on every type the DAG knows 6371 // about, since there is no way to mark an opcode illegal at all value types 6372 // (See also visitSELECT) 6373 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other)) { 6374 // fold (uint_to_fp (setcc x, y, cc)) -> (select_cc x, y, -1.0, 0.0,, cc) 6375 6376 if (N0.getOpcode() == ISD::SETCC && !VT.isVector() && 6377 (!LegalOperations || 6378 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT))) { 6379 SDValue Ops[] = 6380 { N0.getOperand(0), N0.getOperand(1), 6381 DAG.getConstantFP(1.0, VT), DAG.getConstantFP(0.0, VT), 6382 N0.getOperand(2) }; 6383 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT, Ops, 5); 6384 } 6385 } 6386 6387 return SDValue(); 6388} 6389 6390SDValue DAGCombiner::visitFP_TO_SINT(SDNode *N) { 6391 SDValue N0 = N->getOperand(0); 6392 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6393 EVT VT = N->getValueType(0); 6394 6395 // fold (fp_to_sint c1fp) -> c1 6396 if (N0CFP) 6397 return DAG.getNode(ISD::FP_TO_SINT, N->getDebugLoc(), VT, N0); 6398 6399 return SDValue(); 6400} 6401 6402SDValue DAGCombiner::visitFP_TO_UINT(SDNode *N) { 6403 SDValue N0 = N->getOperand(0); 6404 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6405 EVT VT = N->getValueType(0); 6406 6407 // fold (fp_to_uint c1fp) -> c1 6408 if (N0CFP) 6409 return DAG.getNode(ISD::FP_TO_UINT, N->getDebugLoc(), VT, N0); 6410 6411 return SDValue(); 6412} 6413 6414SDValue DAGCombiner::visitFP_ROUND(SDNode *N) { 6415 SDValue N0 = N->getOperand(0); 6416 SDValue N1 = N->getOperand(1); 6417 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6418 EVT VT = N->getValueType(0); 6419 6420 // fold (fp_round c1fp) -> c1fp 6421 if (N0CFP) 6422 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0, N1); 6423 6424 // fold (fp_round (fp_extend x)) -> x 6425 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType()) 6426 return N0.getOperand(0); 6427 6428 // fold (fp_round (fp_round x)) -> (fp_round x) 6429 if (N0.getOpcode() == ISD::FP_ROUND) { 6430 // This is a value preserving truncation if both round's are. 6431 bool IsTrunc = N->getConstantOperandVal(1) == 1 && 6432 N0.getNode()->getConstantOperandVal(1) == 1; 6433 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0.getOperand(0), 6434 DAG.getIntPtrConstant(IsTrunc)); 6435 } 6436 6437 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y) 6438 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse()) { 6439 SDValue Tmp = DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(), VT, 6440 N0.getOperand(0), N1); 6441 AddToWorkList(Tmp.getNode()); 6442 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 6443 Tmp, N0.getOperand(1)); 6444 } 6445 6446 return SDValue(); 6447} 6448 6449SDValue DAGCombiner::visitFP_ROUND_INREG(SDNode *N) { 6450 SDValue N0 = N->getOperand(0); 6451 EVT VT = N->getValueType(0); 6452 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 6453 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6454 6455 // fold (fp_round_inreg c1fp) -> c1fp 6456 if (N0CFP && isTypeLegal(EVT)) { 6457 SDValue Round = DAG.getConstantFP(*N0CFP->getConstantFPValue(), EVT); 6458 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, Round); 6459 } 6460 6461 return SDValue(); 6462} 6463 6464SDValue DAGCombiner::visitFP_EXTEND(SDNode *N) { 6465 SDValue N0 = N->getOperand(0); 6466 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6467 EVT VT = N->getValueType(0); 6468 6469 // If this is fp_round(fpextend), don't fold it, allow ourselves to be folded. 6470 if (N->hasOneUse() && 6471 N->use_begin()->getOpcode() == ISD::FP_ROUND) 6472 return SDValue(); 6473 6474 // fold (fp_extend c1fp) -> c1fp 6475 if (N0CFP) 6476 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, N0); 6477 6478 // Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't affect the 6479 // value of X. 6480 if (N0.getOpcode() == ISD::FP_ROUND 6481 && N0.getNode()->getConstantOperandVal(1) == 1) { 6482 SDValue In = N0.getOperand(0); 6483 if (In.getValueType() == VT) return In; 6484 if (VT.bitsLT(In.getValueType())) 6485 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, 6486 In, N0.getOperand(1)); 6487 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, In); 6488 } 6489 6490 // fold (fpext (load x)) -> (fpext (fptrunc (extload x))) 6491 if (ISD::isNON_EXTLoad(N0.getNode()) && N0.hasOneUse() && 6492 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 6493 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) { 6494 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 6495 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT, 6496 LN0->getChain(), 6497 LN0->getBasePtr(), LN0->getPointerInfo(), 6498 N0.getValueType(), 6499 LN0->isVolatile(), LN0->isNonTemporal(), 6500 LN0->getAlignment()); 6501 CombineTo(N, ExtLoad); 6502 CombineTo(N0.getNode(), 6503 DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(), 6504 N0.getValueType(), ExtLoad, DAG.getIntPtrConstant(1)), 6505 ExtLoad.getValue(1)); 6506 return SDValue(N, 0); // Return N so it doesn't get rechecked! 6507 } 6508 6509 return SDValue(); 6510} 6511 6512SDValue DAGCombiner::visitFNEG(SDNode *N) { 6513 SDValue N0 = N->getOperand(0); 6514 EVT VT = N->getValueType(0); 6515 6516 if (VT.isVector()) { 6517 SDValue FoldedVOp = SimplifyVUnaryOp(N); 6518 if (FoldedVOp.getNode()) return FoldedVOp; 6519 } 6520 6521 if (isNegatibleForFree(N0, LegalOperations, DAG.getTargetLoweringInfo(), 6522 &DAG.getTarget().Options)) 6523 return GetNegatedExpression(N0, DAG, LegalOperations); 6524 6525 // Transform fneg(bitconvert(x)) -> bitconvert(x^sign) to avoid loading 6526 // constant pool values. 6527 if (!TLI.isFNegFree(VT) && N0.getOpcode() == ISD::BITCAST && 6528 !VT.isVector() && 6529 N0.getNode()->hasOneUse() && 6530 N0.getOperand(0).getValueType().isInteger()) { 6531 SDValue Int = N0.getOperand(0); 6532 EVT IntVT = Int.getValueType(); 6533 if (IntVT.isInteger() && !IntVT.isVector()) { 6534 Int = DAG.getNode(ISD::XOR, N0.getDebugLoc(), IntVT, Int, 6535 DAG.getConstant(APInt::getSignBit(IntVT.getSizeInBits()), IntVT)); 6536 AddToWorkList(Int.getNode()); 6537 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), 6538 VT, Int); 6539 } 6540 } 6541 6542 // (fneg (fmul c, x)) -> (fmul -c, x) 6543 if (N0.getOpcode() == ISD::FMUL) { 6544 ConstantFPSDNode *CFP1 = dyn_cast<ConstantFPSDNode>(N0.getOperand(1)); 6545 if (CFP1) { 6546 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 6547 N0.getOperand(0), 6548 DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, 6549 N0.getOperand(1))); 6550 } 6551 } 6552 6553 return SDValue(); 6554} 6555 6556SDValue DAGCombiner::visitFCEIL(SDNode *N) { 6557 SDValue N0 = N->getOperand(0); 6558 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6559 EVT VT = N->getValueType(0); 6560 6561 // fold (fceil c1) -> fceil(c1) 6562 if (N0CFP) 6563 return DAG.getNode(ISD::FCEIL, N->getDebugLoc(), VT, N0); 6564 6565 return SDValue(); 6566} 6567 6568SDValue DAGCombiner::visitFTRUNC(SDNode *N) { 6569 SDValue N0 = N->getOperand(0); 6570 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6571 EVT VT = N->getValueType(0); 6572 6573 // fold (ftrunc c1) -> ftrunc(c1) 6574 if (N0CFP) 6575 return DAG.getNode(ISD::FTRUNC, N->getDebugLoc(), VT, N0); 6576 6577 return SDValue(); 6578} 6579 6580SDValue DAGCombiner::visitFFLOOR(SDNode *N) { 6581 SDValue N0 = N->getOperand(0); 6582 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6583 EVT VT = N->getValueType(0); 6584 6585 // fold (ffloor c1) -> ffloor(c1) 6586 if (N0CFP) 6587 return DAG.getNode(ISD::FFLOOR, N->getDebugLoc(), VT, N0); 6588 6589 return SDValue(); 6590} 6591 6592SDValue DAGCombiner::visitFABS(SDNode *N) { 6593 SDValue N0 = N->getOperand(0); 6594 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6595 EVT VT = N->getValueType(0); 6596 6597 if (VT.isVector()) { 6598 SDValue FoldedVOp = SimplifyVUnaryOp(N); 6599 if (FoldedVOp.getNode()) return FoldedVOp; 6600 } 6601 6602 // fold (fabs c1) -> fabs(c1) 6603 if (N0CFP) 6604 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 6605 // fold (fabs (fabs x)) -> (fabs x) 6606 if (N0.getOpcode() == ISD::FABS) 6607 return N->getOperand(0); 6608 // fold (fabs (fneg x)) -> (fabs x) 6609 // fold (fabs (fcopysign x, y)) -> (fabs x) 6610 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN) 6611 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0.getOperand(0)); 6612 6613 // Transform fabs(bitconvert(x)) -> bitconvert(x&~sign) to avoid loading 6614 // constant pool values. 6615 if (!TLI.isFAbsFree(VT) && 6616 N0.getOpcode() == ISD::BITCAST && N0.getNode()->hasOneUse() && 6617 N0.getOperand(0).getValueType().isInteger() && 6618 !N0.getOperand(0).getValueType().isVector()) { 6619 SDValue Int = N0.getOperand(0); 6620 EVT IntVT = Int.getValueType(); 6621 if (IntVT.isInteger() && !IntVT.isVector()) { 6622 Int = DAG.getNode(ISD::AND, N0.getDebugLoc(), IntVT, Int, 6623 DAG.getConstant(~APInt::getSignBit(IntVT.getSizeInBits()), IntVT)); 6624 AddToWorkList(Int.getNode()); 6625 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), 6626 N->getValueType(0), Int); 6627 } 6628 } 6629 6630 return SDValue(); 6631} 6632 6633SDValue DAGCombiner::visitBRCOND(SDNode *N) { 6634 SDValue Chain = N->getOperand(0); 6635 SDValue N1 = N->getOperand(1); 6636 SDValue N2 = N->getOperand(2); 6637 6638 // If N is a constant we could fold this into a fallthrough or unconditional 6639 // branch. However that doesn't happen very often in normal code, because 6640 // Instcombine/SimplifyCFG should have handled the available opportunities. 6641 // If we did this folding here, it would be necessary to update the 6642 // MachineBasicBlock CFG, which is awkward. 6643 6644 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal 6645 // on the target. 6646 if (N1.getOpcode() == ISD::SETCC && 6647 TLI.isOperationLegalOrCustom(ISD::BR_CC, MVT::Other)) { 6648 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other, 6649 Chain, N1.getOperand(2), 6650 N1.getOperand(0), N1.getOperand(1), N2); 6651 } 6652 6653 if ((N1.hasOneUse() && N1.getOpcode() == ISD::SRL) || 6654 ((N1.getOpcode() == ISD::TRUNCATE && N1.hasOneUse()) && 6655 (N1.getOperand(0).hasOneUse() && 6656 N1.getOperand(0).getOpcode() == ISD::SRL))) { 6657 SDNode *Trunc = 0; 6658 if (N1.getOpcode() == ISD::TRUNCATE) { 6659 // Look pass the truncate. 6660 Trunc = N1.getNode(); 6661 N1 = N1.getOperand(0); 6662 } 6663 6664 // Match this pattern so that we can generate simpler code: 6665 // 6666 // %a = ... 6667 // %b = and i32 %a, 2 6668 // %c = srl i32 %b, 1 6669 // brcond i32 %c ... 6670 // 6671 // into 6672 // 6673 // %a = ... 6674 // %b = and i32 %a, 2 6675 // %c = setcc eq %b, 0 6676 // brcond %c ... 6677 // 6678 // This applies only when the AND constant value has one bit set and the 6679 // SRL constant is equal to the log2 of the AND constant. The back-end is 6680 // smart enough to convert the result into a TEST/JMP sequence. 6681 SDValue Op0 = N1.getOperand(0); 6682 SDValue Op1 = N1.getOperand(1); 6683 6684 if (Op0.getOpcode() == ISD::AND && 6685 Op1.getOpcode() == ISD::Constant) { 6686 SDValue AndOp1 = Op0.getOperand(1); 6687 6688 if (AndOp1.getOpcode() == ISD::Constant) { 6689 const APInt &AndConst = cast<ConstantSDNode>(AndOp1)->getAPIntValue(); 6690 6691 if (AndConst.isPowerOf2() && 6692 cast<ConstantSDNode>(Op1)->getAPIntValue()==AndConst.logBase2()) { 6693 SDValue SetCC = 6694 DAG.getSetCC(N->getDebugLoc(), 6695 TLI.getSetCCResultType(Op0.getValueType()), 6696 Op0, DAG.getConstant(0, Op0.getValueType()), 6697 ISD::SETNE); 6698 6699 SDValue NewBRCond = DAG.getNode(ISD::BRCOND, N->getDebugLoc(), 6700 MVT::Other, Chain, SetCC, N2); 6701 // Don't add the new BRCond into the worklist or else SimplifySelectCC 6702 // will convert it back to (X & C1) >> C2. 6703 CombineTo(N, NewBRCond, false); 6704 // Truncate is dead. 6705 if (Trunc) { 6706 removeFromWorkList(Trunc); 6707 DAG.DeleteNode(Trunc); 6708 } 6709 // Replace the uses of SRL with SETCC 6710 WorkListRemover DeadNodes(*this); 6711 DAG.ReplaceAllUsesOfValueWith(N1, SetCC); 6712 removeFromWorkList(N1.getNode()); 6713 DAG.DeleteNode(N1.getNode()); 6714 return SDValue(N, 0); // Return N so it doesn't get rechecked! 6715 } 6716 } 6717 } 6718 6719 if (Trunc) 6720 // Restore N1 if the above transformation doesn't match. 6721 N1 = N->getOperand(1); 6722 } 6723 6724 // Transform br(xor(x, y)) -> br(x != y) 6725 // Transform br(xor(xor(x,y), 1)) -> br (x == y) 6726 if (N1.hasOneUse() && N1.getOpcode() == ISD::XOR) { 6727 SDNode *TheXor = N1.getNode(); 6728 SDValue Op0 = TheXor->getOperand(0); 6729 SDValue Op1 = TheXor->getOperand(1); 6730 if (Op0.getOpcode() == Op1.getOpcode()) { 6731 // Avoid missing important xor optimizations. 6732 SDValue Tmp = visitXOR(TheXor); 6733 if (Tmp.getNode() && Tmp.getNode() != TheXor) { 6734 DEBUG(dbgs() << "\nReplacing.8 "; 6735 TheXor->dump(&DAG); 6736 dbgs() << "\nWith: "; 6737 Tmp.getNode()->dump(&DAG); 6738 dbgs() << '\n'); 6739 WorkListRemover DeadNodes(*this); 6740 DAG.ReplaceAllUsesOfValueWith(N1, Tmp); 6741 removeFromWorkList(TheXor); 6742 DAG.DeleteNode(TheXor); 6743 return DAG.getNode(ISD::BRCOND, N->getDebugLoc(), 6744 MVT::Other, Chain, Tmp, N2); 6745 } 6746 } 6747 6748 if (Op0.getOpcode() != ISD::SETCC && Op1.getOpcode() != ISD::SETCC) { 6749 bool Equal = false; 6750 if (ConstantSDNode *RHSCI = dyn_cast<ConstantSDNode>(Op0)) 6751 if (RHSCI->getAPIntValue() == 1 && Op0.hasOneUse() && 6752 Op0.getOpcode() == ISD::XOR) { 6753 TheXor = Op0.getNode(); 6754 Equal = true; 6755 } 6756 6757 EVT SetCCVT = N1.getValueType(); 6758 if (LegalTypes) 6759 SetCCVT = TLI.getSetCCResultType(SetCCVT); 6760 SDValue SetCC = DAG.getSetCC(TheXor->getDebugLoc(), 6761 SetCCVT, 6762 Op0, Op1, 6763 Equal ? ISD::SETEQ : ISD::SETNE); 6764 // Replace the uses of XOR with SETCC 6765 WorkListRemover DeadNodes(*this); 6766 DAG.ReplaceAllUsesOfValueWith(N1, SetCC); 6767 removeFromWorkList(N1.getNode()); 6768 DAG.DeleteNode(N1.getNode()); 6769 return DAG.getNode(ISD::BRCOND, N->getDebugLoc(), 6770 MVT::Other, Chain, SetCC, N2); 6771 } 6772 } 6773 6774 return SDValue(); 6775} 6776 6777// Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB. 6778// 6779SDValue DAGCombiner::visitBR_CC(SDNode *N) { 6780 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1)); 6781 SDValue CondLHS = N->getOperand(2), CondRHS = N->getOperand(3); 6782 6783 // If N is a constant we could fold this into a fallthrough or unconditional 6784 // branch. However that doesn't happen very often in normal code, because 6785 // Instcombine/SimplifyCFG should have handled the available opportunities. 6786 // If we did this folding here, it would be necessary to update the 6787 // MachineBasicBlock CFG, which is awkward. 6788 6789 // Use SimplifySetCC to simplify SETCC's. 6790 SDValue Simp = SimplifySetCC(TLI.getSetCCResultType(CondLHS.getValueType()), 6791 CondLHS, CondRHS, CC->get(), N->getDebugLoc(), 6792 false); 6793 if (Simp.getNode()) AddToWorkList(Simp.getNode()); 6794 6795 // fold to a simpler setcc 6796 if (Simp.getNode() && Simp.getOpcode() == ISD::SETCC) 6797 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other, 6798 N->getOperand(0), Simp.getOperand(2), 6799 Simp.getOperand(0), Simp.getOperand(1), 6800 N->getOperand(4)); 6801 6802 return SDValue(); 6803} 6804 6805/// canFoldInAddressingMode - Return true if 'Use' is a load or a store that 6806/// uses N as its base pointer and that N may be folded in the load / store 6807/// addressing mode. 6808static bool canFoldInAddressingMode(SDNode *N, SDNode *Use, 6809 SelectionDAG &DAG, 6810 const TargetLowering &TLI) { 6811 EVT VT; 6812 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Use)) { 6813 if (LD->isIndexed() || LD->getBasePtr().getNode() != N) 6814 return false; 6815 VT = Use->getValueType(0); 6816 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(Use)) { 6817 if (ST->isIndexed() || ST->getBasePtr().getNode() != N) 6818 return false; 6819 VT = ST->getValue().getValueType(); 6820 } else 6821 return false; 6822 6823 AddrMode AM; 6824 if (N->getOpcode() == ISD::ADD) { 6825 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1)); 6826 if (Offset) 6827 // [reg +/- imm] 6828 AM.BaseOffs = Offset->getSExtValue(); 6829 else 6830 // [reg +/- reg] 6831 AM.Scale = 1; 6832 } else if (N->getOpcode() == ISD::SUB) { 6833 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1)); 6834 if (Offset) 6835 // [reg +/- imm] 6836 AM.BaseOffs = -Offset->getSExtValue(); 6837 else 6838 // [reg +/- reg] 6839 AM.Scale = 1; 6840 } else 6841 return false; 6842 6843 return TLI.isLegalAddressingMode(AM, VT.getTypeForEVT(*DAG.getContext())); 6844} 6845 6846/// CombineToPreIndexedLoadStore - Try turning a load / store into a 6847/// pre-indexed load / store when the base pointer is an add or subtract 6848/// and it has other uses besides the load / store. After the 6849/// transformation, the new indexed load / store has effectively folded 6850/// the add / subtract in and all of its other uses are redirected to the 6851/// new load / store. 6852bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) { 6853 if (Level < AfterLegalizeDAG) 6854 return false; 6855 6856 bool isLoad = true; 6857 SDValue Ptr; 6858 EVT VT; 6859 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 6860 if (LD->isIndexed()) 6861 return false; 6862 VT = LD->getMemoryVT(); 6863 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) && 6864 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT)) 6865 return false; 6866 Ptr = LD->getBasePtr(); 6867 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 6868 if (ST->isIndexed()) 6869 return false; 6870 VT = ST->getMemoryVT(); 6871 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) && 6872 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT)) 6873 return false; 6874 Ptr = ST->getBasePtr(); 6875 isLoad = false; 6876 } else { 6877 return false; 6878 } 6879 6880 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail 6881 // out. There is no reason to make this a preinc/predec. 6882 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) || 6883 Ptr.getNode()->hasOneUse()) 6884 return false; 6885 6886 // Ask the target to do addressing mode selection. 6887 SDValue BasePtr; 6888 SDValue Offset; 6889 ISD::MemIndexedMode AM = ISD::UNINDEXED; 6890 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG)) 6891 return false; 6892 // Don't create a indexed load / store with zero offset. 6893 if (isa<ConstantSDNode>(Offset) && 6894 cast<ConstantSDNode>(Offset)->isNullValue()) 6895 return false; 6896 6897 // Try turning it into a pre-indexed load / store except when: 6898 // 1) The new base ptr is a frame index. 6899 // 2) If N is a store and the new base ptr is either the same as or is a 6900 // predecessor of the value being stored. 6901 // 3) Another use of old base ptr is a predecessor of N. If ptr is folded 6902 // that would create a cycle. 6903 // 4) All uses are load / store ops that use it as old base ptr. 6904 6905 // Check #1. Preinc'ing a frame index would require copying the stack pointer 6906 // (plus the implicit offset) to a register to preinc anyway. 6907 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr)) 6908 return false; 6909 6910 // Check #2. 6911 if (!isLoad) { 6912 SDValue Val = cast<StoreSDNode>(N)->getValue(); 6913 if (Val == BasePtr || BasePtr.getNode()->isPredecessorOf(Val.getNode())) 6914 return false; 6915 } 6916 6917 // Now check for #3 and #4. 6918 bool RealUse = false; 6919 6920 // Caches for hasPredecessorHelper 6921 SmallPtrSet<const SDNode *, 32> Visited; 6922 SmallVector<const SDNode *, 16> Worklist; 6923 6924 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(), 6925 E = Ptr.getNode()->use_end(); I != E; ++I) { 6926 SDNode *Use = *I; 6927 if (Use == N) 6928 continue; 6929 if (N->hasPredecessorHelper(Use, Visited, Worklist)) 6930 return false; 6931 6932 // If Ptr may be folded in addressing mode of other use, then it's 6933 // not profitable to do this transformation. 6934 if (!canFoldInAddressingMode(Ptr.getNode(), Use, DAG, TLI)) 6935 RealUse = true; 6936 } 6937 6938 if (!RealUse) 6939 return false; 6940 6941 SDValue Result; 6942 if (isLoad) 6943 Result = DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(), 6944 BasePtr, Offset, AM); 6945 else 6946 Result = DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(), 6947 BasePtr, Offset, AM); 6948 ++PreIndexedNodes; 6949 ++NodesCombined; 6950 DEBUG(dbgs() << "\nReplacing.4 "; 6951 N->dump(&DAG); 6952 dbgs() << "\nWith: "; 6953 Result.getNode()->dump(&DAG); 6954 dbgs() << '\n'); 6955 WorkListRemover DeadNodes(*this); 6956 if (isLoad) { 6957 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0)); 6958 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2)); 6959 } else { 6960 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1)); 6961 } 6962 6963 // Finally, since the node is now dead, remove it from the graph. 6964 DAG.DeleteNode(N); 6965 6966 // Replace the uses of Ptr with uses of the updated base value. 6967 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0)); 6968 removeFromWorkList(Ptr.getNode()); 6969 DAG.DeleteNode(Ptr.getNode()); 6970 6971 return true; 6972} 6973 6974/// CombineToPostIndexedLoadStore - Try to combine a load / store with a 6975/// add / sub of the base pointer node into a post-indexed load / store. 6976/// The transformation folded the add / subtract into the new indexed 6977/// load / store effectively and all of its uses are redirected to the 6978/// new load / store. 6979bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) { 6980 if (Level < AfterLegalizeDAG) 6981 return false; 6982 6983 bool isLoad = true; 6984 SDValue Ptr; 6985 EVT VT; 6986 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 6987 if (LD->isIndexed()) 6988 return false; 6989 VT = LD->getMemoryVT(); 6990 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) && 6991 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT)) 6992 return false; 6993 Ptr = LD->getBasePtr(); 6994 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 6995 if (ST->isIndexed()) 6996 return false; 6997 VT = ST->getMemoryVT(); 6998 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) && 6999 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT)) 7000 return false; 7001 Ptr = ST->getBasePtr(); 7002 isLoad = false; 7003 } else { 7004 return false; 7005 } 7006 7007 if (Ptr.getNode()->hasOneUse()) 7008 return false; 7009 7010 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(), 7011 E = Ptr.getNode()->use_end(); I != E; ++I) { 7012 SDNode *Op = *I; 7013 if (Op == N || 7014 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB)) 7015 continue; 7016 7017 SDValue BasePtr; 7018 SDValue Offset; 7019 ISD::MemIndexedMode AM = ISD::UNINDEXED; 7020 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) { 7021 // Don't create a indexed load / store with zero offset. 7022 if (isa<ConstantSDNode>(Offset) && 7023 cast<ConstantSDNode>(Offset)->isNullValue()) 7024 continue; 7025 7026 // Try turning it into a post-indexed load / store except when 7027 // 1) All uses are load / store ops that use it as base ptr (and 7028 // it may be folded as addressing mmode). 7029 // 2) Op must be independent of N, i.e. Op is neither a predecessor 7030 // nor a successor of N. Otherwise, if Op is folded that would 7031 // create a cycle. 7032 7033 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr)) 7034 continue; 7035 7036 // Check for #1. 7037 bool TryNext = false; 7038 for (SDNode::use_iterator II = BasePtr.getNode()->use_begin(), 7039 EE = BasePtr.getNode()->use_end(); II != EE; ++II) { 7040 SDNode *Use = *II; 7041 if (Use == Ptr.getNode()) 7042 continue; 7043 7044 // If all the uses are load / store addresses, then don't do the 7045 // transformation. 7046 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){ 7047 bool RealUse = false; 7048 for (SDNode::use_iterator III = Use->use_begin(), 7049 EEE = Use->use_end(); III != EEE; ++III) { 7050 SDNode *UseUse = *III; 7051 if (!canFoldInAddressingMode(Use, UseUse, DAG, TLI)) 7052 RealUse = true; 7053 } 7054 7055 if (!RealUse) { 7056 TryNext = true; 7057 break; 7058 } 7059 } 7060 } 7061 7062 if (TryNext) 7063 continue; 7064 7065 // Check for #2 7066 if (!Op->isPredecessorOf(N) && !N->isPredecessorOf(Op)) { 7067 SDValue Result = isLoad 7068 ? DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(), 7069 BasePtr, Offset, AM) 7070 : DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(), 7071 BasePtr, Offset, AM); 7072 ++PostIndexedNodes; 7073 ++NodesCombined; 7074 DEBUG(dbgs() << "\nReplacing.5 "; 7075 N->dump(&DAG); 7076 dbgs() << "\nWith: "; 7077 Result.getNode()->dump(&DAG); 7078 dbgs() << '\n'); 7079 WorkListRemover DeadNodes(*this); 7080 if (isLoad) { 7081 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0)); 7082 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2)); 7083 } else { 7084 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1)); 7085 } 7086 7087 // Finally, since the node is now dead, remove it from the graph. 7088 DAG.DeleteNode(N); 7089 7090 // Replace the uses of Use with uses of the updated base value. 7091 DAG.ReplaceAllUsesOfValueWith(SDValue(Op, 0), 7092 Result.getValue(isLoad ? 1 : 0)); 7093 removeFromWorkList(Op); 7094 DAG.DeleteNode(Op); 7095 return true; 7096 } 7097 } 7098 } 7099 7100 return false; 7101} 7102 7103SDValue DAGCombiner::visitLOAD(SDNode *N) { 7104 LoadSDNode *LD = cast<LoadSDNode>(N); 7105 SDValue Chain = LD->getChain(); 7106 SDValue Ptr = LD->getBasePtr(); 7107 7108 // If load is not volatile and there are no uses of the loaded value (and 7109 // the updated indexed value in case of indexed loads), change uses of the 7110 // chain value into uses of the chain input (i.e. delete the dead load). 7111 if (!LD->isVolatile()) { 7112 if (N->getValueType(1) == MVT::Other) { 7113 // Unindexed loads. 7114 if (!N->hasAnyUseOfValue(0)) { 7115 // It's not safe to use the two value CombineTo variant here. e.g. 7116 // v1, chain2 = load chain1, loc 7117 // v2, chain3 = load chain2, loc 7118 // v3 = add v2, c 7119 // Now we replace use of chain2 with chain1. This makes the second load 7120 // isomorphic to the one we are deleting, and thus makes this load live. 7121 DEBUG(dbgs() << "\nReplacing.6 "; 7122 N->dump(&DAG); 7123 dbgs() << "\nWith chain: "; 7124 Chain.getNode()->dump(&DAG); 7125 dbgs() << "\n"); 7126 WorkListRemover DeadNodes(*this); 7127 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Chain); 7128 7129 if (N->use_empty()) { 7130 removeFromWorkList(N); 7131 DAG.DeleteNode(N); 7132 } 7133 7134 return SDValue(N, 0); // Return N so it doesn't get rechecked! 7135 } 7136 } else { 7137 // Indexed loads. 7138 assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?"); 7139 if (!N->hasAnyUseOfValue(0) && !N->hasAnyUseOfValue(1)) { 7140 SDValue Undef = DAG.getUNDEF(N->getValueType(0)); 7141 DEBUG(dbgs() << "\nReplacing.7 "; 7142 N->dump(&DAG); 7143 dbgs() << "\nWith: "; 7144 Undef.getNode()->dump(&DAG); 7145 dbgs() << " and 2 other values\n"); 7146 WorkListRemover DeadNodes(*this); 7147 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Undef); 7148 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), 7149 DAG.getUNDEF(N->getValueType(1))); 7150 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 2), Chain); 7151 removeFromWorkList(N); 7152 DAG.DeleteNode(N); 7153 return SDValue(N, 0); // Return N so it doesn't get rechecked! 7154 } 7155 } 7156 } 7157 7158 // If this load is directly stored, replace the load value with the stored 7159 // value. 7160 // TODO: Handle store large -> read small portion. 7161 // TODO: Handle TRUNCSTORE/LOADEXT 7162 if (ISD::isNormalLoad(N) && !LD->isVolatile()) { 7163 if (ISD::isNON_TRUNCStore(Chain.getNode())) { 7164 StoreSDNode *PrevST = cast<StoreSDNode>(Chain); 7165 if (PrevST->getBasePtr() == Ptr && 7166 PrevST->getValue().getValueType() == N->getValueType(0)) 7167 return CombineTo(N, Chain.getOperand(1), Chain); 7168 } 7169 } 7170 7171 // Try to infer better alignment information than the load already has. 7172 if (OptLevel != CodeGenOpt::None && LD->isUnindexed()) { 7173 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) { 7174 if (Align > LD->getAlignment()) 7175 return DAG.getExtLoad(LD->getExtensionType(), N->getDebugLoc(), 7176 LD->getValueType(0), 7177 Chain, Ptr, LD->getPointerInfo(), 7178 LD->getMemoryVT(), 7179 LD->isVolatile(), LD->isNonTemporal(), Align); 7180 } 7181 } 7182 7183 if (CombinerAA) { 7184 // Walk up chain skipping non-aliasing memory nodes. 7185 SDValue BetterChain = FindBetterChain(N, Chain); 7186 7187 // If there is a better chain. 7188 if (Chain != BetterChain) { 7189 SDValue ReplLoad; 7190 7191 // Replace the chain to void dependency. 7192 if (LD->getExtensionType() == ISD::NON_EXTLOAD) { 7193 ReplLoad = DAG.getLoad(N->getValueType(0), LD->getDebugLoc(), 7194 BetterChain, Ptr, LD->getPointerInfo(), 7195 LD->isVolatile(), LD->isNonTemporal(), 7196 LD->isInvariant(), LD->getAlignment()); 7197 } else { 7198 ReplLoad = DAG.getExtLoad(LD->getExtensionType(), LD->getDebugLoc(), 7199 LD->getValueType(0), 7200 BetterChain, Ptr, LD->getPointerInfo(), 7201 LD->getMemoryVT(), 7202 LD->isVolatile(), 7203 LD->isNonTemporal(), 7204 LD->getAlignment()); 7205 } 7206 7207 // Create token factor to keep old chain connected. 7208 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 7209 MVT::Other, Chain, ReplLoad.getValue(1)); 7210 7211 // Make sure the new and old chains are cleaned up. 7212 AddToWorkList(Token.getNode()); 7213 7214 // Replace uses with load result and token factor. Don't add users 7215 // to work list. 7216 return CombineTo(N, ReplLoad.getValue(0), Token, false); 7217 } 7218 } 7219 7220 // Try transforming N to an indexed load. 7221 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 7222 return SDValue(N, 0); 7223 7224 return SDValue(); 7225} 7226 7227/// CheckForMaskedLoad - Check to see if V is (and load (ptr), imm), where the 7228/// load is having specific bytes cleared out. If so, return the byte size 7229/// being masked out and the shift amount. 7230static std::pair<unsigned, unsigned> 7231CheckForMaskedLoad(SDValue V, SDValue Ptr, SDValue Chain) { 7232 std::pair<unsigned, unsigned> Result(0, 0); 7233 7234 // Check for the structure we're looking for. 7235 if (V->getOpcode() != ISD::AND || 7236 !isa<ConstantSDNode>(V->getOperand(1)) || 7237 !ISD::isNormalLoad(V->getOperand(0).getNode())) 7238 return Result; 7239 7240 // Check the chain and pointer. 7241 LoadSDNode *LD = cast<LoadSDNode>(V->getOperand(0)); 7242 if (LD->getBasePtr() != Ptr) return Result; // Not from same pointer. 7243 7244 // The store should be chained directly to the load or be an operand of a 7245 // tokenfactor. 7246 if (LD == Chain.getNode()) 7247 ; // ok. 7248 else if (Chain->getOpcode() != ISD::TokenFactor) 7249 return Result; // Fail. 7250 else { 7251 bool isOk = false; 7252 for (unsigned i = 0, e = Chain->getNumOperands(); i != e; ++i) 7253 if (Chain->getOperand(i).getNode() == LD) { 7254 isOk = true; 7255 break; 7256 } 7257 if (!isOk) return Result; 7258 } 7259 7260 // This only handles simple types. 7261 if (V.getValueType() != MVT::i16 && 7262 V.getValueType() != MVT::i32 && 7263 V.getValueType() != MVT::i64) 7264 return Result; 7265 7266 // Check the constant mask. Invert it so that the bits being masked out are 7267 // 0 and the bits being kept are 1. Use getSExtValue so that leading bits 7268 // follow the sign bit for uniformity. 7269 uint64_t NotMask = ~cast<ConstantSDNode>(V->getOperand(1))->getSExtValue(); 7270 unsigned NotMaskLZ = CountLeadingZeros_64(NotMask); 7271 if (NotMaskLZ & 7) return Result; // Must be multiple of a byte. 7272 unsigned NotMaskTZ = CountTrailingZeros_64(NotMask); 7273 if (NotMaskTZ & 7) return Result; // Must be multiple of a byte. 7274 if (NotMaskLZ == 64) return Result; // All zero mask. 7275 7276 // See if we have a continuous run of bits. If so, we have 0*1+0* 7277 if (CountTrailingOnes_64(NotMask >> NotMaskTZ)+NotMaskTZ+NotMaskLZ != 64) 7278 return Result; 7279 7280 // Adjust NotMaskLZ down to be from the actual size of the int instead of i64. 7281 if (V.getValueType() != MVT::i64 && NotMaskLZ) 7282 NotMaskLZ -= 64-V.getValueSizeInBits(); 7283 7284 unsigned MaskedBytes = (V.getValueSizeInBits()-NotMaskLZ-NotMaskTZ)/8; 7285 switch (MaskedBytes) { 7286 case 1: 7287 case 2: 7288 case 4: break; 7289 default: return Result; // All one mask, or 5-byte mask. 7290 } 7291 7292 // Verify that the first bit starts at a multiple of mask so that the access 7293 // is aligned the same as the access width. 7294 if (NotMaskTZ && NotMaskTZ/8 % MaskedBytes) return Result; 7295 7296 Result.first = MaskedBytes; 7297 Result.second = NotMaskTZ/8; 7298 return Result; 7299} 7300 7301 7302/// ShrinkLoadReplaceStoreWithStore - Check to see if IVal is something that 7303/// provides a value as specified by MaskInfo. If so, replace the specified 7304/// store with a narrower store of truncated IVal. 7305static SDNode * 7306ShrinkLoadReplaceStoreWithStore(const std::pair<unsigned, unsigned> &MaskInfo, 7307 SDValue IVal, StoreSDNode *St, 7308 DAGCombiner *DC) { 7309 unsigned NumBytes = MaskInfo.first; 7310 unsigned ByteShift = MaskInfo.second; 7311 SelectionDAG &DAG = DC->getDAG(); 7312 7313 // Check to see if IVal is all zeros in the part being masked in by the 'or' 7314 // that uses this. If not, this is not a replacement. 7315 APInt Mask = ~APInt::getBitsSet(IVal.getValueSizeInBits(), 7316 ByteShift*8, (ByteShift+NumBytes)*8); 7317 if (!DAG.MaskedValueIsZero(IVal, Mask)) return 0; 7318 7319 // Check that it is legal on the target to do this. It is legal if the new 7320 // VT we're shrinking to (i8/i16/i32) is legal or we're still before type 7321 // legalization. 7322 MVT VT = MVT::getIntegerVT(NumBytes*8); 7323 if (!DC->isTypeLegal(VT)) 7324 return 0; 7325 7326 // Okay, we can do this! Replace the 'St' store with a store of IVal that is 7327 // shifted by ByteShift and truncated down to NumBytes. 7328 if (ByteShift) 7329 IVal = DAG.getNode(ISD::SRL, IVal->getDebugLoc(), IVal.getValueType(), IVal, 7330 DAG.getConstant(ByteShift*8, 7331 DC->getShiftAmountTy(IVal.getValueType()))); 7332 7333 // Figure out the offset for the store and the alignment of the access. 7334 unsigned StOffset; 7335 unsigned NewAlign = St->getAlignment(); 7336 7337 if (DAG.getTargetLoweringInfo().isLittleEndian()) 7338 StOffset = ByteShift; 7339 else 7340 StOffset = IVal.getValueType().getStoreSize() - ByteShift - NumBytes; 7341 7342 SDValue Ptr = St->getBasePtr(); 7343 if (StOffset) { 7344 Ptr = DAG.getNode(ISD::ADD, IVal->getDebugLoc(), Ptr.getValueType(), 7345 Ptr, DAG.getConstant(StOffset, Ptr.getValueType())); 7346 NewAlign = MinAlign(NewAlign, StOffset); 7347 } 7348 7349 // Truncate down to the new size. 7350 IVal = DAG.getNode(ISD::TRUNCATE, IVal->getDebugLoc(), VT, IVal); 7351 7352 ++OpsNarrowed; 7353 return DAG.getStore(St->getChain(), St->getDebugLoc(), IVal, Ptr, 7354 St->getPointerInfo().getWithOffset(StOffset), 7355 false, false, NewAlign).getNode(); 7356} 7357 7358 7359/// ReduceLoadOpStoreWidth - Look for sequence of load / op / store where op is 7360/// one of 'or', 'xor', and 'and' of immediates. If 'op' is only touching some 7361/// of the loaded bits, try narrowing the load and store if it would end up 7362/// being a win for performance or code size. 7363SDValue DAGCombiner::ReduceLoadOpStoreWidth(SDNode *N) { 7364 StoreSDNode *ST = cast<StoreSDNode>(N); 7365 if (ST->isVolatile()) 7366 return SDValue(); 7367 7368 SDValue Chain = ST->getChain(); 7369 SDValue Value = ST->getValue(); 7370 SDValue Ptr = ST->getBasePtr(); 7371 EVT VT = Value.getValueType(); 7372 7373 if (ST->isTruncatingStore() || VT.isVector() || !Value.hasOneUse()) 7374 return SDValue(); 7375 7376 unsigned Opc = Value.getOpcode(); 7377 7378 // If this is "store (or X, Y), P" and X is "(and (load P), cst)", where cst 7379 // is a byte mask indicating a consecutive number of bytes, check to see if 7380 // Y is known to provide just those bytes. If so, we try to replace the 7381 // load + replace + store sequence with a single (narrower) store, which makes 7382 // the load dead. 7383 if (Opc == ISD::OR) { 7384 std::pair<unsigned, unsigned> MaskedLoad; 7385 MaskedLoad = CheckForMaskedLoad(Value.getOperand(0), Ptr, Chain); 7386 if (MaskedLoad.first) 7387 if (SDNode *NewST = ShrinkLoadReplaceStoreWithStore(MaskedLoad, 7388 Value.getOperand(1), ST,this)) 7389 return SDValue(NewST, 0); 7390 7391 // Or is commutative, so try swapping X and Y. 7392 MaskedLoad = CheckForMaskedLoad(Value.getOperand(1), Ptr, Chain); 7393 if (MaskedLoad.first) 7394 if (SDNode *NewST = ShrinkLoadReplaceStoreWithStore(MaskedLoad, 7395 Value.getOperand(0), ST,this)) 7396 return SDValue(NewST, 0); 7397 } 7398 7399 if ((Opc != ISD::OR && Opc != ISD::XOR && Opc != ISD::AND) || 7400 Value.getOperand(1).getOpcode() != ISD::Constant) 7401 return SDValue(); 7402 7403 SDValue N0 = Value.getOperand(0); 7404 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() && 7405 Chain == SDValue(N0.getNode(), 1)) { 7406 LoadSDNode *LD = cast<LoadSDNode>(N0); 7407 if (LD->getBasePtr() != Ptr || 7408 LD->getPointerInfo().getAddrSpace() != 7409 ST->getPointerInfo().getAddrSpace()) 7410 return SDValue(); 7411 7412 // Find the type to narrow it the load / op / store to. 7413 SDValue N1 = Value.getOperand(1); 7414 unsigned BitWidth = N1.getValueSizeInBits(); 7415 APInt Imm = cast<ConstantSDNode>(N1)->getAPIntValue(); 7416 if (Opc == ISD::AND) 7417 Imm ^= APInt::getAllOnesValue(BitWidth); 7418 if (Imm == 0 || Imm.isAllOnesValue()) 7419 return SDValue(); 7420 unsigned ShAmt = Imm.countTrailingZeros(); 7421 unsigned MSB = BitWidth - Imm.countLeadingZeros() - 1; 7422 unsigned NewBW = NextPowerOf2(MSB - ShAmt); 7423 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW); 7424 while (NewBW < BitWidth && 7425 !(TLI.isOperationLegalOrCustom(Opc, NewVT) && 7426 TLI.isNarrowingProfitable(VT, NewVT))) { 7427 NewBW = NextPowerOf2(NewBW); 7428 NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW); 7429 } 7430 if (NewBW >= BitWidth) 7431 return SDValue(); 7432 7433 // If the lsb changed does not start at the type bitwidth boundary, 7434 // start at the previous one. 7435 if (ShAmt % NewBW) 7436 ShAmt = (((ShAmt + NewBW - 1) / NewBW) * NewBW) - NewBW; 7437 APInt Mask = APInt::getBitsSet(BitWidth, ShAmt, 7438 std::min(BitWidth, ShAmt + NewBW)); 7439 if ((Imm & Mask) == Imm) { 7440 APInt NewImm = (Imm & Mask).lshr(ShAmt).trunc(NewBW); 7441 if (Opc == ISD::AND) 7442 NewImm ^= APInt::getAllOnesValue(NewBW); 7443 uint64_t PtrOff = ShAmt / 8; 7444 // For big endian targets, we need to adjust the offset to the pointer to 7445 // load the correct bytes. 7446 if (TLI.isBigEndian()) 7447 PtrOff = (BitWidth + 7 - NewBW) / 8 - PtrOff; 7448 7449 unsigned NewAlign = MinAlign(LD->getAlignment(), PtrOff); 7450 Type *NewVTTy = NewVT.getTypeForEVT(*DAG.getContext()); 7451 if (NewAlign < TLI.getDataLayout()->getABITypeAlignment(NewVTTy)) 7452 return SDValue(); 7453 7454 SDValue NewPtr = DAG.getNode(ISD::ADD, LD->getDebugLoc(), 7455 Ptr.getValueType(), Ptr, 7456 DAG.getConstant(PtrOff, Ptr.getValueType())); 7457 SDValue NewLD = DAG.getLoad(NewVT, N0.getDebugLoc(), 7458 LD->getChain(), NewPtr, 7459 LD->getPointerInfo().getWithOffset(PtrOff), 7460 LD->isVolatile(), LD->isNonTemporal(), 7461 LD->isInvariant(), NewAlign); 7462 SDValue NewVal = DAG.getNode(Opc, Value.getDebugLoc(), NewVT, NewLD, 7463 DAG.getConstant(NewImm, NewVT)); 7464 SDValue NewST = DAG.getStore(Chain, N->getDebugLoc(), 7465 NewVal, NewPtr, 7466 ST->getPointerInfo().getWithOffset(PtrOff), 7467 false, false, NewAlign); 7468 7469 AddToWorkList(NewPtr.getNode()); 7470 AddToWorkList(NewLD.getNode()); 7471 AddToWorkList(NewVal.getNode()); 7472 WorkListRemover DeadNodes(*this); 7473 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), NewLD.getValue(1)); 7474 ++OpsNarrowed; 7475 return NewST; 7476 } 7477 } 7478 7479 return SDValue(); 7480} 7481 7482/// TransformFPLoadStorePair - For a given floating point load / store pair, 7483/// if the load value isn't used by any other operations, then consider 7484/// transforming the pair to integer load / store operations if the target 7485/// deems the transformation profitable. 7486SDValue DAGCombiner::TransformFPLoadStorePair(SDNode *N) { 7487 StoreSDNode *ST = cast<StoreSDNode>(N); 7488 SDValue Chain = ST->getChain(); 7489 SDValue Value = ST->getValue(); 7490 if (ISD::isNormalStore(ST) && ISD::isNormalLoad(Value.getNode()) && 7491 Value.hasOneUse() && 7492 Chain == SDValue(Value.getNode(), 1)) { 7493 LoadSDNode *LD = cast<LoadSDNode>(Value); 7494 EVT VT = LD->getMemoryVT(); 7495 if (!VT.isFloatingPoint() || 7496 VT != ST->getMemoryVT() || 7497 LD->isNonTemporal() || 7498 ST->isNonTemporal() || 7499 LD->getPointerInfo().getAddrSpace() != 0 || 7500 ST->getPointerInfo().getAddrSpace() != 0) 7501 return SDValue(); 7502 7503 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits()); 7504 if (!TLI.isOperationLegal(ISD::LOAD, IntVT) || 7505 !TLI.isOperationLegal(ISD::STORE, IntVT) || 7506 !TLI.isDesirableToTransformToIntegerOp(ISD::LOAD, VT) || 7507 !TLI.isDesirableToTransformToIntegerOp(ISD::STORE, VT)) 7508 return SDValue(); 7509 7510 unsigned LDAlign = LD->getAlignment(); 7511 unsigned STAlign = ST->getAlignment(); 7512 Type *IntVTTy = IntVT.getTypeForEVT(*DAG.getContext()); 7513 unsigned ABIAlign = TLI.getDataLayout()->getABITypeAlignment(IntVTTy); 7514 if (LDAlign < ABIAlign || STAlign < ABIAlign) 7515 return SDValue(); 7516 7517 SDValue NewLD = DAG.getLoad(IntVT, Value.getDebugLoc(), 7518 LD->getChain(), LD->getBasePtr(), 7519 LD->getPointerInfo(), 7520 false, false, false, LDAlign); 7521 7522 SDValue NewST = DAG.getStore(NewLD.getValue(1), N->getDebugLoc(), 7523 NewLD, ST->getBasePtr(), 7524 ST->getPointerInfo(), 7525 false, false, STAlign); 7526 7527 AddToWorkList(NewLD.getNode()); 7528 AddToWorkList(NewST.getNode()); 7529 WorkListRemover DeadNodes(*this); 7530 DAG.ReplaceAllUsesOfValueWith(Value.getValue(1), NewLD.getValue(1)); 7531 ++LdStFP2Int; 7532 return NewST; 7533 } 7534 7535 return SDValue(); 7536} 7537 7538/// Returns the base pointer and an integer offset from that object. 7539static std::pair<SDValue, int64_t> GetPointerBaseAndOffset(SDValue Ptr) { 7540 if (Ptr->getOpcode() == ISD::ADD && isa<ConstantSDNode>(Ptr->getOperand(1))) { 7541 int64_t Offset = cast<ConstantSDNode>(Ptr->getOperand(1))->getSExtValue(); 7542 SDValue Base = Ptr->getOperand(0); 7543 return std::make_pair(Base, Offset); 7544 } 7545 7546 return std::make_pair(Ptr, 0); 7547} 7548 7549/// Holds a pointer to an LSBaseSDNode as well as information on where it 7550/// is located in a sequence of memory operations connected by a chain. 7551struct MemOpLink { 7552 MemOpLink (LSBaseSDNode *N, int64_t Offset, unsigned Seq): 7553 MemNode(N), OffsetFromBase(Offset), SequenceNum(Seq) { } 7554 // Ptr to the mem node. 7555 LSBaseSDNode *MemNode; 7556 // Offset from the base ptr. 7557 int64_t OffsetFromBase; 7558 // What is the sequence number of this mem node. 7559 // Lowest mem operand in the DAG starts at zero. 7560 unsigned SequenceNum; 7561}; 7562 7563/// Sorts store nodes in a link according to their offset from a shared 7564// base ptr. 7565struct ConsecutiveMemoryChainSorter { 7566 bool operator()(MemOpLink LHS, MemOpLink RHS) { 7567 return LHS.OffsetFromBase < RHS.OffsetFromBase; 7568 } 7569}; 7570 7571bool DAGCombiner::MergeConsecutiveStores(StoreSDNode* St) { 7572 EVT MemVT = St->getMemoryVT(); 7573 int64_t ElementSizeBytes = MemVT.getSizeInBits()/8; 7574 7575 // Don't merge vectors into wider inputs. 7576 if (MemVT.isVector() || !MemVT.isSimple()) 7577 return false; 7578 7579 // Perform an early exit check. Do not bother looking at stored values that 7580 // are not constants or loads. 7581 SDValue StoredVal = St->getValue(); 7582 bool IsLoadSrc = isa<LoadSDNode>(StoredVal); 7583 if (!isa<ConstantSDNode>(StoredVal) && !isa<ConstantFPSDNode>(StoredVal) && 7584 !IsLoadSrc) 7585 return false; 7586 7587 // Only look at ends of store sequences. 7588 SDValue Chain = SDValue(St, 1); 7589 if (Chain->hasOneUse() && Chain->use_begin()->getOpcode() == ISD::STORE) 7590 return false; 7591 7592 // This holds the base pointer and the offset in bytes from the base pointer. 7593 std::pair<SDValue, int64_t> BasePtr = 7594 GetPointerBaseAndOffset(St->getBasePtr()); 7595 7596 // We must have a base and an offset. 7597 if (!BasePtr.first.getNode()) 7598 return false; 7599 7600 // Do not handle stores to undef base pointers. 7601 if (BasePtr.first.getOpcode() == ISD::UNDEF) 7602 return false; 7603 7604 // Save the LoadSDNodes that we find in the chain. 7605 // We need to make sure that these nodes do not interfere with 7606 // any of the store nodes. 7607 SmallVector<LSBaseSDNode*, 8> AliasLoadNodes; 7608 7609 // Save the StoreSDNodes that we find in the chain. 7610 SmallVector<MemOpLink, 8> StoreNodes; 7611 7612 // Walk up the chain and look for nodes with offsets from the same 7613 // base pointer. Stop when reaching an instruction with a different kind 7614 // or instruction which has a different base pointer. 7615 unsigned Seq = 0; 7616 StoreSDNode *Index = St; 7617 while (Index) { 7618 // If the chain has more than one use, then we can't reorder the mem ops. 7619 if (Index != St && !SDValue(Index, 1)->hasOneUse()) 7620 break; 7621 7622 // Find the base pointer and offset for this memory node. 7623 std::pair<SDValue, int64_t> Ptr = 7624 GetPointerBaseAndOffset(Index->getBasePtr()); 7625 7626 // Check that the base pointer is the same as the original one. 7627 if (Ptr.first.getNode() != BasePtr.first.getNode()) 7628 break; 7629 7630 // Check that the alignment is the same. 7631 if (Index->getAlignment() != St->getAlignment()) 7632 break; 7633 7634 // The memory operands must not be volatile. 7635 if (Index->isVolatile() || Index->isIndexed()) 7636 break; 7637 7638 // No truncation. 7639 if (StoreSDNode *St = dyn_cast<StoreSDNode>(Index)) 7640 if (St->isTruncatingStore()) 7641 break; 7642 7643 // The stored memory type must be the same. 7644 if (Index->getMemoryVT() != MemVT) 7645 break; 7646 7647 // We do not allow unaligned stores because we want to prevent overriding 7648 // stores. 7649 if (Index->getAlignment()*8 != MemVT.getSizeInBits()) 7650 break; 7651 7652 // We found a potential memory operand to merge. 7653 StoreNodes.push_back(MemOpLink(Index, Ptr.second, Seq++)); 7654 7655 // Find the next memory operand in the chain. If the next operand in the 7656 // chain is a store then move up and continue the scan with the next 7657 // memory operand. If the next operand is a load save it and use alias 7658 // information to check if it interferes with anything. 7659 SDNode *NextInChain = Index->getChain().getNode(); 7660 while (1) { 7661 if (StoreSDNode *STn = dyn_cast<StoreSDNode>(NextInChain)) { 7662 // We found a store node. Use it for the next iteration. 7663 Index = STn; 7664 break; 7665 } else if (LoadSDNode *Ldn = dyn_cast<LoadSDNode>(NextInChain)) { 7666 // Save the load node for later. Continue the scan. 7667 AliasLoadNodes.push_back(Ldn); 7668 NextInChain = Ldn->getChain().getNode(); 7669 continue; 7670 } else { 7671 Index = NULL; 7672 break; 7673 } 7674 } 7675 } 7676 7677 // Check if there is anything to merge. 7678 if (StoreNodes.size() < 2) 7679 return false; 7680 7681 // Sort the memory operands according to their distance from the base pointer. 7682 std::sort(StoreNodes.begin(), StoreNodes.end(), 7683 ConsecutiveMemoryChainSorter()); 7684 7685 // Scan the memory operations on the chain and find the first non-consecutive 7686 // store memory address. 7687 unsigned LastConsecutiveStore = 0; 7688 int64_t StartAddress = StoreNodes[0].OffsetFromBase; 7689 for (unsigned i = 0, e = StoreNodes.size(); i < e; ++i) { 7690 7691 // Check that the addresses are consecutive starting from the second 7692 // element in the list of stores. 7693 if (i > 0) { 7694 int64_t CurrAddress = StoreNodes[i].OffsetFromBase; 7695 if (CurrAddress - StartAddress != (ElementSizeBytes * i)) 7696 break; 7697 } 7698 7699 bool Alias = false; 7700 // Check if this store interferes with any of the loads that we found. 7701 for (unsigned ld = 0, lde = AliasLoadNodes.size(); ld < lde; ++ld) 7702 if (isAlias(AliasLoadNodes[ld], StoreNodes[i].MemNode)) { 7703 Alias = true; 7704 break; 7705 } 7706 // We found a load that alias with this store. Stop the sequence. 7707 if (Alias) 7708 break; 7709 7710 // Mark this node as useful. 7711 LastConsecutiveStore = i; 7712 } 7713 7714 // The node with the lowest store address. 7715 LSBaseSDNode *FirstInChain = StoreNodes[0].MemNode; 7716 7717 // Store the constants into memory as one consecutive store. 7718 if (!IsLoadSrc) { 7719 unsigned LastLegalType = 0; 7720 unsigned LastLegalVectorType = 0; 7721 bool NonZero = false; 7722 for (unsigned i=0; i<LastConsecutiveStore+1; ++i) { 7723 StoreSDNode *St = cast<StoreSDNode>(StoreNodes[i].MemNode); 7724 SDValue StoredVal = St->getValue(); 7725 7726 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(StoredVal)) { 7727 NonZero |= !C->isNullValue(); 7728 } else if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(StoredVal)) { 7729 NonZero |= !C->getConstantFPValue()->isNullValue(); 7730 } else { 7731 // Non constant. 7732 break; 7733 } 7734 7735 // Find a legal type for the constant store. 7736 unsigned StoreBW = (i+1) * ElementSizeBytes * 8; 7737 EVT StoreTy = EVT::getIntegerVT(*DAG.getContext(), StoreBW); 7738 if (TLI.isTypeLegal(StoreTy)) 7739 LastLegalType = i+1; 7740 7741 // Find a legal type for the vector store. 7742 EVT Ty = EVT::getVectorVT(*DAG.getContext(), MemVT, i+1); 7743 if (TLI.isTypeLegal(Ty)) 7744 LastLegalVectorType = i + 1; 7745 } 7746 7747 // We only use vectors if the constant is known to be zero. 7748 if (NonZero) 7749 LastLegalVectorType = 0; 7750 7751 // Check if we found a legal integer type to store. 7752 if (LastLegalType == 0 && LastLegalVectorType == 0) 7753 return false; 7754 7755 bool UseVector = LastLegalVectorType > LastLegalType; 7756 unsigned NumElem = UseVector ? LastLegalVectorType : LastLegalType; 7757 7758 // Make sure we have something to merge. 7759 if (NumElem < 2) 7760 return false; 7761 7762 unsigned EarliestNodeUsed = 0; 7763 for (unsigned i=0; i < NumElem; ++i) { 7764 // Find a chain for the new wide-store operand. Notice that some 7765 // of the store nodes that we found may not be selected for inclusion 7766 // in the wide store. The chain we use needs to be the chain of the 7767 // earliest store node which is *used* and replaced by the wide store. 7768 if (StoreNodes[i].SequenceNum > StoreNodes[EarliestNodeUsed].SequenceNum) 7769 EarliestNodeUsed = i; 7770 } 7771 7772 // The earliest Node in the DAG. 7773 LSBaseSDNode *EarliestOp = StoreNodes[EarliestNodeUsed].MemNode; 7774 DebugLoc DL = StoreNodes[0].MemNode->getDebugLoc(); 7775 7776 SDValue StoredVal; 7777 if (UseVector) { 7778 // Find a legal type for the vector store. 7779 EVT Ty = EVT::getVectorVT(*DAG.getContext(), MemVT, NumElem); 7780 assert(TLI.isTypeLegal(Ty) && "Illegal vector store"); 7781 StoredVal = DAG.getConstant(0, Ty); 7782 } else { 7783 unsigned StoreBW = NumElem * ElementSizeBytes * 8; 7784 APInt StoreInt(StoreBW, 0); 7785 7786 // Construct a single integer constant which is made of the smaller 7787 // constant inputs. 7788 bool IsLE = TLI.isLittleEndian(); 7789 for (unsigned i = 0; i < NumElem ; ++i) { 7790 unsigned Idx = IsLE ?(NumElem - 1 - i) : i; 7791 StoreSDNode *St = cast<StoreSDNode>(StoreNodes[Idx].MemNode); 7792 SDValue Val = St->getValue(); 7793 StoreInt<<=ElementSizeBytes*8; 7794 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Val)) { 7795 StoreInt|=C->getAPIntValue().zext(StoreBW); 7796 } else if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(Val)) { 7797 StoreInt|= C->getValueAPF().bitcastToAPInt().zext(StoreBW); 7798 } else { 7799 assert(false && "Invalid constant element type"); 7800 } 7801 } 7802 7803 // Create the new Load and Store operations. 7804 EVT StoreTy = EVT::getIntegerVT(*DAG.getContext(), StoreBW); 7805 StoredVal = DAG.getConstant(StoreInt, StoreTy); 7806 } 7807 7808 SDValue NewStore = DAG.getStore(EarliestOp->getChain(), DL, StoredVal, 7809 FirstInChain->getBasePtr(), 7810 FirstInChain->getPointerInfo(), 7811 false, false, 7812 FirstInChain->getAlignment()); 7813 7814 // Replace the first store with the new store 7815 CombineTo(EarliestOp, NewStore); 7816 // Erase all other stores. 7817 for (unsigned i = 0; i < NumElem ; ++i) { 7818 if (StoreNodes[i].MemNode == EarliestOp) 7819 continue; 7820 StoreSDNode *St = cast<StoreSDNode>(StoreNodes[i].MemNode); 7821 // ReplaceAllUsesWith will replace all uses that existed when it was 7822 // called, but graph optimizations may cause new ones to appear. For 7823 // example, the case in pr14333 looks like 7824 // 7825 // St's chain -> St -> another store -> X 7826 // 7827 // And the only difference from St to the other store is the chain. 7828 // When we change it's chain to be St's chain they become identical, 7829 // get CSEed and the net result is that X is now a use of St. 7830 // Since we know that St is redundant, just iterate. 7831 while (!St->use_empty()) 7832 DAG.ReplaceAllUsesWith(SDValue(St, 0), St->getChain()); 7833 removeFromWorkList(St); 7834 DAG.DeleteNode(St); 7835 } 7836 7837 return true; 7838 } 7839 7840 // Below we handle the case of multiple consecutive stores that 7841 // come from multiple consecutive loads. We merge them into a single 7842 // wide load and a single wide store. 7843 7844 // Look for load nodes which are used by the stored values. 7845 SmallVector<MemOpLink, 8> LoadNodes; 7846 7847 // Find acceptable loads. Loads need to have the same chain (token factor), 7848 // must not be zext, volatile, indexed, and they must be consecutive. 7849 SDValue LdBasePtr; 7850 for (unsigned i=0; i<LastConsecutiveStore+1; ++i) { 7851 StoreSDNode *St = cast<StoreSDNode>(StoreNodes[i].MemNode); 7852 LoadSDNode *Ld = dyn_cast<LoadSDNode>(St->getValue()); 7853 if (!Ld) break; 7854 7855 // Loads must only have one use. 7856 if (!Ld->hasNUsesOfValue(1, 0)) 7857 break; 7858 7859 // Check that the alignment is the same as the stores. 7860 if (Ld->getAlignment() != St->getAlignment()) 7861 break; 7862 7863 // The memory operands must not be volatile. 7864 if (Ld->isVolatile() || Ld->isIndexed()) 7865 break; 7866 7867 // We do not accept ext loads. 7868 if (Ld->getExtensionType() != ISD::NON_EXTLOAD) 7869 break; 7870 7871 // The stored memory type must be the same. 7872 if (Ld->getMemoryVT() != MemVT) 7873 break; 7874 7875 std::pair<SDValue, int64_t> LdPtr = 7876 GetPointerBaseAndOffset(Ld->getBasePtr()); 7877 7878 // If this is not the first ptr that we check. 7879 if (LdBasePtr.getNode()) { 7880 // The base ptr must be the same. 7881 if (LdPtr.first != LdBasePtr) 7882 break; 7883 } else { 7884 // Check that all other base pointers are the same as this one. 7885 LdBasePtr = LdPtr.first; 7886 } 7887 7888 // We found a potential memory operand to merge. 7889 LoadNodes.push_back(MemOpLink(Ld, LdPtr.second, 0)); 7890 } 7891 7892 if (LoadNodes.size() < 2) 7893 return false; 7894 7895 // Scan the memory operations on the chain and find the first non-consecutive 7896 // load memory address. These variables hold the index in the store node 7897 // array. 7898 unsigned LastConsecutiveLoad = 0; 7899 // This variable refers to the size and not index in the array. 7900 unsigned LastLegalVectorType = 0; 7901 unsigned LastLegalIntegerType = 0; 7902 StartAddress = LoadNodes[0].OffsetFromBase; 7903 SDValue FirstChain = LoadNodes[0].MemNode->getChain(); 7904 for (unsigned i = 1; i < LoadNodes.size(); ++i) { 7905 // All loads much share the same chain. 7906 if (LoadNodes[i].MemNode->getChain() != FirstChain) 7907 break; 7908 7909 int64_t CurrAddress = LoadNodes[i].OffsetFromBase; 7910 if (CurrAddress - StartAddress != (ElementSizeBytes * i)) 7911 break; 7912 LastConsecutiveLoad = i; 7913 7914 // Find a legal type for the vector store. 7915 EVT StoreTy = EVT::getVectorVT(*DAG.getContext(), MemVT, i+1); 7916 if (TLI.isTypeLegal(StoreTy)) 7917 LastLegalVectorType = i + 1; 7918 7919 // Find a legal type for the integer store. 7920 unsigned StoreBW = (i+1) * ElementSizeBytes * 8; 7921 StoreTy = EVT::getIntegerVT(*DAG.getContext(), StoreBW); 7922 if (TLI.isTypeLegal(StoreTy)) 7923 LastLegalIntegerType = i + 1; 7924 } 7925 7926 // Only use vector types if the vector type is larger than the integer type. 7927 // If they are the same, use integers. 7928 bool UseVectorTy = LastLegalVectorType > LastLegalIntegerType; 7929 unsigned LastLegalType = std::max(LastLegalVectorType, LastLegalIntegerType); 7930 7931 // We add +1 here because the LastXXX variables refer to location while 7932 // the NumElem refers to array/index size. 7933 unsigned NumElem = std::min(LastConsecutiveStore, LastConsecutiveLoad) + 1; 7934 NumElem = std::min(LastLegalType, NumElem); 7935 7936 if (NumElem < 2) 7937 return false; 7938 7939 // The earliest Node in the DAG. 7940 unsigned EarliestNodeUsed = 0; 7941 LSBaseSDNode *EarliestOp = StoreNodes[EarliestNodeUsed].MemNode; 7942 for (unsigned i=1; i<NumElem; ++i) { 7943 // Find a chain for the new wide-store operand. Notice that some 7944 // of the store nodes that we found may not be selected for inclusion 7945 // in the wide store. The chain we use needs to be the chain of the 7946 // earliest store node which is *used* and replaced by the wide store. 7947 if (StoreNodes[i].SequenceNum > StoreNodes[EarliestNodeUsed].SequenceNum) 7948 EarliestNodeUsed = i; 7949 } 7950 7951 // Find if it is better to use vectors or integers to load and store 7952 // to memory. 7953 EVT JointMemOpVT; 7954 if (UseVectorTy) { 7955 JointMemOpVT = EVT::getVectorVT(*DAG.getContext(), MemVT, NumElem); 7956 } else { 7957 unsigned StoreBW = NumElem * ElementSizeBytes * 8; 7958 JointMemOpVT = EVT::getIntegerVT(*DAG.getContext(), StoreBW); 7959 } 7960 7961 DebugLoc LoadDL = LoadNodes[0].MemNode->getDebugLoc(); 7962 DebugLoc StoreDL = StoreNodes[0].MemNode->getDebugLoc(); 7963 7964 LoadSDNode *FirstLoad = cast<LoadSDNode>(LoadNodes[0].MemNode); 7965 SDValue NewLoad = DAG.getLoad(JointMemOpVT, LoadDL, 7966 FirstLoad->getChain(), 7967 FirstLoad->getBasePtr(), 7968 FirstLoad->getPointerInfo(), 7969 false, false, false, 7970 FirstLoad->getAlignment()); 7971 7972 SDValue NewStore = DAG.getStore(EarliestOp->getChain(), StoreDL, NewLoad, 7973 FirstInChain->getBasePtr(), 7974 FirstInChain->getPointerInfo(), false, false, 7975 FirstInChain->getAlignment()); 7976 7977 // Replace one of the loads with the new load. 7978 LoadSDNode *Ld = cast<LoadSDNode>(LoadNodes[0].MemNode); 7979 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), 7980 SDValue(NewLoad.getNode(), 1)); 7981 7982 // Remove the rest of the load chains. 7983 for (unsigned i = 1; i < NumElem ; ++i) { 7984 // Replace all chain users of the old load nodes with the chain of the new 7985 // load node. 7986 LoadSDNode *Ld = cast<LoadSDNode>(LoadNodes[i].MemNode); 7987 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), Ld->getChain()); 7988 } 7989 7990 // Replace the first store with the new store. 7991 CombineTo(EarliestOp, NewStore); 7992 // Erase all other stores. 7993 for (unsigned i = 0; i < NumElem ; ++i) { 7994 // Remove all Store nodes. 7995 if (StoreNodes[i].MemNode == EarliestOp) 7996 continue; 7997 StoreSDNode *St = cast<StoreSDNode>(StoreNodes[i].MemNode); 7998 DAG.ReplaceAllUsesOfValueWith(SDValue(St, 0), St->getChain()); 7999 removeFromWorkList(St); 8000 DAG.DeleteNode(St); 8001 } 8002 8003 return true; 8004} 8005 8006SDValue DAGCombiner::visitSTORE(SDNode *N) { 8007 StoreSDNode *ST = cast<StoreSDNode>(N); 8008 SDValue Chain = ST->getChain(); 8009 SDValue Value = ST->getValue(); 8010 SDValue Ptr = ST->getBasePtr(); 8011 8012 // If this is a store of a bit convert, store the input value if the 8013 // resultant store does not need a higher alignment than the original. 8014 if (Value.getOpcode() == ISD::BITCAST && !ST->isTruncatingStore() && 8015 ST->isUnindexed()) { 8016 unsigned OrigAlign = ST->getAlignment(); 8017 EVT SVT = Value.getOperand(0).getValueType(); 8018 unsigned Align = TLI.getDataLayout()-> 8019 getABITypeAlignment(SVT.getTypeForEVT(*DAG.getContext())); 8020 if (Align <= OrigAlign && 8021 ((!LegalOperations && !ST->isVolatile()) || 8022 TLI.isOperationLegalOrCustom(ISD::STORE, SVT))) 8023 return DAG.getStore(Chain, N->getDebugLoc(), Value.getOperand(0), 8024 Ptr, ST->getPointerInfo(), ST->isVolatile(), 8025 ST->isNonTemporal(), OrigAlign); 8026 } 8027 8028 // Turn 'store undef, Ptr' -> nothing. 8029 if (Value.getOpcode() == ISD::UNDEF && ST->isUnindexed()) 8030 return Chain; 8031 8032 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 8033 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) { 8034 // NOTE: If the original store is volatile, this transform must not increase 8035 // the number of stores. For example, on x86-32 an f64 can be stored in one 8036 // processor operation but an i64 (which is not legal) requires two. So the 8037 // transform should not be done in this case. 8038 if (Value.getOpcode() != ISD::TargetConstantFP) { 8039 SDValue Tmp; 8040 switch (CFP->getValueType(0).getSimpleVT().SimpleTy) { 8041 default: llvm_unreachable("Unknown FP type"); 8042 case MVT::f16: // We don't do this for these yet. 8043 case MVT::f80: 8044 case MVT::f128: 8045 case MVT::ppcf128: 8046 break; 8047 case MVT::f32: 8048 if ((isTypeLegal(MVT::i32) && !LegalOperations && !ST->isVolatile()) || 8049 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) { 8050 Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF(). 8051 bitcastToAPInt().getZExtValue(), MVT::i32); 8052 return DAG.getStore(Chain, N->getDebugLoc(), Tmp, 8053 Ptr, ST->getPointerInfo(), ST->isVolatile(), 8054 ST->isNonTemporal(), ST->getAlignment()); 8055 } 8056 break; 8057 case MVT::f64: 8058 if ((TLI.isTypeLegal(MVT::i64) && !LegalOperations && 8059 !ST->isVolatile()) || 8060 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i64)) { 8061 Tmp = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt(). 8062 getZExtValue(), MVT::i64); 8063 return DAG.getStore(Chain, N->getDebugLoc(), Tmp, 8064 Ptr, ST->getPointerInfo(), ST->isVolatile(), 8065 ST->isNonTemporal(), ST->getAlignment()); 8066 } 8067 8068 if (!ST->isVolatile() && 8069 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) { 8070 // Many FP stores are not made apparent until after legalize, e.g. for 8071 // argument passing. Since this is so common, custom legalize the 8072 // 64-bit integer store into two 32-bit stores. 8073 uint64_t Val = CFP->getValueAPF().bitcastToAPInt().getZExtValue(); 8074 SDValue Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32); 8075 SDValue Hi = DAG.getConstant(Val >> 32, MVT::i32); 8076 if (TLI.isBigEndian()) std::swap(Lo, Hi); 8077 8078 unsigned Alignment = ST->getAlignment(); 8079 bool isVolatile = ST->isVolatile(); 8080 bool isNonTemporal = ST->isNonTemporal(); 8081 8082 SDValue St0 = DAG.getStore(Chain, ST->getDebugLoc(), Lo, 8083 Ptr, ST->getPointerInfo(), 8084 isVolatile, isNonTemporal, 8085 ST->getAlignment()); 8086 Ptr = DAG.getNode(ISD::ADD, N->getDebugLoc(), Ptr.getValueType(), Ptr, 8087 DAG.getConstant(4, Ptr.getValueType())); 8088 Alignment = MinAlign(Alignment, 4U); 8089 SDValue St1 = DAG.getStore(Chain, ST->getDebugLoc(), Hi, 8090 Ptr, ST->getPointerInfo().getWithOffset(4), 8091 isVolatile, isNonTemporal, 8092 Alignment); 8093 return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, 8094 St0, St1); 8095 } 8096 8097 break; 8098 } 8099 } 8100 } 8101 8102 // Try to infer better alignment information than the store already has. 8103 if (OptLevel != CodeGenOpt::None && ST->isUnindexed()) { 8104 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) { 8105 if (Align > ST->getAlignment()) 8106 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value, 8107 Ptr, ST->getPointerInfo(), ST->getMemoryVT(), 8108 ST->isVolatile(), ST->isNonTemporal(), Align); 8109 } 8110 } 8111 8112 // Try transforming a pair floating point load / store ops to integer 8113 // load / store ops. 8114 SDValue NewST = TransformFPLoadStorePair(N); 8115 if (NewST.getNode()) 8116 return NewST; 8117 8118 if (CombinerAA) { 8119 // Walk up chain skipping non-aliasing memory nodes. 8120 SDValue BetterChain = FindBetterChain(N, Chain); 8121 8122 // If there is a better chain. 8123 if (Chain != BetterChain) { 8124 SDValue ReplStore; 8125 8126 // Replace the chain to avoid dependency. 8127 if (ST->isTruncatingStore()) { 8128 ReplStore = DAG.getTruncStore(BetterChain, N->getDebugLoc(), Value, Ptr, 8129 ST->getPointerInfo(), 8130 ST->getMemoryVT(), ST->isVolatile(), 8131 ST->isNonTemporal(), ST->getAlignment()); 8132 } else { 8133 ReplStore = DAG.getStore(BetterChain, N->getDebugLoc(), Value, Ptr, 8134 ST->getPointerInfo(), 8135 ST->isVolatile(), ST->isNonTemporal(), 8136 ST->getAlignment()); 8137 } 8138 8139 // Create token to keep both nodes around. 8140 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 8141 MVT::Other, Chain, ReplStore); 8142 8143 // Make sure the new and old chains are cleaned up. 8144 AddToWorkList(Token.getNode()); 8145 8146 // Don't add users to work list. 8147 return CombineTo(N, Token, false); 8148 } 8149 } 8150 8151 // Try transforming N to an indexed store. 8152 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 8153 return SDValue(N, 0); 8154 8155 // FIXME: is there such a thing as a truncating indexed store? 8156 if (ST->isTruncatingStore() && ST->isUnindexed() && 8157 Value.getValueType().isInteger()) { 8158 // See if we can simplify the input to this truncstore with knowledge that 8159 // only the low bits are being used. For example: 8160 // "truncstore (or (shl x, 8), y), i8" -> "truncstore y, i8" 8161 SDValue Shorter = 8162 GetDemandedBits(Value, 8163 APInt::getLowBitsSet( 8164 Value.getValueType().getScalarType().getSizeInBits(), 8165 ST->getMemoryVT().getScalarType().getSizeInBits())); 8166 AddToWorkList(Value.getNode()); 8167 if (Shorter.getNode()) 8168 return DAG.getTruncStore(Chain, N->getDebugLoc(), Shorter, 8169 Ptr, ST->getPointerInfo(), ST->getMemoryVT(), 8170 ST->isVolatile(), ST->isNonTemporal(), 8171 ST->getAlignment()); 8172 8173 // Otherwise, see if we can simplify the operation with 8174 // SimplifyDemandedBits, which only works if the value has a single use. 8175 if (SimplifyDemandedBits(Value, 8176 APInt::getLowBitsSet( 8177 Value.getValueType().getScalarType().getSizeInBits(), 8178 ST->getMemoryVT().getScalarType().getSizeInBits()))) 8179 return SDValue(N, 0); 8180 } 8181 8182 // If this is a load followed by a store to the same location, then the store 8183 // is dead/noop. 8184 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Value)) { 8185 if (Ld->getBasePtr() == Ptr && ST->getMemoryVT() == Ld->getMemoryVT() && 8186 ST->isUnindexed() && !ST->isVolatile() && 8187 // There can't be any side effects between the load and store, such as 8188 // a call or store. 8189 Chain.reachesChainWithoutSideEffects(SDValue(Ld, 1))) { 8190 // The store is dead, remove it. 8191 return Chain; 8192 } 8193 } 8194 8195 // If this is an FP_ROUND or TRUNC followed by a store, fold this into a 8196 // truncating store. We can do this even if this is already a truncstore. 8197 if ((Value.getOpcode() == ISD::FP_ROUND || Value.getOpcode() == ISD::TRUNCATE) 8198 && Value.getNode()->hasOneUse() && ST->isUnindexed() && 8199 TLI.isTruncStoreLegal(Value.getOperand(0).getValueType(), 8200 ST->getMemoryVT())) { 8201 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value.getOperand(0), 8202 Ptr, ST->getPointerInfo(), ST->getMemoryVT(), 8203 ST->isVolatile(), ST->isNonTemporal(), 8204 ST->getAlignment()); 8205 } 8206 8207 // Only perform this optimization before the types are legal, because we 8208 // don't want to perform this optimization on every DAGCombine invocation. 8209 if (!LegalTypes) { 8210 bool EverChanged = false; 8211 8212 do { 8213 // There can be multiple store sequences on the same chain. 8214 // Keep trying to merge store sequences until we are unable to do so 8215 // or until we merge the last store on the chain. 8216 bool Changed = MergeConsecutiveStores(ST); 8217 EverChanged |= Changed; 8218 if (!Changed) break; 8219 } while (ST->getOpcode() != ISD::DELETED_NODE); 8220 8221 if (EverChanged) 8222 return SDValue(N, 0); 8223 } 8224 8225 return ReduceLoadOpStoreWidth(N); 8226} 8227 8228SDValue DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) { 8229 SDValue InVec = N->getOperand(0); 8230 SDValue InVal = N->getOperand(1); 8231 SDValue EltNo = N->getOperand(2); 8232 DebugLoc dl = N->getDebugLoc(); 8233 8234 // If the inserted element is an UNDEF, just use the input vector. 8235 if (InVal.getOpcode() == ISD::UNDEF) 8236 return InVec; 8237 8238 EVT VT = InVec.getValueType(); 8239 8240 // If we can't generate a legal BUILD_VECTOR, exit 8241 if (LegalOperations && !TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) 8242 return SDValue(); 8243 8244 // Check that we know which element is being inserted 8245 if (!isa<ConstantSDNode>(EltNo)) 8246 return SDValue(); 8247 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 8248 8249 // Check that the operand is a BUILD_VECTOR (or UNDEF, which can essentially 8250 // be converted to a BUILD_VECTOR). Fill in the Ops vector with the 8251 // vector elements. 8252 SmallVector<SDValue, 8> Ops; 8253 if (InVec.getOpcode() == ISD::BUILD_VECTOR) { 8254 Ops.append(InVec.getNode()->op_begin(), 8255 InVec.getNode()->op_end()); 8256 } else if (InVec.getOpcode() == ISD::UNDEF) { 8257 unsigned NElts = VT.getVectorNumElements(); 8258 Ops.append(NElts, DAG.getUNDEF(InVal.getValueType())); 8259 } else { 8260 return SDValue(); 8261 } 8262 8263 // Insert the element 8264 if (Elt < Ops.size()) { 8265 // All the operands of BUILD_VECTOR must have the same type; 8266 // we enforce that here. 8267 EVT OpVT = Ops[0].getValueType(); 8268 if (InVal.getValueType() != OpVT) 8269 InVal = OpVT.bitsGT(InVal.getValueType()) ? 8270 DAG.getNode(ISD::ANY_EXTEND, dl, OpVT, InVal) : 8271 DAG.getNode(ISD::TRUNCATE, dl, OpVT, InVal); 8272 Ops[Elt] = InVal; 8273 } 8274 8275 // Return the new vector 8276 return DAG.getNode(ISD::BUILD_VECTOR, dl, 8277 VT, &Ops[0], Ops.size()); 8278} 8279 8280SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) { 8281 // (vextract (scalar_to_vector val, 0) -> val 8282 SDValue InVec = N->getOperand(0); 8283 EVT VT = InVec.getValueType(); 8284 EVT NVT = N->getValueType(0); 8285 8286 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) { 8287 // Check if the result type doesn't match the inserted element type. A 8288 // SCALAR_TO_VECTOR may truncate the inserted element and the 8289 // EXTRACT_VECTOR_ELT may widen the extracted vector. 8290 SDValue InOp = InVec.getOperand(0); 8291 if (InOp.getValueType() != NVT) { 8292 assert(InOp.getValueType().isInteger() && NVT.isInteger()); 8293 return DAG.getSExtOrTrunc(InOp, InVec.getDebugLoc(), NVT); 8294 } 8295 return InOp; 8296 } 8297 8298 SDValue EltNo = N->getOperand(1); 8299 bool ConstEltNo = isa<ConstantSDNode>(EltNo); 8300 8301 // Transform: (EXTRACT_VECTOR_ELT( VECTOR_SHUFFLE )) -> EXTRACT_VECTOR_ELT. 8302 // We only perform this optimization before the op legalization phase because 8303 // we may introduce new vector instructions which are not backed by TD 8304 // patterns. For example on AVX, extracting elements from a wide vector 8305 // without using extract_subvector. 8306 if (InVec.getOpcode() == ISD::VECTOR_SHUFFLE 8307 && ConstEltNo && !LegalOperations) { 8308 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 8309 int NumElem = VT.getVectorNumElements(); 8310 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(InVec); 8311 // Find the new index to extract from. 8312 int OrigElt = SVOp->getMaskElt(Elt); 8313 8314 // Extracting an undef index is undef. 8315 if (OrigElt == -1) 8316 return DAG.getUNDEF(NVT); 8317 8318 // Select the right vector half to extract from. 8319 if (OrigElt < NumElem) { 8320 InVec = InVec->getOperand(0); 8321 } else { 8322 InVec = InVec->getOperand(1); 8323 OrigElt -= NumElem; 8324 } 8325 8326 EVT IndexTy = N->getOperand(1).getValueType(); 8327 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, N->getDebugLoc(), NVT, 8328 InVec, DAG.getConstant(OrigElt, IndexTy)); 8329 } 8330 8331 // Perform only after legalization to ensure build_vector / vector_shuffle 8332 // optimizations have already been done. 8333 if (!LegalOperations) return SDValue(); 8334 8335 // (vextract (v4f32 load $addr), c) -> (f32 load $addr+c*size) 8336 // (vextract (v4f32 s2v (f32 load $addr)), c) -> (f32 load $addr+c*size) 8337 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), 0) -> (f32 load $addr) 8338 8339 if (ConstEltNo) { 8340 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 8341 bool NewLoad = false; 8342 bool BCNumEltsChanged = false; 8343 EVT ExtVT = VT.getVectorElementType(); 8344 EVT LVT = ExtVT; 8345 8346 // If the result of load has to be truncated, then it's not necessarily 8347 // profitable. 8348 if (NVT.bitsLT(LVT) && !TLI.isTruncateFree(LVT, NVT)) 8349 return SDValue(); 8350 8351 if (InVec.getOpcode() == ISD::BITCAST) { 8352 // Don't duplicate a load with other uses. 8353 if (!InVec.hasOneUse()) 8354 return SDValue(); 8355 8356 EVT BCVT = InVec.getOperand(0).getValueType(); 8357 if (!BCVT.isVector() || ExtVT.bitsGT(BCVT.getVectorElementType())) 8358 return SDValue(); 8359 if (VT.getVectorNumElements() != BCVT.getVectorNumElements()) 8360 BCNumEltsChanged = true; 8361 InVec = InVec.getOperand(0); 8362 ExtVT = BCVT.getVectorElementType(); 8363 NewLoad = true; 8364 } 8365 8366 LoadSDNode *LN0 = NULL; 8367 const ShuffleVectorSDNode *SVN = NULL; 8368 if (ISD::isNormalLoad(InVec.getNode())) { 8369 LN0 = cast<LoadSDNode>(InVec); 8370 } else if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR && 8371 InVec.getOperand(0).getValueType() == ExtVT && 8372 ISD::isNormalLoad(InVec.getOperand(0).getNode())) { 8373 // Don't duplicate a load with other uses. 8374 if (!InVec.hasOneUse()) 8375 return SDValue(); 8376 8377 LN0 = cast<LoadSDNode>(InVec.getOperand(0)); 8378 } else if ((SVN = dyn_cast<ShuffleVectorSDNode>(InVec))) { 8379 // (vextract (vector_shuffle (load $addr), v2, <1, u, u, u>), 1) 8380 // => 8381 // (load $addr+1*size) 8382 8383 // Don't duplicate a load with other uses. 8384 if (!InVec.hasOneUse()) 8385 return SDValue(); 8386 8387 // If the bit convert changed the number of elements, it is unsafe 8388 // to examine the mask. 8389 if (BCNumEltsChanged) 8390 return SDValue(); 8391 8392 // Select the input vector, guarding against out of range extract vector. 8393 unsigned NumElems = VT.getVectorNumElements(); 8394 int Idx = (Elt > (int)NumElems) ? -1 : SVN->getMaskElt(Elt); 8395 InVec = (Idx < (int)NumElems) ? InVec.getOperand(0) : InVec.getOperand(1); 8396 8397 if (InVec.getOpcode() == ISD::BITCAST) { 8398 // Don't duplicate a load with other uses. 8399 if (!InVec.hasOneUse()) 8400 return SDValue(); 8401 8402 InVec = InVec.getOperand(0); 8403 } 8404 if (ISD::isNormalLoad(InVec.getNode())) { 8405 LN0 = cast<LoadSDNode>(InVec); 8406 Elt = (Idx < (int)NumElems) ? Idx : Idx - (int)NumElems; 8407 } 8408 } 8409 8410 // Make sure we found a non-volatile load and the extractelement is 8411 // the only use. 8412 if (!LN0 || !LN0->hasNUsesOfValue(1,0) || LN0->isVolatile()) 8413 return SDValue(); 8414 8415 // If Idx was -1 above, Elt is going to be -1, so just return undef. 8416 if (Elt == -1) 8417 return DAG.getUNDEF(LVT); 8418 8419 unsigned Align = LN0->getAlignment(); 8420 if (NewLoad) { 8421 // Check the resultant load doesn't need a higher alignment than the 8422 // original load. 8423 unsigned NewAlign = 8424 TLI.getDataLayout() 8425 ->getABITypeAlignment(LVT.getTypeForEVT(*DAG.getContext())); 8426 8427 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, LVT)) 8428 return SDValue(); 8429 8430 Align = NewAlign; 8431 } 8432 8433 SDValue NewPtr = LN0->getBasePtr(); 8434 unsigned PtrOff = 0; 8435 8436 if (Elt) { 8437 PtrOff = LVT.getSizeInBits() * Elt / 8; 8438 EVT PtrType = NewPtr.getValueType(); 8439 if (TLI.isBigEndian()) 8440 PtrOff = VT.getSizeInBits() / 8 - PtrOff; 8441 NewPtr = DAG.getNode(ISD::ADD, N->getDebugLoc(), PtrType, NewPtr, 8442 DAG.getConstant(PtrOff, PtrType)); 8443 } 8444 8445 // The replacement we need to do here is a little tricky: we need to 8446 // replace an extractelement of a load with a load. 8447 // Use ReplaceAllUsesOfValuesWith to do the replacement. 8448 // Note that this replacement assumes that the extractvalue is the only 8449 // use of the load; that's okay because we don't want to perform this 8450 // transformation in other cases anyway. 8451 SDValue Load; 8452 SDValue Chain; 8453 if (NVT.bitsGT(LVT)) { 8454 // If the result type of vextract is wider than the load, then issue an 8455 // extending load instead. 8456 ISD::LoadExtType ExtType = TLI.isLoadExtLegal(ISD::ZEXTLOAD, LVT) 8457 ? ISD::ZEXTLOAD : ISD::EXTLOAD; 8458 Load = DAG.getExtLoad(ExtType, N->getDebugLoc(), NVT, LN0->getChain(), 8459 NewPtr, LN0->getPointerInfo().getWithOffset(PtrOff), 8460 LVT, LN0->isVolatile(), LN0->isNonTemporal(),Align); 8461 Chain = Load.getValue(1); 8462 } else { 8463 Load = DAG.getLoad(LVT, N->getDebugLoc(), LN0->getChain(), NewPtr, 8464 LN0->getPointerInfo().getWithOffset(PtrOff), 8465 LN0->isVolatile(), LN0->isNonTemporal(), 8466 LN0->isInvariant(), Align); 8467 Chain = Load.getValue(1); 8468 if (NVT.bitsLT(LVT)) 8469 Load = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), NVT, Load); 8470 else 8471 Load = DAG.getNode(ISD::BITCAST, N->getDebugLoc(), NVT, Load); 8472 } 8473 WorkListRemover DeadNodes(*this); 8474 SDValue From[] = { SDValue(N, 0), SDValue(LN0,1) }; 8475 SDValue To[] = { Load, Chain }; 8476 DAG.ReplaceAllUsesOfValuesWith(From, To, 2); 8477 // Since we're explcitly calling ReplaceAllUses, add the new node to the 8478 // worklist explicitly as well. 8479 AddToWorkList(Load.getNode()); 8480 AddUsersToWorkList(Load.getNode()); // Add users too 8481 // Make sure to revisit this node to clean it up; it will usually be dead. 8482 AddToWorkList(N); 8483 return SDValue(N, 0); 8484 } 8485 8486 return SDValue(); 8487} 8488 8489// Simplify (build_vec (ext )) to (bitcast (build_vec )) 8490SDValue DAGCombiner::reduceBuildVecExtToExtBuildVec(SDNode *N) { 8491 // We perform this optimization post type-legalization because 8492 // the type-legalizer often scalarizes integer-promoted vectors. 8493 // Performing this optimization before may create bit-casts which 8494 // will be type-legalized to complex code sequences. 8495 // We perform this optimization only before the operation legalizer because we 8496 // may introduce illegal operations. 8497 if (Level != AfterLegalizeVectorOps && Level != AfterLegalizeTypes) 8498 return SDValue(); 8499 8500 unsigned NumInScalars = N->getNumOperands(); 8501 DebugLoc dl = N->getDebugLoc(); 8502 EVT VT = N->getValueType(0); 8503 8504 // Check to see if this is a BUILD_VECTOR of a bunch of values 8505 // which come from any_extend or zero_extend nodes. If so, we can create 8506 // a new BUILD_VECTOR using bit-casts which may enable other BUILD_VECTOR 8507 // optimizations. We do not handle sign-extend because we can't fill the sign 8508 // using shuffles. 8509 EVT SourceType = MVT::Other; 8510 bool AllAnyExt = true; 8511 8512 for (unsigned i = 0; i != NumInScalars; ++i) { 8513 SDValue In = N->getOperand(i); 8514 // Ignore undef inputs. 8515 if (In.getOpcode() == ISD::UNDEF) continue; 8516 8517 bool AnyExt = In.getOpcode() == ISD::ANY_EXTEND; 8518 bool ZeroExt = In.getOpcode() == ISD::ZERO_EXTEND; 8519 8520 // Abort if the element is not an extension. 8521 if (!ZeroExt && !AnyExt) { 8522 SourceType = MVT::Other; 8523 break; 8524 } 8525 8526 // The input is a ZeroExt or AnyExt. Check the original type. 8527 EVT InTy = In.getOperand(0).getValueType(); 8528 8529 // Check that all of the widened source types are the same. 8530 if (SourceType == MVT::Other) 8531 // First time. 8532 SourceType = InTy; 8533 else if (InTy != SourceType) { 8534 // Multiple income types. Abort. 8535 SourceType = MVT::Other; 8536 break; 8537 } 8538 8539 // Check if all of the extends are ANY_EXTENDs. 8540 AllAnyExt &= AnyExt; 8541 } 8542 8543 // In order to have valid types, all of the inputs must be extended from the 8544 // same source type and all of the inputs must be any or zero extend. 8545 // Scalar sizes must be a power of two. 8546 EVT OutScalarTy = VT.getScalarType(); 8547 bool ValidTypes = SourceType != MVT::Other && 8548 isPowerOf2_32(OutScalarTy.getSizeInBits()) && 8549 isPowerOf2_32(SourceType.getSizeInBits()); 8550 8551 // Create a new simpler BUILD_VECTOR sequence which other optimizations can 8552 // turn into a single shuffle instruction. 8553 if (!ValidTypes) 8554 return SDValue(); 8555 8556 bool isLE = TLI.isLittleEndian(); 8557 unsigned ElemRatio = OutScalarTy.getSizeInBits()/SourceType.getSizeInBits(); 8558 assert(ElemRatio > 1 && "Invalid element size ratio"); 8559 SDValue Filler = AllAnyExt ? DAG.getUNDEF(SourceType): 8560 DAG.getConstant(0, SourceType); 8561 8562 unsigned NewBVElems = ElemRatio * VT.getVectorNumElements(); 8563 SmallVector<SDValue, 8> Ops(NewBVElems, Filler); 8564 8565 // Populate the new build_vector 8566 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { 8567 SDValue Cast = N->getOperand(i); 8568 assert((Cast.getOpcode() == ISD::ANY_EXTEND || 8569 Cast.getOpcode() == ISD::ZERO_EXTEND || 8570 Cast.getOpcode() == ISD::UNDEF) && "Invalid cast opcode"); 8571 SDValue In; 8572 if (Cast.getOpcode() == ISD::UNDEF) 8573 In = DAG.getUNDEF(SourceType); 8574 else 8575 In = Cast->getOperand(0); 8576 unsigned Index = isLE ? (i * ElemRatio) : 8577 (i * ElemRatio + (ElemRatio - 1)); 8578 8579 assert(Index < Ops.size() && "Invalid index"); 8580 Ops[Index] = In; 8581 } 8582 8583 // The type of the new BUILD_VECTOR node. 8584 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), SourceType, NewBVElems); 8585 assert(VecVT.getSizeInBits() == VT.getSizeInBits() && 8586 "Invalid vector size"); 8587 // Check if the new vector type is legal. 8588 if (!isTypeLegal(VecVT)) return SDValue(); 8589 8590 // Make the new BUILD_VECTOR. 8591 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VecVT, &Ops[0], Ops.size()); 8592 8593 // The new BUILD_VECTOR node has the potential to be further optimized. 8594 AddToWorkList(BV.getNode()); 8595 // Bitcast to the desired type. 8596 return DAG.getNode(ISD::BITCAST, dl, VT, BV); 8597} 8598 8599SDValue DAGCombiner::reduceBuildVecConvertToConvertBuildVec(SDNode *N) { 8600 EVT VT = N->getValueType(0); 8601 8602 unsigned NumInScalars = N->getNumOperands(); 8603 DebugLoc dl = N->getDebugLoc(); 8604 8605 EVT SrcVT = MVT::Other; 8606 unsigned Opcode = ISD::DELETED_NODE; 8607 unsigned NumDefs = 0; 8608 8609 for (unsigned i = 0; i != NumInScalars; ++i) { 8610 SDValue In = N->getOperand(i); 8611 unsigned Opc = In.getOpcode(); 8612 8613 if (Opc == ISD::UNDEF) 8614 continue; 8615 8616 // If all scalar values are floats and converted from integers. 8617 if (Opcode == ISD::DELETED_NODE && 8618 (Opc == ISD::UINT_TO_FP || Opc == ISD::SINT_TO_FP)) { 8619 Opcode = Opc; 8620 // If not supported by target, bail out. 8621 if (TLI.getOperationAction(Opcode, VT) != TargetLowering::Legal && 8622 TLI.getOperationAction(Opcode, VT) != TargetLowering::Custom) 8623 return SDValue(); 8624 } 8625 if (Opc != Opcode) 8626 return SDValue(); 8627 8628 EVT InVT = In.getOperand(0).getValueType(); 8629 8630 // If all scalar values are typed differently, bail out. It's chosen to 8631 // simplify BUILD_VECTOR of integer types. 8632 if (SrcVT == MVT::Other) 8633 SrcVT = InVT; 8634 if (SrcVT != InVT) 8635 return SDValue(); 8636 NumDefs++; 8637 } 8638 8639 // If the vector has just one element defined, it's not worth to fold it into 8640 // a vectorized one. 8641 if (NumDefs < 2) 8642 return SDValue(); 8643 8644 assert((Opcode == ISD::UINT_TO_FP || Opcode == ISD::SINT_TO_FP) 8645 && "Should only handle conversion from integer to float."); 8646 assert(SrcVT != MVT::Other && "Cannot determine source type!"); 8647 8648 EVT NVT = EVT::getVectorVT(*DAG.getContext(), SrcVT, NumInScalars); 8649 SmallVector<SDValue, 8> Opnds; 8650 for (unsigned i = 0; i != NumInScalars; ++i) { 8651 SDValue In = N->getOperand(i); 8652 8653 if (In.getOpcode() == ISD::UNDEF) 8654 Opnds.push_back(DAG.getUNDEF(SrcVT)); 8655 else 8656 Opnds.push_back(In.getOperand(0)); 8657 } 8658 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, 8659 &Opnds[0], Opnds.size()); 8660 AddToWorkList(BV.getNode()); 8661 8662 return DAG.getNode(Opcode, dl, VT, BV); 8663} 8664 8665SDValue DAGCombiner::visitBUILD_VECTOR(SDNode *N) { 8666 unsigned NumInScalars = N->getNumOperands(); 8667 DebugLoc dl = N->getDebugLoc(); 8668 EVT VT = N->getValueType(0); 8669 8670 // A vector built entirely of undefs is undef. 8671 if (ISD::allOperandsUndef(N)) 8672 return DAG.getUNDEF(VT); 8673 8674 SDValue V = reduceBuildVecExtToExtBuildVec(N); 8675 if (V.getNode()) 8676 return V; 8677 8678 V = reduceBuildVecConvertToConvertBuildVec(N); 8679 if (V.getNode()) 8680 return V; 8681 8682 // Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT 8683 // operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from 8684 // at most two distinct vectors, turn this into a shuffle node. 8685 8686 // May only combine to shuffle after legalize if shuffle is legal. 8687 if (LegalOperations && 8688 !TLI.isOperationLegalOrCustom(ISD::VECTOR_SHUFFLE, VT)) 8689 return SDValue(); 8690 8691 SDValue VecIn1, VecIn2; 8692 for (unsigned i = 0; i != NumInScalars; ++i) { 8693 // Ignore undef inputs. 8694 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 8695 8696 // If this input is something other than a EXTRACT_VECTOR_ELT with a 8697 // constant index, bail out. 8698 if (N->getOperand(i).getOpcode() != ISD::EXTRACT_VECTOR_ELT || 8699 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) { 8700 VecIn1 = VecIn2 = SDValue(0, 0); 8701 break; 8702 } 8703 8704 // We allow up to two distinct input vectors. 8705 SDValue ExtractedFromVec = N->getOperand(i).getOperand(0); 8706 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2) 8707 continue; 8708 8709 if (VecIn1.getNode() == 0) { 8710 VecIn1 = ExtractedFromVec; 8711 } else if (VecIn2.getNode() == 0) { 8712 VecIn2 = ExtractedFromVec; 8713 } else { 8714 // Too many inputs. 8715 VecIn1 = VecIn2 = SDValue(0, 0); 8716 break; 8717 } 8718 } 8719 8720 // If everything is good, we can make a shuffle operation. 8721 if (VecIn1.getNode()) { 8722 SmallVector<int, 8> Mask; 8723 for (unsigned i = 0; i != NumInScalars; ++i) { 8724 if (N->getOperand(i).getOpcode() == ISD::UNDEF) { 8725 Mask.push_back(-1); 8726 continue; 8727 } 8728 8729 // If extracting from the first vector, just use the index directly. 8730 SDValue Extract = N->getOperand(i); 8731 SDValue ExtVal = Extract.getOperand(1); 8732 if (Extract.getOperand(0) == VecIn1) { 8733 unsigned ExtIndex = cast<ConstantSDNode>(ExtVal)->getZExtValue(); 8734 if (ExtIndex > VT.getVectorNumElements()) 8735 return SDValue(); 8736 8737 Mask.push_back(ExtIndex); 8738 continue; 8739 } 8740 8741 // Otherwise, use InIdx + VecSize 8742 unsigned Idx = cast<ConstantSDNode>(ExtVal)->getZExtValue(); 8743 Mask.push_back(Idx+NumInScalars); 8744 } 8745 8746 // We can't generate a shuffle node with mismatched input and output types. 8747 // Attempt to transform a single input vector to the correct type. 8748 if ((VT != VecIn1.getValueType())) { 8749 // We don't support shuffeling between TWO values of different types. 8750 if (VecIn2.getNode() != 0) 8751 return SDValue(); 8752 8753 // We only support widening of vectors which are half the size of the 8754 // output registers. For example XMM->YMM widening on X86 with AVX. 8755 if (VecIn1.getValueType().getSizeInBits()*2 != VT.getSizeInBits()) 8756 return SDValue(); 8757 8758 // If the input vector type has a different base type to the output 8759 // vector type, bail out. 8760 if (VecIn1.getValueType().getVectorElementType() != 8761 VT.getVectorElementType()) 8762 return SDValue(); 8763 8764 // Widen the input vector by adding undef values. 8765 VecIn1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, 8766 VecIn1, DAG.getUNDEF(VecIn1.getValueType())); 8767 } 8768 8769 // If VecIn2 is unused then change it to undef. 8770 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT); 8771 8772 // Check that we were able to transform all incoming values to the same 8773 // type. 8774 if (VecIn2.getValueType() != VecIn1.getValueType() || 8775 VecIn1.getValueType() != VT) 8776 return SDValue(); 8777 8778 // Only type-legal BUILD_VECTOR nodes are converted to shuffle nodes. 8779 if (!isTypeLegal(VT)) 8780 return SDValue(); 8781 8782 // Return the new VECTOR_SHUFFLE node. 8783 SDValue Ops[2]; 8784 Ops[0] = VecIn1; 8785 Ops[1] = VecIn2; 8786 return DAG.getVectorShuffle(VT, dl, Ops[0], Ops[1], &Mask[0]); 8787 } 8788 8789 return SDValue(); 8790} 8791 8792SDValue DAGCombiner::visitCONCAT_VECTORS(SDNode *N) { 8793 // TODO: Check to see if this is a CONCAT_VECTORS of a bunch of 8794 // EXTRACT_SUBVECTOR operations. If so, and if the EXTRACT_SUBVECTOR vector 8795 // inputs come from at most two distinct vectors, turn this into a shuffle 8796 // node. 8797 8798 // If we only have one input vector, we don't need to do any concatenation. 8799 if (N->getNumOperands() == 1) 8800 return N->getOperand(0); 8801 8802 // Check if all of the operands are undefs. 8803 if (ISD::allOperandsUndef(N)) 8804 return DAG.getUNDEF(N->getValueType(0)); 8805 8806 return SDValue(); 8807} 8808 8809SDValue DAGCombiner::visitEXTRACT_SUBVECTOR(SDNode* N) { 8810 EVT NVT = N->getValueType(0); 8811 SDValue V = N->getOperand(0); 8812 8813 if (V->getOpcode() == ISD::INSERT_SUBVECTOR) { 8814 // Handle only simple case where vector being inserted and vector 8815 // being extracted are of same type, and are half size of larger vectors. 8816 EVT BigVT = V->getOperand(0).getValueType(); 8817 EVT SmallVT = V->getOperand(1).getValueType(); 8818 if (NVT != SmallVT || NVT.getSizeInBits()*2 != BigVT.getSizeInBits()) 8819 return SDValue(); 8820 8821 // Only handle cases where both indexes are constants with the same type. 8822 ConstantSDNode *ExtIdx = dyn_cast<ConstantSDNode>(N->getOperand(1)); 8823 ConstantSDNode *InsIdx = dyn_cast<ConstantSDNode>(V->getOperand(2)); 8824 8825 if (InsIdx && ExtIdx && 8826 InsIdx->getValueType(0).getSizeInBits() <= 64 && 8827 ExtIdx->getValueType(0).getSizeInBits() <= 64) { 8828 // Combine: 8829 // (extract_subvec (insert_subvec V1, V2, InsIdx), ExtIdx) 8830 // Into: 8831 // indices are equal => V1 8832 // otherwise => (extract_subvec V1, ExtIdx) 8833 if (InsIdx->getZExtValue() == ExtIdx->getZExtValue()) 8834 return V->getOperand(1); 8835 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, N->getDebugLoc(), NVT, 8836 V->getOperand(0), N->getOperand(1)); 8837 } 8838 } 8839 8840 if (V->getOpcode() == ISD::CONCAT_VECTORS) { 8841 // Combine: 8842 // (extract_subvec (concat V1, V2, ...), i) 8843 // Into: 8844 // Vi if possible 8845 // Only operand 0 is checked as 'concat' assumes all inputs of the same type. 8846 if (V->getOperand(0).getValueType() != NVT) 8847 return SDValue(); 8848 unsigned Idx = dyn_cast<ConstantSDNode>(N->getOperand(1))->getZExtValue(); 8849 unsigned NumElems = NVT.getVectorNumElements(); 8850 assert((Idx % NumElems) == 0 && 8851 "IDX in concat is not a multiple of the result vector length."); 8852 return V->getOperand(Idx / NumElems); 8853 } 8854 8855 return SDValue(); 8856} 8857 8858SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) { 8859 EVT VT = N->getValueType(0); 8860 unsigned NumElts = VT.getVectorNumElements(); 8861 8862 SDValue N0 = N->getOperand(0); 8863 SDValue N1 = N->getOperand(1); 8864 8865 assert(N0.getValueType() == VT && "Vector shuffle must be normalized in DAG"); 8866 8867 // Canonicalize shuffle undef, undef -> undef 8868 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF) 8869 return DAG.getUNDEF(VT); 8870 8871 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N); 8872 8873 // Canonicalize shuffle v, v -> v, undef 8874 if (N0 == N1) { 8875 SmallVector<int, 8> NewMask; 8876 for (unsigned i = 0; i != NumElts; ++i) { 8877 int Idx = SVN->getMaskElt(i); 8878 if (Idx >= (int)NumElts) Idx -= NumElts; 8879 NewMask.push_back(Idx); 8880 } 8881 return DAG.getVectorShuffle(VT, N->getDebugLoc(), N0, DAG.getUNDEF(VT), 8882 &NewMask[0]); 8883 } 8884 8885 // Canonicalize shuffle undef, v -> v, undef. Commute the shuffle mask. 8886 if (N0.getOpcode() == ISD::UNDEF) { 8887 SmallVector<int, 8> NewMask; 8888 for (unsigned i = 0; i != NumElts; ++i) { 8889 int Idx = SVN->getMaskElt(i); 8890 if (Idx >= 0) { 8891 if (Idx < (int)NumElts) 8892 Idx += NumElts; 8893 else 8894 Idx -= NumElts; 8895 } 8896 NewMask.push_back(Idx); 8897 } 8898 return DAG.getVectorShuffle(VT, N->getDebugLoc(), N1, DAG.getUNDEF(VT), 8899 &NewMask[0]); 8900 } 8901 8902 // Remove references to rhs if it is undef 8903 if (N1.getOpcode() == ISD::UNDEF) { 8904 bool Changed = false; 8905 SmallVector<int, 8> NewMask; 8906 for (unsigned i = 0; i != NumElts; ++i) { 8907 int Idx = SVN->getMaskElt(i); 8908 if (Idx >= (int)NumElts) { 8909 Idx = -1; 8910 Changed = true; 8911 } 8912 NewMask.push_back(Idx); 8913 } 8914 if (Changed) 8915 return DAG.getVectorShuffle(VT, N->getDebugLoc(), N0, N1, &NewMask[0]); 8916 } 8917 8918 // If it is a splat, check if the argument vector is another splat or a 8919 // build_vector with all scalar elements the same. 8920 if (SVN->isSplat() && SVN->getSplatIndex() < (int)NumElts) { 8921 SDNode *V = N0.getNode(); 8922 8923 // If this is a bit convert that changes the element type of the vector but 8924 // not the number of vector elements, look through it. Be careful not to 8925 // look though conversions that change things like v4f32 to v2f64. 8926 if (V->getOpcode() == ISD::BITCAST) { 8927 SDValue ConvInput = V->getOperand(0); 8928 if (ConvInput.getValueType().isVector() && 8929 ConvInput.getValueType().getVectorNumElements() == NumElts) 8930 V = ConvInput.getNode(); 8931 } 8932 8933 if (V->getOpcode() == ISD::BUILD_VECTOR) { 8934 assert(V->getNumOperands() == NumElts && 8935 "BUILD_VECTOR has wrong number of operands"); 8936 SDValue Base; 8937 bool AllSame = true; 8938 for (unsigned i = 0; i != NumElts; ++i) { 8939 if (V->getOperand(i).getOpcode() != ISD::UNDEF) { 8940 Base = V->getOperand(i); 8941 break; 8942 } 8943 } 8944 // Splat of <u, u, u, u>, return <u, u, u, u> 8945 if (!Base.getNode()) 8946 return N0; 8947 for (unsigned i = 0; i != NumElts; ++i) { 8948 if (V->getOperand(i) != Base) { 8949 AllSame = false; 8950 break; 8951 } 8952 } 8953 // Splat of <x, x, x, x>, return <x, x, x, x> 8954 if (AllSame) 8955 return N0; 8956 } 8957 } 8958 8959 // If this shuffle node is simply a swizzle of another shuffle node, 8960 // and it reverses the swizzle of the previous shuffle then we can 8961 // optimize shuffle(shuffle(x, undef), undef) -> x. 8962 if (N0.getOpcode() == ISD::VECTOR_SHUFFLE && Level < AfterLegalizeDAG && 8963 N1.getOpcode() == ISD::UNDEF) { 8964 8965 ShuffleVectorSDNode *OtherSV = cast<ShuffleVectorSDNode>(N0); 8966 8967 // Shuffle nodes can only reverse shuffles with a single non-undef value. 8968 if (N0.getOperand(1).getOpcode() != ISD::UNDEF) 8969 return SDValue(); 8970 8971 // The incoming shuffle must be of the same type as the result of the 8972 // current shuffle. 8973 assert(OtherSV->getOperand(0).getValueType() == VT && 8974 "Shuffle types don't match"); 8975 8976 for (unsigned i = 0; i != NumElts; ++i) { 8977 int Idx = SVN->getMaskElt(i); 8978 assert(Idx < (int)NumElts && "Index references undef operand"); 8979 // Next, this index comes from the first value, which is the incoming 8980 // shuffle. Adopt the incoming index. 8981 if (Idx >= 0) 8982 Idx = OtherSV->getMaskElt(Idx); 8983 8984 // The combined shuffle must map each index to itself. 8985 if (Idx >= 0 && (unsigned)Idx != i) 8986 return SDValue(); 8987 } 8988 8989 return OtherSV->getOperand(0); 8990 } 8991 8992 return SDValue(); 8993} 8994 8995SDValue DAGCombiner::visitMEMBARRIER(SDNode* N) { 8996 if (!TLI.getShouldFoldAtomicFences()) 8997 return SDValue(); 8998 8999 SDValue atomic = N->getOperand(0); 9000 switch (atomic.getOpcode()) { 9001 case ISD::ATOMIC_CMP_SWAP: 9002 case ISD::ATOMIC_SWAP: 9003 case ISD::ATOMIC_LOAD_ADD: 9004 case ISD::ATOMIC_LOAD_SUB: 9005 case ISD::ATOMIC_LOAD_AND: 9006 case ISD::ATOMIC_LOAD_OR: 9007 case ISD::ATOMIC_LOAD_XOR: 9008 case ISD::ATOMIC_LOAD_NAND: 9009 case ISD::ATOMIC_LOAD_MIN: 9010 case ISD::ATOMIC_LOAD_MAX: 9011 case ISD::ATOMIC_LOAD_UMIN: 9012 case ISD::ATOMIC_LOAD_UMAX: 9013 break; 9014 default: 9015 return SDValue(); 9016 } 9017 9018 SDValue fence = atomic.getOperand(0); 9019 if (fence.getOpcode() != ISD::MEMBARRIER) 9020 return SDValue(); 9021 9022 switch (atomic.getOpcode()) { 9023 case ISD::ATOMIC_CMP_SWAP: 9024 return SDValue(DAG.UpdateNodeOperands(atomic.getNode(), 9025 fence.getOperand(0), 9026 atomic.getOperand(1), atomic.getOperand(2), 9027 atomic.getOperand(3)), atomic.getResNo()); 9028 case ISD::ATOMIC_SWAP: 9029 case ISD::ATOMIC_LOAD_ADD: 9030 case ISD::ATOMIC_LOAD_SUB: 9031 case ISD::ATOMIC_LOAD_AND: 9032 case ISD::ATOMIC_LOAD_OR: 9033 case ISD::ATOMIC_LOAD_XOR: 9034 case ISD::ATOMIC_LOAD_NAND: 9035 case ISD::ATOMIC_LOAD_MIN: 9036 case ISD::ATOMIC_LOAD_MAX: 9037 case ISD::ATOMIC_LOAD_UMIN: 9038 case ISD::ATOMIC_LOAD_UMAX: 9039 return SDValue(DAG.UpdateNodeOperands(atomic.getNode(), 9040 fence.getOperand(0), 9041 atomic.getOperand(1), atomic.getOperand(2)), 9042 atomic.getResNo()); 9043 default: 9044 return SDValue(); 9045 } 9046} 9047 9048/// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform 9049/// an AND to a vector_shuffle with the destination vector and a zero vector. 9050/// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==> 9051/// vector_shuffle V, Zero, <0, 4, 2, 4> 9052SDValue DAGCombiner::XformToShuffleWithZero(SDNode *N) { 9053 EVT VT = N->getValueType(0); 9054 DebugLoc dl = N->getDebugLoc(); 9055 SDValue LHS = N->getOperand(0); 9056 SDValue RHS = N->getOperand(1); 9057 if (N->getOpcode() == ISD::AND) { 9058 if (RHS.getOpcode() == ISD::BITCAST) 9059 RHS = RHS.getOperand(0); 9060 if (RHS.getOpcode() == ISD::BUILD_VECTOR) { 9061 SmallVector<int, 8> Indices; 9062 unsigned NumElts = RHS.getNumOperands(); 9063 for (unsigned i = 0; i != NumElts; ++i) { 9064 SDValue Elt = RHS.getOperand(i); 9065 if (!isa<ConstantSDNode>(Elt)) 9066 return SDValue(); 9067 9068 if (cast<ConstantSDNode>(Elt)->isAllOnesValue()) 9069 Indices.push_back(i); 9070 else if (cast<ConstantSDNode>(Elt)->isNullValue()) 9071 Indices.push_back(NumElts); 9072 else 9073 return SDValue(); 9074 } 9075 9076 // Let's see if the target supports this vector_shuffle. 9077 EVT RVT = RHS.getValueType(); 9078 if (!TLI.isVectorClearMaskLegal(Indices, RVT)) 9079 return SDValue(); 9080 9081 // Return the new VECTOR_SHUFFLE node. 9082 EVT EltVT = RVT.getVectorElementType(); 9083 SmallVector<SDValue,8> ZeroOps(RVT.getVectorNumElements(), 9084 DAG.getConstant(0, EltVT)); 9085 SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 9086 RVT, &ZeroOps[0], ZeroOps.size()); 9087 LHS = DAG.getNode(ISD::BITCAST, dl, RVT, LHS); 9088 SDValue Shuf = DAG.getVectorShuffle(RVT, dl, LHS, Zero, &Indices[0]); 9089 return DAG.getNode(ISD::BITCAST, dl, VT, Shuf); 9090 } 9091 } 9092 9093 return SDValue(); 9094} 9095 9096/// SimplifyVBinOp - Visit a binary vector operation, like ADD. 9097SDValue DAGCombiner::SimplifyVBinOp(SDNode *N) { 9098 // After legalize, the target may be depending on adds and other 9099 // binary ops to provide legal ways to construct constants or other 9100 // things. Simplifying them may result in a loss of legality. 9101 if (LegalOperations) return SDValue(); 9102 9103 assert(N->getValueType(0).isVector() && 9104 "SimplifyVBinOp only works on vectors!"); 9105 9106 SDValue LHS = N->getOperand(0); 9107 SDValue RHS = N->getOperand(1); 9108 SDValue Shuffle = XformToShuffleWithZero(N); 9109 if (Shuffle.getNode()) return Shuffle; 9110 9111 // If the LHS and RHS are BUILD_VECTOR nodes, see if we can constant fold 9112 // this operation. 9113 if (LHS.getOpcode() == ISD::BUILD_VECTOR && 9114 RHS.getOpcode() == ISD::BUILD_VECTOR) { 9115 SmallVector<SDValue, 8> Ops; 9116 for (unsigned i = 0, e = LHS.getNumOperands(); i != e; ++i) { 9117 SDValue LHSOp = LHS.getOperand(i); 9118 SDValue RHSOp = RHS.getOperand(i); 9119 // If these two elements can't be folded, bail out. 9120 if ((LHSOp.getOpcode() != ISD::UNDEF && 9121 LHSOp.getOpcode() != ISD::Constant && 9122 LHSOp.getOpcode() != ISD::ConstantFP) || 9123 (RHSOp.getOpcode() != ISD::UNDEF && 9124 RHSOp.getOpcode() != ISD::Constant && 9125 RHSOp.getOpcode() != ISD::ConstantFP)) 9126 break; 9127 9128 // Can't fold divide by zero. 9129 if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV || 9130 N->getOpcode() == ISD::FDIV) { 9131 if ((RHSOp.getOpcode() == ISD::Constant && 9132 cast<ConstantSDNode>(RHSOp.getNode())->isNullValue()) || 9133 (RHSOp.getOpcode() == ISD::ConstantFP && 9134 cast<ConstantFPSDNode>(RHSOp.getNode())->getValueAPF().isZero())) 9135 break; 9136 } 9137 9138 EVT VT = LHSOp.getValueType(); 9139 EVT RVT = RHSOp.getValueType(); 9140 if (RVT != VT) { 9141 // Integer BUILD_VECTOR operands may have types larger than the element 9142 // size (e.g., when the element type is not legal). Prior to type 9143 // legalization, the types may not match between the two BUILD_VECTORS. 9144 // Truncate one of the operands to make them match. 9145 if (RVT.getSizeInBits() > VT.getSizeInBits()) { 9146 RHSOp = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, RHSOp); 9147 } else { 9148 LHSOp = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), RVT, LHSOp); 9149 VT = RVT; 9150 } 9151 } 9152 SDValue FoldOp = DAG.getNode(N->getOpcode(), LHS.getDebugLoc(), VT, 9153 LHSOp, RHSOp); 9154 if (FoldOp.getOpcode() != ISD::UNDEF && 9155 FoldOp.getOpcode() != ISD::Constant && 9156 FoldOp.getOpcode() != ISD::ConstantFP) 9157 break; 9158 Ops.push_back(FoldOp); 9159 AddToWorkList(FoldOp.getNode()); 9160 } 9161 9162 if (Ops.size() == LHS.getNumOperands()) 9163 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 9164 LHS.getValueType(), &Ops[0], Ops.size()); 9165 } 9166 9167 return SDValue(); 9168} 9169 9170/// SimplifyVUnaryOp - Visit a binary vector operation, like FABS/FNEG. 9171SDValue DAGCombiner::SimplifyVUnaryOp(SDNode *N) { 9172 // After legalize, the target may be depending on adds and other 9173 // binary ops to provide legal ways to construct constants or other 9174 // things. Simplifying them may result in a loss of legality. 9175 if (LegalOperations) return SDValue(); 9176 9177 assert(N->getValueType(0).isVector() && 9178 "SimplifyVUnaryOp only works on vectors!"); 9179 9180 SDValue N0 = N->getOperand(0); 9181 9182 if (N0.getOpcode() != ISD::BUILD_VECTOR) 9183 return SDValue(); 9184 9185 // Operand is a BUILD_VECTOR node, see if we can constant fold it. 9186 SmallVector<SDValue, 8> Ops; 9187 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i) { 9188 SDValue Op = N0.getOperand(i); 9189 if (Op.getOpcode() != ISD::UNDEF && 9190 Op.getOpcode() != ISD::ConstantFP) 9191 break; 9192 EVT EltVT = Op.getValueType(); 9193 SDValue FoldOp = DAG.getNode(N->getOpcode(), N0.getDebugLoc(), EltVT, Op); 9194 if (FoldOp.getOpcode() != ISD::UNDEF && 9195 FoldOp.getOpcode() != ISD::ConstantFP) 9196 break; 9197 Ops.push_back(FoldOp); 9198 AddToWorkList(FoldOp.getNode()); 9199 } 9200 9201 if (Ops.size() != N0.getNumOperands()) 9202 return SDValue(); 9203 9204 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 9205 N0.getValueType(), &Ops[0], Ops.size()); 9206} 9207 9208SDValue DAGCombiner::SimplifySelect(DebugLoc DL, SDValue N0, 9209 SDValue N1, SDValue N2){ 9210 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!"); 9211 9212 SDValue SCC = SimplifySelectCC(DL, N0.getOperand(0), N0.getOperand(1), N1, N2, 9213 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 9214 9215 // If we got a simplified select_cc node back from SimplifySelectCC, then 9216 // break it down into a new SETCC node, and a new SELECT node, and then return 9217 // the SELECT node, since we were called with a SELECT node. 9218 if (SCC.getNode()) { 9219 // Check to see if we got a select_cc back (to turn into setcc/select). 9220 // Otherwise, just return whatever node we got back, like fabs. 9221 if (SCC.getOpcode() == ISD::SELECT_CC) { 9222 SDValue SETCC = DAG.getNode(ISD::SETCC, N0.getDebugLoc(), 9223 N0.getValueType(), 9224 SCC.getOperand(0), SCC.getOperand(1), 9225 SCC.getOperand(4)); 9226 AddToWorkList(SETCC.getNode()); 9227 return DAG.getNode(ISD::SELECT, SCC.getDebugLoc(), SCC.getValueType(), 9228 SCC.getOperand(2), SCC.getOperand(3), SETCC); 9229 } 9230 9231 return SCC; 9232 } 9233 return SDValue(); 9234} 9235 9236/// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS 9237/// are the two values being selected between, see if we can simplify the 9238/// select. Callers of this should assume that TheSelect is deleted if this 9239/// returns true. As such, they should return the appropriate thing (e.g. the 9240/// node) back to the top-level of the DAG combiner loop to avoid it being 9241/// looked at. 9242bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDValue LHS, 9243 SDValue RHS) { 9244 9245 // Cannot simplify select with vector condition 9246 if (TheSelect->getOperand(0).getValueType().isVector()) return false; 9247 9248 // If this is a select from two identical things, try to pull the operation 9249 // through the select. 9250 if (LHS.getOpcode() != RHS.getOpcode() || 9251 !LHS.hasOneUse() || !RHS.hasOneUse()) 9252 return false; 9253 9254 // If this is a load and the token chain is identical, replace the select 9255 // of two loads with a load through a select of the address to load from. 9256 // This triggers in things like "select bool X, 10.0, 123.0" after the FP 9257 // constants have been dropped into the constant pool. 9258 if (LHS.getOpcode() == ISD::LOAD) { 9259 LoadSDNode *LLD = cast<LoadSDNode>(LHS); 9260 LoadSDNode *RLD = cast<LoadSDNode>(RHS); 9261 9262 // Token chains must be identical. 9263 if (LHS.getOperand(0) != RHS.getOperand(0) || 9264 // Do not let this transformation reduce the number of volatile loads. 9265 LLD->isVolatile() || RLD->isVolatile() || 9266 // If this is an EXTLOAD, the VT's must match. 9267 LLD->getMemoryVT() != RLD->getMemoryVT() || 9268 // If this is an EXTLOAD, the kind of extension must match. 9269 (LLD->getExtensionType() != RLD->getExtensionType() && 9270 // The only exception is if one of the extensions is anyext. 9271 LLD->getExtensionType() != ISD::EXTLOAD && 9272 RLD->getExtensionType() != ISD::EXTLOAD) || 9273 // FIXME: this discards src value information. This is 9274 // over-conservative. It would be beneficial to be able to remember 9275 // both potential memory locations. Since we are discarding 9276 // src value info, don't do the transformation if the memory 9277 // locations are not in the default address space. 9278 LLD->getPointerInfo().getAddrSpace() != 0 || 9279 RLD->getPointerInfo().getAddrSpace() != 0) 9280 return false; 9281 9282 // Check that the select condition doesn't reach either load. If so, 9283 // folding this will induce a cycle into the DAG. If not, this is safe to 9284 // xform, so create a select of the addresses. 9285 SDValue Addr; 9286 if (TheSelect->getOpcode() == ISD::SELECT) { 9287 SDNode *CondNode = TheSelect->getOperand(0).getNode(); 9288 if ((LLD->hasAnyUseOfValue(1) && LLD->isPredecessorOf(CondNode)) || 9289 (RLD->hasAnyUseOfValue(1) && RLD->isPredecessorOf(CondNode))) 9290 return false; 9291 // The loads must not depend on one another. 9292 if (LLD->isPredecessorOf(RLD) || 9293 RLD->isPredecessorOf(LLD)) 9294 return false; 9295 Addr = DAG.getNode(ISD::SELECT, TheSelect->getDebugLoc(), 9296 LLD->getBasePtr().getValueType(), 9297 TheSelect->getOperand(0), LLD->getBasePtr(), 9298 RLD->getBasePtr()); 9299 } else { // Otherwise SELECT_CC 9300 SDNode *CondLHS = TheSelect->getOperand(0).getNode(); 9301 SDNode *CondRHS = TheSelect->getOperand(1).getNode(); 9302 9303 if ((LLD->hasAnyUseOfValue(1) && 9304 (LLD->isPredecessorOf(CondLHS) || LLD->isPredecessorOf(CondRHS))) || 9305 (RLD->hasAnyUseOfValue(1) && 9306 (RLD->isPredecessorOf(CondLHS) || RLD->isPredecessorOf(CondRHS)))) 9307 return false; 9308 9309 Addr = DAG.getNode(ISD::SELECT_CC, TheSelect->getDebugLoc(), 9310 LLD->getBasePtr().getValueType(), 9311 TheSelect->getOperand(0), 9312 TheSelect->getOperand(1), 9313 LLD->getBasePtr(), RLD->getBasePtr(), 9314 TheSelect->getOperand(4)); 9315 } 9316 9317 SDValue Load; 9318 if (LLD->getExtensionType() == ISD::NON_EXTLOAD) { 9319 Load = DAG.getLoad(TheSelect->getValueType(0), 9320 TheSelect->getDebugLoc(), 9321 // FIXME: Discards pointer info. 9322 LLD->getChain(), Addr, MachinePointerInfo(), 9323 LLD->isVolatile(), LLD->isNonTemporal(), 9324 LLD->isInvariant(), LLD->getAlignment()); 9325 } else { 9326 Load = DAG.getExtLoad(LLD->getExtensionType() == ISD::EXTLOAD ? 9327 RLD->getExtensionType() : LLD->getExtensionType(), 9328 TheSelect->getDebugLoc(), 9329 TheSelect->getValueType(0), 9330 // FIXME: Discards pointer info. 9331 LLD->getChain(), Addr, MachinePointerInfo(), 9332 LLD->getMemoryVT(), LLD->isVolatile(), 9333 LLD->isNonTemporal(), LLD->getAlignment()); 9334 } 9335 9336 // Users of the select now use the result of the load. 9337 CombineTo(TheSelect, Load); 9338 9339 // Users of the old loads now use the new load's chain. We know the 9340 // old-load value is dead now. 9341 CombineTo(LHS.getNode(), Load.getValue(0), Load.getValue(1)); 9342 CombineTo(RHS.getNode(), Load.getValue(0), Load.getValue(1)); 9343 return true; 9344 } 9345 9346 return false; 9347} 9348 9349/// SimplifySelectCC - Simplify an expression of the form (N0 cond N1) ? N2 : N3 9350/// where 'cond' is the comparison specified by CC. 9351SDValue DAGCombiner::SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, 9352 SDValue N2, SDValue N3, 9353 ISD::CondCode CC, bool NotExtCompare) { 9354 // (x ? y : y) -> y. 9355 if (N2 == N3) return N2; 9356 9357 EVT VT = N2.getValueType(); 9358 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 9359 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode()); 9360 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.getNode()); 9361 9362 // Determine if the condition we're dealing with is constant 9363 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()), 9364 N0, N1, CC, DL, false); 9365 if (SCC.getNode()) AddToWorkList(SCC.getNode()); 9366 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode()); 9367 9368 // fold select_cc true, x, y -> x 9369 if (SCCC && !SCCC->isNullValue()) 9370 return N2; 9371 // fold select_cc false, x, y -> y 9372 if (SCCC && SCCC->isNullValue()) 9373 return N3; 9374 9375 // Check to see if we can simplify the select into an fabs node 9376 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) { 9377 // Allow either -0.0 or 0.0 9378 if (CFP->getValueAPF().isZero()) { 9379 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs 9380 if ((CC == ISD::SETGE || CC == ISD::SETGT) && 9381 N0 == N2 && N3.getOpcode() == ISD::FNEG && 9382 N2 == N3.getOperand(0)) 9383 return DAG.getNode(ISD::FABS, DL, VT, N0); 9384 9385 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs 9386 if ((CC == ISD::SETLT || CC == ISD::SETLE) && 9387 N0 == N3 && N2.getOpcode() == ISD::FNEG && 9388 N2.getOperand(0) == N3) 9389 return DAG.getNode(ISD::FABS, DL, VT, N3); 9390 } 9391 } 9392 9393 // Turn "(a cond b) ? 1.0f : 2.0f" into "load (tmp + ((a cond b) ? 0 : 4)" 9394 // where "tmp" is a constant pool entry containing an array with 1.0 and 2.0 9395 // in it. This is a win when the constant is not otherwise available because 9396 // it replaces two constant pool loads with one. We only do this if the FP 9397 // type is known to be legal, because if it isn't, then we are before legalize 9398 // types an we want the other legalization to happen first (e.g. to avoid 9399 // messing with soft float) and if the ConstantFP is not legal, because if 9400 // it is legal, we may not need to store the FP constant in a constant pool. 9401 if (ConstantFPSDNode *TV = dyn_cast<ConstantFPSDNode>(N2)) 9402 if (ConstantFPSDNode *FV = dyn_cast<ConstantFPSDNode>(N3)) { 9403 if (TLI.isTypeLegal(N2.getValueType()) && 9404 (TLI.getOperationAction(ISD::ConstantFP, N2.getValueType()) != 9405 TargetLowering::Legal) && 9406 // If both constants have multiple uses, then we won't need to do an 9407 // extra load, they are likely around in registers for other users. 9408 (TV->hasOneUse() || FV->hasOneUse())) { 9409 Constant *Elts[] = { 9410 const_cast<ConstantFP*>(FV->getConstantFPValue()), 9411 const_cast<ConstantFP*>(TV->getConstantFPValue()) 9412 }; 9413 Type *FPTy = Elts[0]->getType(); 9414 const DataLayout &TD = *TLI.getDataLayout(); 9415 9416 // Create a ConstantArray of the two constants. 9417 Constant *CA = ConstantArray::get(ArrayType::get(FPTy, 2), Elts); 9418 SDValue CPIdx = DAG.getConstantPool(CA, TLI.getPointerTy(), 9419 TD.getPrefTypeAlignment(FPTy)); 9420 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 9421 9422 // Get the offsets to the 0 and 1 element of the array so that we can 9423 // select between them. 9424 SDValue Zero = DAG.getIntPtrConstant(0); 9425 unsigned EltSize = (unsigned)TD.getTypeAllocSize(Elts[0]->getType()); 9426 SDValue One = DAG.getIntPtrConstant(EltSize); 9427 9428 SDValue Cond = DAG.getSetCC(DL, 9429 TLI.getSetCCResultType(N0.getValueType()), 9430 N0, N1, CC); 9431 AddToWorkList(Cond.getNode()); 9432 SDValue CstOffset = DAG.getNode(ISD::SELECT, DL, Zero.getValueType(), 9433 Cond, One, Zero); 9434 AddToWorkList(CstOffset.getNode()); 9435 CPIdx = DAG.getNode(ISD::ADD, DL, TLI.getPointerTy(), CPIdx, 9436 CstOffset); 9437 AddToWorkList(CPIdx.getNode()); 9438 return DAG.getLoad(TV->getValueType(0), DL, DAG.getEntryNode(), CPIdx, 9439 MachinePointerInfo::getConstantPool(), false, 9440 false, false, Alignment); 9441 9442 } 9443 } 9444 9445 // Check to see if we can perform the "gzip trick", transforming 9446 // (select_cc setlt X, 0, A, 0) -> (and (sra X, (sub size(X), 1), A) 9447 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT && 9448 (N1C->isNullValue() || // (a < 0) ? b : 0 9449 (N1C->getAPIntValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0 9450 EVT XType = N0.getValueType(); 9451 EVT AType = N2.getValueType(); 9452 if (XType.bitsGE(AType)) { 9453 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a 9454 // single-bit constant. 9455 if (N2C && ((N2C->getAPIntValue() & (N2C->getAPIntValue()-1)) == 0)) { 9456 unsigned ShCtV = N2C->getAPIntValue().logBase2(); 9457 ShCtV = XType.getSizeInBits()-ShCtV-1; 9458 SDValue ShCt = DAG.getConstant(ShCtV, 9459 getShiftAmountTy(N0.getValueType())); 9460 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), 9461 XType, N0, ShCt); 9462 AddToWorkList(Shift.getNode()); 9463 9464 if (XType.bitsGT(AType)) { 9465 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift); 9466 AddToWorkList(Shift.getNode()); 9467 } 9468 9469 return DAG.getNode(ISD::AND, DL, AType, Shift, N2); 9470 } 9471 9472 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), 9473 XType, N0, 9474 DAG.getConstant(XType.getSizeInBits()-1, 9475 getShiftAmountTy(N0.getValueType()))); 9476 AddToWorkList(Shift.getNode()); 9477 9478 if (XType.bitsGT(AType)) { 9479 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift); 9480 AddToWorkList(Shift.getNode()); 9481 } 9482 9483 return DAG.getNode(ISD::AND, DL, AType, Shift, N2); 9484 } 9485 } 9486 9487 // fold (select_cc seteq (and x, y), 0, 0, A) -> (and (shr (shl x)) A) 9488 // where y is has a single bit set. 9489 // A plaintext description would be, we can turn the SELECT_CC into an AND 9490 // when the condition can be materialized as an all-ones register. Any 9491 // single bit-test can be materialized as an all-ones register with 9492 // shift-left and shift-right-arith. 9493 if (CC == ISD::SETEQ && N0->getOpcode() == ISD::AND && 9494 N0->getValueType(0) == VT && 9495 N1C && N1C->isNullValue() && 9496 N2C && N2C->isNullValue()) { 9497 SDValue AndLHS = N0->getOperand(0); 9498 ConstantSDNode *ConstAndRHS = dyn_cast<ConstantSDNode>(N0->getOperand(1)); 9499 if (ConstAndRHS && ConstAndRHS->getAPIntValue().countPopulation() == 1) { 9500 // Shift the tested bit over the sign bit. 9501 APInt AndMask = ConstAndRHS->getAPIntValue(); 9502 SDValue ShlAmt = 9503 DAG.getConstant(AndMask.countLeadingZeros(), 9504 getShiftAmountTy(AndLHS.getValueType())); 9505 SDValue Shl = DAG.getNode(ISD::SHL, N0.getDebugLoc(), VT, AndLHS, ShlAmt); 9506 9507 // Now arithmetic right shift it all the way over, so the result is either 9508 // all-ones, or zero. 9509 SDValue ShrAmt = 9510 DAG.getConstant(AndMask.getBitWidth()-1, 9511 getShiftAmountTy(Shl.getValueType())); 9512 SDValue Shr = DAG.getNode(ISD::SRA, N0.getDebugLoc(), VT, Shl, ShrAmt); 9513 9514 return DAG.getNode(ISD::AND, DL, VT, Shr, N3); 9515 } 9516 } 9517 9518 // fold select C, 16, 0 -> shl C, 4 9519 if (N2C && N3C && N3C->isNullValue() && N2C->getAPIntValue().isPowerOf2() && 9520 TLI.getBooleanContents(N0.getValueType().isVector()) == 9521 TargetLowering::ZeroOrOneBooleanContent) { 9522 9523 // If the caller doesn't want us to simplify this into a zext of a compare, 9524 // don't do it. 9525 if (NotExtCompare && N2C->getAPIntValue() == 1) 9526 return SDValue(); 9527 9528 // Get a SetCC of the condition 9529 // NOTE: Don't create a SETCC if it's not legal on this target. 9530 if (!LegalOperations || 9531 TLI.isOperationLegal(ISD::SETCC, 9532 LegalTypes ? TLI.getSetCCResultType(N0.getValueType()) : MVT::i1)) { 9533 SDValue Temp, SCC; 9534 // cast from setcc result type to select result type 9535 if (LegalTypes) { 9536 SCC = DAG.getSetCC(DL, TLI.getSetCCResultType(N0.getValueType()), 9537 N0, N1, CC); 9538 if (N2.getValueType().bitsLT(SCC.getValueType())) 9539 Temp = DAG.getZeroExtendInReg(SCC, N2.getDebugLoc(), 9540 N2.getValueType()); 9541 else 9542 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(), 9543 N2.getValueType(), SCC); 9544 } else { 9545 SCC = DAG.getSetCC(N0.getDebugLoc(), MVT::i1, N0, N1, CC); 9546 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(), 9547 N2.getValueType(), SCC); 9548 } 9549 9550 AddToWorkList(SCC.getNode()); 9551 AddToWorkList(Temp.getNode()); 9552 9553 if (N2C->getAPIntValue() == 1) 9554 return Temp; 9555 9556 // shl setcc result by log2 n2c 9557 return DAG.getNode(ISD::SHL, DL, N2.getValueType(), Temp, 9558 DAG.getConstant(N2C->getAPIntValue().logBase2(), 9559 getShiftAmountTy(Temp.getValueType()))); 9560 } 9561 } 9562 9563 // Check to see if this is the equivalent of setcc 9564 // FIXME: Turn all of these into setcc if setcc if setcc is legal 9565 // otherwise, go ahead with the folds. 9566 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getAPIntValue() == 1ULL)) { 9567 EVT XType = N0.getValueType(); 9568 if (!LegalOperations || 9569 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(XType))) { 9570 SDValue Res = DAG.getSetCC(DL, TLI.getSetCCResultType(XType), N0, N1, CC); 9571 if (Res.getValueType() != VT) 9572 Res = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, Res); 9573 return Res; 9574 } 9575 9576 // fold (seteq X, 0) -> (srl (ctlz X, log2(size(X)))) 9577 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ && 9578 (!LegalOperations || 9579 TLI.isOperationLegal(ISD::CTLZ, XType))) { 9580 SDValue Ctlz = DAG.getNode(ISD::CTLZ, N0.getDebugLoc(), XType, N0); 9581 return DAG.getNode(ISD::SRL, DL, XType, Ctlz, 9582 DAG.getConstant(Log2_32(XType.getSizeInBits()), 9583 getShiftAmountTy(Ctlz.getValueType()))); 9584 } 9585 // fold (setgt X, 0) -> (srl (and (-X, ~X), size(X)-1)) 9586 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) { 9587 SDValue NegN0 = DAG.getNode(ISD::SUB, N0.getDebugLoc(), 9588 XType, DAG.getConstant(0, XType), N0); 9589 SDValue NotN0 = DAG.getNOT(N0.getDebugLoc(), N0, XType); 9590 return DAG.getNode(ISD::SRL, DL, XType, 9591 DAG.getNode(ISD::AND, DL, XType, NegN0, NotN0), 9592 DAG.getConstant(XType.getSizeInBits()-1, 9593 getShiftAmountTy(XType))); 9594 } 9595 // fold (setgt X, -1) -> (xor (srl (X, size(X)-1), 1)) 9596 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) { 9597 SDValue Sign = DAG.getNode(ISD::SRL, N0.getDebugLoc(), XType, N0, 9598 DAG.getConstant(XType.getSizeInBits()-1, 9599 getShiftAmountTy(N0.getValueType()))); 9600 return DAG.getNode(ISD::XOR, DL, XType, Sign, DAG.getConstant(1, XType)); 9601 } 9602 } 9603 9604 // Check to see if this is an integer abs. 9605 // select_cc setg[te] X, 0, X, -X -> 9606 // select_cc setgt X, -1, X, -X -> 9607 // select_cc setl[te] X, 0, -X, X -> 9608 // select_cc setlt X, 1, -X, X -> 9609 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 9610 if (N1C) { 9611 ConstantSDNode *SubC = NULL; 9612 if (((N1C->isNullValue() && (CC == ISD::SETGT || CC == ISD::SETGE)) || 9613 (N1C->isAllOnesValue() && CC == ISD::SETGT)) && 9614 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1)) 9615 SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0)); 9616 else if (((N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE)) || 9617 (N1C->isOne() && CC == ISD::SETLT)) && 9618 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1)) 9619 SubC = dyn_cast<ConstantSDNode>(N2.getOperand(0)); 9620 9621 EVT XType = N0.getValueType(); 9622 if (SubC && SubC->isNullValue() && XType.isInteger()) { 9623 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), XType, 9624 N0, 9625 DAG.getConstant(XType.getSizeInBits()-1, 9626 getShiftAmountTy(N0.getValueType()))); 9627 SDValue Add = DAG.getNode(ISD::ADD, N0.getDebugLoc(), 9628 XType, N0, Shift); 9629 AddToWorkList(Shift.getNode()); 9630 AddToWorkList(Add.getNode()); 9631 return DAG.getNode(ISD::XOR, DL, XType, Add, Shift); 9632 } 9633 } 9634 9635 return SDValue(); 9636} 9637 9638/// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC. 9639SDValue DAGCombiner::SimplifySetCC(EVT VT, SDValue N0, 9640 SDValue N1, ISD::CondCode Cond, 9641 DebugLoc DL, bool foldBooleans) { 9642 TargetLowering::DAGCombinerInfo 9643 DagCombineInfo(DAG, !LegalTypes, !LegalOperations, false, this); 9644 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo, DL); 9645} 9646 9647/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 9648/// return a DAG expression to select that will generate the same value by 9649/// multiplying by a magic number. See: 9650/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 9651SDValue DAGCombiner::BuildSDIV(SDNode *N) { 9652 std::vector<SDNode*> Built; 9653 SDValue S = TLI.BuildSDIV(N, DAG, LegalOperations, &Built); 9654 9655 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 9656 ii != ee; ++ii) 9657 AddToWorkList(*ii); 9658 return S; 9659} 9660 9661/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 9662/// return a DAG expression to select that will generate the same value by 9663/// multiplying by a magic number. See: 9664/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 9665SDValue DAGCombiner::BuildUDIV(SDNode *N) { 9666 std::vector<SDNode*> Built; 9667 SDValue S = TLI.BuildUDIV(N, DAG, LegalOperations, &Built); 9668 9669 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 9670 ii != ee; ++ii) 9671 AddToWorkList(*ii); 9672 return S; 9673} 9674 9675/// FindBaseOffset - Return true if base is a frame index, which is known not 9676// to alias with anything but itself. Provides base object and offset as 9677// results. 9678static bool FindBaseOffset(SDValue Ptr, SDValue &Base, int64_t &Offset, 9679 const GlobalValue *&GV, const void *&CV) { 9680 // Assume it is a primitive operation. 9681 Base = Ptr; Offset = 0; GV = 0; CV = 0; 9682 9683 // If it's an adding a simple constant then integrate the offset. 9684 if (Base.getOpcode() == ISD::ADD) { 9685 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) { 9686 Base = Base.getOperand(0); 9687 Offset += C->getZExtValue(); 9688 } 9689 } 9690 9691 // Return the underlying GlobalValue, and update the Offset. Return false 9692 // for GlobalAddressSDNode since the same GlobalAddress may be represented 9693 // by multiple nodes with different offsets. 9694 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Base)) { 9695 GV = G->getGlobal(); 9696 Offset += G->getOffset(); 9697 return false; 9698 } 9699 9700 // Return the underlying Constant value, and update the Offset. Return false 9701 // for ConstantSDNodes since the same constant pool entry may be represented 9702 // by multiple nodes with different offsets. 9703 if (ConstantPoolSDNode *C = dyn_cast<ConstantPoolSDNode>(Base)) { 9704 CV = C->isMachineConstantPoolEntry() ? (const void *)C->getMachineCPVal() 9705 : (const void *)C->getConstVal(); 9706 Offset += C->getOffset(); 9707 return false; 9708 } 9709 // If it's any of the following then it can't alias with anything but itself. 9710 return isa<FrameIndexSDNode>(Base); 9711} 9712 9713/// isAlias - Return true if there is any possibility that the two addresses 9714/// overlap. 9715bool DAGCombiner::isAlias(SDValue Ptr1, int64_t Size1, 9716 const Value *SrcValue1, int SrcValueOffset1, 9717 unsigned SrcValueAlign1, 9718 const MDNode *TBAAInfo1, 9719 SDValue Ptr2, int64_t Size2, 9720 const Value *SrcValue2, int SrcValueOffset2, 9721 unsigned SrcValueAlign2, 9722 const MDNode *TBAAInfo2) const { 9723 // If they are the same then they must be aliases. 9724 if (Ptr1 == Ptr2) return true; 9725 9726 // Gather base node and offset information. 9727 SDValue Base1, Base2; 9728 int64_t Offset1, Offset2; 9729 const GlobalValue *GV1, *GV2; 9730 const void *CV1, *CV2; 9731 bool isFrameIndex1 = FindBaseOffset(Ptr1, Base1, Offset1, GV1, CV1); 9732 bool isFrameIndex2 = FindBaseOffset(Ptr2, Base2, Offset2, GV2, CV2); 9733 9734 // If they have a same base address then check to see if they overlap. 9735 if (Base1 == Base2 || (GV1 && (GV1 == GV2)) || (CV1 && (CV1 == CV2))) 9736 return !((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1); 9737 9738 // It is possible for different frame indices to alias each other, mostly 9739 // when tail call optimization reuses return address slots for arguments. 9740 // To catch this case, look up the actual index of frame indices to compute 9741 // the real alias relationship. 9742 if (isFrameIndex1 && isFrameIndex2) { 9743 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 9744 Offset1 += MFI->getObjectOffset(cast<FrameIndexSDNode>(Base1)->getIndex()); 9745 Offset2 += MFI->getObjectOffset(cast<FrameIndexSDNode>(Base2)->getIndex()); 9746 return !((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1); 9747 } 9748 9749 // Otherwise, if we know what the bases are, and they aren't identical, then 9750 // we know they cannot alias. 9751 if ((isFrameIndex1 || CV1 || GV1) && (isFrameIndex2 || CV2 || GV2)) 9752 return false; 9753 9754 // If we know required SrcValue1 and SrcValue2 have relatively large alignment 9755 // compared to the size and offset of the access, we may be able to prove they 9756 // do not alias. This check is conservative for now to catch cases created by 9757 // splitting vector types. 9758 if ((SrcValueAlign1 == SrcValueAlign2) && 9759 (SrcValueOffset1 != SrcValueOffset2) && 9760 (Size1 == Size2) && (SrcValueAlign1 > Size1)) { 9761 int64_t OffAlign1 = SrcValueOffset1 % SrcValueAlign1; 9762 int64_t OffAlign2 = SrcValueOffset2 % SrcValueAlign1; 9763 9764 // There is no overlap between these relatively aligned accesses of similar 9765 // size, return no alias. 9766 if ((OffAlign1 + Size1) <= OffAlign2 || (OffAlign2 + Size2) <= OffAlign1) 9767 return false; 9768 } 9769 9770 if (CombinerGlobalAA) { 9771 // Use alias analysis information. 9772 int64_t MinOffset = std::min(SrcValueOffset1, SrcValueOffset2); 9773 int64_t Overlap1 = Size1 + SrcValueOffset1 - MinOffset; 9774 int64_t Overlap2 = Size2 + SrcValueOffset2 - MinOffset; 9775 AliasAnalysis::AliasResult AAResult = 9776 AA.alias(AliasAnalysis::Location(SrcValue1, Overlap1, TBAAInfo1), 9777 AliasAnalysis::Location(SrcValue2, Overlap2, TBAAInfo2)); 9778 if (AAResult == AliasAnalysis::NoAlias) 9779 return false; 9780 } 9781 9782 // Otherwise we have to assume they alias. 9783 return true; 9784} 9785 9786bool DAGCombiner::isAlias(LSBaseSDNode *Op0, LSBaseSDNode *Op1) { 9787 SDValue Ptr0, Ptr1; 9788 int64_t Size0, Size1; 9789 const Value *SrcValue0, *SrcValue1; 9790 int SrcValueOffset0, SrcValueOffset1; 9791 unsigned SrcValueAlign0, SrcValueAlign1; 9792 const MDNode *SrcTBAAInfo0, *SrcTBAAInfo1; 9793 FindAliasInfo(Op0, Ptr0, Size0, SrcValue0, SrcValueOffset0, 9794 SrcValueAlign0, SrcTBAAInfo0); 9795 FindAliasInfo(Op1, Ptr1, Size1, SrcValue1, SrcValueOffset1, 9796 SrcValueAlign1, SrcTBAAInfo1); 9797 return isAlias(Ptr0, Size0, SrcValue0, SrcValueOffset0, 9798 SrcValueAlign0, SrcTBAAInfo0, 9799 Ptr1, Size1, SrcValue1, SrcValueOffset1, 9800 SrcValueAlign1, SrcTBAAInfo1); 9801} 9802 9803/// FindAliasInfo - Extracts the relevant alias information from the memory 9804/// node. Returns true if the operand was a load. 9805bool DAGCombiner::FindAliasInfo(SDNode *N, 9806 SDValue &Ptr, int64_t &Size, 9807 const Value *&SrcValue, 9808 int &SrcValueOffset, 9809 unsigned &SrcValueAlign, 9810 const MDNode *&TBAAInfo) const { 9811 LSBaseSDNode *LS = cast<LSBaseSDNode>(N); 9812 9813 Ptr = LS->getBasePtr(); 9814 Size = LS->getMemoryVT().getSizeInBits() >> 3; 9815 SrcValue = LS->getSrcValue(); 9816 SrcValueOffset = LS->getSrcValueOffset(); 9817 SrcValueAlign = LS->getOriginalAlignment(); 9818 TBAAInfo = LS->getTBAAInfo(); 9819 return isa<LoadSDNode>(LS); 9820} 9821 9822/// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 9823/// looking for aliasing nodes and adding them to the Aliases vector. 9824void DAGCombiner::GatherAllAliases(SDNode *N, SDValue OriginalChain, 9825 SmallVector<SDValue, 8> &Aliases) { 9826 SmallVector<SDValue, 8> Chains; // List of chains to visit. 9827 SmallPtrSet<SDNode *, 16> Visited; // Visited node set. 9828 9829 // Get alias information for node. 9830 SDValue Ptr; 9831 int64_t Size; 9832 const Value *SrcValue; 9833 int SrcValueOffset; 9834 unsigned SrcValueAlign; 9835 const MDNode *SrcTBAAInfo; 9836 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset, 9837 SrcValueAlign, SrcTBAAInfo); 9838 9839 // Starting off. 9840 Chains.push_back(OriginalChain); 9841 unsigned Depth = 0; 9842 9843 // Look at each chain and determine if it is an alias. If so, add it to the 9844 // aliases list. If not, then continue up the chain looking for the next 9845 // candidate. 9846 while (!Chains.empty()) { 9847 SDValue Chain = Chains.back(); 9848 Chains.pop_back(); 9849 9850 // For TokenFactor nodes, look at each operand and only continue up the 9851 // chain until we find two aliases. If we've seen two aliases, assume we'll 9852 // find more and revert to original chain since the xform is unlikely to be 9853 // profitable. 9854 // 9855 // FIXME: The depth check could be made to return the last non-aliasing 9856 // chain we found before we hit a tokenfactor rather than the original 9857 // chain. 9858 if (Depth > 6 || Aliases.size() == 2) { 9859 Aliases.clear(); 9860 Aliases.push_back(OriginalChain); 9861 break; 9862 } 9863 9864 // Don't bother if we've been before. 9865 if (!Visited.insert(Chain.getNode())) 9866 continue; 9867 9868 switch (Chain.getOpcode()) { 9869 case ISD::EntryToken: 9870 // Entry token is ideal chain operand, but handled in FindBetterChain. 9871 break; 9872 9873 case ISD::LOAD: 9874 case ISD::STORE: { 9875 // Get alias information for Chain. 9876 SDValue OpPtr; 9877 int64_t OpSize; 9878 const Value *OpSrcValue; 9879 int OpSrcValueOffset; 9880 unsigned OpSrcValueAlign; 9881 const MDNode *OpSrcTBAAInfo; 9882 bool IsOpLoad = FindAliasInfo(Chain.getNode(), OpPtr, OpSize, 9883 OpSrcValue, OpSrcValueOffset, 9884 OpSrcValueAlign, 9885 OpSrcTBAAInfo); 9886 9887 // If chain is alias then stop here. 9888 if (!(IsLoad && IsOpLoad) && 9889 isAlias(Ptr, Size, SrcValue, SrcValueOffset, SrcValueAlign, 9890 SrcTBAAInfo, 9891 OpPtr, OpSize, OpSrcValue, OpSrcValueOffset, 9892 OpSrcValueAlign, OpSrcTBAAInfo)) { 9893 Aliases.push_back(Chain); 9894 } else { 9895 // Look further up the chain. 9896 Chains.push_back(Chain.getOperand(0)); 9897 ++Depth; 9898 } 9899 break; 9900 } 9901 9902 case ISD::TokenFactor: 9903 // We have to check each of the operands of the token factor for "small" 9904 // token factors, so we queue them up. Adding the operands to the queue 9905 // (stack) in reverse order maintains the original order and increases the 9906 // likelihood that getNode will find a matching token factor (CSE.) 9907 if (Chain.getNumOperands() > 16) { 9908 Aliases.push_back(Chain); 9909 break; 9910 } 9911 for (unsigned n = Chain.getNumOperands(); n;) 9912 Chains.push_back(Chain.getOperand(--n)); 9913 ++Depth; 9914 break; 9915 9916 default: 9917 // For all other instructions we will just have to take what we can get. 9918 Aliases.push_back(Chain); 9919 break; 9920 } 9921 } 9922} 9923 9924/// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking 9925/// for a better chain (aliasing node.) 9926SDValue DAGCombiner::FindBetterChain(SDNode *N, SDValue OldChain) { 9927 SmallVector<SDValue, 8> Aliases; // Ops for replacing token factor. 9928 9929 // Accumulate all the aliases to this node. 9930 GatherAllAliases(N, OldChain, Aliases); 9931 9932 // If no operands then chain to entry token. 9933 if (Aliases.size() == 0) 9934 return DAG.getEntryNode(); 9935 9936 // If a single operand then chain to it. We don't need to revisit it. 9937 if (Aliases.size() == 1) 9938 return Aliases[0]; 9939 9940 // Construct a custom tailored token factor. 9941 return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, 9942 &Aliases[0], Aliases.size()); 9943} 9944 9945// SelectionDAG::Combine - This is the entry point for the file. 9946// 9947void SelectionDAG::Combine(CombineLevel Level, AliasAnalysis &AA, 9948 CodeGenOpt::Level OptLevel) { 9949 /// run - This is the main entry point to this class. 9950 /// 9951 DAGCombiner(*this, AA, OptLevel).Run(Level); 9952} 9953