DAGCombiner.cpp revision b05e4778f0871cbb02f61e4d55ad7375738a1d01
1//===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run 11// both before and after the DAG is legalized. 12// 13// This pass is not a substitute for the LLVM IR instcombine pass. This pass is 14// primarily intended to handle simplification opportunities that are implicit 15// in the LLVM IR and exposed by the various codegen lowering phases. 16// 17//===----------------------------------------------------------------------===// 18 19#define DEBUG_TYPE "dagcombine" 20#include "llvm/CodeGen/SelectionDAG.h" 21#include "llvm/ADT/SmallPtrSet.h" 22#include "llvm/ADT/Statistic.h" 23#include "llvm/Analysis/AliasAnalysis.h" 24#include "llvm/CodeGen/MachineFrameInfo.h" 25#include "llvm/CodeGen/MachineFunction.h" 26#include "llvm/IR/DataLayout.h" 27#include "llvm/IR/DerivedTypes.h" 28#include "llvm/IR/Function.h" 29#include "llvm/IR/LLVMContext.h" 30#include "llvm/Support/CommandLine.h" 31#include "llvm/Support/Debug.h" 32#include "llvm/Support/ErrorHandling.h" 33#include "llvm/Support/MathExtras.h" 34#include "llvm/Support/raw_ostream.h" 35#include "llvm/Target/TargetLowering.h" 36#include "llvm/Target/TargetMachine.h" 37#include "llvm/Target/TargetOptions.h" 38#include <algorithm> 39using namespace llvm; 40 41STATISTIC(NodesCombined , "Number of dag nodes combined"); 42STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created"); 43STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created"); 44STATISTIC(OpsNarrowed , "Number of load/op/store narrowed"); 45STATISTIC(LdStFP2Int , "Number of fp load/store pairs transformed to int"); 46 47namespace { 48 static cl::opt<bool> 49 CombinerAA("combiner-alias-analysis", cl::Hidden, 50 cl::desc("Turn on alias analysis during testing")); 51 52 static cl::opt<bool> 53 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden, 54 cl::desc("Include global information in alias analysis")); 55 56//------------------------------ DAGCombiner ---------------------------------// 57 58 class DAGCombiner { 59 SelectionDAG &DAG; 60 const TargetLowering &TLI; 61 CombineLevel Level; 62 CodeGenOpt::Level OptLevel; 63 bool LegalOperations; 64 bool LegalTypes; 65 66 // Worklist of all of the nodes that need to be simplified. 67 // 68 // This has the semantics that when adding to the worklist, 69 // the item added must be next to be processed. It should 70 // also only appear once. The naive approach to this takes 71 // linear time. 72 // 73 // To reduce the insert/remove time to logarithmic, we use 74 // a set and a vector to maintain our worklist. 75 // 76 // The set contains the items on the worklist, but does not 77 // maintain the order they should be visited. 78 // 79 // The vector maintains the order nodes should be visited, but may 80 // contain duplicate or removed nodes. When choosing a node to 81 // visit, we pop off the order stack until we find an item that is 82 // also in the contents set. All operations are O(log N). 83 SmallPtrSet<SDNode*, 64> WorkListContents; 84 SmallVector<SDNode*, 64> WorkListOrder; 85 86 // AA - Used for DAG load/store alias analysis. 87 AliasAnalysis &AA; 88 89 /// AddUsersToWorkList - When an instruction is simplified, add all users of 90 /// the instruction to the work lists because they might get more simplified 91 /// now. 92 /// 93 void AddUsersToWorkList(SDNode *N) { 94 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 95 UI != UE; ++UI) 96 AddToWorkList(*UI); 97 } 98 99 /// visit - call the node-specific routine that knows how to fold each 100 /// particular type of node. 101 SDValue visit(SDNode *N); 102 103 public: 104 /// AddToWorkList - Add to the work list making sure its instance is at the 105 /// back (next to be processed.) 106 void AddToWorkList(SDNode *N) { 107 WorkListContents.insert(N); 108 WorkListOrder.push_back(N); 109 } 110 111 /// removeFromWorkList - remove all instances of N from the worklist. 112 /// 113 void removeFromWorkList(SDNode *N) { 114 WorkListContents.erase(N); 115 } 116 117 SDValue CombineTo(SDNode *N, const SDValue *To, unsigned NumTo, 118 bool AddTo = true); 119 120 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true) { 121 return CombineTo(N, &Res, 1, AddTo); 122 } 123 124 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, 125 bool AddTo = true) { 126 SDValue To[] = { Res0, Res1 }; 127 return CombineTo(N, To, 2, AddTo); 128 } 129 130 void CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO); 131 132 private: 133 134 /// SimplifyDemandedBits - Check the specified integer node value to see if 135 /// it can be simplified or if things it uses can be simplified by bit 136 /// propagation. If so, return true. 137 bool SimplifyDemandedBits(SDValue Op) { 138 unsigned BitWidth = Op.getValueType().getScalarType().getSizeInBits(); 139 APInt Demanded = APInt::getAllOnesValue(BitWidth); 140 return SimplifyDemandedBits(Op, Demanded); 141 } 142 143 bool SimplifyDemandedBits(SDValue Op, const APInt &Demanded); 144 145 bool CombineToPreIndexedLoadStore(SDNode *N); 146 bool CombineToPostIndexedLoadStore(SDNode *N); 147 148 void ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad); 149 SDValue PromoteOperand(SDValue Op, EVT PVT, bool &Replace); 150 SDValue SExtPromoteOperand(SDValue Op, EVT PVT); 151 SDValue ZExtPromoteOperand(SDValue Op, EVT PVT); 152 SDValue PromoteIntBinOp(SDValue Op); 153 SDValue PromoteIntShiftOp(SDValue Op); 154 SDValue PromoteExtend(SDValue Op); 155 bool PromoteLoad(SDValue Op); 156 157 void ExtendSetCCUses(SmallVector<SDNode*, 4> SetCCs, 158 SDValue Trunc, SDValue ExtLoad, SDLoc DL, 159 ISD::NodeType ExtType); 160 161 /// combine - call the node-specific routine that knows how to fold each 162 /// particular type of node. If that doesn't do anything, try the 163 /// target-specific DAG combines. 164 SDValue combine(SDNode *N); 165 166 // Visitation implementation - Implement dag node combining for different 167 // node types. The semantics are as follows: 168 // Return Value: 169 // SDValue.getNode() == 0 - No change was made 170 // SDValue.getNode() == N - N was replaced, is dead and has been handled. 171 // otherwise - N should be replaced by the returned Operand. 172 // 173 SDValue visitTokenFactor(SDNode *N); 174 SDValue visitMERGE_VALUES(SDNode *N); 175 SDValue visitADD(SDNode *N); 176 SDValue visitSUB(SDNode *N); 177 SDValue visitADDC(SDNode *N); 178 SDValue visitSUBC(SDNode *N); 179 SDValue visitADDE(SDNode *N); 180 SDValue visitSUBE(SDNode *N); 181 SDValue visitMUL(SDNode *N); 182 SDValue visitSDIV(SDNode *N); 183 SDValue visitUDIV(SDNode *N); 184 SDValue visitSREM(SDNode *N); 185 SDValue visitUREM(SDNode *N); 186 SDValue visitMULHU(SDNode *N); 187 SDValue visitMULHS(SDNode *N); 188 SDValue visitSMUL_LOHI(SDNode *N); 189 SDValue visitUMUL_LOHI(SDNode *N); 190 SDValue visitSMULO(SDNode *N); 191 SDValue visitUMULO(SDNode *N); 192 SDValue visitSDIVREM(SDNode *N); 193 SDValue visitUDIVREM(SDNode *N); 194 SDValue visitAND(SDNode *N); 195 SDValue visitOR(SDNode *N); 196 SDValue visitXOR(SDNode *N); 197 SDValue SimplifyVBinOp(SDNode *N); 198 SDValue SimplifyVUnaryOp(SDNode *N); 199 SDValue visitSHL(SDNode *N); 200 SDValue visitSRA(SDNode *N); 201 SDValue visitSRL(SDNode *N); 202 SDValue visitCTLZ(SDNode *N); 203 SDValue visitCTLZ_ZERO_UNDEF(SDNode *N); 204 SDValue visitCTTZ(SDNode *N); 205 SDValue visitCTTZ_ZERO_UNDEF(SDNode *N); 206 SDValue visitCTPOP(SDNode *N); 207 SDValue visitSELECT(SDNode *N); 208 SDValue visitVSELECT(SDNode *N); 209 SDValue visitSELECT_CC(SDNode *N); 210 SDValue visitSETCC(SDNode *N); 211 SDValue visitSIGN_EXTEND(SDNode *N); 212 SDValue visitZERO_EXTEND(SDNode *N); 213 SDValue visitANY_EXTEND(SDNode *N); 214 SDValue visitSIGN_EXTEND_INREG(SDNode *N); 215 SDValue visitTRUNCATE(SDNode *N); 216 SDValue visitBITCAST(SDNode *N); 217 SDValue visitBUILD_PAIR(SDNode *N); 218 SDValue visitFADD(SDNode *N); 219 SDValue visitFSUB(SDNode *N); 220 SDValue visitFMUL(SDNode *N); 221 SDValue visitFMA(SDNode *N); 222 SDValue visitFDIV(SDNode *N); 223 SDValue visitFREM(SDNode *N); 224 SDValue visitFCOPYSIGN(SDNode *N); 225 SDValue visitSINT_TO_FP(SDNode *N); 226 SDValue visitUINT_TO_FP(SDNode *N); 227 SDValue visitFP_TO_SINT(SDNode *N); 228 SDValue visitFP_TO_UINT(SDNode *N); 229 SDValue visitFP_ROUND(SDNode *N); 230 SDValue visitFP_ROUND_INREG(SDNode *N); 231 SDValue visitFP_EXTEND(SDNode *N); 232 SDValue visitFNEG(SDNode *N); 233 SDValue visitFABS(SDNode *N); 234 SDValue visitFCEIL(SDNode *N); 235 SDValue visitFTRUNC(SDNode *N); 236 SDValue visitFFLOOR(SDNode *N); 237 SDValue visitBRCOND(SDNode *N); 238 SDValue visitBR_CC(SDNode *N); 239 SDValue visitLOAD(SDNode *N); 240 SDValue visitSTORE(SDNode *N); 241 SDValue visitINSERT_VECTOR_ELT(SDNode *N); 242 SDValue visitEXTRACT_VECTOR_ELT(SDNode *N); 243 SDValue visitBUILD_VECTOR(SDNode *N); 244 SDValue visitCONCAT_VECTORS(SDNode *N); 245 SDValue visitEXTRACT_SUBVECTOR(SDNode *N); 246 SDValue visitVECTOR_SHUFFLE(SDNode *N); 247 248 SDValue XformToShuffleWithZero(SDNode *N); 249 SDValue ReassociateOps(unsigned Opc, SDLoc DL, SDValue LHS, SDValue RHS); 250 251 SDValue visitShiftByConstant(SDNode *N, unsigned Amt); 252 253 bool SimplifySelectOps(SDNode *SELECT, SDValue LHS, SDValue RHS); 254 SDValue SimplifyBinOpWithSameOpcodeHands(SDNode *N); 255 SDValue SimplifySelect(SDLoc DL, SDValue N0, SDValue N1, SDValue N2); 256 SDValue SimplifySelectCC(SDLoc DL, SDValue N0, SDValue N1, SDValue N2, 257 SDValue N3, ISD::CondCode CC, 258 bool NotExtCompare = false); 259 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond, 260 SDLoc DL, bool foldBooleans = true); 261 SDValue SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 262 unsigned HiOp); 263 SDValue CombineConsecutiveLoads(SDNode *N, EVT VT); 264 SDValue ConstantFoldBITCASTofBUILD_VECTOR(SDNode *, EVT); 265 SDValue BuildSDIV(SDNode *N); 266 SDValue BuildUDIV(SDNode *N); 267 SDValue MatchBSwapHWordLow(SDNode *N, SDValue N0, SDValue N1, 268 bool DemandHighBits = true); 269 SDValue MatchBSwapHWord(SDNode *N, SDValue N0, SDValue N1); 270 SDNode *MatchRotate(SDValue LHS, SDValue RHS, SDLoc DL); 271 SDValue ReduceLoadWidth(SDNode *N); 272 SDValue ReduceLoadOpStoreWidth(SDNode *N); 273 SDValue TransformFPLoadStorePair(SDNode *N); 274 SDValue reduceBuildVecExtToExtBuildVec(SDNode *N); 275 SDValue reduceBuildVecConvertToConvertBuildVec(SDNode *N); 276 277 SDValue GetDemandedBits(SDValue V, const APInt &Mask); 278 279 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 280 /// looking for aliasing nodes and adding them to the Aliases vector. 281 void GatherAllAliases(SDNode *N, SDValue OriginalChain, 282 SmallVector<SDValue, 8> &Aliases); 283 284 /// isAlias - Return true if there is any possibility that the two addresses 285 /// overlap. 286 bool isAlias(SDValue Ptr1, int64_t Size1, 287 const Value *SrcValue1, int SrcValueOffset1, 288 unsigned SrcValueAlign1, 289 const MDNode *TBAAInfo1, 290 SDValue Ptr2, int64_t Size2, 291 const Value *SrcValue2, int SrcValueOffset2, 292 unsigned SrcValueAlign2, 293 const MDNode *TBAAInfo2) const; 294 295 /// isAlias - Return true if there is any possibility that the two addresses 296 /// overlap. 297 bool isAlias(LSBaseSDNode *Op0, LSBaseSDNode *Op1); 298 299 /// FindAliasInfo - Extracts the relevant alias information from the memory 300 /// node. Returns true if the operand was a load. 301 bool FindAliasInfo(SDNode *N, 302 SDValue &Ptr, int64_t &Size, 303 const Value *&SrcValue, int &SrcValueOffset, 304 unsigned &SrcValueAlignment, 305 const MDNode *&TBAAInfo) const; 306 307 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, 308 /// looking for a better chain (aliasing node.) 309 SDValue FindBetterChain(SDNode *N, SDValue Chain); 310 311 /// Merge consecutive store operations into a wide store. 312 /// This optimization uses wide integers or vectors when possible. 313 /// \return True if some memory operations were changed. 314 bool MergeConsecutiveStores(StoreSDNode *N); 315 316 public: 317 DAGCombiner(SelectionDAG &D, AliasAnalysis &A, CodeGenOpt::Level OL) 318 : DAG(D), TLI(D.getTargetLoweringInfo()), Level(BeforeLegalizeTypes), 319 OptLevel(OL), LegalOperations(false), LegalTypes(false), AA(A) {} 320 321 /// Run - runs the dag combiner on all nodes in the work list 322 void Run(CombineLevel AtLevel); 323 324 SelectionDAG &getDAG() const { return DAG; } 325 326 /// getShiftAmountTy - Returns a type large enough to hold any valid 327 /// shift amount - before type legalization these can be huge. 328 EVT getShiftAmountTy(EVT LHSTy) { 329 return LegalTypes ? TLI.getShiftAmountTy(LHSTy) : TLI.getPointerTy(); 330 } 331 332 /// isTypeLegal - This method returns true if we are running before type 333 /// legalization or if the specified VT is legal. 334 bool isTypeLegal(const EVT &VT) { 335 if (!LegalTypes) return true; 336 return TLI.isTypeLegal(VT); 337 } 338 339 /// getSetCCResultType - Convenience wrapper around 340 /// TargetLowering::getSetCCResultType 341 EVT getSetCCResultType(EVT VT) const { 342 return TLI.getSetCCResultType(*DAG.getContext(), VT); 343 } 344 }; 345} 346 347 348namespace { 349/// WorkListRemover - This class is a DAGUpdateListener that removes any deleted 350/// nodes from the worklist. 351class WorkListRemover : public SelectionDAG::DAGUpdateListener { 352 DAGCombiner &DC; 353public: 354 explicit WorkListRemover(DAGCombiner &dc) 355 : SelectionDAG::DAGUpdateListener(dc.getDAG()), DC(dc) {} 356 357 virtual void NodeDeleted(SDNode *N, SDNode *E) { 358 DC.removeFromWorkList(N); 359 } 360}; 361} 362 363//===----------------------------------------------------------------------===// 364// TargetLowering::DAGCombinerInfo implementation 365//===----------------------------------------------------------------------===// 366 367void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) { 368 ((DAGCombiner*)DC)->AddToWorkList(N); 369} 370 371void TargetLowering::DAGCombinerInfo::RemoveFromWorklist(SDNode *N) { 372 ((DAGCombiner*)DC)->removeFromWorkList(N); 373} 374 375SDValue TargetLowering::DAGCombinerInfo:: 376CombineTo(SDNode *N, const std::vector<SDValue> &To, bool AddTo) { 377 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size(), AddTo); 378} 379 380SDValue TargetLowering::DAGCombinerInfo:: 381CombineTo(SDNode *N, SDValue Res, bool AddTo) { 382 return ((DAGCombiner*)DC)->CombineTo(N, Res, AddTo); 383} 384 385 386SDValue TargetLowering::DAGCombinerInfo:: 387CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo) { 388 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1, AddTo); 389} 390 391void TargetLowering::DAGCombinerInfo:: 392CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) { 393 return ((DAGCombiner*)DC)->CommitTargetLoweringOpt(TLO); 394} 395 396//===----------------------------------------------------------------------===// 397// Helper Functions 398//===----------------------------------------------------------------------===// 399 400/// isNegatibleForFree - Return 1 if we can compute the negated form of the 401/// specified expression for the same cost as the expression itself, or 2 if we 402/// can compute the negated form more cheaply than the expression itself. 403static char isNegatibleForFree(SDValue Op, bool LegalOperations, 404 const TargetLowering &TLI, 405 const TargetOptions *Options, 406 unsigned Depth = 0) { 407 // fneg is removable even if it has multiple uses. 408 if (Op.getOpcode() == ISD::FNEG) return 2; 409 410 // Don't allow anything with multiple uses. 411 if (!Op.hasOneUse()) return 0; 412 413 // Don't recurse exponentially. 414 if (Depth > 6) return 0; 415 416 switch (Op.getOpcode()) { 417 default: return false; 418 case ISD::ConstantFP: 419 // Don't invert constant FP values after legalize. The negated constant 420 // isn't necessarily legal. 421 return LegalOperations ? 0 : 1; 422 case ISD::FADD: 423 // FIXME: determine better conditions for this xform. 424 if (!Options->UnsafeFPMath) return 0; 425 426 // After operation legalization, it might not be legal to create new FSUBs. 427 if (LegalOperations && 428 !TLI.isOperationLegalOrCustom(ISD::FSUB, Op.getValueType())) 429 return 0; 430 431 // fold (fneg (fadd A, B)) -> (fsub (fneg A), B) 432 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI, 433 Options, Depth + 1)) 434 return V; 435 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A) 436 return isNegatibleForFree(Op.getOperand(1), LegalOperations, TLI, Options, 437 Depth + 1); 438 case ISD::FSUB: 439 // We can't turn -(A-B) into B-A when we honor signed zeros. 440 if (!Options->UnsafeFPMath) return 0; 441 442 // fold (fneg (fsub A, B)) -> (fsub B, A) 443 return 1; 444 445 case ISD::FMUL: 446 case ISD::FDIV: 447 if (Options->HonorSignDependentRoundingFPMath()) return 0; 448 449 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) or (fmul X, (fneg Y)) 450 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI, 451 Options, Depth + 1)) 452 return V; 453 454 return isNegatibleForFree(Op.getOperand(1), LegalOperations, TLI, Options, 455 Depth + 1); 456 457 case ISD::FP_EXTEND: 458 case ISD::FP_ROUND: 459 case ISD::FSIN: 460 return isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI, Options, 461 Depth + 1); 462 } 463} 464 465/// GetNegatedExpression - If isNegatibleForFree returns true, this function 466/// returns the newly negated expression. 467static SDValue GetNegatedExpression(SDValue Op, SelectionDAG &DAG, 468 bool LegalOperations, unsigned Depth = 0) { 469 // fneg is removable even if it has multiple uses. 470 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0); 471 472 // Don't allow anything with multiple uses. 473 assert(Op.hasOneUse() && "Unknown reuse!"); 474 475 assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree"); 476 switch (Op.getOpcode()) { 477 default: llvm_unreachable("Unknown code"); 478 case ISD::ConstantFP: { 479 APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF(); 480 V.changeSign(); 481 return DAG.getConstantFP(V, Op.getValueType()); 482 } 483 case ISD::FADD: 484 // FIXME: determine better conditions for this xform. 485 assert(DAG.getTarget().Options.UnsafeFPMath); 486 487 // fold (fneg (fadd A, B)) -> (fsub (fneg A), B) 488 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, 489 DAG.getTargetLoweringInfo(), 490 &DAG.getTarget().Options, Depth+1)) 491 return DAG.getNode(ISD::FSUB, SDLoc(Op), Op.getValueType(), 492 GetNegatedExpression(Op.getOperand(0), DAG, 493 LegalOperations, Depth+1), 494 Op.getOperand(1)); 495 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A) 496 return DAG.getNode(ISD::FSUB, SDLoc(Op), Op.getValueType(), 497 GetNegatedExpression(Op.getOperand(1), DAG, 498 LegalOperations, Depth+1), 499 Op.getOperand(0)); 500 case ISD::FSUB: 501 // We can't turn -(A-B) into B-A when we honor signed zeros. 502 assert(DAG.getTarget().Options.UnsafeFPMath); 503 504 // fold (fneg (fsub 0, B)) -> B 505 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(Op.getOperand(0))) 506 if (N0CFP->getValueAPF().isZero()) 507 return Op.getOperand(1); 508 509 // fold (fneg (fsub A, B)) -> (fsub B, A) 510 return DAG.getNode(ISD::FSUB, SDLoc(Op), Op.getValueType(), 511 Op.getOperand(1), Op.getOperand(0)); 512 513 case ISD::FMUL: 514 case ISD::FDIV: 515 assert(!DAG.getTarget().Options.HonorSignDependentRoundingFPMath()); 516 517 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) 518 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, 519 DAG.getTargetLoweringInfo(), 520 &DAG.getTarget().Options, Depth+1)) 521 return DAG.getNode(Op.getOpcode(), SDLoc(Op), Op.getValueType(), 522 GetNegatedExpression(Op.getOperand(0), DAG, 523 LegalOperations, Depth+1), 524 Op.getOperand(1)); 525 526 // fold (fneg (fmul X, Y)) -> (fmul X, (fneg Y)) 527 return DAG.getNode(Op.getOpcode(), SDLoc(Op), Op.getValueType(), 528 Op.getOperand(0), 529 GetNegatedExpression(Op.getOperand(1), DAG, 530 LegalOperations, Depth+1)); 531 532 case ISD::FP_EXTEND: 533 case ISD::FSIN: 534 return DAG.getNode(Op.getOpcode(), SDLoc(Op), Op.getValueType(), 535 GetNegatedExpression(Op.getOperand(0), DAG, 536 LegalOperations, Depth+1)); 537 case ISD::FP_ROUND: 538 return DAG.getNode(ISD::FP_ROUND, SDLoc(Op), Op.getValueType(), 539 GetNegatedExpression(Op.getOperand(0), DAG, 540 LegalOperations, Depth+1), 541 Op.getOperand(1)); 542 } 543} 544 545 546// isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc 547// that selects between the values 1 and 0, making it equivalent to a setcc. 548// Also, set the incoming LHS, RHS, and CC references to the appropriate 549// nodes based on the type of node we are checking. This simplifies life a 550// bit for the callers. 551static bool isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS, 552 SDValue &CC) { 553 if (N.getOpcode() == ISD::SETCC) { 554 LHS = N.getOperand(0); 555 RHS = N.getOperand(1); 556 CC = N.getOperand(2); 557 return true; 558 } 559 if (N.getOpcode() == ISD::SELECT_CC && 560 N.getOperand(2).getOpcode() == ISD::Constant && 561 N.getOperand(3).getOpcode() == ISD::Constant && 562 cast<ConstantSDNode>(N.getOperand(2))->getAPIntValue() == 1 && 563 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) { 564 LHS = N.getOperand(0); 565 RHS = N.getOperand(1); 566 CC = N.getOperand(4); 567 return true; 568 } 569 return false; 570} 571 572// isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only 573// one use. If this is true, it allows the users to invert the operation for 574// free when it is profitable to do so. 575static bool isOneUseSetCC(SDValue N) { 576 SDValue N0, N1, N2; 577 if (isSetCCEquivalent(N, N0, N1, N2) && N.getNode()->hasOneUse()) 578 return true; 579 return false; 580} 581 582SDValue DAGCombiner::ReassociateOps(unsigned Opc, SDLoc DL, 583 SDValue N0, SDValue N1) { 584 EVT VT = N0.getValueType(); 585 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) { 586 if (isa<ConstantSDNode>(N1)) { 587 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2)) 588 SDValue OpNode = 589 DAG.FoldConstantArithmetic(Opc, VT, 590 cast<ConstantSDNode>(N0.getOperand(1)), 591 cast<ConstantSDNode>(N1)); 592 return DAG.getNode(Opc, DL, VT, N0.getOperand(0), OpNode); 593 } 594 if (N0.hasOneUse()) { 595 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use 596 SDValue OpNode = DAG.getNode(Opc, SDLoc(N0), VT, 597 N0.getOperand(0), N1); 598 AddToWorkList(OpNode.getNode()); 599 return DAG.getNode(Opc, DL, VT, OpNode, N0.getOperand(1)); 600 } 601 } 602 603 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) { 604 if (isa<ConstantSDNode>(N0)) { 605 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2)) 606 SDValue OpNode = 607 DAG.FoldConstantArithmetic(Opc, VT, 608 cast<ConstantSDNode>(N1.getOperand(1)), 609 cast<ConstantSDNode>(N0)); 610 return DAG.getNode(Opc, DL, VT, N1.getOperand(0), OpNode); 611 } 612 if (N1.hasOneUse()) { 613 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use 614 SDValue OpNode = DAG.getNode(Opc, SDLoc(N0), VT, 615 N1.getOperand(0), N0); 616 AddToWorkList(OpNode.getNode()); 617 return DAG.getNode(Opc, DL, VT, OpNode, N1.getOperand(1)); 618 } 619 } 620 621 return SDValue(); 622} 623 624SDValue DAGCombiner::CombineTo(SDNode *N, const SDValue *To, unsigned NumTo, 625 bool AddTo) { 626 assert(N->getNumValues() == NumTo && "Broken CombineTo call!"); 627 ++NodesCombined; 628 DEBUG(dbgs() << "\nReplacing.1 "; 629 N->dump(&DAG); 630 dbgs() << "\nWith: "; 631 To[0].getNode()->dump(&DAG); 632 dbgs() << " and " << NumTo-1 << " other values\n"; 633 for (unsigned i = 0, e = NumTo; i != e; ++i) 634 assert((!To[i].getNode() || 635 N->getValueType(i) == To[i].getValueType()) && 636 "Cannot combine value to value of different type!")); 637 WorkListRemover DeadNodes(*this); 638 DAG.ReplaceAllUsesWith(N, To); 639 if (AddTo) { 640 // Push the new nodes and any users onto the worklist 641 for (unsigned i = 0, e = NumTo; i != e; ++i) { 642 if (To[i].getNode()) { 643 AddToWorkList(To[i].getNode()); 644 AddUsersToWorkList(To[i].getNode()); 645 } 646 } 647 } 648 649 // Finally, if the node is now dead, remove it from the graph. The node 650 // may not be dead if the replacement process recursively simplified to 651 // something else needing this node. 652 if (N->use_empty()) { 653 // Nodes can be reintroduced into the worklist. Make sure we do not 654 // process a node that has been replaced. 655 removeFromWorkList(N); 656 657 // Finally, since the node is now dead, remove it from the graph. 658 DAG.DeleteNode(N); 659 } 660 return SDValue(N, 0); 661} 662 663void DAGCombiner:: 664CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) { 665 // Replace all uses. If any nodes become isomorphic to other nodes and 666 // are deleted, make sure to remove them from our worklist. 667 WorkListRemover DeadNodes(*this); 668 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New); 669 670 // Push the new node and any (possibly new) users onto the worklist. 671 AddToWorkList(TLO.New.getNode()); 672 AddUsersToWorkList(TLO.New.getNode()); 673 674 // Finally, if the node is now dead, remove it from the graph. The node 675 // may not be dead if the replacement process recursively simplified to 676 // something else needing this node. 677 if (TLO.Old.getNode()->use_empty()) { 678 removeFromWorkList(TLO.Old.getNode()); 679 680 // If the operands of this node are only used by the node, they will now 681 // be dead. Make sure to visit them first to delete dead nodes early. 682 for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands(); i != e; ++i) 683 if (TLO.Old.getNode()->getOperand(i).getNode()->hasOneUse()) 684 AddToWorkList(TLO.Old.getNode()->getOperand(i).getNode()); 685 686 DAG.DeleteNode(TLO.Old.getNode()); 687 } 688} 689 690/// SimplifyDemandedBits - Check the specified integer node value to see if 691/// it can be simplified or if things it uses can be simplified by bit 692/// propagation. If so, return true. 693bool DAGCombiner::SimplifyDemandedBits(SDValue Op, const APInt &Demanded) { 694 TargetLowering::TargetLoweringOpt TLO(DAG, LegalTypes, LegalOperations); 695 APInt KnownZero, KnownOne; 696 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO)) 697 return false; 698 699 // Revisit the node. 700 AddToWorkList(Op.getNode()); 701 702 // Replace the old value with the new one. 703 ++NodesCombined; 704 DEBUG(dbgs() << "\nReplacing.2 "; 705 TLO.Old.getNode()->dump(&DAG); 706 dbgs() << "\nWith: "; 707 TLO.New.getNode()->dump(&DAG); 708 dbgs() << '\n'); 709 710 CommitTargetLoweringOpt(TLO); 711 return true; 712} 713 714void DAGCombiner::ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad) { 715 SDLoc dl(Load); 716 EVT VT = Load->getValueType(0); 717 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, VT, SDValue(ExtLoad, 0)); 718 719 DEBUG(dbgs() << "\nReplacing.9 "; 720 Load->dump(&DAG); 721 dbgs() << "\nWith: "; 722 Trunc.getNode()->dump(&DAG); 723 dbgs() << '\n'); 724 WorkListRemover DeadNodes(*this); 725 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 0), Trunc); 726 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 1), SDValue(ExtLoad, 1)); 727 removeFromWorkList(Load); 728 DAG.DeleteNode(Load); 729 AddToWorkList(Trunc.getNode()); 730} 731 732SDValue DAGCombiner::PromoteOperand(SDValue Op, EVT PVT, bool &Replace) { 733 Replace = false; 734 SDLoc dl(Op); 735 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Op)) { 736 EVT MemVT = LD->getMemoryVT(); 737 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD) 738 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT) ? ISD::ZEXTLOAD 739 : ISD::EXTLOAD) 740 : LD->getExtensionType(); 741 Replace = true; 742 return DAG.getExtLoad(ExtType, dl, PVT, 743 LD->getChain(), LD->getBasePtr(), 744 LD->getPointerInfo(), 745 MemVT, LD->isVolatile(), 746 LD->isNonTemporal(), LD->getAlignment()); 747 } 748 749 unsigned Opc = Op.getOpcode(); 750 switch (Opc) { 751 default: break; 752 case ISD::AssertSext: 753 return DAG.getNode(ISD::AssertSext, dl, PVT, 754 SExtPromoteOperand(Op.getOperand(0), PVT), 755 Op.getOperand(1)); 756 case ISD::AssertZext: 757 return DAG.getNode(ISD::AssertZext, dl, PVT, 758 ZExtPromoteOperand(Op.getOperand(0), PVT), 759 Op.getOperand(1)); 760 case ISD::Constant: { 761 unsigned ExtOpc = 762 Op.getValueType().isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; 763 return DAG.getNode(ExtOpc, dl, PVT, Op); 764 } 765 } 766 767 if (!TLI.isOperationLegal(ISD::ANY_EXTEND, PVT)) 768 return SDValue(); 769 return DAG.getNode(ISD::ANY_EXTEND, dl, PVT, Op); 770} 771 772SDValue DAGCombiner::SExtPromoteOperand(SDValue Op, EVT PVT) { 773 if (!TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, PVT)) 774 return SDValue(); 775 EVT OldVT = Op.getValueType(); 776 SDLoc dl(Op); 777 bool Replace = false; 778 SDValue NewOp = PromoteOperand(Op, PVT, Replace); 779 if (NewOp.getNode() == 0) 780 return SDValue(); 781 AddToWorkList(NewOp.getNode()); 782 783 if (Replace) 784 ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode()); 785 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NewOp.getValueType(), NewOp, 786 DAG.getValueType(OldVT)); 787} 788 789SDValue DAGCombiner::ZExtPromoteOperand(SDValue Op, EVT PVT) { 790 EVT OldVT = Op.getValueType(); 791 SDLoc dl(Op); 792 bool Replace = false; 793 SDValue NewOp = PromoteOperand(Op, PVT, Replace); 794 if (NewOp.getNode() == 0) 795 return SDValue(); 796 AddToWorkList(NewOp.getNode()); 797 798 if (Replace) 799 ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode()); 800 return DAG.getZeroExtendInReg(NewOp, dl, OldVT); 801} 802 803/// PromoteIntBinOp - Promote the specified integer binary operation if the 804/// target indicates it is beneficial. e.g. On x86, it's usually better to 805/// promote i16 operations to i32 since i16 instructions are longer. 806SDValue DAGCombiner::PromoteIntBinOp(SDValue Op) { 807 if (!LegalOperations) 808 return SDValue(); 809 810 EVT VT = Op.getValueType(); 811 if (VT.isVector() || !VT.isInteger()) 812 return SDValue(); 813 814 // If operation type is 'undesirable', e.g. i16 on x86, consider 815 // promoting it. 816 unsigned Opc = Op.getOpcode(); 817 if (TLI.isTypeDesirableForOp(Opc, VT)) 818 return SDValue(); 819 820 EVT PVT = VT; 821 // Consult target whether it is a good idea to promote this operation and 822 // what's the right type to promote it to. 823 if (TLI.IsDesirableToPromoteOp(Op, PVT)) { 824 assert(PVT != VT && "Don't know what type to promote to!"); 825 826 bool Replace0 = false; 827 SDValue N0 = Op.getOperand(0); 828 SDValue NN0 = PromoteOperand(N0, PVT, Replace0); 829 if (NN0.getNode() == 0) 830 return SDValue(); 831 832 bool Replace1 = false; 833 SDValue N1 = Op.getOperand(1); 834 SDValue NN1; 835 if (N0 == N1) 836 NN1 = NN0; 837 else { 838 NN1 = PromoteOperand(N1, PVT, Replace1); 839 if (NN1.getNode() == 0) 840 return SDValue(); 841 } 842 843 AddToWorkList(NN0.getNode()); 844 if (NN1.getNode()) 845 AddToWorkList(NN1.getNode()); 846 847 if (Replace0) 848 ReplaceLoadWithPromotedLoad(N0.getNode(), NN0.getNode()); 849 if (Replace1) 850 ReplaceLoadWithPromotedLoad(N1.getNode(), NN1.getNode()); 851 852 DEBUG(dbgs() << "\nPromoting "; 853 Op.getNode()->dump(&DAG)); 854 SDLoc dl(Op); 855 return DAG.getNode(ISD::TRUNCATE, dl, VT, 856 DAG.getNode(Opc, dl, PVT, NN0, NN1)); 857 } 858 return SDValue(); 859} 860 861/// PromoteIntShiftOp - Promote the specified integer shift operation if the 862/// target indicates it is beneficial. e.g. On x86, it's usually better to 863/// promote i16 operations to i32 since i16 instructions are longer. 864SDValue DAGCombiner::PromoteIntShiftOp(SDValue Op) { 865 if (!LegalOperations) 866 return SDValue(); 867 868 EVT VT = Op.getValueType(); 869 if (VT.isVector() || !VT.isInteger()) 870 return SDValue(); 871 872 // If operation type is 'undesirable', e.g. i16 on x86, consider 873 // promoting it. 874 unsigned Opc = Op.getOpcode(); 875 if (TLI.isTypeDesirableForOp(Opc, VT)) 876 return SDValue(); 877 878 EVT PVT = VT; 879 // Consult target whether it is a good idea to promote this operation and 880 // what's the right type to promote it to. 881 if (TLI.IsDesirableToPromoteOp(Op, PVT)) { 882 assert(PVT != VT && "Don't know what type to promote to!"); 883 884 bool Replace = false; 885 SDValue N0 = Op.getOperand(0); 886 if (Opc == ISD::SRA) 887 N0 = SExtPromoteOperand(Op.getOperand(0), PVT); 888 else if (Opc == ISD::SRL) 889 N0 = ZExtPromoteOperand(Op.getOperand(0), PVT); 890 else 891 N0 = PromoteOperand(N0, PVT, Replace); 892 if (N0.getNode() == 0) 893 return SDValue(); 894 895 AddToWorkList(N0.getNode()); 896 if (Replace) 897 ReplaceLoadWithPromotedLoad(Op.getOperand(0).getNode(), N0.getNode()); 898 899 DEBUG(dbgs() << "\nPromoting "; 900 Op.getNode()->dump(&DAG)); 901 SDLoc dl(Op); 902 return DAG.getNode(ISD::TRUNCATE, dl, VT, 903 DAG.getNode(Opc, dl, PVT, N0, Op.getOperand(1))); 904 } 905 return SDValue(); 906} 907 908SDValue DAGCombiner::PromoteExtend(SDValue Op) { 909 if (!LegalOperations) 910 return SDValue(); 911 912 EVT VT = Op.getValueType(); 913 if (VT.isVector() || !VT.isInteger()) 914 return SDValue(); 915 916 // If operation type is 'undesirable', e.g. i16 on x86, consider 917 // promoting it. 918 unsigned Opc = Op.getOpcode(); 919 if (TLI.isTypeDesirableForOp(Opc, VT)) 920 return SDValue(); 921 922 EVT PVT = VT; 923 // Consult target whether it is a good idea to promote this operation and 924 // what's the right type to promote it to. 925 if (TLI.IsDesirableToPromoteOp(Op, PVT)) { 926 assert(PVT != VT && "Don't know what type to promote to!"); 927 // fold (aext (aext x)) -> (aext x) 928 // fold (aext (zext x)) -> (zext x) 929 // fold (aext (sext x)) -> (sext x) 930 DEBUG(dbgs() << "\nPromoting "; 931 Op.getNode()->dump(&DAG)); 932 return DAG.getNode(Op.getOpcode(), SDLoc(Op), VT, Op.getOperand(0)); 933 } 934 return SDValue(); 935} 936 937bool DAGCombiner::PromoteLoad(SDValue Op) { 938 if (!LegalOperations) 939 return false; 940 941 EVT VT = Op.getValueType(); 942 if (VT.isVector() || !VT.isInteger()) 943 return false; 944 945 // If operation type is 'undesirable', e.g. i16 on x86, consider 946 // promoting it. 947 unsigned Opc = Op.getOpcode(); 948 if (TLI.isTypeDesirableForOp(Opc, VT)) 949 return false; 950 951 EVT PVT = VT; 952 // Consult target whether it is a good idea to promote this operation and 953 // what's the right type to promote it to. 954 if (TLI.IsDesirableToPromoteOp(Op, PVT)) { 955 assert(PVT != VT && "Don't know what type to promote to!"); 956 957 SDLoc dl(Op); 958 SDNode *N = Op.getNode(); 959 LoadSDNode *LD = cast<LoadSDNode>(N); 960 EVT MemVT = LD->getMemoryVT(); 961 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD) 962 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT) ? ISD::ZEXTLOAD 963 : ISD::EXTLOAD) 964 : LD->getExtensionType(); 965 SDValue NewLD = DAG.getExtLoad(ExtType, dl, PVT, 966 LD->getChain(), LD->getBasePtr(), 967 LD->getPointerInfo(), 968 MemVT, LD->isVolatile(), 969 LD->isNonTemporal(), LD->getAlignment()); 970 SDValue Result = DAG.getNode(ISD::TRUNCATE, dl, VT, NewLD); 971 972 DEBUG(dbgs() << "\nPromoting "; 973 N->dump(&DAG); 974 dbgs() << "\nTo: "; 975 Result.getNode()->dump(&DAG); 976 dbgs() << '\n'); 977 WorkListRemover DeadNodes(*this); 978 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result); 979 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), NewLD.getValue(1)); 980 removeFromWorkList(N); 981 DAG.DeleteNode(N); 982 AddToWorkList(Result.getNode()); 983 return true; 984 } 985 return false; 986} 987 988 989//===----------------------------------------------------------------------===// 990// Main DAG Combiner implementation 991//===----------------------------------------------------------------------===// 992 993void DAGCombiner::Run(CombineLevel AtLevel) { 994 // set the instance variables, so that the various visit routines may use it. 995 Level = AtLevel; 996 LegalOperations = Level >= AfterLegalizeVectorOps; 997 LegalTypes = Level >= AfterLegalizeTypes; 998 999 // Add all the dag nodes to the worklist. 1000 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 1001 E = DAG.allnodes_end(); I != E; ++I) 1002 AddToWorkList(I); 1003 1004 // Create a dummy node (which is not added to allnodes), that adds a reference 1005 // to the root node, preventing it from being deleted, and tracking any 1006 // changes of the root. 1007 HandleSDNode Dummy(DAG.getRoot()); 1008 1009 // The root of the dag may dangle to deleted nodes until the dag combiner is 1010 // done. Set it to null to avoid confusion. 1011 DAG.setRoot(SDValue()); 1012 1013 // while the worklist isn't empty, find a node and 1014 // try and combine it. 1015 while (!WorkListContents.empty()) { 1016 SDNode *N; 1017 // The WorkListOrder holds the SDNodes in order, but it may contain duplicates. 1018 // In order to avoid a linear scan, we use a set (O(log N)) to hold what the 1019 // worklist *should* contain, and check the node we want to visit is should 1020 // actually be visited. 1021 do { 1022 N = WorkListOrder.pop_back_val(); 1023 } while (!WorkListContents.erase(N)); 1024 1025 // If N has no uses, it is dead. Make sure to revisit all N's operands once 1026 // N is deleted from the DAG, since they too may now be dead or may have a 1027 // reduced number of uses, allowing other xforms. 1028 if (N->use_empty() && N != &Dummy) { 1029 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 1030 AddToWorkList(N->getOperand(i).getNode()); 1031 1032 DAG.DeleteNode(N); 1033 continue; 1034 } 1035 1036 SDValue RV = combine(N); 1037 1038 if (RV.getNode() == 0) 1039 continue; 1040 1041 ++NodesCombined; 1042 1043 // If we get back the same node we passed in, rather than a new node or 1044 // zero, we know that the node must have defined multiple values and 1045 // CombineTo was used. Since CombineTo takes care of the worklist 1046 // mechanics for us, we have no work to do in this case. 1047 if (RV.getNode() == N) 1048 continue; 1049 1050 assert(N->getOpcode() != ISD::DELETED_NODE && 1051 RV.getNode()->getOpcode() != ISD::DELETED_NODE && 1052 "Node was deleted but visit returned new node!"); 1053 1054 DEBUG(dbgs() << "\nReplacing.3 "; 1055 N->dump(&DAG); 1056 dbgs() << "\nWith: "; 1057 RV.getNode()->dump(&DAG); 1058 dbgs() << '\n'); 1059 1060 // Transfer debug value. 1061 DAG.TransferDbgValues(SDValue(N, 0), RV); 1062 WorkListRemover DeadNodes(*this); 1063 if (N->getNumValues() == RV.getNode()->getNumValues()) 1064 DAG.ReplaceAllUsesWith(N, RV.getNode()); 1065 else { 1066 assert(N->getValueType(0) == RV.getValueType() && 1067 N->getNumValues() == 1 && "Type mismatch"); 1068 SDValue OpV = RV; 1069 DAG.ReplaceAllUsesWith(N, &OpV); 1070 } 1071 1072 // Push the new node and any users onto the worklist 1073 AddToWorkList(RV.getNode()); 1074 AddUsersToWorkList(RV.getNode()); 1075 1076 // Add any uses of the old node to the worklist in case this node is the 1077 // last one that uses them. They may become dead after this node is 1078 // deleted. 1079 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 1080 AddToWorkList(N->getOperand(i).getNode()); 1081 1082 // Finally, if the node is now dead, remove it from the graph. The node 1083 // may not be dead if the replacement process recursively simplified to 1084 // something else needing this node. 1085 if (N->use_empty()) { 1086 // Nodes can be reintroduced into the worklist. Make sure we do not 1087 // process a node that has been replaced. 1088 removeFromWorkList(N); 1089 1090 // Finally, since the node is now dead, remove it from the graph. 1091 DAG.DeleteNode(N); 1092 } 1093 } 1094 1095 // If the root changed (e.g. it was a dead load, update the root). 1096 DAG.setRoot(Dummy.getValue()); 1097 DAG.RemoveDeadNodes(); 1098} 1099 1100SDValue DAGCombiner::visit(SDNode *N) { 1101 switch (N->getOpcode()) { 1102 default: break; 1103 case ISD::TokenFactor: return visitTokenFactor(N); 1104 case ISD::MERGE_VALUES: return visitMERGE_VALUES(N); 1105 case ISD::ADD: return visitADD(N); 1106 case ISD::SUB: return visitSUB(N); 1107 case ISD::ADDC: return visitADDC(N); 1108 case ISD::SUBC: return visitSUBC(N); 1109 case ISD::ADDE: return visitADDE(N); 1110 case ISD::SUBE: return visitSUBE(N); 1111 case ISD::MUL: return visitMUL(N); 1112 case ISD::SDIV: return visitSDIV(N); 1113 case ISD::UDIV: return visitUDIV(N); 1114 case ISD::SREM: return visitSREM(N); 1115 case ISD::UREM: return visitUREM(N); 1116 case ISD::MULHU: return visitMULHU(N); 1117 case ISD::MULHS: return visitMULHS(N); 1118 case ISD::SMUL_LOHI: return visitSMUL_LOHI(N); 1119 case ISD::UMUL_LOHI: return visitUMUL_LOHI(N); 1120 case ISD::SMULO: return visitSMULO(N); 1121 case ISD::UMULO: return visitUMULO(N); 1122 case ISD::SDIVREM: return visitSDIVREM(N); 1123 case ISD::UDIVREM: return visitUDIVREM(N); 1124 case ISD::AND: return visitAND(N); 1125 case ISD::OR: return visitOR(N); 1126 case ISD::XOR: return visitXOR(N); 1127 case ISD::SHL: return visitSHL(N); 1128 case ISD::SRA: return visitSRA(N); 1129 case ISD::SRL: return visitSRL(N); 1130 case ISD::CTLZ: return visitCTLZ(N); 1131 case ISD::CTLZ_ZERO_UNDEF: return visitCTLZ_ZERO_UNDEF(N); 1132 case ISD::CTTZ: return visitCTTZ(N); 1133 case ISD::CTTZ_ZERO_UNDEF: return visitCTTZ_ZERO_UNDEF(N); 1134 case ISD::CTPOP: return visitCTPOP(N); 1135 case ISD::SELECT: return visitSELECT(N); 1136 case ISD::VSELECT: return visitVSELECT(N); 1137 case ISD::SELECT_CC: return visitSELECT_CC(N); 1138 case ISD::SETCC: return visitSETCC(N); 1139 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N); 1140 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N); 1141 case ISD::ANY_EXTEND: return visitANY_EXTEND(N); 1142 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N); 1143 case ISD::TRUNCATE: return visitTRUNCATE(N); 1144 case ISD::BITCAST: return visitBITCAST(N); 1145 case ISD::BUILD_PAIR: return visitBUILD_PAIR(N); 1146 case ISD::FADD: return visitFADD(N); 1147 case ISD::FSUB: return visitFSUB(N); 1148 case ISD::FMUL: return visitFMUL(N); 1149 case ISD::FMA: return visitFMA(N); 1150 case ISD::FDIV: return visitFDIV(N); 1151 case ISD::FREM: return visitFREM(N); 1152 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N); 1153 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N); 1154 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N); 1155 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N); 1156 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N); 1157 case ISD::FP_ROUND: return visitFP_ROUND(N); 1158 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N); 1159 case ISD::FP_EXTEND: return visitFP_EXTEND(N); 1160 case ISD::FNEG: return visitFNEG(N); 1161 case ISD::FABS: return visitFABS(N); 1162 case ISD::FFLOOR: return visitFFLOOR(N); 1163 case ISD::FCEIL: return visitFCEIL(N); 1164 case ISD::FTRUNC: return visitFTRUNC(N); 1165 case ISD::BRCOND: return visitBRCOND(N); 1166 case ISD::BR_CC: return visitBR_CC(N); 1167 case ISD::LOAD: return visitLOAD(N); 1168 case ISD::STORE: return visitSTORE(N); 1169 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N); 1170 case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N); 1171 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N); 1172 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N); 1173 case ISD::EXTRACT_SUBVECTOR: return visitEXTRACT_SUBVECTOR(N); 1174 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N); 1175 } 1176 return SDValue(); 1177} 1178 1179SDValue DAGCombiner::combine(SDNode *N) { 1180 SDValue RV = visit(N); 1181 1182 // If nothing happened, try a target-specific DAG combine. 1183 if (RV.getNode() == 0) { 1184 assert(N->getOpcode() != ISD::DELETED_NODE && 1185 "Node was deleted but visit returned NULL!"); 1186 1187 if (N->getOpcode() >= ISD::BUILTIN_OP_END || 1188 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) { 1189 1190 // Expose the DAG combiner to the target combiner impls. 1191 TargetLowering::DAGCombinerInfo 1192 DagCombineInfo(DAG, Level, false, this); 1193 1194 RV = TLI.PerformDAGCombine(N, DagCombineInfo); 1195 } 1196 } 1197 1198 // If nothing happened still, try promoting the operation. 1199 if (RV.getNode() == 0) { 1200 switch (N->getOpcode()) { 1201 default: break; 1202 case ISD::ADD: 1203 case ISD::SUB: 1204 case ISD::MUL: 1205 case ISD::AND: 1206 case ISD::OR: 1207 case ISD::XOR: 1208 RV = PromoteIntBinOp(SDValue(N, 0)); 1209 break; 1210 case ISD::SHL: 1211 case ISD::SRA: 1212 case ISD::SRL: 1213 RV = PromoteIntShiftOp(SDValue(N, 0)); 1214 break; 1215 case ISD::SIGN_EXTEND: 1216 case ISD::ZERO_EXTEND: 1217 case ISD::ANY_EXTEND: 1218 RV = PromoteExtend(SDValue(N, 0)); 1219 break; 1220 case ISD::LOAD: 1221 if (PromoteLoad(SDValue(N, 0))) 1222 RV = SDValue(N, 0); 1223 break; 1224 } 1225 } 1226 1227 // If N is a commutative binary node, try commuting it to enable more 1228 // sdisel CSE. 1229 if (RV.getNode() == 0 && 1230 SelectionDAG::isCommutativeBinOp(N->getOpcode()) && 1231 N->getNumValues() == 1) { 1232 SDValue N0 = N->getOperand(0); 1233 SDValue N1 = N->getOperand(1); 1234 1235 // Constant operands are canonicalized to RHS. 1236 if (isa<ConstantSDNode>(N0) || !isa<ConstantSDNode>(N1)) { 1237 SDValue Ops[] = { N1, N0 }; 1238 SDNode *CSENode = DAG.getNodeIfExists(N->getOpcode(), N->getVTList(), 1239 Ops, 2); 1240 if (CSENode) 1241 return SDValue(CSENode, 0); 1242 } 1243 } 1244 1245 return RV; 1246} 1247 1248/// getInputChainForNode - Given a node, return its input chain if it has one, 1249/// otherwise return a null sd operand. 1250static SDValue getInputChainForNode(SDNode *N) { 1251 if (unsigned NumOps = N->getNumOperands()) { 1252 if (N->getOperand(0).getValueType() == MVT::Other) 1253 return N->getOperand(0); 1254 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other) 1255 return N->getOperand(NumOps-1); 1256 for (unsigned i = 1; i < NumOps-1; ++i) 1257 if (N->getOperand(i).getValueType() == MVT::Other) 1258 return N->getOperand(i); 1259 } 1260 return SDValue(); 1261} 1262 1263SDValue DAGCombiner::visitTokenFactor(SDNode *N) { 1264 // If N has two operands, where one has an input chain equal to the other, 1265 // the 'other' chain is redundant. 1266 if (N->getNumOperands() == 2) { 1267 if (getInputChainForNode(N->getOperand(0).getNode()) == N->getOperand(1)) 1268 return N->getOperand(0); 1269 if (getInputChainForNode(N->getOperand(1).getNode()) == N->getOperand(0)) 1270 return N->getOperand(1); 1271 } 1272 1273 SmallVector<SDNode *, 8> TFs; // List of token factors to visit. 1274 SmallVector<SDValue, 8> Ops; // Ops for replacing token factor. 1275 SmallPtrSet<SDNode*, 16> SeenOps; 1276 bool Changed = false; // If we should replace this token factor. 1277 1278 // Start out with this token factor. 1279 TFs.push_back(N); 1280 1281 // Iterate through token factors. The TFs grows when new token factors are 1282 // encountered. 1283 for (unsigned i = 0; i < TFs.size(); ++i) { 1284 SDNode *TF = TFs[i]; 1285 1286 // Check each of the operands. 1287 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) { 1288 SDValue Op = TF->getOperand(i); 1289 1290 switch (Op.getOpcode()) { 1291 case ISD::EntryToken: 1292 // Entry tokens don't need to be added to the list. They are 1293 // rededundant. 1294 Changed = true; 1295 break; 1296 1297 case ISD::TokenFactor: 1298 if (Op.hasOneUse() && 1299 std::find(TFs.begin(), TFs.end(), Op.getNode()) == TFs.end()) { 1300 // Queue up for processing. 1301 TFs.push_back(Op.getNode()); 1302 // Clean up in case the token factor is removed. 1303 AddToWorkList(Op.getNode()); 1304 Changed = true; 1305 break; 1306 } 1307 // Fall thru 1308 1309 default: 1310 // Only add if it isn't already in the list. 1311 if (SeenOps.insert(Op.getNode())) 1312 Ops.push_back(Op); 1313 else 1314 Changed = true; 1315 break; 1316 } 1317 } 1318 } 1319 1320 SDValue Result; 1321 1322 // If we've change things around then replace token factor. 1323 if (Changed) { 1324 if (Ops.empty()) { 1325 // The entry token is the only possible outcome. 1326 Result = DAG.getEntryNode(); 1327 } else { 1328 // New and improved token factor. 1329 Result = DAG.getNode(ISD::TokenFactor, SDLoc(N), 1330 MVT::Other, &Ops[0], Ops.size()); 1331 } 1332 1333 // Don't add users to work list. 1334 return CombineTo(N, Result, false); 1335 } 1336 1337 return Result; 1338} 1339 1340/// MERGE_VALUES can always be eliminated. 1341SDValue DAGCombiner::visitMERGE_VALUES(SDNode *N) { 1342 WorkListRemover DeadNodes(*this); 1343 // Replacing results may cause a different MERGE_VALUES to suddenly 1344 // be CSE'd with N, and carry its uses with it. Iterate until no 1345 // uses remain, to ensure that the node can be safely deleted. 1346 // First add the users of this node to the work list so that they 1347 // can be tried again once they have new operands. 1348 AddUsersToWorkList(N); 1349 do { 1350 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 1351 DAG.ReplaceAllUsesOfValueWith(SDValue(N, i), N->getOperand(i)); 1352 } while (!N->use_empty()); 1353 removeFromWorkList(N); 1354 DAG.DeleteNode(N); 1355 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1356} 1357 1358static 1359SDValue combineShlAddConstant(SDLoc DL, SDValue N0, SDValue N1, 1360 SelectionDAG &DAG) { 1361 EVT VT = N0.getValueType(); 1362 SDValue N00 = N0.getOperand(0); 1363 SDValue N01 = N0.getOperand(1); 1364 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01); 1365 1366 if (N01C && N00.getOpcode() == ISD::ADD && N00.getNode()->hasOneUse() && 1367 isa<ConstantSDNode>(N00.getOperand(1))) { 1368 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 1369 N0 = DAG.getNode(ISD::ADD, SDLoc(N0), VT, 1370 DAG.getNode(ISD::SHL, SDLoc(N00), VT, 1371 N00.getOperand(0), N01), 1372 DAG.getNode(ISD::SHL, SDLoc(N01), VT, 1373 N00.getOperand(1), N01)); 1374 return DAG.getNode(ISD::ADD, DL, VT, N0, N1); 1375 } 1376 1377 return SDValue(); 1378} 1379 1380SDValue DAGCombiner::visitADD(SDNode *N) { 1381 SDValue N0 = N->getOperand(0); 1382 SDValue N1 = N->getOperand(1); 1383 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1384 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1385 EVT VT = N0.getValueType(); 1386 1387 // fold vector ops 1388 if (VT.isVector()) { 1389 SDValue FoldedVOp = SimplifyVBinOp(N); 1390 if (FoldedVOp.getNode()) return FoldedVOp; 1391 1392 // fold (add x, 0) -> x, vector edition 1393 if (ISD::isBuildVectorAllZeros(N1.getNode())) 1394 return N0; 1395 if (ISD::isBuildVectorAllZeros(N0.getNode())) 1396 return N1; 1397 } 1398 1399 // fold (add x, undef) -> undef 1400 if (N0.getOpcode() == ISD::UNDEF) 1401 return N0; 1402 if (N1.getOpcode() == ISD::UNDEF) 1403 return N1; 1404 // fold (add c1, c2) -> c1+c2 1405 if (N0C && N1C) 1406 return DAG.FoldConstantArithmetic(ISD::ADD, VT, N0C, N1C); 1407 // canonicalize constant to RHS 1408 if (N0C && !N1C) 1409 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N1, N0); 1410 // fold (add x, 0) -> x 1411 if (N1C && N1C->isNullValue()) 1412 return N0; 1413 // fold (add Sym, c) -> Sym+c 1414 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0)) 1415 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA) && N1C && 1416 GA->getOpcode() == ISD::GlobalAddress) 1417 return DAG.getGlobalAddress(GA->getGlobal(), SDLoc(N1C), VT, 1418 GA->getOffset() + 1419 (uint64_t)N1C->getSExtValue()); 1420 // fold ((c1-A)+c2) -> (c1+c2)-A 1421 if (N1C && N0.getOpcode() == ISD::SUB) 1422 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0))) 1423 return DAG.getNode(ISD::SUB, SDLoc(N), VT, 1424 DAG.getConstant(N1C->getAPIntValue()+ 1425 N0C->getAPIntValue(), VT), 1426 N0.getOperand(1)); 1427 // reassociate add 1428 SDValue RADD = ReassociateOps(ISD::ADD, SDLoc(N), N0, N1); 1429 if (RADD.getNode() != 0) 1430 return RADD; 1431 // fold ((0-A) + B) -> B-A 1432 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) && 1433 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue()) 1434 return DAG.getNode(ISD::SUB, SDLoc(N), VT, N1, N0.getOperand(1)); 1435 // fold (A + (0-B)) -> A-B 1436 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) && 1437 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue()) 1438 return DAG.getNode(ISD::SUB, SDLoc(N), VT, N0, N1.getOperand(1)); 1439 // fold (A+(B-A)) -> B 1440 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1)) 1441 return N1.getOperand(0); 1442 // fold ((B-A)+A) -> B 1443 if (N0.getOpcode() == ISD::SUB && N1 == N0.getOperand(1)) 1444 return N0.getOperand(0); 1445 // fold (A+(B-(A+C))) to (B-C) 1446 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD && 1447 N0 == N1.getOperand(1).getOperand(0)) 1448 return DAG.getNode(ISD::SUB, SDLoc(N), VT, N1.getOperand(0), 1449 N1.getOperand(1).getOperand(1)); 1450 // fold (A+(B-(C+A))) to (B-C) 1451 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD && 1452 N0 == N1.getOperand(1).getOperand(1)) 1453 return DAG.getNode(ISD::SUB, SDLoc(N), VT, N1.getOperand(0), 1454 N1.getOperand(1).getOperand(0)); 1455 // fold (A+((B-A)+or-C)) to (B+or-C) 1456 if ((N1.getOpcode() == ISD::SUB || N1.getOpcode() == ISD::ADD) && 1457 N1.getOperand(0).getOpcode() == ISD::SUB && 1458 N0 == N1.getOperand(0).getOperand(1)) 1459 return DAG.getNode(N1.getOpcode(), SDLoc(N), VT, 1460 N1.getOperand(0).getOperand(0), N1.getOperand(1)); 1461 1462 // fold (A-B)+(C-D) to (A+C)-(B+D) when A or C is constant 1463 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB) { 1464 SDValue N00 = N0.getOperand(0); 1465 SDValue N01 = N0.getOperand(1); 1466 SDValue N10 = N1.getOperand(0); 1467 SDValue N11 = N1.getOperand(1); 1468 1469 if (isa<ConstantSDNode>(N00) || isa<ConstantSDNode>(N10)) 1470 return DAG.getNode(ISD::SUB, SDLoc(N), VT, 1471 DAG.getNode(ISD::ADD, SDLoc(N0), VT, N00, N10), 1472 DAG.getNode(ISD::ADD, SDLoc(N1), VT, N01, N11)); 1473 } 1474 1475 if (!VT.isVector() && SimplifyDemandedBits(SDValue(N, 0))) 1476 return SDValue(N, 0); 1477 1478 // fold (a+b) -> (a|b) iff a and b share no bits. 1479 if (VT.isInteger() && !VT.isVector()) { 1480 APInt LHSZero, LHSOne; 1481 APInt RHSZero, RHSOne; 1482 DAG.ComputeMaskedBits(N0, LHSZero, LHSOne); 1483 1484 if (LHSZero.getBoolValue()) { 1485 DAG.ComputeMaskedBits(N1, RHSZero, RHSOne); 1486 1487 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1488 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1489 if ((RHSZero & ~LHSZero) == ~LHSZero || (LHSZero & ~RHSZero) == ~RHSZero) 1490 return DAG.getNode(ISD::OR, SDLoc(N), VT, N0, N1); 1491 } 1492 } 1493 1494 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 1495 if (N0.getOpcode() == ISD::SHL && N0.getNode()->hasOneUse()) { 1496 SDValue Result = combineShlAddConstant(SDLoc(N), N0, N1, DAG); 1497 if (Result.getNode()) return Result; 1498 } 1499 if (N1.getOpcode() == ISD::SHL && N1.getNode()->hasOneUse()) { 1500 SDValue Result = combineShlAddConstant(SDLoc(N), N1, N0, DAG); 1501 if (Result.getNode()) return Result; 1502 } 1503 1504 // fold (add x, shl(0 - y, n)) -> sub(x, shl(y, n)) 1505 if (N1.getOpcode() == ISD::SHL && 1506 N1.getOperand(0).getOpcode() == ISD::SUB) 1507 if (ConstantSDNode *C = 1508 dyn_cast<ConstantSDNode>(N1.getOperand(0).getOperand(0))) 1509 if (C->getAPIntValue() == 0) 1510 return DAG.getNode(ISD::SUB, SDLoc(N), VT, N0, 1511 DAG.getNode(ISD::SHL, SDLoc(N), VT, 1512 N1.getOperand(0).getOperand(1), 1513 N1.getOperand(1))); 1514 if (N0.getOpcode() == ISD::SHL && 1515 N0.getOperand(0).getOpcode() == ISD::SUB) 1516 if (ConstantSDNode *C = 1517 dyn_cast<ConstantSDNode>(N0.getOperand(0).getOperand(0))) 1518 if (C->getAPIntValue() == 0) 1519 return DAG.getNode(ISD::SUB, SDLoc(N), VT, N1, 1520 DAG.getNode(ISD::SHL, SDLoc(N), VT, 1521 N0.getOperand(0).getOperand(1), 1522 N0.getOperand(1))); 1523 1524 if (N1.getOpcode() == ISD::AND) { 1525 SDValue AndOp0 = N1.getOperand(0); 1526 ConstantSDNode *AndOp1 = dyn_cast<ConstantSDNode>(N1->getOperand(1)); 1527 unsigned NumSignBits = DAG.ComputeNumSignBits(AndOp0); 1528 unsigned DestBits = VT.getScalarType().getSizeInBits(); 1529 1530 // (add z, (and (sbbl x, x), 1)) -> (sub z, (sbbl x, x)) 1531 // and similar xforms where the inner op is either ~0 or 0. 1532 if (NumSignBits == DestBits && AndOp1 && AndOp1->isOne()) { 1533 SDLoc DL(N); 1534 return DAG.getNode(ISD::SUB, DL, VT, N->getOperand(0), AndOp0); 1535 } 1536 } 1537 1538 // add (sext i1), X -> sub X, (zext i1) 1539 if (N0.getOpcode() == ISD::SIGN_EXTEND && 1540 N0.getOperand(0).getValueType() == MVT::i1 && 1541 !TLI.isOperationLegal(ISD::SIGN_EXTEND, MVT::i1)) { 1542 SDLoc DL(N); 1543 SDValue ZExt = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0)); 1544 return DAG.getNode(ISD::SUB, DL, VT, N1, ZExt); 1545 } 1546 1547 return SDValue(); 1548} 1549 1550SDValue DAGCombiner::visitADDC(SDNode *N) { 1551 SDValue N0 = N->getOperand(0); 1552 SDValue N1 = N->getOperand(1); 1553 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1554 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1555 EVT VT = N0.getValueType(); 1556 1557 // If the flag result is dead, turn this into an ADD. 1558 if (!N->hasAnyUseOfValue(1)) 1559 return CombineTo(N, DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, N1), 1560 DAG.getNode(ISD::CARRY_FALSE, 1561 SDLoc(N), MVT::Glue)); 1562 1563 // canonicalize constant to RHS. 1564 if (N0C && !N1C) 1565 return DAG.getNode(ISD::ADDC, SDLoc(N), N->getVTList(), N1, N0); 1566 1567 // fold (addc x, 0) -> x + no carry out 1568 if (N1C && N1C->isNullValue()) 1569 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, 1570 SDLoc(N), MVT::Glue)); 1571 1572 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits. 1573 APInt LHSZero, LHSOne; 1574 APInt RHSZero, RHSOne; 1575 DAG.ComputeMaskedBits(N0, LHSZero, LHSOne); 1576 1577 if (LHSZero.getBoolValue()) { 1578 DAG.ComputeMaskedBits(N1, RHSZero, RHSOne); 1579 1580 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1581 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1582 if ((RHSZero & ~LHSZero) == ~LHSZero || (LHSZero & ~RHSZero) == ~RHSZero) 1583 return CombineTo(N, DAG.getNode(ISD::OR, SDLoc(N), VT, N0, N1), 1584 DAG.getNode(ISD::CARRY_FALSE, 1585 SDLoc(N), MVT::Glue)); 1586 } 1587 1588 return SDValue(); 1589} 1590 1591SDValue DAGCombiner::visitADDE(SDNode *N) { 1592 SDValue N0 = N->getOperand(0); 1593 SDValue N1 = N->getOperand(1); 1594 SDValue CarryIn = N->getOperand(2); 1595 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1596 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1597 1598 // canonicalize constant to RHS 1599 if (N0C && !N1C) 1600 return DAG.getNode(ISD::ADDE, SDLoc(N), N->getVTList(), 1601 N1, N0, CarryIn); 1602 1603 // fold (adde x, y, false) -> (addc x, y) 1604 if (CarryIn.getOpcode() == ISD::CARRY_FALSE) 1605 return DAG.getNode(ISD::ADDC, SDLoc(N), N->getVTList(), N0, N1); 1606 1607 return SDValue(); 1608} 1609 1610// Since it may not be valid to emit a fold to zero for vector initializers 1611// check if we can before folding. 1612static SDValue tryFoldToZero(SDLoc DL, const TargetLowering &TLI, EVT VT, 1613 SelectionDAG &DAG, bool LegalOperations) { 1614 if (!VT.isVector()) { 1615 return DAG.getConstant(0, VT); 1616 } 1617 if (!LegalOperations || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) { 1618 // Produce a vector of zeros. 1619 SDValue El = DAG.getConstant(0, VT.getVectorElementType()); 1620 std::vector<SDValue> Ops(VT.getVectorNumElements(), El); 1621 return DAG.getNode(ISD::BUILD_VECTOR, DL, VT, 1622 &Ops[0], Ops.size()); 1623 } 1624 return SDValue(); 1625} 1626 1627SDValue DAGCombiner::visitSUB(SDNode *N) { 1628 SDValue N0 = N->getOperand(0); 1629 SDValue N1 = N->getOperand(1); 1630 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1631 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1632 ConstantSDNode *N1C1 = N1.getOpcode() != ISD::ADD ? 0 : 1633 dyn_cast<ConstantSDNode>(N1.getOperand(1).getNode()); 1634 EVT VT = N0.getValueType(); 1635 1636 // fold vector ops 1637 if (VT.isVector()) { 1638 SDValue FoldedVOp = SimplifyVBinOp(N); 1639 if (FoldedVOp.getNode()) return FoldedVOp; 1640 1641 // fold (sub x, 0) -> x, vector edition 1642 if (ISD::isBuildVectorAllZeros(N1.getNode())) 1643 return N0; 1644 } 1645 1646 // fold (sub x, x) -> 0 1647 // FIXME: Refactor this and xor and other similar operations together. 1648 if (N0 == N1) 1649 return tryFoldToZero(SDLoc(N), TLI, VT, DAG, LegalOperations); 1650 // fold (sub c1, c2) -> c1-c2 1651 if (N0C && N1C) 1652 return DAG.FoldConstantArithmetic(ISD::SUB, VT, N0C, N1C); 1653 // fold (sub x, c) -> (add x, -c) 1654 if (N1C) 1655 return DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, 1656 DAG.getConstant(-N1C->getAPIntValue(), VT)); 1657 // Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1) 1658 if (N0C && N0C->isAllOnesValue()) 1659 return DAG.getNode(ISD::XOR, SDLoc(N), VT, N1, N0); 1660 // fold A-(A-B) -> B 1661 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(0)) 1662 return N1.getOperand(1); 1663 // fold (A+B)-A -> B 1664 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1) 1665 return N0.getOperand(1); 1666 // fold (A+B)-B -> A 1667 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1) 1668 return N0.getOperand(0); 1669 // fold C2-(A+C1) -> (C2-C1)-A 1670 if (N1.getOpcode() == ISD::ADD && N0C && N1C1) { 1671 SDValue NewC = DAG.getConstant(N0C->getAPIntValue() - N1C1->getAPIntValue(), 1672 VT); 1673 return DAG.getNode(ISD::SUB, SDLoc(N), VT, NewC, 1674 N1.getOperand(0)); 1675 } 1676 // fold ((A+(B+or-C))-B) -> A+or-C 1677 if (N0.getOpcode() == ISD::ADD && 1678 (N0.getOperand(1).getOpcode() == ISD::SUB || 1679 N0.getOperand(1).getOpcode() == ISD::ADD) && 1680 N0.getOperand(1).getOperand(0) == N1) 1681 return DAG.getNode(N0.getOperand(1).getOpcode(), SDLoc(N), VT, 1682 N0.getOperand(0), N0.getOperand(1).getOperand(1)); 1683 // fold ((A+(C+B))-B) -> A+C 1684 if (N0.getOpcode() == ISD::ADD && 1685 N0.getOperand(1).getOpcode() == ISD::ADD && 1686 N0.getOperand(1).getOperand(1) == N1) 1687 return DAG.getNode(ISD::ADD, SDLoc(N), VT, 1688 N0.getOperand(0), N0.getOperand(1).getOperand(0)); 1689 // fold ((A-(B-C))-C) -> A-B 1690 if (N0.getOpcode() == ISD::SUB && 1691 N0.getOperand(1).getOpcode() == ISD::SUB && 1692 N0.getOperand(1).getOperand(1) == N1) 1693 return DAG.getNode(ISD::SUB, SDLoc(N), VT, 1694 N0.getOperand(0), N0.getOperand(1).getOperand(0)); 1695 1696 // If either operand of a sub is undef, the result is undef 1697 if (N0.getOpcode() == ISD::UNDEF) 1698 return N0; 1699 if (N1.getOpcode() == ISD::UNDEF) 1700 return N1; 1701 1702 // If the relocation model supports it, consider symbol offsets. 1703 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0)) 1704 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA)) { 1705 // fold (sub Sym, c) -> Sym-c 1706 if (N1C && GA->getOpcode() == ISD::GlobalAddress) 1707 return DAG.getGlobalAddress(GA->getGlobal(), SDLoc(N1C), VT, 1708 GA->getOffset() - 1709 (uint64_t)N1C->getSExtValue()); 1710 // fold (sub Sym+c1, Sym+c2) -> c1-c2 1711 if (GlobalAddressSDNode *GB = dyn_cast<GlobalAddressSDNode>(N1)) 1712 if (GA->getGlobal() == GB->getGlobal()) 1713 return DAG.getConstant((uint64_t)GA->getOffset() - GB->getOffset(), 1714 VT); 1715 } 1716 1717 return SDValue(); 1718} 1719 1720SDValue DAGCombiner::visitSUBC(SDNode *N) { 1721 SDValue N0 = N->getOperand(0); 1722 SDValue N1 = N->getOperand(1); 1723 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1724 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1725 EVT VT = N0.getValueType(); 1726 1727 // If the flag result is dead, turn this into an SUB. 1728 if (!N->hasAnyUseOfValue(1)) 1729 return CombineTo(N, DAG.getNode(ISD::SUB, SDLoc(N), VT, N0, N1), 1730 DAG.getNode(ISD::CARRY_FALSE, SDLoc(N), 1731 MVT::Glue)); 1732 1733 // fold (subc x, x) -> 0 + no borrow 1734 if (N0 == N1) 1735 return CombineTo(N, DAG.getConstant(0, VT), 1736 DAG.getNode(ISD::CARRY_FALSE, SDLoc(N), 1737 MVT::Glue)); 1738 1739 // fold (subc x, 0) -> x + no borrow 1740 if (N1C && N1C->isNullValue()) 1741 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, SDLoc(N), 1742 MVT::Glue)); 1743 1744 // Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1) + no borrow 1745 if (N0C && N0C->isAllOnesValue()) 1746 return CombineTo(N, DAG.getNode(ISD::XOR, SDLoc(N), VT, N1, N0), 1747 DAG.getNode(ISD::CARRY_FALSE, SDLoc(N), 1748 MVT::Glue)); 1749 1750 return SDValue(); 1751} 1752 1753SDValue DAGCombiner::visitSUBE(SDNode *N) { 1754 SDValue N0 = N->getOperand(0); 1755 SDValue N1 = N->getOperand(1); 1756 SDValue CarryIn = N->getOperand(2); 1757 1758 // fold (sube x, y, false) -> (subc x, y) 1759 if (CarryIn.getOpcode() == ISD::CARRY_FALSE) 1760 return DAG.getNode(ISD::SUBC, SDLoc(N), N->getVTList(), N0, N1); 1761 1762 return SDValue(); 1763} 1764 1765SDValue DAGCombiner::visitMUL(SDNode *N) { 1766 SDValue N0 = N->getOperand(0); 1767 SDValue N1 = N->getOperand(1); 1768 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1769 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1770 EVT VT = N0.getValueType(); 1771 1772 // fold vector ops 1773 if (VT.isVector()) { 1774 SDValue FoldedVOp = SimplifyVBinOp(N); 1775 if (FoldedVOp.getNode()) return FoldedVOp; 1776 } 1777 1778 // fold (mul x, undef) -> 0 1779 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1780 return DAG.getConstant(0, VT); 1781 // fold (mul c1, c2) -> c1*c2 1782 if (N0C && N1C) 1783 return DAG.FoldConstantArithmetic(ISD::MUL, VT, N0C, N1C); 1784 // canonicalize constant to RHS 1785 if (N0C && !N1C) 1786 return DAG.getNode(ISD::MUL, SDLoc(N), VT, N1, N0); 1787 // fold (mul x, 0) -> 0 1788 if (N1C && N1C->isNullValue()) 1789 return N1; 1790 // fold (mul x, -1) -> 0-x 1791 if (N1C && N1C->isAllOnesValue()) 1792 return DAG.getNode(ISD::SUB, SDLoc(N), VT, 1793 DAG.getConstant(0, VT), N0); 1794 // fold (mul x, (1 << c)) -> x << c 1795 if (N1C && N1C->getAPIntValue().isPowerOf2()) 1796 return DAG.getNode(ISD::SHL, SDLoc(N), VT, N0, 1797 DAG.getConstant(N1C->getAPIntValue().logBase2(), 1798 getShiftAmountTy(N0.getValueType()))); 1799 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c 1800 if (N1C && (-N1C->getAPIntValue()).isPowerOf2()) { 1801 unsigned Log2Val = (-N1C->getAPIntValue()).logBase2(); 1802 // FIXME: If the input is something that is easily negated (e.g. a 1803 // single-use add), we should put the negate there. 1804 return DAG.getNode(ISD::SUB, SDLoc(N), VT, 1805 DAG.getConstant(0, VT), 1806 DAG.getNode(ISD::SHL, SDLoc(N), VT, N0, 1807 DAG.getConstant(Log2Val, 1808 getShiftAmountTy(N0.getValueType())))); 1809 } 1810 // (mul (shl X, c1), c2) -> (mul X, c2 << c1) 1811 if (N1C && N0.getOpcode() == ISD::SHL && 1812 isa<ConstantSDNode>(N0.getOperand(1))) { 1813 SDValue C3 = DAG.getNode(ISD::SHL, SDLoc(N), VT, 1814 N1, N0.getOperand(1)); 1815 AddToWorkList(C3.getNode()); 1816 return DAG.getNode(ISD::MUL, SDLoc(N), VT, 1817 N0.getOperand(0), C3); 1818 } 1819 1820 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one 1821 // use. 1822 { 1823 SDValue Sh(0,0), Y(0,0); 1824 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)). 1825 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) && 1826 N0.getNode()->hasOneUse()) { 1827 Sh = N0; Y = N1; 1828 } else if (N1.getOpcode() == ISD::SHL && 1829 isa<ConstantSDNode>(N1.getOperand(1)) && 1830 N1.getNode()->hasOneUse()) { 1831 Sh = N1; Y = N0; 1832 } 1833 1834 if (Sh.getNode()) { 1835 SDValue Mul = DAG.getNode(ISD::MUL, SDLoc(N), VT, 1836 Sh.getOperand(0), Y); 1837 return DAG.getNode(ISD::SHL, SDLoc(N), VT, 1838 Mul, Sh.getOperand(1)); 1839 } 1840 } 1841 1842 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2) 1843 if (N1C && N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse() && 1844 isa<ConstantSDNode>(N0.getOperand(1))) 1845 return DAG.getNode(ISD::ADD, SDLoc(N), VT, 1846 DAG.getNode(ISD::MUL, SDLoc(N0), VT, 1847 N0.getOperand(0), N1), 1848 DAG.getNode(ISD::MUL, SDLoc(N1), VT, 1849 N0.getOperand(1), N1)); 1850 1851 // reassociate mul 1852 SDValue RMUL = ReassociateOps(ISD::MUL, SDLoc(N), N0, N1); 1853 if (RMUL.getNode() != 0) 1854 return RMUL; 1855 1856 return SDValue(); 1857} 1858 1859SDValue DAGCombiner::visitSDIV(SDNode *N) { 1860 SDValue N0 = N->getOperand(0); 1861 SDValue N1 = N->getOperand(1); 1862 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1863 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1864 EVT VT = N->getValueType(0); 1865 1866 // fold vector ops 1867 if (VT.isVector()) { 1868 SDValue FoldedVOp = SimplifyVBinOp(N); 1869 if (FoldedVOp.getNode()) return FoldedVOp; 1870 } 1871 1872 // fold (sdiv c1, c2) -> c1/c2 1873 if (N0C && N1C && !N1C->isNullValue()) 1874 return DAG.FoldConstantArithmetic(ISD::SDIV, VT, N0C, N1C); 1875 // fold (sdiv X, 1) -> X 1876 if (N1C && N1C->getAPIntValue() == 1LL) 1877 return N0; 1878 // fold (sdiv X, -1) -> 0-X 1879 if (N1C && N1C->isAllOnesValue()) 1880 return DAG.getNode(ISD::SUB, SDLoc(N), VT, 1881 DAG.getConstant(0, VT), N0); 1882 // If we know the sign bits of both operands are zero, strength reduce to a 1883 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2 1884 if (!VT.isVector()) { 1885 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 1886 return DAG.getNode(ISD::UDIV, SDLoc(N), N1.getValueType(), 1887 N0, N1); 1888 } 1889 // fold (sdiv X, pow2) -> simple ops after legalize 1890 if (N1C && !N1C->isNullValue() && 1891 (N1C->getAPIntValue().isPowerOf2() || 1892 (-N1C->getAPIntValue()).isPowerOf2())) { 1893 // If dividing by powers of two is cheap, then don't perform the following 1894 // fold. 1895 if (TLI.isPow2DivCheap()) 1896 return SDValue(); 1897 1898 unsigned lg2 = N1C->getAPIntValue().countTrailingZeros(); 1899 1900 // Splat the sign bit into the register 1901 SDValue SGN = DAG.getNode(ISD::SRA, SDLoc(N), VT, N0, 1902 DAG.getConstant(VT.getSizeInBits()-1, 1903 getShiftAmountTy(N0.getValueType()))); 1904 AddToWorkList(SGN.getNode()); 1905 1906 // Add (N0 < 0) ? abs2 - 1 : 0; 1907 SDValue SRL = DAG.getNode(ISD::SRL, SDLoc(N), VT, SGN, 1908 DAG.getConstant(VT.getSizeInBits() - lg2, 1909 getShiftAmountTy(SGN.getValueType()))); 1910 SDValue ADD = DAG.getNode(ISD::ADD, SDLoc(N), VT, N0, SRL); 1911 AddToWorkList(SRL.getNode()); 1912 AddToWorkList(ADD.getNode()); // Divide by pow2 1913 SDValue SRA = DAG.getNode(ISD::SRA, SDLoc(N), VT, ADD, 1914 DAG.getConstant(lg2, getShiftAmountTy(ADD.getValueType()))); 1915 1916 // If we're dividing by a positive value, we're done. Otherwise, we must 1917 // negate the result. 1918 if (N1C->getAPIntValue().isNonNegative()) 1919 return SRA; 1920 1921 AddToWorkList(SRA.getNode()); 1922 return DAG.getNode(ISD::SUB, SDLoc(N), VT, 1923 DAG.getConstant(0, VT), SRA); 1924 } 1925 1926 // if integer divide is expensive and we satisfy the requirements, emit an 1927 // alternate sequence. 1928 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) { 1929 SDValue Op = BuildSDIV(N); 1930 if (Op.getNode()) return Op; 1931 } 1932 1933 // undef / X -> 0 1934 if (N0.getOpcode() == ISD::UNDEF) 1935 return DAG.getConstant(0, VT); 1936 // X / undef -> undef 1937 if (N1.getOpcode() == ISD::UNDEF) 1938 return N1; 1939 1940 return SDValue(); 1941} 1942 1943SDValue DAGCombiner::visitUDIV(SDNode *N) { 1944 SDValue N0 = N->getOperand(0); 1945 SDValue N1 = N->getOperand(1); 1946 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1947 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1948 EVT VT = N->getValueType(0); 1949 1950 // fold vector ops 1951 if (VT.isVector()) { 1952 SDValue FoldedVOp = SimplifyVBinOp(N); 1953 if (FoldedVOp.getNode()) return FoldedVOp; 1954 } 1955 1956 // fold (udiv c1, c2) -> c1/c2 1957 if (N0C && N1C && !N1C->isNullValue()) 1958 return DAG.FoldConstantArithmetic(ISD::UDIV, VT, N0C, N1C); 1959 // fold (udiv x, (1 << c)) -> x >>u c 1960 if (N1C && N1C->getAPIntValue().isPowerOf2()) 1961 return DAG.getNode(ISD::SRL, SDLoc(N), VT, N0, 1962 DAG.getConstant(N1C->getAPIntValue().logBase2(), 1963 getShiftAmountTy(N0.getValueType()))); 1964 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2 1965 if (N1.getOpcode() == ISD::SHL) { 1966 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1967 if (SHC->getAPIntValue().isPowerOf2()) { 1968 EVT ADDVT = N1.getOperand(1).getValueType(); 1969 SDValue Add = DAG.getNode(ISD::ADD, SDLoc(N), ADDVT, 1970 N1.getOperand(1), 1971 DAG.getConstant(SHC->getAPIntValue() 1972 .logBase2(), 1973 ADDVT)); 1974 AddToWorkList(Add.getNode()); 1975 return DAG.getNode(ISD::SRL, SDLoc(N), VT, N0, Add); 1976 } 1977 } 1978 } 1979 // fold (udiv x, c) -> alternate 1980 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) { 1981 SDValue Op = BuildUDIV(N); 1982 if (Op.getNode()) return Op; 1983 } 1984 1985 // undef / X -> 0 1986 if (N0.getOpcode() == ISD::UNDEF) 1987 return DAG.getConstant(0, VT); 1988 // X / undef -> undef 1989 if (N1.getOpcode() == ISD::UNDEF) 1990 return N1; 1991 1992 return SDValue(); 1993} 1994 1995SDValue DAGCombiner::visitSREM(SDNode *N) { 1996 SDValue N0 = N->getOperand(0); 1997 SDValue N1 = N->getOperand(1); 1998 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1999 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2000 EVT VT = N->getValueType(0); 2001 2002 // fold (srem c1, c2) -> c1%c2 2003 if (N0C && N1C && !N1C->isNullValue()) 2004 return DAG.FoldConstantArithmetic(ISD::SREM, VT, N0C, N1C); 2005 // If we know the sign bits of both operands are zero, strength reduce to a 2006 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15 2007 if (!VT.isVector()) { 2008 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 2009 return DAG.getNode(ISD::UREM, SDLoc(N), VT, N0, N1); 2010 } 2011 2012 // If X/C can be simplified by the division-by-constant logic, lower 2013 // X%C to the equivalent of X-X/C*C. 2014 if (N1C && !N1C->isNullValue()) { 2015 SDValue Div = DAG.getNode(ISD::SDIV, SDLoc(N), VT, N0, N1); 2016 AddToWorkList(Div.getNode()); 2017 SDValue OptimizedDiv = combine(Div.getNode()); 2018 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) { 2019 SDValue Mul = DAG.getNode(ISD::MUL, SDLoc(N), VT, 2020 OptimizedDiv, N1); 2021 SDValue Sub = DAG.getNode(ISD::SUB, SDLoc(N), VT, N0, Mul); 2022 AddToWorkList(Mul.getNode()); 2023 return Sub; 2024 } 2025 } 2026 2027 // undef % X -> 0 2028 if (N0.getOpcode() == ISD::UNDEF) 2029 return DAG.getConstant(0, VT); 2030 // X % undef -> undef 2031 if (N1.getOpcode() == ISD::UNDEF) 2032 return N1; 2033 2034 return SDValue(); 2035} 2036 2037SDValue DAGCombiner::visitUREM(SDNode *N) { 2038 SDValue N0 = N->getOperand(0); 2039 SDValue N1 = N->getOperand(1); 2040 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2041 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2042 EVT VT = N->getValueType(0); 2043 2044 // fold (urem c1, c2) -> c1%c2 2045 if (N0C && N1C && !N1C->isNullValue()) 2046 return DAG.FoldConstantArithmetic(ISD::UREM, VT, N0C, N1C); 2047 // fold (urem x, pow2) -> (and x, pow2-1) 2048 if (N1C && !N1C->isNullValue() && N1C->getAPIntValue().isPowerOf2()) 2049 return DAG.getNode(ISD::AND, SDLoc(N), VT, N0, 2050 DAG.getConstant(N1C->getAPIntValue()-1,VT)); 2051 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1)) 2052 if (N1.getOpcode() == ISD::SHL) { 2053 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 2054 if (SHC->getAPIntValue().isPowerOf2()) { 2055 SDValue Add = 2056 DAG.getNode(ISD::ADD, SDLoc(N), VT, N1, 2057 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), 2058 VT)); 2059 AddToWorkList(Add.getNode()); 2060 return DAG.getNode(ISD::AND, SDLoc(N), VT, N0, Add); 2061 } 2062 } 2063 } 2064 2065 // If X/C can be simplified by the division-by-constant logic, lower 2066 // X%C to the equivalent of X-X/C*C. 2067 if (N1C && !N1C->isNullValue()) { 2068 SDValue Div = DAG.getNode(ISD::UDIV, SDLoc(N), VT, N0, N1); 2069 AddToWorkList(Div.getNode()); 2070 SDValue OptimizedDiv = combine(Div.getNode()); 2071 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) { 2072 SDValue Mul = DAG.getNode(ISD::MUL, SDLoc(N), VT, 2073 OptimizedDiv, N1); 2074 SDValue Sub = DAG.getNode(ISD::SUB, SDLoc(N), VT, N0, Mul); 2075 AddToWorkList(Mul.getNode()); 2076 return Sub; 2077 } 2078 } 2079 2080 // undef % X -> 0 2081 if (N0.getOpcode() == ISD::UNDEF) 2082 return DAG.getConstant(0, VT); 2083 // X % undef -> undef 2084 if (N1.getOpcode() == ISD::UNDEF) 2085 return N1; 2086 2087 return SDValue(); 2088} 2089 2090SDValue DAGCombiner::visitMULHS(SDNode *N) { 2091 SDValue N0 = N->getOperand(0); 2092 SDValue N1 = N->getOperand(1); 2093 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2094 EVT VT = N->getValueType(0); 2095 SDLoc DL(N); 2096 2097 // fold (mulhs x, 0) -> 0 2098 if (N1C && N1C->isNullValue()) 2099 return N1; 2100 // fold (mulhs x, 1) -> (sra x, size(x)-1) 2101 if (N1C && N1C->getAPIntValue() == 1) 2102 return DAG.getNode(ISD::SRA, SDLoc(N), N0.getValueType(), N0, 2103 DAG.getConstant(N0.getValueType().getSizeInBits() - 1, 2104 getShiftAmountTy(N0.getValueType()))); 2105 // fold (mulhs x, undef) -> 0 2106 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 2107 return DAG.getConstant(0, VT); 2108 2109 // If the type twice as wide is legal, transform the mulhs to a wider multiply 2110 // plus a shift. 2111 if (VT.isSimple() && !VT.isVector()) { 2112 MVT Simple = VT.getSimpleVT(); 2113 unsigned SimpleSize = Simple.getSizeInBits(); 2114 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2); 2115 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { 2116 N0 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N0); 2117 N1 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N1); 2118 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1); 2119 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1, 2120 DAG.getConstant(SimpleSize, getShiftAmountTy(N1.getValueType()))); 2121 return DAG.getNode(ISD::TRUNCATE, DL, VT, N1); 2122 } 2123 } 2124 2125 return SDValue(); 2126} 2127 2128SDValue DAGCombiner::visitMULHU(SDNode *N) { 2129 SDValue N0 = N->getOperand(0); 2130 SDValue N1 = N->getOperand(1); 2131 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2132 EVT VT = N->getValueType(0); 2133 SDLoc DL(N); 2134 2135 // fold (mulhu x, 0) -> 0 2136 if (N1C && N1C->isNullValue()) 2137 return N1; 2138 // fold (mulhu x, 1) -> 0 2139 if (N1C && N1C->getAPIntValue() == 1) 2140 return DAG.getConstant(0, N0.getValueType()); 2141 // fold (mulhu x, undef) -> 0 2142 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 2143 return DAG.getConstant(0, VT); 2144 2145 // If the type twice as wide is legal, transform the mulhu to a wider multiply 2146 // plus a shift. 2147 if (VT.isSimple() && !VT.isVector()) { 2148 MVT Simple = VT.getSimpleVT(); 2149 unsigned SimpleSize = Simple.getSizeInBits(); 2150 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2); 2151 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { 2152 N0 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N0); 2153 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N1); 2154 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1); 2155 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1, 2156 DAG.getConstant(SimpleSize, getShiftAmountTy(N1.getValueType()))); 2157 return DAG.getNode(ISD::TRUNCATE, DL, VT, N1); 2158 } 2159 } 2160 2161 return SDValue(); 2162} 2163 2164/// SimplifyNodeWithTwoResults - Perform optimizations common to nodes that 2165/// compute two values. LoOp and HiOp give the opcodes for the two computations 2166/// that are being performed. Return true if a simplification was made. 2167/// 2168SDValue DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 2169 unsigned HiOp) { 2170 // If the high half is not needed, just compute the low half. 2171 bool HiExists = N->hasAnyUseOfValue(1); 2172 if (!HiExists && 2173 (!LegalOperations || 2174 TLI.isOperationLegal(LoOp, N->getValueType(0)))) { 2175 SDValue Res = DAG.getNode(LoOp, SDLoc(N), N->getValueType(0), 2176 N->op_begin(), N->getNumOperands()); 2177 return CombineTo(N, Res, Res); 2178 } 2179 2180 // If the low half is not needed, just compute the high half. 2181 bool LoExists = N->hasAnyUseOfValue(0); 2182 if (!LoExists && 2183 (!LegalOperations || 2184 TLI.isOperationLegal(HiOp, N->getValueType(1)))) { 2185 SDValue Res = DAG.getNode(HiOp, SDLoc(N), N->getValueType(1), 2186 N->op_begin(), N->getNumOperands()); 2187 return CombineTo(N, Res, Res); 2188 } 2189 2190 // If both halves are used, return as it is. 2191 if (LoExists && HiExists) 2192 return SDValue(); 2193 2194 // If the two computed results can be simplified separately, separate them. 2195 if (LoExists) { 2196 SDValue Lo = DAG.getNode(LoOp, SDLoc(N), N->getValueType(0), 2197 N->op_begin(), N->getNumOperands()); 2198 AddToWorkList(Lo.getNode()); 2199 SDValue LoOpt = combine(Lo.getNode()); 2200 if (LoOpt.getNode() && LoOpt.getNode() != Lo.getNode() && 2201 (!LegalOperations || 2202 TLI.isOperationLegal(LoOpt.getOpcode(), LoOpt.getValueType()))) 2203 return CombineTo(N, LoOpt, LoOpt); 2204 } 2205 2206 if (HiExists) { 2207 SDValue Hi = DAG.getNode(HiOp, SDLoc(N), N->getValueType(1), 2208 N->op_begin(), N->getNumOperands()); 2209 AddToWorkList(Hi.getNode()); 2210 SDValue HiOpt = combine(Hi.getNode()); 2211 if (HiOpt.getNode() && HiOpt != Hi && 2212 (!LegalOperations || 2213 TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType()))) 2214 return CombineTo(N, HiOpt, HiOpt); 2215 } 2216 2217 return SDValue(); 2218} 2219 2220SDValue DAGCombiner::visitSMUL_LOHI(SDNode *N) { 2221 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS); 2222 if (Res.getNode()) return Res; 2223 2224 EVT VT = N->getValueType(0); 2225 SDLoc DL(N); 2226 2227 // If the type twice as wide is legal, transform the mulhu to a wider multiply 2228 // plus a shift. 2229 if (VT.isSimple() && !VT.isVector()) { 2230 MVT Simple = VT.getSimpleVT(); 2231 unsigned SimpleSize = Simple.getSizeInBits(); 2232 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2); 2233 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { 2234 SDValue Lo = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(0)); 2235 SDValue Hi = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(1)); 2236 Lo = DAG.getNode(ISD::MUL, DL, NewVT, Lo, Hi); 2237 // Compute the high part as N1. 2238 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo, 2239 DAG.getConstant(SimpleSize, getShiftAmountTy(Lo.getValueType()))); 2240 Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi); 2241 // Compute the low part as N0. 2242 Lo = DAG.getNode(ISD::TRUNCATE, DL, VT, Lo); 2243 return CombineTo(N, Lo, Hi); 2244 } 2245 } 2246 2247 return SDValue(); 2248} 2249 2250SDValue DAGCombiner::visitUMUL_LOHI(SDNode *N) { 2251 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU); 2252 if (Res.getNode()) return Res; 2253 2254 EVT VT = N->getValueType(0); 2255 SDLoc DL(N); 2256 2257 // If the type twice as wide is legal, transform the mulhu to a wider multiply 2258 // plus a shift. 2259 if (VT.isSimple() && !VT.isVector()) { 2260 MVT Simple = VT.getSimpleVT(); 2261 unsigned SimpleSize = Simple.getSizeInBits(); 2262 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2); 2263 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { 2264 SDValue Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(0)); 2265 SDValue Hi = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(1)); 2266 Lo = DAG.getNode(ISD::MUL, DL, NewVT, Lo, Hi); 2267 // Compute the high part as N1. 2268 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo, 2269 DAG.getConstant(SimpleSize, getShiftAmountTy(Lo.getValueType()))); 2270 Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi); 2271 // Compute the low part as N0. 2272 Lo = DAG.getNode(ISD::TRUNCATE, DL, VT, Lo); 2273 return CombineTo(N, Lo, Hi); 2274 } 2275 } 2276 2277 return SDValue(); 2278} 2279 2280SDValue DAGCombiner::visitSMULO(SDNode *N) { 2281 // (smulo x, 2) -> (saddo x, x) 2282 if (ConstantSDNode *C2 = dyn_cast<ConstantSDNode>(N->getOperand(1))) 2283 if (C2->getAPIntValue() == 2) 2284 return DAG.getNode(ISD::SADDO, SDLoc(N), N->getVTList(), 2285 N->getOperand(0), N->getOperand(0)); 2286 2287 return SDValue(); 2288} 2289 2290SDValue DAGCombiner::visitUMULO(SDNode *N) { 2291 // (umulo x, 2) -> (uaddo x, x) 2292 if (ConstantSDNode *C2 = dyn_cast<ConstantSDNode>(N->getOperand(1))) 2293 if (C2->getAPIntValue() == 2) 2294 return DAG.getNode(ISD::UADDO, SDLoc(N), N->getVTList(), 2295 N->getOperand(0), N->getOperand(0)); 2296 2297 return SDValue(); 2298} 2299 2300SDValue DAGCombiner::visitSDIVREM(SDNode *N) { 2301 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM); 2302 if (Res.getNode()) return Res; 2303 2304 return SDValue(); 2305} 2306 2307SDValue DAGCombiner::visitUDIVREM(SDNode *N) { 2308 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM); 2309 if (Res.getNode()) return Res; 2310 2311 return SDValue(); 2312} 2313 2314/// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with 2315/// two operands of the same opcode, try to simplify it. 2316SDValue DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) { 2317 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1); 2318 EVT VT = N0.getValueType(); 2319 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!"); 2320 2321 // Bail early if none of these transforms apply. 2322 if (N0.getNode()->getNumOperands() == 0) return SDValue(); 2323 2324 // For each of OP in AND/OR/XOR: 2325 // fold (OP (zext x), (zext y)) -> (zext (OP x, y)) 2326 // fold (OP (sext x), (sext y)) -> (sext (OP x, y)) 2327 // fold (OP (aext x), (aext y)) -> (aext (OP x, y)) 2328 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y)) (if trunc isn't free) 2329 // 2330 // do not sink logical op inside of a vector extend, since it may combine 2331 // into a vsetcc. 2332 EVT Op0VT = N0.getOperand(0).getValueType(); 2333 if ((N0.getOpcode() == ISD::ZERO_EXTEND || 2334 N0.getOpcode() == ISD::SIGN_EXTEND || 2335 // Avoid infinite looping with PromoteIntBinOp. 2336 (N0.getOpcode() == ISD::ANY_EXTEND && 2337 (!LegalTypes || TLI.isTypeDesirableForOp(N->getOpcode(), Op0VT))) || 2338 (N0.getOpcode() == ISD::TRUNCATE && 2339 (!TLI.isZExtFree(VT, Op0VT) || 2340 !TLI.isTruncateFree(Op0VT, VT)) && 2341 TLI.isTypeLegal(Op0VT))) && 2342 !VT.isVector() && 2343 Op0VT == N1.getOperand(0).getValueType() && 2344 (!LegalOperations || TLI.isOperationLegal(N->getOpcode(), Op0VT))) { 2345 SDValue ORNode = DAG.getNode(N->getOpcode(), SDLoc(N0), 2346 N0.getOperand(0).getValueType(), 2347 N0.getOperand(0), N1.getOperand(0)); 2348 AddToWorkList(ORNode.getNode()); 2349 return DAG.getNode(N0.getOpcode(), SDLoc(N), VT, ORNode); 2350 } 2351 2352 // For each of OP in SHL/SRL/SRA/AND... 2353 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z) 2354 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z) 2355 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z) 2356 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL || 2357 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) && 2358 N0.getOperand(1) == N1.getOperand(1)) { 2359 SDValue ORNode = DAG.getNode(N->getOpcode(), SDLoc(N0), 2360 N0.getOperand(0).getValueType(), 2361 N0.getOperand(0), N1.getOperand(0)); 2362 AddToWorkList(ORNode.getNode()); 2363 return DAG.getNode(N0.getOpcode(), SDLoc(N), VT, 2364 ORNode, N0.getOperand(1)); 2365 } 2366 2367 // Simplify xor/and/or (bitcast(A), bitcast(B)) -> bitcast(op (A,B)) 2368 // Only perform this optimization after type legalization and before 2369 // LegalizeVectorOprs. LegalizeVectorOprs promotes vector operations by 2370 // adding bitcasts. For example (xor v4i32) is promoted to (v2i64), and 2371 // we don't want to undo this promotion. 2372 // We also handle SCALAR_TO_VECTOR because xor/or/and operations are cheaper 2373 // on scalars. 2374 if ((N0.getOpcode() == ISD::BITCAST || 2375 N0.getOpcode() == ISD::SCALAR_TO_VECTOR) && 2376 Level == AfterLegalizeTypes) { 2377 SDValue In0 = N0.getOperand(0); 2378 SDValue In1 = N1.getOperand(0); 2379 EVT In0Ty = In0.getValueType(); 2380 EVT In1Ty = In1.getValueType(); 2381 SDLoc DL(N); 2382 // If both incoming values are integers, and the original types are the 2383 // same. 2384 if (In0Ty.isInteger() && In1Ty.isInteger() && In0Ty == In1Ty) { 2385 SDValue Op = DAG.getNode(N->getOpcode(), DL, In0Ty, In0, In1); 2386 SDValue BC = DAG.getNode(N0.getOpcode(), DL, VT, Op); 2387 AddToWorkList(Op.getNode()); 2388 return BC; 2389 } 2390 } 2391 2392 // Xor/and/or are indifferent to the swizzle operation (shuffle of one value). 2393 // Simplify xor/and/or (shuff(A), shuff(B)) -> shuff(op (A,B)) 2394 // If both shuffles use the same mask, and both shuffle within a single 2395 // vector, then it is worthwhile to move the swizzle after the operation. 2396 // The type-legalizer generates this pattern when loading illegal 2397 // vector types from memory. In many cases this allows additional shuffle 2398 // optimizations. 2399 if (N0.getOpcode() == ISD::VECTOR_SHUFFLE && Level < AfterLegalizeDAG && 2400 N0.getOperand(1).getOpcode() == ISD::UNDEF && 2401 N1.getOperand(1).getOpcode() == ISD::UNDEF) { 2402 ShuffleVectorSDNode *SVN0 = cast<ShuffleVectorSDNode>(N0); 2403 ShuffleVectorSDNode *SVN1 = cast<ShuffleVectorSDNode>(N1); 2404 2405 assert(N0.getOperand(0).getValueType() == N1.getOperand(1).getValueType() && 2406 "Inputs to shuffles are not the same type"); 2407 2408 unsigned NumElts = VT.getVectorNumElements(); 2409 2410 // Check that both shuffles use the same mask. The masks are known to be of 2411 // the same length because the result vector type is the same. 2412 bool SameMask = true; 2413 for (unsigned i = 0; i != NumElts; ++i) { 2414 int Idx0 = SVN0->getMaskElt(i); 2415 int Idx1 = SVN1->getMaskElt(i); 2416 if (Idx0 != Idx1) { 2417 SameMask = false; 2418 break; 2419 } 2420 } 2421 2422 if (SameMask) { 2423 SDValue Op = DAG.getNode(N->getOpcode(), SDLoc(N), VT, 2424 N0.getOperand(0), N1.getOperand(0)); 2425 AddToWorkList(Op.getNode()); 2426 return DAG.getVectorShuffle(VT, SDLoc(N), Op, 2427 DAG.getUNDEF(VT), &SVN0->getMask()[0]); 2428 } 2429 } 2430 2431 return SDValue(); 2432} 2433 2434SDValue DAGCombiner::visitAND(SDNode *N) { 2435 SDValue N0 = N->getOperand(0); 2436 SDValue N1 = N->getOperand(1); 2437 SDValue LL, LR, RL, RR, CC0, CC1; 2438 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2439 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2440 EVT VT = N1.getValueType(); 2441 unsigned BitWidth = VT.getScalarType().getSizeInBits(); 2442 2443 // fold vector ops 2444 if (VT.isVector()) { 2445 SDValue FoldedVOp = SimplifyVBinOp(N); 2446 if (FoldedVOp.getNode()) return FoldedVOp; 2447 2448 // fold (and x, 0) -> 0, vector edition 2449 if (ISD::isBuildVectorAllZeros(N0.getNode())) 2450 return N0; 2451 if (ISD::isBuildVectorAllZeros(N1.getNode())) 2452 return N1; 2453 2454 // fold (and x, -1) -> x, vector edition 2455 if (ISD::isBuildVectorAllOnes(N0.getNode())) 2456 return N1; 2457 if (ISD::isBuildVectorAllOnes(N1.getNode())) 2458 return N0; 2459 } 2460 2461 // fold (and x, undef) -> 0 2462 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 2463 return DAG.getConstant(0, VT); 2464 // fold (and c1, c2) -> c1&c2 2465 if (N0C && N1C) 2466 return DAG.FoldConstantArithmetic(ISD::AND, VT, N0C, N1C); 2467 // canonicalize constant to RHS 2468 if (N0C && !N1C) 2469 return DAG.getNode(ISD::AND, SDLoc(N), VT, N1, N0); 2470 // fold (and x, -1) -> x 2471 if (N1C && N1C->isAllOnesValue()) 2472 return N0; 2473 // if (and x, c) is known to be zero, return 0 2474 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0), 2475 APInt::getAllOnesValue(BitWidth))) 2476 return DAG.getConstant(0, VT); 2477 // reassociate and 2478 SDValue RAND = ReassociateOps(ISD::AND, SDLoc(N), N0, N1); 2479 if (RAND.getNode() != 0) 2480 return RAND; 2481 // fold (and (or x, C), D) -> D if (C & D) == D 2482 if (N1C && N0.getOpcode() == ISD::OR) 2483 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 2484 if ((ORI->getAPIntValue() & N1C->getAPIntValue()) == N1C->getAPIntValue()) 2485 return N1; 2486 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits. 2487 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 2488 SDValue N0Op0 = N0.getOperand(0); 2489 APInt Mask = ~N1C->getAPIntValue(); 2490 Mask = Mask.trunc(N0Op0.getValueSizeInBits()); 2491 if (DAG.MaskedValueIsZero(N0Op0, Mask)) { 2492 SDValue Zext = DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), 2493 N0.getValueType(), N0Op0); 2494 2495 // Replace uses of the AND with uses of the Zero extend node. 2496 CombineTo(N, Zext); 2497 2498 // We actually want to replace all uses of the any_extend with the 2499 // zero_extend, to avoid duplicating things. This will later cause this 2500 // AND to be folded. 2501 CombineTo(N0.getNode(), Zext); 2502 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2503 } 2504 } 2505 // similarly fold (and (X (load ([non_ext|any_ext|zero_ext] V))), c) -> 2506 // (X (load ([non_ext|zero_ext] V))) if 'and' only clears top bits which must 2507 // already be zero by virtue of the width of the base type of the load. 2508 // 2509 // the 'X' node here can either be nothing or an extract_vector_elt to catch 2510 // more cases. 2511 if ((N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT && 2512 N0.getOperand(0).getOpcode() == ISD::LOAD) || 2513 N0.getOpcode() == ISD::LOAD) { 2514 LoadSDNode *Load = cast<LoadSDNode>( (N0.getOpcode() == ISD::LOAD) ? 2515 N0 : N0.getOperand(0) ); 2516 2517 // Get the constant (if applicable) the zero'th operand is being ANDed with. 2518 // This can be a pure constant or a vector splat, in which case we treat the 2519 // vector as a scalar and use the splat value. 2520 APInt Constant = APInt::getNullValue(1); 2521 if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(N1)) { 2522 Constant = C->getAPIntValue(); 2523 } else if (BuildVectorSDNode *Vector = dyn_cast<BuildVectorSDNode>(N1)) { 2524 APInt SplatValue, SplatUndef; 2525 unsigned SplatBitSize; 2526 bool HasAnyUndefs; 2527 bool IsSplat = Vector->isConstantSplat(SplatValue, SplatUndef, 2528 SplatBitSize, HasAnyUndefs); 2529 if (IsSplat) { 2530 // Undef bits can contribute to a possible optimisation if set, so 2531 // set them. 2532 SplatValue |= SplatUndef; 2533 2534 // The splat value may be something like "0x00FFFFFF", which means 0 for 2535 // the first vector value and FF for the rest, repeating. We need a mask 2536 // that will apply equally to all members of the vector, so AND all the 2537 // lanes of the constant together. 2538 EVT VT = Vector->getValueType(0); 2539 unsigned BitWidth = VT.getVectorElementType().getSizeInBits(); 2540 2541 // If the splat value has been compressed to a bitlength lower 2542 // than the size of the vector lane, we need to re-expand it to 2543 // the lane size. 2544 if (BitWidth > SplatBitSize) 2545 for (SplatValue = SplatValue.zextOrTrunc(BitWidth); 2546 SplatBitSize < BitWidth; 2547 SplatBitSize = SplatBitSize * 2) 2548 SplatValue |= SplatValue.shl(SplatBitSize); 2549 2550 Constant = APInt::getAllOnesValue(BitWidth); 2551 for (unsigned i = 0, n = SplatBitSize/BitWidth; i < n; ++i) 2552 Constant &= SplatValue.lshr(i*BitWidth).zextOrTrunc(BitWidth); 2553 } 2554 } 2555 2556 // If we want to change an EXTLOAD to a ZEXTLOAD, ensure a ZEXTLOAD is 2557 // actually legal and isn't going to get expanded, else this is a false 2558 // optimisation. 2559 bool CanZextLoadProfitably = TLI.isLoadExtLegal(ISD::ZEXTLOAD, 2560 Load->getMemoryVT()); 2561 2562 // Resize the constant to the same size as the original memory access before 2563 // extension. If it is still the AllOnesValue then this AND is completely 2564 // unneeded. 2565 Constant = 2566 Constant.zextOrTrunc(Load->getMemoryVT().getScalarType().getSizeInBits()); 2567 2568 bool B; 2569 switch (Load->getExtensionType()) { 2570 default: B = false; break; 2571 case ISD::EXTLOAD: B = CanZextLoadProfitably; break; 2572 case ISD::ZEXTLOAD: 2573 case ISD::NON_EXTLOAD: B = true; break; 2574 } 2575 2576 if (B && Constant.isAllOnesValue()) { 2577 // If the load type was an EXTLOAD, convert to ZEXTLOAD in order to 2578 // preserve semantics once we get rid of the AND. 2579 SDValue NewLoad(Load, 0); 2580 if (Load->getExtensionType() == ISD::EXTLOAD) { 2581 NewLoad = DAG.getLoad(Load->getAddressingMode(), ISD::ZEXTLOAD, 2582 Load->getValueType(0), SDLoc(Load), 2583 Load->getChain(), Load->getBasePtr(), 2584 Load->getOffset(), Load->getMemoryVT(), 2585 Load->getMemOperand()); 2586 // Replace uses of the EXTLOAD with the new ZEXTLOAD. 2587 if (Load->getNumValues() == 3) { 2588 // PRE/POST_INC loads have 3 values. 2589 SDValue To[] = { NewLoad.getValue(0), NewLoad.getValue(1), 2590 NewLoad.getValue(2) }; 2591 CombineTo(Load, To, 3, true); 2592 } else { 2593 CombineTo(Load, NewLoad.getValue(0), NewLoad.getValue(1)); 2594 } 2595 } 2596 2597 // Fold the AND away, taking care not to fold to the old load node if we 2598 // replaced it. 2599 CombineTo(N, (N0.getNode() == Load) ? NewLoad : N0); 2600 2601 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2602 } 2603 } 2604 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y)) 2605 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 2606 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 2607 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 2608 2609 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 2610 LL.getValueType().isInteger()) { 2611 // fold (and (seteq X, 0), (seteq Y, 0)) -> (seteq (or X, Y), 0) 2612 if (cast<ConstantSDNode>(LR)->isNullValue() && Op1 == ISD::SETEQ) { 2613 SDValue ORNode = DAG.getNode(ISD::OR, SDLoc(N0), 2614 LR.getValueType(), LL, RL); 2615 AddToWorkList(ORNode.getNode()); 2616 return DAG.getSetCC(SDLoc(N), VT, ORNode, LR, Op1); 2617 } 2618 // fold (and (seteq X, -1), (seteq Y, -1)) -> (seteq (and X, Y), -1) 2619 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) { 2620 SDValue ANDNode = DAG.getNode(ISD::AND, SDLoc(N0), 2621 LR.getValueType(), LL, RL); 2622 AddToWorkList(ANDNode.getNode()); 2623 return DAG.getSetCC(SDLoc(N), VT, ANDNode, LR, Op1); 2624 } 2625 // fold (and (setgt X, -1), (setgt Y, -1)) -> (setgt (or X, Y), -1) 2626 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) { 2627 SDValue ORNode = DAG.getNode(ISD::OR, SDLoc(N0), 2628 LR.getValueType(), LL, RL); 2629 AddToWorkList(ORNode.getNode()); 2630 return DAG.getSetCC(SDLoc(N), VT, ORNode, LR, Op1); 2631 } 2632 } 2633 // canonicalize equivalent to ll == rl 2634 if (LL == RR && LR == RL) { 2635 Op1 = ISD::getSetCCSwappedOperands(Op1); 2636 std::swap(RL, RR); 2637 } 2638 if (LL == RL && LR == RR) { 2639 bool isInteger = LL.getValueType().isInteger(); 2640 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger); 2641 if (Result != ISD::SETCC_INVALID && 2642 (!LegalOperations || 2643 (TLI.isCondCodeLegal(Result, LL.getSimpleValueType()) && 2644 TLI.isOperationLegal(ISD::SETCC, 2645 getSetCCResultType(N0.getSimpleValueType()))))) 2646 return DAG.getSetCC(SDLoc(N), N0.getValueType(), 2647 LL, LR, Result); 2648 } 2649 } 2650 2651 // Simplify: (and (op x...), (op y...)) -> (op (and x, y)) 2652 if (N0.getOpcode() == N1.getOpcode()) { 2653 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 2654 if (Tmp.getNode()) return Tmp; 2655 } 2656 2657 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1) 2658 // fold (and (sra)) -> (and (srl)) when possible. 2659 if (!VT.isVector() && 2660 SimplifyDemandedBits(SDValue(N, 0))) 2661 return SDValue(N, 0); 2662 2663 // fold (zext_inreg (extload x)) -> (zextload x) 2664 if (ISD::isEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode())) { 2665 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2666 EVT MemVT = LN0->getMemoryVT(); 2667 // If we zero all the possible extended bits, then we can turn this into 2668 // a zextload if we are running before legalize or the operation is legal. 2669 unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits(); 2670 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 2671 BitWidth - MemVT.getScalarType().getSizeInBits())) && 2672 ((!LegalOperations && !LN0->isVolatile()) || 2673 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) { 2674 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(N0), VT, 2675 LN0->getChain(), LN0->getBasePtr(), 2676 LN0->getPointerInfo(), MemVT, 2677 LN0->isVolatile(), LN0->isNonTemporal(), 2678 LN0->getAlignment()); 2679 AddToWorkList(N); 2680 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 2681 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2682 } 2683 } 2684 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use 2685 if (ISD::isSEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 2686 N0.hasOneUse()) { 2687 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2688 EVT MemVT = LN0->getMemoryVT(); 2689 // If we zero all the possible extended bits, then we can turn this into 2690 // a zextload if we are running before legalize or the operation is legal. 2691 unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits(); 2692 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 2693 BitWidth - MemVT.getScalarType().getSizeInBits())) && 2694 ((!LegalOperations && !LN0->isVolatile()) || 2695 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) { 2696 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(N0), VT, 2697 LN0->getChain(), 2698 LN0->getBasePtr(), LN0->getPointerInfo(), 2699 MemVT, 2700 LN0->isVolatile(), LN0->isNonTemporal(), 2701 LN0->getAlignment()); 2702 AddToWorkList(N); 2703 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 2704 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2705 } 2706 } 2707 2708 // fold (and (load x), 255) -> (zextload x, i8) 2709 // fold (and (extload x, i16), 255) -> (zextload x, i8) 2710 // fold (and (any_ext (extload x, i16)), 255) -> (zextload x, i8) 2711 if (N1C && (N0.getOpcode() == ISD::LOAD || 2712 (N0.getOpcode() == ISD::ANY_EXTEND && 2713 N0.getOperand(0).getOpcode() == ISD::LOAD))) { 2714 bool HasAnyExt = N0.getOpcode() == ISD::ANY_EXTEND; 2715 LoadSDNode *LN0 = HasAnyExt 2716 ? cast<LoadSDNode>(N0.getOperand(0)) 2717 : cast<LoadSDNode>(N0); 2718 if (LN0->getExtensionType() != ISD::SEXTLOAD && 2719 LN0->isUnindexed() && N0.hasOneUse() && LN0->hasOneUse()) { 2720 uint32_t ActiveBits = N1C->getAPIntValue().getActiveBits(); 2721 if (ActiveBits > 0 && APIntOps::isMask(ActiveBits, N1C->getAPIntValue())){ 2722 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), ActiveBits); 2723 EVT LoadedVT = LN0->getMemoryVT(); 2724 2725 if (ExtVT == LoadedVT && 2726 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) { 2727 EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT; 2728 2729 SDValue NewLoad = 2730 DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(LN0), LoadResultTy, 2731 LN0->getChain(), LN0->getBasePtr(), 2732 LN0->getPointerInfo(), 2733 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(), 2734 LN0->getAlignment()); 2735 AddToWorkList(N); 2736 CombineTo(LN0, NewLoad, NewLoad.getValue(1)); 2737 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2738 } 2739 2740 // Do not change the width of a volatile load. 2741 // Do not generate loads of non-round integer types since these can 2742 // be expensive (and would be wrong if the type is not byte sized). 2743 if (!LN0->isVolatile() && LoadedVT.bitsGT(ExtVT) && ExtVT.isRound() && 2744 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) { 2745 EVT PtrType = LN0->getOperand(1).getValueType(); 2746 2747 unsigned Alignment = LN0->getAlignment(); 2748 SDValue NewPtr = LN0->getBasePtr(); 2749 2750 // For big endian targets, we need to add an offset to the pointer 2751 // to load the correct bytes. For little endian systems, we merely 2752 // need to read fewer bytes from the same pointer. 2753 if (TLI.isBigEndian()) { 2754 unsigned LVTStoreBytes = LoadedVT.getStoreSize(); 2755 unsigned EVTStoreBytes = ExtVT.getStoreSize(); 2756 unsigned PtrOff = LVTStoreBytes - EVTStoreBytes; 2757 NewPtr = DAG.getNode(ISD::ADD, SDLoc(LN0), PtrType, 2758 NewPtr, DAG.getConstant(PtrOff, PtrType)); 2759 Alignment = MinAlign(Alignment, PtrOff); 2760 } 2761 2762 AddToWorkList(NewPtr.getNode()); 2763 2764 EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT; 2765 SDValue Load = 2766 DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(LN0), LoadResultTy, 2767 LN0->getChain(), NewPtr, 2768 LN0->getPointerInfo(), 2769 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(), 2770 Alignment); 2771 AddToWorkList(N); 2772 CombineTo(LN0, Load, Load.getValue(1)); 2773 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2774 } 2775 } 2776 } 2777 } 2778 2779 if (N0.getOpcode() == ISD::ADD && N1.getOpcode() == ISD::SRL && 2780 VT.getSizeInBits() <= 64) { 2781 if (ConstantSDNode *ADDI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 2782 APInt ADDC = ADDI->getAPIntValue(); 2783 if (!TLI.isLegalAddImmediate(ADDC.getSExtValue())) { 2784 // Look for (and (add x, c1), (lshr y, c2)). If C1 wasn't a legal 2785 // immediate for an add, but it is legal if its top c2 bits are set, 2786 // transform the ADD so the immediate doesn't need to be materialized 2787 // in a register. 2788 if (ConstantSDNode *SRLI = dyn_cast<ConstantSDNode>(N1.getOperand(1))) { 2789 APInt Mask = APInt::getHighBitsSet(VT.getSizeInBits(), 2790 SRLI->getZExtValue()); 2791 if (DAG.MaskedValueIsZero(N0.getOperand(1), Mask)) { 2792 ADDC |= Mask; 2793 if (TLI.isLegalAddImmediate(ADDC.getSExtValue())) { 2794 SDValue NewAdd = 2795 DAG.getNode(ISD::ADD, SDLoc(N0), VT, 2796 N0.getOperand(0), DAG.getConstant(ADDC, VT)); 2797 CombineTo(N0.getNode(), NewAdd); 2798 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2799 } 2800 } 2801 } 2802 } 2803 } 2804 } 2805 2806 return SDValue(); 2807} 2808 2809/// MatchBSwapHWord - Match (a >> 8) | (a << 8) as (bswap a) >> 16 2810/// 2811SDValue DAGCombiner::MatchBSwapHWordLow(SDNode *N, SDValue N0, SDValue N1, 2812 bool DemandHighBits) { 2813 if (!LegalOperations) 2814 return SDValue(); 2815 2816 EVT VT = N->getValueType(0); 2817 if (VT != MVT::i64 && VT != MVT::i32 && VT != MVT::i16) 2818 return SDValue(); 2819 if (!TLI.isOperationLegal(ISD::BSWAP, VT)) 2820 return SDValue(); 2821 2822 // Recognize (and (shl a, 8), 0xff), (and (srl a, 8), 0xff00) 2823 bool LookPassAnd0 = false; 2824 bool LookPassAnd1 = false; 2825 if (N0.getOpcode() == ISD::AND && N0.getOperand(0).getOpcode() == ISD::SRL) 2826 std::swap(N0, N1); 2827 if (N1.getOpcode() == ISD::AND && N1.getOperand(0).getOpcode() == ISD::SHL) 2828 std::swap(N0, N1); 2829 if (N0.getOpcode() == ISD::AND) { 2830 if (!N0.getNode()->hasOneUse()) 2831 return SDValue(); 2832 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2833 if (!N01C || N01C->getZExtValue() != 0xFF00) 2834 return SDValue(); 2835 N0 = N0.getOperand(0); 2836 LookPassAnd0 = true; 2837 } 2838 2839 if (N1.getOpcode() == ISD::AND) { 2840 if (!N1.getNode()->hasOneUse()) 2841 return SDValue(); 2842 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1)); 2843 if (!N11C || N11C->getZExtValue() != 0xFF) 2844 return SDValue(); 2845 N1 = N1.getOperand(0); 2846 LookPassAnd1 = true; 2847 } 2848 2849 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL) 2850 std::swap(N0, N1); 2851 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL) 2852 return SDValue(); 2853 if (!N0.getNode()->hasOneUse() || 2854 !N1.getNode()->hasOneUse()) 2855 return SDValue(); 2856 2857 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2858 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1)); 2859 if (!N01C || !N11C) 2860 return SDValue(); 2861 if (N01C->getZExtValue() != 8 || N11C->getZExtValue() != 8) 2862 return SDValue(); 2863 2864 // Look for (shl (and a, 0xff), 8), (srl (and a, 0xff00), 8) 2865 SDValue N00 = N0->getOperand(0); 2866 if (!LookPassAnd0 && N00.getOpcode() == ISD::AND) { 2867 if (!N00.getNode()->hasOneUse()) 2868 return SDValue(); 2869 ConstantSDNode *N001C = dyn_cast<ConstantSDNode>(N00.getOperand(1)); 2870 if (!N001C || N001C->getZExtValue() != 0xFF) 2871 return SDValue(); 2872 N00 = N00.getOperand(0); 2873 LookPassAnd0 = true; 2874 } 2875 2876 SDValue N10 = N1->getOperand(0); 2877 if (!LookPassAnd1 && N10.getOpcode() == ISD::AND) { 2878 if (!N10.getNode()->hasOneUse()) 2879 return SDValue(); 2880 ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N10.getOperand(1)); 2881 if (!N101C || N101C->getZExtValue() != 0xFF00) 2882 return SDValue(); 2883 N10 = N10.getOperand(0); 2884 LookPassAnd1 = true; 2885 } 2886 2887 if (N00 != N10) 2888 return SDValue(); 2889 2890 // Make sure everything beyond the low halfword is zero since the SRL 16 2891 // will clear the top bits. 2892 unsigned OpSizeInBits = VT.getSizeInBits(); 2893 if (DemandHighBits && OpSizeInBits > 16 && 2894 (!LookPassAnd0 || !LookPassAnd1) && 2895 !DAG.MaskedValueIsZero(N10, APInt::getHighBitsSet(OpSizeInBits, 16))) 2896 return SDValue(); 2897 2898 SDValue Res = DAG.getNode(ISD::BSWAP, SDLoc(N), VT, N00); 2899 if (OpSizeInBits > 16) 2900 Res = DAG.getNode(ISD::SRL, SDLoc(N), VT, Res, 2901 DAG.getConstant(OpSizeInBits-16, getShiftAmountTy(VT))); 2902 return Res; 2903} 2904 2905/// isBSwapHWordElement - Return true if the specified node is an element 2906/// that makes up a 32-bit packed halfword byteswap. i.e. 2907/// ((x&0xff)<<8)|((x&0xff00)>>8)|((x&0x00ff0000)<<8)|((x&0xff000000)>>8) 2908static bool isBSwapHWordElement(SDValue N, SmallVector<SDNode*,4> &Parts) { 2909 if (!N.getNode()->hasOneUse()) 2910 return false; 2911 2912 unsigned Opc = N.getOpcode(); 2913 if (Opc != ISD::AND && Opc != ISD::SHL && Opc != ISD::SRL) 2914 return false; 2915 2916 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N.getOperand(1)); 2917 if (!N1C) 2918 return false; 2919 2920 unsigned Num; 2921 switch (N1C->getZExtValue()) { 2922 default: 2923 return false; 2924 case 0xFF: Num = 0; break; 2925 case 0xFF00: Num = 1; break; 2926 case 0xFF0000: Num = 2; break; 2927 case 0xFF000000: Num = 3; break; 2928 } 2929 2930 // Look for (x & 0xff) << 8 as well as ((x << 8) & 0xff00). 2931 SDValue N0 = N.getOperand(0); 2932 if (Opc == ISD::AND) { 2933 if (Num == 0 || Num == 2) { 2934 // (x >> 8) & 0xff 2935 // (x >> 8) & 0xff0000 2936 if (N0.getOpcode() != ISD::SRL) 2937 return false; 2938 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2939 if (!C || C->getZExtValue() != 8) 2940 return false; 2941 } else { 2942 // (x << 8) & 0xff00 2943 // (x << 8) & 0xff000000 2944 if (N0.getOpcode() != ISD::SHL) 2945 return false; 2946 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2947 if (!C || C->getZExtValue() != 8) 2948 return false; 2949 } 2950 } else if (Opc == ISD::SHL) { 2951 // (x & 0xff) << 8 2952 // (x & 0xff0000) << 8 2953 if (Num != 0 && Num != 2) 2954 return false; 2955 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N.getOperand(1)); 2956 if (!C || C->getZExtValue() != 8) 2957 return false; 2958 } else { // Opc == ISD::SRL 2959 // (x & 0xff00) >> 8 2960 // (x & 0xff000000) >> 8 2961 if (Num != 1 && Num != 3) 2962 return false; 2963 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N.getOperand(1)); 2964 if (!C || C->getZExtValue() != 8) 2965 return false; 2966 } 2967 2968 if (Parts[Num]) 2969 return false; 2970 2971 Parts[Num] = N0.getOperand(0).getNode(); 2972 return true; 2973} 2974 2975/// MatchBSwapHWord - Match a 32-bit packed halfword bswap. That is 2976/// ((x&0xff)<<8)|((x&0xff00)>>8)|((x&0x00ff0000)<<8)|((x&0xff000000)>>8) 2977/// => (rotl (bswap x), 16) 2978SDValue DAGCombiner::MatchBSwapHWord(SDNode *N, SDValue N0, SDValue N1) { 2979 if (!LegalOperations) 2980 return SDValue(); 2981 2982 EVT VT = N->getValueType(0); 2983 if (VT != MVT::i32) 2984 return SDValue(); 2985 if (!TLI.isOperationLegal(ISD::BSWAP, VT)) 2986 return SDValue(); 2987 2988 SmallVector<SDNode*,4> Parts(4, (SDNode*)0); 2989 // Look for either 2990 // (or (or (and), (and)), (or (and), (and))) 2991 // (or (or (or (and), (and)), (and)), (and)) 2992 if (N0.getOpcode() != ISD::OR) 2993 return SDValue(); 2994 SDValue N00 = N0.getOperand(0); 2995 SDValue N01 = N0.getOperand(1); 2996 2997 if (N1.getOpcode() == ISD::OR && 2998 N00.getNumOperands() == 2 && N01.getNumOperands() == 2) { 2999 // (or (or (and), (and)), (or (and), (and))) 3000 SDValue N000 = N00.getOperand(0); 3001 if (!isBSwapHWordElement(N000, Parts)) 3002 return SDValue(); 3003 3004 SDValue N001 = N00.getOperand(1); 3005 if (!isBSwapHWordElement(N001, Parts)) 3006 return SDValue(); 3007 SDValue N010 = N01.getOperand(0); 3008 if (!isBSwapHWordElement(N010, Parts)) 3009 return SDValue(); 3010 SDValue N011 = N01.getOperand(1); 3011 if (!isBSwapHWordElement(N011, Parts)) 3012 return SDValue(); 3013 } else { 3014 // (or (or (or (and), (and)), (and)), (and)) 3015 if (!isBSwapHWordElement(N1, Parts)) 3016 return SDValue(); 3017 if (!isBSwapHWordElement(N01, Parts)) 3018 return SDValue(); 3019 if (N00.getOpcode() != ISD::OR) 3020 return SDValue(); 3021 SDValue N000 = N00.getOperand(0); 3022 if (!isBSwapHWordElement(N000, Parts)) 3023 return SDValue(); 3024 SDValue N001 = N00.getOperand(1); 3025 if (!isBSwapHWordElement(N001, Parts)) 3026 return SDValue(); 3027 } 3028 3029 // Make sure the parts are all coming from the same node. 3030 if (Parts[0] != Parts[1] || Parts[0] != Parts[2] || Parts[0] != Parts[3]) 3031 return SDValue(); 3032 3033 SDValue BSwap = DAG.getNode(ISD::BSWAP, SDLoc(N), VT, 3034 SDValue(Parts[0],0)); 3035 3036 // Result of the bswap should be rotated by 16. If it's not legal, than 3037 // do (x << 16) | (x >> 16). 3038 SDValue ShAmt = DAG.getConstant(16, getShiftAmountTy(VT)); 3039 if (TLI.isOperationLegalOrCustom(ISD::ROTL, VT)) 3040 return DAG.getNode(ISD::ROTL, SDLoc(N), VT, BSwap, ShAmt); 3041 if (TLI.isOperationLegalOrCustom(ISD::ROTR, VT)) 3042 return DAG.getNode(ISD::ROTR, SDLoc(N), VT, BSwap, ShAmt); 3043 return DAG.getNode(ISD::OR, SDLoc(N), VT, 3044 DAG.getNode(ISD::SHL, SDLoc(N), VT, BSwap, ShAmt), 3045 DAG.getNode(ISD::SRL, SDLoc(N), VT, BSwap, ShAmt)); 3046} 3047 3048SDValue DAGCombiner::visitOR(SDNode *N) { 3049 SDValue N0 = N->getOperand(0); 3050 SDValue N1 = N->getOperand(1); 3051 SDValue LL, LR, RL, RR, CC0, CC1; 3052 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3053 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3054 EVT VT = N1.getValueType(); 3055 3056 // fold vector ops 3057 if (VT.isVector()) { 3058 SDValue FoldedVOp = SimplifyVBinOp(N); 3059 if (FoldedVOp.getNode()) return FoldedVOp; 3060 3061 // fold (or x, 0) -> x, vector edition 3062 if (ISD::isBuildVectorAllZeros(N0.getNode())) 3063 return N1; 3064 if (ISD::isBuildVectorAllZeros(N1.getNode())) 3065 return N0; 3066 3067 // fold (or x, -1) -> -1, vector edition 3068 if (ISD::isBuildVectorAllOnes(N0.getNode())) 3069 return N0; 3070 if (ISD::isBuildVectorAllOnes(N1.getNode())) 3071 return N1; 3072 } 3073 3074 // fold (or x, undef) -> -1 3075 if (!LegalOperations && 3076 (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)) { 3077 EVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT; 3078 return DAG.getConstant(APInt::getAllOnesValue(EltVT.getSizeInBits()), VT); 3079 } 3080 // fold (or c1, c2) -> c1|c2 3081 if (N0C && N1C) 3082 return DAG.FoldConstantArithmetic(ISD::OR, VT, N0C, N1C); 3083 // canonicalize constant to RHS 3084 if (N0C && !N1C) 3085 return DAG.getNode(ISD::OR, SDLoc(N), VT, N1, N0); 3086 // fold (or x, 0) -> x 3087 if (N1C && N1C->isNullValue()) 3088 return N0; 3089 // fold (or x, -1) -> -1 3090 if (N1C && N1C->isAllOnesValue()) 3091 return N1; 3092 // fold (or x, c) -> c iff (x & ~c) == 0 3093 if (N1C && DAG.MaskedValueIsZero(N0, ~N1C->getAPIntValue())) 3094 return N1; 3095 3096 // Recognize halfword bswaps as (bswap + rotl 16) or (bswap + shl 16) 3097 SDValue BSwap = MatchBSwapHWord(N, N0, N1); 3098 if (BSwap.getNode() != 0) 3099 return BSwap; 3100 BSwap = MatchBSwapHWordLow(N, N0, N1); 3101 if (BSwap.getNode() != 0) 3102 return BSwap; 3103 3104 // reassociate or 3105 SDValue ROR = ReassociateOps(ISD::OR, SDLoc(N), N0, N1); 3106 if (ROR.getNode() != 0) 3107 return ROR; 3108 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2) 3109 // iff (c1 & c2) == 0. 3110 if (N1C && N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() && 3111 isa<ConstantSDNode>(N0.getOperand(1))) { 3112 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1)); 3113 if ((C1->getAPIntValue() & N1C->getAPIntValue()) != 0) 3114 return DAG.getNode(ISD::AND, SDLoc(N), VT, 3115 DAG.getNode(ISD::OR, SDLoc(N0), VT, 3116 N0.getOperand(0), N1), 3117 DAG.FoldConstantArithmetic(ISD::OR, VT, N1C, C1)); 3118 } 3119 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y)) 3120 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 3121 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 3122 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 3123 3124 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 3125 LL.getValueType().isInteger()) { 3126 // fold (or (setne X, 0), (setne Y, 0)) -> (setne (or X, Y), 0) 3127 // fold (or (setlt X, 0), (setlt Y, 0)) -> (setne (or X, Y), 0) 3128 if (cast<ConstantSDNode>(LR)->isNullValue() && 3129 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) { 3130 SDValue ORNode = DAG.getNode(ISD::OR, SDLoc(LR), 3131 LR.getValueType(), LL, RL); 3132 AddToWorkList(ORNode.getNode()); 3133 return DAG.getSetCC(SDLoc(N), VT, ORNode, LR, Op1); 3134 } 3135 // fold (or (setne X, -1), (setne Y, -1)) -> (setne (and X, Y), -1) 3136 // fold (or (setgt X, -1), (setgt Y -1)) -> (setgt (and X, Y), -1) 3137 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && 3138 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) { 3139 SDValue ANDNode = DAG.getNode(ISD::AND, SDLoc(LR), 3140 LR.getValueType(), LL, RL); 3141 AddToWorkList(ANDNode.getNode()); 3142 return DAG.getSetCC(SDLoc(N), VT, ANDNode, LR, Op1); 3143 } 3144 } 3145 // canonicalize equivalent to ll == rl 3146 if (LL == RR && LR == RL) { 3147 Op1 = ISD::getSetCCSwappedOperands(Op1); 3148 std::swap(RL, RR); 3149 } 3150 if (LL == RL && LR == RR) { 3151 bool isInteger = LL.getValueType().isInteger(); 3152 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger); 3153 if (Result != ISD::SETCC_INVALID && 3154 (!LegalOperations || 3155 (TLI.isCondCodeLegal(Result, LL.getSimpleValueType()) && 3156 TLI.isOperationLegal(ISD::SETCC, 3157 getSetCCResultType(N0.getValueType()))))) 3158 return DAG.getSetCC(SDLoc(N), N0.getValueType(), 3159 LL, LR, Result); 3160 } 3161 } 3162 3163 // Simplify: (or (op x...), (op y...)) -> (op (or x, y)) 3164 if (N0.getOpcode() == N1.getOpcode()) { 3165 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 3166 if (Tmp.getNode()) return Tmp; 3167 } 3168 3169 // (or (and X, C1), (and Y, C2)) -> (and (or X, Y), C3) if possible. 3170 if (N0.getOpcode() == ISD::AND && 3171 N1.getOpcode() == ISD::AND && 3172 N0.getOperand(1).getOpcode() == ISD::Constant && 3173 N1.getOperand(1).getOpcode() == ISD::Constant && 3174 // Don't increase # computations. 3175 (N0.getNode()->hasOneUse() || N1.getNode()->hasOneUse())) { 3176 // We can only do this xform if we know that bits from X that are set in C2 3177 // but not in C1 are already zero. Likewise for Y. 3178 const APInt &LHSMask = 3179 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 3180 const APInt &RHSMask = 3181 cast<ConstantSDNode>(N1.getOperand(1))->getAPIntValue(); 3182 3183 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) && 3184 DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) { 3185 SDValue X = DAG.getNode(ISD::OR, SDLoc(N0), VT, 3186 N0.getOperand(0), N1.getOperand(0)); 3187 return DAG.getNode(ISD::AND, SDLoc(N), VT, X, 3188 DAG.getConstant(LHSMask | RHSMask, VT)); 3189 } 3190 } 3191 3192 // See if this is some rotate idiom. 3193 if (SDNode *Rot = MatchRotate(N0, N1, SDLoc(N))) 3194 return SDValue(Rot, 0); 3195 3196 // Simplify the operands using demanded-bits information. 3197 if (!VT.isVector() && 3198 SimplifyDemandedBits(SDValue(N, 0))) 3199 return SDValue(N, 0); 3200 3201 return SDValue(); 3202} 3203 3204/// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present. 3205static bool MatchRotateHalf(SDValue Op, SDValue &Shift, SDValue &Mask) { 3206 if (Op.getOpcode() == ISD::AND) { 3207 if (isa<ConstantSDNode>(Op.getOperand(1))) { 3208 Mask = Op.getOperand(1); 3209 Op = Op.getOperand(0); 3210 } else { 3211 return false; 3212 } 3213 } 3214 3215 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) { 3216 Shift = Op; 3217 return true; 3218 } 3219 3220 return false; 3221} 3222 3223// MatchRotate - Handle an 'or' of two operands. If this is one of the many 3224// idioms for rotate, and if the target supports rotation instructions, generate 3225// a rot[lr]. 3226SDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS, SDLoc DL) { 3227 // Must be a legal type. Expanded 'n promoted things won't work with rotates. 3228 EVT VT = LHS.getValueType(); 3229 if (!TLI.isTypeLegal(VT)) return 0; 3230 3231 // The target must have at least one rotate flavor. 3232 bool HasROTL = TLI.isOperationLegalOrCustom(ISD::ROTL, VT); 3233 bool HasROTR = TLI.isOperationLegalOrCustom(ISD::ROTR, VT); 3234 if (!HasROTL && !HasROTR) return 0; 3235 3236 // Match "(X shl/srl V1) & V2" where V2 may not be present. 3237 SDValue LHSShift; // The shift. 3238 SDValue LHSMask; // AND value if any. 3239 if (!MatchRotateHalf(LHS, LHSShift, LHSMask)) 3240 return 0; // Not part of a rotate. 3241 3242 SDValue RHSShift; // The shift. 3243 SDValue RHSMask; // AND value if any. 3244 if (!MatchRotateHalf(RHS, RHSShift, RHSMask)) 3245 return 0; // Not part of a rotate. 3246 3247 if (LHSShift.getOperand(0) != RHSShift.getOperand(0)) 3248 return 0; // Not shifting the same value. 3249 3250 if (LHSShift.getOpcode() == RHSShift.getOpcode()) 3251 return 0; // Shifts must disagree. 3252 3253 // Canonicalize shl to left side in a shl/srl pair. 3254 if (RHSShift.getOpcode() == ISD::SHL) { 3255 std::swap(LHS, RHS); 3256 std::swap(LHSShift, RHSShift); 3257 std::swap(LHSMask , RHSMask ); 3258 } 3259 3260 unsigned OpSizeInBits = VT.getSizeInBits(); 3261 SDValue LHSShiftArg = LHSShift.getOperand(0); 3262 SDValue LHSShiftAmt = LHSShift.getOperand(1); 3263 SDValue RHSShiftAmt = RHSShift.getOperand(1); 3264 3265 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1) 3266 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2) 3267 if (LHSShiftAmt.getOpcode() == ISD::Constant && 3268 RHSShiftAmt.getOpcode() == ISD::Constant) { 3269 uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getZExtValue(); 3270 uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getZExtValue(); 3271 if ((LShVal + RShVal) != OpSizeInBits) 3272 return 0; 3273 3274 SDValue Rot = DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT, 3275 LHSShiftArg, HasROTL ? LHSShiftAmt : RHSShiftAmt); 3276 3277 // If there is an AND of either shifted operand, apply it to the result. 3278 if (LHSMask.getNode() || RHSMask.getNode()) { 3279 APInt Mask = APInt::getAllOnesValue(OpSizeInBits); 3280 3281 if (LHSMask.getNode()) { 3282 APInt RHSBits = APInt::getLowBitsSet(OpSizeInBits, LShVal); 3283 Mask &= cast<ConstantSDNode>(LHSMask)->getAPIntValue() | RHSBits; 3284 } 3285 if (RHSMask.getNode()) { 3286 APInt LHSBits = APInt::getHighBitsSet(OpSizeInBits, RShVal); 3287 Mask &= cast<ConstantSDNode>(RHSMask)->getAPIntValue() | LHSBits; 3288 } 3289 3290 Rot = DAG.getNode(ISD::AND, DL, VT, Rot, DAG.getConstant(Mask, VT)); 3291 } 3292 3293 return Rot.getNode(); 3294 } 3295 3296 // If there is a mask here, and we have a variable shift, we can't be sure 3297 // that we're masking out the right stuff. 3298 if (LHSMask.getNode() || RHSMask.getNode()) 3299 return 0; 3300 3301 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y) 3302 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y)) 3303 if (RHSShiftAmt.getOpcode() == ISD::SUB && 3304 LHSShiftAmt == RHSShiftAmt.getOperand(1)) { 3305 if (ConstantSDNode *SUBC = 3306 dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) { 3307 if (SUBC->getAPIntValue() == OpSizeInBits) { 3308 return DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT, LHSShiftArg, 3309 HasROTL ? LHSShiftAmt : RHSShiftAmt).getNode(); 3310 } 3311 } 3312 } 3313 3314 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y) 3315 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y)) 3316 if (LHSShiftAmt.getOpcode() == ISD::SUB && 3317 RHSShiftAmt == LHSShiftAmt.getOperand(1)) { 3318 if (ConstantSDNode *SUBC = 3319 dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) { 3320 if (SUBC->getAPIntValue() == OpSizeInBits) { 3321 return DAG.getNode(HasROTR ? ISD::ROTR : ISD::ROTL, DL, VT, LHSShiftArg, 3322 HasROTR ? RHSShiftAmt : LHSShiftAmt).getNode(); 3323 } 3324 } 3325 } 3326 3327 // Look for sign/zext/any-extended or truncate cases: 3328 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND || 3329 LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND || 3330 LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND || 3331 LHSShiftAmt.getOpcode() == ISD::TRUNCATE) && 3332 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND || 3333 RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND || 3334 RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND || 3335 RHSShiftAmt.getOpcode() == ISD::TRUNCATE)) { 3336 SDValue LExtOp0 = LHSShiftAmt.getOperand(0); 3337 SDValue RExtOp0 = RHSShiftAmt.getOperand(0); 3338 if (RExtOp0.getOpcode() == ISD::SUB && 3339 RExtOp0.getOperand(1) == LExtOp0) { 3340 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 3341 // (rotl x, y) 3342 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 3343 // (rotr x, (sub 32, y)) 3344 if (ConstantSDNode *SUBC = 3345 dyn_cast<ConstantSDNode>(RExtOp0.getOperand(0))) { 3346 if (SUBC->getAPIntValue() == OpSizeInBits) { 3347 return DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT, 3348 LHSShiftArg, 3349 HasROTL ? LHSShiftAmt : RHSShiftAmt).getNode(); 3350 } 3351 } 3352 } else if (LExtOp0.getOpcode() == ISD::SUB && 3353 RExtOp0 == LExtOp0.getOperand(1)) { 3354 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) -> 3355 // (rotr x, y) 3356 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) -> 3357 // (rotl x, (sub 32, y)) 3358 if (ConstantSDNode *SUBC = 3359 dyn_cast<ConstantSDNode>(LExtOp0.getOperand(0))) { 3360 if (SUBC->getAPIntValue() == OpSizeInBits) { 3361 return DAG.getNode(HasROTR ? ISD::ROTR : ISD::ROTL, DL, VT, 3362 LHSShiftArg, 3363 HasROTR ? RHSShiftAmt : LHSShiftAmt).getNode(); 3364 } 3365 } 3366 } 3367 } 3368 3369 return 0; 3370} 3371 3372SDValue DAGCombiner::visitXOR(SDNode *N) { 3373 SDValue N0 = N->getOperand(0); 3374 SDValue N1 = N->getOperand(1); 3375 SDValue LHS, RHS, CC; 3376 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3377 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3378 EVT VT = N0.getValueType(); 3379 3380 // fold vector ops 3381 if (VT.isVector()) { 3382 SDValue FoldedVOp = SimplifyVBinOp(N); 3383 if (FoldedVOp.getNode()) return FoldedVOp; 3384 3385 // fold (xor x, 0) -> x, vector edition 3386 if (ISD::isBuildVectorAllZeros(N0.getNode())) 3387 return N1; 3388 if (ISD::isBuildVectorAllZeros(N1.getNode())) 3389 return N0; 3390 } 3391 3392 // fold (xor undef, undef) -> 0. This is a common idiom (misuse). 3393 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF) 3394 return DAG.getConstant(0, VT); 3395 // fold (xor x, undef) -> undef 3396 if (N0.getOpcode() == ISD::UNDEF) 3397 return N0; 3398 if (N1.getOpcode() == ISD::UNDEF) 3399 return N1; 3400 // fold (xor c1, c2) -> c1^c2 3401 if (N0C && N1C) 3402 return DAG.FoldConstantArithmetic(ISD::XOR, VT, N0C, N1C); 3403 // canonicalize constant to RHS 3404 if (N0C && !N1C) 3405 return DAG.getNode(ISD::XOR, SDLoc(N), VT, N1, N0); 3406 // fold (xor x, 0) -> x 3407 if (N1C && N1C->isNullValue()) 3408 return N0; 3409 // reassociate xor 3410 SDValue RXOR = ReassociateOps(ISD::XOR, SDLoc(N), N0, N1); 3411 if (RXOR.getNode() != 0) 3412 return RXOR; 3413 3414 // fold !(x cc y) -> (x !cc y) 3415 if (N1C && N1C->getAPIntValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) { 3416 bool isInt = LHS.getValueType().isInteger(); 3417 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(), 3418 isInt); 3419 3420 if (!LegalOperations || 3421 TLI.isCondCodeLegal(NotCC, LHS.getSimpleValueType())) { 3422 switch (N0.getOpcode()) { 3423 default: 3424 llvm_unreachable("Unhandled SetCC Equivalent!"); 3425 case ISD::SETCC: 3426 return DAG.getSetCC(SDLoc(N), VT, LHS, RHS, NotCC); 3427 case ISD::SELECT_CC: 3428 return DAG.getSelectCC(SDLoc(N), LHS, RHS, N0.getOperand(2), 3429 N0.getOperand(3), NotCC); 3430 } 3431 } 3432 } 3433 3434 // fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y))) 3435 if (N1C && N1C->getAPIntValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND && 3436 N0.getNode()->hasOneUse() && 3437 isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){ 3438 SDValue V = N0.getOperand(0); 3439 V = DAG.getNode(ISD::XOR, SDLoc(N0), V.getValueType(), V, 3440 DAG.getConstant(1, V.getValueType())); 3441 AddToWorkList(V.getNode()); 3442 return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), VT, V); 3443 } 3444 3445 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are setcc 3446 if (N1C && N1C->getAPIntValue() == 1 && VT == MVT::i1 && 3447 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 3448 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1); 3449 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) { 3450 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 3451 LHS = DAG.getNode(ISD::XOR, SDLoc(LHS), VT, LHS, N1); // LHS = ~LHS 3452 RHS = DAG.getNode(ISD::XOR, SDLoc(RHS), VT, RHS, N1); // RHS = ~RHS 3453 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode()); 3454 return DAG.getNode(NewOpcode, SDLoc(N), VT, LHS, RHS); 3455 } 3456 } 3457 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are constants 3458 if (N1C && N1C->isAllOnesValue() && 3459 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 3460 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1); 3461 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) { 3462 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 3463 LHS = DAG.getNode(ISD::XOR, SDLoc(LHS), VT, LHS, N1); // LHS = ~LHS 3464 RHS = DAG.getNode(ISD::XOR, SDLoc(RHS), VT, RHS, N1); // RHS = ~RHS 3465 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode()); 3466 return DAG.getNode(NewOpcode, SDLoc(N), VT, LHS, RHS); 3467 } 3468 } 3469 // fold (xor (and x, y), y) -> (and (not x), y) 3470 if (N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() && 3471 N0->getOperand(1) == N1) { 3472 SDValue X = N0->getOperand(0); 3473 SDValue NotX = DAG.getNOT(SDLoc(X), X, VT); 3474 AddToWorkList(NotX.getNode()); 3475 return DAG.getNode(ISD::AND, SDLoc(N), VT, NotX, N1); 3476 } 3477 // fold (xor (xor x, c1), c2) -> (xor x, (xor c1, c2)) 3478 if (N1C && N0.getOpcode() == ISD::XOR) { 3479 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0)); 3480 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 3481 if (N00C) 3482 return DAG.getNode(ISD::XOR, SDLoc(N), VT, N0.getOperand(1), 3483 DAG.getConstant(N1C->getAPIntValue() ^ 3484 N00C->getAPIntValue(), VT)); 3485 if (N01C) 3486 return DAG.getNode(ISD::XOR, SDLoc(N), VT, N0.getOperand(0), 3487 DAG.getConstant(N1C->getAPIntValue() ^ 3488 N01C->getAPIntValue(), VT)); 3489 } 3490 // fold (xor x, x) -> 0 3491 if (N0 == N1) 3492 return tryFoldToZero(SDLoc(N), TLI, VT, DAG, LegalOperations); 3493 3494 // Simplify: xor (op x...), (op y...) -> (op (xor x, y)) 3495 if (N0.getOpcode() == N1.getOpcode()) { 3496 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 3497 if (Tmp.getNode()) return Tmp; 3498 } 3499 3500 // Simplify the expression using non-local knowledge. 3501 if (!VT.isVector() && 3502 SimplifyDemandedBits(SDValue(N, 0))) 3503 return SDValue(N, 0); 3504 3505 return SDValue(); 3506} 3507 3508/// visitShiftByConstant - Handle transforms common to the three shifts, when 3509/// the shift amount is a constant. 3510SDValue DAGCombiner::visitShiftByConstant(SDNode *N, unsigned Amt) { 3511 SDNode *LHS = N->getOperand(0).getNode(); 3512 if (!LHS->hasOneUse()) return SDValue(); 3513 3514 // We want to pull some binops through shifts, so that we have (and (shift)) 3515 // instead of (shift (and)), likewise for add, or, xor, etc. This sort of 3516 // thing happens with address calculations, so it's important to canonicalize 3517 // it. 3518 bool HighBitSet = false; // Can we transform this if the high bit is set? 3519 3520 switch (LHS->getOpcode()) { 3521 default: return SDValue(); 3522 case ISD::OR: 3523 case ISD::XOR: 3524 HighBitSet = false; // We can only transform sra if the high bit is clear. 3525 break; 3526 case ISD::AND: 3527 HighBitSet = true; // We can only transform sra if the high bit is set. 3528 break; 3529 case ISD::ADD: 3530 if (N->getOpcode() != ISD::SHL) 3531 return SDValue(); // only shl(add) not sr[al](add). 3532 HighBitSet = false; // We can only transform sra if the high bit is clear. 3533 break; 3534 } 3535 3536 // We require the RHS of the binop to be a constant as well. 3537 ConstantSDNode *BinOpCst = dyn_cast<ConstantSDNode>(LHS->getOperand(1)); 3538 if (!BinOpCst) return SDValue(); 3539 3540 // FIXME: disable this unless the input to the binop is a shift by a constant. 3541 // If it is not a shift, it pessimizes some common cases like: 3542 // 3543 // void foo(int *X, int i) { X[i & 1235] = 1; } 3544 // int bar(int *X, int i) { return X[i & 255]; } 3545 SDNode *BinOpLHSVal = LHS->getOperand(0).getNode(); 3546 if ((BinOpLHSVal->getOpcode() != ISD::SHL && 3547 BinOpLHSVal->getOpcode() != ISD::SRA && 3548 BinOpLHSVal->getOpcode() != ISD::SRL) || 3549 !isa<ConstantSDNode>(BinOpLHSVal->getOperand(1))) 3550 return SDValue(); 3551 3552 EVT VT = N->getValueType(0); 3553 3554 // If this is a signed shift right, and the high bit is modified by the 3555 // logical operation, do not perform the transformation. The highBitSet 3556 // boolean indicates the value of the high bit of the constant which would 3557 // cause it to be modified for this operation. 3558 if (N->getOpcode() == ISD::SRA) { 3559 bool BinOpRHSSignSet = BinOpCst->getAPIntValue().isNegative(); 3560 if (BinOpRHSSignSet != HighBitSet) 3561 return SDValue(); 3562 } 3563 3564 // Fold the constants, shifting the binop RHS by the shift amount. 3565 SDValue NewRHS = DAG.getNode(N->getOpcode(), SDLoc(LHS->getOperand(1)), 3566 N->getValueType(0), 3567 LHS->getOperand(1), N->getOperand(1)); 3568 3569 // Create the new shift. 3570 SDValue NewShift = DAG.getNode(N->getOpcode(), 3571 SDLoc(LHS->getOperand(0)), 3572 VT, LHS->getOperand(0), N->getOperand(1)); 3573 3574 // Create the new binop. 3575 return DAG.getNode(LHS->getOpcode(), SDLoc(N), VT, NewShift, NewRHS); 3576} 3577 3578SDValue DAGCombiner::visitSHL(SDNode *N) { 3579 SDValue N0 = N->getOperand(0); 3580 SDValue N1 = N->getOperand(1); 3581 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3582 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3583 EVT VT = N0.getValueType(); 3584 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits(); 3585 3586 // fold (shl c1, c2) -> c1<<c2 3587 if (N0C && N1C) 3588 return DAG.FoldConstantArithmetic(ISD::SHL, VT, N0C, N1C); 3589 // fold (shl 0, x) -> 0 3590 if (N0C && N0C->isNullValue()) 3591 return N0; 3592 // fold (shl x, c >= size(x)) -> undef 3593 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 3594 return DAG.getUNDEF(VT); 3595 // fold (shl x, 0) -> x 3596 if (N1C && N1C->isNullValue()) 3597 return N0; 3598 // fold (shl undef, x) -> 0 3599 if (N0.getOpcode() == ISD::UNDEF) 3600 return DAG.getConstant(0, VT); 3601 // if (shl x, c) is known to be zero, return 0 3602 if (DAG.MaskedValueIsZero(SDValue(N, 0), 3603 APInt::getAllOnesValue(OpSizeInBits))) 3604 return DAG.getConstant(0, VT); 3605 // fold (shl x, (trunc (and y, c))) -> (shl x, (and (trunc y), (trunc c))). 3606 if (N1.getOpcode() == ISD::TRUNCATE && 3607 N1.getOperand(0).getOpcode() == ISD::AND && 3608 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 3609 SDValue N101 = N1.getOperand(0).getOperand(1); 3610 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 3611 EVT TruncVT = N1.getValueType(); 3612 SDValue N100 = N1.getOperand(0).getOperand(0); 3613 APInt TruncC = N101C->getAPIntValue(); 3614 TruncC = TruncC.trunc(TruncVT.getSizeInBits()); 3615 return DAG.getNode(ISD::SHL, SDLoc(N), VT, N0, 3616 DAG.getNode(ISD::AND, SDLoc(N), TruncVT, 3617 DAG.getNode(ISD::TRUNCATE, 3618 SDLoc(N), 3619 TruncVT, N100), 3620 DAG.getConstant(TruncC, TruncVT))); 3621 } 3622 } 3623 3624 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 3625 return SDValue(N, 0); 3626 3627 // fold (shl (shl x, c1), c2) -> 0 or (shl x, (add c1, c2)) 3628 if (N1C && N0.getOpcode() == ISD::SHL && 3629 N0.getOperand(1).getOpcode() == ISD::Constant) { 3630 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 3631 uint64_t c2 = N1C->getZExtValue(); 3632 if (c1 + c2 >= OpSizeInBits) 3633 return DAG.getConstant(0, VT); 3634 return DAG.getNode(ISD::SHL, SDLoc(N), VT, N0.getOperand(0), 3635 DAG.getConstant(c1 + c2, N1.getValueType())); 3636 } 3637 3638 // fold (shl (ext (shl x, c1)), c2) -> (ext (shl x, (add c1, c2))) 3639 // For this to be valid, the second form must not preserve any of the bits 3640 // that are shifted out by the inner shift in the first form. This means 3641 // the outer shift size must be >= the number of bits added by the ext. 3642 // As a corollary, we don't care what kind of ext it is. 3643 if (N1C && (N0.getOpcode() == ISD::ZERO_EXTEND || 3644 N0.getOpcode() == ISD::ANY_EXTEND || 3645 N0.getOpcode() == ISD::SIGN_EXTEND) && 3646 N0.getOperand(0).getOpcode() == ISD::SHL && 3647 isa<ConstantSDNode>(N0.getOperand(0)->getOperand(1))) { 3648 uint64_t c1 = 3649 cast<ConstantSDNode>(N0.getOperand(0)->getOperand(1))->getZExtValue(); 3650 uint64_t c2 = N1C->getZExtValue(); 3651 EVT InnerShiftVT = N0.getOperand(0).getValueType(); 3652 uint64_t InnerShiftSize = InnerShiftVT.getScalarType().getSizeInBits(); 3653 if (c2 >= OpSizeInBits - InnerShiftSize) { 3654 if (c1 + c2 >= OpSizeInBits) 3655 return DAG.getConstant(0, VT); 3656 return DAG.getNode(ISD::SHL, SDLoc(N0), VT, 3657 DAG.getNode(N0.getOpcode(), SDLoc(N0), VT, 3658 N0.getOperand(0)->getOperand(0)), 3659 DAG.getConstant(c1 + c2, N1.getValueType())); 3660 } 3661 } 3662 3663 // fold (shl (srl x, c1), c2) -> (and (shl x, (sub c2, c1), MASK) or 3664 // (and (srl x, (sub c1, c2), MASK) 3665 // Only fold this if the inner shift has no other uses -- if it does, folding 3666 // this will increase the total number of instructions. 3667 if (N1C && N0.getOpcode() == ISD::SRL && N0.hasOneUse() && 3668 N0.getOperand(1).getOpcode() == ISD::Constant) { 3669 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 3670 if (c1 < VT.getSizeInBits()) { 3671 uint64_t c2 = N1C->getZExtValue(); 3672 APInt Mask = APInt::getHighBitsSet(VT.getSizeInBits(), 3673 VT.getSizeInBits() - c1); 3674 SDValue Shift; 3675 if (c2 > c1) { 3676 Mask = Mask.shl(c2-c1); 3677 Shift = DAG.getNode(ISD::SHL, SDLoc(N), VT, N0.getOperand(0), 3678 DAG.getConstant(c2-c1, N1.getValueType())); 3679 } else { 3680 Mask = Mask.lshr(c1-c2); 3681 Shift = DAG.getNode(ISD::SRL, SDLoc(N), VT, N0.getOperand(0), 3682 DAG.getConstant(c1-c2, N1.getValueType())); 3683 } 3684 return DAG.getNode(ISD::AND, SDLoc(N0), VT, Shift, 3685 DAG.getConstant(Mask, VT)); 3686 } 3687 } 3688 // fold (shl (sra x, c1), c1) -> (and x, (shl -1, c1)) 3689 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) { 3690 SDValue HiBitsMask = 3691 DAG.getConstant(APInt::getHighBitsSet(VT.getSizeInBits(), 3692 VT.getSizeInBits() - 3693 N1C->getZExtValue()), 3694 VT); 3695 return DAG.getNode(ISD::AND, SDLoc(N), VT, N0.getOperand(0), 3696 HiBitsMask); 3697 } 3698 3699 if (N1C) { 3700 SDValue NewSHL = visitShiftByConstant(N, N1C->getZExtValue()); 3701 if (NewSHL.getNode()) 3702 return NewSHL; 3703 } 3704 3705 return SDValue(); 3706} 3707 3708SDValue DAGCombiner::visitSRA(SDNode *N) { 3709 SDValue N0 = N->getOperand(0); 3710 SDValue N1 = N->getOperand(1); 3711 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3712 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3713 EVT VT = N0.getValueType(); 3714 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits(); 3715 3716 // fold (sra c1, c2) -> (sra c1, c2) 3717 if (N0C && N1C) 3718 return DAG.FoldConstantArithmetic(ISD::SRA, VT, N0C, N1C); 3719 // fold (sra 0, x) -> 0 3720 if (N0C && N0C->isNullValue()) 3721 return N0; 3722 // fold (sra -1, x) -> -1 3723 if (N0C && N0C->isAllOnesValue()) 3724 return N0; 3725 // fold (sra x, (setge c, size(x))) -> undef 3726 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 3727 return DAG.getUNDEF(VT); 3728 // fold (sra x, 0) -> x 3729 if (N1C && N1C->isNullValue()) 3730 return N0; 3731 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports 3732 // sext_inreg. 3733 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) { 3734 unsigned LowBits = OpSizeInBits - (unsigned)N1C->getZExtValue(); 3735 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), LowBits); 3736 if (VT.isVector()) 3737 ExtVT = EVT::getVectorVT(*DAG.getContext(), 3738 ExtVT, VT.getVectorNumElements()); 3739 if ((!LegalOperations || 3740 TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, ExtVT))) 3741 return DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N), VT, 3742 N0.getOperand(0), DAG.getValueType(ExtVT)); 3743 } 3744 3745 // fold (sra (sra x, c1), c2) -> (sra x, (add c1, c2)) 3746 if (N1C && N0.getOpcode() == ISD::SRA) { 3747 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 3748 unsigned Sum = N1C->getZExtValue() + C1->getZExtValue(); 3749 if (Sum >= OpSizeInBits) Sum = OpSizeInBits-1; 3750 return DAG.getNode(ISD::SRA, SDLoc(N), VT, N0.getOperand(0), 3751 DAG.getConstant(Sum, N1C->getValueType(0))); 3752 } 3753 } 3754 3755 // fold (sra (shl X, m), (sub result_size, n)) 3756 // -> (sign_extend (trunc (shl X, (sub (sub result_size, n), m)))) for 3757 // result_size - n != m. 3758 // If truncate is free for the target sext(shl) is likely to result in better 3759 // code. 3760 if (N0.getOpcode() == ISD::SHL) { 3761 // Get the two constanst of the shifts, CN0 = m, CN = n. 3762 const ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 3763 if (N01C && N1C) { 3764 // Determine what the truncate's result bitsize and type would be. 3765 EVT TruncVT = 3766 EVT::getIntegerVT(*DAG.getContext(), 3767 OpSizeInBits - N1C->getZExtValue()); 3768 // Determine the residual right-shift amount. 3769 signed ShiftAmt = N1C->getZExtValue() - N01C->getZExtValue(); 3770 3771 // If the shift is not a no-op (in which case this should be just a sign 3772 // extend already), the truncated to type is legal, sign_extend is legal 3773 // on that type, and the truncate to that type is both legal and free, 3774 // perform the transform. 3775 if ((ShiftAmt > 0) && 3776 TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND, TruncVT) && 3777 TLI.isOperationLegalOrCustom(ISD::TRUNCATE, VT) && 3778 TLI.isTruncateFree(VT, TruncVT)) { 3779 3780 SDValue Amt = DAG.getConstant(ShiftAmt, 3781 getShiftAmountTy(N0.getOperand(0).getValueType())); 3782 SDValue Shift = DAG.getNode(ISD::SRL, SDLoc(N0), VT, 3783 N0.getOperand(0), Amt); 3784 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, SDLoc(N0), TruncVT, 3785 Shift); 3786 return DAG.getNode(ISD::SIGN_EXTEND, SDLoc(N), 3787 N->getValueType(0), Trunc); 3788 } 3789 } 3790 } 3791 3792 // fold (sra x, (trunc (and y, c))) -> (sra x, (and (trunc y), (trunc c))). 3793 if (N1.getOpcode() == ISD::TRUNCATE && 3794 N1.getOperand(0).getOpcode() == ISD::AND && 3795 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 3796 SDValue N101 = N1.getOperand(0).getOperand(1); 3797 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 3798 EVT TruncVT = N1.getValueType(); 3799 SDValue N100 = N1.getOperand(0).getOperand(0); 3800 APInt TruncC = N101C->getAPIntValue(); 3801 TruncC = TruncC.trunc(TruncVT.getScalarType().getSizeInBits()); 3802 return DAG.getNode(ISD::SRA, SDLoc(N), VT, N0, 3803 DAG.getNode(ISD::AND, SDLoc(N), 3804 TruncVT, 3805 DAG.getNode(ISD::TRUNCATE, 3806 SDLoc(N), 3807 TruncVT, N100), 3808 DAG.getConstant(TruncC, TruncVT))); 3809 } 3810 } 3811 3812 // fold (sra (trunc (sr x, c1)), c2) -> (trunc (sra x, c1+c2)) 3813 // if c1 is equal to the number of bits the trunc removes 3814 if (N0.getOpcode() == ISD::TRUNCATE && 3815 (N0.getOperand(0).getOpcode() == ISD::SRL || 3816 N0.getOperand(0).getOpcode() == ISD::SRA) && 3817 N0.getOperand(0).hasOneUse() && 3818 N0.getOperand(0).getOperand(1).hasOneUse() && 3819 N1C && isa<ConstantSDNode>(N0.getOperand(0).getOperand(1))) { 3820 EVT LargeVT = N0.getOperand(0).getValueType(); 3821 ConstantSDNode *LargeShiftAmt = 3822 cast<ConstantSDNode>(N0.getOperand(0).getOperand(1)); 3823 3824 if (LargeVT.getScalarType().getSizeInBits() - OpSizeInBits == 3825 LargeShiftAmt->getZExtValue()) { 3826 SDValue Amt = 3827 DAG.getConstant(LargeShiftAmt->getZExtValue() + N1C->getZExtValue(), 3828 getShiftAmountTy(N0.getOperand(0).getOperand(0).getValueType())); 3829 SDValue SRA = DAG.getNode(ISD::SRA, SDLoc(N), LargeVT, 3830 N0.getOperand(0).getOperand(0), Amt); 3831 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, SRA); 3832 } 3833 } 3834 3835 // Simplify, based on bits shifted out of the LHS. 3836 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 3837 return SDValue(N, 0); 3838 3839 3840 // If the sign bit is known to be zero, switch this to a SRL. 3841 if (DAG.SignBitIsZero(N0)) 3842 return DAG.getNode(ISD::SRL, SDLoc(N), VT, N0, N1); 3843 3844 if (N1C) { 3845 SDValue NewSRA = visitShiftByConstant(N, N1C->getZExtValue()); 3846 if (NewSRA.getNode()) 3847 return NewSRA; 3848 } 3849 3850 return SDValue(); 3851} 3852 3853SDValue DAGCombiner::visitSRL(SDNode *N) { 3854 SDValue N0 = N->getOperand(0); 3855 SDValue N1 = N->getOperand(1); 3856 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3857 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3858 EVT VT = N0.getValueType(); 3859 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits(); 3860 3861 // fold (srl c1, c2) -> c1 >>u c2 3862 if (N0C && N1C) 3863 return DAG.FoldConstantArithmetic(ISD::SRL, VT, N0C, N1C); 3864 // fold (srl 0, x) -> 0 3865 if (N0C && N0C->isNullValue()) 3866 return N0; 3867 // fold (srl x, c >= size(x)) -> undef 3868 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 3869 return DAG.getUNDEF(VT); 3870 // fold (srl x, 0) -> x 3871 if (N1C && N1C->isNullValue()) 3872 return N0; 3873 // if (srl x, c) is known to be zero, return 0 3874 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0), 3875 APInt::getAllOnesValue(OpSizeInBits))) 3876 return DAG.getConstant(0, VT); 3877 3878 // fold (srl (srl x, c1), c2) -> 0 or (srl x, (add c1, c2)) 3879 if (N1C && N0.getOpcode() == ISD::SRL && 3880 N0.getOperand(1).getOpcode() == ISD::Constant) { 3881 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 3882 uint64_t c2 = N1C->getZExtValue(); 3883 if (c1 + c2 >= OpSizeInBits) 3884 return DAG.getConstant(0, VT); 3885 return DAG.getNode(ISD::SRL, SDLoc(N), VT, N0.getOperand(0), 3886 DAG.getConstant(c1 + c2, N1.getValueType())); 3887 } 3888 3889 // fold (srl (trunc (srl x, c1)), c2) -> 0 or (trunc (srl x, (add c1, c2))) 3890 if (N1C && N0.getOpcode() == ISD::TRUNCATE && 3891 N0.getOperand(0).getOpcode() == ISD::SRL && 3892 isa<ConstantSDNode>(N0.getOperand(0)->getOperand(1))) { 3893 uint64_t c1 = 3894 cast<ConstantSDNode>(N0.getOperand(0)->getOperand(1))->getZExtValue(); 3895 uint64_t c2 = N1C->getZExtValue(); 3896 EVT InnerShiftVT = N0.getOperand(0).getValueType(); 3897 EVT ShiftCountVT = N0.getOperand(0)->getOperand(1).getValueType(); 3898 uint64_t InnerShiftSize = InnerShiftVT.getScalarType().getSizeInBits(); 3899 // This is only valid if the OpSizeInBits + c1 = size of inner shift. 3900 if (c1 + OpSizeInBits == InnerShiftSize) { 3901 if (c1 + c2 >= InnerShiftSize) 3902 return DAG.getConstant(0, VT); 3903 return DAG.getNode(ISD::TRUNCATE, SDLoc(N0), VT, 3904 DAG.getNode(ISD::SRL, SDLoc(N0), InnerShiftVT, 3905 N0.getOperand(0)->getOperand(0), 3906 DAG.getConstant(c1 + c2, ShiftCountVT))); 3907 } 3908 } 3909 3910 // fold (srl (shl x, c), c) -> (and x, cst2) 3911 if (N1C && N0.getOpcode() == ISD::SHL && N0.getOperand(1) == N1 && 3912 N0.getValueSizeInBits() <= 64) { 3913 uint64_t ShAmt = N1C->getZExtValue()+64-N0.getValueSizeInBits(); 3914 return DAG.getNode(ISD::AND, SDLoc(N), VT, N0.getOperand(0), 3915 DAG.getConstant(~0ULL >> ShAmt, VT)); 3916 } 3917 3918 3919 // fold (srl (anyextend x), c) -> (anyextend (srl x, c)) 3920 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 3921 // Shifting in all undef bits? 3922 EVT SmallVT = N0.getOperand(0).getValueType(); 3923 if (N1C->getZExtValue() >= SmallVT.getSizeInBits()) 3924 return DAG.getUNDEF(VT); 3925 3926 if (!LegalTypes || TLI.isTypeDesirableForOp(ISD::SRL, SmallVT)) { 3927 uint64_t ShiftAmt = N1C->getZExtValue(); 3928 SDValue SmallShift = DAG.getNode(ISD::SRL, SDLoc(N0), SmallVT, 3929 N0.getOperand(0), 3930 DAG.getConstant(ShiftAmt, getShiftAmountTy(SmallVT))); 3931 AddToWorkList(SmallShift.getNode()); 3932 return DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), VT, SmallShift); 3933 } 3934 } 3935 3936 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign 3937 // bit, which is unmodified by sra. 3938 if (N1C && N1C->getZExtValue() + 1 == VT.getSizeInBits()) { 3939 if (N0.getOpcode() == ISD::SRA) 3940 return DAG.getNode(ISD::SRL, SDLoc(N), VT, N0.getOperand(0), N1); 3941 } 3942 3943 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit). 3944 if (N1C && N0.getOpcode() == ISD::CTLZ && 3945 N1C->getAPIntValue() == Log2_32(VT.getSizeInBits())) { 3946 APInt KnownZero, KnownOne; 3947 DAG.ComputeMaskedBits(N0.getOperand(0), KnownZero, KnownOne); 3948 3949 // If any of the input bits are KnownOne, then the input couldn't be all 3950 // zeros, thus the result of the srl will always be zero. 3951 if (KnownOne.getBoolValue()) return DAG.getConstant(0, VT); 3952 3953 // If all of the bits input the to ctlz node are known to be zero, then 3954 // the result of the ctlz is "32" and the result of the shift is one. 3955 APInt UnknownBits = ~KnownZero; 3956 if (UnknownBits == 0) return DAG.getConstant(1, VT); 3957 3958 // Otherwise, check to see if there is exactly one bit input to the ctlz. 3959 if ((UnknownBits & (UnknownBits - 1)) == 0) { 3960 // Okay, we know that only that the single bit specified by UnknownBits 3961 // could be set on input to the CTLZ node. If this bit is set, the SRL 3962 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair 3963 // to an SRL/XOR pair, which is likely to simplify more. 3964 unsigned ShAmt = UnknownBits.countTrailingZeros(); 3965 SDValue Op = N0.getOperand(0); 3966 3967 if (ShAmt) { 3968 Op = DAG.getNode(ISD::SRL, SDLoc(N0), VT, Op, 3969 DAG.getConstant(ShAmt, getShiftAmountTy(Op.getValueType()))); 3970 AddToWorkList(Op.getNode()); 3971 } 3972 3973 return DAG.getNode(ISD::XOR, SDLoc(N), VT, 3974 Op, DAG.getConstant(1, VT)); 3975 } 3976 } 3977 3978 // fold (srl x, (trunc (and y, c))) -> (srl x, (and (trunc y), (trunc c))). 3979 if (N1.getOpcode() == ISD::TRUNCATE && 3980 N1.getOperand(0).getOpcode() == ISD::AND && 3981 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 3982 SDValue N101 = N1.getOperand(0).getOperand(1); 3983 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 3984 EVT TruncVT = N1.getValueType(); 3985 SDValue N100 = N1.getOperand(0).getOperand(0); 3986 APInt TruncC = N101C->getAPIntValue(); 3987 TruncC = TruncC.trunc(TruncVT.getSizeInBits()); 3988 return DAG.getNode(ISD::SRL, SDLoc(N), VT, N0, 3989 DAG.getNode(ISD::AND, SDLoc(N), 3990 TruncVT, 3991 DAG.getNode(ISD::TRUNCATE, 3992 SDLoc(N), 3993 TruncVT, N100), 3994 DAG.getConstant(TruncC, TruncVT))); 3995 } 3996 } 3997 3998 // fold operands of srl based on knowledge that the low bits are not 3999 // demanded. 4000 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 4001 return SDValue(N, 0); 4002 4003 if (N1C) { 4004 SDValue NewSRL = visitShiftByConstant(N, N1C->getZExtValue()); 4005 if (NewSRL.getNode()) 4006 return NewSRL; 4007 } 4008 4009 // Attempt to convert a srl of a load into a narrower zero-extending load. 4010 SDValue NarrowLoad = ReduceLoadWidth(N); 4011 if (NarrowLoad.getNode()) 4012 return NarrowLoad; 4013 4014 // Here is a common situation. We want to optimize: 4015 // 4016 // %a = ... 4017 // %b = and i32 %a, 2 4018 // %c = srl i32 %b, 1 4019 // brcond i32 %c ... 4020 // 4021 // into 4022 // 4023 // %a = ... 4024 // %b = and %a, 2 4025 // %c = setcc eq %b, 0 4026 // brcond %c ... 4027 // 4028 // However when after the source operand of SRL is optimized into AND, the SRL 4029 // itself may not be optimized further. Look for it and add the BRCOND into 4030 // the worklist. 4031 if (N->hasOneUse()) { 4032 SDNode *Use = *N->use_begin(); 4033 if (Use->getOpcode() == ISD::BRCOND) 4034 AddToWorkList(Use); 4035 else if (Use->getOpcode() == ISD::TRUNCATE && Use->hasOneUse()) { 4036 // Also look pass the truncate. 4037 Use = *Use->use_begin(); 4038 if (Use->getOpcode() == ISD::BRCOND) 4039 AddToWorkList(Use); 4040 } 4041 } 4042 4043 return SDValue(); 4044} 4045 4046SDValue DAGCombiner::visitCTLZ(SDNode *N) { 4047 SDValue N0 = N->getOperand(0); 4048 EVT VT = N->getValueType(0); 4049 4050 // fold (ctlz c1) -> c2 4051 if (isa<ConstantSDNode>(N0)) 4052 return DAG.getNode(ISD::CTLZ, SDLoc(N), VT, N0); 4053 return SDValue(); 4054} 4055 4056SDValue DAGCombiner::visitCTLZ_ZERO_UNDEF(SDNode *N) { 4057 SDValue N0 = N->getOperand(0); 4058 EVT VT = N->getValueType(0); 4059 4060 // fold (ctlz_zero_undef c1) -> c2 4061 if (isa<ConstantSDNode>(N0)) 4062 return DAG.getNode(ISD::CTLZ_ZERO_UNDEF, SDLoc(N), VT, N0); 4063 return SDValue(); 4064} 4065 4066SDValue DAGCombiner::visitCTTZ(SDNode *N) { 4067 SDValue N0 = N->getOperand(0); 4068 EVT VT = N->getValueType(0); 4069 4070 // fold (cttz c1) -> c2 4071 if (isa<ConstantSDNode>(N0)) 4072 return DAG.getNode(ISD::CTTZ, SDLoc(N), VT, N0); 4073 return SDValue(); 4074} 4075 4076SDValue DAGCombiner::visitCTTZ_ZERO_UNDEF(SDNode *N) { 4077 SDValue N0 = N->getOperand(0); 4078 EVT VT = N->getValueType(0); 4079 4080 // fold (cttz_zero_undef c1) -> c2 4081 if (isa<ConstantSDNode>(N0)) 4082 return DAG.getNode(ISD::CTTZ_ZERO_UNDEF, SDLoc(N), VT, N0); 4083 return SDValue(); 4084} 4085 4086SDValue DAGCombiner::visitCTPOP(SDNode *N) { 4087 SDValue N0 = N->getOperand(0); 4088 EVT VT = N->getValueType(0); 4089 4090 // fold (ctpop c1) -> c2 4091 if (isa<ConstantSDNode>(N0)) 4092 return DAG.getNode(ISD::CTPOP, SDLoc(N), VT, N0); 4093 return SDValue(); 4094} 4095 4096SDValue DAGCombiner::visitSELECT(SDNode *N) { 4097 SDValue N0 = N->getOperand(0); 4098 SDValue N1 = N->getOperand(1); 4099 SDValue N2 = N->getOperand(2); 4100 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 4101 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 4102 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2); 4103 EVT VT = N->getValueType(0); 4104 EVT VT0 = N0.getValueType(); 4105 4106 // fold (select C, X, X) -> X 4107 if (N1 == N2) 4108 return N1; 4109 // fold (select true, X, Y) -> X 4110 if (N0C && !N0C->isNullValue()) 4111 return N1; 4112 // fold (select false, X, Y) -> Y 4113 if (N0C && N0C->isNullValue()) 4114 return N2; 4115 // fold (select C, 1, X) -> (or C, X) 4116 if (VT == MVT::i1 && N1C && N1C->getAPIntValue() == 1) 4117 return DAG.getNode(ISD::OR, SDLoc(N), VT, N0, N2); 4118 // fold (select C, 0, 1) -> (xor C, 1) 4119 if (VT.isInteger() && 4120 (VT0 == MVT::i1 || 4121 (VT0.isInteger() && 4122 TLI.getBooleanContents(false) == 4123 TargetLowering::ZeroOrOneBooleanContent)) && 4124 N1C && N2C && N1C->isNullValue() && N2C->getAPIntValue() == 1) { 4125 SDValue XORNode; 4126 if (VT == VT0) 4127 return DAG.getNode(ISD::XOR, SDLoc(N), VT0, 4128 N0, DAG.getConstant(1, VT0)); 4129 XORNode = DAG.getNode(ISD::XOR, SDLoc(N0), VT0, 4130 N0, DAG.getConstant(1, VT0)); 4131 AddToWorkList(XORNode.getNode()); 4132 if (VT.bitsGT(VT0)) 4133 return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), VT, XORNode); 4134 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, XORNode); 4135 } 4136 // fold (select C, 0, X) -> (and (not C), X) 4137 if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) { 4138 SDValue NOTNode = DAG.getNOT(SDLoc(N0), N0, VT); 4139 AddToWorkList(NOTNode.getNode()); 4140 return DAG.getNode(ISD::AND, SDLoc(N), VT, NOTNode, N2); 4141 } 4142 // fold (select C, X, 1) -> (or (not C), X) 4143 if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getAPIntValue() == 1) { 4144 SDValue NOTNode = DAG.getNOT(SDLoc(N0), N0, VT); 4145 AddToWorkList(NOTNode.getNode()); 4146 return DAG.getNode(ISD::OR, SDLoc(N), VT, NOTNode, N1); 4147 } 4148 // fold (select C, X, 0) -> (and C, X) 4149 if (VT == MVT::i1 && N2C && N2C->isNullValue()) 4150 return DAG.getNode(ISD::AND, SDLoc(N), VT, N0, N1); 4151 // fold (select X, X, Y) -> (or X, Y) 4152 // fold (select X, 1, Y) -> (or X, Y) 4153 if (VT == MVT::i1 && (N0 == N1 || (N1C && N1C->getAPIntValue() == 1))) 4154 return DAG.getNode(ISD::OR, SDLoc(N), VT, N0, N2); 4155 // fold (select X, Y, X) -> (and X, Y) 4156 // fold (select X, Y, 0) -> (and X, Y) 4157 if (VT == MVT::i1 && (N0 == N2 || (N2C && N2C->getAPIntValue() == 0))) 4158 return DAG.getNode(ISD::AND, SDLoc(N), VT, N0, N1); 4159 4160 // If we can fold this based on the true/false value, do so. 4161 if (SimplifySelectOps(N, N1, N2)) 4162 return SDValue(N, 0); // Don't revisit N. 4163 4164 // fold selects based on a setcc into other things, such as min/max/abs 4165 if (N0.getOpcode() == ISD::SETCC) { 4166 // FIXME: 4167 // Check against MVT::Other for SELECT_CC, which is a workaround for targets 4168 // having to say they don't support SELECT_CC on every type the DAG knows 4169 // about, since there is no way to mark an opcode illegal at all value types 4170 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other) && 4171 TLI.isOperationLegalOrCustom(ISD::SELECT_CC, VT)) 4172 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), VT, 4173 N0.getOperand(0), N0.getOperand(1), 4174 N1, N2, N0.getOperand(2)); 4175 return SimplifySelect(SDLoc(N), N0, N1, N2); 4176 } 4177 4178 return SDValue(); 4179} 4180 4181SDValue DAGCombiner::visitVSELECT(SDNode *N) { 4182 SDValue N0 = N->getOperand(0); 4183 SDValue N1 = N->getOperand(1); 4184 SDValue N2 = N->getOperand(2); 4185 SDLoc DL(N); 4186 4187 // Canonicalize integer abs. 4188 // vselect (setg[te] X, 0), X, -X -> 4189 // vselect (setgt X, -1), X, -X -> 4190 // vselect (setl[te] X, 0), -X, X -> 4191 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 4192 if (N0.getOpcode() == ISD::SETCC) { 4193 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1); 4194 ISD::CondCode CC = cast<CondCodeSDNode>(N0.getOperand(2))->get(); 4195 bool isAbs = false; 4196 bool RHSIsAllZeros = ISD::isBuildVectorAllZeros(RHS.getNode()); 4197 4198 if (((RHSIsAllZeros && (CC == ISD::SETGT || CC == ISD::SETGE)) || 4199 (ISD::isBuildVectorAllOnes(RHS.getNode()) && CC == ISD::SETGT)) && 4200 N1 == LHS && N2.getOpcode() == ISD::SUB && N1 == N2.getOperand(1)) 4201 isAbs = ISD::isBuildVectorAllZeros(N2.getOperand(0).getNode()); 4202 else if ((RHSIsAllZeros && (CC == ISD::SETLT || CC == ISD::SETLE)) && 4203 N2 == LHS && N1.getOpcode() == ISD::SUB && N2 == N1.getOperand(1)) 4204 isAbs = ISD::isBuildVectorAllZeros(N1.getOperand(0).getNode()); 4205 4206 if (isAbs) { 4207 EVT VT = LHS.getValueType(); 4208 SDValue Shift = DAG.getNode( 4209 ISD::SRA, DL, VT, LHS, 4210 DAG.getConstant(VT.getScalarType().getSizeInBits() - 1, VT)); 4211 SDValue Add = DAG.getNode(ISD::ADD, DL, VT, LHS, Shift); 4212 AddToWorkList(Shift.getNode()); 4213 AddToWorkList(Add.getNode()); 4214 return DAG.getNode(ISD::XOR, DL, VT, Add, Shift); 4215 } 4216 } 4217 4218 return SDValue(); 4219} 4220 4221SDValue DAGCombiner::visitSELECT_CC(SDNode *N) { 4222 SDValue N0 = N->getOperand(0); 4223 SDValue N1 = N->getOperand(1); 4224 SDValue N2 = N->getOperand(2); 4225 SDValue N3 = N->getOperand(3); 4226 SDValue N4 = N->getOperand(4); 4227 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get(); 4228 4229 // fold select_cc lhs, rhs, x, x, cc -> x 4230 if (N2 == N3) 4231 return N2; 4232 4233 // Determine if the condition we're dealing with is constant 4234 SDValue SCC = SimplifySetCC(getSetCCResultType(N0.getValueType()), 4235 N0, N1, CC, SDLoc(N), false); 4236 if (SCC.getNode()) AddToWorkList(SCC.getNode()); 4237 4238 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode())) { 4239 if (!SCCC->isNullValue()) 4240 return N2; // cond always true -> true val 4241 else 4242 return N3; // cond always false -> false val 4243 } 4244 4245 // Fold to a simpler select_cc 4246 if (SCC.getNode() && SCC.getOpcode() == ISD::SETCC) 4247 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), N2.getValueType(), 4248 SCC.getOperand(0), SCC.getOperand(1), N2, N3, 4249 SCC.getOperand(2)); 4250 4251 // If we can fold this based on the true/false value, do so. 4252 if (SimplifySelectOps(N, N2, N3)) 4253 return SDValue(N, 0); // Don't revisit N. 4254 4255 // fold select_cc into other things, such as min/max/abs 4256 return SimplifySelectCC(SDLoc(N), N0, N1, N2, N3, CC); 4257} 4258 4259SDValue DAGCombiner::visitSETCC(SDNode *N) { 4260 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1), 4261 cast<CondCodeSDNode>(N->getOperand(2))->get(), 4262 SDLoc(N)); 4263} 4264 4265// ExtendUsesToFormExtLoad - Trying to extend uses of a load to enable this: 4266// "fold ({s|z|a}ext (load x)) -> ({s|z|a}ext (truncate ({s|z|a}extload x)))" 4267// transformation. Returns true if extension are possible and the above 4268// mentioned transformation is profitable. 4269static bool ExtendUsesToFormExtLoad(SDNode *N, SDValue N0, 4270 unsigned ExtOpc, 4271 SmallVector<SDNode*, 4> &ExtendNodes, 4272 const TargetLowering &TLI) { 4273 bool HasCopyToRegUses = false; 4274 bool isTruncFree = TLI.isTruncateFree(N->getValueType(0), N0.getValueType()); 4275 for (SDNode::use_iterator UI = N0.getNode()->use_begin(), 4276 UE = N0.getNode()->use_end(); 4277 UI != UE; ++UI) { 4278 SDNode *User = *UI; 4279 if (User == N) 4280 continue; 4281 if (UI.getUse().getResNo() != N0.getResNo()) 4282 continue; 4283 // FIXME: Only extend SETCC N, N and SETCC N, c for now. 4284 if (ExtOpc != ISD::ANY_EXTEND && User->getOpcode() == ISD::SETCC) { 4285 ISD::CondCode CC = cast<CondCodeSDNode>(User->getOperand(2))->get(); 4286 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC)) 4287 // Sign bits will be lost after a zext. 4288 return false; 4289 bool Add = false; 4290 for (unsigned i = 0; i != 2; ++i) { 4291 SDValue UseOp = User->getOperand(i); 4292 if (UseOp == N0) 4293 continue; 4294 if (!isa<ConstantSDNode>(UseOp)) 4295 return false; 4296 Add = true; 4297 } 4298 if (Add) 4299 ExtendNodes.push_back(User); 4300 continue; 4301 } 4302 // If truncates aren't free and there are users we can't 4303 // extend, it isn't worthwhile. 4304 if (!isTruncFree) 4305 return false; 4306 // Remember if this value is live-out. 4307 if (User->getOpcode() == ISD::CopyToReg) 4308 HasCopyToRegUses = true; 4309 } 4310 4311 if (HasCopyToRegUses) { 4312 bool BothLiveOut = false; 4313 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 4314 UI != UE; ++UI) { 4315 SDUse &Use = UI.getUse(); 4316 if (Use.getResNo() == 0 && Use.getUser()->getOpcode() == ISD::CopyToReg) { 4317 BothLiveOut = true; 4318 break; 4319 } 4320 } 4321 if (BothLiveOut) 4322 // Both unextended and extended values are live out. There had better be 4323 // a good reason for the transformation. 4324 return ExtendNodes.size(); 4325 } 4326 return true; 4327} 4328 4329void DAGCombiner::ExtendSetCCUses(SmallVector<SDNode*, 4> SetCCs, 4330 SDValue Trunc, SDValue ExtLoad, SDLoc DL, 4331 ISD::NodeType ExtType) { 4332 // Extend SetCC uses if necessary. 4333 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 4334 SDNode *SetCC = SetCCs[i]; 4335 SmallVector<SDValue, 4> Ops; 4336 4337 for (unsigned j = 0; j != 2; ++j) { 4338 SDValue SOp = SetCC->getOperand(j); 4339 if (SOp == Trunc) 4340 Ops.push_back(ExtLoad); 4341 else 4342 Ops.push_back(DAG.getNode(ExtType, DL, ExtLoad->getValueType(0), SOp)); 4343 } 4344 4345 Ops.push_back(SetCC->getOperand(2)); 4346 CombineTo(SetCC, DAG.getNode(ISD::SETCC, DL, SetCC->getValueType(0), 4347 &Ops[0], Ops.size())); 4348 } 4349} 4350 4351SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) { 4352 SDValue N0 = N->getOperand(0); 4353 EVT VT = N->getValueType(0); 4354 4355 // fold (sext c1) -> c1 4356 if (isa<ConstantSDNode>(N0)) 4357 return DAG.getNode(ISD::SIGN_EXTEND, SDLoc(N), VT, N0); 4358 4359 // fold (sext (sext x)) -> (sext x) 4360 // fold (sext (aext x)) -> (sext x) 4361 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 4362 return DAG.getNode(ISD::SIGN_EXTEND, SDLoc(N), VT, 4363 N0.getOperand(0)); 4364 4365 if (N0.getOpcode() == ISD::TRUNCATE) { 4366 // fold (sext (truncate (load x))) -> (sext (smaller load x)) 4367 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n))) 4368 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 4369 if (NarrowLoad.getNode()) { 4370 SDNode* oye = N0.getNode()->getOperand(0).getNode(); 4371 if (NarrowLoad.getNode() != N0.getNode()) { 4372 CombineTo(N0.getNode(), NarrowLoad); 4373 // CombineTo deleted the truncate, if needed, but not what's under it. 4374 AddToWorkList(oye); 4375 } 4376 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4377 } 4378 4379 // See if the value being truncated is already sign extended. If so, just 4380 // eliminate the trunc/sext pair. 4381 SDValue Op = N0.getOperand(0); 4382 unsigned OpBits = Op.getValueType().getScalarType().getSizeInBits(); 4383 unsigned MidBits = N0.getValueType().getScalarType().getSizeInBits(); 4384 unsigned DestBits = VT.getScalarType().getSizeInBits(); 4385 unsigned NumSignBits = DAG.ComputeNumSignBits(Op); 4386 4387 if (OpBits == DestBits) { 4388 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign 4389 // bits, it is already ready. 4390 if (NumSignBits > DestBits-MidBits) 4391 return Op; 4392 } else if (OpBits < DestBits) { 4393 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign 4394 // bits, just sext from i32. 4395 if (NumSignBits > OpBits-MidBits) 4396 return DAG.getNode(ISD::SIGN_EXTEND, SDLoc(N), VT, Op); 4397 } else { 4398 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign 4399 // bits, just truncate to i32. 4400 if (NumSignBits > OpBits-MidBits) 4401 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, Op); 4402 } 4403 4404 // fold (sext (truncate x)) -> (sextinreg x). 4405 if (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, 4406 N0.getValueType())) { 4407 if (OpBits < DestBits) 4408 Op = DAG.getNode(ISD::ANY_EXTEND, SDLoc(N0), VT, Op); 4409 else if (OpBits > DestBits) 4410 Op = DAG.getNode(ISD::TRUNCATE, SDLoc(N0), VT, Op); 4411 return DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N), VT, Op, 4412 DAG.getValueType(N0.getValueType())); 4413 } 4414 } 4415 4416 // fold (sext (load x)) -> (sext (truncate (sextload x))) 4417 // None of the supported targets knows how to perform load and sign extend 4418 // on vectors in one instruction. We only perform this transformation on 4419 // scalars. 4420 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() && 4421 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 4422 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()))) { 4423 bool DoXform = true; 4424 SmallVector<SDNode*, 4> SetCCs; 4425 if (!N0.hasOneUse()) 4426 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::SIGN_EXTEND, SetCCs, TLI); 4427 if (DoXform) { 4428 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4429 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, SDLoc(N), VT, 4430 LN0->getChain(), 4431 LN0->getBasePtr(), LN0->getPointerInfo(), 4432 N0.getValueType(), 4433 LN0->isVolatile(), LN0->isNonTemporal(), 4434 LN0->getAlignment()); 4435 CombineTo(N, ExtLoad); 4436 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, SDLoc(N0), 4437 N0.getValueType(), ExtLoad); 4438 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 4439 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, SDLoc(N), 4440 ISD::SIGN_EXTEND); 4441 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4442 } 4443 } 4444 4445 // fold (sext (sextload x)) -> (sext (truncate (sextload x))) 4446 // fold (sext ( extload x)) -> (sext (truncate (sextload x))) 4447 if ((ISD::isSEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) && 4448 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) { 4449 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4450 EVT MemVT = LN0->getMemoryVT(); 4451 if ((!LegalOperations && !LN0->isVolatile()) || 4452 TLI.isLoadExtLegal(ISD::SEXTLOAD, MemVT)) { 4453 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, SDLoc(N), VT, 4454 LN0->getChain(), 4455 LN0->getBasePtr(), LN0->getPointerInfo(), 4456 MemVT, 4457 LN0->isVolatile(), LN0->isNonTemporal(), 4458 LN0->getAlignment()); 4459 CombineTo(N, ExtLoad); 4460 CombineTo(N0.getNode(), 4461 DAG.getNode(ISD::TRUNCATE, SDLoc(N0), 4462 N0.getValueType(), ExtLoad), 4463 ExtLoad.getValue(1)); 4464 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4465 } 4466 } 4467 4468 // fold (sext (and/or/xor (load x), cst)) -> 4469 // (and/or/xor (sextload x), (sext cst)) 4470 if ((N0.getOpcode() == ISD::AND || N0.getOpcode() == ISD::OR || 4471 N0.getOpcode() == ISD::XOR) && 4472 isa<LoadSDNode>(N0.getOperand(0)) && 4473 N0.getOperand(1).getOpcode() == ISD::Constant && 4474 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()) && 4475 (!LegalOperations && TLI.isOperationLegal(N0.getOpcode(), VT))) { 4476 LoadSDNode *LN0 = cast<LoadSDNode>(N0.getOperand(0)); 4477 if (LN0->getExtensionType() != ISD::ZEXTLOAD) { 4478 bool DoXform = true; 4479 SmallVector<SDNode*, 4> SetCCs; 4480 if (!N0.hasOneUse()) 4481 DoXform = ExtendUsesToFormExtLoad(N, N0.getOperand(0), ISD::SIGN_EXTEND, 4482 SetCCs, TLI); 4483 if (DoXform) { 4484 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, SDLoc(LN0), VT, 4485 LN0->getChain(), LN0->getBasePtr(), 4486 LN0->getPointerInfo(), 4487 LN0->getMemoryVT(), 4488 LN0->isVolatile(), 4489 LN0->isNonTemporal(), 4490 LN0->getAlignment()); 4491 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 4492 Mask = Mask.sext(VT.getSizeInBits()); 4493 SDValue And = DAG.getNode(N0.getOpcode(), SDLoc(N), VT, 4494 ExtLoad, DAG.getConstant(Mask, VT)); 4495 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, 4496 SDLoc(N0.getOperand(0)), 4497 N0.getOperand(0).getValueType(), ExtLoad); 4498 CombineTo(N, And); 4499 CombineTo(N0.getOperand(0).getNode(), Trunc, ExtLoad.getValue(1)); 4500 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, SDLoc(N), 4501 ISD::SIGN_EXTEND); 4502 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4503 } 4504 } 4505 } 4506 4507 if (N0.getOpcode() == ISD::SETCC) { 4508 // sext(setcc) -> sext_in_reg(vsetcc) for vectors. 4509 // Only do this before legalize for now. 4510 if (VT.isVector() && !LegalOperations && 4511 TLI.getBooleanContents(true) == 4512 TargetLowering::ZeroOrNegativeOneBooleanContent) { 4513 EVT N0VT = N0.getOperand(0).getValueType(); 4514 // On some architectures (such as SSE/NEON/etc) the SETCC result type is 4515 // of the same size as the compared operands. Only optimize sext(setcc()) 4516 // if this is the case. 4517 EVT SVT = getSetCCResultType(N0VT); 4518 4519 // We know that the # elements of the results is the same as the 4520 // # elements of the compare (and the # elements of the compare result 4521 // for that matter). Check to see that they are the same size. If so, 4522 // we know that the element size of the sext'd result matches the 4523 // element size of the compare operands. 4524 if (VT.getSizeInBits() == SVT.getSizeInBits()) 4525 return DAG.getSetCC(SDLoc(N), VT, N0.getOperand(0), 4526 N0.getOperand(1), 4527 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 4528 4529 // If the desired elements are smaller or larger than the source 4530 // elements we can use a matching integer vector type and then 4531 // truncate/sign extend 4532 EVT MatchingVectorType = N0VT.changeVectorElementTypeToInteger(); 4533 if (SVT == MatchingVectorType) { 4534 SDValue VsetCC = DAG.getSetCC(SDLoc(N), MatchingVectorType, 4535 N0.getOperand(0), N0.getOperand(1), 4536 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 4537 return DAG.getSExtOrTrunc(VsetCC, SDLoc(N), VT); 4538 } 4539 } 4540 4541 // sext(setcc x, y, cc) -> (select_cc x, y, -1, 0, cc) 4542 unsigned ElementWidth = VT.getScalarType().getSizeInBits(); 4543 SDValue NegOne = 4544 DAG.getConstant(APInt::getAllOnesValue(ElementWidth), VT); 4545 SDValue SCC = 4546 SimplifySelectCC(SDLoc(N), N0.getOperand(0), N0.getOperand(1), 4547 NegOne, DAG.getConstant(0, VT), 4548 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 4549 if (SCC.getNode()) return SCC; 4550 if (!VT.isVector() && 4551 (!LegalOperations || 4552 TLI.isOperationLegal(ISD::SETCC, getSetCCResultType(VT)))) { 4553 return DAG.getSelect(SDLoc(N), VT, 4554 DAG.getSetCC(SDLoc(N), 4555 getSetCCResultType(VT), 4556 N0.getOperand(0), N0.getOperand(1), 4557 cast<CondCodeSDNode>(N0.getOperand(2))->get()), 4558 NegOne, DAG.getConstant(0, VT)); 4559 } 4560 } 4561 4562 // fold (sext x) -> (zext x) if the sign bit is known zero. 4563 if ((!LegalOperations || TLI.isOperationLegal(ISD::ZERO_EXTEND, VT)) && 4564 DAG.SignBitIsZero(N0)) 4565 return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), VT, N0); 4566 4567 return SDValue(); 4568} 4569 4570// isTruncateOf - If N is a truncate of some other value, return true, record 4571// the value being truncated in Op and which of Op's bits are zero in KnownZero. 4572// This function computes KnownZero to avoid a duplicated call to 4573// ComputeMaskedBits in the caller. 4574static bool isTruncateOf(SelectionDAG &DAG, SDValue N, SDValue &Op, 4575 APInt &KnownZero) { 4576 APInt KnownOne; 4577 if (N->getOpcode() == ISD::TRUNCATE) { 4578 Op = N->getOperand(0); 4579 DAG.ComputeMaskedBits(Op, KnownZero, KnownOne); 4580 return true; 4581 } 4582 4583 if (N->getOpcode() != ISD::SETCC || N->getValueType(0) != MVT::i1 || 4584 cast<CondCodeSDNode>(N->getOperand(2))->get() != ISD::SETNE) 4585 return false; 4586 4587 SDValue Op0 = N->getOperand(0); 4588 SDValue Op1 = N->getOperand(1); 4589 assert(Op0.getValueType() == Op1.getValueType()); 4590 4591 ConstantSDNode *COp0 = dyn_cast<ConstantSDNode>(Op0); 4592 ConstantSDNode *COp1 = dyn_cast<ConstantSDNode>(Op1); 4593 if (COp0 && COp0->isNullValue()) 4594 Op = Op1; 4595 else if (COp1 && COp1->isNullValue()) 4596 Op = Op0; 4597 else 4598 return false; 4599 4600 DAG.ComputeMaskedBits(Op, KnownZero, KnownOne); 4601 4602 if (!(KnownZero | APInt(Op.getValueSizeInBits(), 1)).isAllOnesValue()) 4603 return false; 4604 4605 return true; 4606} 4607 4608SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) { 4609 SDValue N0 = N->getOperand(0); 4610 EVT VT = N->getValueType(0); 4611 4612 // fold (zext c1) -> c1 4613 if (isa<ConstantSDNode>(N0)) 4614 return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), VT, N0); 4615 // fold (zext (zext x)) -> (zext x) 4616 // fold (zext (aext x)) -> (zext x) 4617 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 4618 return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), VT, 4619 N0.getOperand(0)); 4620 4621 // fold (zext (truncate x)) -> (zext x) or 4622 // (zext (truncate x)) -> (truncate x) 4623 // This is valid when the truncated bits of x are already zero. 4624 // FIXME: We should extend this to work for vectors too. 4625 SDValue Op; 4626 APInt KnownZero; 4627 if (!VT.isVector() && isTruncateOf(DAG, N0, Op, KnownZero)) { 4628 APInt TruncatedBits = 4629 (Op.getValueSizeInBits() == N0.getValueSizeInBits()) ? 4630 APInt(Op.getValueSizeInBits(), 0) : 4631 APInt::getBitsSet(Op.getValueSizeInBits(), 4632 N0.getValueSizeInBits(), 4633 std::min(Op.getValueSizeInBits(), 4634 VT.getSizeInBits())); 4635 if (TruncatedBits == (KnownZero & TruncatedBits)) { 4636 if (VT.bitsGT(Op.getValueType())) 4637 return DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N), VT, Op); 4638 if (VT.bitsLT(Op.getValueType())) 4639 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, Op); 4640 4641 return Op; 4642 } 4643 } 4644 4645 // fold (zext (truncate (load x))) -> (zext (smaller load x)) 4646 // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n))) 4647 if (N0.getOpcode() == ISD::TRUNCATE) { 4648 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 4649 if (NarrowLoad.getNode()) { 4650 SDNode* oye = N0.getNode()->getOperand(0).getNode(); 4651 if (NarrowLoad.getNode() != N0.getNode()) { 4652 CombineTo(N0.getNode(), NarrowLoad); 4653 // CombineTo deleted the truncate, if needed, but not what's under it. 4654 AddToWorkList(oye); 4655 } 4656 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4657 } 4658 } 4659 4660 // fold (zext (truncate x)) -> (and x, mask) 4661 if (N0.getOpcode() == ISD::TRUNCATE && 4662 (!LegalOperations || TLI.isOperationLegal(ISD::AND, VT))) { 4663 4664 // fold (zext (truncate (load x))) -> (zext (smaller load x)) 4665 // fold (zext (truncate (srl (load x), c))) -> (zext (smaller load (x+c/n))) 4666 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 4667 if (NarrowLoad.getNode()) { 4668 SDNode* oye = N0.getNode()->getOperand(0).getNode(); 4669 if (NarrowLoad.getNode() != N0.getNode()) { 4670 CombineTo(N0.getNode(), NarrowLoad); 4671 // CombineTo deleted the truncate, if needed, but not what's under it. 4672 AddToWorkList(oye); 4673 } 4674 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4675 } 4676 4677 SDValue Op = N0.getOperand(0); 4678 if (Op.getValueType().bitsLT(VT)) { 4679 Op = DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), VT, Op); 4680 AddToWorkList(Op.getNode()); 4681 } else if (Op.getValueType().bitsGT(VT)) { 4682 Op = DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, Op); 4683 AddToWorkList(Op.getNode()); 4684 } 4685 return DAG.getZeroExtendInReg(Op, SDLoc(N), 4686 N0.getValueType().getScalarType()); 4687 } 4688 4689 // Fold (zext (and (trunc x), cst)) -> (and x, cst), 4690 // if either of the casts is not free. 4691 if (N0.getOpcode() == ISD::AND && 4692 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 4693 N0.getOperand(1).getOpcode() == ISD::Constant && 4694 (!TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(), 4695 N0.getValueType()) || 4696 !TLI.isZExtFree(N0.getValueType(), VT))) { 4697 SDValue X = N0.getOperand(0).getOperand(0); 4698 if (X.getValueType().bitsLT(VT)) { 4699 X = DAG.getNode(ISD::ANY_EXTEND, SDLoc(X), VT, X); 4700 } else if (X.getValueType().bitsGT(VT)) { 4701 X = DAG.getNode(ISD::TRUNCATE, SDLoc(X), VT, X); 4702 } 4703 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 4704 Mask = Mask.zext(VT.getSizeInBits()); 4705 return DAG.getNode(ISD::AND, SDLoc(N), VT, 4706 X, DAG.getConstant(Mask, VT)); 4707 } 4708 4709 // fold (zext (load x)) -> (zext (truncate (zextload x))) 4710 // None of the supported targets knows how to perform load and vector_zext 4711 // on vectors in one instruction. We only perform this transformation on 4712 // scalars. 4713 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() && 4714 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 4715 TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()))) { 4716 bool DoXform = true; 4717 SmallVector<SDNode*, 4> SetCCs; 4718 if (!N0.hasOneUse()) 4719 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ZERO_EXTEND, SetCCs, TLI); 4720 if (DoXform) { 4721 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4722 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(N), VT, 4723 LN0->getChain(), 4724 LN0->getBasePtr(), LN0->getPointerInfo(), 4725 N0.getValueType(), 4726 LN0->isVolatile(), LN0->isNonTemporal(), 4727 LN0->getAlignment()); 4728 CombineTo(N, ExtLoad); 4729 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, SDLoc(N0), 4730 N0.getValueType(), ExtLoad); 4731 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 4732 4733 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, SDLoc(N), 4734 ISD::ZERO_EXTEND); 4735 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4736 } 4737 } 4738 4739 // fold (zext (and/or/xor (load x), cst)) -> 4740 // (and/or/xor (zextload x), (zext cst)) 4741 if ((N0.getOpcode() == ISD::AND || N0.getOpcode() == ISD::OR || 4742 N0.getOpcode() == ISD::XOR) && 4743 isa<LoadSDNode>(N0.getOperand(0)) && 4744 N0.getOperand(1).getOpcode() == ISD::Constant && 4745 TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()) && 4746 (!LegalOperations && TLI.isOperationLegal(N0.getOpcode(), VT))) { 4747 LoadSDNode *LN0 = cast<LoadSDNode>(N0.getOperand(0)); 4748 if (LN0->getExtensionType() != ISD::SEXTLOAD) { 4749 bool DoXform = true; 4750 SmallVector<SDNode*, 4> SetCCs; 4751 if (!N0.hasOneUse()) 4752 DoXform = ExtendUsesToFormExtLoad(N, N0.getOperand(0), ISD::ZERO_EXTEND, 4753 SetCCs, TLI); 4754 if (DoXform) { 4755 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(LN0), VT, 4756 LN0->getChain(), LN0->getBasePtr(), 4757 LN0->getPointerInfo(), 4758 LN0->getMemoryVT(), 4759 LN0->isVolatile(), 4760 LN0->isNonTemporal(), 4761 LN0->getAlignment()); 4762 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 4763 Mask = Mask.zext(VT.getSizeInBits()); 4764 SDValue And = DAG.getNode(N0.getOpcode(), SDLoc(N), VT, 4765 ExtLoad, DAG.getConstant(Mask, VT)); 4766 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, 4767 SDLoc(N0.getOperand(0)), 4768 N0.getOperand(0).getValueType(), ExtLoad); 4769 CombineTo(N, And); 4770 CombineTo(N0.getOperand(0).getNode(), Trunc, ExtLoad.getValue(1)); 4771 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, SDLoc(N), 4772 ISD::ZERO_EXTEND); 4773 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4774 } 4775 } 4776 } 4777 4778 // fold (zext (zextload x)) -> (zext (truncate (zextload x))) 4779 // fold (zext ( extload x)) -> (zext (truncate (zextload x))) 4780 if ((ISD::isZEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) && 4781 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) { 4782 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4783 EVT MemVT = LN0->getMemoryVT(); 4784 if ((!LegalOperations && !LN0->isVolatile()) || 4785 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT)) { 4786 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(N), VT, 4787 LN0->getChain(), 4788 LN0->getBasePtr(), LN0->getPointerInfo(), 4789 MemVT, 4790 LN0->isVolatile(), LN0->isNonTemporal(), 4791 LN0->getAlignment()); 4792 CombineTo(N, ExtLoad); 4793 CombineTo(N0.getNode(), 4794 DAG.getNode(ISD::TRUNCATE, SDLoc(N0), N0.getValueType(), 4795 ExtLoad), 4796 ExtLoad.getValue(1)); 4797 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4798 } 4799 } 4800 4801 if (N0.getOpcode() == ISD::SETCC) { 4802 if (!LegalOperations && VT.isVector()) { 4803 // zext(setcc) -> (and (vsetcc), (1, 1, ...) for vectors. 4804 // Only do this before legalize for now. 4805 EVT N0VT = N0.getOperand(0).getValueType(); 4806 EVT EltVT = VT.getVectorElementType(); 4807 SmallVector<SDValue,8> OneOps(VT.getVectorNumElements(), 4808 DAG.getConstant(1, EltVT)); 4809 if (VT.getSizeInBits() == N0VT.getSizeInBits()) 4810 // We know that the # elements of the results is the same as the 4811 // # elements of the compare (and the # elements of the compare result 4812 // for that matter). Check to see that they are the same size. If so, 4813 // we know that the element size of the sext'd result matches the 4814 // element size of the compare operands. 4815 return DAG.getNode(ISD::AND, SDLoc(N), VT, 4816 DAG.getSetCC(SDLoc(N), VT, N0.getOperand(0), 4817 N0.getOperand(1), 4818 cast<CondCodeSDNode>(N0.getOperand(2))->get()), 4819 DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), VT, 4820 &OneOps[0], OneOps.size())); 4821 4822 // If the desired elements are smaller or larger than the source 4823 // elements we can use a matching integer vector type and then 4824 // truncate/sign extend 4825 EVT MatchingElementType = 4826 EVT::getIntegerVT(*DAG.getContext(), 4827 N0VT.getScalarType().getSizeInBits()); 4828 EVT MatchingVectorType = 4829 EVT::getVectorVT(*DAG.getContext(), MatchingElementType, 4830 N0VT.getVectorNumElements()); 4831 SDValue VsetCC = 4832 DAG.getSetCC(SDLoc(N), MatchingVectorType, N0.getOperand(0), 4833 N0.getOperand(1), 4834 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 4835 return DAG.getNode(ISD::AND, SDLoc(N), VT, 4836 DAG.getSExtOrTrunc(VsetCC, SDLoc(N), VT), 4837 DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), VT, 4838 &OneOps[0], OneOps.size())); 4839 } 4840 4841 // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 4842 SDValue SCC = 4843 SimplifySelectCC(SDLoc(N), N0.getOperand(0), N0.getOperand(1), 4844 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 4845 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 4846 if (SCC.getNode()) return SCC; 4847 } 4848 4849 // (zext (shl (zext x), cst)) -> (shl (zext x), cst) 4850 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL) && 4851 isa<ConstantSDNode>(N0.getOperand(1)) && 4852 N0.getOperand(0).getOpcode() == ISD::ZERO_EXTEND && 4853 N0.hasOneUse()) { 4854 SDValue ShAmt = N0.getOperand(1); 4855 unsigned ShAmtVal = cast<ConstantSDNode>(ShAmt)->getZExtValue(); 4856 if (N0.getOpcode() == ISD::SHL) { 4857 SDValue InnerZExt = N0.getOperand(0); 4858 // If the original shl may be shifting out bits, do not perform this 4859 // transformation. 4860 unsigned KnownZeroBits = InnerZExt.getValueType().getSizeInBits() - 4861 InnerZExt.getOperand(0).getValueType().getSizeInBits(); 4862 if (ShAmtVal > KnownZeroBits) 4863 return SDValue(); 4864 } 4865 4866 SDLoc DL(N); 4867 4868 // Ensure that the shift amount is wide enough for the shifted value. 4869 if (VT.getSizeInBits() >= 256) 4870 ShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, ShAmt); 4871 4872 return DAG.getNode(N0.getOpcode(), DL, VT, 4873 DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0)), 4874 ShAmt); 4875 } 4876 4877 return SDValue(); 4878} 4879 4880SDValue DAGCombiner::visitANY_EXTEND(SDNode *N) { 4881 SDValue N0 = N->getOperand(0); 4882 EVT VT = N->getValueType(0); 4883 4884 // fold (aext c1) -> c1 4885 if (isa<ConstantSDNode>(N0)) 4886 return DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), VT, N0); 4887 // fold (aext (aext x)) -> (aext x) 4888 // fold (aext (zext x)) -> (zext x) 4889 // fold (aext (sext x)) -> (sext x) 4890 if (N0.getOpcode() == ISD::ANY_EXTEND || 4891 N0.getOpcode() == ISD::ZERO_EXTEND || 4892 N0.getOpcode() == ISD::SIGN_EXTEND) 4893 return DAG.getNode(N0.getOpcode(), SDLoc(N), VT, N0.getOperand(0)); 4894 4895 // fold (aext (truncate (load x))) -> (aext (smaller load x)) 4896 // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n))) 4897 if (N0.getOpcode() == ISD::TRUNCATE) { 4898 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 4899 if (NarrowLoad.getNode()) { 4900 SDNode* oye = N0.getNode()->getOperand(0).getNode(); 4901 if (NarrowLoad.getNode() != N0.getNode()) { 4902 CombineTo(N0.getNode(), NarrowLoad); 4903 // CombineTo deleted the truncate, if needed, but not what's under it. 4904 AddToWorkList(oye); 4905 } 4906 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4907 } 4908 } 4909 4910 // fold (aext (truncate x)) 4911 if (N0.getOpcode() == ISD::TRUNCATE) { 4912 SDValue TruncOp = N0.getOperand(0); 4913 if (TruncOp.getValueType() == VT) 4914 return TruncOp; // x iff x size == zext size. 4915 if (TruncOp.getValueType().bitsGT(VT)) 4916 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, TruncOp); 4917 return DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), VT, TruncOp); 4918 } 4919 4920 // Fold (aext (and (trunc x), cst)) -> (and x, cst) 4921 // if the trunc is not free. 4922 if (N0.getOpcode() == ISD::AND && 4923 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 4924 N0.getOperand(1).getOpcode() == ISD::Constant && 4925 !TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(), 4926 N0.getValueType())) { 4927 SDValue X = N0.getOperand(0).getOperand(0); 4928 if (X.getValueType().bitsLT(VT)) { 4929 X = DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), VT, X); 4930 } else if (X.getValueType().bitsGT(VT)) { 4931 X = DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, X); 4932 } 4933 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 4934 Mask = Mask.zext(VT.getSizeInBits()); 4935 return DAG.getNode(ISD::AND, SDLoc(N), VT, 4936 X, DAG.getConstant(Mask, VT)); 4937 } 4938 4939 // fold (aext (load x)) -> (aext (truncate (extload x))) 4940 // None of the supported targets knows how to perform load and any_ext 4941 // on vectors in one instruction. We only perform this transformation on 4942 // scalars. 4943 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() && 4944 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 4945 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) { 4946 bool DoXform = true; 4947 SmallVector<SDNode*, 4> SetCCs; 4948 if (!N0.hasOneUse()) 4949 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ANY_EXTEND, SetCCs, TLI); 4950 if (DoXform) { 4951 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4952 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, SDLoc(N), VT, 4953 LN0->getChain(), 4954 LN0->getBasePtr(), LN0->getPointerInfo(), 4955 N0.getValueType(), 4956 LN0->isVolatile(), LN0->isNonTemporal(), 4957 LN0->getAlignment()); 4958 CombineTo(N, ExtLoad); 4959 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, SDLoc(N0), 4960 N0.getValueType(), ExtLoad); 4961 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 4962 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, SDLoc(N), 4963 ISD::ANY_EXTEND); 4964 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4965 } 4966 } 4967 4968 // fold (aext (zextload x)) -> (aext (truncate (zextload x))) 4969 // fold (aext (sextload x)) -> (aext (truncate (sextload x))) 4970 // fold (aext ( extload x)) -> (aext (truncate (extload x))) 4971 if (N0.getOpcode() == ISD::LOAD && 4972 !ISD::isNON_EXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 4973 N0.hasOneUse()) { 4974 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4975 EVT MemVT = LN0->getMemoryVT(); 4976 SDValue ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), SDLoc(N), 4977 VT, LN0->getChain(), LN0->getBasePtr(), 4978 LN0->getPointerInfo(), MemVT, 4979 LN0->isVolatile(), LN0->isNonTemporal(), 4980 LN0->getAlignment()); 4981 CombineTo(N, ExtLoad); 4982 CombineTo(N0.getNode(), 4983 DAG.getNode(ISD::TRUNCATE, SDLoc(N0), 4984 N0.getValueType(), ExtLoad), 4985 ExtLoad.getValue(1)); 4986 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4987 } 4988 4989 if (N0.getOpcode() == ISD::SETCC) { 4990 // aext(setcc) -> sext_in_reg(vsetcc) for vectors. 4991 // Only do this before legalize for now. 4992 if (VT.isVector() && !LegalOperations) { 4993 EVT N0VT = N0.getOperand(0).getValueType(); 4994 // We know that the # elements of the results is the same as the 4995 // # elements of the compare (and the # elements of the compare result 4996 // for that matter). Check to see that they are the same size. If so, 4997 // we know that the element size of the sext'd result matches the 4998 // element size of the compare operands. 4999 if (VT.getSizeInBits() == N0VT.getSizeInBits()) 5000 return DAG.getSetCC(SDLoc(N), VT, N0.getOperand(0), 5001 N0.getOperand(1), 5002 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 5003 // If the desired elements are smaller or larger than the source 5004 // elements we can use a matching integer vector type and then 5005 // truncate/sign extend 5006 else { 5007 EVT MatchingElementType = 5008 EVT::getIntegerVT(*DAG.getContext(), 5009 N0VT.getScalarType().getSizeInBits()); 5010 EVT MatchingVectorType = 5011 EVT::getVectorVT(*DAG.getContext(), MatchingElementType, 5012 N0VT.getVectorNumElements()); 5013 SDValue VsetCC = 5014 DAG.getSetCC(SDLoc(N), MatchingVectorType, N0.getOperand(0), 5015 N0.getOperand(1), 5016 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 5017 return DAG.getSExtOrTrunc(VsetCC, SDLoc(N), VT); 5018 } 5019 } 5020 5021 // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 5022 SDValue SCC = 5023 SimplifySelectCC(SDLoc(N), N0.getOperand(0), N0.getOperand(1), 5024 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 5025 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 5026 if (SCC.getNode()) 5027 return SCC; 5028 } 5029 5030 return SDValue(); 5031} 5032 5033/// GetDemandedBits - See if the specified operand can be simplified with the 5034/// knowledge that only the bits specified by Mask are used. If so, return the 5035/// simpler operand, otherwise return a null SDValue. 5036SDValue DAGCombiner::GetDemandedBits(SDValue V, const APInt &Mask) { 5037 switch (V.getOpcode()) { 5038 default: break; 5039 case ISD::Constant: { 5040 const ConstantSDNode *CV = cast<ConstantSDNode>(V.getNode()); 5041 assert(CV != 0 && "Const value should be ConstSDNode."); 5042 const APInt &CVal = CV->getAPIntValue(); 5043 APInt NewVal = CVal & Mask; 5044 if (NewVal != CVal) { 5045 return DAG.getConstant(NewVal, V.getValueType()); 5046 } 5047 break; 5048 } 5049 case ISD::OR: 5050 case ISD::XOR: 5051 // If the LHS or RHS don't contribute bits to the or, drop them. 5052 if (DAG.MaskedValueIsZero(V.getOperand(0), Mask)) 5053 return V.getOperand(1); 5054 if (DAG.MaskedValueIsZero(V.getOperand(1), Mask)) 5055 return V.getOperand(0); 5056 break; 5057 case ISD::SRL: 5058 // Only look at single-use SRLs. 5059 if (!V.getNode()->hasOneUse()) 5060 break; 5061 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(V.getOperand(1))) { 5062 // See if we can recursively simplify the LHS. 5063 unsigned Amt = RHSC->getZExtValue(); 5064 5065 // Watch out for shift count overflow though. 5066 if (Amt >= Mask.getBitWidth()) break; 5067 APInt NewMask = Mask << Amt; 5068 SDValue SimplifyLHS = GetDemandedBits(V.getOperand(0), NewMask); 5069 if (SimplifyLHS.getNode()) 5070 return DAG.getNode(ISD::SRL, SDLoc(V), V.getValueType(), 5071 SimplifyLHS, V.getOperand(1)); 5072 } 5073 } 5074 return SDValue(); 5075} 5076 5077/// ReduceLoadWidth - If the result of a wider load is shifted to right of N 5078/// bits and then truncated to a narrower type and where N is a multiple 5079/// of number of bits of the narrower type, transform it to a narrower load 5080/// from address + N / num of bits of new type. If the result is to be 5081/// extended, also fold the extension to form a extending load. 5082SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) { 5083 unsigned Opc = N->getOpcode(); 5084 5085 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD; 5086 SDValue N0 = N->getOperand(0); 5087 EVT VT = N->getValueType(0); 5088 EVT ExtVT = VT; 5089 5090 // This transformation isn't valid for vector loads. 5091 if (VT.isVector()) 5092 return SDValue(); 5093 5094 // Special case: SIGN_EXTEND_INREG is basically truncating to ExtVT then 5095 // extended to VT. 5096 if (Opc == ISD::SIGN_EXTEND_INREG) { 5097 ExtType = ISD::SEXTLOAD; 5098 ExtVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 5099 } else if (Opc == ISD::SRL) { 5100 // Another special-case: SRL is basically zero-extending a narrower value. 5101 ExtType = ISD::ZEXTLOAD; 5102 N0 = SDValue(N, 0); 5103 ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 5104 if (!N01) return SDValue(); 5105 ExtVT = EVT::getIntegerVT(*DAG.getContext(), 5106 VT.getSizeInBits() - N01->getZExtValue()); 5107 } 5108 if (LegalOperations && !TLI.isLoadExtLegal(ExtType, ExtVT)) 5109 return SDValue(); 5110 5111 unsigned EVTBits = ExtVT.getSizeInBits(); 5112 5113 // Do not generate loads of non-round integer types since these can 5114 // be expensive (and would be wrong if the type is not byte sized). 5115 if (!ExtVT.isRound()) 5116 return SDValue(); 5117 5118 unsigned ShAmt = 0; 5119 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) { 5120 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 5121 ShAmt = N01->getZExtValue(); 5122 // Is the shift amount a multiple of size of VT? 5123 if ((ShAmt & (EVTBits-1)) == 0) { 5124 N0 = N0.getOperand(0); 5125 // Is the load width a multiple of size of VT? 5126 if ((N0.getValueType().getSizeInBits() & (EVTBits-1)) != 0) 5127 return SDValue(); 5128 } 5129 5130 // At this point, we must have a load or else we can't do the transform. 5131 if (!isa<LoadSDNode>(N0)) return SDValue(); 5132 5133 // Because a SRL must be assumed to *need* to zero-extend the high bits 5134 // (as opposed to anyext the high bits), we can't combine the zextload 5135 // lowering of SRL and an sextload. 5136 if (cast<LoadSDNode>(N0)->getExtensionType() == ISD::SEXTLOAD) 5137 return SDValue(); 5138 5139 // If the shift amount is larger than the input type then we're not 5140 // accessing any of the loaded bytes. If the load was a zextload/extload 5141 // then the result of the shift+trunc is zero/undef (handled elsewhere). 5142 if (ShAmt >= cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits()) 5143 return SDValue(); 5144 } 5145 } 5146 5147 // If the load is shifted left (and the result isn't shifted back right), 5148 // we can fold the truncate through the shift. 5149 unsigned ShLeftAmt = 0; 5150 if (ShAmt == 0 && N0.getOpcode() == ISD::SHL && N0.hasOneUse() && 5151 ExtVT == VT && TLI.isNarrowingProfitable(N0.getValueType(), VT)) { 5152 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 5153 ShLeftAmt = N01->getZExtValue(); 5154 N0 = N0.getOperand(0); 5155 } 5156 } 5157 5158 // If we haven't found a load, we can't narrow it. Don't transform one with 5159 // multiple uses, this would require adding a new load. 5160 if (!isa<LoadSDNode>(N0) || !N0.hasOneUse()) 5161 return SDValue(); 5162 5163 // Don't change the width of a volatile load. 5164 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 5165 if (LN0->isVolatile()) 5166 return SDValue(); 5167 5168 // Verify that we are actually reducing a load width here. 5169 if (LN0->getMemoryVT().getSizeInBits() < EVTBits) 5170 return SDValue(); 5171 5172 // For the transform to be legal, the load must produce only two values 5173 // (the value loaded and the chain). Don't transform a pre-increment 5174 // load, for example, which produces an extra value. Otherwise the 5175 // transformation is not equivalent, and the downstream logic to replace 5176 // uses gets things wrong. 5177 if (LN0->getNumValues() > 2) 5178 return SDValue(); 5179 5180 EVT PtrType = N0.getOperand(1).getValueType(); 5181 5182 if (PtrType == MVT::Untyped || PtrType.isExtended()) 5183 // It's not possible to generate a constant of extended or untyped type. 5184 return SDValue(); 5185 5186 // For big endian targets, we need to adjust the offset to the pointer to 5187 // load the correct bytes. 5188 if (TLI.isBigEndian()) { 5189 unsigned LVTStoreBits = LN0->getMemoryVT().getStoreSizeInBits(); 5190 unsigned EVTStoreBits = ExtVT.getStoreSizeInBits(); 5191 ShAmt = LVTStoreBits - EVTStoreBits - ShAmt; 5192 } 5193 5194 uint64_t PtrOff = ShAmt / 8; 5195 unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff); 5196 SDValue NewPtr = DAG.getNode(ISD::ADD, SDLoc(LN0), 5197 PtrType, LN0->getBasePtr(), 5198 DAG.getConstant(PtrOff, PtrType)); 5199 AddToWorkList(NewPtr.getNode()); 5200 5201 SDValue Load; 5202 if (ExtType == ISD::NON_EXTLOAD) 5203 Load = DAG.getLoad(VT, SDLoc(N0), LN0->getChain(), NewPtr, 5204 LN0->getPointerInfo().getWithOffset(PtrOff), 5205 LN0->isVolatile(), LN0->isNonTemporal(), 5206 LN0->isInvariant(), NewAlign); 5207 else 5208 Load = DAG.getExtLoad(ExtType, SDLoc(N0), VT, LN0->getChain(),NewPtr, 5209 LN0->getPointerInfo().getWithOffset(PtrOff), 5210 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(), 5211 NewAlign); 5212 5213 // Replace the old load's chain with the new load's chain. 5214 WorkListRemover DeadNodes(*this); 5215 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1)); 5216 5217 // Shift the result left, if we've swallowed a left shift. 5218 SDValue Result = Load; 5219 if (ShLeftAmt != 0) { 5220 EVT ShImmTy = getShiftAmountTy(Result.getValueType()); 5221 if (!isUIntN(ShImmTy.getSizeInBits(), ShLeftAmt)) 5222 ShImmTy = VT; 5223 // If the shift amount is as large as the result size (but, presumably, 5224 // no larger than the source) then the useful bits of the result are 5225 // zero; we can't simply return the shortened shift, because the result 5226 // of that operation is undefined. 5227 if (ShLeftAmt >= VT.getSizeInBits()) 5228 Result = DAG.getConstant(0, VT); 5229 else 5230 Result = DAG.getNode(ISD::SHL, SDLoc(N0), VT, 5231 Result, DAG.getConstant(ShLeftAmt, ShImmTy)); 5232 } 5233 5234 // Return the new loaded value. 5235 return Result; 5236} 5237 5238SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) { 5239 SDValue N0 = N->getOperand(0); 5240 SDValue N1 = N->getOperand(1); 5241 EVT VT = N->getValueType(0); 5242 EVT EVT = cast<VTSDNode>(N1)->getVT(); 5243 unsigned VTBits = VT.getScalarType().getSizeInBits(); 5244 unsigned EVTBits = EVT.getScalarType().getSizeInBits(); 5245 5246 // fold (sext_in_reg c1) -> c1 5247 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF) 5248 return DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N), VT, N0, N1); 5249 5250 // If the input is already sign extended, just drop the extension. 5251 if (DAG.ComputeNumSignBits(N0) >= VTBits-EVTBits+1) 5252 return N0; 5253 5254 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2 5255 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 5256 EVT.bitsLT(cast<VTSDNode>(N0.getOperand(1))->getVT())) { 5257 return DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N), VT, 5258 N0.getOperand(0), N1); 5259 } 5260 5261 // fold (sext_in_reg (sext x)) -> (sext x) 5262 // fold (sext_in_reg (aext x)) -> (sext x) 5263 // if x is small enough. 5264 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) { 5265 SDValue N00 = N0.getOperand(0); 5266 if (N00.getValueType().getScalarType().getSizeInBits() <= EVTBits && 5267 (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND, VT))) 5268 return DAG.getNode(ISD::SIGN_EXTEND, SDLoc(N), VT, N00, N1); 5269 } 5270 5271 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero. 5272 if (DAG.MaskedValueIsZero(N0, APInt::getBitsSet(VTBits, EVTBits-1, EVTBits))) 5273 return DAG.getZeroExtendInReg(N0, SDLoc(N), EVT); 5274 5275 // fold operands of sext_in_reg based on knowledge that the top bits are not 5276 // demanded. 5277 if (SimplifyDemandedBits(SDValue(N, 0))) 5278 return SDValue(N, 0); 5279 5280 // fold (sext_in_reg (load x)) -> (smaller sextload x) 5281 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits)) 5282 SDValue NarrowLoad = ReduceLoadWidth(N); 5283 if (NarrowLoad.getNode()) 5284 return NarrowLoad; 5285 5286 // fold (sext_in_reg (srl X, 24), i8) -> (sra X, 24) 5287 // fold (sext_in_reg (srl X, 23), i8) -> (sra X, 23) iff possible. 5288 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above. 5289 if (N0.getOpcode() == ISD::SRL) { 5290 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 5291 if (ShAmt->getZExtValue()+EVTBits <= VTBits) { 5292 // We can turn this into an SRA iff the input to the SRL is already sign 5293 // extended enough. 5294 unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0)); 5295 if (VTBits-(ShAmt->getZExtValue()+EVTBits) < InSignBits) 5296 return DAG.getNode(ISD::SRA, SDLoc(N), VT, 5297 N0.getOperand(0), N0.getOperand(1)); 5298 } 5299 } 5300 5301 // fold (sext_inreg (extload x)) -> (sextload x) 5302 if (ISD::isEXTLoad(N0.getNode()) && 5303 ISD::isUNINDEXEDLoad(N0.getNode()) && 5304 EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 5305 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 5306 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) { 5307 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 5308 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, SDLoc(N), VT, 5309 LN0->getChain(), 5310 LN0->getBasePtr(), LN0->getPointerInfo(), 5311 EVT, 5312 LN0->isVolatile(), LN0->isNonTemporal(), 5313 LN0->getAlignment()); 5314 CombineTo(N, ExtLoad); 5315 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 5316 AddToWorkList(ExtLoad.getNode()); 5317 return SDValue(N, 0); // Return N so it doesn't get rechecked! 5318 } 5319 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use 5320 if (ISD::isZEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 5321 N0.hasOneUse() && 5322 EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 5323 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 5324 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) { 5325 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 5326 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, SDLoc(N), VT, 5327 LN0->getChain(), 5328 LN0->getBasePtr(), LN0->getPointerInfo(), 5329 EVT, 5330 LN0->isVolatile(), LN0->isNonTemporal(), 5331 LN0->getAlignment()); 5332 CombineTo(N, ExtLoad); 5333 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 5334 return SDValue(N, 0); // Return N so it doesn't get rechecked! 5335 } 5336 5337 // Form (sext_inreg (bswap >> 16)) or (sext_inreg (rotl (bswap) 16)) 5338 if (EVTBits <= 16 && N0.getOpcode() == ISD::OR) { 5339 SDValue BSwap = MatchBSwapHWordLow(N0.getNode(), N0.getOperand(0), 5340 N0.getOperand(1), false); 5341 if (BSwap.getNode() != 0) 5342 return DAG.getNode(ISD::SIGN_EXTEND_INREG, SDLoc(N), VT, 5343 BSwap, N1); 5344 } 5345 5346 return SDValue(); 5347} 5348 5349SDValue DAGCombiner::visitTRUNCATE(SDNode *N) { 5350 SDValue N0 = N->getOperand(0); 5351 EVT VT = N->getValueType(0); 5352 bool isLE = TLI.isLittleEndian(); 5353 5354 // noop truncate 5355 if (N0.getValueType() == N->getValueType(0)) 5356 return N0; 5357 // fold (truncate c1) -> c1 5358 if (isa<ConstantSDNode>(N0)) 5359 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, N0); 5360 // fold (truncate (truncate x)) -> (truncate x) 5361 if (N0.getOpcode() == ISD::TRUNCATE) 5362 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, N0.getOperand(0)); 5363 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x 5364 if (N0.getOpcode() == ISD::ZERO_EXTEND || 5365 N0.getOpcode() == ISD::SIGN_EXTEND || 5366 N0.getOpcode() == ISD::ANY_EXTEND) { 5367 if (N0.getOperand(0).getValueType().bitsLT(VT)) 5368 // if the source is smaller than the dest, we still need an extend 5369 return DAG.getNode(N0.getOpcode(), SDLoc(N), VT, 5370 N0.getOperand(0)); 5371 if (N0.getOperand(0).getValueType().bitsGT(VT)) 5372 // if the source is larger than the dest, than we just need the truncate 5373 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, N0.getOperand(0)); 5374 // if the source and dest are the same type, we can drop both the extend 5375 // and the truncate. 5376 return N0.getOperand(0); 5377 } 5378 5379 // Fold extract-and-trunc into a narrow extract. For example: 5380 // i64 x = EXTRACT_VECTOR_ELT(v2i64 val, i32 1) 5381 // i32 y = TRUNCATE(i64 x) 5382 // -- becomes -- 5383 // v16i8 b = BITCAST (v2i64 val) 5384 // i8 x = EXTRACT_VECTOR_ELT(v16i8 b, i32 8) 5385 // 5386 // Note: We only run this optimization after type legalization (which often 5387 // creates this pattern) and before operation legalization after which 5388 // we need to be more careful about the vector instructions that we generate. 5389 if (N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT && 5390 LegalTypes && !LegalOperations && N0->hasOneUse()) { 5391 5392 EVT VecTy = N0.getOperand(0).getValueType(); 5393 EVT ExTy = N0.getValueType(); 5394 EVT TrTy = N->getValueType(0); 5395 5396 unsigned NumElem = VecTy.getVectorNumElements(); 5397 unsigned SizeRatio = ExTy.getSizeInBits()/TrTy.getSizeInBits(); 5398 5399 EVT NVT = EVT::getVectorVT(*DAG.getContext(), TrTy, SizeRatio * NumElem); 5400 assert(NVT.getSizeInBits() == VecTy.getSizeInBits() && "Invalid Size"); 5401 5402 SDValue EltNo = N0->getOperand(1); 5403 if (isa<ConstantSDNode>(EltNo) && isTypeLegal(NVT)) { 5404 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 5405 EVT IndexTy = N0->getOperand(1).getValueType(); 5406 int Index = isLE ? (Elt*SizeRatio) : (Elt*SizeRatio + (SizeRatio-1)); 5407 5408 SDValue V = DAG.getNode(ISD::BITCAST, SDLoc(N), 5409 NVT, N0.getOperand(0)); 5410 5411 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, 5412 SDLoc(N), TrTy, V, 5413 DAG.getConstant(Index, IndexTy)); 5414 } 5415 } 5416 5417 // Fold a series of buildvector, bitcast, and truncate if possible. 5418 // For example fold 5419 // (2xi32 trunc (bitcast ((4xi32)buildvector x, x, y, y) 2xi64)) to 5420 // (2xi32 (buildvector x, y)). 5421 if (Level == AfterLegalizeVectorOps && VT.isVector() && 5422 N0.getOpcode() == ISD::BITCAST && N0.hasOneUse() && 5423 N0.getOperand(0).getOpcode() == ISD::BUILD_VECTOR && 5424 N0.getOperand(0).hasOneUse()) { 5425 5426 SDValue BuildVect = N0.getOperand(0); 5427 EVT BuildVectEltTy = BuildVect.getValueType().getVectorElementType(); 5428 EVT TruncVecEltTy = VT.getVectorElementType(); 5429 5430 // Check that the element types match. 5431 if (BuildVectEltTy == TruncVecEltTy) { 5432 // Now we only need to compute the offset of the truncated elements. 5433 unsigned BuildVecNumElts = BuildVect.getNumOperands(); 5434 unsigned TruncVecNumElts = VT.getVectorNumElements(); 5435 unsigned TruncEltOffset = BuildVecNumElts / TruncVecNumElts; 5436 5437 assert((BuildVecNumElts % TruncVecNumElts) == 0 && 5438 "Invalid number of elements"); 5439 5440 SmallVector<SDValue, 8> Opnds; 5441 for (unsigned i = 0, e = BuildVecNumElts; i != e; i += TruncEltOffset) 5442 Opnds.push_back(BuildVect.getOperand(i)); 5443 5444 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), VT, &Opnds[0], 5445 Opnds.size()); 5446 } 5447 } 5448 5449 // See if we can simplify the input to this truncate through knowledge that 5450 // only the low bits are being used. 5451 // For example "trunc (or (shl x, 8), y)" // -> trunc y 5452 // Currently we only perform this optimization on scalars because vectors 5453 // may have different active low bits. 5454 if (!VT.isVector()) { 5455 SDValue Shorter = 5456 GetDemandedBits(N0, APInt::getLowBitsSet(N0.getValueSizeInBits(), 5457 VT.getSizeInBits())); 5458 if (Shorter.getNode()) 5459 return DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, Shorter); 5460 } 5461 // fold (truncate (load x)) -> (smaller load x) 5462 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits)) 5463 if (!LegalTypes || TLI.isTypeDesirableForOp(N0.getOpcode(), VT)) { 5464 SDValue Reduced = ReduceLoadWidth(N); 5465 if (Reduced.getNode()) 5466 return Reduced; 5467 } 5468 // fold (trunc (concat ... x ...)) -> (concat ..., (trunc x), ...)), 5469 // where ... are all 'undef'. 5470 if (N0.getOpcode() == ISD::CONCAT_VECTORS && !LegalTypes) { 5471 SmallVector<EVT, 8> VTs; 5472 SDValue V; 5473 unsigned Idx = 0; 5474 unsigned NumDefs = 0; 5475 5476 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i) { 5477 SDValue X = N0.getOperand(i); 5478 if (X.getOpcode() != ISD::UNDEF) { 5479 V = X; 5480 Idx = i; 5481 NumDefs++; 5482 } 5483 // Stop if more than one members are non-undef. 5484 if (NumDefs > 1) 5485 break; 5486 VTs.push_back(EVT::getVectorVT(*DAG.getContext(), 5487 VT.getVectorElementType(), 5488 X.getValueType().getVectorNumElements())); 5489 } 5490 5491 if (NumDefs == 0) 5492 return DAG.getUNDEF(VT); 5493 5494 if (NumDefs == 1) { 5495 assert(V.getNode() && "The single defined operand is empty!"); 5496 SmallVector<SDValue, 8> Opnds; 5497 for (unsigned i = 0, e = VTs.size(); i != e; ++i) { 5498 if (i != Idx) { 5499 Opnds.push_back(DAG.getUNDEF(VTs[i])); 5500 continue; 5501 } 5502 SDValue NV = DAG.getNode(ISD::TRUNCATE, SDLoc(V), VTs[i], V); 5503 AddToWorkList(NV.getNode()); 5504 Opnds.push_back(NV); 5505 } 5506 return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(N), VT, 5507 &Opnds[0], Opnds.size()); 5508 } 5509 } 5510 5511 // Simplify the operands using demanded-bits information. 5512 if (!VT.isVector() && 5513 SimplifyDemandedBits(SDValue(N, 0))) 5514 return SDValue(N, 0); 5515 5516 return SDValue(); 5517} 5518 5519static SDNode *getBuildPairElt(SDNode *N, unsigned i) { 5520 SDValue Elt = N->getOperand(i); 5521 if (Elt.getOpcode() != ISD::MERGE_VALUES) 5522 return Elt.getNode(); 5523 return Elt.getOperand(Elt.getResNo()).getNode(); 5524} 5525 5526/// CombineConsecutiveLoads - build_pair (load, load) -> load 5527/// if load locations are consecutive. 5528SDValue DAGCombiner::CombineConsecutiveLoads(SDNode *N, EVT VT) { 5529 assert(N->getOpcode() == ISD::BUILD_PAIR); 5530 5531 LoadSDNode *LD1 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 0)); 5532 LoadSDNode *LD2 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 1)); 5533 if (!LD1 || !LD2 || !ISD::isNON_EXTLoad(LD1) || !LD1->hasOneUse() || 5534 LD1->getPointerInfo().getAddrSpace() != 5535 LD2->getPointerInfo().getAddrSpace()) 5536 return SDValue(); 5537 EVT LD1VT = LD1->getValueType(0); 5538 5539 if (ISD::isNON_EXTLoad(LD2) && 5540 LD2->hasOneUse() && 5541 // If both are volatile this would reduce the number of volatile loads. 5542 // If one is volatile it might be ok, but play conservative and bail out. 5543 !LD1->isVolatile() && 5544 !LD2->isVolatile() && 5545 DAG.isConsecutiveLoad(LD2, LD1, LD1VT.getSizeInBits()/8, 1)) { 5546 unsigned Align = LD1->getAlignment(); 5547 unsigned NewAlign = TLI.getDataLayout()-> 5548 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext())); 5549 5550 if (NewAlign <= Align && 5551 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) 5552 return DAG.getLoad(VT, SDLoc(N), LD1->getChain(), 5553 LD1->getBasePtr(), LD1->getPointerInfo(), 5554 false, false, false, Align); 5555 } 5556 5557 return SDValue(); 5558} 5559 5560SDValue DAGCombiner::visitBITCAST(SDNode *N) { 5561 SDValue N0 = N->getOperand(0); 5562 EVT VT = N->getValueType(0); 5563 5564 // If the input is a BUILD_VECTOR with all constant elements, fold this now. 5565 // Only do this before legalize, since afterward the target may be depending 5566 // on the bitconvert. 5567 // First check to see if this is all constant. 5568 if (!LegalTypes && 5569 N0.getOpcode() == ISD::BUILD_VECTOR && N0.getNode()->hasOneUse() && 5570 VT.isVector()) { 5571 bool isSimple = true; 5572 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i) 5573 if (N0.getOperand(i).getOpcode() != ISD::UNDEF && 5574 N0.getOperand(i).getOpcode() != ISD::Constant && 5575 N0.getOperand(i).getOpcode() != ISD::ConstantFP) { 5576 isSimple = false; 5577 break; 5578 } 5579 5580 EVT DestEltVT = N->getValueType(0).getVectorElementType(); 5581 assert(!DestEltVT.isVector() && 5582 "Element type of vector ValueType must not be vector!"); 5583 if (isSimple) 5584 return ConstantFoldBITCASTofBUILD_VECTOR(N0.getNode(), DestEltVT); 5585 } 5586 5587 // If the input is a constant, let getNode fold it. 5588 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) { 5589 SDValue Res = DAG.getNode(ISD::BITCAST, SDLoc(N), VT, N0); 5590 if (Res.getNode() != N) { 5591 if (!LegalOperations || 5592 TLI.isOperationLegal(Res.getNode()->getOpcode(), VT)) 5593 return Res; 5594 5595 // Folding it resulted in an illegal node, and it's too late to 5596 // do that. Clean up the old node and forego the transformation. 5597 // Ideally this won't happen very often, because instcombine 5598 // and the earlier dagcombine runs (where illegal nodes are 5599 // permitted) should have folded most of them already. 5600 DAG.DeleteNode(Res.getNode()); 5601 } 5602 } 5603 5604 // (conv (conv x, t1), t2) -> (conv x, t2) 5605 if (N0.getOpcode() == ISD::BITCAST) 5606 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, 5607 N0.getOperand(0)); 5608 5609 // fold (conv (load x)) -> (load (conv*)x) 5610 // If the resultant load doesn't need a higher alignment than the original! 5611 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() && 5612 // Do not change the width of a volatile load. 5613 !cast<LoadSDNode>(N0)->isVolatile() && 5614 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) { 5615 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 5616 unsigned Align = TLI.getDataLayout()-> 5617 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext())); 5618 unsigned OrigAlign = LN0->getAlignment(); 5619 5620 if (Align <= OrigAlign) { 5621 SDValue Load = DAG.getLoad(VT, SDLoc(N), LN0->getChain(), 5622 LN0->getBasePtr(), LN0->getPointerInfo(), 5623 LN0->isVolatile(), LN0->isNonTemporal(), 5624 LN0->isInvariant(), OrigAlign); 5625 AddToWorkList(N); 5626 CombineTo(N0.getNode(), 5627 DAG.getNode(ISD::BITCAST, SDLoc(N0), 5628 N0.getValueType(), Load), 5629 Load.getValue(1)); 5630 return Load; 5631 } 5632 } 5633 5634 // fold (bitconvert (fneg x)) -> (xor (bitconvert x), signbit) 5635 // fold (bitconvert (fabs x)) -> (and (bitconvert x), (not signbit)) 5636 // This often reduces constant pool loads. 5637 if (((N0.getOpcode() == ISD::FNEG && !TLI.isFNegFree(VT)) || 5638 (N0.getOpcode() == ISD::FABS && !TLI.isFAbsFree(VT))) && 5639 N0.getNode()->hasOneUse() && VT.isInteger() && 5640 !VT.isVector() && !N0.getValueType().isVector()) { 5641 SDValue NewConv = DAG.getNode(ISD::BITCAST, SDLoc(N0), VT, 5642 N0.getOperand(0)); 5643 AddToWorkList(NewConv.getNode()); 5644 5645 APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); 5646 if (N0.getOpcode() == ISD::FNEG) 5647 return DAG.getNode(ISD::XOR, SDLoc(N), VT, 5648 NewConv, DAG.getConstant(SignBit, VT)); 5649 assert(N0.getOpcode() == ISD::FABS); 5650 return DAG.getNode(ISD::AND, SDLoc(N), VT, 5651 NewConv, DAG.getConstant(~SignBit, VT)); 5652 } 5653 5654 // fold (bitconvert (fcopysign cst, x)) -> 5655 // (or (and (bitconvert x), sign), (and cst, (not sign))) 5656 // Note that we don't handle (copysign x, cst) because this can always be 5657 // folded to an fneg or fabs. 5658 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse() && 5659 isa<ConstantFPSDNode>(N0.getOperand(0)) && 5660 VT.isInteger() && !VT.isVector()) { 5661 unsigned OrigXWidth = N0.getOperand(1).getValueType().getSizeInBits(); 5662 EVT IntXVT = EVT::getIntegerVT(*DAG.getContext(), OrigXWidth); 5663 if (isTypeLegal(IntXVT)) { 5664 SDValue X = DAG.getNode(ISD::BITCAST, SDLoc(N0), 5665 IntXVT, N0.getOperand(1)); 5666 AddToWorkList(X.getNode()); 5667 5668 // If X has a different width than the result/lhs, sext it or truncate it. 5669 unsigned VTWidth = VT.getSizeInBits(); 5670 if (OrigXWidth < VTWidth) { 5671 X = DAG.getNode(ISD::SIGN_EXTEND, SDLoc(N), VT, X); 5672 AddToWorkList(X.getNode()); 5673 } else if (OrigXWidth > VTWidth) { 5674 // To get the sign bit in the right place, we have to shift it right 5675 // before truncating. 5676 X = DAG.getNode(ISD::SRL, SDLoc(X), 5677 X.getValueType(), X, 5678 DAG.getConstant(OrigXWidth-VTWidth, X.getValueType())); 5679 AddToWorkList(X.getNode()); 5680 X = DAG.getNode(ISD::TRUNCATE, SDLoc(X), VT, X); 5681 AddToWorkList(X.getNode()); 5682 } 5683 5684 APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); 5685 X = DAG.getNode(ISD::AND, SDLoc(X), VT, 5686 X, DAG.getConstant(SignBit, VT)); 5687 AddToWorkList(X.getNode()); 5688 5689 SDValue Cst = DAG.getNode(ISD::BITCAST, SDLoc(N0), 5690 VT, N0.getOperand(0)); 5691 Cst = DAG.getNode(ISD::AND, SDLoc(Cst), VT, 5692 Cst, DAG.getConstant(~SignBit, VT)); 5693 AddToWorkList(Cst.getNode()); 5694 5695 return DAG.getNode(ISD::OR, SDLoc(N), VT, X, Cst); 5696 } 5697 } 5698 5699 // bitconvert(build_pair(ld, ld)) -> ld iff load locations are consecutive. 5700 if (N0.getOpcode() == ISD::BUILD_PAIR) { 5701 SDValue CombineLD = CombineConsecutiveLoads(N0.getNode(), VT); 5702 if (CombineLD.getNode()) 5703 return CombineLD; 5704 } 5705 5706 return SDValue(); 5707} 5708 5709SDValue DAGCombiner::visitBUILD_PAIR(SDNode *N) { 5710 EVT VT = N->getValueType(0); 5711 return CombineConsecutiveLoads(N, VT); 5712} 5713 5714/// ConstantFoldBITCASTofBUILD_VECTOR - We know that BV is a build_vector 5715/// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the 5716/// destination element value type. 5717SDValue DAGCombiner:: 5718ConstantFoldBITCASTofBUILD_VECTOR(SDNode *BV, EVT DstEltVT) { 5719 EVT SrcEltVT = BV->getValueType(0).getVectorElementType(); 5720 5721 // If this is already the right type, we're done. 5722 if (SrcEltVT == DstEltVT) return SDValue(BV, 0); 5723 5724 unsigned SrcBitSize = SrcEltVT.getSizeInBits(); 5725 unsigned DstBitSize = DstEltVT.getSizeInBits(); 5726 5727 // If this is a conversion of N elements of one type to N elements of another 5728 // type, convert each element. This handles FP<->INT cases. 5729 if (SrcBitSize == DstBitSize) { 5730 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, 5731 BV->getValueType(0).getVectorNumElements()); 5732 5733 // Due to the FP element handling below calling this routine recursively, 5734 // we can end up with a scalar-to-vector node here. 5735 if (BV->getOpcode() == ISD::SCALAR_TO_VECTOR) 5736 return DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(BV), VT, 5737 DAG.getNode(ISD::BITCAST, SDLoc(BV), 5738 DstEltVT, BV->getOperand(0))); 5739 5740 SmallVector<SDValue, 8> Ops; 5741 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 5742 SDValue Op = BV->getOperand(i); 5743 // If the vector element type is not legal, the BUILD_VECTOR operands 5744 // are promoted and implicitly truncated. Make that explicit here. 5745 if (Op.getValueType() != SrcEltVT) 5746 Op = DAG.getNode(ISD::TRUNCATE, SDLoc(BV), SrcEltVT, Op); 5747 Ops.push_back(DAG.getNode(ISD::BITCAST, SDLoc(BV), 5748 DstEltVT, Op)); 5749 AddToWorkList(Ops.back().getNode()); 5750 } 5751 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(BV), VT, 5752 &Ops[0], Ops.size()); 5753 } 5754 5755 // Otherwise, we're growing or shrinking the elements. To avoid having to 5756 // handle annoying details of growing/shrinking FP values, we convert them to 5757 // int first. 5758 if (SrcEltVT.isFloatingPoint()) { 5759 // Convert the input float vector to a int vector where the elements are the 5760 // same sizes. 5761 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!"); 5762 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), SrcEltVT.getSizeInBits()); 5763 BV = ConstantFoldBITCASTofBUILD_VECTOR(BV, IntVT).getNode(); 5764 SrcEltVT = IntVT; 5765 } 5766 5767 // Now we know the input is an integer vector. If the output is a FP type, 5768 // convert to integer first, then to FP of the right size. 5769 if (DstEltVT.isFloatingPoint()) { 5770 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!"); 5771 EVT TmpVT = EVT::getIntegerVT(*DAG.getContext(), DstEltVT.getSizeInBits()); 5772 SDNode *Tmp = ConstantFoldBITCASTofBUILD_VECTOR(BV, TmpVT).getNode(); 5773 5774 // Next, convert to FP elements of the same size. 5775 return ConstantFoldBITCASTofBUILD_VECTOR(Tmp, DstEltVT); 5776 } 5777 5778 // Okay, we know the src/dst types are both integers of differing types. 5779 // Handling growing first. 5780 assert(SrcEltVT.isInteger() && DstEltVT.isInteger()); 5781 if (SrcBitSize < DstBitSize) { 5782 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize; 5783 5784 SmallVector<SDValue, 8> Ops; 5785 for (unsigned i = 0, e = BV->getNumOperands(); i != e; 5786 i += NumInputsPerOutput) { 5787 bool isLE = TLI.isLittleEndian(); 5788 APInt NewBits = APInt(DstBitSize, 0); 5789 bool EltIsUndef = true; 5790 for (unsigned j = 0; j != NumInputsPerOutput; ++j) { 5791 // Shift the previously computed bits over. 5792 NewBits <<= SrcBitSize; 5793 SDValue Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j)); 5794 if (Op.getOpcode() == ISD::UNDEF) continue; 5795 EltIsUndef = false; 5796 5797 NewBits |= cast<ConstantSDNode>(Op)->getAPIntValue(). 5798 zextOrTrunc(SrcBitSize).zext(DstBitSize); 5799 } 5800 5801 if (EltIsUndef) 5802 Ops.push_back(DAG.getUNDEF(DstEltVT)); 5803 else 5804 Ops.push_back(DAG.getConstant(NewBits, DstEltVT)); 5805 } 5806 5807 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, Ops.size()); 5808 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(BV), VT, 5809 &Ops[0], Ops.size()); 5810 } 5811 5812 // Finally, this must be the case where we are shrinking elements: each input 5813 // turns into multiple outputs. 5814 bool isS2V = ISD::isScalarToVector(BV); 5815 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize; 5816 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, 5817 NumOutputsPerInput*BV->getNumOperands()); 5818 SmallVector<SDValue, 8> Ops; 5819 5820 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 5821 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) { 5822 for (unsigned j = 0; j != NumOutputsPerInput; ++j) 5823 Ops.push_back(DAG.getUNDEF(DstEltVT)); 5824 continue; 5825 } 5826 5827 APInt OpVal = cast<ConstantSDNode>(BV->getOperand(i))-> 5828 getAPIntValue().zextOrTrunc(SrcBitSize); 5829 5830 for (unsigned j = 0; j != NumOutputsPerInput; ++j) { 5831 APInt ThisVal = OpVal.trunc(DstBitSize); 5832 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT)); 5833 if (isS2V && i == 0 && j == 0 && ThisVal.zext(SrcBitSize) == OpVal) 5834 // Simply turn this into a SCALAR_TO_VECTOR of the new type. 5835 return DAG.getNode(ISD::SCALAR_TO_VECTOR, SDLoc(BV), VT, 5836 Ops[0]); 5837 OpVal = OpVal.lshr(DstBitSize); 5838 } 5839 5840 // For big endian targets, swap the order of the pieces of each element. 5841 if (TLI.isBigEndian()) 5842 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end()); 5843 } 5844 5845 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(BV), VT, 5846 &Ops[0], Ops.size()); 5847} 5848 5849SDValue DAGCombiner::visitFADD(SDNode *N) { 5850 SDValue N0 = N->getOperand(0); 5851 SDValue N1 = N->getOperand(1); 5852 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5853 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 5854 EVT VT = N->getValueType(0); 5855 5856 // fold vector ops 5857 if (VT.isVector()) { 5858 SDValue FoldedVOp = SimplifyVBinOp(N); 5859 if (FoldedVOp.getNode()) return FoldedVOp; 5860 } 5861 5862 // fold (fadd c1, c2) -> c1 + c2 5863 if (N0CFP && N1CFP) 5864 return DAG.getNode(ISD::FADD, SDLoc(N), VT, N0, N1); 5865 // canonicalize constant to RHS 5866 if (N0CFP && !N1CFP) 5867 return DAG.getNode(ISD::FADD, SDLoc(N), VT, N1, N0); 5868 // fold (fadd A, 0) -> A 5869 if (DAG.getTarget().Options.UnsafeFPMath && N1CFP && 5870 N1CFP->getValueAPF().isZero()) 5871 return N0; 5872 // fold (fadd A, (fneg B)) -> (fsub A, B) 5873 if ((!LegalOperations || TLI.isOperationLegalOrCustom(ISD::FSUB, VT)) && 5874 isNegatibleForFree(N1, LegalOperations, TLI, &DAG.getTarget().Options) == 2) 5875 return DAG.getNode(ISD::FSUB, SDLoc(N), VT, N0, 5876 GetNegatedExpression(N1, DAG, LegalOperations)); 5877 // fold (fadd (fneg A), B) -> (fsub B, A) 5878 if ((!LegalOperations || TLI.isOperationLegalOrCustom(ISD::FSUB, VT)) && 5879 isNegatibleForFree(N0, LegalOperations, TLI, &DAG.getTarget().Options) == 2) 5880 return DAG.getNode(ISD::FSUB, SDLoc(N), VT, N1, 5881 GetNegatedExpression(N0, DAG, LegalOperations)); 5882 5883 // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2)) 5884 if (DAG.getTarget().Options.UnsafeFPMath && N1CFP && 5885 N0.getOpcode() == ISD::FADD && N0.getNode()->hasOneUse() && 5886 isa<ConstantFPSDNode>(N0.getOperand(1))) 5887 return DAG.getNode(ISD::FADD, SDLoc(N), VT, N0.getOperand(0), 5888 DAG.getNode(ISD::FADD, SDLoc(N), VT, 5889 N0.getOperand(1), N1)); 5890 5891 // No FP constant should be created after legalization as Instruction 5892 // Selection pass has hard time in dealing with FP constant. 5893 // 5894 // We don't need test this condition for transformation like following, as 5895 // the DAG being transformed implies it is legal to take FP constant as 5896 // operand. 5897 // 5898 // (fadd (fmul c, x), x) -> (fmul c+1, x) 5899 // 5900 bool AllowNewFpConst = (Level < AfterLegalizeDAG); 5901 5902 // If allow, fold (fadd (fneg x), x) -> 0.0 5903 if (AllowNewFpConst && DAG.getTarget().Options.UnsafeFPMath && 5904 N0.getOpcode() == ISD::FNEG && N0.getOperand(0) == N1) { 5905 return DAG.getConstantFP(0.0, VT); 5906 } 5907 5908 // If allow, fold (fadd x, (fneg x)) -> 0.0 5909 if (AllowNewFpConst && DAG.getTarget().Options.UnsafeFPMath && 5910 N1.getOpcode() == ISD::FNEG && N1.getOperand(0) == N0) { 5911 return DAG.getConstantFP(0.0, VT); 5912 } 5913 5914 // In unsafe math mode, we can fold chains of FADD's of the same value 5915 // into multiplications. This transform is not safe in general because 5916 // we are reducing the number of rounding steps. 5917 if (DAG.getTarget().Options.UnsafeFPMath && 5918 TLI.isOperationLegalOrCustom(ISD::FMUL, VT) && 5919 !N0CFP && !N1CFP) { 5920 if (N0.getOpcode() == ISD::FMUL) { 5921 ConstantFPSDNode *CFP00 = dyn_cast<ConstantFPSDNode>(N0.getOperand(0)); 5922 ConstantFPSDNode *CFP01 = dyn_cast<ConstantFPSDNode>(N0.getOperand(1)); 5923 5924 // (fadd (fmul c, x), x) -> (fmul x, c+1) 5925 if (CFP00 && !CFP01 && N0.getOperand(1) == N1) { 5926 SDValue NewCFP = DAG.getNode(ISD::FADD, SDLoc(N), VT, 5927 SDValue(CFP00, 0), 5928 DAG.getConstantFP(1.0, VT)); 5929 return DAG.getNode(ISD::FMUL, SDLoc(N), VT, 5930 N1, NewCFP); 5931 } 5932 5933 // (fadd (fmul x, c), x) -> (fmul x, c+1) 5934 if (CFP01 && !CFP00 && N0.getOperand(0) == N1) { 5935 SDValue NewCFP = DAG.getNode(ISD::FADD, SDLoc(N), VT, 5936 SDValue(CFP01, 0), 5937 DAG.getConstantFP(1.0, VT)); 5938 return DAG.getNode(ISD::FMUL, SDLoc(N), VT, 5939 N1, NewCFP); 5940 } 5941 5942 // (fadd (fmul c, x), (fadd x, x)) -> (fmul x, c+2) 5943 if (CFP00 && !CFP01 && N1.getOpcode() == ISD::FADD && 5944 N1.getOperand(0) == N1.getOperand(1) && 5945 N0.getOperand(1) == N1.getOperand(0)) { 5946 SDValue NewCFP = DAG.getNode(ISD::FADD, SDLoc(N), VT, 5947 SDValue(CFP00, 0), 5948 DAG.getConstantFP(2.0, VT)); 5949 return DAG.getNode(ISD::FMUL, SDLoc(N), VT, 5950 N0.getOperand(1), NewCFP); 5951 } 5952 5953 // (fadd (fmul x, c), (fadd x, x)) -> (fmul x, c+2) 5954 if (CFP01 && !CFP00 && N1.getOpcode() == ISD::FADD && 5955 N1.getOperand(0) == N1.getOperand(1) && 5956 N0.getOperand(0) == N1.getOperand(0)) { 5957 SDValue NewCFP = DAG.getNode(ISD::FADD, SDLoc(N), VT, 5958 SDValue(CFP01, 0), 5959 DAG.getConstantFP(2.0, VT)); 5960 return DAG.getNode(ISD::FMUL, SDLoc(N), VT, 5961 N0.getOperand(0), NewCFP); 5962 } 5963 } 5964 5965 if (N1.getOpcode() == ISD::FMUL) { 5966 ConstantFPSDNode *CFP10 = dyn_cast<ConstantFPSDNode>(N1.getOperand(0)); 5967 ConstantFPSDNode *CFP11 = dyn_cast<ConstantFPSDNode>(N1.getOperand(1)); 5968 5969 // (fadd x, (fmul c, x)) -> (fmul x, c+1) 5970 if (CFP10 && !CFP11 && N1.getOperand(1) == N0) { 5971 SDValue NewCFP = DAG.getNode(ISD::FADD, SDLoc(N), VT, 5972 SDValue(CFP10, 0), 5973 DAG.getConstantFP(1.0, VT)); 5974 return DAG.getNode(ISD::FMUL, SDLoc(N), VT, 5975 N0, NewCFP); 5976 } 5977 5978 // (fadd x, (fmul x, c)) -> (fmul x, c+1) 5979 if (CFP11 && !CFP10 && N1.getOperand(0) == N0) { 5980 SDValue NewCFP = DAG.getNode(ISD::FADD, SDLoc(N), VT, 5981 SDValue(CFP11, 0), 5982 DAG.getConstantFP(1.0, VT)); 5983 return DAG.getNode(ISD::FMUL, SDLoc(N), VT, 5984 N0, NewCFP); 5985 } 5986 5987 5988 // (fadd (fadd x, x), (fmul c, x)) -> (fmul x, c+2) 5989 if (CFP10 && !CFP11 && N0.getOpcode() == ISD::FADD && 5990 N0.getOperand(0) == N0.getOperand(1) && 5991 N1.getOperand(1) == N0.getOperand(0)) { 5992 SDValue NewCFP = DAG.getNode(ISD::FADD, SDLoc(N), VT, 5993 SDValue(CFP10, 0), 5994 DAG.getConstantFP(2.0, VT)); 5995 return DAG.getNode(ISD::FMUL, SDLoc(N), VT, 5996 N1.getOperand(1), NewCFP); 5997 } 5998 5999 // (fadd (fadd x, x), (fmul x, c)) -> (fmul x, c+2) 6000 if (CFP11 && !CFP10 && N0.getOpcode() == ISD::FADD && 6001 N0.getOperand(0) == N0.getOperand(1) && 6002 N1.getOperand(0) == N0.getOperand(0)) { 6003 SDValue NewCFP = DAG.getNode(ISD::FADD, SDLoc(N), VT, 6004 SDValue(CFP11, 0), 6005 DAG.getConstantFP(2.0, VT)); 6006 return DAG.getNode(ISD::FMUL, SDLoc(N), VT, 6007 N1.getOperand(0), NewCFP); 6008 } 6009 } 6010 6011 if (N0.getOpcode() == ISD::FADD && AllowNewFpConst) { 6012 ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N0.getOperand(0)); 6013 // (fadd (fadd x, x), x) -> (fmul x, 3.0) 6014 if (!CFP && N0.getOperand(0) == N0.getOperand(1) && 6015 (N0.getOperand(0) == N1)) { 6016 return DAG.getNode(ISD::FMUL, SDLoc(N), VT, 6017 N1, DAG.getConstantFP(3.0, VT)); 6018 } 6019 } 6020 6021 if (N1.getOpcode() == ISD::FADD && AllowNewFpConst) { 6022 ConstantFPSDNode *CFP10 = dyn_cast<ConstantFPSDNode>(N1.getOperand(0)); 6023 // (fadd x, (fadd x, x)) -> (fmul x, 3.0) 6024 if (!CFP10 && N1.getOperand(0) == N1.getOperand(1) && 6025 N1.getOperand(0) == N0) { 6026 return DAG.getNode(ISD::FMUL, SDLoc(N), VT, 6027 N0, DAG.getConstantFP(3.0, VT)); 6028 } 6029 } 6030 6031 // (fadd (fadd x, x), (fadd x, x)) -> (fmul x, 4.0) 6032 if (AllowNewFpConst && 6033 N0.getOpcode() == ISD::FADD && N1.getOpcode() == ISD::FADD && 6034 N0.getOperand(0) == N0.getOperand(1) && 6035 N1.getOperand(0) == N1.getOperand(1) && 6036 N0.getOperand(0) == N1.getOperand(0)) { 6037 return DAG.getNode(ISD::FMUL, SDLoc(N), VT, 6038 N0.getOperand(0), 6039 DAG.getConstantFP(4.0, VT)); 6040 } 6041 } 6042 6043 // FADD -> FMA combines: 6044 if ((DAG.getTarget().Options.AllowFPOpFusion == FPOpFusion::Fast || 6045 DAG.getTarget().Options.UnsafeFPMath) && 6046 DAG.getTarget().getTargetLowering()->isFMAFasterThanMulAndAdd(VT) && 6047 TLI.isOperationLegalOrCustom(ISD::FMA, VT)) { 6048 6049 // fold (fadd (fmul x, y), z) -> (fma x, y, z) 6050 if (N0.getOpcode() == ISD::FMUL && N0->hasOneUse()) { 6051 return DAG.getNode(ISD::FMA, SDLoc(N), VT, 6052 N0.getOperand(0), N0.getOperand(1), N1); 6053 } 6054 6055 // fold (fadd x, (fmul y, z)) -> (fma y, z, x) 6056 // Note: Commutes FADD operands. 6057 if (N1.getOpcode() == ISD::FMUL && N1->hasOneUse()) { 6058 return DAG.getNode(ISD::FMA, SDLoc(N), VT, 6059 N1.getOperand(0), N1.getOperand(1), N0); 6060 } 6061 } 6062 6063 return SDValue(); 6064} 6065 6066SDValue DAGCombiner::visitFSUB(SDNode *N) { 6067 SDValue N0 = N->getOperand(0); 6068 SDValue N1 = N->getOperand(1); 6069 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6070 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 6071 EVT VT = N->getValueType(0); 6072 SDLoc dl(N); 6073 6074 // fold vector ops 6075 if (VT.isVector()) { 6076 SDValue FoldedVOp = SimplifyVBinOp(N); 6077 if (FoldedVOp.getNode()) return FoldedVOp; 6078 } 6079 6080 // fold (fsub c1, c2) -> c1-c2 6081 if (N0CFP && N1CFP) 6082 return DAG.getNode(ISD::FSUB, SDLoc(N), VT, N0, N1); 6083 // fold (fsub A, 0) -> A 6084 if (DAG.getTarget().Options.UnsafeFPMath && 6085 N1CFP && N1CFP->getValueAPF().isZero()) 6086 return N0; 6087 // fold (fsub 0, B) -> -B 6088 if (DAG.getTarget().Options.UnsafeFPMath && 6089 N0CFP && N0CFP->getValueAPF().isZero()) { 6090 if (isNegatibleForFree(N1, LegalOperations, TLI, &DAG.getTarget().Options)) 6091 return GetNegatedExpression(N1, DAG, LegalOperations); 6092 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 6093 return DAG.getNode(ISD::FNEG, dl, VT, N1); 6094 } 6095 // fold (fsub A, (fneg B)) -> (fadd A, B) 6096 if (isNegatibleForFree(N1, LegalOperations, TLI, &DAG.getTarget().Options)) 6097 return DAG.getNode(ISD::FADD, dl, VT, N0, 6098 GetNegatedExpression(N1, DAG, LegalOperations)); 6099 6100 // If 'unsafe math' is enabled, fold 6101 // (fsub x, x) -> 0.0 & 6102 // (fsub x, (fadd x, y)) -> (fneg y) & 6103 // (fsub x, (fadd y, x)) -> (fneg y) 6104 if (DAG.getTarget().Options.UnsafeFPMath) { 6105 if (N0 == N1) 6106 return DAG.getConstantFP(0.0f, VT); 6107 6108 if (N1.getOpcode() == ISD::FADD) { 6109 SDValue N10 = N1->getOperand(0); 6110 SDValue N11 = N1->getOperand(1); 6111 6112 if (N10 == N0 && isNegatibleForFree(N11, LegalOperations, TLI, 6113 &DAG.getTarget().Options)) 6114 return GetNegatedExpression(N11, DAG, LegalOperations); 6115 else if (N11 == N0 && isNegatibleForFree(N10, LegalOperations, TLI, 6116 &DAG.getTarget().Options)) 6117 return GetNegatedExpression(N10, DAG, LegalOperations); 6118 } 6119 } 6120 6121 // FSUB -> FMA combines: 6122 if ((DAG.getTarget().Options.AllowFPOpFusion == FPOpFusion::Fast || 6123 DAG.getTarget().Options.UnsafeFPMath) && 6124 DAG.getTarget().getTargetLowering()->isFMAFasterThanMulAndAdd(VT) && 6125 TLI.isOperationLegalOrCustom(ISD::FMA, VT)) { 6126 6127 // fold (fsub (fmul x, y), z) -> (fma x, y, (fneg z)) 6128 if (N0.getOpcode() == ISD::FMUL && N0->hasOneUse()) { 6129 return DAG.getNode(ISD::FMA, dl, VT, 6130 N0.getOperand(0), N0.getOperand(1), 6131 DAG.getNode(ISD::FNEG, dl, VT, N1)); 6132 } 6133 6134 // fold (fsub x, (fmul y, z)) -> (fma (fneg y), z, x) 6135 // Note: Commutes FSUB operands. 6136 if (N1.getOpcode() == ISD::FMUL && N1->hasOneUse()) { 6137 return DAG.getNode(ISD::FMA, dl, VT, 6138 DAG.getNode(ISD::FNEG, dl, VT, 6139 N1.getOperand(0)), 6140 N1.getOperand(1), N0); 6141 } 6142 6143 // fold (fsub (-(fmul, x, y)), z) -> (fma (fneg x), y, (fneg z)) 6144 if (N0.getOpcode() == ISD::FNEG && 6145 N0.getOperand(0).getOpcode() == ISD::FMUL && 6146 N0->hasOneUse() && N0.getOperand(0).hasOneUse()) { 6147 SDValue N00 = N0.getOperand(0).getOperand(0); 6148 SDValue N01 = N0.getOperand(0).getOperand(1); 6149 return DAG.getNode(ISD::FMA, dl, VT, 6150 DAG.getNode(ISD::FNEG, dl, VT, N00), N01, 6151 DAG.getNode(ISD::FNEG, dl, VT, N1)); 6152 } 6153 } 6154 6155 return SDValue(); 6156} 6157 6158SDValue DAGCombiner::visitFMUL(SDNode *N) { 6159 SDValue N0 = N->getOperand(0); 6160 SDValue N1 = N->getOperand(1); 6161 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6162 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 6163 EVT VT = N->getValueType(0); 6164 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 6165 6166 // fold vector ops 6167 if (VT.isVector()) { 6168 SDValue FoldedVOp = SimplifyVBinOp(N); 6169 if (FoldedVOp.getNode()) return FoldedVOp; 6170 } 6171 6172 // fold (fmul c1, c2) -> c1*c2 6173 if (N0CFP && N1CFP) 6174 return DAG.getNode(ISD::FMUL, SDLoc(N), VT, N0, N1); 6175 // canonicalize constant to RHS 6176 if (N0CFP && !N1CFP) 6177 return DAG.getNode(ISD::FMUL, SDLoc(N), VT, N1, N0); 6178 // fold (fmul A, 0) -> 0 6179 if (DAG.getTarget().Options.UnsafeFPMath && 6180 N1CFP && N1CFP->getValueAPF().isZero()) 6181 return N1; 6182 // fold (fmul A, 0) -> 0, vector edition. 6183 if (DAG.getTarget().Options.UnsafeFPMath && 6184 ISD::isBuildVectorAllZeros(N1.getNode())) 6185 return N1; 6186 // fold (fmul A, 1.0) -> A 6187 if (N1CFP && N1CFP->isExactlyValue(1.0)) 6188 return N0; 6189 // fold (fmul X, 2.0) -> (fadd X, X) 6190 if (N1CFP && N1CFP->isExactlyValue(+2.0)) 6191 return DAG.getNode(ISD::FADD, SDLoc(N), VT, N0, N0); 6192 // fold (fmul X, -1.0) -> (fneg X) 6193 if (N1CFP && N1CFP->isExactlyValue(-1.0)) 6194 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 6195 return DAG.getNode(ISD::FNEG, SDLoc(N), VT, N0); 6196 6197 // fold (fmul (fneg X), (fneg Y)) -> (fmul X, Y) 6198 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations, TLI, 6199 &DAG.getTarget().Options)) { 6200 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations, TLI, 6201 &DAG.getTarget().Options)) { 6202 // Both can be negated for free, check to see if at least one is cheaper 6203 // negated. 6204 if (LHSNeg == 2 || RHSNeg == 2) 6205 return DAG.getNode(ISD::FMUL, SDLoc(N), VT, 6206 GetNegatedExpression(N0, DAG, LegalOperations), 6207 GetNegatedExpression(N1, DAG, LegalOperations)); 6208 } 6209 } 6210 6211 // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2)) 6212 if (DAG.getTarget().Options.UnsafeFPMath && 6213 N1CFP && N0.getOpcode() == ISD::FMUL && 6214 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 6215 return DAG.getNode(ISD::FMUL, SDLoc(N), VT, N0.getOperand(0), 6216 DAG.getNode(ISD::FMUL, SDLoc(N), VT, 6217 N0.getOperand(1), N1)); 6218 6219 return SDValue(); 6220} 6221 6222SDValue DAGCombiner::visitFMA(SDNode *N) { 6223 SDValue N0 = N->getOperand(0); 6224 SDValue N1 = N->getOperand(1); 6225 SDValue N2 = N->getOperand(2); 6226 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6227 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 6228 EVT VT = N->getValueType(0); 6229 SDLoc dl(N); 6230 6231 if (DAG.getTarget().Options.UnsafeFPMath) { 6232 if (N0CFP && N0CFP->isZero()) 6233 return N2; 6234 if (N1CFP && N1CFP->isZero()) 6235 return N2; 6236 } 6237 if (N0CFP && N0CFP->isExactlyValue(1.0)) 6238 return DAG.getNode(ISD::FADD, SDLoc(N), VT, N1, N2); 6239 if (N1CFP && N1CFP->isExactlyValue(1.0)) 6240 return DAG.getNode(ISD::FADD, SDLoc(N), VT, N0, N2); 6241 6242 // Canonicalize (fma c, x, y) -> (fma x, c, y) 6243 if (N0CFP && !N1CFP) 6244 return DAG.getNode(ISD::FMA, SDLoc(N), VT, N1, N0, N2); 6245 6246 // (fma x, c1, (fmul x, c2)) -> (fmul x, c1+c2) 6247 if (DAG.getTarget().Options.UnsafeFPMath && N1CFP && 6248 N2.getOpcode() == ISD::FMUL && 6249 N0 == N2.getOperand(0) && 6250 N2.getOperand(1).getOpcode() == ISD::ConstantFP) { 6251 return DAG.getNode(ISD::FMUL, dl, VT, N0, 6252 DAG.getNode(ISD::FADD, dl, VT, N1, N2.getOperand(1))); 6253 } 6254 6255 6256 // (fma (fmul x, c1), c2, y) -> (fma x, c1*c2, y) 6257 if (DAG.getTarget().Options.UnsafeFPMath && 6258 N0.getOpcode() == ISD::FMUL && N1CFP && 6259 N0.getOperand(1).getOpcode() == ISD::ConstantFP) { 6260 return DAG.getNode(ISD::FMA, dl, VT, 6261 N0.getOperand(0), 6262 DAG.getNode(ISD::FMUL, dl, VT, N1, N0.getOperand(1)), 6263 N2); 6264 } 6265 6266 // (fma x, 1, y) -> (fadd x, y) 6267 // (fma x, -1, y) -> (fadd (fneg x), y) 6268 if (N1CFP) { 6269 if (N1CFP->isExactlyValue(1.0)) 6270 return DAG.getNode(ISD::FADD, dl, VT, N0, N2); 6271 6272 if (N1CFP->isExactlyValue(-1.0) && 6273 (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))) { 6274 SDValue RHSNeg = DAG.getNode(ISD::FNEG, dl, VT, N0); 6275 AddToWorkList(RHSNeg.getNode()); 6276 return DAG.getNode(ISD::FADD, dl, VT, N2, RHSNeg); 6277 } 6278 } 6279 6280 // (fma x, c, x) -> (fmul x, (c+1)) 6281 if (DAG.getTarget().Options.UnsafeFPMath && N1CFP && N0 == N2) { 6282 return DAG.getNode(ISD::FMUL, dl, VT, 6283 N0, 6284 DAG.getNode(ISD::FADD, dl, VT, 6285 N1, DAG.getConstantFP(1.0, VT))); 6286 } 6287 6288 // (fma x, c, (fneg x)) -> (fmul x, (c-1)) 6289 if (DAG.getTarget().Options.UnsafeFPMath && N1CFP && 6290 N2.getOpcode() == ISD::FNEG && N2.getOperand(0) == N0) { 6291 return DAG.getNode(ISD::FMUL, dl, VT, 6292 N0, 6293 DAG.getNode(ISD::FADD, dl, VT, 6294 N1, DAG.getConstantFP(-1.0, VT))); 6295 } 6296 6297 6298 return SDValue(); 6299} 6300 6301SDValue DAGCombiner::visitFDIV(SDNode *N) { 6302 SDValue N0 = N->getOperand(0); 6303 SDValue N1 = N->getOperand(1); 6304 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6305 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 6306 EVT VT = N->getValueType(0); 6307 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 6308 6309 // fold vector ops 6310 if (VT.isVector()) { 6311 SDValue FoldedVOp = SimplifyVBinOp(N); 6312 if (FoldedVOp.getNode()) return FoldedVOp; 6313 } 6314 6315 // fold (fdiv c1, c2) -> c1/c2 6316 if (N0CFP && N1CFP) 6317 return DAG.getNode(ISD::FDIV, SDLoc(N), VT, N0, N1); 6318 6319 // fold (fdiv X, c2) -> fmul X, 1/c2 if losing precision is acceptable. 6320 if (N1CFP && DAG.getTarget().Options.UnsafeFPMath) { 6321 // Compute the reciprocal 1.0 / c2. 6322 APFloat N1APF = N1CFP->getValueAPF(); 6323 APFloat Recip(N1APF.getSemantics(), 1); // 1.0 6324 APFloat::opStatus st = Recip.divide(N1APF, APFloat::rmNearestTiesToEven); 6325 // Only do the transform if the reciprocal is a legal fp immediate that 6326 // isn't too nasty (eg NaN, denormal, ...). 6327 if ((st == APFloat::opOK || st == APFloat::opInexact) && // Not too nasty 6328 (!LegalOperations || 6329 // FIXME: custom lowering of ConstantFP might fail (see e.g. ARM 6330 // backend)... we should handle this gracefully after Legalize. 6331 // TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT) || 6332 TLI.isOperationLegal(llvm::ISD::ConstantFP, VT) || 6333 TLI.isFPImmLegal(Recip, VT))) 6334 return DAG.getNode(ISD::FMUL, SDLoc(N), VT, N0, 6335 DAG.getConstantFP(Recip, VT)); 6336 } 6337 6338 // (fdiv (fneg X), (fneg Y)) -> (fdiv X, Y) 6339 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations, TLI, 6340 &DAG.getTarget().Options)) { 6341 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations, TLI, 6342 &DAG.getTarget().Options)) { 6343 // Both can be negated for free, check to see if at least one is cheaper 6344 // negated. 6345 if (LHSNeg == 2 || RHSNeg == 2) 6346 return DAG.getNode(ISD::FDIV, SDLoc(N), VT, 6347 GetNegatedExpression(N0, DAG, LegalOperations), 6348 GetNegatedExpression(N1, DAG, LegalOperations)); 6349 } 6350 } 6351 6352 return SDValue(); 6353} 6354 6355SDValue DAGCombiner::visitFREM(SDNode *N) { 6356 SDValue N0 = N->getOperand(0); 6357 SDValue N1 = N->getOperand(1); 6358 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6359 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 6360 EVT VT = N->getValueType(0); 6361 6362 // fold (frem c1, c2) -> fmod(c1,c2) 6363 if (N0CFP && N1CFP) 6364 return DAG.getNode(ISD::FREM, SDLoc(N), VT, N0, N1); 6365 6366 return SDValue(); 6367} 6368 6369SDValue DAGCombiner::visitFCOPYSIGN(SDNode *N) { 6370 SDValue N0 = N->getOperand(0); 6371 SDValue N1 = N->getOperand(1); 6372 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6373 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 6374 EVT VT = N->getValueType(0); 6375 6376 if (N0CFP && N1CFP) // Constant fold 6377 return DAG.getNode(ISD::FCOPYSIGN, SDLoc(N), VT, N0, N1); 6378 6379 if (N1CFP) { 6380 const APFloat& V = N1CFP->getValueAPF(); 6381 // copysign(x, c1) -> fabs(x) iff ispos(c1) 6382 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1) 6383 if (!V.isNegative()) { 6384 if (!LegalOperations || TLI.isOperationLegal(ISD::FABS, VT)) 6385 return DAG.getNode(ISD::FABS, SDLoc(N), VT, N0); 6386 } else { 6387 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 6388 return DAG.getNode(ISD::FNEG, SDLoc(N), VT, 6389 DAG.getNode(ISD::FABS, SDLoc(N0), VT, N0)); 6390 } 6391 } 6392 6393 // copysign(fabs(x), y) -> copysign(x, y) 6394 // copysign(fneg(x), y) -> copysign(x, y) 6395 // copysign(copysign(x,z), y) -> copysign(x, y) 6396 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG || 6397 N0.getOpcode() == ISD::FCOPYSIGN) 6398 return DAG.getNode(ISD::FCOPYSIGN, SDLoc(N), VT, 6399 N0.getOperand(0), N1); 6400 6401 // copysign(x, abs(y)) -> abs(x) 6402 if (N1.getOpcode() == ISD::FABS) 6403 return DAG.getNode(ISD::FABS, SDLoc(N), VT, N0); 6404 6405 // copysign(x, copysign(y,z)) -> copysign(x, z) 6406 if (N1.getOpcode() == ISD::FCOPYSIGN) 6407 return DAG.getNode(ISD::FCOPYSIGN, SDLoc(N), VT, 6408 N0, N1.getOperand(1)); 6409 6410 // copysign(x, fp_extend(y)) -> copysign(x, y) 6411 // copysign(x, fp_round(y)) -> copysign(x, y) 6412 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND) 6413 return DAG.getNode(ISD::FCOPYSIGN, SDLoc(N), VT, 6414 N0, N1.getOperand(0)); 6415 6416 return SDValue(); 6417} 6418 6419SDValue DAGCombiner::visitSINT_TO_FP(SDNode *N) { 6420 SDValue N0 = N->getOperand(0); 6421 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 6422 EVT VT = N->getValueType(0); 6423 EVT OpVT = N0.getValueType(); 6424 6425 // fold (sint_to_fp c1) -> c1fp 6426 if (N0C && 6427 // ...but only if the target supports immediate floating-point values 6428 (!LegalOperations || 6429 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT))) 6430 return DAG.getNode(ISD::SINT_TO_FP, SDLoc(N), VT, N0); 6431 6432 // If the input is a legal type, and SINT_TO_FP is not legal on this target, 6433 // but UINT_TO_FP is legal on this target, try to convert. 6434 if (!TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT) && 6435 TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT)) { 6436 // If the sign bit is known to be zero, we can change this to UINT_TO_FP. 6437 if (DAG.SignBitIsZero(N0)) 6438 return DAG.getNode(ISD::UINT_TO_FP, SDLoc(N), VT, N0); 6439 } 6440 6441 // The next optimizations are desireable only if SELECT_CC can be lowered. 6442 // Check against MVT::Other for SELECT_CC, which is a workaround for targets 6443 // having to say they don't support SELECT_CC on every type the DAG knows 6444 // about, since there is no way to mark an opcode illegal at all value types 6445 // (See also visitSELECT) 6446 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other)) { 6447 // fold (sint_to_fp (setcc x, y, cc)) -> (select_cc x, y, -1.0, 0.0,, cc) 6448 if (N0.getOpcode() == ISD::SETCC && N0.getValueType() == MVT::i1 && 6449 !VT.isVector() && 6450 (!LegalOperations || 6451 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT))) { 6452 SDValue Ops[] = 6453 { N0.getOperand(0), N0.getOperand(1), 6454 DAG.getConstantFP(-1.0, VT) , DAG.getConstantFP(0.0, VT), 6455 N0.getOperand(2) }; 6456 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), VT, Ops, 5); 6457 } 6458 6459 // fold (sint_to_fp (zext (setcc x, y, cc))) -> 6460 // (select_cc x, y, 1.0, 0.0,, cc) 6461 if (N0.getOpcode() == ISD::ZERO_EXTEND && 6462 N0.getOperand(0).getOpcode() == ISD::SETCC &&!VT.isVector() && 6463 (!LegalOperations || 6464 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT))) { 6465 SDValue Ops[] = 6466 { N0.getOperand(0).getOperand(0), N0.getOperand(0).getOperand(1), 6467 DAG.getConstantFP(1.0, VT) , DAG.getConstantFP(0.0, VT), 6468 N0.getOperand(0).getOperand(2) }; 6469 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), VT, Ops, 5); 6470 } 6471 } 6472 6473 return SDValue(); 6474} 6475 6476SDValue DAGCombiner::visitUINT_TO_FP(SDNode *N) { 6477 SDValue N0 = N->getOperand(0); 6478 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 6479 EVT VT = N->getValueType(0); 6480 EVT OpVT = N0.getValueType(); 6481 6482 // fold (uint_to_fp c1) -> c1fp 6483 if (N0C && 6484 // ...but only if the target supports immediate floating-point values 6485 (!LegalOperations || 6486 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT))) 6487 return DAG.getNode(ISD::UINT_TO_FP, SDLoc(N), VT, N0); 6488 6489 // If the input is a legal type, and UINT_TO_FP is not legal on this target, 6490 // but SINT_TO_FP is legal on this target, try to convert. 6491 if (!TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT) && 6492 TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT)) { 6493 // If the sign bit is known to be zero, we can change this to SINT_TO_FP. 6494 if (DAG.SignBitIsZero(N0)) 6495 return DAG.getNode(ISD::SINT_TO_FP, SDLoc(N), VT, N0); 6496 } 6497 6498 // The next optimizations are desireable only if SELECT_CC can be lowered. 6499 // Check against MVT::Other for SELECT_CC, which is a workaround for targets 6500 // having to say they don't support SELECT_CC on every type the DAG knows 6501 // about, since there is no way to mark an opcode illegal at all value types 6502 // (See also visitSELECT) 6503 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other)) { 6504 // fold (uint_to_fp (setcc x, y, cc)) -> (select_cc x, y, -1.0, 0.0,, cc) 6505 6506 if (N0.getOpcode() == ISD::SETCC && !VT.isVector() && 6507 (!LegalOperations || 6508 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT))) { 6509 SDValue Ops[] = 6510 { N0.getOperand(0), N0.getOperand(1), 6511 DAG.getConstantFP(1.0, VT), DAG.getConstantFP(0.0, VT), 6512 N0.getOperand(2) }; 6513 return DAG.getNode(ISD::SELECT_CC, SDLoc(N), VT, Ops, 5); 6514 } 6515 } 6516 6517 return SDValue(); 6518} 6519 6520SDValue DAGCombiner::visitFP_TO_SINT(SDNode *N) { 6521 SDValue N0 = N->getOperand(0); 6522 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6523 EVT VT = N->getValueType(0); 6524 6525 // fold (fp_to_sint c1fp) -> c1 6526 if (N0CFP) 6527 return DAG.getNode(ISD::FP_TO_SINT, SDLoc(N), VT, N0); 6528 6529 return SDValue(); 6530} 6531 6532SDValue DAGCombiner::visitFP_TO_UINT(SDNode *N) { 6533 SDValue N0 = N->getOperand(0); 6534 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6535 EVT VT = N->getValueType(0); 6536 6537 // fold (fp_to_uint c1fp) -> c1 6538 if (N0CFP) 6539 return DAG.getNode(ISD::FP_TO_UINT, SDLoc(N), VT, N0); 6540 6541 return SDValue(); 6542} 6543 6544SDValue DAGCombiner::visitFP_ROUND(SDNode *N) { 6545 SDValue N0 = N->getOperand(0); 6546 SDValue N1 = N->getOperand(1); 6547 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6548 EVT VT = N->getValueType(0); 6549 6550 // fold (fp_round c1fp) -> c1fp 6551 if (N0CFP) 6552 return DAG.getNode(ISD::FP_ROUND, SDLoc(N), VT, N0, N1); 6553 6554 // fold (fp_round (fp_extend x)) -> x 6555 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType()) 6556 return N0.getOperand(0); 6557 6558 // fold (fp_round (fp_round x)) -> (fp_round x) 6559 if (N0.getOpcode() == ISD::FP_ROUND) { 6560 // This is a value preserving truncation if both round's are. 6561 bool IsTrunc = N->getConstantOperandVal(1) == 1 && 6562 N0.getNode()->getConstantOperandVal(1) == 1; 6563 return DAG.getNode(ISD::FP_ROUND, SDLoc(N), VT, N0.getOperand(0), 6564 DAG.getIntPtrConstant(IsTrunc)); 6565 } 6566 6567 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y) 6568 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse()) { 6569 SDValue Tmp = DAG.getNode(ISD::FP_ROUND, SDLoc(N0), VT, 6570 N0.getOperand(0), N1); 6571 AddToWorkList(Tmp.getNode()); 6572 return DAG.getNode(ISD::FCOPYSIGN, SDLoc(N), VT, 6573 Tmp, N0.getOperand(1)); 6574 } 6575 6576 return SDValue(); 6577} 6578 6579SDValue DAGCombiner::visitFP_ROUND_INREG(SDNode *N) { 6580 SDValue N0 = N->getOperand(0); 6581 EVT VT = N->getValueType(0); 6582 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 6583 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6584 6585 // fold (fp_round_inreg c1fp) -> c1fp 6586 if (N0CFP && isTypeLegal(EVT)) { 6587 SDValue Round = DAG.getConstantFP(*N0CFP->getConstantFPValue(), EVT); 6588 return DAG.getNode(ISD::FP_EXTEND, SDLoc(N), VT, Round); 6589 } 6590 6591 return SDValue(); 6592} 6593 6594SDValue DAGCombiner::visitFP_EXTEND(SDNode *N) { 6595 SDValue N0 = N->getOperand(0); 6596 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6597 EVT VT = N->getValueType(0); 6598 6599 // If this is fp_round(fpextend), don't fold it, allow ourselves to be folded. 6600 if (N->hasOneUse() && 6601 N->use_begin()->getOpcode() == ISD::FP_ROUND) 6602 return SDValue(); 6603 6604 // fold (fp_extend c1fp) -> c1fp 6605 if (N0CFP) 6606 return DAG.getNode(ISD::FP_EXTEND, SDLoc(N), VT, N0); 6607 6608 // Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't affect the 6609 // value of X. 6610 if (N0.getOpcode() == ISD::FP_ROUND 6611 && N0.getNode()->getConstantOperandVal(1) == 1) { 6612 SDValue In = N0.getOperand(0); 6613 if (In.getValueType() == VT) return In; 6614 if (VT.bitsLT(In.getValueType())) 6615 return DAG.getNode(ISD::FP_ROUND, SDLoc(N), VT, 6616 In, N0.getOperand(1)); 6617 return DAG.getNode(ISD::FP_EXTEND, SDLoc(N), VT, In); 6618 } 6619 6620 // fold (fpext (load x)) -> (fpext (fptrunc (extload x))) 6621 if (ISD::isNON_EXTLoad(N0.getNode()) && N0.hasOneUse() && 6622 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 6623 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) { 6624 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 6625 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, SDLoc(N), VT, 6626 LN0->getChain(), 6627 LN0->getBasePtr(), LN0->getPointerInfo(), 6628 N0.getValueType(), 6629 LN0->isVolatile(), LN0->isNonTemporal(), 6630 LN0->getAlignment()); 6631 CombineTo(N, ExtLoad); 6632 CombineTo(N0.getNode(), 6633 DAG.getNode(ISD::FP_ROUND, SDLoc(N0), 6634 N0.getValueType(), ExtLoad, DAG.getIntPtrConstant(1)), 6635 ExtLoad.getValue(1)); 6636 return SDValue(N, 0); // Return N so it doesn't get rechecked! 6637 } 6638 6639 return SDValue(); 6640} 6641 6642SDValue DAGCombiner::visitFNEG(SDNode *N) { 6643 SDValue N0 = N->getOperand(0); 6644 EVT VT = N->getValueType(0); 6645 6646 if (VT.isVector()) { 6647 SDValue FoldedVOp = SimplifyVUnaryOp(N); 6648 if (FoldedVOp.getNode()) return FoldedVOp; 6649 } 6650 6651 if (isNegatibleForFree(N0, LegalOperations, DAG.getTargetLoweringInfo(), 6652 &DAG.getTarget().Options)) 6653 return GetNegatedExpression(N0, DAG, LegalOperations); 6654 6655 // Transform fneg(bitconvert(x)) -> bitconvert(x^sign) to avoid loading 6656 // constant pool values. 6657 if (!TLI.isFNegFree(VT) && N0.getOpcode() == ISD::BITCAST && 6658 !VT.isVector() && 6659 N0.getNode()->hasOneUse() && 6660 N0.getOperand(0).getValueType().isInteger()) { 6661 SDValue Int = N0.getOperand(0); 6662 EVT IntVT = Int.getValueType(); 6663 if (IntVT.isInteger() && !IntVT.isVector()) { 6664 Int = DAG.getNode(ISD::XOR, SDLoc(N0), IntVT, Int, 6665 DAG.getConstant(APInt::getSignBit(IntVT.getSizeInBits()), IntVT)); 6666 AddToWorkList(Int.getNode()); 6667 return DAG.getNode(ISD::BITCAST, SDLoc(N), 6668 VT, Int); 6669 } 6670 } 6671 6672 // (fneg (fmul c, x)) -> (fmul -c, x) 6673 if (N0.getOpcode() == ISD::FMUL) { 6674 ConstantFPSDNode *CFP1 = dyn_cast<ConstantFPSDNode>(N0.getOperand(1)); 6675 if (CFP1) { 6676 return DAG.getNode(ISD::FMUL, SDLoc(N), VT, 6677 N0.getOperand(0), 6678 DAG.getNode(ISD::FNEG, SDLoc(N), VT, 6679 N0.getOperand(1))); 6680 } 6681 } 6682 6683 return SDValue(); 6684} 6685 6686SDValue DAGCombiner::visitFCEIL(SDNode *N) { 6687 SDValue N0 = N->getOperand(0); 6688 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6689 EVT VT = N->getValueType(0); 6690 6691 // fold (fceil c1) -> fceil(c1) 6692 if (N0CFP) 6693 return DAG.getNode(ISD::FCEIL, SDLoc(N), VT, N0); 6694 6695 return SDValue(); 6696} 6697 6698SDValue DAGCombiner::visitFTRUNC(SDNode *N) { 6699 SDValue N0 = N->getOperand(0); 6700 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6701 EVT VT = N->getValueType(0); 6702 6703 // fold (ftrunc c1) -> ftrunc(c1) 6704 if (N0CFP) 6705 return DAG.getNode(ISD::FTRUNC, SDLoc(N), VT, N0); 6706 6707 return SDValue(); 6708} 6709 6710SDValue DAGCombiner::visitFFLOOR(SDNode *N) { 6711 SDValue N0 = N->getOperand(0); 6712 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6713 EVT VT = N->getValueType(0); 6714 6715 // fold (ffloor c1) -> ffloor(c1) 6716 if (N0CFP) 6717 return DAG.getNode(ISD::FFLOOR, SDLoc(N), VT, N0); 6718 6719 return SDValue(); 6720} 6721 6722SDValue DAGCombiner::visitFABS(SDNode *N) { 6723 SDValue N0 = N->getOperand(0); 6724 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6725 EVT VT = N->getValueType(0); 6726 6727 if (VT.isVector()) { 6728 SDValue FoldedVOp = SimplifyVUnaryOp(N); 6729 if (FoldedVOp.getNode()) return FoldedVOp; 6730 } 6731 6732 // fold (fabs c1) -> fabs(c1) 6733 if (N0CFP) 6734 return DAG.getNode(ISD::FABS, SDLoc(N), VT, N0); 6735 // fold (fabs (fabs x)) -> (fabs x) 6736 if (N0.getOpcode() == ISD::FABS) 6737 return N->getOperand(0); 6738 // fold (fabs (fneg x)) -> (fabs x) 6739 // fold (fabs (fcopysign x, y)) -> (fabs x) 6740 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN) 6741 return DAG.getNode(ISD::FABS, SDLoc(N), VT, N0.getOperand(0)); 6742 6743 // Transform fabs(bitconvert(x)) -> bitconvert(x&~sign) to avoid loading 6744 // constant pool values. 6745 if (!TLI.isFAbsFree(VT) && 6746 N0.getOpcode() == ISD::BITCAST && N0.getNode()->hasOneUse() && 6747 N0.getOperand(0).getValueType().isInteger() && 6748 !N0.getOperand(0).getValueType().isVector()) { 6749 SDValue Int = N0.getOperand(0); 6750 EVT IntVT = Int.getValueType(); 6751 if (IntVT.isInteger() && !IntVT.isVector()) { 6752 Int = DAG.getNode(ISD::AND, SDLoc(N0), IntVT, Int, 6753 DAG.getConstant(~APInt::getSignBit(IntVT.getSizeInBits()), IntVT)); 6754 AddToWorkList(Int.getNode()); 6755 return DAG.getNode(ISD::BITCAST, SDLoc(N), 6756 N->getValueType(0), Int); 6757 } 6758 } 6759 6760 return SDValue(); 6761} 6762 6763SDValue DAGCombiner::visitBRCOND(SDNode *N) { 6764 SDValue Chain = N->getOperand(0); 6765 SDValue N1 = N->getOperand(1); 6766 SDValue N2 = N->getOperand(2); 6767 6768 // If N is a constant we could fold this into a fallthrough or unconditional 6769 // branch. However that doesn't happen very often in normal code, because 6770 // Instcombine/SimplifyCFG should have handled the available opportunities. 6771 // If we did this folding here, it would be necessary to update the 6772 // MachineBasicBlock CFG, which is awkward. 6773 6774 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal 6775 // on the target. 6776 if (N1.getOpcode() == ISD::SETCC && 6777 TLI.isOperationLegalOrCustom(ISD::BR_CC, 6778 N1.getOperand(0).getValueType())) { 6779 return DAG.getNode(ISD::BR_CC, SDLoc(N), MVT::Other, 6780 Chain, N1.getOperand(2), 6781 N1.getOperand(0), N1.getOperand(1), N2); 6782 } 6783 6784 if ((N1.hasOneUse() && N1.getOpcode() == ISD::SRL) || 6785 ((N1.getOpcode() == ISD::TRUNCATE && N1.hasOneUse()) && 6786 (N1.getOperand(0).hasOneUse() && 6787 N1.getOperand(0).getOpcode() == ISD::SRL))) { 6788 SDNode *Trunc = 0; 6789 if (N1.getOpcode() == ISD::TRUNCATE) { 6790 // Look pass the truncate. 6791 Trunc = N1.getNode(); 6792 N1 = N1.getOperand(0); 6793 } 6794 6795 // Match this pattern so that we can generate simpler code: 6796 // 6797 // %a = ... 6798 // %b = and i32 %a, 2 6799 // %c = srl i32 %b, 1 6800 // brcond i32 %c ... 6801 // 6802 // into 6803 // 6804 // %a = ... 6805 // %b = and i32 %a, 2 6806 // %c = setcc eq %b, 0 6807 // brcond %c ... 6808 // 6809 // This applies only when the AND constant value has one bit set and the 6810 // SRL constant is equal to the log2 of the AND constant. The back-end is 6811 // smart enough to convert the result into a TEST/JMP sequence. 6812 SDValue Op0 = N1.getOperand(0); 6813 SDValue Op1 = N1.getOperand(1); 6814 6815 if (Op0.getOpcode() == ISD::AND && 6816 Op1.getOpcode() == ISD::Constant) { 6817 SDValue AndOp1 = Op0.getOperand(1); 6818 6819 if (AndOp1.getOpcode() == ISD::Constant) { 6820 const APInt &AndConst = cast<ConstantSDNode>(AndOp1)->getAPIntValue(); 6821 6822 if (AndConst.isPowerOf2() && 6823 cast<ConstantSDNode>(Op1)->getAPIntValue()==AndConst.logBase2()) { 6824 SDValue SetCC = 6825 DAG.getSetCC(SDLoc(N), 6826 getSetCCResultType(Op0.getValueType()), 6827 Op0, DAG.getConstant(0, Op0.getValueType()), 6828 ISD::SETNE); 6829 6830 SDValue NewBRCond = DAG.getNode(ISD::BRCOND, SDLoc(N), 6831 MVT::Other, Chain, SetCC, N2); 6832 // Don't add the new BRCond into the worklist or else SimplifySelectCC 6833 // will convert it back to (X & C1) >> C2. 6834 CombineTo(N, NewBRCond, false); 6835 // Truncate is dead. 6836 if (Trunc) { 6837 removeFromWorkList(Trunc); 6838 DAG.DeleteNode(Trunc); 6839 } 6840 // Replace the uses of SRL with SETCC 6841 WorkListRemover DeadNodes(*this); 6842 DAG.ReplaceAllUsesOfValueWith(N1, SetCC); 6843 removeFromWorkList(N1.getNode()); 6844 DAG.DeleteNode(N1.getNode()); 6845 return SDValue(N, 0); // Return N so it doesn't get rechecked! 6846 } 6847 } 6848 } 6849 6850 if (Trunc) 6851 // Restore N1 if the above transformation doesn't match. 6852 N1 = N->getOperand(1); 6853 } 6854 6855 // Transform br(xor(x, y)) -> br(x != y) 6856 // Transform br(xor(xor(x,y), 1)) -> br (x == y) 6857 if (N1.hasOneUse() && N1.getOpcode() == ISD::XOR) { 6858 SDNode *TheXor = N1.getNode(); 6859 SDValue Op0 = TheXor->getOperand(0); 6860 SDValue Op1 = TheXor->getOperand(1); 6861 if (Op0.getOpcode() == Op1.getOpcode()) { 6862 // Avoid missing important xor optimizations. 6863 SDValue Tmp = visitXOR(TheXor); 6864 if (Tmp.getNode()) { 6865 if (Tmp.getNode() != TheXor) { 6866 DEBUG(dbgs() << "\nReplacing.8 "; 6867 TheXor->dump(&DAG); 6868 dbgs() << "\nWith: "; 6869 Tmp.getNode()->dump(&DAG); 6870 dbgs() << '\n'); 6871 WorkListRemover DeadNodes(*this); 6872 DAG.ReplaceAllUsesOfValueWith(N1, Tmp); 6873 removeFromWorkList(TheXor); 6874 DAG.DeleteNode(TheXor); 6875 return DAG.getNode(ISD::BRCOND, SDLoc(N), 6876 MVT::Other, Chain, Tmp, N2); 6877 } 6878 6879 // visitXOR has changed XOR's operands or replaced the XOR completely, 6880 // bail out. 6881 return SDValue(N, 0); 6882 } 6883 } 6884 6885 if (Op0.getOpcode() != ISD::SETCC && Op1.getOpcode() != ISD::SETCC) { 6886 bool Equal = false; 6887 if (ConstantSDNode *RHSCI = dyn_cast<ConstantSDNode>(Op0)) 6888 if (RHSCI->getAPIntValue() == 1 && Op0.hasOneUse() && 6889 Op0.getOpcode() == ISD::XOR) { 6890 TheXor = Op0.getNode(); 6891 Equal = true; 6892 } 6893 6894 EVT SetCCVT = N1.getValueType(); 6895 if (LegalTypes) 6896 SetCCVT = getSetCCResultType(SetCCVT); 6897 SDValue SetCC = DAG.getSetCC(SDLoc(TheXor), 6898 SetCCVT, 6899 Op0, Op1, 6900 Equal ? ISD::SETEQ : ISD::SETNE); 6901 // Replace the uses of XOR with SETCC 6902 WorkListRemover DeadNodes(*this); 6903 DAG.ReplaceAllUsesOfValueWith(N1, SetCC); 6904 removeFromWorkList(N1.getNode()); 6905 DAG.DeleteNode(N1.getNode()); 6906 return DAG.getNode(ISD::BRCOND, SDLoc(N), 6907 MVT::Other, Chain, SetCC, N2); 6908 } 6909 } 6910 6911 return SDValue(); 6912} 6913 6914// Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB. 6915// 6916SDValue DAGCombiner::visitBR_CC(SDNode *N) { 6917 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1)); 6918 SDValue CondLHS = N->getOperand(2), CondRHS = N->getOperand(3); 6919 6920 // If N is a constant we could fold this into a fallthrough or unconditional 6921 // branch. However that doesn't happen very often in normal code, because 6922 // Instcombine/SimplifyCFG should have handled the available opportunities. 6923 // If we did this folding here, it would be necessary to update the 6924 // MachineBasicBlock CFG, which is awkward. 6925 6926 // Use SimplifySetCC to simplify SETCC's. 6927 SDValue Simp = SimplifySetCC(getSetCCResultType(CondLHS.getValueType()), 6928 CondLHS, CondRHS, CC->get(), SDLoc(N), 6929 false); 6930 if (Simp.getNode()) AddToWorkList(Simp.getNode()); 6931 6932 // fold to a simpler setcc 6933 if (Simp.getNode() && Simp.getOpcode() == ISD::SETCC) 6934 return DAG.getNode(ISD::BR_CC, SDLoc(N), MVT::Other, 6935 N->getOperand(0), Simp.getOperand(2), 6936 Simp.getOperand(0), Simp.getOperand(1), 6937 N->getOperand(4)); 6938 6939 return SDValue(); 6940} 6941 6942/// canFoldInAddressingMode - Return true if 'Use' is a load or a store that 6943/// uses N as its base pointer and that N may be folded in the load / store 6944/// addressing mode. 6945static bool canFoldInAddressingMode(SDNode *N, SDNode *Use, 6946 SelectionDAG &DAG, 6947 const TargetLowering &TLI) { 6948 EVT VT; 6949 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Use)) { 6950 if (LD->isIndexed() || LD->getBasePtr().getNode() != N) 6951 return false; 6952 VT = Use->getValueType(0); 6953 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(Use)) { 6954 if (ST->isIndexed() || ST->getBasePtr().getNode() != N) 6955 return false; 6956 VT = ST->getValue().getValueType(); 6957 } else 6958 return false; 6959 6960 TargetLowering::AddrMode AM; 6961 if (N->getOpcode() == ISD::ADD) { 6962 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1)); 6963 if (Offset) 6964 // [reg +/- imm] 6965 AM.BaseOffs = Offset->getSExtValue(); 6966 else 6967 // [reg +/- reg] 6968 AM.Scale = 1; 6969 } else if (N->getOpcode() == ISD::SUB) { 6970 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1)); 6971 if (Offset) 6972 // [reg +/- imm] 6973 AM.BaseOffs = -Offset->getSExtValue(); 6974 else 6975 // [reg +/- reg] 6976 AM.Scale = 1; 6977 } else 6978 return false; 6979 6980 return TLI.isLegalAddressingMode(AM, VT.getTypeForEVT(*DAG.getContext())); 6981} 6982 6983/// CombineToPreIndexedLoadStore - Try turning a load / store into a 6984/// pre-indexed load / store when the base pointer is an add or subtract 6985/// and it has other uses besides the load / store. After the 6986/// transformation, the new indexed load / store has effectively folded 6987/// the add / subtract in and all of its other uses are redirected to the 6988/// new load / store. 6989bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) { 6990 if (Level < AfterLegalizeDAG) 6991 return false; 6992 6993 bool isLoad = true; 6994 SDValue Ptr; 6995 EVT VT; 6996 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 6997 if (LD->isIndexed()) 6998 return false; 6999 VT = LD->getMemoryVT(); 7000 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) && 7001 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT)) 7002 return false; 7003 Ptr = LD->getBasePtr(); 7004 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 7005 if (ST->isIndexed()) 7006 return false; 7007 VT = ST->getMemoryVT(); 7008 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) && 7009 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT)) 7010 return false; 7011 Ptr = ST->getBasePtr(); 7012 isLoad = false; 7013 } else { 7014 return false; 7015 } 7016 7017 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail 7018 // out. There is no reason to make this a preinc/predec. 7019 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) || 7020 Ptr.getNode()->hasOneUse()) 7021 return false; 7022 7023 // Ask the target to do addressing mode selection. 7024 SDValue BasePtr; 7025 SDValue Offset; 7026 ISD::MemIndexedMode AM = ISD::UNINDEXED; 7027 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG)) 7028 return false; 7029 7030 // Backends without true r+i pre-indexed forms may need to pass a 7031 // constant base with a variable offset so that constant coercion 7032 // will work with the patterns in canonical form. 7033 bool Swapped = false; 7034 if (isa<ConstantSDNode>(BasePtr)) { 7035 std::swap(BasePtr, Offset); 7036 Swapped = true; 7037 } 7038 7039 // Don't create a indexed load / store with zero offset. 7040 if (isa<ConstantSDNode>(Offset) && 7041 cast<ConstantSDNode>(Offset)->isNullValue()) 7042 return false; 7043 7044 // Try turning it into a pre-indexed load / store except when: 7045 // 1) The new base ptr is a frame index. 7046 // 2) If N is a store and the new base ptr is either the same as or is a 7047 // predecessor of the value being stored. 7048 // 3) Another use of old base ptr is a predecessor of N. If ptr is folded 7049 // that would create a cycle. 7050 // 4) All uses are load / store ops that use it as old base ptr. 7051 7052 // Check #1. Preinc'ing a frame index would require copying the stack pointer 7053 // (plus the implicit offset) to a register to preinc anyway. 7054 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr)) 7055 return false; 7056 7057 // Check #2. 7058 if (!isLoad) { 7059 SDValue Val = cast<StoreSDNode>(N)->getValue(); 7060 if (Val == BasePtr || BasePtr.getNode()->isPredecessorOf(Val.getNode())) 7061 return false; 7062 } 7063 7064 // If the offset is a constant, there may be other adds of constants that 7065 // can be folded with this one. We should do this to avoid having to keep 7066 // a copy of the original base pointer. 7067 SmallVector<SDNode *, 16> OtherUses; 7068 if (isa<ConstantSDNode>(Offset)) 7069 for (SDNode::use_iterator I = BasePtr.getNode()->use_begin(), 7070 E = BasePtr.getNode()->use_end(); I != E; ++I) { 7071 SDNode *Use = *I; 7072 if (Use == Ptr.getNode()) 7073 continue; 7074 7075 if (Use->isPredecessorOf(N)) 7076 continue; 7077 7078 if (Use->getOpcode() != ISD::ADD && Use->getOpcode() != ISD::SUB) { 7079 OtherUses.clear(); 7080 break; 7081 } 7082 7083 SDValue Op0 = Use->getOperand(0), Op1 = Use->getOperand(1); 7084 if (Op1.getNode() == BasePtr.getNode()) 7085 std::swap(Op0, Op1); 7086 assert(Op0.getNode() == BasePtr.getNode() && 7087 "Use of ADD/SUB but not an operand"); 7088 7089 if (!isa<ConstantSDNode>(Op1)) { 7090 OtherUses.clear(); 7091 break; 7092 } 7093 7094 // FIXME: In some cases, we can be smarter about this. 7095 if (Op1.getValueType() != Offset.getValueType()) { 7096 OtherUses.clear(); 7097 break; 7098 } 7099 7100 OtherUses.push_back(Use); 7101 } 7102 7103 if (Swapped) 7104 std::swap(BasePtr, Offset); 7105 7106 // Now check for #3 and #4. 7107 bool RealUse = false; 7108 7109 // Caches for hasPredecessorHelper 7110 SmallPtrSet<const SDNode *, 32> Visited; 7111 SmallVector<const SDNode *, 16> Worklist; 7112 7113 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(), 7114 E = Ptr.getNode()->use_end(); I != E; ++I) { 7115 SDNode *Use = *I; 7116 if (Use == N) 7117 continue; 7118 if (N->hasPredecessorHelper(Use, Visited, Worklist)) 7119 return false; 7120 7121 // If Ptr may be folded in addressing mode of other use, then it's 7122 // not profitable to do this transformation. 7123 if (!canFoldInAddressingMode(Ptr.getNode(), Use, DAG, TLI)) 7124 RealUse = true; 7125 } 7126 7127 if (!RealUse) 7128 return false; 7129 7130 SDValue Result; 7131 if (isLoad) 7132 Result = DAG.getIndexedLoad(SDValue(N,0), SDLoc(N), 7133 BasePtr, Offset, AM); 7134 else 7135 Result = DAG.getIndexedStore(SDValue(N,0), SDLoc(N), 7136 BasePtr, Offset, AM); 7137 ++PreIndexedNodes; 7138 ++NodesCombined; 7139 DEBUG(dbgs() << "\nReplacing.4 "; 7140 N->dump(&DAG); 7141 dbgs() << "\nWith: "; 7142 Result.getNode()->dump(&DAG); 7143 dbgs() << '\n'); 7144 WorkListRemover DeadNodes(*this); 7145 if (isLoad) { 7146 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0)); 7147 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2)); 7148 } else { 7149 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1)); 7150 } 7151 7152 // Finally, since the node is now dead, remove it from the graph. 7153 DAG.DeleteNode(N); 7154 7155 if (Swapped) 7156 std::swap(BasePtr, Offset); 7157 7158 // Replace other uses of BasePtr that can be updated to use Ptr 7159 for (unsigned i = 0, e = OtherUses.size(); i != e; ++i) { 7160 unsigned OffsetIdx = 1; 7161 if (OtherUses[i]->getOperand(OffsetIdx).getNode() == BasePtr.getNode()) 7162 OffsetIdx = 0; 7163 assert(OtherUses[i]->getOperand(!OffsetIdx).getNode() == 7164 BasePtr.getNode() && "Expected BasePtr operand"); 7165 7166 // We need to replace ptr0 in the following expression: 7167 // x0 * offset0 + y0 * ptr0 = t0 7168 // knowing that 7169 // x1 * offset1 + y1 * ptr0 = t1 (the indexed load/store) 7170 // 7171 // where x0, x1, y0 and y1 in {-1, 1} are given by the types of the 7172 // indexed load/store and the expresion that needs to be re-written. 7173 // 7174 // Therefore, we have: 7175 // t0 = (x0 * offset0 - x1 * y0 * y1 *offset1) + (y0 * y1) * t1 7176 7177 ConstantSDNode *CN = 7178 cast<ConstantSDNode>(OtherUses[i]->getOperand(OffsetIdx)); 7179 int X0, X1, Y0, Y1; 7180 APInt Offset0 = CN->getAPIntValue(); 7181 APInt Offset1 = cast<ConstantSDNode>(Offset)->getAPIntValue(); 7182 7183 X0 = (OtherUses[i]->getOpcode() == ISD::SUB && OffsetIdx == 1) ? -1 : 1; 7184 Y0 = (OtherUses[i]->getOpcode() == ISD::SUB && OffsetIdx == 0) ? -1 : 1; 7185 X1 = (AM == ISD::PRE_DEC && !Swapped) ? -1 : 1; 7186 Y1 = (AM == ISD::PRE_DEC && Swapped) ? -1 : 1; 7187 7188 unsigned Opcode = (Y0 * Y1 < 0) ? ISD::SUB : ISD::ADD; 7189 7190 APInt CNV = Offset0; 7191 if (X0 < 0) CNV = -CNV; 7192 if (X1 * Y0 * Y1 < 0) CNV = CNV + Offset1; 7193 else CNV = CNV - Offset1; 7194 7195 // We can now generate the new expression. 7196 SDValue NewOp1 = DAG.getConstant(CNV, CN->getValueType(0)); 7197 SDValue NewOp2 = Result.getValue(isLoad ? 1 : 0); 7198 7199 SDValue NewUse = DAG.getNode(Opcode, 7200 SDLoc(OtherUses[i]), 7201 OtherUses[i]->getValueType(0), NewOp1, NewOp2); 7202 DAG.ReplaceAllUsesOfValueWith(SDValue(OtherUses[i], 0), NewUse); 7203 removeFromWorkList(OtherUses[i]); 7204 DAG.DeleteNode(OtherUses[i]); 7205 } 7206 7207 // Replace the uses of Ptr with uses of the updated base value. 7208 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0)); 7209 removeFromWorkList(Ptr.getNode()); 7210 DAG.DeleteNode(Ptr.getNode()); 7211 7212 return true; 7213} 7214 7215/// CombineToPostIndexedLoadStore - Try to combine a load / store with a 7216/// add / sub of the base pointer node into a post-indexed load / store. 7217/// The transformation folded the add / subtract into the new indexed 7218/// load / store effectively and all of its uses are redirected to the 7219/// new load / store. 7220bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) { 7221 if (Level < AfterLegalizeDAG) 7222 return false; 7223 7224 bool isLoad = true; 7225 SDValue Ptr; 7226 EVT VT; 7227 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 7228 if (LD->isIndexed()) 7229 return false; 7230 VT = LD->getMemoryVT(); 7231 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) && 7232 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT)) 7233 return false; 7234 Ptr = LD->getBasePtr(); 7235 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 7236 if (ST->isIndexed()) 7237 return false; 7238 VT = ST->getMemoryVT(); 7239 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) && 7240 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT)) 7241 return false; 7242 Ptr = ST->getBasePtr(); 7243 isLoad = false; 7244 } else { 7245 return false; 7246 } 7247 7248 if (Ptr.getNode()->hasOneUse()) 7249 return false; 7250 7251 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(), 7252 E = Ptr.getNode()->use_end(); I != E; ++I) { 7253 SDNode *Op = *I; 7254 if (Op == N || 7255 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB)) 7256 continue; 7257 7258 SDValue BasePtr; 7259 SDValue Offset; 7260 ISD::MemIndexedMode AM = ISD::UNINDEXED; 7261 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) { 7262 // Don't create a indexed load / store with zero offset. 7263 if (isa<ConstantSDNode>(Offset) && 7264 cast<ConstantSDNode>(Offset)->isNullValue()) 7265 continue; 7266 7267 // Try turning it into a post-indexed load / store except when 7268 // 1) All uses are load / store ops that use it as base ptr (and 7269 // it may be folded as addressing mmode). 7270 // 2) Op must be independent of N, i.e. Op is neither a predecessor 7271 // nor a successor of N. Otherwise, if Op is folded that would 7272 // create a cycle. 7273 7274 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr)) 7275 continue; 7276 7277 // Check for #1. 7278 bool TryNext = false; 7279 for (SDNode::use_iterator II = BasePtr.getNode()->use_begin(), 7280 EE = BasePtr.getNode()->use_end(); II != EE; ++II) { 7281 SDNode *Use = *II; 7282 if (Use == Ptr.getNode()) 7283 continue; 7284 7285 // If all the uses are load / store addresses, then don't do the 7286 // transformation. 7287 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){ 7288 bool RealUse = false; 7289 for (SDNode::use_iterator III = Use->use_begin(), 7290 EEE = Use->use_end(); III != EEE; ++III) { 7291 SDNode *UseUse = *III; 7292 if (!canFoldInAddressingMode(Use, UseUse, DAG, TLI)) 7293 RealUse = true; 7294 } 7295 7296 if (!RealUse) { 7297 TryNext = true; 7298 break; 7299 } 7300 } 7301 } 7302 7303 if (TryNext) 7304 continue; 7305 7306 // Check for #2 7307 if (!Op->isPredecessorOf(N) && !N->isPredecessorOf(Op)) { 7308 SDValue Result = isLoad 7309 ? DAG.getIndexedLoad(SDValue(N,0), SDLoc(N), 7310 BasePtr, Offset, AM) 7311 : DAG.getIndexedStore(SDValue(N,0), SDLoc(N), 7312 BasePtr, Offset, AM); 7313 ++PostIndexedNodes; 7314 ++NodesCombined; 7315 DEBUG(dbgs() << "\nReplacing.5 "; 7316 N->dump(&DAG); 7317 dbgs() << "\nWith: "; 7318 Result.getNode()->dump(&DAG); 7319 dbgs() << '\n'); 7320 WorkListRemover DeadNodes(*this); 7321 if (isLoad) { 7322 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0)); 7323 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2)); 7324 } else { 7325 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1)); 7326 } 7327 7328 // Finally, since the node is now dead, remove it from the graph. 7329 DAG.DeleteNode(N); 7330 7331 // Replace the uses of Use with uses of the updated base value. 7332 DAG.ReplaceAllUsesOfValueWith(SDValue(Op, 0), 7333 Result.getValue(isLoad ? 1 : 0)); 7334 removeFromWorkList(Op); 7335 DAG.DeleteNode(Op); 7336 return true; 7337 } 7338 } 7339 } 7340 7341 return false; 7342} 7343 7344SDValue DAGCombiner::visitLOAD(SDNode *N) { 7345 LoadSDNode *LD = cast<LoadSDNode>(N); 7346 SDValue Chain = LD->getChain(); 7347 SDValue Ptr = LD->getBasePtr(); 7348 7349 // If load is not volatile and there are no uses of the loaded value (and 7350 // the updated indexed value in case of indexed loads), change uses of the 7351 // chain value into uses of the chain input (i.e. delete the dead load). 7352 if (!LD->isVolatile()) { 7353 if (N->getValueType(1) == MVT::Other) { 7354 // Unindexed loads. 7355 if (!N->hasAnyUseOfValue(0)) { 7356 // It's not safe to use the two value CombineTo variant here. e.g. 7357 // v1, chain2 = load chain1, loc 7358 // v2, chain3 = load chain2, loc 7359 // v3 = add v2, c 7360 // Now we replace use of chain2 with chain1. This makes the second load 7361 // isomorphic to the one we are deleting, and thus makes this load live. 7362 DEBUG(dbgs() << "\nReplacing.6 "; 7363 N->dump(&DAG); 7364 dbgs() << "\nWith chain: "; 7365 Chain.getNode()->dump(&DAG); 7366 dbgs() << "\n"); 7367 WorkListRemover DeadNodes(*this); 7368 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Chain); 7369 7370 if (N->use_empty()) { 7371 removeFromWorkList(N); 7372 DAG.DeleteNode(N); 7373 } 7374 7375 return SDValue(N, 0); // Return N so it doesn't get rechecked! 7376 } 7377 } else { 7378 // Indexed loads. 7379 assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?"); 7380 if (!N->hasAnyUseOfValue(0) && !N->hasAnyUseOfValue(1)) { 7381 SDValue Undef = DAG.getUNDEF(N->getValueType(0)); 7382 DEBUG(dbgs() << "\nReplacing.7 "; 7383 N->dump(&DAG); 7384 dbgs() << "\nWith: "; 7385 Undef.getNode()->dump(&DAG); 7386 dbgs() << " and 2 other values\n"); 7387 WorkListRemover DeadNodes(*this); 7388 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Undef); 7389 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), 7390 DAG.getUNDEF(N->getValueType(1))); 7391 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 2), Chain); 7392 removeFromWorkList(N); 7393 DAG.DeleteNode(N); 7394 return SDValue(N, 0); // Return N so it doesn't get rechecked! 7395 } 7396 } 7397 } 7398 7399 // If this load is directly stored, replace the load value with the stored 7400 // value. 7401 // TODO: Handle store large -> read small portion. 7402 // TODO: Handle TRUNCSTORE/LOADEXT 7403 if (ISD::isNormalLoad(N) && !LD->isVolatile()) { 7404 if (ISD::isNON_TRUNCStore(Chain.getNode())) { 7405 StoreSDNode *PrevST = cast<StoreSDNode>(Chain); 7406 if (PrevST->getBasePtr() == Ptr && 7407 PrevST->getValue().getValueType() == N->getValueType(0)) 7408 return CombineTo(N, Chain.getOperand(1), Chain); 7409 } 7410 } 7411 7412 // Try to infer better alignment information than the load already has. 7413 if (OptLevel != CodeGenOpt::None && LD->isUnindexed()) { 7414 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) { 7415 if (Align > LD->getMemOperand()->getBaseAlignment()) { 7416 SDValue NewLoad = 7417 DAG.getExtLoad(LD->getExtensionType(), SDLoc(N), 7418 LD->getValueType(0), 7419 Chain, Ptr, LD->getPointerInfo(), 7420 LD->getMemoryVT(), 7421 LD->isVolatile(), LD->isNonTemporal(), Align); 7422 return CombineTo(N, NewLoad, SDValue(NewLoad.getNode(), 1), true); 7423 } 7424 } 7425 } 7426 7427 if (CombinerAA) { 7428 // Walk up chain skipping non-aliasing memory nodes. 7429 SDValue BetterChain = FindBetterChain(N, Chain); 7430 7431 // If there is a better chain. 7432 if (Chain != BetterChain) { 7433 SDValue ReplLoad; 7434 7435 // Replace the chain to void dependency. 7436 if (LD->getExtensionType() == ISD::NON_EXTLOAD) { 7437 ReplLoad = DAG.getLoad(N->getValueType(0), SDLoc(LD), 7438 BetterChain, Ptr, LD->getPointerInfo(), 7439 LD->isVolatile(), LD->isNonTemporal(), 7440 LD->isInvariant(), LD->getAlignment()); 7441 } else { 7442 ReplLoad = DAG.getExtLoad(LD->getExtensionType(), SDLoc(LD), 7443 LD->getValueType(0), 7444 BetterChain, Ptr, LD->getPointerInfo(), 7445 LD->getMemoryVT(), 7446 LD->isVolatile(), 7447 LD->isNonTemporal(), 7448 LD->getAlignment()); 7449 } 7450 7451 // Create token factor to keep old chain connected. 7452 SDValue Token = DAG.getNode(ISD::TokenFactor, SDLoc(N), 7453 MVT::Other, Chain, ReplLoad.getValue(1)); 7454 7455 // Make sure the new and old chains are cleaned up. 7456 AddToWorkList(Token.getNode()); 7457 7458 // Replace uses with load result and token factor. Don't add users 7459 // to work list. 7460 return CombineTo(N, ReplLoad.getValue(0), Token, false); 7461 } 7462 } 7463 7464 // Try transforming N to an indexed load. 7465 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 7466 return SDValue(N, 0); 7467 7468 return SDValue(); 7469} 7470 7471/// CheckForMaskedLoad - Check to see if V is (and load (ptr), imm), where the 7472/// load is having specific bytes cleared out. If so, return the byte size 7473/// being masked out and the shift amount. 7474static std::pair<unsigned, unsigned> 7475CheckForMaskedLoad(SDValue V, SDValue Ptr, SDValue Chain) { 7476 std::pair<unsigned, unsigned> Result(0, 0); 7477 7478 // Check for the structure we're looking for. 7479 if (V->getOpcode() != ISD::AND || 7480 !isa<ConstantSDNode>(V->getOperand(1)) || 7481 !ISD::isNormalLoad(V->getOperand(0).getNode())) 7482 return Result; 7483 7484 // Check the chain and pointer. 7485 LoadSDNode *LD = cast<LoadSDNode>(V->getOperand(0)); 7486 if (LD->getBasePtr() != Ptr) return Result; // Not from same pointer. 7487 7488 // The store should be chained directly to the load or be an operand of a 7489 // tokenfactor. 7490 if (LD == Chain.getNode()) 7491 ; // ok. 7492 else if (Chain->getOpcode() != ISD::TokenFactor) 7493 return Result; // Fail. 7494 else { 7495 bool isOk = false; 7496 for (unsigned i = 0, e = Chain->getNumOperands(); i != e; ++i) 7497 if (Chain->getOperand(i).getNode() == LD) { 7498 isOk = true; 7499 break; 7500 } 7501 if (!isOk) return Result; 7502 } 7503 7504 // This only handles simple types. 7505 if (V.getValueType() != MVT::i16 && 7506 V.getValueType() != MVT::i32 && 7507 V.getValueType() != MVT::i64) 7508 return Result; 7509 7510 // Check the constant mask. Invert it so that the bits being masked out are 7511 // 0 and the bits being kept are 1. Use getSExtValue so that leading bits 7512 // follow the sign bit for uniformity. 7513 uint64_t NotMask = ~cast<ConstantSDNode>(V->getOperand(1))->getSExtValue(); 7514 unsigned NotMaskLZ = countLeadingZeros(NotMask); 7515 if (NotMaskLZ & 7) return Result; // Must be multiple of a byte. 7516 unsigned NotMaskTZ = countTrailingZeros(NotMask); 7517 if (NotMaskTZ & 7) return Result; // Must be multiple of a byte. 7518 if (NotMaskLZ == 64) return Result; // All zero mask. 7519 7520 // See if we have a continuous run of bits. If so, we have 0*1+0* 7521 if (CountTrailingOnes_64(NotMask >> NotMaskTZ)+NotMaskTZ+NotMaskLZ != 64) 7522 return Result; 7523 7524 // Adjust NotMaskLZ down to be from the actual size of the int instead of i64. 7525 if (V.getValueType() != MVT::i64 && NotMaskLZ) 7526 NotMaskLZ -= 64-V.getValueSizeInBits(); 7527 7528 unsigned MaskedBytes = (V.getValueSizeInBits()-NotMaskLZ-NotMaskTZ)/8; 7529 switch (MaskedBytes) { 7530 case 1: 7531 case 2: 7532 case 4: break; 7533 default: return Result; // All one mask, or 5-byte mask. 7534 } 7535 7536 // Verify that the first bit starts at a multiple of mask so that the access 7537 // is aligned the same as the access width. 7538 if (NotMaskTZ && NotMaskTZ/8 % MaskedBytes) return Result; 7539 7540 Result.first = MaskedBytes; 7541 Result.second = NotMaskTZ/8; 7542 return Result; 7543} 7544 7545 7546/// ShrinkLoadReplaceStoreWithStore - Check to see if IVal is something that 7547/// provides a value as specified by MaskInfo. If so, replace the specified 7548/// store with a narrower store of truncated IVal. 7549static SDNode * 7550ShrinkLoadReplaceStoreWithStore(const std::pair<unsigned, unsigned> &MaskInfo, 7551 SDValue IVal, StoreSDNode *St, 7552 DAGCombiner *DC) { 7553 unsigned NumBytes = MaskInfo.first; 7554 unsigned ByteShift = MaskInfo.second; 7555 SelectionDAG &DAG = DC->getDAG(); 7556 7557 // Check to see if IVal is all zeros in the part being masked in by the 'or' 7558 // that uses this. If not, this is not a replacement. 7559 APInt Mask = ~APInt::getBitsSet(IVal.getValueSizeInBits(), 7560 ByteShift*8, (ByteShift+NumBytes)*8); 7561 if (!DAG.MaskedValueIsZero(IVal, Mask)) return 0; 7562 7563 // Check that it is legal on the target to do this. It is legal if the new 7564 // VT we're shrinking to (i8/i16/i32) is legal or we're still before type 7565 // legalization. 7566 MVT VT = MVT::getIntegerVT(NumBytes*8); 7567 if (!DC->isTypeLegal(VT)) 7568 return 0; 7569 7570 // Okay, we can do this! Replace the 'St' store with a store of IVal that is 7571 // shifted by ByteShift and truncated down to NumBytes. 7572 if (ByteShift) 7573 IVal = DAG.getNode(ISD::SRL, SDLoc(IVal), IVal.getValueType(), IVal, 7574 DAG.getConstant(ByteShift*8, 7575 DC->getShiftAmountTy(IVal.getValueType()))); 7576 7577 // Figure out the offset for the store and the alignment of the access. 7578 unsigned StOffset; 7579 unsigned NewAlign = St->getAlignment(); 7580 7581 if (DAG.getTargetLoweringInfo().isLittleEndian()) 7582 StOffset = ByteShift; 7583 else 7584 StOffset = IVal.getValueType().getStoreSize() - ByteShift - NumBytes; 7585 7586 SDValue Ptr = St->getBasePtr(); 7587 if (StOffset) { 7588 Ptr = DAG.getNode(ISD::ADD, SDLoc(IVal), Ptr.getValueType(), 7589 Ptr, DAG.getConstant(StOffset, Ptr.getValueType())); 7590 NewAlign = MinAlign(NewAlign, StOffset); 7591 } 7592 7593 // Truncate down to the new size. 7594 IVal = DAG.getNode(ISD::TRUNCATE, SDLoc(IVal), VT, IVal); 7595 7596 ++OpsNarrowed; 7597 return DAG.getStore(St->getChain(), SDLoc(St), IVal, Ptr, 7598 St->getPointerInfo().getWithOffset(StOffset), 7599 false, false, NewAlign).getNode(); 7600} 7601 7602 7603/// ReduceLoadOpStoreWidth - Look for sequence of load / op / store where op is 7604/// one of 'or', 'xor', and 'and' of immediates. If 'op' is only touching some 7605/// of the loaded bits, try narrowing the load and store if it would end up 7606/// being a win for performance or code size. 7607SDValue DAGCombiner::ReduceLoadOpStoreWidth(SDNode *N) { 7608 StoreSDNode *ST = cast<StoreSDNode>(N); 7609 if (ST->isVolatile()) 7610 return SDValue(); 7611 7612 SDValue Chain = ST->getChain(); 7613 SDValue Value = ST->getValue(); 7614 SDValue Ptr = ST->getBasePtr(); 7615 EVT VT = Value.getValueType(); 7616 7617 if (ST->isTruncatingStore() || VT.isVector() || !Value.hasOneUse()) 7618 return SDValue(); 7619 7620 unsigned Opc = Value.getOpcode(); 7621 7622 // If this is "store (or X, Y), P" and X is "(and (load P), cst)", where cst 7623 // is a byte mask indicating a consecutive number of bytes, check to see if 7624 // Y is known to provide just those bytes. If so, we try to replace the 7625 // load + replace + store sequence with a single (narrower) store, which makes 7626 // the load dead. 7627 if (Opc == ISD::OR) { 7628 std::pair<unsigned, unsigned> MaskedLoad; 7629 MaskedLoad = CheckForMaskedLoad(Value.getOperand(0), Ptr, Chain); 7630 if (MaskedLoad.first) 7631 if (SDNode *NewST = ShrinkLoadReplaceStoreWithStore(MaskedLoad, 7632 Value.getOperand(1), ST,this)) 7633 return SDValue(NewST, 0); 7634 7635 // Or is commutative, so try swapping X and Y. 7636 MaskedLoad = CheckForMaskedLoad(Value.getOperand(1), Ptr, Chain); 7637 if (MaskedLoad.first) 7638 if (SDNode *NewST = ShrinkLoadReplaceStoreWithStore(MaskedLoad, 7639 Value.getOperand(0), ST,this)) 7640 return SDValue(NewST, 0); 7641 } 7642 7643 if ((Opc != ISD::OR && Opc != ISD::XOR && Opc != ISD::AND) || 7644 Value.getOperand(1).getOpcode() != ISD::Constant) 7645 return SDValue(); 7646 7647 SDValue N0 = Value.getOperand(0); 7648 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() && 7649 Chain == SDValue(N0.getNode(), 1)) { 7650 LoadSDNode *LD = cast<LoadSDNode>(N0); 7651 if (LD->getBasePtr() != Ptr || 7652 LD->getPointerInfo().getAddrSpace() != 7653 ST->getPointerInfo().getAddrSpace()) 7654 return SDValue(); 7655 7656 // Find the type to narrow it the load / op / store to. 7657 SDValue N1 = Value.getOperand(1); 7658 unsigned BitWidth = N1.getValueSizeInBits(); 7659 APInt Imm = cast<ConstantSDNode>(N1)->getAPIntValue(); 7660 if (Opc == ISD::AND) 7661 Imm ^= APInt::getAllOnesValue(BitWidth); 7662 if (Imm == 0 || Imm.isAllOnesValue()) 7663 return SDValue(); 7664 unsigned ShAmt = Imm.countTrailingZeros(); 7665 unsigned MSB = BitWidth - Imm.countLeadingZeros() - 1; 7666 unsigned NewBW = NextPowerOf2(MSB - ShAmt); 7667 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW); 7668 while (NewBW < BitWidth && 7669 !(TLI.isOperationLegalOrCustom(Opc, NewVT) && 7670 TLI.isNarrowingProfitable(VT, NewVT))) { 7671 NewBW = NextPowerOf2(NewBW); 7672 NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW); 7673 } 7674 if (NewBW >= BitWidth) 7675 return SDValue(); 7676 7677 // If the lsb changed does not start at the type bitwidth boundary, 7678 // start at the previous one. 7679 if (ShAmt % NewBW) 7680 ShAmt = (((ShAmt + NewBW - 1) / NewBW) * NewBW) - NewBW; 7681 APInt Mask = APInt::getBitsSet(BitWidth, ShAmt, 7682 std::min(BitWidth, ShAmt + NewBW)); 7683 if ((Imm & Mask) == Imm) { 7684 APInt NewImm = (Imm & Mask).lshr(ShAmt).trunc(NewBW); 7685 if (Opc == ISD::AND) 7686 NewImm ^= APInt::getAllOnesValue(NewBW); 7687 uint64_t PtrOff = ShAmt / 8; 7688 // For big endian targets, we need to adjust the offset to the pointer to 7689 // load the correct bytes. 7690 if (TLI.isBigEndian()) 7691 PtrOff = (BitWidth + 7 - NewBW) / 8 - PtrOff; 7692 7693 unsigned NewAlign = MinAlign(LD->getAlignment(), PtrOff); 7694 Type *NewVTTy = NewVT.getTypeForEVT(*DAG.getContext()); 7695 if (NewAlign < TLI.getDataLayout()->getABITypeAlignment(NewVTTy)) 7696 return SDValue(); 7697 7698 SDValue NewPtr = DAG.getNode(ISD::ADD, SDLoc(LD), 7699 Ptr.getValueType(), Ptr, 7700 DAG.getConstant(PtrOff, Ptr.getValueType())); 7701 SDValue NewLD = DAG.getLoad(NewVT, SDLoc(N0), 7702 LD->getChain(), NewPtr, 7703 LD->getPointerInfo().getWithOffset(PtrOff), 7704 LD->isVolatile(), LD->isNonTemporal(), 7705 LD->isInvariant(), NewAlign); 7706 SDValue NewVal = DAG.getNode(Opc, SDLoc(Value), NewVT, NewLD, 7707 DAG.getConstant(NewImm, NewVT)); 7708 SDValue NewST = DAG.getStore(Chain, SDLoc(N), 7709 NewVal, NewPtr, 7710 ST->getPointerInfo().getWithOffset(PtrOff), 7711 false, false, NewAlign); 7712 7713 AddToWorkList(NewPtr.getNode()); 7714 AddToWorkList(NewLD.getNode()); 7715 AddToWorkList(NewVal.getNode()); 7716 WorkListRemover DeadNodes(*this); 7717 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), NewLD.getValue(1)); 7718 ++OpsNarrowed; 7719 return NewST; 7720 } 7721 } 7722 7723 return SDValue(); 7724} 7725 7726/// TransformFPLoadStorePair - For a given floating point load / store pair, 7727/// if the load value isn't used by any other operations, then consider 7728/// transforming the pair to integer load / store operations if the target 7729/// deems the transformation profitable. 7730SDValue DAGCombiner::TransformFPLoadStorePair(SDNode *N) { 7731 StoreSDNode *ST = cast<StoreSDNode>(N); 7732 SDValue Chain = ST->getChain(); 7733 SDValue Value = ST->getValue(); 7734 if (ISD::isNormalStore(ST) && ISD::isNormalLoad(Value.getNode()) && 7735 Value.hasOneUse() && 7736 Chain == SDValue(Value.getNode(), 1)) { 7737 LoadSDNode *LD = cast<LoadSDNode>(Value); 7738 EVT VT = LD->getMemoryVT(); 7739 if (!VT.isFloatingPoint() || 7740 VT != ST->getMemoryVT() || 7741 LD->isNonTemporal() || 7742 ST->isNonTemporal() || 7743 LD->getPointerInfo().getAddrSpace() != 0 || 7744 ST->getPointerInfo().getAddrSpace() != 0) 7745 return SDValue(); 7746 7747 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits()); 7748 if (!TLI.isOperationLegal(ISD::LOAD, IntVT) || 7749 !TLI.isOperationLegal(ISD::STORE, IntVT) || 7750 !TLI.isDesirableToTransformToIntegerOp(ISD::LOAD, VT) || 7751 !TLI.isDesirableToTransformToIntegerOp(ISD::STORE, VT)) 7752 return SDValue(); 7753 7754 unsigned LDAlign = LD->getAlignment(); 7755 unsigned STAlign = ST->getAlignment(); 7756 Type *IntVTTy = IntVT.getTypeForEVT(*DAG.getContext()); 7757 unsigned ABIAlign = TLI.getDataLayout()->getABITypeAlignment(IntVTTy); 7758 if (LDAlign < ABIAlign || STAlign < ABIAlign) 7759 return SDValue(); 7760 7761 SDValue NewLD = DAG.getLoad(IntVT, SDLoc(Value), 7762 LD->getChain(), LD->getBasePtr(), 7763 LD->getPointerInfo(), 7764 false, false, false, LDAlign); 7765 7766 SDValue NewST = DAG.getStore(NewLD.getValue(1), SDLoc(N), 7767 NewLD, ST->getBasePtr(), 7768 ST->getPointerInfo(), 7769 false, false, STAlign); 7770 7771 AddToWorkList(NewLD.getNode()); 7772 AddToWorkList(NewST.getNode()); 7773 WorkListRemover DeadNodes(*this); 7774 DAG.ReplaceAllUsesOfValueWith(Value.getValue(1), NewLD.getValue(1)); 7775 ++LdStFP2Int; 7776 return NewST; 7777 } 7778 7779 return SDValue(); 7780} 7781 7782/// Helper struct to parse and store a memory address as base + index + offset. 7783/// We ignore sign extensions when it is safe to do so. 7784/// The following two expressions are not equivalent. To differentiate we need 7785/// to store whether there was a sign extension involved in the index 7786/// computation. 7787/// (load (i64 add (i64 copyfromreg %c) 7788/// (i64 signextend (add (i8 load %index) 7789/// (i8 1)))) 7790/// vs 7791/// 7792/// (load (i64 add (i64 copyfromreg %c) 7793/// (i64 signextend (i32 add (i32 signextend (i8 load %index)) 7794/// (i32 1))))) 7795struct BaseIndexOffset { 7796 SDValue Base; 7797 SDValue Index; 7798 int64_t Offset; 7799 bool IsIndexSignExt; 7800 7801 BaseIndexOffset() : Offset(0), IsIndexSignExt(false) {} 7802 7803 BaseIndexOffset(SDValue Base, SDValue Index, int64_t Offset, 7804 bool IsIndexSignExt) : 7805 Base(Base), Index(Index), Offset(Offset), IsIndexSignExt(IsIndexSignExt) {} 7806 7807 bool equalBaseIndex(const BaseIndexOffset &Other) { 7808 return Other.Base == Base && Other.Index == Index && 7809 Other.IsIndexSignExt == IsIndexSignExt; 7810 } 7811 7812 /// Parses tree in Ptr for base, index, offset addresses. 7813 static BaseIndexOffset match(SDValue Ptr) { 7814 bool IsIndexSignExt = false; 7815 7816 // Just Base or possibly anything else. 7817 if (Ptr->getOpcode() != ISD::ADD) 7818 return BaseIndexOffset(Ptr, SDValue(), 0, IsIndexSignExt); 7819 7820 // Base + offset. 7821 if (isa<ConstantSDNode>(Ptr->getOperand(1))) { 7822 int64_t Offset = cast<ConstantSDNode>(Ptr->getOperand(1))->getSExtValue(); 7823 return BaseIndexOffset(Ptr->getOperand(0), SDValue(), Offset, 7824 IsIndexSignExt); 7825 } 7826 7827 // Look at Base + Index + Offset cases. 7828 SDValue Base = Ptr->getOperand(0); 7829 SDValue IndexOffset = Ptr->getOperand(1); 7830 7831 // Skip signextends. 7832 if (IndexOffset->getOpcode() == ISD::SIGN_EXTEND) { 7833 IndexOffset = IndexOffset->getOperand(0); 7834 IsIndexSignExt = true; 7835 } 7836 7837 // Either the case of Base + Index (no offset) or something else. 7838 if (IndexOffset->getOpcode() != ISD::ADD) 7839 return BaseIndexOffset(Base, IndexOffset, 0, IsIndexSignExt); 7840 7841 // Now we have the case of Base + Index + offset. 7842 SDValue Index = IndexOffset->getOperand(0); 7843 SDValue Offset = IndexOffset->getOperand(1); 7844 7845 if (!isa<ConstantSDNode>(Offset)) 7846 return BaseIndexOffset(Ptr, SDValue(), 0, IsIndexSignExt); 7847 7848 // Ignore signextends. 7849 if (Index->getOpcode() == ISD::SIGN_EXTEND) { 7850 Index = Index->getOperand(0); 7851 IsIndexSignExt = true; 7852 } else IsIndexSignExt = false; 7853 7854 int64_t Off = cast<ConstantSDNode>(Offset)->getSExtValue(); 7855 return BaseIndexOffset(Base, Index, Off, IsIndexSignExt); 7856 } 7857}; 7858 7859/// Holds a pointer to an LSBaseSDNode as well as information on where it 7860/// is located in a sequence of memory operations connected by a chain. 7861struct MemOpLink { 7862 MemOpLink (LSBaseSDNode *N, int64_t Offset, unsigned Seq): 7863 MemNode(N), OffsetFromBase(Offset), SequenceNum(Seq) { } 7864 // Ptr to the mem node. 7865 LSBaseSDNode *MemNode; 7866 // Offset from the base ptr. 7867 int64_t OffsetFromBase; 7868 // What is the sequence number of this mem node. 7869 // Lowest mem operand in the DAG starts at zero. 7870 unsigned SequenceNum; 7871}; 7872 7873/// Sorts store nodes in a link according to their offset from a shared 7874// base ptr. 7875struct ConsecutiveMemoryChainSorter { 7876 bool operator()(MemOpLink LHS, MemOpLink RHS) { 7877 return LHS.OffsetFromBase < RHS.OffsetFromBase; 7878 } 7879}; 7880 7881bool DAGCombiner::MergeConsecutiveStores(StoreSDNode* St) { 7882 EVT MemVT = St->getMemoryVT(); 7883 int64_t ElementSizeBytes = MemVT.getSizeInBits()/8; 7884 bool NoVectors = DAG.getMachineFunction().getFunction()->getAttributes(). 7885 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoImplicitFloat); 7886 7887 // Don't merge vectors into wider inputs. 7888 if (MemVT.isVector() || !MemVT.isSimple()) 7889 return false; 7890 7891 // Perform an early exit check. Do not bother looking at stored values that 7892 // are not constants or loads. 7893 SDValue StoredVal = St->getValue(); 7894 bool IsLoadSrc = isa<LoadSDNode>(StoredVal); 7895 if (!isa<ConstantSDNode>(StoredVal) && !isa<ConstantFPSDNode>(StoredVal) && 7896 !IsLoadSrc) 7897 return false; 7898 7899 // Only look at ends of store sequences. 7900 SDValue Chain = SDValue(St, 1); 7901 if (Chain->hasOneUse() && Chain->use_begin()->getOpcode() == ISD::STORE) 7902 return false; 7903 7904 // This holds the base pointer, index, and the offset in bytes from the base 7905 // pointer. 7906 BaseIndexOffset BasePtr = BaseIndexOffset::match(St->getBasePtr()); 7907 7908 // We must have a base and an offset. 7909 if (!BasePtr.Base.getNode()) 7910 return false; 7911 7912 // Do not handle stores to undef base pointers. 7913 if (BasePtr.Base.getOpcode() == ISD::UNDEF) 7914 return false; 7915 7916 // Save the LoadSDNodes that we find in the chain. 7917 // We need to make sure that these nodes do not interfere with 7918 // any of the store nodes. 7919 SmallVector<LSBaseSDNode*, 8> AliasLoadNodes; 7920 7921 // Save the StoreSDNodes that we find in the chain. 7922 SmallVector<MemOpLink, 8> StoreNodes; 7923 7924 // Walk up the chain and look for nodes with offsets from the same 7925 // base pointer. Stop when reaching an instruction with a different kind 7926 // or instruction which has a different base pointer. 7927 unsigned Seq = 0; 7928 StoreSDNode *Index = St; 7929 while (Index) { 7930 // If the chain has more than one use, then we can't reorder the mem ops. 7931 if (Index != St && !SDValue(Index, 1)->hasOneUse()) 7932 break; 7933 7934 // Find the base pointer and offset for this memory node. 7935 BaseIndexOffset Ptr = BaseIndexOffset::match(Index->getBasePtr()); 7936 7937 // Check that the base pointer is the same as the original one. 7938 if (!Ptr.equalBaseIndex(BasePtr)) 7939 break; 7940 7941 // Check that the alignment is the same. 7942 if (Index->getAlignment() != St->getAlignment()) 7943 break; 7944 7945 // The memory operands must not be volatile. 7946 if (Index->isVolatile() || Index->isIndexed()) 7947 break; 7948 7949 // No truncation. 7950 if (StoreSDNode *St = dyn_cast<StoreSDNode>(Index)) 7951 if (St->isTruncatingStore()) 7952 break; 7953 7954 // The stored memory type must be the same. 7955 if (Index->getMemoryVT() != MemVT) 7956 break; 7957 7958 // We do not allow unaligned stores because we want to prevent overriding 7959 // stores. 7960 if (Index->getAlignment()*8 != MemVT.getSizeInBits()) 7961 break; 7962 7963 // We found a potential memory operand to merge. 7964 StoreNodes.push_back(MemOpLink(Index, Ptr.Offset, Seq++)); 7965 7966 // Find the next memory operand in the chain. If the next operand in the 7967 // chain is a store then move up and continue the scan with the next 7968 // memory operand. If the next operand is a load save it and use alias 7969 // information to check if it interferes with anything. 7970 SDNode *NextInChain = Index->getChain().getNode(); 7971 while (1) { 7972 if (StoreSDNode *STn = dyn_cast<StoreSDNode>(NextInChain)) { 7973 // We found a store node. Use it for the next iteration. 7974 Index = STn; 7975 break; 7976 } else if (LoadSDNode *Ldn = dyn_cast<LoadSDNode>(NextInChain)) { 7977 // Save the load node for later. Continue the scan. 7978 AliasLoadNodes.push_back(Ldn); 7979 NextInChain = Ldn->getChain().getNode(); 7980 continue; 7981 } else { 7982 Index = NULL; 7983 break; 7984 } 7985 } 7986 } 7987 7988 // Check if there is anything to merge. 7989 if (StoreNodes.size() < 2) 7990 return false; 7991 7992 // Sort the memory operands according to their distance from the base pointer. 7993 std::sort(StoreNodes.begin(), StoreNodes.end(), 7994 ConsecutiveMemoryChainSorter()); 7995 7996 // Scan the memory operations on the chain and find the first non-consecutive 7997 // store memory address. 7998 unsigned LastConsecutiveStore = 0; 7999 int64_t StartAddress = StoreNodes[0].OffsetFromBase; 8000 for (unsigned i = 0, e = StoreNodes.size(); i < e; ++i) { 8001 8002 // Check that the addresses are consecutive starting from the second 8003 // element in the list of stores. 8004 if (i > 0) { 8005 int64_t CurrAddress = StoreNodes[i].OffsetFromBase; 8006 if (CurrAddress - StartAddress != (ElementSizeBytes * i)) 8007 break; 8008 } 8009 8010 bool Alias = false; 8011 // Check if this store interferes with any of the loads that we found. 8012 for (unsigned ld = 0, lde = AliasLoadNodes.size(); ld < lde; ++ld) 8013 if (isAlias(AliasLoadNodes[ld], StoreNodes[i].MemNode)) { 8014 Alias = true; 8015 break; 8016 } 8017 // We found a load that alias with this store. Stop the sequence. 8018 if (Alias) 8019 break; 8020 8021 // Mark this node as useful. 8022 LastConsecutiveStore = i; 8023 } 8024 8025 // The node with the lowest store address. 8026 LSBaseSDNode *FirstInChain = StoreNodes[0].MemNode; 8027 8028 // Store the constants into memory as one consecutive store. 8029 if (!IsLoadSrc) { 8030 unsigned LastLegalType = 0; 8031 unsigned LastLegalVectorType = 0; 8032 bool NonZero = false; 8033 for (unsigned i=0; i<LastConsecutiveStore+1; ++i) { 8034 StoreSDNode *St = cast<StoreSDNode>(StoreNodes[i].MemNode); 8035 SDValue StoredVal = St->getValue(); 8036 8037 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(StoredVal)) { 8038 NonZero |= !C->isNullValue(); 8039 } else if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(StoredVal)) { 8040 NonZero |= !C->getConstantFPValue()->isNullValue(); 8041 } else { 8042 // Non constant. 8043 break; 8044 } 8045 8046 // Find a legal type for the constant store. 8047 unsigned StoreBW = (i+1) * ElementSizeBytes * 8; 8048 EVT StoreTy = EVT::getIntegerVT(*DAG.getContext(), StoreBW); 8049 if (TLI.isTypeLegal(StoreTy)) 8050 LastLegalType = i+1; 8051 // Or check whether a truncstore is legal. 8052 else if (TLI.getTypeAction(*DAG.getContext(), StoreTy) == 8053 TargetLowering::TypePromoteInteger) { 8054 EVT LegalizedStoredValueTy = 8055 TLI.getTypeToTransformTo(*DAG.getContext(), StoredVal.getValueType()); 8056 if (TLI.isTruncStoreLegal(LegalizedStoredValueTy, StoreTy)) 8057 LastLegalType = i+1; 8058 } 8059 8060 // Find a legal type for the vector store. 8061 EVT Ty = EVT::getVectorVT(*DAG.getContext(), MemVT, i+1); 8062 if (TLI.isTypeLegal(Ty)) 8063 LastLegalVectorType = i + 1; 8064 } 8065 8066 // We only use vectors if the constant is known to be zero and the 8067 // function is not marked with the noimplicitfloat attribute. 8068 if (NonZero || NoVectors) 8069 LastLegalVectorType = 0; 8070 8071 // Check if we found a legal integer type to store. 8072 if (LastLegalType == 0 && LastLegalVectorType == 0) 8073 return false; 8074 8075 bool UseVector = (LastLegalVectorType > LastLegalType) && !NoVectors; 8076 unsigned NumElem = UseVector ? LastLegalVectorType : LastLegalType; 8077 8078 // Make sure we have something to merge. 8079 if (NumElem < 2) 8080 return false; 8081 8082 unsigned EarliestNodeUsed = 0; 8083 for (unsigned i=0; i < NumElem; ++i) { 8084 // Find a chain for the new wide-store operand. Notice that some 8085 // of the store nodes that we found may not be selected for inclusion 8086 // in the wide store. The chain we use needs to be the chain of the 8087 // earliest store node which is *used* and replaced by the wide store. 8088 if (StoreNodes[i].SequenceNum > StoreNodes[EarliestNodeUsed].SequenceNum) 8089 EarliestNodeUsed = i; 8090 } 8091 8092 // The earliest Node in the DAG. 8093 LSBaseSDNode *EarliestOp = StoreNodes[EarliestNodeUsed].MemNode; 8094 SDLoc DL(StoreNodes[0].MemNode); 8095 8096 SDValue StoredVal; 8097 if (UseVector) { 8098 // Find a legal type for the vector store. 8099 EVT Ty = EVT::getVectorVT(*DAG.getContext(), MemVT, NumElem); 8100 assert(TLI.isTypeLegal(Ty) && "Illegal vector store"); 8101 StoredVal = DAG.getConstant(0, Ty); 8102 } else { 8103 unsigned StoreBW = NumElem * ElementSizeBytes * 8; 8104 APInt StoreInt(StoreBW, 0); 8105 8106 // Construct a single integer constant which is made of the smaller 8107 // constant inputs. 8108 bool IsLE = TLI.isLittleEndian(); 8109 for (unsigned i = 0; i < NumElem ; ++i) { 8110 unsigned Idx = IsLE ?(NumElem - 1 - i) : i; 8111 StoreSDNode *St = cast<StoreSDNode>(StoreNodes[Idx].MemNode); 8112 SDValue Val = St->getValue(); 8113 StoreInt<<=ElementSizeBytes*8; 8114 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Val)) { 8115 StoreInt|=C->getAPIntValue().zext(StoreBW); 8116 } else if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(Val)) { 8117 StoreInt|= C->getValueAPF().bitcastToAPInt().zext(StoreBW); 8118 } else { 8119 assert(false && "Invalid constant element type"); 8120 } 8121 } 8122 8123 // Create the new Load and Store operations. 8124 EVT StoreTy = EVT::getIntegerVT(*DAG.getContext(), StoreBW); 8125 StoredVal = DAG.getConstant(StoreInt, StoreTy); 8126 } 8127 8128 SDValue NewStore = DAG.getStore(EarliestOp->getChain(), DL, StoredVal, 8129 FirstInChain->getBasePtr(), 8130 FirstInChain->getPointerInfo(), 8131 false, false, 8132 FirstInChain->getAlignment()); 8133 8134 // Replace the first store with the new store 8135 CombineTo(EarliestOp, NewStore); 8136 // Erase all other stores. 8137 for (unsigned i = 0; i < NumElem ; ++i) { 8138 if (StoreNodes[i].MemNode == EarliestOp) 8139 continue; 8140 StoreSDNode *St = cast<StoreSDNode>(StoreNodes[i].MemNode); 8141 // ReplaceAllUsesWith will replace all uses that existed when it was 8142 // called, but graph optimizations may cause new ones to appear. For 8143 // example, the case in pr14333 looks like 8144 // 8145 // St's chain -> St -> another store -> X 8146 // 8147 // And the only difference from St to the other store is the chain. 8148 // When we change it's chain to be St's chain they become identical, 8149 // get CSEed and the net result is that X is now a use of St. 8150 // Since we know that St is redundant, just iterate. 8151 while (!St->use_empty()) 8152 DAG.ReplaceAllUsesWith(SDValue(St, 0), St->getChain()); 8153 removeFromWorkList(St); 8154 DAG.DeleteNode(St); 8155 } 8156 8157 return true; 8158 } 8159 8160 // Below we handle the case of multiple consecutive stores that 8161 // come from multiple consecutive loads. We merge them into a single 8162 // wide load and a single wide store. 8163 8164 // Look for load nodes which are used by the stored values. 8165 SmallVector<MemOpLink, 8> LoadNodes; 8166 8167 // Find acceptable loads. Loads need to have the same chain (token factor), 8168 // must not be zext, volatile, indexed, and they must be consecutive. 8169 BaseIndexOffset LdBasePtr; 8170 for (unsigned i=0; i<LastConsecutiveStore+1; ++i) { 8171 StoreSDNode *St = cast<StoreSDNode>(StoreNodes[i].MemNode); 8172 LoadSDNode *Ld = dyn_cast<LoadSDNode>(St->getValue()); 8173 if (!Ld) break; 8174 8175 // Loads must only have one use. 8176 if (!Ld->hasNUsesOfValue(1, 0)) 8177 break; 8178 8179 // Check that the alignment is the same as the stores. 8180 if (Ld->getAlignment() != St->getAlignment()) 8181 break; 8182 8183 // The memory operands must not be volatile. 8184 if (Ld->isVolatile() || Ld->isIndexed()) 8185 break; 8186 8187 // We do not accept ext loads. 8188 if (Ld->getExtensionType() != ISD::NON_EXTLOAD) 8189 break; 8190 8191 // The stored memory type must be the same. 8192 if (Ld->getMemoryVT() != MemVT) 8193 break; 8194 8195 BaseIndexOffset LdPtr = BaseIndexOffset::match(Ld->getBasePtr()); 8196 // If this is not the first ptr that we check. 8197 if (LdBasePtr.Base.getNode()) { 8198 // The base ptr must be the same. 8199 if (!LdPtr.equalBaseIndex(LdBasePtr)) 8200 break; 8201 } else { 8202 // Check that all other base pointers are the same as this one. 8203 LdBasePtr = LdPtr; 8204 } 8205 8206 // We found a potential memory operand to merge. 8207 LoadNodes.push_back(MemOpLink(Ld, LdPtr.Offset, 0)); 8208 } 8209 8210 if (LoadNodes.size() < 2) 8211 return false; 8212 8213 // Scan the memory operations on the chain and find the first non-consecutive 8214 // load memory address. These variables hold the index in the store node 8215 // array. 8216 unsigned LastConsecutiveLoad = 0; 8217 // This variable refers to the size and not index in the array. 8218 unsigned LastLegalVectorType = 0; 8219 unsigned LastLegalIntegerType = 0; 8220 StartAddress = LoadNodes[0].OffsetFromBase; 8221 SDValue FirstChain = LoadNodes[0].MemNode->getChain(); 8222 for (unsigned i = 1; i < LoadNodes.size(); ++i) { 8223 // All loads much share the same chain. 8224 if (LoadNodes[i].MemNode->getChain() != FirstChain) 8225 break; 8226 8227 int64_t CurrAddress = LoadNodes[i].OffsetFromBase; 8228 if (CurrAddress - StartAddress != (ElementSizeBytes * i)) 8229 break; 8230 LastConsecutiveLoad = i; 8231 8232 // Find a legal type for the vector store. 8233 EVT StoreTy = EVT::getVectorVT(*DAG.getContext(), MemVT, i+1); 8234 if (TLI.isTypeLegal(StoreTy)) 8235 LastLegalVectorType = i + 1; 8236 8237 // Find a legal type for the integer store. 8238 unsigned StoreBW = (i+1) * ElementSizeBytes * 8; 8239 StoreTy = EVT::getIntegerVT(*DAG.getContext(), StoreBW); 8240 if (TLI.isTypeLegal(StoreTy)) 8241 LastLegalIntegerType = i + 1; 8242 // Or check whether a truncstore and extload is legal. 8243 else if (TLI.getTypeAction(*DAG.getContext(), StoreTy) == 8244 TargetLowering::TypePromoteInteger) { 8245 EVT LegalizedStoredValueTy = 8246 TLI.getTypeToTransformTo(*DAG.getContext(), StoreTy); 8247 if (TLI.isTruncStoreLegal(LegalizedStoredValueTy, StoreTy) && 8248 TLI.isLoadExtLegal(ISD::ZEXTLOAD, StoreTy) && 8249 TLI.isLoadExtLegal(ISD::SEXTLOAD, StoreTy) && 8250 TLI.isLoadExtLegal(ISD::EXTLOAD, StoreTy)) 8251 LastLegalIntegerType = i+1; 8252 } 8253 } 8254 8255 // Only use vector types if the vector type is larger than the integer type. 8256 // If they are the same, use integers. 8257 bool UseVectorTy = LastLegalVectorType > LastLegalIntegerType && !NoVectors; 8258 unsigned LastLegalType = std::max(LastLegalVectorType, LastLegalIntegerType); 8259 8260 // We add +1 here because the LastXXX variables refer to location while 8261 // the NumElem refers to array/index size. 8262 unsigned NumElem = std::min(LastConsecutiveStore, LastConsecutiveLoad) + 1; 8263 NumElem = std::min(LastLegalType, NumElem); 8264 8265 if (NumElem < 2) 8266 return false; 8267 8268 // The earliest Node in the DAG. 8269 unsigned EarliestNodeUsed = 0; 8270 LSBaseSDNode *EarliestOp = StoreNodes[EarliestNodeUsed].MemNode; 8271 for (unsigned i=1; i<NumElem; ++i) { 8272 // Find a chain for the new wide-store operand. Notice that some 8273 // of the store nodes that we found may not be selected for inclusion 8274 // in the wide store. The chain we use needs to be the chain of the 8275 // earliest store node which is *used* and replaced by the wide store. 8276 if (StoreNodes[i].SequenceNum > StoreNodes[EarliestNodeUsed].SequenceNum) 8277 EarliestNodeUsed = i; 8278 } 8279 8280 // Find if it is better to use vectors or integers to load and store 8281 // to memory. 8282 EVT JointMemOpVT; 8283 if (UseVectorTy) { 8284 JointMemOpVT = EVT::getVectorVT(*DAG.getContext(), MemVT, NumElem); 8285 } else { 8286 unsigned StoreBW = NumElem * ElementSizeBytes * 8; 8287 JointMemOpVT = EVT::getIntegerVT(*DAG.getContext(), StoreBW); 8288 } 8289 8290 SDLoc LoadDL(LoadNodes[0].MemNode); 8291 SDLoc StoreDL(StoreNodes[0].MemNode); 8292 8293 LoadSDNode *FirstLoad = cast<LoadSDNode>(LoadNodes[0].MemNode); 8294 SDValue NewLoad = DAG.getLoad(JointMemOpVT, LoadDL, 8295 FirstLoad->getChain(), 8296 FirstLoad->getBasePtr(), 8297 FirstLoad->getPointerInfo(), 8298 false, false, false, 8299 FirstLoad->getAlignment()); 8300 8301 SDValue NewStore = DAG.getStore(EarliestOp->getChain(), StoreDL, NewLoad, 8302 FirstInChain->getBasePtr(), 8303 FirstInChain->getPointerInfo(), false, false, 8304 FirstInChain->getAlignment()); 8305 8306 // Replace one of the loads with the new load. 8307 LoadSDNode *Ld = cast<LoadSDNode>(LoadNodes[0].MemNode); 8308 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), 8309 SDValue(NewLoad.getNode(), 1)); 8310 8311 // Remove the rest of the load chains. 8312 for (unsigned i = 1; i < NumElem ; ++i) { 8313 // Replace all chain users of the old load nodes with the chain of the new 8314 // load node. 8315 LoadSDNode *Ld = cast<LoadSDNode>(LoadNodes[i].MemNode); 8316 DAG.ReplaceAllUsesOfValueWith(SDValue(Ld, 1), Ld->getChain()); 8317 } 8318 8319 // Replace the first store with the new store. 8320 CombineTo(EarliestOp, NewStore); 8321 // Erase all other stores. 8322 for (unsigned i = 0; i < NumElem ; ++i) { 8323 // Remove all Store nodes. 8324 if (StoreNodes[i].MemNode == EarliestOp) 8325 continue; 8326 StoreSDNode *St = cast<StoreSDNode>(StoreNodes[i].MemNode); 8327 DAG.ReplaceAllUsesOfValueWith(SDValue(St, 0), St->getChain()); 8328 removeFromWorkList(St); 8329 DAG.DeleteNode(St); 8330 } 8331 8332 return true; 8333} 8334 8335SDValue DAGCombiner::visitSTORE(SDNode *N) { 8336 StoreSDNode *ST = cast<StoreSDNode>(N); 8337 SDValue Chain = ST->getChain(); 8338 SDValue Value = ST->getValue(); 8339 SDValue Ptr = ST->getBasePtr(); 8340 8341 // If this is a store of a bit convert, store the input value if the 8342 // resultant store does not need a higher alignment than the original. 8343 if (Value.getOpcode() == ISD::BITCAST && !ST->isTruncatingStore() && 8344 ST->isUnindexed()) { 8345 unsigned OrigAlign = ST->getAlignment(); 8346 EVT SVT = Value.getOperand(0).getValueType(); 8347 unsigned Align = TLI.getDataLayout()-> 8348 getABITypeAlignment(SVT.getTypeForEVT(*DAG.getContext())); 8349 if (Align <= OrigAlign && 8350 ((!LegalOperations && !ST->isVolatile()) || 8351 TLI.isOperationLegalOrCustom(ISD::STORE, SVT))) 8352 return DAG.getStore(Chain, SDLoc(N), Value.getOperand(0), 8353 Ptr, ST->getPointerInfo(), ST->isVolatile(), 8354 ST->isNonTemporal(), OrigAlign); 8355 } 8356 8357 // Turn 'store undef, Ptr' -> nothing. 8358 if (Value.getOpcode() == ISD::UNDEF && ST->isUnindexed()) 8359 return Chain; 8360 8361 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 8362 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) { 8363 // NOTE: If the original store is volatile, this transform must not increase 8364 // the number of stores. For example, on x86-32 an f64 can be stored in one 8365 // processor operation but an i64 (which is not legal) requires two. So the 8366 // transform should not be done in this case. 8367 if (Value.getOpcode() != ISD::TargetConstantFP) { 8368 SDValue Tmp; 8369 switch (CFP->getValueType(0).getSimpleVT().SimpleTy) { 8370 default: llvm_unreachable("Unknown FP type"); 8371 case MVT::f16: // We don't do this for these yet. 8372 case MVT::f80: 8373 case MVT::f128: 8374 case MVT::ppcf128: 8375 break; 8376 case MVT::f32: 8377 if ((isTypeLegal(MVT::i32) && !LegalOperations && !ST->isVolatile()) || 8378 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) { 8379 Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF(). 8380 bitcastToAPInt().getZExtValue(), MVT::i32); 8381 return DAG.getStore(Chain, SDLoc(N), Tmp, 8382 Ptr, ST->getPointerInfo(), ST->isVolatile(), 8383 ST->isNonTemporal(), ST->getAlignment()); 8384 } 8385 break; 8386 case MVT::f64: 8387 if ((TLI.isTypeLegal(MVT::i64) && !LegalOperations && 8388 !ST->isVolatile()) || 8389 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i64)) { 8390 Tmp = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt(). 8391 getZExtValue(), MVT::i64); 8392 return DAG.getStore(Chain, SDLoc(N), Tmp, 8393 Ptr, ST->getPointerInfo(), ST->isVolatile(), 8394 ST->isNonTemporal(), ST->getAlignment()); 8395 } 8396 8397 if (!ST->isVolatile() && 8398 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) { 8399 // Many FP stores are not made apparent until after legalize, e.g. for 8400 // argument passing. Since this is so common, custom legalize the 8401 // 64-bit integer store into two 32-bit stores. 8402 uint64_t Val = CFP->getValueAPF().bitcastToAPInt().getZExtValue(); 8403 SDValue Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32); 8404 SDValue Hi = DAG.getConstant(Val >> 32, MVT::i32); 8405 if (TLI.isBigEndian()) std::swap(Lo, Hi); 8406 8407 unsigned Alignment = ST->getAlignment(); 8408 bool isVolatile = ST->isVolatile(); 8409 bool isNonTemporal = ST->isNonTemporal(); 8410 8411 SDValue St0 = DAG.getStore(Chain, SDLoc(ST), Lo, 8412 Ptr, ST->getPointerInfo(), 8413 isVolatile, isNonTemporal, 8414 ST->getAlignment()); 8415 Ptr = DAG.getNode(ISD::ADD, SDLoc(N), Ptr.getValueType(), Ptr, 8416 DAG.getConstant(4, Ptr.getValueType())); 8417 Alignment = MinAlign(Alignment, 4U); 8418 SDValue St1 = DAG.getStore(Chain, SDLoc(ST), Hi, 8419 Ptr, ST->getPointerInfo().getWithOffset(4), 8420 isVolatile, isNonTemporal, 8421 Alignment); 8422 return DAG.getNode(ISD::TokenFactor, SDLoc(N), MVT::Other, 8423 St0, St1); 8424 } 8425 8426 break; 8427 } 8428 } 8429 } 8430 8431 // Try to infer better alignment information than the store already has. 8432 if (OptLevel != CodeGenOpt::None && ST->isUnindexed()) { 8433 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) { 8434 if (Align > ST->getAlignment()) 8435 return DAG.getTruncStore(Chain, SDLoc(N), Value, 8436 Ptr, ST->getPointerInfo(), ST->getMemoryVT(), 8437 ST->isVolatile(), ST->isNonTemporal(), Align); 8438 } 8439 } 8440 8441 // Try transforming a pair floating point load / store ops to integer 8442 // load / store ops. 8443 SDValue NewST = TransformFPLoadStorePair(N); 8444 if (NewST.getNode()) 8445 return NewST; 8446 8447 if (CombinerAA) { 8448 // Walk up chain skipping non-aliasing memory nodes. 8449 SDValue BetterChain = FindBetterChain(N, Chain); 8450 8451 // If there is a better chain. 8452 if (Chain != BetterChain) { 8453 SDValue ReplStore; 8454 8455 // Replace the chain to avoid dependency. 8456 if (ST->isTruncatingStore()) { 8457 ReplStore = DAG.getTruncStore(BetterChain, SDLoc(N), Value, Ptr, 8458 ST->getPointerInfo(), 8459 ST->getMemoryVT(), ST->isVolatile(), 8460 ST->isNonTemporal(), ST->getAlignment()); 8461 } else { 8462 ReplStore = DAG.getStore(BetterChain, SDLoc(N), Value, Ptr, 8463 ST->getPointerInfo(), 8464 ST->isVolatile(), ST->isNonTemporal(), 8465 ST->getAlignment()); 8466 } 8467 8468 // Create token to keep both nodes around. 8469 SDValue Token = DAG.getNode(ISD::TokenFactor, SDLoc(N), 8470 MVT::Other, Chain, ReplStore); 8471 8472 // Make sure the new and old chains are cleaned up. 8473 AddToWorkList(Token.getNode()); 8474 8475 // Don't add users to work list. 8476 return CombineTo(N, Token, false); 8477 } 8478 } 8479 8480 // Try transforming N to an indexed store. 8481 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 8482 return SDValue(N, 0); 8483 8484 // FIXME: is there such a thing as a truncating indexed store? 8485 if (ST->isTruncatingStore() && ST->isUnindexed() && 8486 Value.getValueType().isInteger()) { 8487 // See if we can simplify the input to this truncstore with knowledge that 8488 // only the low bits are being used. For example: 8489 // "truncstore (or (shl x, 8), y), i8" -> "truncstore y, i8" 8490 SDValue Shorter = 8491 GetDemandedBits(Value, 8492 APInt::getLowBitsSet( 8493 Value.getValueType().getScalarType().getSizeInBits(), 8494 ST->getMemoryVT().getScalarType().getSizeInBits())); 8495 AddToWorkList(Value.getNode()); 8496 if (Shorter.getNode()) 8497 return DAG.getTruncStore(Chain, SDLoc(N), Shorter, 8498 Ptr, ST->getPointerInfo(), ST->getMemoryVT(), 8499 ST->isVolatile(), ST->isNonTemporal(), 8500 ST->getAlignment()); 8501 8502 // Otherwise, see if we can simplify the operation with 8503 // SimplifyDemandedBits, which only works if the value has a single use. 8504 if (SimplifyDemandedBits(Value, 8505 APInt::getLowBitsSet( 8506 Value.getValueType().getScalarType().getSizeInBits(), 8507 ST->getMemoryVT().getScalarType().getSizeInBits()))) 8508 return SDValue(N, 0); 8509 } 8510 8511 // If this is a load followed by a store to the same location, then the store 8512 // is dead/noop. 8513 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Value)) { 8514 if (Ld->getBasePtr() == Ptr && ST->getMemoryVT() == Ld->getMemoryVT() && 8515 ST->isUnindexed() && !ST->isVolatile() && 8516 // There can't be any side effects between the load and store, such as 8517 // a call or store. 8518 Chain.reachesChainWithoutSideEffects(SDValue(Ld, 1))) { 8519 // The store is dead, remove it. 8520 return Chain; 8521 } 8522 } 8523 8524 // If this is an FP_ROUND or TRUNC followed by a store, fold this into a 8525 // truncating store. We can do this even if this is already a truncstore. 8526 if ((Value.getOpcode() == ISD::FP_ROUND || Value.getOpcode() == ISD::TRUNCATE) 8527 && Value.getNode()->hasOneUse() && ST->isUnindexed() && 8528 TLI.isTruncStoreLegal(Value.getOperand(0).getValueType(), 8529 ST->getMemoryVT())) { 8530 return DAG.getTruncStore(Chain, SDLoc(N), Value.getOperand(0), 8531 Ptr, ST->getPointerInfo(), ST->getMemoryVT(), 8532 ST->isVolatile(), ST->isNonTemporal(), 8533 ST->getAlignment()); 8534 } 8535 8536 // Only perform this optimization before the types are legal, because we 8537 // don't want to perform this optimization on every DAGCombine invocation. 8538 if (!LegalTypes) { 8539 bool EverChanged = false; 8540 8541 do { 8542 // There can be multiple store sequences on the same chain. 8543 // Keep trying to merge store sequences until we are unable to do so 8544 // or until we merge the last store on the chain. 8545 bool Changed = MergeConsecutiveStores(ST); 8546 EverChanged |= Changed; 8547 if (!Changed) break; 8548 } while (ST->getOpcode() != ISD::DELETED_NODE); 8549 8550 if (EverChanged) 8551 return SDValue(N, 0); 8552 } 8553 8554 return ReduceLoadOpStoreWidth(N); 8555} 8556 8557SDValue DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) { 8558 SDValue InVec = N->getOperand(0); 8559 SDValue InVal = N->getOperand(1); 8560 SDValue EltNo = N->getOperand(2); 8561 SDLoc dl(N); 8562 8563 // If the inserted element is an UNDEF, just use the input vector. 8564 if (InVal.getOpcode() == ISD::UNDEF) 8565 return InVec; 8566 8567 EVT VT = InVec.getValueType(); 8568 8569 // If we can't generate a legal BUILD_VECTOR, exit 8570 if (LegalOperations && !TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) 8571 return SDValue(); 8572 8573 // Check that we know which element is being inserted 8574 if (!isa<ConstantSDNode>(EltNo)) 8575 return SDValue(); 8576 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 8577 8578 // Check that the operand is a BUILD_VECTOR (or UNDEF, which can essentially 8579 // be converted to a BUILD_VECTOR). Fill in the Ops vector with the 8580 // vector elements. 8581 SmallVector<SDValue, 8> Ops; 8582 if (InVec.getOpcode() == ISD::BUILD_VECTOR) { 8583 Ops.append(InVec.getNode()->op_begin(), 8584 InVec.getNode()->op_end()); 8585 } else if (InVec.getOpcode() == ISD::UNDEF) { 8586 unsigned NElts = VT.getVectorNumElements(); 8587 Ops.append(NElts, DAG.getUNDEF(InVal.getValueType())); 8588 } else { 8589 return SDValue(); 8590 } 8591 8592 // Insert the element 8593 if (Elt < Ops.size()) { 8594 // All the operands of BUILD_VECTOR must have the same type; 8595 // we enforce that here. 8596 EVT OpVT = Ops[0].getValueType(); 8597 if (InVal.getValueType() != OpVT) 8598 InVal = OpVT.bitsGT(InVal.getValueType()) ? 8599 DAG.getNode(ISD::ANY_EXTEND, dl, OpVT, InVal) : 8600 DAG.getNode(ISD::TRUNCATE, dl, OpVT, InVal); 8601 Ops[Elt] = InVal; 8602 } 8603 8604 // Return the new vector 8605 return DAG.getNode(ISD::BUILD_VECTOR, dl, 8606 VT, &Ops[0], Ops.size()); 8607} 8608 8609SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) { 8610 // (vextract (scalar_to_vector val, 0) -> val 8611 SDValue InVec = N->getOperand(0); 8612 EVT VT = InVec.getValueType(); 8613 EVT NVT = N->getValueType(0); 8614 8615 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) { 8616 // Check if the result type doesn't match the inserted element type. A 8617 // SCALAR_TO_VECTOR may truncate the inserted element and the 8618 // EXTRACT_VECTOR_ELT may widen the extracted vector. 8619 SDValue InOp = InVec.getOperand(0); 8620 if (InOp.getValueType() != NVT) { 8621 assert(InOp.getValueType().isInteger() && NVT.isInteger()); 8622 return DAG.getSExtOrTrunc(InOp, SDLoc(InVec), NVT); 8623 } 8624 return InOp; 8625 } 8626 8627 SDValue EltNo = N->getOperand(1); 8628 bool ConstEltNo = isa<ConstantSDNode>(EltNo); 8629 8630 // Transform: (EXTRACT_VECTOR_ELT( VECTOR_SHUFFLE )) -> EXTRACT_VECTOR_ELT. 8631 // We only perform this optimization before the op legalization phase because 8632 // we may introduce new vector instructions which are not backed by TD 8633 // patterns. For example on AVX, extracting elements from a wide vector 8634 // without using extract_subvector. 8635 if (InVec.getOpcode() == ISD::VECTOR_SHUFFLE 8636 && ConstEltNo && !LegalOperations) { 8637 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 8638 int NumElem = VT.getVectorNumElements(); 8639 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(InVec); 8640 // Find the new index to extract from. 8641 int OrigElt = SVOp->getMaskElt(Elt); 8642 8643 // Extracting an undef index is undef. 8644 if (OrigElt == -1) 8645 return DAG.getUNDEF(NVT); 8646 8647 // Select the right vector half to extract from. 8648 if (OrigElt < NumElem) { 8649 InVec = InVec->getOperand(0); 8650 } else { 8651 InVec = InVec->getOperand(1); 8652 OrigElt -= NumElem; 8653 } 8654 8655 EVT IndexTy = N->getOperand(1).getValueType(); 8656 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(N), NVT, 8657 InVec, DAG.getConstant(OrigElt, IndexTy)); 8658 } 8659 8660 // Perform only after legalization to ensure build_vector / vector_shuffle 8661 // optimizations have already been done. 8662 if (!LegalOperations) return SDValue(); 8663 8664 // (vextract (v4f32 load $addr), c) -> (f32 load $addr+c*size) 8665 // (vextract (v4f32 s2v (f32 load $addr)), c) -> (f32 load $addr+c*size) 8666 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), 0) -> (f32 load $addr) 8667 8668 if (ConstEltNo) { 8669 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 8670 bool NewLoad = false; 8671 bool BCNumEltsChanged = false; 8672 EVT ExtVT = VT.getVectorElementType(); 8673 EVT LVT = ExtVT; 8674 8675 // If the result of load has to be truncated, then it's not necessarily 8676 // profitable. 8677 if (NVT.bitsLT(LVT) && !TLI.isTruncateFree(LVT, NVT)) 8678 return SDValue(); 8679 8680 if (InVec.getOpcode() == ISD::BITCAST) { 8681 // Don't duplicate a load with other uses. 8682 if (!InVec.hasOneUse()) 8683 return SDValue(); 8684 8685 EVT BCVT = InVec.getOperand(0).getValueType(); 8686 if (!BCVT.isVector() || ExtVT.bitsGT(BCVT.getVectorElementType())) 8687 return SDValue(); 8688 if (VT.getVectorNumElements() != BCVT.getVectorNumElements()) 8689 BCNumEltsChanged = true; 8690 InVec = InVec.getOperand(0); 8691 ExtVT = BCVT.getVectorElementType(); 8692 NewLoad = true; 8693 } 8694 8695 LoadSDNode *LN0 = NULL; 8696 const ShuffleVectorSDNode *SVN = NULL; 8697 if (ISD::isNormalLoad(InVec.getNode())) { 8698 LN0 = cast<LoadSDNode>(InVec); 8699 } else if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR && 8700 InVec.getOperand(0).getValueType() == ExtVT && 8701 ISD::isNormalLoad(InVec.getOperand(0).getNode())) { 8702 // Don't duplicate a load with other uses. 8703 if (!InVec.hasOneUse()) 8704 return SDValue(); 8705 8706 LN0 = cast<LoadSDNode>(InVec.getOperand(0)); 8707 } else if ((SVN = dyn_cast<ShuffleVectorSDNode>(InVec))) { 8708 // (vextract (vector_shuffle (load $addr), v2, <1, u, u, u>), 1) 8709 // => 8710 // (load $addr+1*size) 8711 8712 // Don't duplicate a load with other uses. 8713 if (!InVec.hasOneUse()) 8714 return SDValue(); 8715 8716 // If the bit convert changed the number of elements, it is unsafe 8717 // to examine the mask. 8718 if (BCNumEltsChanged) 8719 return SDValue(); 8720 8721 // Select the input vector, guarding against out of range extract vector. 8722 unsigned NumElems = VT.getVectorNumElements(); 8723 int Idx = (Elt > (int)NumElems) ? -1 : SVN->getMaskElt(Elt); 8724 InVec = (Idx < (int)NumElems) ? InVec.getOperand(0) : InVec.getOperand(1); 8725 8726 if (InVec.getOpcode() == ISD::BITCAST) { 8727 // Don't duplicate a load with other uses. 8728 if (!InVec.hasOneUse()) 8729 return SDValue(); 8730 8731 InVec = InVec.getOperand(0); 8732 } 8733 if (ISD::isNormalLoad(InVec.getNode())) { 8734 LN0 = cast<LoadSDNode>(InVec); 8735 Elt = (Idx < (int)NumElems) ? Idx : Idx - (int)NumElems; 8736 } 8737 } 8738 8739 // Make sure we found a non-volatile load and the extractelement is 8740 // the only use. 8741 if (!LN0 || !LN0->hasNUsesOfValue(1,0) || LN0->isVolatile()) 8742 return SDValue(); 8743 8744 // If Idx was -1 above, Elt is going to be -1, so just return undef. 8745 if (Elt == -1) 8746 return DAG.getUNDEF(LVT); 8747 8748 unsigned Align = LN0->getAlignment(); 8749 if (NewLoad) { 8750 // Check the resultant load doesn't need a higher alignment than the 8751 // original load. 8752 unsigned NewAlign = 8753 TLI.getDataLayout() 8754 ->getABITypeAlignment(LVT.getTypeForEVT(*DAG.getContext())); 8755 8756 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, LVT)) 8757 return SDValue(); 8758 8759 Align = NewAlign; 8760 } 8761 8762 SDValue NewPtr = LN0->getBasePtr(); 8763 unsigned PtrOff = 0; 8764 8765 if (Elt) { 8766 PtrOff = LVT.getSizeInBits() * Elt / 8; 8767 EVT PtrType = NewPtr.getValueType(); 8768 if (TLI.isBigEndian()) 8769 PtrOff = VT.getSizeInBits() / 8 - PtrOff; 8770 NewPtr = DAG.getNode(ISD::ADD, SDLoc(N), PtrType, NewPtr, 8771 DAG.getConstant(PtrOff, PtrType)); 8772 } 8773 8774 // The replacement we need to do here is a little tricky: we need to 8775 // replace an extractelement of a load with a load. 8776 // Use ReplaceAllUsesOfValuesWith to do the replacement. 8777 // Note that this replacement assumes that the extractvalue is the only 8778 // use of the load; that's okay because we don't want to perform this 8779 // transformation in other cases anyway. 8780 SDValue Load; 8781 SDValue Chain; 8782 if (NVT.bitsGT(LVT)) { 8783 // If the result type of vextract is wider than the load, then issue an 8784 // extending load instead. 8785 ISD::LoadExtType ExtType = TLI.isLoadExtLegal(ISD::ZEXTLOAD, LVT) 8786 ? ISD::ZEXTLOAD : ISD::EXTLOAD; 8787 Load = DAG.getExtLoad(ExtType, SDLoc(N), NVT, LN0->getChain(), 8788 NewPtr, LN0->getPointerInfo().getWithOffset(PtrOff), 8789 LVT, LN0->isVolatile(), LN0->isNonTemporal(),Align); 8790 Chain = Load.getValue(1); 8791 } else { 8792 Load = DAG.getLoad(LVT, SDLoc(N), LN0->getChain(), NewPtr, 8793 LN0->getPointerInfo().getWithOffset(PtrOff), 8794 LN0->isVolatile(), LN0->isNonTemporal(), 8795 LN0->isInvariant(), Align); 8796 Chain = Load.getValue(1); 8797 if (NVT.bitsLT(LVT)) 8798 Load = DAG.getNode(ISD::TRUNCATE, SDLoc(N), NVT, Load); 8799 else 8800 Load = DAG.getNode(ISD::BITCAST, SDLoc(N), NVT, Load); 8801 } 8802 WorkListRemover DeadNodes(*this); 8803 SDValue From[] = { SDValue(N, 0), SDValue(LN0,1) }; 8804 SDValue To[] = { Load, Chain }; 8805 DAG.ReplaceAllUsesOfValuesWith(From, To, 2); 8806 // Since we're explcitly calling ReplaceAllUses, add the new node to the 8807 // worklist explicitly as well. 8808 AddToWorkList(Load.getNode()); 8809 AddUsersToWorkList(Load.getNode()); // Add users too 8810 // Make sure to revisit this node to clean it up; it will usually be dead. 8811 AddToWorkList(N); 8812 return SDValue(N, 0); 8813 } 8814 8815 return SDValue(); 8816} 8817 8818// Simplify (build_vec (ext )) to (bitcast (build_vec )) 8819SDValue DAGCombiner::reduceBuildVecExtToExtBuildVec(SDNode *N) { 8820 // We perform this optimization post type-legalization because 8821 // the type-legalizer often scalarizes integer-promoted vectors. 8822 // Performing this optimization before may create bit-casts which 8823 // will be type-legalized to complex code sequences. 8824 // We perform this optimization only before the operation legalizer because we 8825 // may introduce illegal operations. 8826 if (Level != AfterLegalizeVectorOps && Level != AfterLegalizeTypes) 8827 return SDValue(); 8828 8829 unsigned NumInScalars = N->getNumOperands(); 8830 SDLoc dl(N); 8831 EVT VT = N->getValueType(0); 8832 8833 // Check to see if this is a BUILD_VECTOR of a bunch of values 8834 // which come from any_extend or zero_extend nodes. If so, we can create 8835 // a new BUILD_VECTOR using bit-casts which may enable other BUILD_VECTOR 8836 // optimizations. We do not handle sign-extend because we can't fill the sign 8837 // using shuffles. 8838 EVT SourceType = MVT::Other; 8839 bool AllAnyExt = true; 8840 8841 for (unsigned i = 0; i != NumInScalars; ++i) { 8842 SDValue In = N->getOperand(i); 8843 // Ignore undef inputs. 8844 if (In.getOpcode() == ISD::UNDEF) continue; 8845 8846 bool AnyExt = In.getOpcode() == ISD::ANY_EXTEND; 8847 bool ZeroExt = In.getOpcode() == ISD::ZERO_EXTEND; 8848 8849 // Abort if the element is not an extension. 8850 if (!ZeroExt && !AnyExt) { 8851 SourceType = MVT::Other; 8852 break; 8853 } 8854 8855 // The input is a ZeroExt or AnyExt. Check the original type. 8856 EVT InTy = In.getOperand(0).getValueType(); 8857 8858 // Check that all of the widened source types are the same. 8859 if (SourceType == MVT::Other) 8860 // First time. 8861 SourceType = InTy; 8862 else if (InTy != SourceType) { 8863 // Multiple income types. Abort. 8864 SourceType = MVT::Other; 8865 break; 8866 } 8867 8868 // Check if all of the extends are ANY_EXTENDs. 8869 AllAnyExt &= AnyExt; 8870 } 8871 8872 // In order to have valid types, all of the inputs must be extended from the 8873 // same source type and all of the inputs must be any or zero extend. 8874 // Scalar sizes must be a power of two. 8875 EVT OutScalarTy = VT.getScalarType(); 8876 bool ValidTypes = SourceType != MVT::Other && 8877 isPowerOf2_32(OutScalarTy.getSizeInBits()) && 8878 isPowerOf2_32(SourceType.getSizeInBits()); 8879 8880 // Create a new simpler BUILD_VECTOR sequence which other optimizations can 8881 // turn into a single shuffle instruction. 8882 if (!ValidTypes) 8883 return SDValue(); 8884 8885 bool isLE = TLI.isLittleEndian(); 8886 unsigned ElemRatio = OutScalarTy.getSizeInBits()/SourceType.getSizeInBits(); 8887 assert(ElemRatio > 1 && "Invalid element size ratio"); 8888 SDValue Filler = AllAnyExt ? DAG.getUNDEF(SourceType): 8889 DAG.getConstant(0, SourceType); 8890 8891 unsigned NewBVElems = ElemRatio * VT.getVectorNumElements(); 8892 SmallVector<SDValue, 8> Ops(NewBVElems, Filler); 8893 8894 // Populate the new build_vector 8895 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { 8896 SDValue Cast = N->getOperand(i); 8897 assert((Cast.getOpcode() == ISD::ANY_EXTEND || 8898 Cast.getOpcode() == ISD::ZERO_EXTEND || 8899 Cast.getOpcode() == ISD::UNDEF) && "Invalid cast opcode"); 8900 SDValue In; 8901 if (Cast.getOpcode() == ISD::UNDEF) 8902 In = DAG.getUNDEF(SourceType); 8903 else 8904 In = Cast->getOperand(0); 8905 unsigned Index = isLE ? (i * ElemRatio) : 8906 (i * ElemRatio + (ElemRatio - 1)); 8907 8908 assert(Index < Ops.size() && "Invalid index"); 8909 Ops[Index] = In; 8910 } 8911 8912 // The type of the new BUILD_VECTOR node. 8913 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), SourceType, NewBVElems); 8914 assert(VecVT.getSizeInBits() == VT.getSizeInBits() && 8915 "Invalid vector size"); 8916 // Check if the new vector type is legal. 8917 if (!isTypeLegal(VecVT)) return SDValue(); 8918 8919 // Make the new BUILD_VECTOR. 8920 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, VecVT, &Ops[0], Ops.size()); 8921 8922 // The new BUILD_VECTOR node has the potential to be further optimized. 8923 AddToWorkList(BV.getNode()); 8924 // Bitcast to the desired type. 8925 return DAG.getNode(ISD::BITCAST, dl, VT, BV); 8926} 8927 8928SDValue DAGCombiner::reduceBuildVecConvertToConvertBuildVec(SDNode *N) { 8929 EVT VT = N->getValueType(0); 8930 8931 unsigned NumInScalars = N->getNumOperands(); 8932 SDLoc dl(N); 8933 8934 EVT SrcVT = MVT::Other; 8935 unsigned Opcode = ISD::DELETED_NODE; 8936 unsigned NumDefs = 0; 8937 8938 for (unsigned i = 0; i != NumInScalars; ++i) { 8939 SDValue In = N->getOperand(i); 8940 unsigned Opc = In.getOpcode(); 8941 8942 if (Opc == ISD::UNDEF) 8943 continue; 8944 8945 // If all scalar values are floats and converted from integers. 8946 if (Opcode == ISD::DELETED_NODE && 8947 (Opc == ISD::UINT_TO_FP || Opc == ISD::SINT_TO_FP)) { 8948 Opcode = Opc; 8949 } 8950 8951 if (Opc != Opcode) 8952 return SDValue(); 8953 8954 EVT InVT = In.getOperand(0).getValueType(); 8955 8956 // If all scalar values are typed differently, bail out. It's chosen to 8957 // simplify BUILD_VECTOR of integer types. 8958 if (SrcVT == MVT::Other) 8959 SrcVT = InVT; 8960 if (SrcVT != InVT) 8961 return SDValue(); 8962 NumDefs++; 8963 } 8964 8965 // If the vector has just one element defined, it's not worth to fold it into 8966 // a vectorized one. 8967 if (NumDefs < 2) 8968 return SDValue(); 8969 8970 assert((Opcode == ISD::UINT_TO_FP || Opcode == ISD::SINT_TO_FP) 8971 && "Should only handle conversion from integer to float."); 8972 assert(SrcVT != MVT::Other && "Cannot determine source type!"); 8973 8974 EVT NVT = EVT::getVectorVT(*DAG.getContext(), SrcVT, NumInScalars); 8975 8976 if (!TLI.isOperationLegalOrCustom(Opcode, NVT)) 8977 return SDValue(); 8978 8979 SmallVector<SDValue, 8> Opnds; 8980 for (unsigned i = 0; i != NumInScalars; ++i) { 8981 SDValue In = N->getOperand(i); 8982 8983 if (In.getOpcode() == ISD::UNDEF) 8984 Opnds.push_back(DAG.getUNDEF(SrcVT)); 8985 else 8986 Opnds.push_back(In.getOperand(0)); 8987 } 8988 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, dl, NVT, 8989 &Opnds[0], Opnds.size()); 8990 AddToWorkList(BV.getNode()); 8991 8992 return DAG.getNode(Opcode, dl, VT, BV); 8993} 8994 8995SDValue DAGCombiner::visitBUILD_VECTOR(SDNode *N) { 8996 unsigned NumInScalars = N->getNumOperands(); 8997 SDLoc dl(N); 8998 EVT VT = N->getValueType(0); 8999 9000 // A vector built entirely of undefs is undef. 9001 if (ISD::allOperandsUndef(N)) 9002 return DAG.getUNDEF(VT); 9003 9004 SDValue V = reduceBuildVecExtToExtBuildVec(N); 9005 if (V.getNode()) 9006 return V; 9007 9008 V = reduceBuildVecConvertToConvertBuildVec(N); 9009 if (V.getNode()) 9010 return V; 9011 9012 // Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT 9013 // operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from 9014 // at most two distinct vectors, turn this into a shuffle node. 9015 9016 // May only combine to shuffle after legalize if shuffle is legal. 9017 if (LegalOperations && 9018 !TLI.isOperationLegalOrCustom(ISD::VECTOR_SHUFFLE, VT)) 9019 return SDValue(); 9020 9021 SDValue VecIn1, VecIn2; 9022 for (unsigned i = 0; i != NumInScalars; ++i) { 9023 // Ignore undef inputs. 9024 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 9025 9026 // If this input is something other than a EXTRACT_VECTOR_ELT with a 9027 // constant index, bail out. 9028 if (N->getOperand(i).getOpcode() != ISD::EXTRACT_VECTOR_ELT || 9029 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) { 9030 VecIn1 = VecIn2 = SDValue(0, 0); 9031 break; 9032 } 9033 9034 // We allow up to two distinct input vectors. 9035 SDValue ExtractedFromVec = N->getOperand(i).getOperand(0); 9036 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2) 9037 continue; 9038 9039 if (VecIn1.getNode() == 0) { 9040 VecIn1 = ExtractedFromVec; 9041 } else if (VecIn2.getNode() == 0) { 9042 VecIn2 = ExtractedFromVec; 9043 } else { 9044 // Too many inputs. 9045 VecIn1 = VecIn2 = SDValue(0, 0); 9046 break; 9047 } 9048 } 9049 9050 // If everything is good, we can make a shuffle operation. 9051 if (VecIn1.getNode()) { 9052 SmallVector<int, 8> Mask; 9053 for (unsigned i = 0; i != NumInScalars; ++i) { 9054 if (N->getOperand(i).getOpcode() == ISD::UNDEF) { 9055 Mask.push_back(-1); 9056 continue; 9057 } 9058 9059 // If extracting from the first vector, just use the index directly. 9060 SDValue Extract = N->getOperand(i); 9061 SDValue ExtVal = Extract.getOperand(1); 9062 if (Extract.getOperand(0) == VecIn1) { 9063 unsigned ExtIndex = cast<ConstantSDNode>(ExtVal)->getZExtValue(); 9064 if (ExtIndex > VT.getVectorNumElements()) 9065 return SDValue(); 9066 9067 Mask.push_back(ExtIndex); 9068 continue; 9069 } 9070 9071 // Otherwise, use InIdx + VecSize 9072 unsigned Idx = cast<ConstantSDNode>(ExtVal)->getZExtValue(); 9073 Mask.push_back(Idx+NumInScalars); 9074 } 9075 9076 // We can't generate a shuffle node with mismatched input and output types. 9077 // Attempt to transform a single input vector to the correct type. 9078 if ((VT != VecIn1.getValueType())) { 9079 // We don't support shuffeling between TWO values of different types. 9080 if (VecIn2.getNode() != 0) 9081 return SDValue(); 9082 9083 // We only support widening of vectors which are half the size of the 9084 // output registers. For example XMM->YMM widening on X86 with AVX. 9085 if (VecIn1.getValueType().getSizeInBits()*2 != VT.getSizeInBits()) 9086 return SDValue(); 9087 9088 // If the input vector type has a different base type to the output 9089 // vector type, bail out. 9090 if (VecIn1.getValueType().getVectorElementType() != 9091 VT.getVectorElementType()) 9092 return SDValue(); 9093 9094 // Widen the input vector by adding undef values. 9095 VecIn1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, 9096 VecIn1, DAG.getUNDEF(VecIn1.getValueType())); 9097 } 9098 9099 // If VecIn2 is unused then change it to undef. 9100 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT); 9101 9102 // Check that we were able to transform all incoming values to the same 9103 // type. 9104 if (VecIn2.getValueType() != VecIn1.getValueType() || 9105 VecIn1.getValueType() != VT) 9106 return SDValue(); 9107 9108 // Only type-legal BUILD_VECTOR nodes are converted to shuffle nodes. 9109 if (!isTypeLegal(VT)) 9110 return SDValue(); 9111 9112 // Return the new VECTOR_SHUFFLE node. 9113 SDValue Ops[2]; 9114 Ops[0] = VecIn1; 9115 Ops[1] = VecIn2; 9116 return DAG.getVectorShuffle(VT, dl, Ops[0], Ops[1], &Mask[0]); 9117 } 9118 9119 return SDValue(); 9120} 9121 9122SDValue DAGCombiner::visitCONCAT_VECTORS(SDNode *N) { 9123 // TODO: Check to see if this is a CONCAT_VECTORS of a bunch of 9124 // EXTRACT_SUBVECTOR operations. If so, and if the EXTRACT_SUBVECTOR vector 9125 // inputs come from at most two distinct vectors, turn this into a shuffle 9126 // node. 9127 9128 // If we only have one input vector, we don't need to do any concatenation. 9129 if (N->getNumOperands() == 1) 9130 return N->getOperand(0); 9131 9132 // Check if all of the operands are undefs. 9133 if (ISD::allOperandsUndef(N)) 9134 return DAG.getUNDEF(N->getValueType(0)); 9135 9136 // Type legalization of vectors and DAG canonicalization of SHUFFLE_VECTOR 9137 // nodes often generate nop CONCAT_VECTOR nodes. 9138 // Scan the CONCAT_VECTOR operands and look for a CONCAT operations that 9139 // place the incoming vectors at the exact same location. 9140 SDValue SingleSource = SDValue(); 9141 unsigned PartNumElem = N->getOperand(0).getValueType().getVectorNumElements(); 9142 9143 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { 9144 SDValue Op = N->getOperand(i); 9145 9146 if (Op.getOpcode() == ISD::UNDEF) 9147 continue; 9148 9149 // Check if this is the identity extract: 9150 if (Op.getOpcode() != ISD::EXTRACT_SUBVECTOR) 9151 return SDValue(); 9152 9153 // Find the single incoming vector for the extract_subvector. 9154 if (SingleSource.getNode()) { 9155 if (Op.getOperand(0) != SingleSource) 9156 return SDValue(); 9157 } else { 9158 SingleSource = Op.getOperand(0); 9159 9160 // Check the source type is the same as the type of the result. 9161 // If not, this concat may extend the vector, so we can not 9162 // optimize it away. 9163 if (SingleSource.getValueType() != N->getValueType(0)) 9164 return SDValue(); 9165 } 9166 9167 unsigned IdentityIndex = i * PartNumElem; 9168 ConstantSDNode *CS = dyn_cast<ConstantSDNode>(Op.getOperand(1)); 9169 // The extract index must be constant. 9170 if (!CS) 9171 return SDValue(); 9172 9173 // Check that we are reading from the identity index. 9174 if (CS->getZExtValue() != IdentityIndex) 9175 return SDValue(); 9176 } 9177 9178 if (SingleSource.getNode()) 9179 return SingleSource; 9180 9181 return SDValue(); 9182} 9183 9184SDValue DAGCombiner::visitEXTRACT_SUBVECTOR(SDNode* N) { 9185 EVT NVT = N->getValueType(0); 9186 SDValue V = N->getOperand(0); 9187 9188 if (V->getOpcode() == ISD::CONCAT_VECTORS) { 9189 // Combine: 9190 // (extract_subvec (concat V1, V2, ...), i) 9191 // Into: 9192 // Vi if possible 9193 // Only operand 0 is checked as 'concat' assumes all inputs of the same type. 9194 if (V->getOperand(0).getValueType() != NVT) 9195 return SDValue(); 9196 unsigned Idx = dyn_cast<ConstantSDNode>(N->getOperand(1))->getZExtValue(); 9197 unsigned NumElems = NVT.getVectorNumElements(); 9198 assert((Idx % NumElems) == 0 && 9199 "IDX in concat is not a multiple of the result vector length."); 9200 return V->getOperand(Idx / NumElems); 9201 } 9202 9203 // Skip bitcasting 9204 if (V->getOpcode() == ISD::BITCAST) 9205 V = V.getOperand(0); 9206 9207 if (V->getOpcode() == ISD::INSERT_SUBVECTOR) { 9208 SDLoc dl(N); 9209 // Handle only simple case where vector being inserted and vector 9210 // being extracted are of same type, and are half size of larger vectors. 9211 EVT BigVT = V->getOperand(0).getValueType(); 9212 EVT SmallVT = V->getOperand(1).getValueType(); 9213 if (!NVT.bitsEq(SmallVT) || NVT.getSizeInBits()*2 != BigVT.getSizeInBits()) 9214 return SDValue(); 9215 9216 // Only handle cases where both indexes are constants with the same type. 9217 ConstantSDNode *ExtIdx = dyn_cast<ConstantSDNode>(N->getOperand(1)); 9218 ConstantSDNode *InsIdx = dyn_cast<ConstantSDNode>(V->getOperand(2)); 9219 9220 if (InsIdx && ExtIdx && 9221 InsIdx->getValueType(0).getSizeInBits() <= 64 && 9222 ExtIdx->getValueType(0).getSizeInBits() <= 64) { 9223 // Combine: 9224 // (extract_subvec (insert_subvec V1, V2, InsIdx), ExtIdx) 9225 // Into: 9226 // indices are equal or bit offsets are equal => V1 9227 // otherwise => (extract_subvec V1, ExtIdx) 9228 if (InsIdx->getZExtValue() * SmallVT.getScalarType().getSizeInBits() == 9229 ExtIdx->getZExtValue() * NVT.getScalarType().getSizeInBits()) 9230 return DAG.getNode(ISD::BITCAST, dl, NVT, V->getOperand(1)); 9231 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, NVT, 9232 DAG.getNode(ISD::BITCAST, dl, 9233 N->getOperand(0).getValueType(), 9234 V->getOperand(0)), N->getOperand(1)); 9235 } 9236 } 9237 9238 return SDValue(); 9239} 9240 9241// Tries to turn a shuffle of two CONCAT_VECTORS into a single concat. 9242static SDValue partitionShuffleOfConcats(SDNode *N, SelectionDAG &DAG) { 9243 EVT VT = N->getValueType(0); 9244 unsigned NumElts = VT.getVectorNumElements(); 9245 9246 SDValue N0 = N->getOperand(0); 9247 SDValue N1 = N->getOperand(1); 9248 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N); 9249 9250 SmallVector<SDValue, 4> Ops; 9251 EVT ConcatVT = N0.getOperand(0).getValueType(); 9252 unsigned NumElemsPerConcat = ConcatVT.getVectorNumElements(); 9253 unsigned NumConcats = NumElts / NumElemsPerConcat; 9254 9255 // Look at every vector that's inserted. We're looking for exact 9256 // subvector-sized copies from a concatenated vector 9257 for (unsigned I = 0; I != NumConcats; ++I) { 9258 // Make sure we're dealing with a copy. 9259 unsigned Begin = I * NumElemsPerConcat; 9260 bool AllUndef = true, NoUndef = true; 9261 for (unsigned J = Begin; J != Begin + NumElemsPerConcat; ++J) { 9262 if (SVN->getMaskElt(J) >= 0) 9263 AllUndef = false; 9264 else 9265 NoUndef = false; 9266 } 9267 9268 if (NoUndef) { 9269 if (SVN->getMaskElt(Begin) % NumElemsPerConcat != 0) 9270 return SDValue(); 9271 9272 for (unsigned J = 1; J != NumElemsPerConcat; ++J) 9273 if (SVN->getMaskElt(Begin + J - 1) + 1 != SVN->getMaskElt(Begin + J)) 9274 return SDValue(); 9275 9276 unsigned FirstElt = SVN->getMaskElt(Begin) / NumElemsPerConcat; 9277 if (FirstElt < N0.getNumOperands()) 9278 Ops.push_back(N0.getOperand(FirstElt)); 9279 else 9280 Ops.push_back(N1.getOperand(FirstElt - N0.getNumOperands())); 9281 9282 } else if (AllUndef) { 9283 Ops.push_back(DAG.getUNDEF(N0.getOperand(0).getValueType())); 9284 } else { // Mixed with general masks and undefs, can't do optimization. 9285 return SDValue(); 9286 } 9287 } 9288 9289 return DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(N), VT, Ops.data(), 9290 Ops.size()); 9291} 9292 9293SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) { 9294 EVT VT = N->getValueType(0); 9295 unsigned NumElts = VT.getVectorNumElements(); 9296 9297 SDValue N0 = N->getOperand(0); 9298 SDValue N1 = N->getOperand(1); 9299 9300 assert(N0.getValueType() == VT && "Vector shuffle must be normalized in DAG"); 9301 9302 // Canonicalize shuffle undef, undef -> undef 9303 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF) 9304 return DAG.getUNDEF(VT); 9305 9306 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N); 9307 9308 // Canonicalize shuffle v, v -> v, undef 9309 if (N0 == N1) { 9310 SmallVector<int, 8> NewMask; 9311 for (unsigned i = 0; i != NumElts; ++i) { 9312 int Idx = SVN->getMaskElt(i); 9313 if (Idx >= (int)NumElts) Idx -= NumElts; 9314 NewMask.push_back(Idx); 9315 } 9316 return DAG.getVectorShuffle(VT, SDLoc(N), N0, DAG.getUNDEF(VT), 9317 &NewMask[0]); 9318 } 9319 9320 // Canonicalize shuffle undef, v -> v, undef. Commute the shuffle mask. 9321 if (N0.getOpcode() == ISD::UNDEF) { 9322 SmallVector<int, 8> NewMask; 9323 for (unsigned i = 0; i != NumElts; ++i) { 9324 int Idx = SVN->getMaskElt(i); 9325 if (Idx >= 0) { 9326 if (Idx < (int)NumElts) 9327 Idx += NumElts; 9328 else 9329 Idx -= NumElts; 9330 } 9331 NewMask.push_back(Idx); 9332 } 9333 return DAG.getVectorShuffle(VT, SDLoc(N), N1, DAG.getUNDEF(VT), 9334 &NewMask[0]); 9335 } 9336 9337 // Remove references to rhs if it is undef 9338 if (N1.getOpcode() == ISD::UNDEF) { 9339 bool Changed = false; 9340 SmallVector<int, 8> NewMask; 9341 for (unsigned i = 0; i != NumElts; ++i) { 9342 int Idx = SVN->getMaskElt(i); 9343 if (Idx >= (int)NumElts) { 9344 Idx = -1; 9345 Changed = true; 9346 } 9347 NewMask.push_back(Idx); 9348 } 9349 if (Changed) 9350 return DAG.getVectorShuffle(VT, SDLoc(N), N0, N1, &NewMask[0]); 9351 } 9352 9353 // If it is a splat, check if the argument vector is another splat or a 9354 // build_vector with all scalar elements the same. 9355 if (SVN->isSplat() && SVN->getSplatIndex() < (int)NumElts) { 9356 SDNode *V = N0.getNode(); 9357 9358 // If this is a bit convert that changes the element type of the vector but 9359 // not the number of vector elements, look through it. Be careful not to 9360 // look though conversions that change things like v4f32 to v2f64. 9361 if (V->getOpcode() == ISD::BITCAST) { 9362 SDValue ConvInput = V->getOperand(0); 9363 if (ConvInput.getValueType().isVector() && 9364 ConvInput.getValueType().getVectorNumElements() == NumElts) 9365 V = ConvInput.getNode(); 9366 } 9367 9368 if (V->getOpcode() == ISD::BUILD_VECTOR) { 9369 assert(V->getNumOperands() == NumElts && 9370 "BUILD_VECTOR has wrong number of operands"); 9371 SDValue Base; 9372 bool AllSame = true; 9373 for (unsigned i = 0; i != NumElts; ++i) { 9374 if (V->getOperand(i).getOpcode() != ISD::UNDEF) { 9375 Base = V->getOperand(i); 9376 break; 9377 } 9378 } 9379 // Splat of <u, u, u, u>, return <u, u, u, u> 9380 if (!Base.getNode()) 9381 return N0; 9382 for (unsigned i = 0; i != NumElts; ++i) { 9383 if (V->getOperand(i) != Base) { 9384 AllSame = false; 9385 break; 9386 } 9387 } 9388 // Splat of <x, x, x, x>, return <x, x, x, x> 9389 if (AllSame) 9390 return N0; 9391 } 9392 } 9393 9394 if (N0.getOpcode() == ISD::CONCAT_VECTORS && 9395 Level < AfterLegalizeVectorOps && 9396 (N1.getOpcode() == ISD::UNDEF || 9397 (N1.getOpcode() == ISD::CONCAT_VECTORS && 9398 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()))) { 9399 SDValue V = partitionShuffleOfConcats(N, DAG); 9400 9401 if (V.getNode()) 9402 return V; 9403 } 9404 9405 // If this shuffle node is simply a swizzle of another shuffle node, 9406 // and it reverses the swizzle of the previous shuffle then we can 9407 // optimize shuffle(shuffle(x, undef), undef) -> x. 9408 if (N0.getOpcode() == ISD::VECTOR_SHUFFLE && Level < AfterLegalizeDAG && 9409 N1.getOpcode() == ISD::UNDEF) { 9410 9411 ShuffleVectorSDNode *OtherSV = cast<ShuffleVectorSDNode>(N0); 9412 9413 // Shuffle nodes can only reverse shuffles with a single non-undef value. 9414 if (N0.getOperand(1).getOpcode() != ISD::UNDEF) 9415 return SDValue(); 9416 9417 // The incoming shuffle must be of the same type as the result of the 9418 // current shuffle. 9419 assert(OtherSV->getOperand(0).getValueType() == VT && 9420 "Shuffle types don't match"); 9421 9422 for (unsigned i = 0; i != NumElts; ++i) { 9423 int Idx = SVN->getMaskElt(i); 9424 assert(Idx < (int)NumElts && "Index references undef operand"); 9425 // Next, this index comes from the first value, which is the incoming 9426 // shuffle. Adopt the incoming index. 9427 if (Idx >= 0) 9428 Idx = OtherSV->getMaskElt(Idx); 9429 9430 // The combined shuffle must map each index to itself. 9431 if (Idx >= 0 && (unsigned)Idx != i) 9432 return SDValue(); 9433 } 9434 9435 return OtherSV->getOperand(0); 9436 } 9437 9438 return SDValue(); 9439} 9440 9441/// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform 9442/// an AND to a vector_shuffle with the destination vector and a zero vector. 9443/// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==> 9444/// vector_shuffle V, Zero, <0, 4, 2, 4> 9445SDValue DAGCombiner::XformToShuffleWithZero(SDNode *N) { 9446 EVT VT = N->getValueType(0); 9447 SDLoc dl(N); 9448 SDValue LHS = N->getOperand(0); 9449 SDValue RHS = N->getOperand(1); 9450 if (N->getOpcode() == ISD::AND) { 9451 if (RHS.getOpcode() == ISD::BITCAST) 9452 RHS = RHS.getOperand(0); 9453 if (RHS.getOpcode() == ISD::BUILD_VECTOR) { 9454 SmallVector<int, 8> Indices; 9455 unsigned NumElts = RHS.getNumOperands(); 9456 for (unsigned i = 0; i != NumElts; ++i) { 9457 SDValue Elt = RHS.getOperand(i); 9458 if (!isa<ConstantSDNode>(Elt)) 9459 return SDValue(); 9460 9461 if (cast<ConstantSDNode>(Elt)->isAllOnesValue()) 9462 Indices.push_back(i); 9463 else if (cast<ConstantSDNode>(Elt)->isNullValue()) 9464 Indices.push_back(NumElts); 9465 else 9466 return SDValue(); 9467 } 9468 9469 // Let's see if the target supports this vector_shuffle. 9470 EVT RVT = RHS.getValueType(); 9471 if (!TLI.isVectorClearMaskLegal(Indices, RVT)) 9472 return SDValue(); 9473 9474 // Return the new VECTOR_SHUFFLE node. 9475 EVT EltVT = RVT.getVectorElementType(); 9476 SmallVector<SDValue,8> ZeroOps(RVT.getVectorNumElements(), 9477 DAG.getConstant(0, EltVT)); 9478 SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), 9479 RVT, &ZeroOps[0], ZeroOps.size()); 9480 LHS = DAG.getNode(ISD::BITCAST, dl, RVT, LHS); 9481 SDValue Shuf = DAG.getVectorShuffle(RVT, dl, LHS, Zero, &Indices[0]); 9482 return DAG.getNode(ISD::BITCAST, dl, VT, Shuf); 9483 } 9484 } 9485 9486 return SDValue(); 9487} 9488 9489/// SimplifyVBinOp - Visit a binary vector operation, like ADD. 9490SDValue DAGCombiner::SimplifyVBinOp(SDNode *N) { 9491 assert(N->getValueType(0).isVector() && 9492 "SimplifyVBinOp only works on vectors!"); 9493 9494 SDValue LHS = N->getOperand(0); 9495 SDValue RHS = N->getOperand(1); 9496 SDValue Shuffle = XformToShuffleWithZero(N); 9497 if (Shuffle.getNode()) return Shuffle; 9498 9499 // If the LHS and RHS are BUILD_VECTOR nodes, see if we can constant fold 9500 // this operation. 9501 if (LHS.getOpcode() == ISD::BUILD_VECTOR && 9502 RHS.getOpcode() == ISD::BUILD_VECTOR) { 9503 SmallVector<SDValue, 8> Ops; 9504 for (unsigned i = 0, e = LHS.getNumOperands(); i != e; ++i) { 9505 SDValue LHSOp = LHS.getOperand(i); 9506 SDValue RHSOp = RHS.getOperand(i); 9507 // If these two elements can't be folded, bail out. 9508 if ((LHSOp.getOpcode() != ISD::UNDEF && 9509 LHSOp.getOpcode() != ISD::Constant && 9510 LHSOp.getOpcode() != ISD::ConstantFP) || 9511 (RHSOp.getOpcode() != ISD::UNDEF && 9512 RHSOp.getOpcode() != ISD::Constant && 9513 RHSOp.getOpcode() != ISD::ConstantFP)) 9514 break; 9515 9516 // Can't fold divide by zero. 9517 if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV || 9518 N->getOpcode() == ISD::FDIV) { 9519 if ((RHSOp.getOpcode() == ISD::Constant && 9520 cast<ConstantSDNode>(RHSOp.getNode())->isNullValue()) || 9521 (RHSOp.getOpcode() == ISD::ConstantFP && 9522 cast<ConstantFPSDNode>(RHSOp.getNode())->getValueAPF().isZero())) 9523 break; 9524 } 9525 9526 EVT VT = LHSOp.getValueType(); 9527 EVT RVT = RHSOp.getValueType(); 9528 if (RVT != VT) { 9529 // Integer BUILD_VECTOR operands may have types larger than the element 9530 // size (e.g., when the element type is not legal). Prior to type 9531 // legalization, the types may not match between the two BUILD_VECTORS. 9532 // Truncate one of the operands to make them match. 9533 if (RVT.getSizeInBits() > VT.getSizeInBits()) { 9534 RHSOp = DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, RHSOp); 9535 } else { 9536 LHSOp = DAG.getNode(ISD::TRUNCATE, SDLoc(N), RVT, LHSOp); 9537 VT = RVT; 9538 } 9539 } 9540 SDValue FoldOp = DAG.getNode(N->getOpcode(), SDLoc(LHS), VT, 9541 LHSOp, RHSOp); 9542 if (FoldOp.getOpcode() != ISD::UNDEF && 9543 FoldOp.getOpcode() != ISD::Constant && 9544 FoldOp.getOpcode() != ISD::ConstantFP) 9545 break; 9546 Ops.push_back(FoldOp); 9547 AddToWorkList(FoldOp.getNode()); 9548 } 9549 9550 if (Ops.size() == LHS.getNumOperands()) 9551 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), 9552 LHS.getValueType(), &Ops[0], Ops.size()); 9553 } 9554 9555 return SDValue(); 9556} 9557 9558/// SimplifyVUnaryOp - Visit a binary vector operation, like FABS/FNEG. 9559SDValue DAGCombiner::SimplifyVUnaryOp(SDNode *N) { 9560 assert(N->getValueType(0).isVector() && 9561 "SimplifyVUnaryOp only works on vectors!"); 9562 9563 SDValue N0 = N->getOperand(0); 9564 9565 if (N0.getOpcode() != ISD::BUILD_VECTOR) 9566 return SDValue(); 9567 9568 // Operand is a BUILD_VECTOR node, see if we can constant fold it. 9569 SmallVector<SDValue, 8> Ops; 9570 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i) { 9571 SDValue Op = N0.getOperand(i); 9572 if (Op.getOpcode() != ISD::UNDEF && 9573 Op.getOpcode() != ISD::ConstantFP) 9574 break; 9575 EVT EltVT = Op.getValueType(); 9576 SDValue FoldOp = DAG.getNode(N->getOpcode(), SDLoc(N0), EltVT, Op); 9577 if (FoldOp.getOpcode() != ISD::UNDEF && 9578 FoldOp.getOpcode() != ISD::ConstantFP) 9579 break; 9580 Ops.push_back(FoldOp); 9581 AddToWorkList(FoldOp.getNode()); 9582 } 9583 9584 if (Ops.size() != N0.getNumOperands()) 9585 return SDValue(); 9586 9587 return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), 9588 N0.getValueType(), &Ops[0], Ops.size()); 9589} 9590 9591SDValue DAGCombiner::SimplifySelect(SDLoc DL, SDValue N0, 9592 SDValue N1, SDValue N2){ 9593 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!"); 9594 9595 SDValue SCC = SimplifySelectCC(DL, N0.getOperand(0), N0.getOperand(1), N1, N2, 9596 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 9597 9598 // If we got a simplified select_cc node back from SimplifySelectCC, then 9599 // break it down into a new SETCC node, and a new SELECT node, and then return 9600 // the SELECT node, since we were called with a SELECT node. 9601 if (SCC.getNode()) { 9602 // Check to see if we got a select_cc back (to turn into setcc/select). 9603 // Otherwise, just return whatever node we got back, like fabs. 9604 if (SCC.getOpcode() == ISD::SELECT_CC) { 9605 SDValue SETCC = DAG.getNode(ISD::SETCC, SDLoc(N0), 9606 N0.getValueType(), 9607 SCC.getOperand(0), SCC.getOperand(1), 9608 SCC.getOperand(4)); 9609 AddToWorkList(SETCC.getNode()); 9610 return DAG.getSelect(SDLoc(SCC), SCC.getValueType(), 9611 SCC.getOperand(2), SCC.getOperand(3), SETCC); 9612 } 9613 9614 return SCC; 9615 } 9616 return SDValue(); 9617} 9618 9619/// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS 9620/// are the two values being selected between, see if we can simplify the 9621/// select. Callers of this should assume that TheSelect is deleted if this 9622/// returns true. As such, they should return the appropriate thing (e.g. the 9623/// node) back to the top-level of the DAG combiner loop to avoid it being 9624/// looked at. 9625bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDValue LHS, 9626 SDValue RHS) { 9627 9628 // Cannot simplify select with vector condition 9629 if (TheSelect->getOperand(0).getValueType().isVector()) return false; 9630 9631 // If this is a select from two identical things, try to pull the operation 9632 // through the select. 9633 if (LHS.getOpcode() != RHS.getOpcode() || 9634 !LHS.hasOneUse() || !RHS.hasOneUse()) 9635 return false; 9636 9637 // If this is a load and the token chain is identical, replace the select 9638 // of two loads with a load through a select of the address to load from. 9639 // This triggers in things like "select bool X, 10.0, 123.0" after the FP 9640 // constants have been dropped into the constant pool. 9641 if (LHS.getOpcode() == ISD::LOAD) { 9642 LoadSDNode *LLD = cast<LoadSDNode>(LHS); 9643 LoadSDNode *RLD = cast<LoadSDNode>(RHS); 9644 9645 // Token chains must be identical. 9646 if (LHS.getOperand(0) != RHS.getOperand(0) || 9647 // Do not let this transformation reduce the number of volatile loads. 9648 LLD->isVolatile() || RLD->isVolatile() || 9649 // If this is an EXTLOAD, the VT's must match. 9650 LLD->getMemoryVT() != RLD->getMemoryVT() || 9651 // If this is an EXTLOAD, the kind of extension must match. 9652 (LLD->getExtensionType() != RLD->getExtensionType() && 9653 // The only exception is if one of the extensions is anyext. 9654 LLD->getExtensionType() != ISD::EXTLOAD && 9655 RLD->getExtensionType() != ISD::EXTLOAD) || 9656 // FIXME: this discards src value information. This is 9657 // over-conservative. It would be beneficial to be able to remember 9658 // both potential memory locations. Since we are discarding 9659 // src value info, don't do the transformation if the memory 9660 // locations are not in the default address space. 9661 LLD->getPointerInfo().getAddrSpace() != 0 || 9662 RLD->getPointerInfo().getAddrSpace() != 0 || 9663 !TLI.isOperationLegalOrCustom(TheSelect->getOpcode(), 9664 LLD->getBasePtr().getValueType())) 9665 return false; 9666 9667 // Check that the select condition doesn't reach either load. If so, 9668 // folding this will induce a cycle into the DAG. If not, this is safe to 9669 // xform, so create a select of the addresses. 9670 SDValue Addr; 9671 if (TheSelect->getOpcode() == ISD::SELECT) { 9672 SDNode *CondNode = TheSelect->getOperand(0).getNode(); 9673 if ((LLD->hasAnyUseOfValue(1) && LLD->isPredecessorOf(CondNode)) || 9674 (RLD->hasAnyUseOfValue(1) && RLD->isPredecessorOf(CondNode))) 9675 return false; 9676 // The loads must not depend on one another. 9677 if (LLD->isPredecessorOf(RLD) || 9678 RLD->isPredecessorOf(LLD)) 9679 return false; 9680 Addr = DAG.getSelect(SDLoc(TheSelect), 9681 LLD->getBasePtr().getValueType(), 9682 TheSelect->getOperand(0), LLD->getBasePtr(), 9683 RLD->getBasePtr()); 9684 } else { // Otherwise SELECT_CC 9685 SDNode *CondLHS = TheSelect->getOperand(0).getNode(); 9686 SDNode *CondRHS = TheSelect->getOperand(1).getNode(); 9687 9688 if ((LLD->hasAnyUseOfValue(1) && 9689 (LLD->isPredecessorOf(CondLHS) || LLD->isPredecessorOf(CondRHS))) || 9690 (RLD->hasAnyUseOfValue(1) && 9691 (RLD->isPredecessorOf(CondLHS) || RLD->isPredecessorOf(CondRHS)))) 9692 return false; 9693 9694 Addr = DAG.getNode(ISD::SELECT_CC, SDLoc(TheSelect), 9695 LLD->getBasePtr().getValueType(), 9696 TheSelect->getOperand(0), 9697 TheSelect->getOperand(1), 9698 LLD->getBasePtr(), RLD->getBasePtr(), 9699 TheSelect->getOperand(4)); 9700 } 9701 9702 SDValue Load; 9703 if (LLD->getExtensionType() == ISD::NON_EXTLOAD) { 9704 Load = DAG.getLoad(TheSelect->getValueType(0), 9705 SDLoc(TheSelect), 9706 // FIXME: Discards pointer info. 9707 LLD->getChain(), Addr, MachinePointerInfo(), 9708 LLD->isVolatile(), LLD->isNonTemporal(), 9709 LLD->isInvariant(), LLD->getAlignment()); 9710 } else { 9711 Load = DAG.getExtLoad(LLD->getExtensionType() == ISD::EXTLOAD ? 9712 RLD->getExtensionType() : LLD->getExtensionType(), 9713 SDLoc(TheSelect), 9714 TheSelect->getValueType(0), 9715 // FIXME: Discards pointer info. 9716 LLD->getChain(), Addr, MachinePointerInfo(), 9717 LLD->getMemoryVT(), LLD->isVolatile(), 9718 LLD->isNonTemporal(), LLD->getAlignment()); 9719 } 9720 9721 // Users of the select now use the result of the load. 9722 CombineTo(TheSelect, Load); 9723 9724 // Users of the old loads now use the new load's chain. We know the 9725 // old-load value is dead now. 9726 CombineTo(LHS.getNode(), Load.getValue(0), Load.getValue(1)); 9727 CombineTo(RHS.getNode(), Load.getValue(0), Load.getValue(1)); 9728 return true; 9729 } 9730 9731 return false; 9732} 9733 9734/// SimplifySelectCC - Simplify an expression of the form (N0 cond N1) ? N2 : N3 9735/// where 'cond' is the comparison specified by CC. 9736SDValue DAGCombiner::SimplifySelectCC(SDLoc DL, SDValue N0, SDValue N1, 9737 SDValue N2, SDValue N3, 9738 ISD::CondCode CC, bool NotExtCompare) { 9739 // (x ? y : y) -> y. 9740 if (N2 == N3) return N2; 9741 9742 EVT VT = N2.getValueType(); 9743 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 9744 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode()); 9745 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.getNode()); 9746 9747 // Determine if the condition we're dealing with is constant 9748 SDValue SCC = SimplifySetCC(getSetCCResultType(N0.getValueType()), 9749 N0, N1, CC, DL, false); 9750 if (SCC.getNode()) AddToWorkList(SCC.getNode()); 9751 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode()); 9752 9753 // fold select_cc true, x, y -> x 9754 if (SCCC && !SCCC->isNullValue()) 9755 return N2; 9756 // fold select_cc false, x, y -> y 9757 if (SCCC && SCCC->isNullValue()) 9758 return N3; 9759 9760 // Check to see if we can simplify the select into an fabs node 9761 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) { 9762 // Allow either -0.0 or 0.0 9763 if (CFP->getValueAPF().isZero()) { 9764 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs 9765 if ((CC == ISD::SETGE || CC == ISD::SETGT) && 9766 N0 == N2 && N3.getOpcode() == ISD::FNEG && 9767 N2 == N3.getOperand(0)) 9768 return DAG.getNode(ISD::FABS, DL, VT, N0); 9769 9770 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs 9771 if ((CC == ISD::SETLT || CC == ISD::SETLE) && 9772 N0 == N3 && N2.getOpcode() == ISD::FNEG && 9773 N2.getOperand(0) == N3) 9774 return DAG.getNode(ISD::FABS, DL, VT, N3); 9775 } 9776 } 9777 9778 // Turn "(a cond b) ? 1.0f : 2.0f" into "load (tmp + ((a cond b) ? 0 : 4)" 9779 // where "tmp" is a constant pool entry containing an array with 1.0 and 2.0 9780 // in it. This is a win when the constant is not otherwise available because 9781 // it replaces two constant pool loads with one. We only do this if the FP 9782 // type is known to be legal, because if it isn't, then we are before legalize 9783 // types an we want the other legalization to happen first (e.g. to avoid 9784 // messing with soft float) and if the ConstantFP is not legal, because if 9785 // it is legal, we may not need to store the FP constant in a constant pool. 9786 if (ConstantFPSDNode *TV = dyn_cast<ConstantFPSDNode>(N2)) 9787 if (ConstantFPSDNode *FV = dyn_cast<ConstantFPSDNode>(N3)) { 9788 if (TLI.isTypeLegal(N2.getValueType()) && 9789 (TLI.getOperationAction(ISD::ConstantFP, N2.getValueType()) != 9790 TargetLowering::Legal) && 9791 // If both constants have multiple uses, then we won't need to do an 9792 // extra load, they are likely around in registers for other users. 9793 (TV->hasOneUse() || FV->hasOneUse())) { 9794 Constant *Elts[] = { 9795 const_cast<ConstantFP*>(FV->getConstantFPValue()), 9796 const_cast<ConstantFP*>(TV->getConstantFPValue()) 9797 }; 9798 Type *FPTy = Elts[0]->getType(); 9799 const DataLayout &TD = *TLI.getDataLayout(); 9800 9801 // Create a ConstantArray of the two constants. 9802 Constant *CA = ConstantArray::get(ArrayType::get(FPTy, 2), Elts); 9803 SDValue CPIdx = DAG.getConstantPool(CA, TLI.getPointerTy(), 9804 TD.getPrefTypeAlignment(FPTy)); 9805 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 9806 9807 // Get the offsets to the 0 and 1 element of the array so that we can 9808 // select between them. 9809 SDValue Zero = DAG.getIntPtrConstant(0); 9810 unsigned EltSize = (unsigned)TD.getTypeAllocSize(Elts[0]->getType()); 9811 SDValue One = DAG.getIntPtrConstant(EltSize); 9812 9813 SDValue Cond = DAG.getSetCC(DL, 9814 getSetCCResultType(N0.getValueType()), 9815 N0, N1, CC); 9816 AddToWorkList(Cond.getNode()); 9817 SDValue CstOffset = DAG.getSelect(DL, Zero.getValueType(), 9818 Cond, One, Zero); 9819 AddToWorkList(CstOffset.getNode()); 9820 CPIdx = DAG.getNode(ISD::ADD, DL, TLI.getPointerTy(), CPIdx, 9821 CstOffset); 9822 AddToWorkList(CPIdx.getNode()); 9823 return DAG.getLoad(TV->getValueType(0), DL, DAG.getEntryNode(), CPIdx, 9824 MachinePointerInfo::getConstantPool(), false, 9825 false, false, Alignment); 9826 9827 } 9828 } 9829 9830 // Check to see if we can perform the "gzip trick", transforming 9831 // (select_cc setlt X, 0, A, 0) -> (and (sra X, (sub size(X), 1), A) 9832 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT && 9833 (N1C->isNullValue() || // (a < 0) ? b : 0 9834 (N1C->getAPIntValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0 9835 EVT XType = N0.getValueType(); 9836 EVT AType = N2.getValueType(); 9837 if (XType.bitsGE(AType)) { 9838 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a 9839 // single-bit constant. 9840 if (N2C && ((N2C->getAPIntValue() & (N2C->getAPIntValue()-1)) == 0)) { 9841 unsigned ShCtV = N2C->getAPIntValue().logBase2(); 9842 ShCtV = XType.getSizeInBits()-ShCtV-1; 9843 SDValue ShCt = DAG.getConstant(ShCtV, 9844 getShiftAmountTy(N0.getValueType())); 9845 SDValue Shift = DAG.getNode(ISD::SRL, SDLoc(N0), 9846 XType, N0, ShCt); 9847 AddToWorkList(Shift.getNode()); 9848 9849 if (XType.bitsGT(AType)) { 9850 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift); 9851 AddToWorkList(Shift.getNode()); 9852 } 9853 9854 return DAG.getNode(ISD::AND, DL, AType, Shift, N2); 9855 } 9856 9857 SDValue Shift = DAG.getNode(ISD::SRA, SDLoc(N0), 9858 XType, N0, 9859 DAG.getConstant(XType.getSizeInBits()-1, 9860 getShiftAmountTy(N0.getValueType()))); 9861 AddToWorkList(Shift.getNode()); 9862 9863 if (XType.bitsGT(AType)) { 9864 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift); 9865 AddToWorkList(Shift.getNode()); 9866 } 9867 9868 return DAG.getNode(ISD::AND, DL, AType, Shift, N2); 9869 } 9870 } 9871 9872 // fold (select_cc seteq (and x, y), 0, 0, A) -> (and (shr (shl x)) A) 9873 // where y is has a single bit set. 9874 // A plaintext description would be, we can turn the SELECT_CC into an AND 9875 // when the condition can be materialized as an all-ones register. Any 9876 // single bit-test can be materialized as an all-ones register with 9877 // shift-left and shift-right-arith. 9878 if (CC == ISD::SETEQ && N0->getOpcode() == ISD::AND && 9879 N0->getValueType(0) == VT && 9880 N1C && N1C->isNullValue() && 9881 N2C && N2C->isNullValue()) { 9882 SDValue AndLHS = N0->getOperand(0); 9883 ConstantSDNode *ConstAndRHS = dyn_cast<ConstantSDNode>(N0->getOperand(1)); 9884 if (ConstAndRHS && ConstAndRHS->getAPIntValue().countPopulation() == 1) { 9885 // Shift the tested bit over the sign bit. 9886 APInt AndMask = ConstAndRHS->getAPIntValue(); 9887 SDValue ShlAmt = 9888 DAG.getConstant(AndMask.countLeadingZeros(), 9889 getShiftAmountTy(AndLHS.getValueType())); 9890 SDValue Shl = DAG.getNode(ISD::SHL, SDLoc(N0), VT, AndLHS, ShlAmt); 9891 9892 // Now arithmetic right shift it all the way over, so the result is either 9893 // all-ones, or zero. 9894 SDValue ShrAmt = 9895 DAG.getConstant(AndMask.getBitWidth()-1, 9896 getShiftAmountTy(Shl.getValueType())); 9897 SDValue Shr = DAG.getNode(ISD::SRA, SDLoc(N0), VT, Shl, ShrAmt); 9898 9899 return DAG.getNode(ISD::AND, DL, VT, Shr, N3); 9900 } 9901 } 9902 9903 // fold select C, 16, 0 -> shl C, 4 9904 if (N2C && N3C && N3C->isNullValue() && N2C->getAPIntValue().isPowerOf2() && 9905 TLI.getBooleanContents(N0.getValueType().isVector()) == 9906 TargetLowering::ZeroOrOneBooleanContent) { 9907 9908 // If the caller doesn't want us to simplify this into a zext of a compare, 9909 // don't do it. 9910 if (NotExtCompare && N2C->getAPIntValue() == 1) 9911 return SDValue(); 9912 9913 // Get a SetCC of the condition 9914 // NOTE: Don't create a SETCC if it's not legal on this target. 9915 if (!LegalOperations || 9916 TLI.isOperationLegal(ISD::SETCC, 9917 LegalTypes ? getSetCCResultType(N0.getValueType()) : MVT::i1)) { 9918 SDValue Temp, SCC; 9919 // cast from setcc result type to select result type 9920 if (LegalTypes) { 9921 SCC = DAG.getSetCC(DL, getSetCCResultType(N0.getValueType()), 9922 N0, N1, CC); 9923 if (N2.getValueType().bitsLT(SCC.getValueType())) 9924 Temp = DAG.getZeroExtendInReg(SCC, SDLoc(N2), 9925 N2.getValueType()); 9926 else 9927 Temp = DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N2), 9928 N2.getValueType(), SCC); 9929 } else { 9930 SCC = DAG.getSetCC(SDLoc(N0), MVT::i1, N0, N1, CC); 9931 Temp = DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N2), 9932 N2.getValueType(), SCC); 9933 } 9934 9935 AddToWorkList(SCC.getNode()); 9936 AddToWorkList(Temp.getNode()); 9937 9938 if (N2C->getAPIntValue() == 1) 9939 return Temp; 9940 9941 // shl setcc result by log2 n2c 9942 return DAG.getNode(ISD::SHL, DL, N2.getValueType(), Temp, 9943 DAG.getConstant(N2C->getAPIntValue().logBase2(), 9944 getShiftAmountTy(Temp.getValueType()))); 9945 } 9946 } 9947 9948 // Check to see if this is the equivalent of setcc 9949 // FIXME: Turn all of these into setcc if setcc if setcc is legal 9950 // otherwise, go ahead with the folds. 9951 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getAPIntValue() == 1ULL)) { 9952 EVT XType = N0.getValueType(); 9953 if (!LegalOperations || 9954 TLI.isOperationLegal(ISD::SETCC, getSetCCResultType(XType))) { 9955 SDValue Res = DAG.getSetCC(DL, getSetCCResultType(XType), N0, N1, CC); 9956 if (Res.getValueType() != VT) 9957 Res = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, Res); 9958 return Res; 9959 } 9960 9961 // fold (seteq X, 0) -> (srl (ctlz X, log2(size(X)))) 9962 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ && 9963 (!LegalOperations || 9964 TLI.isOperationLegal(ISD::CTLZ, XType))) { 9965 SDValue Ctlz = DAG.getNode(ISD::CTLZ, SDLoc(N0), XType, N0); 9966 return DAG.getNode(ISD::SRL, DL, XType, Ctlz, 9967 DAG.getConstant(Log2_32(XType.getSizeInBits()), 9968 getShiftAmountTy(Ctlz.getValueType()))); 9969 } 9970 // fold (setgt X, 0) -> (srl (and (-X, ~X), size(X)-1)) 9971 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) { 9972 SDValue NegN0 = DAG.getNode(ISD::SUB, SDLoc(N0), 9973 XType, DAG.getConstant(0, XType), N0); 9974 SDValue NotN0 = DAG.getNOT(SDLoc(N0), N0, XType); 9975 return DAG.getNode(ISD::SRL, DL, XType, 9976 DAG.getNode(ISD::AND, DL, XType, NegN0, NotN0), 9977 DAG.getConstant(XType.getSizeInBits()-1, 9978 getShiftAmountTy(XType))); 9979 } 9980 // fold (setgt X, -1) -> (xor (srl (X, size(X)-1), 1)) 9981 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) { 9982 SDValue Sign = DAG.getNode(ISD::SRL, SDLoc(N0), XType, N0, 9983 DAG.getConstant(XType.getSizeInBits()-1, 9984 getShiftAmountTy(N0.getValueType()))); 9985 return DAG.getNode(ISD::XOR, DL, XType, Sign, DAG.getConstant(1, XType)); 9986 } 9987 } 9988 9989 // Check to see if this is an integer abs. 9990 // select_cc setg[te] X, 0, X, -X -> 9991 // select_cc setgt X, -1, X, -X -> 9992 // select_cc setl[te] X, 0, -X, X -> 9993 // select_cc setlt X, 1, -X, X -> 9994 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 9995 if (N1C) { 9996 ConstantSDNode *SubC = NULL; 9997 if (((N1C->isNullValue() && (CC == ISD::SETGT || CC == ISD::SETGE)) || 9998 (N1C->isAllOnesValue() && CC == ISD::SETGT)) && 9999 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1)) 10000 SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0)); 10001 else if (((N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE)) || 10002 (N1C->isOne() && CC == ISD::SETLT)) && 10003 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1)) 10004 SubC = dyn_cast<ConstantSDNode>(N2.getOperand(0)); 10005 10006 EVT XType = N0.getValueType(); 10007 if (SubC && SubC->isNullValue() && XType.isInteger()) { 10008 SDValue Shift = DAG.getNode(ISD::SRA, SDLoc(N0), XType, 10009 N0, 10010 DAG.getConstant(XType.getSizeInBits()-1, 10011 getShiftAmountTy(N0.getValueType()))); 10012 SDValue Add = DAG.getNode(ISD::ADD, SDLoc(N0), 10013 XType, N0, Shift); 10014 AddToWorkList(Shift.getNode()); 10015 AddToWorkList(Add.getNode()); 10016 return DAG.getNode(ISD::XOR, DL, XType, Add, Shift); 10017 } 10018 } 10019 10020 return SDValue(); 10021} 10022 10023/// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC. 10024SDValue DAGCombiner::SimplifySetCC(EVT VT, SDValue N0, 10025 SDValue N1, ISD::CondCode Cond, 10026 SDLoc DL, bool foldBooleans) { 10027 TargetLowering::DAGCombinerInfo 10028 DagCombineInfo(DAG, Level, false, this); 10029 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo, DL); 10030} 10031 10032/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 10033/// return a DAG expression to select that will generate the same value by 10034/// multiplying by a magic number. See: 10035/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 10036SDValue DAGCombiner::BuildSDIV(SDNode *N) { 10037 std::vector<SDNode*> Built; 10038 SDValue S = TLI.BuildSDIV(N, DAG, LegalOperations, &Built); 10039 10040 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 10041 ii != ee; ++ii) 10042 AddToWorkList(*ii); 10043 return S; 10044} 10045 10046/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 10047/// return a DAG expression to select that will generate the same value by 10048/// multiplying by a magic number. See: 10049/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 10050SDValue DAGCombiner::BuildUDIV(SDNode *N) { 10051 std::vector<SDNode*> Built; 10052 SDValue S = TLI.BuildUDIV(N, DAG, LegalOperations, &Built); 10053 10054 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 10055 ii != ee; ++ii) 10056 AddToWorkList(*ii); 10057 return S; 10058} 10059 10060/// FindBaseOffset - Return true if base is a frame index, which is known not 10061// to alias with anything but itself. Provides base object and offset as 10062// results. 10063static bool FindBaseOffset(SDValue Ptr, SDValue &Base, int64_t &Offset, 10064 const GlobalValue *&GV, const void *&CV) { 10065 // Assume it is a primitive operation. 10066 Base = Ptr; Offset = 0; GV = 0; CV = 0; 10067 10068 // If it's an adding a simple constant then integrate the offset. 10069 if (Base.getOpcode() == ISD::ADD) { 10070 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) { 10071 Base = Base.getOperand(0); 10072 Offset += C->getZExtValue(); 10073 } 10074 } 10075 10076 // Return the underlying GlobalValue, and update the Offset. Return false 10077 // for GlobalAddressSDNode since the same GlobalAddress may be represented 10078 // by multiple nodes with different offsets. 10079 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Base)) { 10080 GV = G->getGlobal(); 10081 Offset += G->getOffset(); 10082 return false; 10083 } 10084 10085 // Return the underlying Constant value, and update the Offset. Return false 10086 // for ConstantSDNodes since the same constant pool entry may be represented 10087 // by multiple nodes with different offsets. 10088 if (ConstantPoolSDNode *C = dyn_cast<ConstantPoolSDNode>(Base)) { 10089 CV = C->isMachineConstantPoolEntry() ? (const void *)C->getMachineCPVal() 10090 : (const void *)C->getConstVal(); 10091 Offset += C->getOffset(); 10092 return false; 10093 } 10094 // If it's any of the following then it can't alias with anything but itself. 10095 return isa<FrameIndexSDNode>(Base); 10096} 10097 10098/// isAlias - Return true if there is any possibility that the two addresses 10099/// overlap. 10100bool DAGCombiner::isAlias(SDValue Ptr1, int64_t Size1, 10101 const Value *SrcValue1, int SrcValueOffset1, 10102 unsigned SrcValueAlign1, 10103 const MDNode *TBAAInfo1, 10104 SDValue Ptr2, int64_t Size2, 10105 const Value *SrcValue2, int SrcValueOffset2, 10106 unsigned SrcValueAlign2, 10107 const MDNode *TBAAInfo2) const { 10108 // If they are the same then they must be aliases. 10109 if (Ptr1 == Ptr2) return true; 10110 10111 // Gather base node and offset information. 10112 SDValue Base1, Base2; 10113 int64_t Offset1, Offset2; 10114 const GlobalValue *GV1, *GV2; 10115 const void *CV1, *CV2; 10116 bool isFrameIndex1 = FindBaseOffset(Ptr1, Base1, Offset1, GV1, CV1); 10117 bool isFrameIndex2 = FindBaseOffset(Ptr2, Base2, Offset2, GV2, CV2); 10118 10119 // If they have a same base address then check to see if they overlap. 10120 if (Base1 == Base2 || (GV1 && (GV1 == GV2)) || (CV1 && (CV1 == CV2))) 10121 return !((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1); 10122 10123 // It is possible for different frame indices to alias each other, mostly 10124 // when tail call optimization reuses return address slots for arguments. 10125 // To catch this case, look up the actual index of frame indices to compute 10126 // the real alias relationship. 10127 if (isFrameIndex1 && isFrameIndex2) { 10128 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 10129 Offset1 += MFI->getObjectOffset(cast<FrameIndexSDNode>(Base1)->getIndex()); 10130 Offset2 += MFI->getObjectOffset(cast<FrameIndexSDNode>(Base2)->getIndex()); 10131 return !((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1); 10132 } 10133 10134 // Otherwise, if we know what the bases are, and they aren't identical, then 10135 // we know they cannot alias. 10136 if ((isFrameIndex1 || CV1 || GV1) && (isFrameIndex2 || CV2 || GV2)) 10137 return false; 10138 10139 // If we know required SrcValue1 and SrcValue2 have relatively large alignment 10140 // compared to the size and offset of the access, we may be able to prove they 10141 // do not alias. This check is conservative for now to catch cases created by 10142 // splitting vector types. 10143 if ((SrcValueAlign1 == SrcValueAlign2) && 10144 (SrcValueOffset1 != SrcValueOffset2) && 10145 (Size1 == Size2) && (SrcValueAlign1 > Size1)) { 10146 int64_t OffAlign1 = SrcValueOffset1 % SrcValueAlign1; 10147 int64_t OffAlign2 = SrcValueOffset2 % SrcValueAlign1; 10148 10149 // There is no overlap between these relatively aligned accesses of similar 10150 // size, return no alias. 10151 if ((OffAlign1 + Size1) <= OffAlign2 || (OffAlign2 + Size2) <= OffAlign1) 10152 return false; 10153 } 10154 10155 if (CombinerGlobalAA) { 10156 // Use alias analysis information. 10157 int64_t MinOffset = std::min(SrcValueOffset1, SrcValueOffset2); 10158 int64_t Overlap1 = Size1 + SrcValueOffset1 - MinOffset; 10159 int64_t Overlap2 = Size2 + SrcValueOffset2 - MinOffset; 10160 AliasAnalysis::AliasResult AAResult = 10161 AA.alias(AliasAnalysis::Location(SrcValue1, Overlap1, TBAAInfo1), 10162 AliasAnalysis::Location(SrcValue2, Overlap2, TBAAInfo2)); 10163 if (AAResult == AliasAnalysis::NoAlias) 10164 return false; 10165 } 10166 10167 // Otherwise we have to assume they alias. 10168 return true; 10169} 10170 10171bool DAGCombiner::isAlias(LSBaseSDNode *Op0, LSBaseSDNode *Op1) { 10172 SDValue Ptr0, Ptr1; 10173 int64_t Size0, Size1; 10174 const Value *SrcValue0, *SrcValue1; 10175 int SrcValueOffset0, SrcValueOffset1; 10176 unsigned SrcValueAlign0, SrcValueAlign1; 10177 const MDNode *SrcTBAAInfo0, *SrcTBAAInfo1; 10178 FindAliasInfo(Op0, Ptr0, Size0, SrcValue0, SrcValueOffset0, 10179 SrcValueAlign0, SrcTBAAInfo0); 10180 FindAliasInfo(Op1, Ptr1, Size1, SrcValue1, SrcValueOffset1, 10181 SrcValueAlign1, SrcTBAAInfo1); 10182 return isAlias(Ptr0, Size0, SrcValue0, SrcValueOffset0, 10183 SrcValueAlign0, SrcTBAAInfo0, 10184 Ptr1, Size1, SrcValue1, SrcValueOffset1, 10185 SrcValueAlign1, SrcTBAAInfo1); 10186} 10187 10188/// FindAliasInfo - Extracts the relevant alias information from the memory 10189/// node. Returns true if the operand was a load. 10190bool DAGCombiner::FindAliasInfo(SDNode *N, 10191 SDValue &Ptr, int64_t &Size, 10192 const Value *&SrcValue, 10193 int &SrcValueOffset, 10194 unsigned &SrcValueAlign, 10195 const MDNode *&TBAAInfo) const { 10196 LSBaseSDNode *LS = cast<LSBaseSDNode>(N); 10197 10198 Ptr = LS->getBasePtr(); 10199 Size = LS->getMemoryVT().getSizeInBits() >> 3; 10200 SrcValue = LS->getSrcValue(); 10201 SrcValueOffset = LS->getSrcValueOffset(); 10202 SrcValueAlign = LS->getOriginalAlignment(); 10203 TBAAInfo = LS->getTBAAInfo(); 10204 return isa<LoadSDNode>(LS); 10205} 10206 10207/// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 10208/// looking for aliasing nodes and adding them to the Aliases vector. 10209void DAGCombiner::GatherAllAliases(SDNode *N, SDValue OriginalChain, 10210 SmallVector<SDValue, 8> &Aliases) { 10211 SmallVector<SDValue, 8> Chains; // List of chains to visit. 10212 SmallPtrSet<SDNode *, 16> Visited; // Visited node set. 10213 10214 // Get alias information for node. 10215 SDValue Ptr; 10216 int64_t Size; 10217 const Value *SrcValue; 10218 int SrcValueOffset; 10219 unsigned SrcValueAlign; 10220 const MDNode *SrcTBAAInfo; 10221 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset, 10222 SrcValueAlign, SrcTBAAInfo); 10223 10224 // Starting off. 10225 Chains.push_back(OriginalChain); 10226 unsigned Depth = 0; 10227 10228 // Look at each chain and determine if it is an alias. If so, add it to the 10229 // aliases list. If not, then continue up the chain looking for the next 10230 // candidate. 10231 while (!Chains.empty()) { 10232 SDValue Chain = Chains.back(); 10233 Chains.pop_back(); 10234 10235 // For TokenFactor nodes, look at each operand and only continue up the 10236 // chain until we find two aliases. If we've seen two aliases, assume we'll 10237 // find more and revert to original chain since the xform is unlikely to be 10238 // profitable. 10239 // 10240 // FIXME: The depth check could be made to return the last non-aliasing 10241 // chain we found before we hit a tokenfactor rather than the original 10242 // chain. 10243 if (Depth > 6 || Aliases.size() == 2) { 10244 Aliases.clear(); 10245 Aliases.push_back(OriginalChain); 10246 break; 10247 } 10248 10249 // Don't bother if we've been before. 10250 if (!Visited.insert(Chain.getNode())) 10251 continue; 10252 10253 switch (Chain.getOpcode()) { 10254 case ISD::EntryToken: 10255 // Entry token is ideal chain operand, but handled in FindBetterChain. 10256 break; 10257 10258 case ISD::LOAD: 10259 case ISD::STORE: { 10260 // Get alias information for Chain. 10261 SDValue OpPtr; 10262 int64_t OpSize; 10263 const Value *OpSrcValue; 10264 int OpSrcValueOffset; 10265 unsigned OpSrcValueAlign; 10266 const MDNode *OpSrcTBAAInfo; 10267 bool IsOpLoad = FindAliasInfo(Chain.getNode(), OpPtr, OpSize, 10268 OpSrcValue, OpSrcValueOffset, 10269 OpSrcValueAlign, 10270 OpSrcTBAAInfo); 10271 10272 // If chain is alias then stop here. 10273 if (!(IsLoad && IsOpLoad) && 10274 isAlias(Ptr, Size, SrcValue, SrcValueOffset, SrcValueAlign, 10275 SrcTBAAInfo, 10276 OpPtr, OpSize, OpSrcValue, OpSrcValueOffset, 10277 OpSrcValueAlign, OpSrcTBAAInfo)) { 10278 Aliases.push_back(Chain); 10279 } else { 10280 // Look further up the chain. 10281 Chains.push_back(Chain.getOperand(0)); 10282 ++Depth; 10283 } 10284 break; 10285 } 10286 10287 case ISD::TokenFactor: 10288 // We have to check each of the operands of the token factor for "small" 10289 // token factors, so we queue them up. Adding the operands to the queue 10290 // (stack) in reverse order maintains the original order and increases the 10291 // likelihood that getNode will find a matching token factor (CSE.) 10292 if (Chain.getNumOperands() > 16) { 10293 Aliases.push_back(Chain); 10294 break; 10295 } 10296 for (unsigned n = Chain.getNumOperands(); n;) 10297 Chains.push_back(Chain.getOperand(--n)); 10298 ++Depth; 10299 break; 10300 10301 default: 10302 // For all other instructions we will just have to take what we can get. 10303 Aliases.push_back(Chain); 10304 break; 10305 } 10306 } 10307} 10308 10309/// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking 10310/// for a better chain (aliasing node.) 10311SDValue DAGCombiner::FindBetterChain(SDNode *N, SDValue OldChain) { 10312 SmallVector<SDValue, 8> Aliases; // Ops for replacing token factor. 10313 10314 // Accumulate all the aliases to this node. 10315 GatherAllAliases(N, OldChain, Aliases); 10316 10317 // If no operands then chain to entry token. 10318 if (Aliases.size() == 0) 10319 return DAG.getEntryNode(); 10320 10321 // If a single operand then chain to it. We don't need to revisit it. 10322 if (Aliases.size() == 1) 10323 return Aliases[0]; 10324 10325 // Construct a custom tailored token factor. 10326 return DAG.getNode(ISD::TokenFactor, SDLoc(N), MVT::Other, 10327 &Aliases[0], Aliases.size()); 10328} 10329 10330// SelectionDAG::Combine - This is the entry point for the file. 10331// 10332void SelectionDAG::Combine(CombineLevel Level, AliasAnalysis &AA, 10333 CodeGenOpt::Level OptLevel) { 10334 /// run - This is the main entry point to this class. 10335 /// 10336 DAGCombiner(*this, AA, OptLevel).Run(Level); 10337} 10338