DAGCombiner.cpp revision b3452ea35c3e78d1a8c7d92f9448b0054d36e740
1//===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run 11// both before and after the DAG is legalized. 12// 13// This pass is not a substitute for the LLVM IR instcombine pass. This pass is 14// primarily intended to handle simplification opportunities that are implicit 15// in the LLVM IR and exposed by the various codegen lowering phases. 16// 17//===----------------------------------------------------------------------===// 18 19#define DEBUG_TYPE "dagcombine" 20#include "llvm/CodeGen/SelectionDAG.h" 21#include "llvm/DerivedTypes.h" 22#include "llvm/LLVMContext.h" 23#include "llvm/CodeGen/MachineFunction.h" 24#include "llvm/CodeGen/MachineFrameInfo.h" 25#include "llvm/CodeGen/PseudoSourceValue.h" 26#include "llvm/Analysis/AliasAnalysis.h" 27#include "llvm/Target/TargetData.h" 28#include "llvm/Target/TargetLowering.h" 29#include "llvm/Target/TargetMachine.h" 30#include "llvm/Target/TargetOptions.h" 31#include "llvm/ADT/SmallPtrSet.h" 32#include "llvm/ADT/Statistic.h" 33#include "llvm/Support/CommandLine.h" 34#include "llvm/Support/Debug.h" 35#include "llvm/Support/ErrorHandling.h" 36#include "llvm/Support/MathExtras.h" 37#include "llvm/Support/raw_ostream.h" 38#include <algorithm> 39using namespace llvm; 40 41STATISTIC(NodesCombined , "Number of dag nodes combined"); 42STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created"); 43STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created"); 44STATISTIC(OpsNarrowed , "Number of load/op/store narrowed"); 45STATISTIC(LdStFP2Int , "Number of fp load/store pairs transformed to int"); 46 47namespace { 48 static cl::opt<bool> 49 CombinerAA("combiner-alias-analysis", cl::Hidden, 50 cl::desc("Turn on alias analysis during testing")); 51 52 static cl::opt<bool> 53 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden, 54 cl::desc("Include global information in alias analysis")); 55 56//------------------------------ DAGCombiner ---------------------------------// 57 58 class DAGCombiner { 59 SelectionDAG &DAG; 60 const TargetLowering &TLI; 61 CombineLevel Level; 62 CodeGenOpt::Level OptLevel; 63 bool LegalOperations; 64 bool LegalTypes; 65 66 // Worklist of all of the nodes that need to be simplified. 67 std::vector<SDNode*> WorkList; 68 69 // AA - Used for DAG load/store alias analysis. 70 AliasAnalysis &AA; 71 72 /// AddUsersToWorkList - When an instruction is simplified, add all users of 73 /// the instruction to the work lists because they might get more simplified 74 /// now. 75 /// 76 void AddUsersToWorkList(SDNode *N) { 77 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 78 UI != UE; ++UI) 79 AddToWorkList(*UI); 80 } 81 82 /// visit - call the node-specific routine that knows how to fold each 83 /// particular type of node. 84 SDValue visit(SDNode *N); 85 86 public: 87 /// AddToWorkList - Add to the work list making sure it's instance is at the 88 /// the back (next to be processed.) 89 void AddToWorkList(SDNode *N) { 90 removeFromWorkList(N); 91 WorkList.push_back(N); 92 } 93 94 /// removeFromWorkList - remove all instances of N from the worklist. 95 /// 96 void removeFromWorkList(SDNode *N) { 97 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N), 98 WorkList.end()); 99 } 100 101 SDValue CombineTo(SDNode *N, const SDValue *To, unsigned NumTo, 102 bool AddTo = true); 103 104 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true) { 105 return CombineTo(N, &Res, 1, AddTo); 106 } 107 108 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, 109 bool AddTo = true) { 110 SDValue To[] = { Res0, Res1 }; 111 return CombineTo(N, To, 2, AddTo); 112 } 113 114 void CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO); 115 116 private: 117 118 /// SimplifyDemandedBits - Check the specified integer node value to see if 119 /// it can be simplified or if things it uses can be simplified by bit 120 /// propagation. If so, return true. 121 bool SimplifyDemandedBits(SDValue Op) { 122 unsigned BitWidth = Op.getValueType().getScalarType().getSizeInBits(); 123 APInt Demanded = APInt::getAllOnesValue(BitWidth); 124 return SimplifyDemandedBits(Op, Demanded); 125 } 126 127 bool SimplifyDemandedBits(SDValue Op, const APInt &Demanded); 128 129 bool CombineToPreIndexedLoadStore(SDNode *N); 130 bool CombineToPostIndexedLoadStore(SDNode *N); 131 132 void ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad); 133 SDValue PromoteOperand(SDValue Op, EVT PVT, bool &Replace); 134 SDValue SExtPromoteOperand(SDValue Op, EVT PVT); 135 SDValue ZExtPromoteOperand(SDValue Op, EVT PVT); 136 SDValue PromoteIntBinOp(SDValue Op); 137 SDValue PromoteIntShiftOp(SDValue Op); 138 SDValue PromoteExtend(SDValue Op); 139 bool PromoteLoad(SDValue Op); 140 141 /// combine - call the node-specific routine that knows how to fold each 142 /// particular type of node. If that doesn't do anything, try the 143 /// target-specific DAG combines. 144 SDValue combine(SDNode *N); 145 146 // Visitation implementation - Implement dag node combining for different 147 // node types. The semantics are as follows: 148 // Return Value: 149 // SDValue.getNode() == 0 - No change was made 150 // SDValue.getNode() == N - N was replaced, is dead and has been handled. 151 // otherwise - N should be replaced by the returned Operand. 152 // 153 SDValue visitTokenFactor(SDNode *N); 154 SDValue visitMERGE_VALUES(SDNode *N); 155 SDValue visitADD(SDNode *N); 156 SDValue visitSUB(SDNode *N); 157 SDValue visitADDC(SDNode *N); 158 SDValue visitADDE(SDNode *N); 159 SDValue visitMUL(SDNode *N); 160 SDValue visitSDIV(SDNode *N); 161 SDValue visitUDIV(SDNode *N); 162 SDValue visitSREM(SDNode *N); 163 SDValue visitUREM(SDNode *N); 164 SDValue visitMULHU(SDNode *N); 165 SDValue visitMULHS(SDNode *N); 166 SDValue visitSMUL_LOHI(SDNode *N); 167 SDValue visitUMUL_LOHI(SDNode *N); 168 SDValue visitSDIVREM(SDNode *N); 169 SDValue visitUDIVREM(SDNode *N); 170 SDValue visitAND(SDNode *N); 171 SDValue visitOR(SDNode *N); 172 SDValue visitXOR(SDNode *N); 173 SDValue SimplifyVBinOp(SDNode *N); 174 SDValue visitSHL(SDNode *N); 175 SDValue visitSRA(SDNode *N); 176 SDValue visitSRL(SDNode *N); 177 SDValue visitCTLZ(SDNode *N); 178 SDValue visitCTTZ(SDNode *N); 179 SDValue visitCTPOP(SDNode *N); 180 SDValue visitSELECT(SDNode *N); 181 SDValue visitSELECT_CC(SDNode *N); 182 SDValue visitSETCC(SDNode *N); 183 SDValue visitSIGN_EXTEND(SDNode *N); 184 SDValue visitZERO_EXTEND(SDNode *N); 185 SDValue visitANY_EXTEND(SDNode *N); 186 SDValue visitSIGN_EXTEND_INREG(SDNode *N); 187 SDValue visitTRUNCATE(SDNode *N); 188 SDValue visitBITCAST(SDNode *N); 189 SDValue visitBUILD_PAIR(SDNode *N); 190 SDValue visitFADD(SDNode *N); 191 SDValue visitFSUB(SDNode *N); 192 SDValue visitFMUL(SDNode *N); 193 SDValue visitFDIV(SDNode *N); 194 SDValue visitFREM(SDNode *N); 195 SDValue visitFCOPYSIGN(SDNode *N); 196 SDValue visitSINT_TO_FP(SDNode *N); 197 SDValue visitUINT_TO_FP(SDNode *N); 198 SDValue visitFP_TO_SINT(SDNode *N); 199 SDValue visitFP_TO_UINT(SDNode *N); 200 SDValue visitFP_ROUND(SDNode *N); 201 SDValue visitFP_ROUND_INREG(SDNode *N); 202 SDValue visitFP_EXTEND(SDNode *N); 203 SDValue visitFNEG(SDNode *N); 204 SDValue visitFABS(SDNode *N); 205 SDValue visitBRCOND(SDNode *N); 206 SDValue visitBR_CC(SDNode *N); 207 SDValue visitLOAD(SDNode *N); 208 SDValue visitSTORE(SDNode *N); 209 SDValue visitINSERT_VECTOR_ELT(SDNode *N); 210 SDValue visitEXTRACT_VECTOR_ELT(SDNode *N); 211 SDValue visitBUILD_VECTOR(SDNode *N); 212 SDValue visitCONCAT_VECTORS(SDNode *N); 213 SDValue visitVECTOR_SHUFFLE(SDNode *N); 214 SDValue visitMEMBARRIER(SDNode *N); 215 216 SDValue XformToShuffleWithZero(SDNode *N); 217 SDValue ReassociateOps(unsigned Opc, DebugLoc DL, SDValue LHS, SDValue RHS); 218 219 SDValue visitShiftByConstant(SDNode *N, unsigned Amt); 220 221 bool SimplifySelectOps(SDNode *SELECT, SDValue LHS, SDValue RHS); 222 SDValue SimplifyBinOpWithSameOpcodeHands(SDNode *N); 223 SDValue SimplifySelect(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2); 224 SDValue SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2, 225 SDValue N3, ISD::CondCode CC, 226 bool NotExtCompare = false); 227 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond, 228 DebugLoc DL, bool foldBooleans = true); 229 SDValue SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 230 unsigned HiOp); 231 SDValue CombineConsecutiveLoads(SDNode *N, EVT VT); 232 SDValue ConstantFoldBITCASTofBUILD_VECTOR(SDNode *, EVT); 233 SDValue BuildSDIV(SDNode *N); 234 SDValue BuildUDIV(SDNode *N); 235 SDNode *MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL); 236 SDValue ReduceLoadWidth(SDNode *N); 237 SDValue ReduceLoadOpStoreWidth(SDNode *N); 238 SDValue TransformFPLoadStorePair(SDNode *N); 239 240 SDValue GetDemandedBits(SDValue V, const APInt &Mask); 241 242 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 243 /// looking for aliasing nodes and adding them to the Aliases vector. 244 void GatherAllAliases(SDNode *N, SDValue OriginalChain, 245 SmallVector<SDValue, 8> &Aliases); 246 247 /// isAlias - Return true if there is any possibility that the two addresses 248 /// overlap. 249 bool isAlias(SDValue Ptr1, int64_t Size1, 250 const Value *SrcValue1, int SrcValueOffset1, 251 unsigned SrcValueAlign1, 252 const MDNode *TBAAInfo1, 253 SDValue Ptr2, int64_t Size2, 254 const Value *SrcValue2, int SrcValueOffset2, 255 unsigned SrcValueAlign2, 256 const MDNode *TBAAInfo2) const; 257 258 /// FindAliasInfo - Extracts the relevant alias information from the memory 259 /// node. Returns true if the operand was a load. 260 bool FindAliasInfo(SDNode *N, 261 SDValue &Ptr, int64_t &Size, 262 const Value *&SrcValue, int &SrcValueOffset, 263 unsigned &SrcValueAlignment, 264 const MDNode *&TBAAInfo) const; 265 266 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, 267 /// looking for a better chain (aliasing node.) 268 SDValue FindBetterChain(SDNode *N, SDValue Chain); 269 270 public: 271 DAGCombiner(SelectionDAG &D, AliasAnalysis &A, CodeGenOpt::Level OL) 272 : DAG(D), TLI(D.getTargetLoweringInfo()), Level(Unrestricted), 273 OptLevel(OL), LegalOperations(false), LegalTypes(false), AA(A) {} 274 275 /// Run - runs the dag combiner on all nodes in the work list 276 void Run(CombineLevel AtLevel); 277 278 SelectionDAG &getDAG() const { return DAG; } 279 280 /// getShiftAmountTy - Returns a type large enough to hold any valid 281 /// shift amount - before type legalization these can be huge. 282 EVT getShiftAmountTy(EVT LHSTy) { 283 return LegalTypes ? TLI.getShiftAmountTy(LHSTy) : TLI.getPointerTy(); 284 } 285 286 /// isTypeLegal - This method returns true if we are running before type 287 /// legalization or if the specified VT is legal. 288 bool isTypeLegal(const EVT &VT) { 289 if (!LegalTypes) return true; 290 return TLI.isTypeLegal(VT); 291 } 292 }; 293} 294 295 296namespace { 297/// WorkListRemover - This class is a DAGUpdateListener that removes any deleted 298/// nodes from the worklist. 299class WorkListRemover : public SelectionDAG::DAGUpdateListener { 300 DAGCombiner &DC; 301public: 302 explicit WorkListRemover(DAGCombiner &dc) : DC(dc) {} 303 304 virtual void NodeDeleted(SDNode *N, SDNode *E) { 305 DC.removeFromWorkList(N); 306 } 307 308 virtual void NodeUpdated(SDNode *N) { 309 // Ignore updates. 310 } 311}; 312} 313 314//===----------------------------------------------------------------------===// 315// TargetLowering::DAGCombinerInfo implementation 316//===----------------------------------------------------------------------===// 317 318void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) { 319 ((DAGCombiner*)DC)->AddToWorkList(N); 320} 321 322void TargetLowering::DAGCombinerInfo::RemoveFromWorklist(SDNode *N) { 323 ((DAGCombiner*)DC)->removeFromWorkList(N); 324} 325 326SDValue TargetLowering::DAGCombinerInfo:: 327CombineTo(SDNode *N, const std::vector<SDValue> &To, bool AddTo) { 328 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size(), AddTo); 329} 330 331SDValue TargetLowering::DAGCombinerInfo:: 332CombineTo(SDNode *N, SDValue Res, bool AddTo) { 333 return ((DAGCombiner*)DC)->CombineTo(N, Res, AddTo); 334} 335 336 337SDValue TargetLowering::DAGCombinerInfo:: 338CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo) { 339 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1, AddTo); 340} 341 342void TargetLowering::DAGCombinerInfo:: 343CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) { 344 return ((DAGCombiner*)DC)->CommitTargetLoweringOpt(TLO); 345} 346 347//===----------------------------------------------------------------------===// 348// Helper Functions 349//===----------------------------------------------------------------------===// 350 351/// isNegatibleForFree - Return 1 if we can compute the negated form of the 352/// specified expression for the same cost as the expression itself, or 2 if we 353/// can compute the negated form more cheaply than the expression itself. 354static char isNegatibleForFree(SDValue Op, bool LegalOperations, 355 unsigned Depth = 0) { 356 // No compile time optimizations on this type. 357 if (Op.getValueType() == MVT::ppcf128) 358 return 0; 359 360 // fneg is removable even if it has multiple uses. 361 if (Op.getOpcode() == ISD::FNEG) return 2; 362 363 // Don't allow anything with multiple uses. 364 if (!Op.hasOneUse()) return 0; 365 366 // Don't recurse exponentially. 367 if (Depth > 6) return 0; 368 369 switch (Op.getOpcode()) { 370 default: return false; 371 case ISD::ConstantFP: 372 // Don't invert constant FP values after legalize. The negated constant 373 // isn't necessarily legal. 374 return LegalOperations ? 0 : 1; 375 case ISD::FADD: 376 // FIXME: determine better conditions for this xform. 377 if (!UnsafeFPMath) return 0; 378 379 // fold (fsub (fadd A, B)) -> (fsub (fneg A), B) 380 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 381 return V; 382 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A) 383 return isNegatibleForFree(Op.getOperand(1), LegalOperations, Depth+1); 384 case ISD::FSUB: 385 // We can't turn -(A-B) into B-A when we honor signed zeros. 386 if (!UnsafeFPMath) return 0; 387 388 // fold (fneg (fsub A, B)) -> (fsub B, A) 389 return 1; 390 391 case ISD::FMUL: 392 case ISD::FDIV: 393 if (HonorSignDependentRoundingFPMath()) return 0; 394 395 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) or (fmul X, (fneg Y)) 396 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 397 return V; 398 399 return isNegatibleForFree(Op.getOperand(1), LegalOperations, Depth+1); 400 401 case ISD::FP_EXTEND: 402 case ISD::FP_ROUND: 403 case ISD::FSIN: 404 return isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1); 405 } 406} 407 408/// GetNegatedExpression - If isNegatibleForFree returns true, this function 409/// returns the newly negated expression. 410static SDValue GetNegatedExpression(SDValue Op, SelectionDAG &DAG, 411 bool LegalOperations, unsigned Depth = 0) { 412 // fneg is removable even if it has multiple uses. 413 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0); 414 415 // Don't allow anything with multiple uses. 416 assert(Op.hasOneUse() && "Unknown reuse!"); 417 418 assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree"); 419 switch (Op.getOpcode()) { 420 default: llvm_unreachable("Unknown code"); 421 case ISD::ConstantFP: { 422 APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF(); 423 V.changeSign(); 424 return DAG.getConstantFP(V, Op.getValueType()); 425 } 426 case ISD::FADD: 427 // FIXME: determine better conditions for this xform. 428 assert(UnsafeFPMath); 429 430 // fold (fneg (fadd A, B)) -> (fsub (fneg A), B) 431 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 432 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 433 GetNegatedExpression(Op.getOperand(0), DAG, 434 LegalOperations, Depth+1), 435 Op.getOperand(1)); 436 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A) 437 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 438 GetNegatedExpression(Op.getOperand(1), DAG, 439 LegalOperations, Depth+1), 440 Op.getOperand(0)); 441 case ISD::FSUB: 442 // We can't turn -(A-B) into B-A when we honor signed zeros. 443 assert(UnsafeFPMath); 444 445 // fold (fneg (fsub 0, B)) -> B 446 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(Op.getOperand(0))) 447 if (N0CFP->getValueAPF().isZero()) 448 return Op.getOperand(1); 449 450 // fold (fneg (fsub A, B)) -> (fsub B, A) 451 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 452 Op.getOperand(1), Op.getOperand(0)); 453 454 case ISD::FMUL: 455 case ISD::FDIV: 456 assert(!HonorSignDependentRoundingFPMath()); 457 458 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) 459 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 460 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 461 GetNegatedExpression(Op.getOperand(0), DAG, 462 LegalOperations, Depth+1), 463 Op.getOperand(1)); 464 465 // fold (fneg (fmul X, Y)) -> (fmul X, (fneg Y)) 466 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 467 Op.getOperand(0), 468 GetNegatedExpression(Op.getOperand(1), DAG, 469 LegalOperations, Depth+1)); 470 471 case ISD::FP_EXTEND: 472 case ISD::FSIN: 473 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 474 GetNegatedExpression(Op.getOperand(0), DAG, 475 LegalOperations, Depth+1)); 476 case ISD::FP_ROUND: 477 return DAG.getNode(ISD::FP_ROUND, Op.getDebugLoc(), Op.getValueType(), 478 GetNegatedExpression(Op.getOperand(0), DAG, 479 LegalOperations, Depth+1), 480 Op.getOperand(1)); 481 } 482} 483 484 485// isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc 486// that selects between the values 1 and 0, making it equivalent to a setcc. 487// Also, set the incoming LHS, RHS, and CC references to the appropriate 488// nodes based on the type of node we are checking. This simplifies life a 489// bit for the callers. 490static bool isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS, 491 SDValue &CC) { 492 if (N.getOpcode() == ISD::SETCC) { 493 LHS = N.getOperand(0); 494 RHS = N.getOperand(1); 495 CC = N.getOperand(2); 496 return true; 497 } 498 if (N.getOpcode() == ISD::SELECT_CC && 499 N.getOperand(2).getOpcode() == ISD::Constant && 500 N.getOperand(3).getOpcode() == ISD::Constant && 501 cast<ConstantSDNode>(N.getOperand(2))->getAPIntValue() == 1 && 502 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) { 503 LHS = N.getOperand(0); 504 RHS = N.getOperand(1); 505 CC = N.getOperand(4); 506 return true; 507 } 508 return false; 509} 510 511// isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only 512// one use. If this is true, it allows the users to invert the operation for 513// free when it is profitable to do so. 514static bool isOneUseSetCC(SDValue N) { 515 SDValue N0, N1, N2; 516 if (isSetCCEquivalent(N, N0, N1, N2) && N.getNode()->hasOneUse()) 517 return true; 518 return false; 519} 520 521SDValue DAGCombiner::ReassociateOps(unsigned Opc, DebugLoc DL, 522 SDValue N0, SDValue N1) { 523 EVT VT = N0.getValueType(); 524 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) { 525 if (isa<ConstantSDNode>(N1)) { 526 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2)) 527 SDValue OpNode = 528 DAG.FoldConstantArithmetic(Opc, VT, 529 cast<ConstantSDNode>(N0.getOperand(1)), 530 cast<ConstantSDNode>(N1)); 531 return DAG.getNode(Opc, DL, VT, N0.getOperand(0), OpNode); 532 } else if (N0.hasOneUse()) { 533 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use 534 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT, 535 N0.getOperand(0), N1); 536 AddToWorkList(OpNode.getNode()); 537 return DAG.getNode(Opc, DL, VT, OpNode, N0.getOperand(1)); 538 } 539 } 540 541 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) { 542 if (isa<ConstantSDNode>(N0)) { 543 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2)) 544 SDValue OpNode = 545 DAG.FoldConstantArithmetic(Opc, VT, 546 cast<ConstantSDNode>(N1.getOperand(1)), 547 cast<ConstantSDNode>(N0)); 548 return DAG.getNode(Opc, DL, VT, N1.getOperand(0), OpNode); 549 } else if (N1.hasOneUse()) { 550 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use 551 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT, 552 N1.getOperand(0), N0); 553 AddToWorkList(OpNode.getNode()); 554 return DAG.getNode(Opc, DL, VT, OpNode, N1.getOperand(1)); 555 } 556 } 557 558 return SDValue(); 559} 560 561SDValue DAGCombiner::CombineTo(SDNode *N, const SDValue *To, unsigned NumTo, 562 bool AddTo) { 563 assert(N->getNumValues() == NumTo && "Broken CombineTo call!"); 564 ++NodesCombined; 565 DEBUG(dbgs() << "\nReplacing.1 "; 566 N->dump(&DAG); 567 dbgs() << "\nWith: "; 568 To[0].getNode()->dump(&DAG); 569 dbgs() << " and " << NumTo-1 << " other values\n"; 570 for (unsigned i = 0, e = NumTo; i != e; ++i) 571 assert((!To[i].getNode() || 572 N->getValueType(i) == To[i].getValueType()) && 573 "Cannot combine value to value of different type!")); 574 WorkListRemover DeadNodes(*this); 575 DAG.ReplaceAllUsesWith(N, To, &DeadNodes); 576 577 if (AddTo) { 578 // Push the new nodes and any users onto the worklist 579 for (unsigned i = 0, e = NumTo; i != e; ++i) { 580 if (To[i].getNode()) { 581 AddToWorkList(To[i].getNode()); 582 AddUsersToWorkList(To[i].getNode()); 583 } 584 } 585 } 586 587 // Finally, if the node is now dead, remove it from the graph. The node 588 // may not be dead if the replacement process recursively simplified to 589 // something else needing this node. 590 if (N->use_empty()) { 591 // Nodes can be reintroduced into the worklist. Make sure we do not 592 // process a node that has been replaced. 593 removeFromWorkList(N); 594 595 // Finally, since the node is now dead, remove it from the graph. 596 DAG.DeleteNode(N); 597 } 598 return SDValue(N, 0); 599} 600 601void DAGCombiner:: 602CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) { 603 // Replace all uses. If any nodes become isomorphic to other nodes and 604 // are deleted, make sure to remove them from our worklist. 605 WorkListRemover DeadNodes(*this); 606 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &DeadNodes); 607 608 // Push the new node and any (possibly new) users onto the worklist. 609 AddToWorkList(TLO.New.getNode()); 610 AddUsersToWorkList(TLO.New.getNode()); 611 612 // Finally, if the node is now dead, remove it from the graph. The node 613 // may not be dead if the replacement process recursively simplified to 614 // something else needing this node. 615 if (TLO.Old.getNode()->use_empty()) { 616 removeFromWorkList(TLO.Old.getNode()); 617 618 // If the operands of this node are only used by the node, they will now 619 // be dead. Make sure to visit them first to delete dead nodes early. 620 for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands(); i != e; ++i) 621 if (TLO.Old.getNode()->getOperand(i).getNode()->hasOneUse()) 622 AddToWorkList(TLO.Old.getNode()->getOperand(i).getNode()); 623 624 DAG.DeleteNode(TLO.Old.getNode()); 625 } 626} 627 628/// SimplifyDemandedBits - Check the specified integer node value to see if 629/// it can be simplified or if things it uses can be simplified by bit 630/// propagation. If so, return true. 631bool DAGCombiner::SimplifyDemandedBits(SDValue Op, const APInt &Demanded) { 632 TargetLowering::TargetLoweringOpt TLO(DAG, LegalTypes, LegalOperations); 633 APInt KnownZero, KnownOne; 634 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO)) 635 return false; 636 637 // Revisit the node. 638 AddToWorkList(Op.getNode()); 639 640 // Replace the old value with the new one. 641 ++NodesCombined; 642 DEBUG(dbgs() << "\nReplacing.2 "; 643 TLO.Old.getNode()->dump(&DAG); 644 dbgs() << "\nWith: "; 645 TLO.New.getNode()->dump(&DAG); 646 dbgs() << '\n'); 647 648 CommitTargetLoweringOpt(TLO); 649 return true; 650} 651 652void DAGCombiner::ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad) { 653 DebugLoc dl = Load->getDebugLoc(); 654 EVT VT = Load->getValueType(0); 655 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, VT, SDValue(ExtLoad, 0)); 656 657 DEBUG(dbgs() << "\nReplacing.9 "; 658 Load->dump(&DAG); 659 dbgs() << "\nWith: "; 660 Trunc.getNode()->dump(&DAG); 661 dbgs() << '\n'); 662 WorkListRemover DeadNodes(*this); 663 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 0), Trunc, &DeadNodes); 664 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 1), SDValue(ExtLoad, 1), 665 &DeadNodes); 666 removeFromWorkList(Load); 667 DAG.DeleteNode(Load); 668 AddToWorkList(Trunc.getNode()); 669} 670 671SDValue DAGCombiner::PromoteOperand(SDValue Op, EVT PVT, bool &Replace) { 672 Replace = false; 673 DebugLoc dl = Op.getDebugLoc(); 674 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Op)) { 675 EVT MemVT = LD->getMemoryVT(); 676 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD) 677 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT) ? ISD::ZEXTLOAD 678 : ISD::EXTLOAD) 679 : LD->getExtensionType(); 680 Replace = true; 681 return DAG.getExtLoad(ExtType, dl, PVT, 682 LD->getChain(), LD->getBasePtr(), 683 LD->getPointerInfo(), 684 MemVT, LD->isVolatile(), 685 LD->isNonTemporal(), LD->getAlignment()); 686 } 687 688 unsigned Opc = Op.getOpcode(); 689 switch (Opc) { 690 default: break; 691 case ISD::AssertSext: 692 return DAG.getNode(ISD::AssertSext, dl, PVT, 693 SExtPromoteOperand(Op.getOperand(0), PVT), 694 Op.getOperand(1)); 695 case ISD::AssertZext: 696 return DAG.getNode(ISD::AssertZext, dl, PVT, 697 ZExtPromoteOperand(Op.getOperand(0), PVT), 698 Op.getOperand(1)); 699 case ISD::Constant: { 700 unsigned ExtOpc = 701 Op.getValueType().isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; 702 return DAG.getNode(ExtOpc, dl, PVT, Op); 703 } 704 } 705 706 if (!TLI.isOperationLegal(ISD::ANY_EXTEND, PVT)) 707 return SDValue(); 708 return DAG.getNode(ISD::ANY_EXTEND, dl, PVT, Op); 709} 710 711SDValue DAGCombiner::SExtPromoteOperand(SDValue Op, EVT PVT) { 712 if (!TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, PVT)) 713 return SDValue(); 714 EVT OldVT = Op.getValueType(); 715 DebugLoc dl = Op.getDebugLoc(); 716 bool Replace = false; 717 SDValue NewOp = PromoteOperand(Op, PVT, Replace); 718 if (NewOp.getNode() == 0) 719 return SDValue(); 720 AddToWorkList(NewOp.getNode()); 721 722 if (Replace) 723 ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode()); 724 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NewOp.getValueType(), NewOp, 725 DAG.getValueType(OldVT)); 726} 727 728SDValue DAGCombiner::ZExtPromoteOperand(SDValue Op, EVT PVT) { 729 EVT OldVT = Op.getValueType(); 730 DebugLoc dl = Op.getDebugLoc(); 731 bool Replace = false; 732 SDValue NewOp = PromoteOperand(Op, PVT, Replace); 733 if (NewOp.getNode() == 0) 734 return SDValue(); 735 AddToWorkList(NewOp.getNode()); 736 737 if (Replace) 738 ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode()); 739 return DAG.getZeroExtendInReg(NewOp, dl, OldVT); 740} 741 742/// PromoteIntBinOp - Promote the specified integer binary operation if the 743/// target indicates it is beneficial. e.g. On x86, it's usually better to 744/// promote i16 operations to i32 since i16 instructions are longer. 745SDValue DAGCombiner::PromoteIntBinOp(SDValue Op) { 746 if (!LegalOperations) 747 return SDValue(); 748 749 EVT VT = Op.getValueType(); 750 if (VT.isVector() || !VT.isInteger()) 751 return SDValue(); 752 753 // If operation type is 'undesirable', e.g. i16 on x86, consider 754 // promoting it. 755 unsigned Opc = Op.getOpcode(); 756 if (TLI.isTypeDesirableForOp(Opc, VT)) 757 return SDValue(); 758 759 EVT PVT = VT; 760 // Consult target whether it is a good idea to promote this operation and 761 // what's the right type to promote it to. 762 if (TLI.IsDesirableToPromoteOp(Op, PVT)) { 763 assert(PVT != VT && "Don't know what type to promote to!"); 764 765 bool Replace0 = false; 766 SDValue N0 = Op.getOperand(0); 767 SDValue NN0 = PromoteOperand(N0, PVT, Replace0); 768 if (NN0.getNode() == 0) 769 return SDValue(); 770 771 bool Replace1 = false; 772 SDValue N1 = Op.getOperand(1); 773 SDValue NN1; 774 if (N0 == N1) 775 NN1 = NN0; 776 else { 777 NN1 = PromoteOperand(N1, PVT, Replace1); 778 if (NN1.getNode() == 0) 779 return SDValue(); 780 } 781 782 AddToWorkList(NN0.getNode()); 783 if (NN1.getNode()) 784 AddToWorkList(NN1.getNode()); 785 786 if (Replace0) 787 ReplaceLoadWithPromotedLoad(N0.getNode(), NN0.getNode()); 788 if (Replace1) 789 ReplaceLoadWithPromotedLoad(N1.getNode(), NN1.getNode()); 790 791 DEBUG(dbgs() << "\nPromoting "; 792 Op.getNode()->dump(&DAG)); 793 DebugLoc dl = Op.getDebugLoc(); 794 return DAG.getNode(ISD::TRUNCATE, dl, VT, 795 DAG.getNode(Opc, dl, PVT, NN0, NN1)); 796 } 797 return SDValue(); 798} 799 800/// PromoteIntShiftOp - Promote the specified integer shift operation if the 801/// target indicates it is beneficial. e.g. On x86, it's usually better to 802/// promote i16 operations to i32 since i16 instructions are longer. 803SDValue DAGCombiner::PromoteIntShiftOp(SDValue Op) { 804 if (!LegalOperations) 805 return SDValue(); 806 807 EVT VT = Op.getValueType(); 808 if (VT.isVector() || !VT.isInteger()) 809 return SDValue(); 810 811 // If operation type is 'undesirable', e.g. i16 on x86, consider 812 // promoting it. 813 unsigned Opc = Op.getOpcode(); 814 if (TLI.isTypeDesirableForOp(Opc, VT)) 815 return SDValue(); 816 817 EVT PVT = VT; 818 // Consult target whether it is a good idea to promote this operation and 819 // what's the right type to promote it to. 820 if (TLI.IsDesirableToPromoteOp(Op, PVT)) { 821 assert(PVT != VT && "Don't know what type to promote to!"); 822 823 bool Replace = false; 824 SDValue N0 = Op.getOperand(0); 825 if (Opc == ISD::SRA) 826 N0 = SExtPromoteOperand(Op.getOperand(0), PVT); 827 else if (Opc == ISD::SRL) 828 N0 = ZExtPromoteOperand(Op.getOperand(0), PVT); 829 else 830 N0 = PromoteOperand(N0, PVT, Replace); 831 if (N0.getNode() == 0) 832 return SDValue(); 833 834 AddToWorkList(N0.getNode()); 835 if (Replace) 836 ReplaceLoadWithPromotedLoad(Op.getOperand(0).getNode(), N0.getNode()); 837 838 DEBUG(dbgs() << "\nPromoting "; 839 Op.getNode()->dump(&DAG)); 840 DebugLoc dl = Op.getDebugLoc(); 841 return DAG.getNode(ISD::TRUNCATE, dl, VT, 842 DAG.getNode(Opc, dl, PVT, N0, Op.getOperand(1))); 843 } 844 return SDValue(); 845} 846 847SDValue DAGCombiner::PromoteExtend(SDValue Op) { 848 if (!LegalOperations) 849 return SDValue(); 850 851 EVT VT = Op.getValueType(); 852 if (VT.isVector() || !VT.isInteger()) 853 return SDValue(); 854 855 // If operation type is 'undesirable', e.g. i16 on x86, consider 856 // promoting it. 857 unsigned Opc = Op.getOpcode(); 858 if (TLI.isTypeDesirableForOp(Opc, VT)) 859 return SDValue(); 860 861 EVT PVT = VT; 862 // Consult target whether it is a good idea to promote this operation and 863 // what's the right type to promote it to. 864 if (TLI.IsDesirableToPromoteOp(Op, PVT)) { 865 assert(PVT != VT && "Don't know what type to promote to!"); 866 // fold (aext (aext x)) -> (aext x) 867 // fold (aext (zext x)) -> (zext x) 868 // fold (aext (sext x)) -> (sext x) 869 DEBUG(dbgs() << "\nPromoting "; 870 Op.getNode()->dump(&DAG)); 871 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), VT, Op.getOperand(0)); 872 } 873 return SDValue(); 874} 875 876bool DAGCombiner::PromoteLoad(SDValue Op) { 877 if (!LegalOperations) 878 return false; 879 880 EVT VT = Op.getValueType(); 881 if (VT.isVector() || !VT.isInteger()) 882 return false; 883 884 // If operation type is 'undesirable', e.g. i16 on x86, consider 885 // promoting it. 886 unsigned Opc = Op.getOpcode(); 887 if (TLI.isTypeDesirableForOp(Opc, VT)) 888 return false; 889 890 EVT PVT = VT; 891 // Consult target whether it is a good idea to promote this operation and 892 // what's the right type to promote it to. 893 if (TLI.IsDesirableToPromoteOp(Op, PVT)) { 894 assert(PVT != VT && "Don't know what type to promote to!"); 895 896 DebugLoc dl = Op.getDebugLoc(); 897 SDNode *N = Op.getNode(); 898 LoadSDNode *LD = cast<LoadSDNode>(N); 899 EVT MemVT = LD->getMemoryVT(); 900 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD) 901 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT) ? ISD::ZEXTLOAD 902 : ISD::EXTLOAD) 903 : LD->getExtensionType(); 904 SDValue NewLD = DAG.getExtLoad(ExtType, dl, PVT, 905 LD->getChain(), LD->getBasePtr(), 906 LD->getPointerInfo(), 907 MemVT, LD->isVolatile(), 908 LD->isNonTemporal(), LD->getAlignment()); 909 SDValue Result = DAG.getNode(ISD::TRUNCATE, dl, VT, NewLD); 910 911 DEBUG(dbgs() << "\nPromoting "; 912 N->dump(&DAG); 913 dbgs() << "\nTo: "; 914 Result.getNode()->dump(&DAG); 915 dbgs() << '\n'); 916 WorkListRemover DeadNodes(*this); 917 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result, &DeadNodes); 918 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), NewLD.getValue(1), &DeadNodes); 919 removeFromWorkList(N); 920 DAG.DeleteNode(N); 921 AddToWorkList(Result.getNode()); 922 return true; 923 } 924 return false; 925} 926 927 928//===----------------------------------------------------------------------===// 929// Main DAG Combiner implementation 930//===----------------------------------------------------------------------===// 931 932void DAGCombiner::Run(CombineLevel AtLevel) { 933 // set the instance variables, so that the various visit routines may use it. 934 Level = AtLevel; 935 LegalOperations = Level >= NoIllegalOperations; 936 LegalTypes = Level >= NoIllegalTypes; 937 938 // Add all the dag nodes to the worklist. 939 WorkList.reserve(DAG.allnodes_size()); 940 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 941 E = DAG.allnodes_end(); I != E; ++I) 942 WorkList.push_back(I); 943 944 // Create a dummy node (which is not added to allnodes), that adds a reference 945 // to the root node, preventing it from being deleted, and tracking any 946 // changes of the root. 947 HandleSDNode Dummy(DAG.getRoot()); 948 949 // The root of the dag may dangle to deleted nodes until the dag combiner is 950 // done. Set it to null to avoid confusion. 951 DAG.setRoot(SDValue()); 952 953 // while the worklist isn't empty, inspect the node on the end of it and 954 // try and combine it. 955 while (!WorkList.empty()) { 956 SDNode *N = WorkList.back(); 957 WorkList.pop_back(); 958 959 // If N has no uses, it is dead. Make sure to revisit all N's operands once 960 // N is deleted from the DAG, since they too may now be dead or may have a 961 // reduced number of uses, allowing other xforms. 962 if (N->use_empty() && N != &Dummy) { 963 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 964 AddToWorkList(N->getOperand(i).getNode()); 965 966 DAG.DeleteNode(N); 967 continue; 968 } 969 970 SDValue RV = combine(N); 971 972 if (RV.getNode() == 0) 973 continue; 974 975 ++NodesCombined; 976 977 // If we get back the same node we passed in, rather than a new node or 978 // zero, we know that the node must have defined multiple values and 979 // CombineTo was used. Since CombineTo takes care of the worklist 980 // mechanics for us, we have no work to do in this case. 981 if (RV.getNode() == N) 982 continue; 983 984 assert(N->getOpcode() != ISD::DELETED_NODE && 985 RV.getNode()->getOpcode() != ISD::DELETED_NODE && 986 "Node was deleted but visit returned new node!"); 987 988 DEBUG(dbgs() << "\nReplacing.3 "; 989 N->dump(&DAG); 990 dbgs() << "\nWith: "; 991 RV.getNode()->dump(&DAG); 992 dbgs() << '\n'); 993 WorkListRemover DeadNodes(*this); 994 if (N->getNumValues() == RV.getNode()->getNumValues()) 995 DAG.ReplaceAllUsesWith(N, RV.getNode(), &DeadNodes); 996 else { 997 assert(N->getValueType(0) == RV.getValueType() && 998 N->getNumValues() == 1 && "Type mismatch"); 999 SDValue OpV = RV; 1000 DAG.ReplaceAllUsesWith(N, &OpV, &DeadNodes); 1001 } 1002 1003 // Push the new node and any users onto the worklist 1004 AddToWorkList(RV.getNode()); 1005 AddUsersToWorkList(RV.getNode()); 1006 1007 // Add any uses of the old node to the worklist in case this node is the 1008 // last one that uses them. They may become dead after this node is 1009 // deleted. 1010 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 1011 AddToWorkList(N->getOperand(i).getNode()); 1012 1013 // Finally, if the node is now dead, remove it from the graph. The node 1014 // may not be dead if the replacement process recursively simplified to 1015 // something else needing this node. 1016 if (N->use_empty()) { 1017 // Nodes can be reintroduced into the worklist. Make sure we do not 1018 // process a node that has been replaced. 1019 removeFromWorkList(N); 1020 1021 // Finally, since the node is now dead, remove it from the graph. 1022 DAG.DeleteNode(N); 1023 } 1024 } 1025 1026 // If the root changed (e.g. it was a dead load, update the root). 1027 DAG.setRoot(Dummy.getValue()); 1028} 1029 1030SDValue DAGCombiner::visit(SDNode *N) { 1031 switch (N->getOpcode()) { 1032 default: break; 1033 case ISD::TokenFactor: return visitTokenFactor(N); 1034 case ISD::MERGE_VALUES: return visitMERGE_VALUES(N); 1035 case ISD::ADD: return visitADD(N); 1036 case ISD::SUB: return visitSUB(N); 1037 case ISD::ADDC: return visitADDC(N); 1038 case ISD::ADDE: return visitADDE(N); 1039 case ISD::MUL: return visitMUL(N); 1040 case ISD::SDIV: return visitSDIV(N); 1041 case ISD::UDIV: return visitUDIV(N); 1042 case ISD::SREM: return visitSREM(N); 1043 case ISD::UREM: return visitUREM(N); 1044 case ISD::MULHU: return visitMULHU(N); 1045 case ISD::MULHS: return visitMULHS(N); 1046 case ISD::SMUL_LOHI: return visitSMUL_LOHI(N); 1047 case ISD::UMUL_LOHI: return visitUMUL_LOHI(N); 1048 case ISD::SDIVREM: return visitSDIVREM(N); 1049 case ISD::UDIVREM: return visitUDIVREM(N); 1050 case ISD::AND: return visitAND(N); 1051 case ISD::OR: return visitOR(N); 1052 case ISD::XOR: return visitXOR(N); 1053 case ISD::SHL: return visitSHL(N); 1054 case ISD::SRA: return visitSRA(N); 1055 case ISD::SRL: return visitSRL(N); 1056 case ISD::CTLZ: return visitCTLZ(N); 1057 case ISD::CTTZ: return visitCTTZ(N); 1058 case ISD::CTPOP: return visitCTPOP(N); 1059 case ISD::SELECT: return visitSELECT(N); 1060 case ISD::SELECT_CC: return visitSELECT_CC(N); 1061 case ISD::SETCC: return visitSETCC(N); 1062 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N); 1063 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N); 1064 case ISD::ANY_EXTEND: return visitANY_EXTEND(N); 1065 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N); 1066 case ISD::TRUNCATE: return visitTRUNCATE(N); 1067 case ISD::BITCAST: return visitBITCAST(N); 1068 case ISD::BUILD_PAIR: return visitBUILD_PAIR(N); 1069 case ISD::FADD: return visitFADD(N); 1070 case ISD::FSUB: return visitFSUB(N); 1071 case ISD::FMUL: return visitFMUL(N); 1072 case ISD::FDIV: return visitFDIV(N); 1073 case ISD::FREM: return visitFREM(N); 1074 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N); 1075 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N); 1076 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N); 1077 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N); 1078 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N); 1079 case ISD::FP_ROUND: return visitFP_ROUND(N); 1080 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N); 1081 case ISD::FP_EXTEND: return visitFP_EXTEND(N); 1082 case ISD::FNEG: return visitFNEG(N); 1083 case ISD::FABS: return visitFABS(N); 1084 case ISD::BRCOND: return visitBRCOND(N); 1085 case ISD::BR_CC: return visitBR_CC(N); 1086 case ISD::LOAD: return visitLOAD(N); 1087 case ISD::STORE: return visitSTORE(N); 1088 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N); 1089 case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N); 1090 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N); 1091 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N); 1092 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N); 1093 case ISD::MEMBARRIER: return visitMEMBARRIER(N); 1094 } 1095 return SDValue(); 1096} 1097 1098SDValue DAGCombiner::combine(SDNode *N) { 1099 SDValue RV = visit(N); 1100 1101 // If nothing happened, try a target-specific DAG combine. 1102 if (RV.getNode() == 0) { 1103 assert(N->getOpcode() != ISD::DELETED_NODE && 1104 "Node was deleted but visit returned NULL!"); 1105 1106 if (N->getOpcode() >= ISD::BUILTIN_OP_END || 1107 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) { 1108 1109 // Expose the DAG combiner to the target combiner impls. 1110 TargetLowering::DAGCombinerInfo 1111 DagCombineInfo(DAG, !LegalTypes, !LegalOperations, false, this); 1112 1113 RV = TLI.PerformDAGCombine(N, DagCombineInfo); 1114 } 1115 } 1116 1117 // If nothing happened still, try promoting the operation. 1118 if (RV.getNode() == 0) { 1119 switch (N->getOpcode()) { 1120 default: break; 1121 case ISD::ADD: 1122 case ISD::SUB: 1123 case ISD::MUL: 1124 case ISD::AND: 1125 case ISD::OR: 1126 case ISD::XOR: 1127 RV = PromoteIntBinOp(SDValue(N, 0)); 1128 break; 1129 case ISD::SHL: 1130 case ISD::SRA: 1131 case ISD::SRL: 1132 RV = PromoteIntShiftOp(SDValue(N, 0)); 1133 break; 1134 case ISD::SIGN_EXTEND: 1135 case ISD::ZERO_EXTEND: 1136 case ISD::ANY_EXTEND: 1137 RV = PromoteExtend(SDValue(N, 0)); 1138 break; 1139 case ISD::LOAD: 1140 if (PromoteLoad(SDValue(N, 0))) 1141 RV = SDValue(N, 0); 1142 break; 1143 } 1144 } 1145 1146 // If N is a commutative binary node, try commuting it to enable more 1147 // sdisel CSE. 1148 if (RV.getNode() == 0 && 1149 SelectionDAG::isCommutativeBinOp(N->getOpcode()) && 1150 N->getNumValues() == 1) { 1151 SDValue N0 = N->getOperand(0); 1152 SDValue N1 = N->getOperand(1); 1153 1154 // Constant operands are canonicalized to RHS. 1155 if (isa<ConstantSDNode>(N0) || !isa<ConstantSDNode>(N1)) { 1156 SDValue Ops[] = { N1, N0 }; 1157 SDNode *CSENode = DAG.getNodeIfExists(N->getOpcode(), N->getVTList(), 1158 Ops, 2); 1159 if (CSENode) 1160 return SDValue(CSENode, 0); 1161 } 1162 } 1163 1164 return RV; 1165} 1166 1167/// getInputChainForNode - Given a node, return its input chain if it has one, 1168/// otherwise return a null sd operand. 1169static SDValue getInputChainForNode(SDNode *N) { 1170 if (unsigned NumOps = N->getNumOperands()) { 1171 if (N->getOperand(0).getValueType() == MVT::Other) 1172 return N->getOperand(0); 1173 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other) 1174 return N->getOperand(NumOps-1); 1175 for (unsigned i = 1; i < NumOps-1; ++i) 1176 if (N->getOperand(i).getValueType() == MVT::Other) 1177 return N->getOperand(i); 1178 } 1179 return SDValue(); 1180} 1181 1182SDValue DAGCombiner::visitTokenFactor(SDNode *N) { 1183 // If N has two operands, where one has an input chain equal to the other, 1184 // the 'other' chain is redundant. 1185 if (N->getNumOperands() == 2) { 1186 if (getInputChainForNode(N->getOperand(0).getNode()) == N->getOperand(1)) 1187 return N->getOperand(0); 1188 if (getInputChainForNode(N->getOperand(1).getNode()) == N->getOperand(0)) 1189 return N->getOperand(1); 1190 } 1191 1192 SmallVector<SDNode *, 8> TFs; // List of token factors to visit. 1193 SmallVector<SDValue, 8> Ops; // Ops for replacing token factor. 1194 SmallPtrSet<SDNode*, 16> SeenOps; 1195 bool Changed = false; // If we should replace this token factor. 1196 1197 // Start out with this token factor. 1198 TFs.push_back(N); 1199 1200 // Iterate through token factors. The TFs grows when new token factors are 1201 // encountered. 1202 for (unsigned i = 0; i < TFs.size(); ++i) { 1203 SDNode *TF = TFs[i]; 1204 1205 // Check each of the operands. 1206 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) { 1207 SDValue Op = TF->getOperand(i); 1208 1209 switch (Op.getOpcode()) { 1210 case ISD::EntryToken: 1211 // Entry tokens don't need to be added to the list. They are 1212 // rededundant. 1213 Changed = true; 1214 break; 1215 1216 case ISD::TokenFactor: 1217 if (Op.hasOneUse() && 1218 std::find(TFs.begin(), TFs.end(), Op.getNode()) == TFs.end()) { 1219 // Queue up for processing. 1220 TFs.push_back(Op.getNode()); 1221 // Clean up in case the token factor is removed. 1222 AddToWorkList(Op.getNode()); 1223 Changed = true; 1224 break; 1225 } 1226 // Fall thru 1227 1228 default: 1229 // Only add if it isn't already in the list. 1230 if (SeenOps.insert(Op.getNode())) 1231 Ops.push_back(Op); 1232 else 1233 Changed = true; 1234 break; 1235 } 1236 } 1237 } 1238 1239 SDValue Result; 1240 1241 // If we've change things around then replace token factor. 1242 if (Changed) { 1243 if (Ops.empty()) { 1244 // The entry token is the only possible outcome. 1245 Result = DAG.getEntryNode(); 1246 } else { 1247 // New and improved token factor. 1248 Result = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 1249 MVT::Other, &Ops[0], Ops.size()); 1250 } 1251 1252 // Don't add users to work list. 1253 return CombineTo(N, Result, false); 1254 } 1255 1256 return Result; 1257} 1258 1259/// MERGE_VALUES can always be eliminated. 1260SDValue DAGCombiner::visitMERGE_VALUES(SDNode *N) { 1261 WorkListRemover DeadNodes(*this); 1262 // Replacing results may cause a different MERGE_VALUES to suddenly 1263 // be CSE'd with N, and carry its uses with it. Iterate until no 1264 // uses remain, to ensure that the node can be safely deleted. 1265 do { 1266 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 1267 DAG.ReplaceAllUsesOfValueWith(SDValue(N, i), N->getOperand(i), 1268 &DeadNodes); 1269 } while (!N->use_empty()); 1270 removeFromWorkList(N); 1271 DAG.DeleteNode(N); 1272 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1273} 1274 1275static 1276SDValue combineShlAddConstant(DebugLoc DL, SDValue N0, SDValue N1, 1277 SelectionDAG &DAG) { 1278 EVT VT = N0.getValueType(); 1279 SDValue N00 = N0.getOperand(0); 1280 SDValue N01 = N0.getOperand(1); 1281 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01); 1282 1283 if (N01C && N00.getOpcode() == ISD::ADD && N00.getNode()->hasOneUse() && 1284 isa<ConstantSDNode>(N00.getOperand(1))) { 1285 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 1286 N0 = DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, 1287 DAG.getNode(ISD::SHL, N00.getDebugLoc(), VT, 1288 N00.getOperand(0), N01), 1289 DAG.getNode(ISD::SHL, N01.getDebugLoc(), VT, 1290 N00.getOperand(1), N01)); 1291 return DAG.getNode(ISD::ADD, DL, VT, N0, N1); 1292 } 1293 1294 return SDValue(); 1295} 1296 1297/// isCarryMaterialization - Returns true if V is an ADDE node that is known to 1298/// return 0 or 1 depending on the carry flag. 1299static bool isCarryMaterialization(SDValue V) { 1300 if (V.getOpcode() != ISD::ADDE) 1301 return false; 1302 1303 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V.getOperand(0)); 1304 return C && C->isNullValue() && V.getOperand(0) == V.getOperand(1); 1305} 1306 1307SDValue DAGCombiner::visitADD(SDNode *N) { 1308 SDValue N0 = N->getOperand(0); 1309 SDValue N1 = N->getOperand(1); 1310 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1311 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1312 EVT VT = N0.getValueType(); 1313 1314 // fold vector ops 1315 if (VT.isVector()) { 1316 SDValue FoldedVOp = SimplifyVBinOp(N); 1317 if (FoldedVOp.getNode()) return FoldedVOp; 1318 } 1319 1320 // fold (add x, undef) -> undef 1321 if (N0.getOpcode() == ISD::UNDEF) 1322 return N0; 1323 if (N1.getOpcode() == ISD::UNDEF) 1324 return N1; 1325 // fold (add c1, c2) -> c1+c2 1326 if (N0C && N1C) 1327 return DAG.FoldConstantArithmetic(ISD::ADD, VT, N0C, N1C); 1328 // canonicalize constant to RHS 1329 if (N0C && !N1C) 1330 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0); 1331 // fold (add x, 0) -> x 1332 if (N1C && N1C->isNullValue()) 1333 return N0; 1334 // fold (add Sym, c) -> Sym+c 1335 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0)) 1336 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA) && N1C && 1337 GA->getOpcode() == ISD::GlobalAddress) 1338 return DAG.getGlobalAddress(GA->getGlobal(), N1C->getDebugLoc(), VT, 1339 GA->getOffset() + 1340 (uint64_t)N1C->getSExtValue()); 1341 // fold ((c1-A)+c2) -> (c1+c2)-A 1342 if (N1C && N0.getOpcode() == ISD::SUB) 1343 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0))) 1344 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1345 DAG.getConstant(N1C->getAPIntValue()+ 1346 N0C->getAPIntValue(), VT), 1347 N0.getOperand(1)); 1348 // reassociate add 1349 SDValue RADD = ReassociateOps(ISD::ADD, N->getDebugLoc(), N0, N1); 1350 if (RADD.getNode() != 0) 1351 return RADD; 1352 // fold ((0-A) + B) -> B-A 1353 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) && 1354 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue()) 1355 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1, N0.getOperand(1)); 1356 // fold (A + (0-B)) -> A-B 1357 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) && 1358 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue()) 1359 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, N1.getOperand(1)); 1360 // fold (A+(B-A)) -> B 1361 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1)) 1362 return N1.getOperand(0); 1363 // fold ((B-A)+A) -> B 1364 if (N0.getOpcode() == ISD::SUB && N1 == N0.getOperand(1)) 1365 return N0.getOperand(0); 1366 // fold (A+(B-(A+C))) to (B-C) 1367 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD && 1368 N0 == N1.getOperand(1).getOperand(0)) 1369 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0), 1370 N1.getOperand(1).getOperand(1)); 1371 // fold (A+(B-(C+A))) to (B-C) 1372 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD && 1373 N0 == N1.getOperand(1).getOperand(1)) 1374 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0), 1375 N1.getOperand(1).getOperand(0)); 1376 // fold (A+((B-A)+or-C)) to (B+or-C) 1377 if ((N1.getOpcode() == ISD::SUB || N1.getOpcode() == ISD::ADD) && 1378 N1.getOperand(0).getOpcode() == ISD::SUB && 1379 N0 == N1.getOperand(0).getOperand(1)) 1380 return DAG.getNode(N1.getOpcode(), N->getDebugLoc(), VT, 1381 N1.getOperand(0).getOperand(0), N1.getOperand(1)); 1382 1383 // fold (A-B)+(C-D) to (A+C)-(B+D) when A or C is constant 1384 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB) { 1385 SDValue N00 = N0.getOperand(0); 1386 SDValue N01 = N0.getOperand(1); 1387 SDValue N10 = N1.getOperand(0); 1388 SDValue N11 = N1.getOperand(1); 1389 1390 if (isa<ConstantSDNode>(N00) || isa<ConstantSDNode>(N10)) 1391 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1392 DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, N00, N10), 1393 DAG.getNode(ISD::ADD, N1.getDebugLoc(), VT, N01, N11)); 1394 } 1395 1396 if (!VT.isVector() && SimplifyDemandedBits(SDValue(N, 0))) 1397 return SDValue(N, 0); 1398 1399 // fold (a+b) -> (a|b) iff a and b share no bits. 1400 if (VT.isInteger() && !VT.isVector()) { 1401 APInt LHSZero, LHSOne; 1402 APInt RHSZero, RHSOne; 1403 APInt Mask = APInt::getAllOnesValue(VT.getScalarType().getSizeInBits()); 1404 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 1405 1406 if (LHSZero.getBoolValue()) { 1407 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 1408 1409 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1410 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1411 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 1412 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 1413 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1); 1414 } 1415 } 1416 1417 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 1418 if (N0.getOpcode() == ISD::SHL && N0.getNode()->hasOneUse()) { 1419 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N0, N1, DAG); 1420 if (Result.getNode()) return Result; 1421 } 1422 if (N1.getOpcode() == ISD::SHL && N1.getNode()->hasOneUse()) { 1423 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N1, N0, DAG); 1424 if (Result.getNode()) return Result; 1425 } 1426 1427 // fold (add x, shl(0 - y, n)) -> sub(x, shl(y, n)) 1428 if (N1.getOpcode() == ISD::SHL && 1429 N1.getOperand(0).getOpcode() == ISD::SUB) 1430 if (ConstantSDNode *C = 1431 dyn_cast<ConstantSDNode>(N1.getOperand(0).getOperand(0))) 1432 if (C->getAPIntValue() == 0) 1433 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, 1434 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1435 N1.getOperand(0).getOperand(1), 1436 N1.getOperand(1))); 1437 if (N0.getOpcode() == ISD::SHL && 1438 N0.getOperand(0).getOpcode() == ISD::SUB) 1439 if (ConstantSDNode *C = 1440 dyn_cast<ConstantSDNode>(N0.getOperand(0).getOperand(0))) 1441 if (C->getAPIntValue() == 0) 1442 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1, 1443 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1444 N0.getOperand(0).getOperand(1), 1445 N0.getOperand(1))); 1446 1447 if (N1.getOpcode() == ISD::AND) { 1448 SDValue AndOp0 = N1.getOperand(0); 1449 ConstantSDNode *AndOp1 = dyn_cast<ConstantSDNode>(N1->getOperand(1)); 1450 unsigned NumSignBits = DAG.ComputeNumSignBits(AndOp0); 1451 unsigned DestBits = VT.getScalarType().getSizeInBits(); 1452 1453 // (add z, (and (sbbl x, x), 1)) -> (sub z, (sbbl x, x)) 1454 // and similar xforms where the inner op is either ~0 or 0. 1455 if (NumSignBits == DestBits && AndOp1 && AndOp1->isOne()) { 1456 DebugLoc DL = N->getDebugLoc(); 1457 return DAG.getNode(ISD::SUB, DL, VT, N->getOperand(0), AndOp0); 1458 } 1459 } 1460 1461 // add (sext i1), X -> sub X, (zext i1) 1462 if (N0.getOpcode() == ISD::SIGN_EXTEND && 1463 N0.getOperand(0).getValueType() == MVT::i1 && 1464 !TLI.isOperationLegal(ISD::SIGN_EXTEND, MVT::i1)) { 1465 DebugLoc DL = N->getDebugLoc(); 1466 SDValue ZExt = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0)); 1467 return DAG.getNode(ISD::SUB, DL, VT, N1, ZExt); 1468 } 1469 1470 // add (adde 0, 0, glue), X -> adde X, 0, glue 1471 if (N0->hasOneUse() && isCarryMaterialization(N0)) 1472 return DAG.getNode(ISD::ADDE, N->getDebugLoc(), 1473 DAG.getVTList(VT, MVT::Glue), N1, N0.getOperand(0), 1474 N0.getOperand(2)); 1475 1476 // add X, (adde 0, 0, glue) -> adde X, 0, glue 1477 if (N1->hasOneUse() && isCarryMaterialization(N1)) 1478 return DAG.getNode(ISD::ADDE, N->getDebugLoc(), 1479 DAG.getVTList(VT, MVT::Glue), N0, N1.getOperand(0), 1480 N1.getOperand(2)); 1481 1482 return SDValue(); 1483} 1484 1485SDValue DAGCombiner::visitADDC(SDNode *N) { 1486 SDValue N0 = N->getOperand(0); 1487 SDValue N1 = N->getOperand(1); 1488 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1489 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1490 EVT VT = N0.getValueType(); 1491 1492 // If the flag result is dead, turn this into an ADD. 1493 if (N->hasNUsesOfValue(0, 1)) 1494 return CombineTo(N, DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0), 1495 DAG.getNode(ISD::CARRY_FALSE, 1496 N->getDebugLoc(), MVT::Glue)); 1497 1498 // canonicalize constant to RHS. 1499 if (N0C && !N1C) 1500 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0); 1501 1502 // fold (addc x, 0) -> x + no carry out 1503 if (N1C && N1C->isNullValue()) 1504 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, 1505 N->getDebugLoc(), MVT::Glue)); 1506 1507 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits. 1508 APInt LHSZero, LHSOne; 1509 APInt RHSZero, RHSOne; 1510 APInt Mask = APInt::getAllOnesValue(VT.getScalarType().getSizeInBits()); 1511 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 1512 1513 if (LHSZero.getBoolValue()) { 1514 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 1515 1516 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1517 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1518 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 1519 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 1520 return CombineTo(N, DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1), 1521 DAG.getNode(ISD::CARRY_FALSE, 1522 N->getDebugLoc(), MVT::Glue)); 1523 } 1524 1525 // addc (adde 0, 0, glue), X -> adde X, 0, glue 1526 if (N0->hasOneUse() && isCarryMaterialization(N0)) 1527 return DAG.getNode(ISD::ADDE, N->getDebugLoc(), N->getVTList(), N1, 1528 DAG.getConstant(0, VT), N0.getOperand(2)); 1529 1530 // addc X, (adde 0, 0, glue) -> adde X, 0, glue 1531 if (N1->hasOneUse() && isCarryMaterialization(N1)) 1532 return DAG.getNode(ISD::ADDE, N->getDebugLoc(), N->getVTList(), N0, 1533 DAG.getConstant(0, VT), N1.getOperand(2)); 1534 1535 return SDValue(); 1536} 1537 1538SDValue DAGCombiner::visitADDE(SDNode *N) { 1539 SDValue N0 = N->getOperand(0); 1540 SDValue N1 = N->getOperand(1); 1541 SDValue CarryIn = N->getOperand(2); 1542 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1543 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1544 1545 // If both operands are null we know that carry out will always be false. 1546 if (N0C && N0C->isNullValue() && N0 == N1) 1547 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), DAG.getNode(ISD::CARRY_FALSE, 1548 N->getDebugLoc(), 1549 MVT::Glue)); 1550 1551 // canonicalize constant to RHS 1552 if (N0C && !N1C) 1553 return DAG.getNode(ISD::ADDE, N->getDebugLoc(), N->getVTList(), 1554 N1, N0, CarryIn); 1555 1556 // fold (adde x, y, false) -> (addc x, y) 1557 if (CarryIn.getOpcode() == ISD::CARRY_FALSE) 1558 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0); 1559 1560 return SDValue(); 1561} 1562 1563// Since it may not be valid to emit a fold to zero for vector initializers 1564// check if we can before folding. 1565static SDValue tryFoldToZero(DebugLoc DL, const TargetLowering &TLI, EVT VT, 1566 SelectionDAG &DAG, bool LegalOperations) { 1567 if (!VT.isVector()) { 1568 return DAG.getConstant(0, VT); 1569 } else if (!LegalOperations || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) { 1570 // Produce a vector of zeros. 1571 SDValue El = DAG.getConstant(0, VT.getVectorElementType()); 1572 std::vector<SDValue> Ops(VT.getVectorNumElements(), El); 1573 return DAG.getNode(ISD::BUILD_VECTOR, DL, VT, 1574 &Ops[0], Ops.size()); 1575 } 1576 return SDValue(); 1577} 1578 1579SDValue DAGCombiner::visitSUB(SDNode *N) { 1580 SDValue N0 = N->getOperand(0); 1581 SDValue N1 = N->getOperand(1); 1582 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1583 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1584 EVT VT = N0.getValueType(); 1585 1586 // fold vector ops 1587 if (VT.isVector()) { 1588 SDValue FoldedVOp = SimplifyVBinOp(N); 1589 if (FoldedVOp.getNode()) return FoldedVOp; 1590 } 1591 1592 // fold (sub x, x) -> 0 1593 // FIXME: Refactor this and xor and other similar operations together. 1594 if (N0 == N1) 1595 return tryFoldToZero(N->getDebugLoc(), TLI, VT, DAG, LegalOperations); 1596 // fold (sub c1, c2) -> c1-c2 1597 if (N0C && N1C) 1598 return DAG.FoldConstantArithmetic(ISD::SUB, VT, N0C, N1C); 1599 // fold (sub x, c) -> (add x, -c) 1600 if (N1C) 1601 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, 1602 DAG.getConstant(-N1C->getAPIntValue(), VT)); 1603 // Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1) 1604 if (N0C && N0C->isAllOnesValue()) 1605 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0); 1606 // fold A-(A-B) -> B 1607 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(0)) 1608 return N1.getOperand(1); 1609 // fold (A+B)-A -> B 1610 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1) 1611 return N0.getOperand(1); 1612 // fold (A+B)-B -> A 1613 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1) 1614 return N0.getOperand(0); 1615 // fold ((A+(B+or-C))-B) -> A+or-C 1616 if (N0.getOpcode() == ISD::ADD && 1617 (N0.getOperand(1).getOpcode() == ISD::SUB || 1618 N0.getOperand(1).getOpcode() == ISD::ADD) && 1619 N0.getOperand(1).getOperand(0) == N1) 1620 return DAG.getNode(N0.getOperand(1).getOpcode(), N->getDebugLoc(), VT, 1621 N0.getOperand(0), N0.getOperand(1).getOperand(1)); 1622 // fold ((A+(C+B))-B) -> A+C 1623 if (N0.getOpcode() == ISD::ADD && 1624 N0.getOperand(1).getOpcode() == ISD::ADD && 1625 N0.getOperand(1).getOperand(1) == N1) 1626 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, 1627 N0.getOperand(0), N0.getOperand(1).getOperand(0)); 1628 // fold ((A-(B-C))-C) -> A-B 1629 if (N0.getOpcode() == ISD::SUB && 1630 N0.getOperand(1).getOpcode() == ISD::SUB && 1631 N0.getOperand(1).getOperand(1) == N1) 1632 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1633 N0.getOperand(0), N0.getOperand(1).getOperand(0)); 1634 1635 // If either operand of a sub is undef, the result is undef 1636 if (N0.getOpcode() == ISD::UNDEF) 1637 return N0; 1638 if (N1.getOpcode() == ISD::UNDEF) 1639 return N1; 1640 1641 // If the relocation model supports it, consider symbol offsets. 1642 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0)) 1643 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA)) { 1644 // fold (sub Sym, c) -> Sym-c 1645 if (N1C && GA->getOpcode() == ISD::GlobalAddress) 1646 return DAG.getGlobalAddress(GA->getGlobal(), N1C->getDebugLoc(), VT, 1647 GA->getOffset() - 1648 (uint64_t)N1C->getSExtValue()); 1649 // fold (sub Sym+c1, Sym+c2) -> c1-c2 1650 if (GlobalAddressSDNode *GB = dyn_cast<GlobalAddressSDNode>(N1)) 1651 if (GA->getGlobal() == GB->getGlobal()) 1652 return DAG.getConstant((uint64_t)GA->getOffset() - GB->getOffset(), 1653 VT); 1654 } 1655 1656 return SDValue(); 1657} 1658 1659SDValue DAGCombiner::visitMUL(SDNode *N) { 1660 SDValue N0 = N->getOperand(0); 1661 SDValue N1 = N->getOperand(1); 1662 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1663 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1664 EVT VT = N0.getValueType(); 1665 1666 // fold vector ops 1667 if (VT.isVector()) { 1668 SDValue FoldedVOp = SimplifyVBinOp(N); 1669 if (FoldedVOp.getNode()) return FoldedVOp; 1670 } 1671 1672 // fold (mul x, undef) -> 0 1673 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1674 return DAG.getConstant(0, VT); 1675 // fold (mul c1, c2) -> c1*c2 1676 if (N0C && N1C) 1677 return DAG.FoldConstantArithmetic(ISD::MUL, VT, N0C, N1C); 1678 // canonicalize constant to RHS 1679 if (N0C && !N1C) 1680 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, N1, N0); 1681 // fold (mul x, 0) -> 0 1682 if (N1C && N1C->isNullValue()) 1683 return N1; 1684 // fold (mul x, -1) -> 0-x 1685 if (N1C && N1C->isAllOnesValue()) 1686 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1687 DAG.getConstant(0, VT), N0); 1688 // fold (mul x, (1 << c)) -> x << c 1689 if (N1C && N1C->getAPIntValue().isPowerOf2()) 1690 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 1691 DAG.getConstant(N1C->getAPIntValue().logBase2(), 1692 getShiftAmountTy(N0.getValueType()))); 1693 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c 1694 if (N1C && (-N1C->getAPIntValue()).isPowerOf2()) { 1695 unsigned Log2Val = (-N1C->getAPIntValue()).logBase2(); 1696 // FIXME: If the input is something that is easily negated (e.g. a 1697 // single-use add), we should put the negate there. 1698 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1699 DAG.getConstant(0, VT), 1700 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 1701 DAG.getConstant(Log2Val, 1702 getShiftAmountTy(N0.getValueType())))); 1703 } 1704 // (mul (shl X, c1), c2) -> (mul X, c2 << c1) 1705 if (N1C && N0.getOpcode() == ISD::SHL && 1706 isa<ConstantSDNode>(N0.getOperand(1))) { 1707 SDValue C3 = DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1708 N1, N0.getOperand(1)); 1709 AddToWorkList(C3.getNode()); 1710 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1711 N0.getOperand(0), C3); 1712 } 1713 1714 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one 1715 // use. 1716 { 1717 SDValue Sh(0,0), Y(0,0); 1718 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)). 1719 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) && 1720 N0.getNode()->hasOneUse()) { 1721 Sh = N0; Y = N1; 1722 } else if (N1.getOpcode() == ISD::SHL && 1723 isa<ConstantSDNode>(N1.getOperand(1)) && 1724 N1.getNode()->hasOneUse()) { 1725 Sh = N1; Y = N0; 1726 } 1727 1728 if (Sh.getNode()) { 1729 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1730 Sh.getOperand(0), Y); 1731 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1732 Mul, Sh.getOperand(1)); 1733 } 1734 } 1735 1736 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2) 1737 if (N1C && N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse() && 1738 isa<ConstantSDNode>(N0.getOperand(1))) 1739 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, 1740 DAG.getNode(ISD::MUL, N0.getDebugLoc(), VT, 1741 N0.getOperand(0), N1), 1742 DAG.getNode(ISD::MUL, N1.getDebugLoc(), VT, 1743 N0.getOperand(1), N1)); 1744 1745 // reassociate mul 1746 SDValue RMUL = ReassociateOps(ISD::MUL, N->getDebugLoc(), N0, N1); 1747 if (RMUL.getNode() != 0) 1748 return RMUL; 1749 1750 return SDValue(); 1751} 1752 1753SDValue DAGCombiner::visitSDIV(SDNode *N) { 1754 SDValue N0 = N->getOperand(0); 1755 SDValue N1 = N->getOperand(1); 1756 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1757 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1758 EVT VT = N->getValueType(0); 1759 1760 // fold vector ops 1761 if (VT.isVector()) { 1762 SDValue FoldedVOp = SimplifyVBinOp(N); 1763 if (FoldedVOp.getNode()) return FoldedVOp; 1764 } 1765 1766 // fold (sdiv c1, c2) -> c1/c2 1767 if (N0C && N1C && !N1C->isNullValue()) 1768 return DAG.FoldConstantArithmetic(ISD::SDIV, VT, N0C, N1C); 1769 // fold (sdiv X, 1) -> X 1770 if (N1C && N1C->getSExtValue() == 1LL) 1771 return N0; 1772 // fold (sdiv X, -1) -> 0-X 1773 if (N1C && N1C->isAllOnesValue()) 1774 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1775 DAG.getConstant(0, VT), N0); 1776 // If we know the sign bits of both operands are zero, strength reduce to a 1777 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2 1778 if (!VT.isVector()) { 1779 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 1780 return DAG.getNode(ISD::UDIV, N->getDebugLoc(), N1.getValueType(), 1781 N0, N1); 1782 } 1783 // fold (sdiv X, pow2) -> simple ops after legalize 1784 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap() && 1785 (isPowerOf2_64(N1C->getSExtValue()) || 1786 isPowerOf2_64(-N1C->getSExtValue()))) { 1787 // If dividing by powers of two is cheap, then don't perform the following 1788 // fold. 1789 if (TLI.isPow2DivCheap()) 1790 return SDValue(); 1791 1792 int64_t pow2 = N1C->getSExtValue(); 1793 int64_t abs2 = pow2 > 0 ? pow2 : -pow2; 1794 unsigned lg2 = Log2_64(abs2); 1795 1796 // Splat the sign bit into the register 1797 SDValue SGN = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0, 1798 DAG.getConstant(VT.getSizeInBits()-1, 1799 getShiftAmountTy(N0.getValueType()))); 1800 AddToWorkList(SGN.getNode()); 1801 1802 // Add (N0 < 0) ? abs2 - 1 : 0; 1803 SDValue SRL = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, SGN, 1804 DAG.getConstant(VT.getSizeInBits() - lg2, 1805 getShiftAmountTy(SGN.getValueType()))); 1806 SDValue ADD = DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, SRL); 1807 AddToWorkList(SRL.getNode()); 1808 AddToWorkList(ADD.getNode()); // Divide by pow2 1809 SDValue SRA = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, ADD, 1810 DAG.getConstant(lg2, getShiftAmountTy(ADD.getValueType()))); 1811 1812 // If we're dividing by a positive value, we're done. Otherwise, we must 1813 // negate the result. 1814 if (pow2 > 0) 1815 return SRA; 1816 1817 AddToWorkList(SRA.getNode()); 1818 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1819 DAG.getConstant(0, VT), SRA); 1820 } 1821 1822 // if integer divide is expensive and we satisfy the requirements, emit an 1823 // alternate sequence. 1824 if (N1C && (N1C->getSExtValue() < -1 || N1C->getSExtValue() > 1) && 1825 !TLI.isIntDivCheap()) { 1826 SDValue Op = BuildSDIV(N); 1827 if (Op.getNode()) return Op; 1828 } 1829 1830 // undef / X -> 0 1831 if (N0.getOpcode() == ISD::UNDEF) 1832 return DAG.getConstant(0, VT); 1833 // X / undef -> undef 1834 if (N1.getOpcode() == ISD::UNDEF) 1835 return N1; 1836 1837 return SDValue(); 1838} 1839 1840SDValue DAGCombiner::visitUDIV(SDNode *N) { 1841 SDValue N0 = N->getOperand(0); 1842 SDValue N1 = N->getOperand(1); 1843 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1844 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1845 EVT VT = N->getValueType(0); 1846 1847 // fold vector ops 1848 if (VT.isVector()) { 1849 SDValue FoldedVOp = SimplifyVBinOp(N); 1850 if (FoldedVOp.getNode()) return FoldedVOp; 1851 } 1852 1853 // fold (udiv c1, c2) -> c1/c2 1854 if (N0C && N1C && !N1C->isNullValue()) 1855 return DAG.FoldConstantArithmetic(ISD::UDIV, VT, N0C, N1C); 1856 // fold (udiv x, (1 << c)) -> x >>u c 1857 if (N1C && N1C->getAPIntValue().isPowerOf2()) 1858 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, 1859 DAG.getConstant(N1C->getAPIntValue().logBase2(), 1860 getShiftAmountTy(N0.getValueType()))); 1861 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2 1862 if (N1.getOpcode() == ISD::SHL) { 1863 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1864 if (SHC->getAPIntValue().isPowerOf2()) { 1865 EVT ADDVT = N1.getOperand(1).getValueType(); 1866 SDValue Add = DAG.getNode(ISD::ADD, N->getDebugLoc(), ADDVT, 1867 N1.getOperand(1), 1868 DAG.getConstant(SHC->getAPIntValue() 1869 .logBase2(), 1870 ADDVT)); 1871 AddToWorkList(Add.getNode()); 1872 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, Add); 1873 } 1874 } 1875 } 1876 // fold (udiv x, c) -> alternate 1877 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) { 1878 SDValue Op = BuildUDIV(N); 1879 if (Op.getNode()) return Op; 1880 } 1881 1882 // undef / X -> 0 1883 if (N0.getOpcode() == ISD::UNDEF) 1884 return DAG.getConstant(0, VT); 1885 // X / undef -> undef 1886 if (N1.getOpcode() == ISD::UNDEF) 1887 return N1; 1888 1889 return SDValue(); 1890} 1891 1892SDValue DAGCombiner::visitSREM(SDNode *N) { 1893 SDValue N0 = N->getOperand(0); 1894 SDValue N1 = N->getOperand(1); 1895 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1896 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1897 EVT VT = N->getValueType(0); 1898 1899 // fold (srem c1, c2) -> c1%c2 1900 if (N0C && N1C && !N1C->isNullValue()) 1901 return DAG.FoldConstantArithmetic(ISD::SREM, VT, N0C, N1C); 1902 // If we know the sign bits of both operands are zero, strength reduce to a 1903 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15 1904 if (!VT.isVector()) { 1905 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 1906 return DAG.getNode(ISD::UREM, N->getDebugLoc(), VT, N0, N1); 1907 } 1908 1909 // If X/C can be simplified by the division-by-constant logic, lower 1910 // X%C to the equivalent of X-X/C*C. 1911 if (N1C && !N1C->isNullValue()) { 1912 SDValue Div = DAG.getNode(ISD::SDIV, N->getDebugLoc(), VT, N0, N1); 1913 AddToWorkList(Div.getNode()); 1914 SDValue OptimizedDiv = combine(Div.getNode()); 1915 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) { 1916 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1917 OptimizedDiv, N1); 1918 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul); 1919 AddToWorkList(Mul.getNode()); 1920 return Sub; 1921 } 1922 } 1923 1924 // undef % X -> 0 1925 if (N0.getOpcode() == ISD::UNDEF) 1926 return DAG.getConstant(0, VT); 1927 // X % undef -> undef 1928 if (N1.getOpcode() == ISD::UNDEF) 1929 return N1; 1930 1931 return SDValue(); 1932} 1933 1934SDValue DAGCombiner::visitUREM(SDNode *N) { 1935 SDValue N0 = N->getOperand(0); 1936 SDValue N1 = N->getOperand(1); 1937 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1938 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1939 EVT VT = N->getValueType(0); 1940 1941 // fold (urem c1, c2) -> c1%c2 1942 if (N0C && N1C && !N1C->isNullValue()) 1943 return DAG.FoldConstantArithmetic(ISD::UREM, VT, N0C, N1C); 1944 // fold (urem x, pow2) -> (and x, pow2-1) 1945 if (N1C && !N1C->isNullValue() && N1C->getAPIntValue().isPowerOf2()) 1946 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, 1947 DAG.getConstant(N1C->getAPIntValue()-1,VT)); 1948 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1)) 1949 if (N1.getOpcode() == ISD::SHL) { 1950 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1951 if (SHC->getAPIntValue().isPowerOf2()) { 1952 SDValue Add = 1953 DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, 1954 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), 1955 VT)); 1956 AddToWorkList(Add.getNode()); 1957 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, Add); 1958 } 1959 } 1960 } 1961 1962 // If X/C can be simplified by the division-by-constant logic, lower 1963 // X%C to the equivalent of X-X/C*C. 1964 if (N1C && !N1C->isNullValue()) { 1965 SDValue Div = DAG.getNode(ISD::UDIV, N->getDebugLoc(), VT, N0, N1); 1966 AddToWorkList(Div.getNode()); 1967 SDValue OptimizedDiv = combine(Div.getNode()); 1968 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) { 1969 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1970 OptimizedDiv, N1); 1971 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul); 1972 AddToWorkList(Mul.getNode()); 1973 return Sub; 1974 } 1975 } 1976 1977 // undef % X -> 0 1978 if (N0.getOpcode() == ISD::UNDEF) 1979 return DAG.getConstant(0, VT); 1980 // X % undef -> undef 1981 if (N1.getOpcode() == ISD::UNDEF) 1982 return N1; 1983 1984 return SDValue(); 1985} 1986 1987SDValue DAGCombiner::visitMULHS(SDNode *N) { 1988 SDValue N0 = N->getOperand(0); 1989 SDValue N1 = N->getOperand(1); 1990 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1991 EVT VT = N->getValueType(0); 1992 DebugLoc DL = N->getDebugLoc(); 1993 1994 // fold (mulhs x, 0) -> 0 1995 if (N1C && N1C->isNullValue()) 1996 return N1; 1997 // fold (mulhs x, 1) -> (sra x, size(x)-1) 1998 if (N1C && N1C->getAPIntValue() == 1) 1999 return DAG.getNode(ISD::SRA, N->getDebugLoc(), N0.getValueType(), N0, 2000 DAG.getConstant(N0.getValueType().getSizeInBits() - 1, 2001 getShiftAmountTy(N0.getValueType()))); 2002 // fold (mulhs x, undef) -> 0 2003 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 2004 return DAG.getConstant(0, VT); 2005 2006 // If the type twice as wide is legal, transform the mulhs to a wider multiply 2007 // plus a shift. 2008 if (VT.isSimple() && !VT.isVector()) { 2009 MVT Simple = VT.getSimpleVT(); 2010 unsigned SimpleSize = Simple.getSizeInBits(); 2011 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2); 2012 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { 2013 N0 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N0); 2014 N1 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N1); 2015 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1); 2016 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1, 2017 DAG.getConstant(SimpleSize, getShiftAmountTy(N1.getValueType()))); 2018 return DAG.getNode(ISD::TRUNCATE, DL, VT, N1); 2019 } 2020 } 2021 2022 return SDValue(); 2023} 2024 2025SDValue DAGCombiner::visitMULHU(SDNode *N) { 2026 SDValue N0 = N->getOperand(0); 2027 SDValue N1 = N->getOperand(1); 2028 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2029 EVT VT = N->getValueType(0); 2030 DebugLoc DL = N->getDebugLoc(); 2031 2032 // fold (mulhu x, 0) -> 0 2033 if (N1C && N1C->isNullValue()) 2034 return N1; 2035 // fold (mulhu x, 1) -> 0 2036 if (N1C && N1C->getAPIntValue() == 1) 2037 return DAG.getConstant(0, N0.getValueType()); 2038 // fold (mulhu x, undef) -> 0 2039 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 2040 return DAG.getConstant(0, VT); 2041 2042 // If the type twice as wide is legal, transform the mulhu to a wider multiply 2043 // plus a shift. 2044 if (VT.isSimple() && !VT.isVector()) { 2045 MVT Simple = VT.getSimpleVT(); 2046 unsigned SimpleSize = Simple.getSizeInBits(); 2047 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2); 2048 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { 2049 N0 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N0); 2050 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N1); 2051 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1); 2052 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1, 2053 DAG.getConstant(SimpleSize, getShiftAmountTy(N1.getValueType()))); 2054 return DAG.getNode(ISD::TRUNCATE, DL, VT, N1); 2055 } 2056 } 2057 2058 return SDValue(); 2059} 2060 2061/// SimplifyNodeWithTwoResults - Perform optimizations common to nodes that 2062/// compute two values. LoOp and HiOp give the opcodes for the two computations 2063/// that are being performed. Return true if a simplification was made. 2064/// 2065SDValue DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 2066 unsigned HiOp) { 2067 // If the high half is not needed, just compute the low half. 2068 bool HiExists = N->hasAnyUseOfValue(1); 2069 if (!HiExists && 2070 (!LegalOperations || 2071 TLI.isOperationLegal(LoOp, N->getValueType(0)))) { 2072 SDValue Res = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0), 2073 N->op_begin(), N->getNumOperands()); 2074 return CombineTo(N, Res, Res); 2075 } 2076 2077 // If the low half is not needed, just compute the high half. 2078 bool LoExists = N->hasAnyUseOfValue(0); 2079 if (!LoExists && 2080 (!LegalOperations || 2081 TLI.isOperationLegal(HiOp, N->getValueType(1)))) { 2082 SDValue Res = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1), 2083 N->op_begin(), N->getNumOperands()); 2084 return CombineTo(N, Res, Res); 2085 } 2086 2087 // If both halves are used, return as it is. 2088 if (LoExists && HiExists) 2089 return SDValue(); 2090 2091 // If the two computed results can be simplified separately, separate them. 2092 if (LoExists) { 2093 SDValue Lo = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0), 2094 N->op_begin(), N->getNumOperands()); 2095 AddToWorkList(Lo.getNode()); 2096 SDValue LoOpt = combine(Lo.getNode()); 2097 if (LoOpt.getNode() && LoOpt.getNode() != Lo.getNode() && 2098 (!LegalOperations || 2099 TLI.isOperationLegal(LoOpt.getOpcode(), LoOpt.getValueType()))) 2100 return CombineTo(N, LoOpt, LoOpt); 2101 } 2102 2103 if (HiExists) { 2104 SDValue Hi = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1), 2105 N->op_begin(), N->getNumOperands()); 2106 AddToWorkList(Hi.getNode()); 2107 SDValue HiOpt = combine(Hi.getNode()); 2108 if (HiOpt.getNode() && HiOpt != Hi && 2109 (!LegalOperations || 2110 TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType()))) 2111 return CombineTo(N, HiOpt, HiOpt); 2112 } 2113 2114 return SDValue(); 2115} 2116 2117SDValue DAGCombiner::visitSMUL_LOHI(SDNode *N) { 2118 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS); 2119 if (Res.getNode()) return Res; 2120 2121 EVT VT = N->getValueType(0); 2122 DebugLoc DL = N->getDebugLoc(); 2123 2124 // If the type twice as wide is legal, transform the mulhu to a wider multiply 2125 // plus a shift. 2126 if (VT.isSimple() && !VT.isVector()) { 2127 MVT Simple = VT.getSimpleVT(); 2128 unsigned SimpleSize = Simple.getSizeInBits(); 2129 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2); 2130 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { 2131 SDValue Lo = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(0)); 2132 SDValue Hi = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(1)); 2133 Lo = DAG.getNode(ISD::MUL, DL, NewVT, Lo, Hi); 2134 // Compute the high part as N1. 2135 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo, 2136 DAG.getConstant(SimpleSize, getShiftAmountTy(Lo.getValueType()))); 2137 Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi); 2138 // Compute the low part as N0. 2139 Lo = DAG.getNode(ISD::TRUNCATE, DL, VT, Lo); 2140 return CombineTo(N, Lo, Hi); 2141 } 2142 } 2143 2144 return SDValue(); 2145} 2146 2147SDValue DAGCombiner::visitUMUL_LOHI(SDNode *N) { 2148 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU); 2149 if (Res.getNode()) return Res; 2150 2151 EVT VT = N->getValueType(0); 2152 DebugLoc DL = N->getDebugLoc(); 2153 2154 // If the type twice as wide is legal, transform the mulhu to a wider multiply 2155 // plus a shift. 2156 if (VT.isSimple() && !VT.isVector()) { 2157 MVT Simple = VT.getSimpleVT(); 2158 unsigned SimpleSize = Simple.getSizeInBits(); 2159 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2); 2160 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { 2161 SDValue Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(0)); 2162 SDValue Hi = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(1)); 2163 Lo = DAG.getNode(ISD::MUL, DL, NewVT, Lo, Hi); 2164 // Compute the high part as N1. 2165 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo, 2166 DAG.getConstant(SimpleSize, getShiftAmountTy(Lo.getValueType()))); 2167 Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi); 2168 // Compute the low part as N0. 2169 Lo = DAG.getNode(ISD::TRUNCATE, DL, VT, Lo); 2170 return CombineTo(N, Lo, Hi); 2171 } 2172 } 2173 2174 return SDValue(); 2175} 2176 2177SDValue DAGCombiner::visitSDIVREM(SDNode *N) { 2178 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM); 2179 if (Res.getNode()) return Res; 2180 2181 return SDValue(); 2182} 2183 2184SDValue DAGCombiner::visitUDIVREM(SDNode *N) { 2185 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM); 2186 if (Res.getNode()) return Res; 2187 2188 return SDValue(); 2189} 2190 2191/// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with 2192/// two operands of the same opcode, try to simplify it. 2193SDValue DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) { 2194 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1); 2195 EVT VT = N0.getValueType(); 2196 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!"); 2197 2198 // Bail early if none of these transforms apply. 2199 if (N0.getNode()->getNumOperands() == 0) return SDValue(); 2200 2201 // For each of OP in AND/OR/XOR: 2202 // fold (OP (zext x), (zext y)) -> (zext (OP x, y)) 2203 // fold (OP (sext x), (sext y)) -> (sext (OP x, y)) 2204 // fold (OP (aext x), (aext y)) -> (aext (OP x, y)) 2205 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y)) (if trunc isn't free) 2206 // 2207 // do not sink logical op inside of a vector extend, since it may combine 2208 // into a vsetcc. 2209 EVT Op0VT = N0.getOperand(0).getValueType(); 2210 if ((N0.getOpcode() == ISD::ZERO_EXTEND || 2211 N0.getOpcode() == ISD::SIGN_EXTEND || 2212 // Avoid infinite looping with PromoteIntBinOp. 2213 (N0.getOpcode() == ISD::ANY_EXTEND && 2214 (!LegalTypes || TLI.isTypeDesirableForOp(N->getOpcode(), Op0VT))) || 2215 (N0.getOpcode() == ISD::TRUNCATE && 2216 (!TLI.isZExtFree(VT, Op0VT) || 2217 !TLI.isTruncateFree(Op0VT, VT)) && 2218 TLI.isTypeLegal(Op0VT))) && 2219 !VT.isVector() && 2220 Op0VT == N1.getOperand(0).getValueType() && 2221 (!LegalOperations || TLI.isOperationLegal(N->getOpcode(), Op0VT))) { 2222 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(), 2223 N0.getOperand(0).getValueType(), 2224 N0.getOperand(0), N1.getOperand(0)); 2225 AddToWorkList(ORNode.getNode()); 2226 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, ORNode); 2227 } 2228 2229 // For each of OP in SHL/SRL/SRA/AND... 2230 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z) 2231 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z) 2232 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z) 2233 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL || 2234 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) && 2235 N0.getOperand(1) == N1.getOperand(1)) { 2236 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(), 2237 N0.getOperand(0).getValueType(), 2238 N0.getOperand(0), N1.getOperand(0)); 2239 AddToWorkList(ORNode.getNode()); 2240 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, 2241 ORNode, N0.getOperand(1)); 2242 } 2243 2244 return SDValue(); 2245} 2246 2247SDValue DAGCombiner::visitAND(SDNode *N) { 2248 SDValue N0 = N->getOperand(0); 2249 SDValue N1 = N->getOperand(1); 2250 SDValue LL, LR, RL, RR, CC0, CC1; 2251 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2252 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2253 EVT VT = N1.getValueType(); 2254 unsigned BitWidth = VT.getScalarType().getSizeInBits(); 2255 2256 // fold vector ops 2257 if (VT.isVector()) { 2258 SDValue FoldedVOp = SimplifyVBinOp(N); 2259 if (FoldedVOp.getNode()) return FoldedVOp; 2260 } 2261 2262 // fold (and x, undef) -> 0 2263 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 2264 return DAG.getConstant(0, VT); 2265 // fold (and c1, c2) -> c1&c2 2266 if (N0C && N1C) 2267 return DAG.FoldConstantArithmetic(ISD::AND, VT, N0C, N1C); 2268 // canonicalize constant to RHS 2269 if (N0C && !N1C) 2270 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N1, N0); 2271 // fold (and x, -1) -> x 2272 if (N1C && N1C->isAllOnesValue()) 2273 return N0; 2274 // if (and x, c) is known to be zero, return 0 2275 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0), 2276 APInt::getAllOnesValue(BitWidth))) 2277 return DAG.getConstant(0, VT); 2278 // reassociate and 2279 SDValue RAND = ReassociateOps(ISD::AND, N->getDebugLoc(), N0, N1); 2280 if (RAND.getNode() != 0) 2281 return RAND; 2282 // fold (and (or x, C), D) -> D if (C & D) == D 2283 if (N1C && N0.getOpcode() == ISD::OR) 2284 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 2285 if ((ORI->getAPIntValue() & N1C->getAPIntValue()) == N1C->getAPIntValue()) 2286 return N1; 2287 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits. 2288 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 2289 SDValue N0Op0 = N0.getOperand(0); 2290 APInt Mask = ~N1C->getAPIntValue(); 2291 Mask = Mask.trunc(N0Op0.getValueSizeInBits()); 2292 if (DAG.MaskedValueIsZero(N0Op0, Mask)) { 2293 SDValue Zext = DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), 2294 N0.getValueType(), N0Op0); 2295 2296 // Replace uses of the AND with uses of the Zero extend node. 2297 CombineTo(N, Zext); 2298 2299 // We actually want to replace all uses of the any_extend with the 2300 // zero_extend, to avoid duplicating things. This will later cause this 2301 // AND to be folded. 2302 CombineTo(N0.getNode(), Zext); 2303 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2304 } 2305 } 2306 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y)) 2307 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 2308 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 2309 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 2310 2311 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 2312 LL.getValueType().isInteger()) { 2313 // fold (and (seteq X, 0), (seteq Y, 0)) -> (seteq (or X, Y), 0) 2314 if (cast<ConstantSDNode>(LR)->isNullValue() && Op1 == ISD::SETEQ) { 2315 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(), 2316 LR.getValueType(), LL, RL); 2317 AddToWorkList(ORNode.getNode()); 2318 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 2319 } 2320 // fold (and (seteq X, -1), (seteq Y, -1)) -> (seteq (and X, Y), -1) 2321 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) { 2322 SDValue ANDNode = DAG.getNode(ISD::AND, N0.getDebugLoc(), 2323 LR.getValueType(), LL, RL); 2324 AddToWorkList(ANDNode.getNode()); 2325 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1); 2326 } 2327 // fold (and (setgt X, -1), (setgt Y, -1)) -> (setgt (or X, Y), -1) 2328 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) { 2329 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(), 2330 LR.getValueType(), LL, RL); 2331 AddToWorkList(ORNode.getNode()); 2332 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 2333 } 2334 } 2335 // canonicalize equivalent to ll == rl 2336 if (LL == RR && LR == RL) { 2337 Op1 = ISD::getSetCCSwappedOperands(Op1); 2338 std::swap(RL, RR); 2339 } 2340 if (LL == RL && LR == RR) { 2341 bool isInteger = LL.getValueType().isInteger(); 2342 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger); 2343 if (Result != ISD::SETCC_INVALID && 2344 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType()))) 2345 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(), 2346 LL, LR, Result); 2347 } 2348 } 2349 2350 // Simplify: (and (op x...), (op y...)) -> (op (and x, y)) 2351 if (N0.getOpcode() == N1.getOpcode()) { 2352 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 2353 if (Tmp.getNode()) return Tmp; 2354 } 2355 2356 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1) 2357 // fold (and (sra)) -> (and (srl)) when possible. 2358 if (!VT.isVector() && 2359 SimplifyDemandedBits(SDValue(N, 0))) 2360 return SDValue(N, 0); 2361 2362 // fold (zext_inreg (extload x)) -> (zextload x) 2363 if (ISD::isEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode())) { 2364 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2365 EVT MemVT = LN0->getMemoryVT(); 2366 // If we zero all the possible extended bits, then we can turn this into 2367 // a zextload if we are running before legalize or the operation is legal. 2368 unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits(); 2369 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 2370 BitWidth - MemVT.getScalarType().getSizeInBits())) && 2371 ((!LegalOperations && !LN0->isVolatile()) || 2372 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) { 2373 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT, 2374 LN0->getChain(), LN0->getBasePtr(), 2375 LN0->getPointerInfo(), MemVT, 2376 LN0->isVolatile(), LN0->isNonTemporal(), 2377 LN0->getAlignment()); 2378 AddToWorkList(N); 2379 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 2380 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2381 } 2382 } 2383 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use 2384 if (ISD::isSEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 2385 N0.hasOneUse()) { 2386 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2387 EVT MemVT = LN0->getMemoryVT(); 2388 // If we zero all the possible extended bits, then we can turn this into 2389 // a zextload if we are running before legalize or the operation is legal. 2390 unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits(); 2391 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 2392 BitWidth - MemVT.getScalarType().getSizeInBits())) && 2393 ((!LegalOperations && !LN0->isVolatile()) || 2394 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) { 2395 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT, 2396 LN0->getChain(), 2397 LN0->getBasePtr(), LN0->getPointerInfo(), 2398 MemVT, 2399 LN0->isVolatile(), LN0->isNonTemporal(), 2400 LN0->getAlignment()); 2401 AddToWorkList(N); 2402 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 2403 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2404 } 2405 } 2406 2407 // fold (and (load x), 255) -> (zextload x, i8) 2408 // fold (and (extload x, i16), 255) -> (zextload x, i8) 2409 // fold (and (any_ext (extload x, i16)), 255) -> (zextload x, i8) 2410 if (N1C && (N0.getOpcode() == ISD::LOAD || 2411 (N0.getOpcode() == ISD::ANY_EXTEND && 2412 N0.getOperand(0).getOpcode() == ISD::LOAD))) { 2413 bool HasAnyExt = N0.getOpcode() == ISD::ANY_EXTEND; 2414 LoadSDNode *LN0 = HasAnyExt 2415 ? cast<LoadSDNode>(N0.getOperand(0)) 2416 : cast<LoadSDNode>(N0); 2417 if (LN0->getExtensionType() != ISD::SEXTLOAD && 2418 LN0->isUnindexed() && N0.hasOneUse() && LN0->hasOneUse()) { 2419 uint32_t ActiveBits = N1C->getAPIntValue().getActiveBits(); 2420 if (ActiveBits > 0 && APIntOps::isMask(ActiveBits, N1C->getAPIntValue())){ 2421 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), ActiveBits); 2422 EVT LoadedVT = LN0->getMemoryVT(); 2423 2424 if (ExtVT == LoadedVT && 2425 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) { 2426 EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT; 2427 2428 SDValue NewLoad = 2429 DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), LoadResultTy, 2430 LN0->getChain(), LN0->getBasePtr(), 2431 LN0->getPointerInfo(), 2432 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(), 2433 LN0->getAlignment()); 2434 AddToWorkList(N); 2435 CombineTo(LN0, NewLoad, NewLoad.getValue(1)); 2436 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2437 } 2438 2439 // Do not change the width of a volatile load. 2440 // Do not generate loads of non-round integer types since these can 2441 // be expensive (and would be wrong if the type is not byte sized). 2442 if (!LN0->isVolatile() && LoadedVT.bitsGT(ExtVT) && ExtVT.isRound() && 2443 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) { 2444 EVT PtrType = LN0->getOperand(1).getValueType(); 2445 2446 unsigned Alignment = LN0->getAlignment(); 2447 SDValue NewPtr = LN0->getBasePtr(); 2448 2449 // For big endian targets, we need to add an offset to the pointer 2450 // to load the correct bytes. For little endian systems, we merely 2451 // need to read fewer bytes from the same pointer. 2452 if (TLI.isBigEndian()) { 2453 unsigned LVTStoreBytes = LoadedVT.getStoreSize(); 2454 unsigned EVTStoreBytes = ExtVT.getStoreSize(); 2455 unsigned PtrOff = LVTStoreBytes - EVTStoreBytes; 2456 NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(), PtrType, 2457 NewPtr, DAG.getConstant(PtrOff, PtrType)); 2458 Alignment = MinAlign(Alignment, PtrOff); 2459 } 2460 2461 AddToWorkList(NewPtr.getNode()); 2462 2463 EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT; 2464 SDValue Load = 2465 DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), LoadResultTy, 2466 LN0->getChain(), NewPtr, 2467 LN0->getPointerInfo(), 2468 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(), 2469 Alignment); 2470 AddToWorkList(N); 2471 CombineTo(LN0, Load, Load.getValue(1)); 2472 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2473 } 2474 } 2475 } 2476 } 2477 2478 return SDValue(); 2479} 2480 2481SDValue DAGCombiner::visitOR(SDNode *N) { 2482 SDValue N0 = N->getOperand(0); 2483 SDValue N1 = N->getOperand(1); 2484 SDValue LL, LR, RL, RR, CC0, CC1; 2485 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2486 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2487 EVT VT = N1.getValueType(); 2488 2489 // fold vector ops 2490 if (VT.isVector()) { 2491 SDValue FoldedVOp = SimplifyVBinOp(N); 2492 if (FoldedVOp.getNode()) return FoldedVOp; 2493 } 2494 2495 // fold (or x, undef) -> -1 2496 if (!LegalOperations && 2497 (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)) { 2498 EVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT; 2499 return DAG.getConstant(APInt::getAllOnesValue(EltVT.getSizeInBits()), VT); 2500 } 2501 // fold (or c1, c2) -> c1|c2 2502 if (N0C && N1C) 2503 return DAG.FoldConstantArithmetic(ISD::OR, VT, N0C, N1C); 2504 // canonicalize constant to RHS 2505 if (N0C && !N1C) 2506 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N1, N0); 2507 // fold (or x, 0) -> x 2508 if (N1C && N1C->isNullValue()) 2509 return N0; 2510 // fold (or x, -1) -> -1 2511 if (N1C && N1C->isAllOnesValue()) 2512 return N1; 2513 // fold (or x, c) -> c iff (x & ~c) == 0 2514 if (N1C && DAG.MaskedValueIsZero(N0, ~N1C->getAPIntValue())) 2515 return N1; 2516 // reassociate or 2517 SDValue ROR = ReassociateOps(ISD::OR, N->getDebugLoc(), N0, N1); 2518 if (ROR.getNode() != 0) 2519 return ROR; 2520 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2) 2521 // iff (c1 & c2) == 0. 2522 if (N1C && N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() && 2523 isa<ConstantSDNode>(N0.getOperand(1))) { 2524 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1)); 2525 if ((C1->getAPIntValue() & N1C->getAPIntValue()) != 0) 2526 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 2527 DAG.getNode(ISD::OR, N0.getDebugLoc(), VT, 2528 N0.getOperand(0), N1), 2529 DAG.FoldConstantArithmetic(ISD::OR, VT, N1C, C1)); 2530 } 2531 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y)) 2532 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 2533 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 2534 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 2535 2536 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 2537 LL.getValueType().isInteger()) { 2538 // fold (or (setne X, 0), (setne Y, 0)) -> (setne (or X, Y), 0) 2539 // fold (or (setlt X, 0), (setlt Y, 0)) -> (setne (or X, Y), 0) 2540 if (cast<ConstantSDNode>(LR)->isNullValue() && 2541 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) { 2542 SDValue ORNode = DAG.getNode(ISD::OR, LR.getDebugLoc(), 2543 LR.getValueType(), LL, RL); 2544 AddToWorkList(ORNode.getNode()); 2545 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 2546 } 2547 // fold (or (setne X, -1), (setne Y, -1)) -> (setne (and X, Y), -1) 2548 // fold (or (setgt X, -1), (setgt Y -1)) -> (setgt (and X, Y), -1) 2549 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && 2550 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) { 2551 SDValue ANDNode = DAG.getNode(ISD::AND, LR.getDebugLoc(), 2552 LR.getValueType(), LL, RL); 2553 AddToWorkList(ANDNode.getNode()); 2554 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1); 2555 } 2556 } 2557 // canonicalize equivalent to ll == rl 2558 if (LL == RR && LR == RL) { 2559 Op1 = ISD::getSetCCSwappedOperands(Op1); 2560 std::swap(RL, RR); 2561 } 2562 if (LL == RL && LR == RR) { 2563 bool isInteger = LL.getValueType().isInteger(); 2564 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger); 2565 if (Result != ISD::SETCC_INVALID && 2566 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType()))) 2567 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(), 2568 LL, LR, Result); 2569 } 2570 } 2571 2572 // Simplify: (or (op x...), (op y...)) -> (op (or x, y)) 2573 if (N0.getOpcode() == N1.getOpcode()) { 2574 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 2575 if (Tmp.getNode()) return Tmp; 2576 } 2577 2578 // (or (and X, C1), (and Y, C2)) -> (and (or X, Y), C3) if possible. 2579 if (N0.getOpcode() == ISD::AND && 2580 N1.getOpcode() == ISD::AND && 2581 N0.getOperand(1).getOpcode() == ISD::Constant && 2582 N1.getOperand(1).getOpcode() == ISD::Constant && 2583 // Don't increase # computations. 2584 (N0.getNode()->hasOneUse() || N1.getNode()->hasOneUse())) { 2585 // We can only do this xform if we know that bits from X that are set in C2 2586 // but not in C1 are already zero. Likewise for Y. 2587 const APInt &LHSMask = 2588 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 2589 const APInt &RHSMask = 2590 cast<ConstantSDNode>(N1.getOperand(1))->getAPIntValue(); 2591 2592 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) && 2593 DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) { 2594 SDValue X = DAG.getNode(ISD::OR, N0.getDebugLoc(), VT, 2595 N0.getOperand(0), N1.getOperand(0)); 2596 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, X, 2597 DAG.getConstant(LHSMask | RHSMask, VT)); 2598 } 2599 } 2600 2601 // See if this is some rotate idiom. 2602 if (SDNode *Rot = MatchRotate(N0, N1, N->getDebugLoc())) 2603 return SDValue(Rot, 0); 2604 2605 // Simplify the operands using demanded-bits information. 2606 if (!VT.isVector() && 2607 SimplifyDemandedBits(SDValue(N, 0))) 2608 return SDValue(N, 0); 2609 2610 return SDValue(); 2611} 2612 2613/// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present. 2614static bool MatchRotateHalf(SDValue Op, SDValue &Shift, SDValue &Mask) { 2615 if (Op.getOpcode() == ISD::AND) { 2616 if (isa<ConstantSDNode>(Op.getOperand(1))) { 2617 Mask = Op.getOperand(1); 2618 Op = Op.getOperand(0); 2619 } else { 2620 return false; 2621 } 2622 } 2623 2624 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) { 2625 Shift = Op; 2626 return true; 2627 } 2628 2629 return false; 2630} 2631 2632// MatchRotate - Handle an 'or' of two operands. If this is one of the many 2633// idioms for rotate, and if the target supports rotation instructions, generate 2634// a rot[lr]. 2635SDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL) { 2636 // Must be a legal type. Expanded 'n promoted things won't work with rotates. 2637 EVT VT = LHS.getValueType(); 2638 if (!TLI.isTypeLegal(VT)) return 0; 2639 2640 // The target must have at least one rotate flavor. 2641 bool HasROTL = TLI.isOperationLegalOrCustom(ISD::ROTL, VT); 2642 bool HasROTR = TLI.isOperationLegalOrCustom(ISD::ROTR, VT); 2643 if (!HasROTL && !HasROTR) return 0; 2644 2645 // Match "(X shl/srl V1) & V2" where V2 may not be present. 2646 SDValue LHSShift; // The shift. 2647 SDValue LHSMask; // AND value if any. 2648 if (!MatchRotateHalf(LHS, LHSShift, LHSMask)) 2649 return 0; // Not part of a rotate. 2650 2651 SDValue RHSShift; // The shift. 2652 SDValue RHSMask; // AND value if any. 2653 if (!MatchRotateHalf(RHS, RHSShift, RHSMask)) 2654 return 0; // Not part of a rotate. 2655 2656 if (LHSShift.getOperand(0) != RHSShift.getOperand(0)) 2657 return 0; // Not shifting the same value. 2658 2659 if (LHSShift.getOpcode() == RHSShift.getOpcode()) 2660 return 0; // Shifts must disagree. 2661 2662 // Canonicalize shl to left side in a shl/srl pair. 2663 if (RHSShift.getOpcode() == ISD::SHL) { 2664 std::swap(LHS, RHS); 2665 std::swap(LHSShift, RHSShift); 2666 std::swap(LHSMask , RHSMask ); 2667 } 2668 2669 unsigned OpSizeInBits = VT.getSizeInBits(); 2670 SDValue LHSShiftArg = LHSShift.getOperand(0); 2671 SDValue LHSShiftAmt = LHSShift.getOperand(1); 2672 SDValue RHSShiftAmt = RHSShift.getOperand(1); 2673 2674 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1) 2675 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2) 2676 if (LHSShiftAmt.getOpcode() == ISD::Constant && 2677 RHSShiftAmt.getOpcode() == ISD::Constant) { 2678 uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getZExtValue(); 2679 uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getZExtValue(); 2680 if ((LShVal + RShVal) != OpSizeInBits) 2681 return 0; 2682 2683 SDValue Rot; 2684 if (HasROTL) 2685 Rot = DAG.getNode(ISD::ROTL, DL, VT, LHSShiftArg, LHSShiftAmt); 2686 else 2687 Rot = DAG.getNode(ISD::ROTR, DL, VT, LHSShiftArg, RHSShiftAmt); 2688 2689 // If there is an AND of either shifted operand, apply it to the result. 2690 if (LHSMask.getNode() || RHSMask.getNode()) { 2691 APInt Mask = APInt::getAllOnesValue(OpSizeInBits); 2692 2693 if (LHSMask.getNode()) { 2694 APInt RHSBits = APInt::getLowBitsSet(OpSizeInBits, LShVal); 2695 Mask &= cast<ConstantSDNode>(LHSMask)->getAPIntValue() | RHSBits; 2696 } 2697 if (RHSMask.getNode()) { 2698 APInt LHSBits = APInt::getHighBitsSet(OpSizeInBits, RShVal); 2699 Mask &= cast<ConstantSDNode>(RHSMask)->getAPIntValue() | LHSBits; 2700 } 2701 2702 Rot = DAG.getNode(ISD::AND, DL, VT, Rot, DAG.getConstant(Mask, VT)); 2703 } 2704 2705 return Rot.getNode(); 2706 } 2707 2708 // If there is a mask here, and we have a variable shift, we can't be sure 2709 // that we're masking out the right stuff. 2710 if (LHSMask.getNode() || RHSMask.getNode()) 2711 return 0; 2712 2713 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y) 2714 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y)) 2715 if (RHSShiftAmt.getOpcode() == ISD::SUB && 2716 LHSShiftAmt == RHSShiftAmt.getOperand(1)) { 2717 if (ConstantSDNode *SUBC = 2718 dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) { 2719 if (SUBC->getAPIntValue() == OpSizeInBits) { 2720 if (HasROTL) 2721 return DAG.getNode(ISD::ROTL, DL, VT, 2722 LHSShiftArg, LHSShiftAmt).getNode(); 2723 else 2724 return DAG.getNode(ISD::ROTR, DL, VT, 2725 LHSShiftArg, RHSShiftAmt).getNode(); 2726 } 2727 } 2728 } 2729 2730 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y) 2731 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y)) 2732 if (LHSShiftAmt.getOpcode() == ISD::SUB && 2733 RHSShiftAmt == LHSShiftAmt.getOperand(1)) { 2734 if (ConstantSDNode *SUBC = 2735 dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) { 2736 if (SUBC->getAPIntValue() == OpSizeInBits) { 2737 if (HasROTR) 2738 return DAG.getNode(ISD::ROTR, DL, VT, 2739 LHSShiftArg, RHSShiftAmt).getNode(); 2740 else 2741 return DAG.getNode(ISD::ROTL, DL, VT, 2742 LHSShiftArg, LHSShiftAmt).getNode(); 2743 } 2744 } 2745 } 2746 2747 // Look for sign/zext/any-extended or truncate cases: 2748 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 2749 || LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 2750 || LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND 2751 || LHSShiftAmt.getOpcode() == ISD::TRUNCATE) && 2752 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 2753 || RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 2754 || RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND 2755 || RHSShiftAmt.getOpcode() == ISD::TRUNCATE)) { 2756 SDValue LExtOp0 = LHSShiftAmt.getOperand(0); 2757 SDValue RExtOp0 = RHSShiftAmt.getOperand(0); 2758 if (RExtOp0.getOpcode() == ISD::SUB && 2759 RExtOp0.getOperand(1) == LExtOp0) { 2760 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 2761 // (rotl x, y) 2762 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 2763 // (rotr x, (sub 32, y)) 2764 if (ConstantSDNode *SUBC = 2765 dyn_cast<ConstantSDNode>(RExtOp0.getOperand(0))) { 2766 if (SUBC->getAPIntValue() == OpSizeInBits) { 2767 return DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT, 2768 LHSShiftArg, 2769 HasROTL ? LHSShiftAmt : RHSShiftAmt).getNode(); 2770 } 2771 } 2772 } else if (LExtOp0.getOpcode() == ISD::SUB && 2773 RExtOp0 == LExtOp0.getOperand(1)) { 2774 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) -> 2775 // (rotr x, y) 2776 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) -> 2777 // (rotl x, (sub 32, y)) 2778 if (ConstantSDNode *SUBC = 2779 dyn_cast<ConstantSDNode>(LExtOp0.getOperand(0))) { 2780 if (SUBC->getAPIntValue() == OpSizeInBits) { 2781 return DAG.getNode(HasROTR ? ISD::ROTR : ISD::ROTL, DL, VT, 2782 LHSShiftArg, 2783 HasROTR ? RHSShiftAmt : LHSShiftAmt).getNode(); 2784 } 2785 } 2786 } 2787 } 2788 2789 return 0; 2790} 2791 2792SDValue DAGCombiner::visitXOR(SDNode *N) { 2793 SDValue N0 = N->getOperand(0); 2794 SDValue N1 = N->getOperand(1); 2795 SDValue LHS, RHS, CC; 2796 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2797 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2798 EVT VT = N0.getValueType(); 2799 2800 // fold vector ops 2801 if (VT.isVector()) { 2802 SDValue FoldedVOp = SimplifyVBinOp(N); 2803 if (FoldedVOp.getNode()) return FoldedVOp; 2804 } 2805 2806 // fold (xor undef, undef) -> 0. This is a common idiom (misuse). 2807 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF) 2808 return DAG.getConstant(0, VT); 2809 // fold (xor x, undef) -> undef 2810 if (N0.getOpcode() == ISD::UNDEF) 2811 return N0; 2812 if (N1.getOpcode() == ISD::UNDEF) 2813 return N1; 2814 // fold (xor c1, c2) -> c1^c2 2815 if (N0C && N1C) 2816 return DAG.FoldConstantArithmetic(ISD::XOR, VT, N0C, N1C); 2817 // canonicalize constant to RHS 2818 if (N0C && !N1C) 2819 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0); 2820 // fold (xor x, 0) -> x 2821 if (N1C && N1C->isNullValue()) 2822 return N0; 2823 // reassociate xor 2824 SDValue RXOR = ReassociateOps(ISD::XOR, N->getDebugLoc(), N0, N1); 2825 if (RXOR.getNode() != 0) 2826 return RXOR; 2827 2828 // fold !(x cc y) -> (x !cc y) 2829 if (N1C && N1C->getAPIntValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) { 2830 bool isInt = LHS.getValueType().isInteger(); 2831 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(), 2832 isInt); 2833 2834 if (!LegalOperations || TLI.isCondCodeLegal(NotCC, LHS.getValueType())) { 2835 switch (N0.getOpcode()) { 2836 default: 2837 llvm_unreachable("Unhandled SetCC Equivalent!"); 2838 case ISD::SETCC: 2839 return DAG.getSetCC(N->getDebugLoc(), VT, LHS, RHS, NotCC); 2840 case ISD::SELECT_CC: 2841 return DAG.getSelectCC(N->getDebugLoc(), LHS, RHS, N0.getOperand(2), 2842 N0.getOperand(3), NotCC); 2843 } 2844 } 2845 } 2846 2847 // fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y))) 2848 if (N1C && N1C->getAPIntValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND && 2849 N0.getNode()->hasOneUse() && 2850 isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){ 2851 SDValue V = N0.getOperand(0); 2852 V = DAG.getNode(ISD::XOR, N0.getDebugLoc(), V.getValueType(), V, 2853 DAG.getConstant(1, V.getValueType())); 2854 AddToWorkList(V.getNode()); 2855 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, V); 2856 } 2857 2858 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are setcc 2859 if (N1C && N1C->getAPIntValue() == 1 && VT == MVT::i1 && 2860 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 2861 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1); 2862 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) { 2863 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 2864 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS 2865 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS 2866 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode()); 2867 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS); 2868 } 2869 } 2870 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are constants 2871 if (N1C && N1C->isAllOnesValue() && 2872 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 2873 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1); 2874 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) { 2875 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 2876 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS 2877 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS 2878 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode()); 2879 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS); 2880 } 2881 } 2882 // fold (xor (xor x, c1), c2) -> (xor x, (xor c1, c2)) 2883 if (N1C && N0.getOpcode() == ISD::XOR) { 2884 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0)); 2885 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2886 if (N00C) 2887 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(1), 2888 DAG.getConstant(N1C->getAPIntValue() ^ 2889 N00C->getAPIntValue(), VT)); 2890 if (N01C) 2891 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(0), 2892 DAG.getConstant(N1C->getAPIntValue() ^ 2893 N01C->getAPIntValue(), VT)); 2894 } 2895 // fold (xor x, x) -> 0 2896 if (N0 == N1) 2897 return tryFoldToZero(N->getDebugLoc(), TLI, VT, DAG, LegalOperations); 2898 2899 // Simplify: xor (op x...), (op y...) -> (op (xor x, y)) 2900 if (N0.getOpcode() == N1.getOpcode()) { 2901 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 2902 if (Tmp.getNode()) return Tmp; 2903 } 2904 2905 // Simplify the expression using non-local knowledge. 2906 if (!VT.isVector() && 2907 SimplifyDemandedBits(SDValue(N, 0))) 2908 return SDValue(N, 0); 2909 2910 return SDValue(); 2911} 2912 2913/// visitShiftByConstant - Handle transforms common to the three shifts, when 2914/// the shift amount is a constant. 2915SDValue DAGCombiner::visitShiftByConstant(SDNode *N, unsigned Amt) { 2916 SDNode *LHS = N->getOperand(0).getNode(); 2917 if (!LHS->hasOneUse()) return SDValue(); 2918 2919 // We want to pull some binops through shifts, so that we have (and (shift)) 2920 // instead of (shift (and)), likewise for add, or, xor, etc. This sort of 2921 // thing happens with address calculations, so it's important to canonicalize 2922 // it. 2923 bool HighBitSet = false; // Can we transform this if the high bit is set? 2924 2925 switch (LHS->getOpcode()) { 2926 default: return SDValue(); 2927 case ISD::OR: 2928 case ISD::XOR: 2929 HighBitSet = false; // We can only transform sra if the high bit is clear. 2930 break; 2931 case ISD::AND: 2932 HighBitSet = true; // We can only transform sra if the high bit is set. 2933 break; 2934 case ISD::ADD: 2935 if (N->getOpcode() != ISD::SHL) 2936 return SDValue(); // only shl(add) not sr[al](add). 2937 HighBitSet = false; // We can only transform sra if the high bit is clear. 2938 break; 2939 } 2940 2941 // We require the RHS of the binop to be a constant as well. 2942 ConstantSDNode *BinOpCst = dyn_cast<ConstantSDNode>(LHS->getOperand(1)); 2943 if (!BinOpCst) return SDValue(); 2944 2945 // FIXME: disable this unless the input to the binop is a shift by a constant. 2946 // If it is not a shift, it pessimizes some common cases like: 2947 // 2948 // void foo(int *X, int i) { X[i & 1235] = 1; } 2949 // int bar(int *X, int i) { return X[i & 255]; } 2950 SDNode *BinOpLHSVal = LHS->getOperand(0).getNode(); 2951 if ((BinOpLHSVal->getOpcode() != ISD::SHL && 2952 BinOpLHSVal->getOpcode() != ISD::SRA && 2953 BinOpLHSVal->getOpcode() != ISD::SRL) || 2954 !isa<ConstantSDNode>(BinOpLHSVal->getOperand(1))) 2955 return SDValue(); 2956 2957 EVT VT = N->getValueType(0); 2958 2959 // If this is a signed shift right, and the high bit is modified by the 2960 // logical operation, do not perform the transformation. The highBitSet 2961 // boolean indicates the value of the high bit of the constant which would 2962 // cause it to be modified for this operation. 2963 if (N->getOpcode() == ISD::SRA) { 2964 bool BinOpRHSSignSet = BinOpCst->getAPIntValue().isNegative(); 2965 if (BinOpRHSSignSet != HighBitSet) 2966 return SDValue(); 2967 } 2968 2969 // Fold the constants, shifting the binop RHS by the shift amount. 2970 SDValue NewRHS = DAG.getNode(N->getOpcode(), LHS->getOperand(1).getDebugLoc(), 2971 N->getValueType(0), 2972 LHS->getOperand(1), N->getOperand(1)); 2973 2974 // Create the new shift. 2975 SDValue NewShift = DAG.getNode(N->getOpcode(), 2976 LHS->getOperand(0).getDebugLoc(), 2977 VT, LHS->getOperand(0), N->getOperand(1)); 2978 2979 // Create the new binop. 2980 return DAG.getNode(LHS->getOpcode(), N->getDebugLoc(), VT, NewShift, NewRHS); 2981} 2982 2983SDValue DAGCombiner::visitSHL(SDNode *N) { 2984 SDValue N0 = N->getOperand(0); 2985 SDValue N1 = N->getOperand(1); 2986 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2987 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2988 EVT VT = N0.getValueType(); 2989 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits(); 2990 2991 // fold (shl c1, c2) -> c1<<c2 2992 if (N0C && N1C) 2993 return DAG.FoldConstantArithmetic(ISD::SHL, VT, N0C, N1C); 2994 // fold (shl 0, x) -> 0 2995 if (N0C && N0C->isNullValue()) 2996 return N0; 2997 // fold (shl x, c >= size(x)) -> undef 2998 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 2999 return DAG.getUNDEF(VT); 3000 // fold (shl x, 0) -> x 3001 if (N1C && N1C->isNullValue()) 3002 return N0; 3003 // if (shl x, c) is known to be zero, return 0 3004 if (DAG.MaskedValueIsZero(SDValue(N, 0), 3005 APInt::getAllOnesValue(OpSizeInBits))) 3006 return DAG.getConstant(0, VT); 3007 // fold (shl x, (trunc (and y, c))) -> (shl x, (and (trunc y), (trunc c))). 3008 if (N1.getOpcode() == ISD::TRUNCATE && 3009 N1.getOperand(0).getOpcode() == ISD::AND && 3010 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 3011 SDValue N101 = N1.getOperand(0).getOperand(1); 3012 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 3013 EVT TruncVT = N1.getValueType(); 3014 SDValue N100 = N1.getOperand(0).getOperand(0); 3015 APInt TruncC = N101C->getAPIntValue(); 3016 TruncC = TruncC.trunc(TruncVT.getSizeInBits()); 3017 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 3018 DAG.getNode(ISD::AND, N->getDebugLoc(), TruncVT, 3019 DAG.getNode(ISD::TRUNCATE, 3020 N->getDebugLoc(), 3021 TruncVT, N100), 3022 DAG.getConstant(TruncC, TruncVT))); 3023 } 3024 } 3025 3026 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 3027 return SDValue(N, 0); 3028 3029 // fold (shl (shl x, c1), c2) -> 0 or (shl x, (add c1, c2)) 3030 if (N1C && N0.getOpcode() == ISD::SHL && 3031 N0.getOperand(1).getOpcode() == ISD::Constant) { 3032 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 3033 uint64_t c2 = N1C->getZExtValue(); 3034 if (c1 + c2 >= OpSizeInBits) 3035 return DAG.getConstant(0, VT); 3036 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0.getOperand(0), 3037 DAG.getConstant(c1 + c2, N1.getValueType())); 3038 } 3039 3040 // fold (shl (ext (shl x, c1)), c2) -> (ext (shl x, (add c1, c2))) 3041 // For this to be valid, the second form must not preserve any of the bits 3042 // that are shifted out by the inner shift in the first form. This means 3043 // the outer shift size must be >= the number of bits added by the ext. 3044 // As a corollary, we don't care what kind of ext it is. 3045 if (N1C && (N0.getOpcode() == ISD::ZERO_EXTEND || 3046 N0.getOpcode() == ISD::ANY_EXTEND || 3047 N0.getOpcode() == ISD::SIGN_EXTEND) && 3048 N0.getOperand(0).getOpcode() == ISD::SHL && 3049 isa<ConstantSDNode>(N0.getOperand(0)->getOperand(1))) { 3050 uint64_t c1 = 3051 cast<ConstantSDNode>(N0.getOperand(0)->getOperand(1))->getZExtValue(); 3052 uint64_t c2 = N1C->getZExtValue(); 3053 EVT InnerShiftVT = N0.getOperand(0).getValueType(); 3054 uint64_t InnerShiftSize = InnerShiftVT.getScalarType().getSizeInBits(); 3055 if (c2 >= OpSizeInBits - InnerShiftSize) { 3056 if (c1 + c2 >= OpSizeInBits) 3057 return DAG.getConstant(0, VT); 3058 return DAG.getNode(ISD::SHL, N0->getDebugLoc(), VT, 3059 DAG.getNode(N0.getOpcode(), N0->getDebugLoc(), VT, 3060 N0.getOperand(0)->getOperand(0)), 3061 DAG.getConstant(c1 + c2, N1.getValueType())); 3062 } 3063 } 3064 3065 // fold (shl (srl x, c1), c2) -> (shl (and x, (shl -1, c1)), (sub c2, c1)) or 3066 // (srl (and x, (shl -1, c1)), (sub c1, c2)) 3067 if (N1C && N0.getOpcode() == ISD::SRL && 3068 N0.getOperand(1).getOpcode() == ISD::Constant) { 3069 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 3070 if (c1 < VT.getSizeInBits()) { 3071 uint64_t c2 = N1C->getZExtValue(); 3072 SDValue HiBitsMask = 3073 DAG.getConstant(APInt::getHighBitsSet(VT.getSizeInBits(), 3074 VT.getSizeInBits() - c1), 3075 VT); 3076 SDValue Mask = DAG.getNode(ISD::AND, N0.getDebugLoc(), VT, 3077 N0.getOperand(0), 3078 HiBitsMask); 3079 if (c2 > c1) 3080 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, Mask, 3081 DAG.getConstant(c2-c1, N1.getValueType())); 3082 else 3083 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, Mask, 3084 DAG.getConstant(c1-c2, N1.getValueType())); 3085 } 3086 } 3087 // fold (shl (sra x, c1), c1) -> (and x, (shl -1, c1)) 3088 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) { 3089 SDValue HiBitsMask = 3090 DAG.getConstant(APInt::getHighBitsSet(VT.getSizeInBits(), 3091 VT.getSizeInBits() - 3092 N1C->getZExtValue()), 3093 VT); 3094 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0), 3095 HiBitsMask); 3096 } 3097 3098 if (N1C) { 3099 SDValue NewSHL = visitShiftByConstant(N, N1C->getZExtValue()); 3100 if (NewSHL.getNode()) 3101 return NewSHL; 3102 } 3103 3104 return SDValue(); 3105} 3106 3107SDValue DAGCombiner::visitSRA(SDNode *N) { 3108 SDValue N0 = N->getOperand(0); 3109 SDValue N1 = N->getOperand(1); 3110 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3111 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3112 EVT VT = N0.getValueType(); 3113 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits(); 3114 3115 // fold (sra c1, c2) -> (sra c1, c2) 3116 if (N0C && N1C) 3117 return DAG.FoldConstantArithmetic(ISD::SRA, VT, N0C, N1C); 3118 // fold (sra 0, x) -> 0 3119 if (N0C && N0C->isNullValue()) 3120 return N0; 3121 // fold (sra -1, x) -> -1 3122 if (N0C && N0C->isAllOnesValue()) 3123 return N0; 3124 // fold (sra x, (setge c, size(x))) -> undef 3125 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 3126 return DAG.getUNDEF(VT); 3127 // fold (sra x, 0) -> x 3128 if (N1C && N1C->isNullValue()) 3129 return N0; 3130 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports 3131 // sext_inreg. 3132 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) { 3133 unsigned LowBits = OpSizeInBits - (unsigned)N1C->getZExtValue(); 3134 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), LowBits); 3135 if (VT.isVector()) 3136 ExtVT = EVT::getVectorVT(*DAG.getContext(), 3137 ExtVT, VT.getVectorNumElements()); 3138 if ((!LegalOperations || 3139 TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, ExtVT))) 3140 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, 3141 N0.getOperand(0), DAG.getValueType(ExtVT)); 3142 } 3143 3144 // fold (sra (sra x, c1), c2) -> (sra x, (add c1, c2)) 3145 if (N1C && N0.getOpcode() == ISD::SRA) { 3146 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 3147 unsigned Sum = N1C->getZExtValue() + C1->getZExtValue(); 3148 if (Sum >= OpSizeInBits) Sum = OpSizeInBits-1; 3149 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0.getOperand(0), 3150 DAG.getConstant(Sum, N1C->getValueType(0))); 3151 } 3152 } 3153 3154 // fold (sra (shl X, m), (sub result_size, n)) 3155 // -> (sign_extend (trunc (shl X, (sub (sub result_size, n), m)))) for 3156 // result_size - n != m. 3157 // If truncate is free for the target sext(shl) is likely to result in better 3158 // code. 3159 if (N0.getOpcode() == ISD::SHL) { 3160 // Get the two constanst of the shifts, CN0 = m, CN = n. 3161 const ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 3162 if (N01C && N1C) { 3163 // Determine what the truncate's result bitsize and type would be. 3164 EVT TruncVT = 3165 EVT::getIntegerVT(*DAG.getContext(), 3166 OpSizeInBits - N1C->getZExtValue()); 3167 // Determine the residual right-shift amount. 3168 signed ShiftAmt = N1C->getZExtValue() - N01C->getZExtValue(); 3169 3170 // If the shift is not a no-op (in which case this should be just a sign 3171 // extend already), the truncated to type is legal, sign_extend is legal 3172 // on that type, and the truncate to that type is both legal and free, 3173 // perform the transform. 3174 if ((ShiftAmt > 0) && 3175 TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND, TruncVT) && 3176 TLI.isOperationLegalOrCustom(ISD::TRUNCATE, VT) && 3177 TLI.isTruncateFree(VT, TruncVT)) { 3178 3179 SDValue Amt = DAG.getConstant(ShiftAmt, 3180 getShiftAmountTy(N0.getOperand(0).getValueType())); 3181 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, 3182 N0.getOperand(0), Amt); 3183 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), TruncVT, 3184 Shift); 3185 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), 3186 N->getValueType(0), Trunc); 3187 } 3188 } 3189 } 3190 3191 // fold (sra x, (trunc (and y, c))) -> (sra x, (and (trunc y), (trunc c))). 3192 if (N1.getOpcode() == ISD::TRUNCATE && 3193 N1.getOperand(0).getOpcode() == ISD::AND && 3194 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 3195 SDValue N101 = N1.getOperand(0).getOperand(1); 3196 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 3197 EVT TruncVT = N1.getValueType(); 3198 SDValue N100 = N1.getOperand(0).getOperand(0); 3199 APInt TruncC = N101C->getAPIntValue(); 3200 TruncC = TruncC.trunc(TruncVT.getScalarType().getSizeInBits()); 3201 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0, 3202 DAG.getNode(ISD::AND, N->getDebugLoc(), 3203 TruncVT, 3204 DAG.getNode(ISD::TRUNCATE, 3205 N->getDebugLoc(), 3206 TruncVT, N100), 3207 DAG.getConstant(TruncC, TruncVT))); 3208 } 3209 } 3210 3211 // fold (sra (trunc (sr x, c1)), c2) -> (trunc (sra x, c1+c2)) 3212 // if c1 is equal to the number of bits the trunc removes 3213 if (N0.getOpcode() == ISD::TRUNCATE && 3214 (N0.getOperand(0).getOpcode() == ISD::SRL || 3215 N0.getOperand(0).getOpcode() == ISD::SRA) && 3216 N0.getOperand(0).hasOneUse() && 3217 N0.getOperand(0).getOperand(1).hasOneUse() && 3218 N1C && isa<ConstantSDNode>(N0.getOperand(0).getOperand(1))) { 3219 EVT LargeVT = N0.getOperand(0).getValueType(); 3220 ConstantSDNode *LargeShiftAmt = 3221 cast<ConstantSDNode>(N0.getOperand(0).getOperand(1)); 3222 3223 if (LargeVT.getScalarType().getSizeInBits() - OpSizeInBits == 3224 LargeShiftAmt->getZExtValue()) { 3225 SDValue Amt = 3226 DAG.getConstant(LargeShiftAmt->getZExtValue() + N1C->getZExtValue(), 3227 getShiftAmountTy(N0.getOperand(0).getOperand(0).getValueType())); 3228 SDValue SRA = DAG.getNode(ISD::SRA, N->getDebugLoc(), LargeVT, 3229 N0.getOperand(0).getOperand(0), Amt); 3230 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, SRA); 3231 } 3232 } 3233 3234 // Simplify, based on bits shifted out of the LHS. 3235 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 3236 return SDValue(N, 0); 3237 3238 3239 // If the sign bit is known to be zero, switch this to a SRL. 3240 if (DAG.SignBitIsZero(N0)) 3241 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, N1); 3242 3243 if (N1C) { 3244 SDValue NewSRA = visitShiftByConstant(N, N1C->getZExtValue()); 3245 if (NewSRA.getNode()) 3246 return NewSRA; 3247 } 3248 3249 return SDValue(); 3250} 3251 3252SDValue DAGCombiner::visitSRL(SDNode *N) { 3253 SDValue N0 = N->getOperand(0); 3254 SDValue N1 = N->getOperand(1); 3255 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3256 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3257 EVT VT = N0.getValueType(); 3258 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits(); 3259 3260 // fold (srl c1, c2) -> c1 >>u c2 3261 if (N0C && N1C) 3262 return DAG.FoldConstantArithmetic(ISD::SRL, VT, N0C, N1C); 3263 // fold (srl 0, x) -> 0 3264 if (N0C && N0C->isNullValue()) 3265 return N0; 3266 // fold (srl x, c >= size(x)) -> undef 3267 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 3268 return DAG.getUNDEF(VT); 3269 // fold (srl x, 0) -> x 3270 if (N1C && N1C->isNullValue()) 3271 return N0; 3272 // if (srl x, c) is known to be zero, return 0 3273 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0), 3274 APInt::getAllOnesValue(OpSizeInBits))) 3275 return DAG.getConstant(0, VT); 3276 3277 // fold (srl (srl x, c1), c2) -> 0 or (srl x, (add c1, c2)) 3278 if (N1C && N0.getOpcode() == ISD::SRL && 3279 N0.getOperand(1).getOpcode() == ISD::Constant) { 3280 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 3281 uint64_t c2 = N1C->getZExtValue(); 3282 if (c1 + c2 >= OpSizeInBits) 3283 return DAG.getConstant(0, VT); 3284 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), 3285 DAG.getConstant(c1 + c2, N1.getValueType())); 3286 } 3287 3288 // fold (srl (trunc (srl x, c1)), c2) -> 0 or (trunc (srl x, (add c1, c2))) 3289 if (N1C && N0.getOpcode() == ISD::TRUNCATE && 3290 N0.getOperand(0).getOpcode() == ISD::SRL && 3291 isa<ConstantSDNode>(N0.getOperand(0)->getOperand(1))) { 3292 uint64_t c1 = 3293 cast<ConstantSDNode>(N0.getOperand(0)->getOperand(1))->getZExtValue(); 3294 uint64_t c2 = N1C->getZExtValue(); 3295 EVT InnerShiftVT = N0.getOperand(0).getValueType(); 3296 EVT ShiftCountVT = N0.getOperand(0)->getOperand(1).getValueType(); 3297 uint64_t InnerShiftSize = InnerShiftVT.getScalarType().getSizeInBits(); 3298 // This is only valid if the OpSizeInBits + c1 = size of inner shift. 3299 if (c1 + OpSizeInBits == InnerShiftSize) { 3300 if (c1 + c2 >= InnerShiftSize) 3301 return DAG.getConstant(0, VT); 3302 return DAG.getNode(ISD::TRUNCATE, N0->getDebugLoc(), VT, 3303 DAG.getNode(ISD::SRL, N0->getDebugLoc(), InnerShiftVT, 3304 N0.getOperand(0)->getOperand(0), 3305 DAG.getConstant(c1 + c2, ShiftCountVT))); 3306 } 3307 } 3308 3309 // fold (srl (shl x, c), c) -> (and x, cst2) 3310 if (N1C && N0.getOpcode() == ISD::SHL && N0.getOperand(1) == N1 && 3311 N0.getValueSizeInBits() <= 64) { 3312 uint64_t ShAmt = N1C->getZExtValue()+64-N0.getValueSizeInBits(); 3313 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0), 3314 DAG.getConstant(~0ULL >> ShAmt, VT)); 3315 } 3316 3317 3318 // fold (srl (anyextend x), c) -> (anyextend (srl x, c)) 3319 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 3320 // Shifting in all undef bits? 3321 EVT SmallVT = N0.getOperand(0).getValueType(); 3322 if (N1C->getZExtValue() >= SmallVT.getSizeInBits()) 3323 return DAG.getUNDEF(VT); 3324 3325 if (!LegalTypes || TLI.isTypeDesirableForOp(ISD::SRL, SmallVT)) { 3326 SDValue SmallShift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), SmallVT, 3327 N0.getOperand(0), N1); 3328 AddToWorkList(SmallShift.getNode()); 3329 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, SmallShift); 3330 } 3331 } 3332 3333 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign 3334 // bit, which is unmodified by sra. 3335 if (N1C && N1C->getZExtValue() + 1 == VT.getSizeInBits()) { 3336 if (N0.getOpcode() == ISD::SRA) 3337 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), N1); 3338 } 3339 3340 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit). 3341 if (N1C && N0.getOpcode() == ISD::CTLZ && 3342 N1C->getAPIntValue() == Log2_32(VT.getSizeInBits())) { 3343 APInt KnownZero, KnownOne; 3344 APInt Mask = APInt::getAllOnesValue(VT.getScalarType().getSizeInBits()); 3345 DAG.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne); 3346 3347 // If any of the input bits are KnownOne, then the input couldn't be all 3348 // zeros, thus the result of the srl will always be zero. 3349 if (KnownOne.getBoolValue()) return DAG.getConstant(0, VT); 3350 3351 // If all of the bits input the to ctlz node are known to be zero, then 3352 // the result of the ctlz is "32" and the result of the shift is one. 3353 APInt UnknownBits = ~KnownZero & Mask; 3354 if (UnknownBits == 0) return DAG.getConstant(1, VT); 3355 3356 // Otherwise, check to see if there is exactly one bit input to the ctlz. 3357 if ((UnknownBits & (UnknownBits - 1)) == 0) { 3358 // Okay, we know that only that the single bit specified by UnknownBits 3359 // could be set on input to the CTLZ node. If this bit is set, the SRL 3360 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair 3361 // to an SRL/XOR pair, which is likely to simplify more. 3362 unsigned ShAmt = UnknownBits.countTrailingZeros(); 3363 SDValue Op = N0.getOperand(0); 3364 3365 if (ShAmt) { 3366 Op = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, Op, 3367 DAG.getConstant(ShAmt, getShiftAmountTy(Op.getValueType()))); 3368 AddToWorkList(Op.getNode()); 3369 } 3370 3371 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, 3372 Op, DAG.getConstant(1, VT)); 3373 } 3374 } 3375 3376 // fold (srl x, (trunc (and y, c))) -> (srl x, (and (trunc y), (trunc c))). 3377 if (N1.getOpcode() == ISD::TRUNCATE && 3378 N1.getOperand(0).getOpcode() == ISD::AND && 3379 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 3380 SDValue N101 = N1.getOperand(0).getOperand(1); 3381 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 3382 EVT TruncVT = N1.getValueType(); 3383 SDValue N100 = N1.getOperand(0).getOperand(0); 3384 APInt TruncC = N101C->getAPIntValue(); 3385 TruncC = TruncC.trunc(TruncVT.getSizeInBits()); 3386 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, 3387 DAG.getNode(ISD::AND, N->getDebugLoc(), 3388 TruncVT, 3389 DAG.getNode(ISD::TRUNCATE, 3390 N->getDebugLoc(), 3391 TruncVT, N100), 3392 DAG.getConstant(TruncC, TruncVT))); 3393 } 3394 } 3395 3396 // fold operands of srl based on knowledge that the low bits are not 3397 // demanded. 3398 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 3399 return SDValue(N, 0); 3400 3401 if (N1C) { 3402 SDValue NewSRL = visitShiftByConstant(N, N1C->getZExtValue()); 3403 if (NewSRL.getNode()) 3404 return NewSRL; 3405 } 3406 3407 // Attempt to convert a srl of a load into a narrower zero-extending load. 3408 SDValue NarrowLoad = ReduceLoadWidth(N); 3409 if (NarrowLoad.getNode()) 3410 return NarrowLoad; 3411 3412 // Here is a common situation. We want to optimize: 3413 // 3414 // %a = ... 3415 // %b = and i32 %a, 2 3416 // %c = srl i32 %b, 1 3417 // brcond i32 %c ... 3418 // 3419 // into 3420 // 3421 // %a = ... 3422 // %b = and %a, 2 3423 // %c = setcc eq %b, 0 3424 // brcond %c ... 3425 // 3426 // However when after the source operand of SRL is optimized into AND, the SRL 3427 // itself may not be optimized further. Look for it and add the BRCOND into 3428 // the worklist. 3429 if (N->hasOneUse()) { 3430 SDNode *Use = *N->use_begin(); 3431 if (Use->getOpcode() == ISD::BRCOND) 3432 AddToWorkList(Use); 3433 else if (Use->getOpcode() == ISD::TRUNCATE && Use->hasOneUse()) { 3434 // Also look pass the truncate. 3435 Use = *Use->use_begin(); 3436 if (Use->getOpcode() == ISD::BRCOND) 3437 AddToWorkList(Use); 3438 } 3439 } 3440 3441 return SDValue(); 3442} 3443 3444SDValue DAGCombiner::visitCTLZ(SDNode *N) { 3445 SDValue N0 = N->getOperand(0); 3446 EVT VT = N->getValueType(0); 3447 3448 // fold (ctlz c1) -> c2 3449 if (isa<ConstantSDNode>(N0)) 3450 return DAG.getNode(ISD::CTLZ, N->getDebugLoc(), VT, N0); 3451 return SDValue(); 3452} 3453 3454SDValue DAGCombiner::visitCTTZ(SDNode *N) { 3455 SDValue N0 = N->getOperand(0); 3456 EVT VT = N->getValueType(0); 3457 3458 // fold (cttz c1) -> c2 3459 if (isa<ConstantSDNode>(N0)) 3460 return DAG.getNode(ISD::CTTZ, N->getDebugLoc(), VT, N0); 3461 return SDValue(); 3462} 3463 3464SDValue DAGCombiner::visitCTPOP(SDNode *N) { 3465 SDValue N0 = N->getOperand(0); 3466 EVT VT = N->getValueType(0); 3467 3468 // fold (ctpop c1) -> c2 3469 if (isa<ConstantSDNode>(N0)) 3470 return DAG.getNode(ISD::CTPOP, N->getDebugLoc(), VT, N0); 3471 return SDValue(); 3472} 3473 3474SDValue DAGCombiner::visitSELECT(SDNode *N) { 3475 SDValue N0 = N->getOperand(0); 3476 SDValue N1 = N->getOperand(1); 3477 SDValue N2 = N->getOperand(2); 3478 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3479 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3480 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2); 3481 EVT VT = N->getValueType(0); 3482 EVT VT0 = N0.getValueType(); 3483 3484 // fold (select C, X, X) -> X 3485 if (N1 == N2) 3486 return N1; 3487 // fold (select true, X, Y) -> X 3488 if (N0C && !N0C->isNullValue()) 3489 return N1; 3490 // fold (select false, X, Y) -> Y 3491 if (N0C && N0C->isNullValue()) 3492 return N2; 3493 // fold (select C, 1, X) -> (or C, X) 3494 if (VT == MVT::i1 && N1C && N1C->getAPIntValue() == 1) 3495 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2); 3496 // fold (select C, 0, 1) -> (xor C, 1) 3497 if (VT.isInteger() && 3498 (VT0 == MVT::i1 || 3499 (VT0.isInteger() && 3500 TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent)) && 3501 N1C && N2C && N1C->isNullValue() && N2C->getAPIntValue() == 1) { 3502 SDValue XORNode; 3503 if (VT == VT0) 3504 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT0, 3505 N0, DAG.getConstant(1, VT0)); 3506 XORNode = DAG.getNode(ISD::XOR, N0.getDebugLoc(), VT0, 3507 N0, DAG.getConstant(1, VT0)); 3508 AddToWorkList(XORNode.getNode()); 3509 if (VT.bitsGT(VT0)) 3510 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, XORNode); 3511 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, XORNode); 3512 } 3513 // fold (select C, 0, X) -> (and (not C), X) 3514 if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) { 3515 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT); 3516 AddToWorkList(NOTNode.getNode()); 3517 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, NOTNode, N2); 3518 } 3519 // fold (select C, X, 1) -> (or (not C), X) 3520 if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getAPIntValue() == 1) { 3521 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT); 3522 AddToWorkList(NOTNode.getNode()); 3523 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, NOTNode, N1); 3524 } 3525 // fold (select C, X, 0) -> (and C, X) 3526 if (VT == MVT::i1 && N2C && N2C->isNullValue()) 3527 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1); 3528 // fold (select X, X, Y) -> (or X, Y) 3529 // fold (select X, 1, Y) -> (or X, Y) 3530 if (VT == MVT::i1 && (N0 == N1 || (N1C && N1C->getAPIntValue() == 1))) 3531 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2); 3532 // fold (select X, Y, X) -> (and X, Y) 3533 // fold (select X, Y, 0) -> (and X, Y) 3534 if (VT == MVT::i1 && (N0 == N2 || (N2C && N2C->getAPIntValue() == 0))) 3535 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1); 3536 3537 // If we can fold this based on the true/false value, do so. 3538 if (SimplifySelectOps(N, N1, N2)) 3539 return SDValue(N, 0); // Don't revisit N. 3540 3541 // fold selects based on a setcc into other things, such as min/max/abs 3542 if (N0.getOpcode() == ISD::SETCC) { 3543 // FIXME: 3544 // Check against MVT::Other for SELECT_CC, which is a workaround for targets 3545 // having to say they don't support SELECT_CC on every type the DAG knows 3546 // about, since there is no way to mark an opcode illegal at all value types 3547 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other) && 3548 TLI.isOperationLegalOrCustom(ISD::SELECT_CC, VT)) 3549 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT, 3550 N0.getOperand(0), N0.getOperand(1), 3551 N1, N2, N0.getOperand(2)); 3552 return SimplifySelect(N->getDebugLoc(), N0, N1, N2); 3553 } 3554 3555 return SDValue(); 3556} 3557 3558SDValue DAGCombiner::visitSELECT_CC(SDNode *N) { 3559 SDValue N0 = N->getOperand(0); 3560 SDValue N1 = N->getOperand(1); 3561 SDValue N2 = N->getOperand(2); 3562 SDValue N3 = N->getOperand(3); 3563 SDValue N4 = N->getOperand(4); 3564 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get(); 3565 3566 // fold select_cc lhs, rhs, x, x, cc -> x 3567 if (N2 == N3) 3568 return N2; 3569 3570 // Determine if the condition we're dealing with is constant 3571 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()), 3572 N0, N1, CC, N->getDebugLoc(), false); 3573 if (SCC.getNode()) AddToWorkList(SCC.getNode()); 3574 3575 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode())) { 3576 if (!SCCC->isNullValue()) 3577 return N2; // cond always true -> true val 3578 else 3579 return N3; // cond always false -> false val 3580 } 3581 3582 // Fold to a simpler select_cc 3583 if (SCC.getNode() && SCC.getOpcode() == ISD::SETCC) 3584 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), N2.getValueType(), 3585 SCC.getOperand(0), SCC.getOperand(1), N2, N3, 3586 SCC.getOperand(2)); 3587 3588 // If we can fold this based on the true/false value, do so. 3589 if (SimplifySelectOps(N, N2, N3)) 3590 return SDValue(N, 0); // Don't revisit N. 3591 3592 // fold select_cc into other things, such as min/max/abs 3593 return SimplifySelectCC(N->getDebugLoc(), N0, N1, N2, N3, CC); 3594} 3595 3596SDValue DAGCombiner::visitSETCC(SDNode *N) { 3597 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1), 3598 cast<CondCodeSDNode>(N->getOperand(2))->get(), 3599 N->getDebugLoc()); 3600} 3601 3602// ExtendUsesToFormExtLoad - Trying to extend uses of a load to enable this: 3603// "fold ({s|z|a}ext (load x)) -> ({s|z|a}ext (truncate ({s|z|a}extload x)))" 3604// transformation. Returns true if extension are possible and the above 3605// mentioned transformation is profitable. 3606static bool ExtendUsesToFormExtLoad(SDNode *N, SDValue N0, 3607 unsigned ExtOpc, 3608 SmallVector<SDNode*, 4> &ExtendNodes, 3609 const TargetLowering &TLI) { 3610 bool HasCopyToRegUses = false; 3611 bool isTruncFree = TLI.isTruncateFree(N->getValueType(0), N0.getValueType()); 3612 for (SDNode::use_iterator UI = N0.getNode()->use_begin(), 3613 UE = N0.getNode()->use_end(); 3614 UI != UE; ++UI) { 3615 SDNode *User = *UI; 3616 if (User == N) 3617 continue; 3618 if (UI.getUse().getResNo() != N0.getResNo()) 3619 continue; 3620 // FIXME: Only extend SETCC N, N and SETCC N, c for now. 3621 if (ExtOpc != ISD::ANY_EXTEND && User->getOpcode() == ISD::SETCC) { 3622 ISD::CondCode CC = cast<CondCodeSDNode>(User->getOperand(2))->get(); 3623 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC)) 3624 // Sign bits will be lost after a zext. 3625 return false; 3626 bool Add = false; 3627 for (unsigned i = 0; i != 2; ++i) { 3628 SDValue UseOp = User->getOperand(i); 3629 if (UseOp == N0) 3630 continue; 3631 if (!isa<ConstantSDNode>(UseOp)) 3632 return false; 3633 Add = true; 3634 } 3635 if (Add) 3636 ExtendNodes.push_back(User); 3637 continue; 3638 } 3639 // If truncates aren't free and there are users we can't 3640 // extend, it isn't worthwhile. 3641 if (!isTruncFree) 3642 return false; 3643 // Remember if this value is live-out. 3644 if (User->getOpcode() == ISD::CopyToReg) 3645 HasCopyToRegUses = true; 3646 } 3647 3648 if (HasCopyToRegUses) { 3649 bool BothLiveOut = false; 3650 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 3651 UI != UE; ++UI) { 3652 SDUse &Use = UI.getUse(); 3653 if (Use.getResNo() == 0 && Use.getUser()->getOpcode() == ISD::CopyToReg) { 3654 BothLiveOut = true; 3655 break; 3656 } 3657 } 3658 if (BothLiveOut) 3659 // Both unextended and extended values are live out. There had better be 3660 // a good reason for the transformation. 3661 return ExtendNodes.size(); 3662 } 3663 return true; 3664} 3665 3666SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) { 3667 SDValue N0 = N->getOperand(0); 3668 EVT VT = N->getValueType(0); 3669 3670 // fold (sext c1) -> c1 3671 if (isa<ConstantSDNode>(N0)) 3672 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N0); 3673 3674 // fold (sext (sext x)) -> (sext x) 3675 // fold (sext (aext x)) -> (sext x) 3676 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 3677 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, 3678 N0.getOperand(0)); 3679 3680 if (N0.getOpcode() == ISD::TRUNCATE) { 3681 // fold (sext (truncate (load x))) -> (sext (smaller load x)) 3682 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n))) 3683 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 3684 if (NarrowLoad.getNode()) { 3685 SDNode* oye = N0.getNode()->getOperand(0).getNode(); 3686 if (NarrowLoad.getNode() != N0.getNode()) { 3687 CombineTo(N0.getNode(), NarrowLoad); 3688 // CombineTo deleted the truncate, if needed, but not what's under it. 3689 AddToWorkList(oye); 3690 } 3691 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3692 } 3693 3694 // See if the value being truncated is already sign extended. If so, just 3695 // eliminate the trunc/sext pair. 3696 SDValue Op = N0.getOperand(0); 3697 unsigned OpBits = Op.getValueType().getScalarType().getSizeInBits(); 3698 unsigned MidBits = N0.getValueType().getScalarType().getSizeInBits(); 3699 unsigned DestBits = VT.getScalarType().getSizeInBits(); 3700 unsigned NumSignBits = DAG.ComputeNumSignBits(Op); 3701 3702 if (OpBits == DestBits) { 3703 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign 3704 // bits, it is already ready. 3705 if (NumSignBits > DestBits-MidBits) 3706 return Op; 3707 } else if (OpBits < DestBits) { 3708 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign 3709 // bits, just sext from i32. 3710 if (NumSignBits > OpBits-MidBits) 3711 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, Op); 3712 } else { 3713 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign 3714 // bits, just truncate to i32. 3715 if (NumSignBits > OpBits-MidBits) 3716 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op); 3717 } 3718 3719 // fold (sext (truncate x)) -> (sextinreg x). 3720 if (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, 3721 N0.getValueType())) { 3722 if (OpBits < DestBits) 3723 Op = DAG.getNode(ISD::ANY_EXTEND, N0.getDebugLoc(), VT, Op); 3724 else if (OpBits > DestBits) 3725 Op = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), VT, Op); 3726 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, Op, 3727 DAG.getValueType(N0.getValueType())); 3728 } 3729 } 3730 3731 // fold (sext (load x)) -> (sext (truncate (sextload x))) 3732 // None of the supported targets knows how to perform load and sign extend 3733 // on vectors in one instruction. We only perform this transformation on 3734 // scalars. 3735 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() && 3736 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3737 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()))) { 3738 bool DoXform = true; 3739 SmallVector<SDNode*, 4> SetCCs; 3740 if (!N0.hasOneUse()) 3741 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::SIGN_EXTEND, SetCCs, TLI); 3742 if (DoXform) { 3743 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3744 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 3745 LN0->getChain(), 3746 LN0->getBasePtr(), LN0->getPointerInfo(), 3747 N0.getValueType(), 3748 LN0->isVolatile(), LN0->isNonTemporal(), 3749 LN0->getAlignment()); 3750 CombineTo(N, ExtLoad); 3751 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3752 N0.getValueType(), ExtLoad); 3753 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 3754 3755 // Extend SetCC uses if necessary. 3756 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 3757 SDNode *SetCC = SetCCs[i]; 3758 SmallVector<SDValue, 4> Ops; 3759 3760 for (unsigned j = 0; j != 2; ++j) { 3761 SDValue SOp = SetCC->getOperand(j); 3762 if (SOp == Trunc) 3763 Ops.push_back(ExtLoad); 3764 else 3765 Ops.push_back(DAG.getNode(ISD::SIGN_EXTEND, 3766 N->getDebugLoc(), VT, SOp)); 3767 } 3768 3769 Ops.push_back(SetCC->getOperand(2)); 3770 CombineTo(SetCC, DAG.getNode(ISD::SETCC, N->getDebugLoc(), 3771 SetCC->getValueType(0), 3772 &Ops[0], Ops.size())); 3773 } 3774 3775 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3776 } 3777 } 3778 3779 // fold (sext (sextload x)) -> (sext (truncate (sextload x))) 3780 // fold (sext ( extload x)) -> (sext (truncate (sextload x))) 3781 if ((ISD::isSEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) && 3782 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) { 3783 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3784 EVT MemVT = LN0->getMemoryVT(); 3785 if ((!LegalOperations && !LN0->isVolatile()) || 3786 TLI.isLoadExtLegal(ISD::SEXTLOAD, MemVT)) { 3787 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 3788 LN0->getChain(), 3789 LN0->getBasePtr(), LN0->getPointerInfo(), 3790 MemVT, 3791 LN0->isVolatile(), LN0->isNonTemporal(), 3792 LN0->getAlignment()); 3793 CombineTo(N, ExtLoad); 3794 CombineTo(N0.getNode(), 3795 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3796 N0.getValueType(), ExtLoad), 3797 ExtLoad.getValue(1)); 3798 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3799 } 3800 } 3801 3802 if (N0.getOpcode() == ISD::SETCC) { 3803 // sext(setcc) -> sext_in_reg(vsetcc) for vectors. 3804 // Only do this before legalize for now. 3805 if (VT.isVector() && !LegalOperations) { 3806 EVT N0VT = N0.getOperand(0).getValueType(); 3807 // We know that the # elements of the results is the same as the 3808 // # elements of the compare (and the # elements of the compare result 3809 // for that matter). Check to see that they are the same size. If so, 3810 // we know that the element size of the sext'd result matches the 3811 // element size of the compare operands. 3812 if (VT.getSizeInBits() == N0VT.getSizeInBits()) 3813 return DAG.getVSetCC(N->getDebugLoc(), VT, N0.getOperand(0), 3814 N0.getOperand(1), 3815 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 3816 // If the desired elements are smaller or larger than the source 3817 // elements we can use a matching integer vector type and then 3818 // truncate/sign extend 3819 else { 3820 EVT MatchingElementType = 3821 EVT::getIntegerVT(*DAG.getContext(), 3822 N0VT.getScalarType().getSizeInBits()); 3823 EVT MatchingVectorType = 3824 EVT::getVectorVT(*DAG.getContext(), MatchingElementType, 3825 N0VT.getVectorNumElements()); 3826 SDValue VsetCC = 3827 DAG.getVSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0), 3828 N0.getOperand(1), 3829 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 3830 return DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT); 3831 } 3832 } 3833 3834 // sext(setcc x, y, cc) -> (select_cc x, y, -1, 0, cc) 3835 unsigned ElementWidth = VT.getScalarType().getSizeInBits(); 3836 SDValue NegOne = 3837 DAG.getConstant(APInt::getAllOnesValue(ElementWidth), VT); 3838 SDValue SCC = 3839 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 3840 NegOne, DAG.getConstant(0, VT), 3841 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 3842 if (SCC.getNode()) return SCC; 3843 if (!LegalOperations || 3844 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(VT))) 3845 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT, 3846 DAG.getSetCC(N->getDebugLoc(), 3847 TLI.getSetCCResultType(VT), 3848 N0.getOperand(0), N0.getOperand(1), 3849 cast<CondCodeSDNode>(N0.getOperand(2))->get()), 3850 NegOne, DAG.getConstant(0, VT)); 3851 } 3852 3853 // fold (sext x) -> (zext x) if the sign bit is known zero. 3854 if ((!LegalOperations || TLI.isOperationLegal(ISD::ZERO_EXTEND, VT)) && 3855 DAG.SignBitIsZero(N0)) 3856 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0); 3857 3858 return SDValue(); 3859} 3860 3861SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) { 3862 SDValue N0 = N->getOperand(0); 3863 EVT VT = N->getValueType(0); 3864 3865 // fold (zext c1) -> c1 3866 if (isa<ConstantSDNode>(N0)) 3867 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0); 3868 // fold (zext (zext x)) -> (zext x) 3869 // fold (zext (aext x)) -> (zext x) 3870 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 3871 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, 3872 N0.getOperand(0)); 3873 3874 // fold (zext (truncate (load x))) -> (zext (smaller load x)) 3875 // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n))) 3876 if (N0.getOpcode() == ISD::TRUNCATE) { 3877 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 3878 if (NarrowLoad.getNode()) { 3879 SDNode* oye = N0.getNode()->getOperand(0).getNode(); 3880 if (NarrowLoad.getNode() != N0.getNode()) { 3881 CombineTo(N0.getNode(), NarrowLoad); 3882 // CombineTo deleted the truncate, if needed, but not what's under it. 3883 AddToWorkList(oye); 3884 } 3885 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, NarrowLoad); 3886 } 3887 } 3888 3889 // fold (zext (truncate x)) -> (and x, mask) 3890 if (N0.getOpcode() == ISD::TRUNCATE && 3891 (!LegalOperations || TLI.isOperationLegal(ISD::AND, VT))) { 3892 3893 // fold (zext (truncate (load x))) -> (zext (smaller load x)) 3894 // fold (zext (truncate (srl (load x), c))) -> (zext (smaller load (x+c/n))) 3895 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 3896 if (NarrowLoad.getNode()) { 3897 SDNode* oye = N0.getNode()->getOperand(0).getNode(); 3898 if (NarrowLoad.getNode() != N0.getNode()) { 3899 CombineTo(N0.getNode(), NarrowLoad); 3900 // CombineTo deleted the truncate, if needed, but not what's under it. 3901 AddToWorkList(oye); 3902 } 3903 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3904 } 3905 3906 SDValue Op = N0.getOperand(0); 3907 if (Op.getValueType().bitsLT(VT)) { 3908 Op = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, Op); 3909 } else if (Op.getValueType().bitsGT(VT)) { 3910 Op = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op); 3911 } 3912 return DAG.getZeroExtendInReg(Op, N->getDebugLoc(), 3913 N0.getValueType().getScalarType()); 3914 } 3915 3916 // Fold (zext (and (trunc x), cst)) -> (and x, cst), 3917 // if either of the casts is not free. 3918 if (N0.getOpcode() == ISD::AND && 3919 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 3920 N0.getOperand(1).getOpcode() == ISD::Constant && 3921 (!TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(), 3922 N0.getValueType()) || 3923 !TLI.isZExtFree(N0.getValueType(), VT))) { 3924 SDValue X = N0.getOperand(0).getOperand(0); 3925 if (X.getValueType().bitsLT(VT)) { 3926 X = DAG.getNode(ISD::ANY_EXTEND, X.getDebugLoc(), VT, X); 3927 } else if (X.getValueType().bitsGT(VT)) { 3928 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X); 3929 } 3930 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 3931 Mask = Mask.zext(VT.getSizeInBits()); 3932 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 3933 X, DAG.getConstant(Mask, VT)); 3934 } 3935 3936 // fold (zext (load x)) -> (zext (truncate (zextload x))) 3937 // None of the supported targets knows how to perform load and vector_zext 3938 // on vectors in one instruction. We only perform this transformation on 3939 // scalars. 3940 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() && 3941 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3942 TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()))) { 3943 bool DoXform = true; 3944 SmallVector<SDNode*, 4> SetCCs; 3945 if (!N0.hasOneUse()) 3946 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ZERO_EXTEND, SetCCs, TLI); 3947 if (DoXform) { 3948 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3949 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT, 3950 LN0->getChain(), 3951 LN0->getBasePtr(), LN0->getPointerInfo(), 3952 N0.getValueType(), 3953 LN0->isVolatile(), LN0->isNonTemporal(), 3954 LN0->getAlignment()); 3955 CombineTo(N, ExtLoad); 3956 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3957 N0.getValueType(), ExtLoad); 3958 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 3959 3960 // Extend SetCC uses if necessary. 3961 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 3962 SDNode *SetCC = SetCCs[i]; 3963 SmallVector<SDValue, 4> Ops; 3964 3965 for (unsigned j = 0; j != 2; ++j) { 3966 SDValue SOp = SetCC->getOperand(j); 3967 if (SOp == Trunc) 3968 Ops.push_back(ExtLoad); 3969 else 3970 Ops.push_back(DAG.getNode(ISD::ZERO_EXTEND, 3971 N->getDebugLoc(), VT, SOp)); 3972 } 3973 3974 Ops.push_back(SetCC->getOperand(2)); 3975 CombineTo(SetCC, DAG.getNode(ISD::SETCC, N->getDebugLoc(), 3976 SetCC->getValueType(0), 3977 &Ops[0], Ops.size())); 3978 } 3979 3980 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3981 } 3982 } 3983 3984 // fold (zext (zextload x)) -> (zext (truncate (zextload x))) 3985 // fold (zext ( extload x)) -> (zext (truncate (zextload x))) 3986 if ((ISD::isZEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) && 3987 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) { 3988 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3989 EVT MemVT = LN0->getMemoryVT(); 3990 if ((!LegalOperations && !LN0->isVolatile()) || 3991 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT)) { 3992 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT, 3993 LN0->getChain(), 3994 LN0->getBasePtr(), LN0->getPointerInfo(), 3995 MemVT, 3996 LN0->isVolatile(), LN0->isNonTemporal(), 3997 LN0->getAlignment()); 3998 CombineTo(N, ExtLoad); 3999 CombineTo(N0.getNode(), 4000 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), N0.getValueType(), 4001 ExtLoad), 4002 ExtLoad.getValue(1)); 4003 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4004 } 4005 } 4006 4007 if (N0.getOpcode() == ISD::SETCC) { 4008 if (!LegalOperations && VT.isVector()) { 4009 // zext(setcc) -> (and (vsetcc), (1, 1, ...) for vectors. 4010 // Only do this before legalize for now. 4011 EVT N0VT = N0.getOperand(0).getValueType(); 4012 EVT EltVT = VT.getVectorElementType(); 4013 SmallVector<SDValue,8> OneOps(VT.getVectorNumElements(), 4014 DAG.getConstant(1, EltVT)); 4015 if (VT.getSizeInBits() == N0VT.getSizeInBits()) { 4016 // We know that the # elements of the results is the same as the 4017 // # elements of the compare (and the # elements of the compare result 4018 // for that matter). Check to see that they are the same size. If so, 4019 // we know that the element size of the sext'd result matches the 4020 // element size of the compare operands. 4021 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 4022 DAG.getVSetCC(N->getDebugLoc(), VT, N0.getOperand(0), 4023 N0.getOperand(1), 4024 cast<CondCodeSDNode>(N0.getOperand(2))->get()), 4025 DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT, 4026 &OneOps[0], OneOps.size())); 4027 } else { 4028 // If the desired elements are smaller or larger than the source 4029 // elements we can use a matching integer vector type and then 4030 // truncate/sign extend 4031 EVT MatchingElementType = 4032 EVT::getIntegerVT(*DAG.getContext(), 4033 N0VT.getScalarType().getSizeInBits()); 4034 EVT MatchingVectorType = 4035 EVT::getVectorVT(*DAG.getContext(), MatchingElementType, 4036 N0VT.getVectorNumElements()); 4037 SDValue VsetCC = 4038 DAG.getVSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0), 4039 N0.getOperand(1), 4040 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 4041 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 4042 DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT), 4043 DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT, 4044 &OneOps[0], OneOps.size())); 4045 } 4046 } 4047 4048 // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 4049 SDValue SCC = 4050 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 4051 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 4052 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 4053 if (SCC.getNode()) return SCC; 4054 } 4055 4056 // (zext (shl (zext x), cst)) -> (shl (zext x), cst) 4057 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL) && 4058 isa<ConstantSDNode>(N0.getOperand(1)) && 4059 N0.getOperand(0).getOpcode() == ISD::ZERO_EXTEND && 4060 N0.hasOneUse()) { 4061 SDValue ShAmt = N0.getOperand(1); 4062 unsigned ShAmtVal = cast<ConstantSDNode>(ShAmt)->getZExtValue(); 4063 if (N0.getOpcode() == ISD::SHL) { 4064 SDValue InnerZExt = N0.getOperand(0); 4065 // If the original shl may be shifting out bits, do not perform this 4066 // transformation. 4067 unsigned KnownZeroBits = InnerZExt.getValueType().getSizeInBits() - 4068 InnerZExt.getOperand(0).getValueType().getSizeInBits(); 4069 if (ShAmtVal > KnownZeroBits) 4070 return SDValue(); 4071 } 4072 4073 DebugLoc DL = N->getDebugLoc(); 4074 4075 // Ensure that the shift amount is wide enough for the shifted value. 4076 if (VT.getSizeInBits() >= 256) 4077 ShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, ShAmt); 4078 4079 return DAG.getNode(N0.getOpcode(), DL, VT, 4080 DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0)), 4081 ShAmt); 4082 } 4083 4084 return SDValue(); 4085} 4086 4087SDValue DAGCombiner::visitANY_EXTEND(SDNode *N) { 4088 SDValue N0 = N->getOperand(0); 4089 EVT VT = N->getValueType(0); 4090 4091 // fold (aext c1) -> c1 4092 if (isa<ConstantSDNode>(N0)) 4093 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, N0); 4094 // fold (aext (aext x)) -> (aext x) 4095 // fold (aext (zext x)) -> (zext x) 4096 // fold (aext (sext x)) -> (sext x) 4097 if (N0.getOpcode() == ISD::ANY_EXTEND || 4098 N0.getOpcode() == ISD::ZERO_EXTEND || 4099 N0.getOpcode() == ISD::SIGN_EXTEND) 4100 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, N0.getOperand(0)); 4101 4102 // fold (aext (truncate (load x))) -> (aext (smaller load x)) 4103 // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n))) 4104 if (N0.getOpcode() == ISD::TRUNCATE) { 4105 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 4106 if (NarrowLoad.getNode()) { 4107 SDNode* oye = N0.getNode()->getOperand(0).getNode(); 4108 if (NarrowLoad.getNode() != N0.getNode()) { 4109 CombineTo(N0.getNode(), NarrowLoad); 4110 // CombineTo deleted the truncate, if needed, but not what's under it. 4111 AddToWorkList(oye); 4112 } 4113 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, NarrowLoad); 4114 } 4115 } 4116 4117 // fold (aext (truncate x)) 4118 if (N0.getOpcode() == ISD::TRUNCATE) { 4119 SDValue TruncOp = N0.getOperand(0); 4120 if (TruncOp.getValueType() == VT) 4121 return TruncOp; // x iff x size == zext size. 4122 if (TruncOp.getValueType().bitsGT(VT)) 4123 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, TruncOp); 4124 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, TruncOp); 4125 } 4126 4127 // Fold (aext (and (trunc x), cst)) -> (and x, cst) 4128 // if the trunc is not free. 4129 if (N0.getOpcode() == ISD::AND && 4130 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 4131 N0.getOperand(1).getOpcode() == ISD::Constant && 4132 !TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(), 4133 N0.getValueType())) { 4134 SDValue X = N0.getOperand(0).getOperand(0); 4135 if (X.getValueType().bitsLT(VT)) { 4136 X = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, X); 4137 } else if (X.getValueType().bitsGT(VT)) { 4138 X = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, X); 4139 } 4140 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 4141 Mask = Mask.zext(VT.getSizeInBits()); 4142 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 4143 X, DAG.getConstant(Mask, VT)); 4144 } 4145 4146 // fold (aext (load x)) -> (aext (truncate (extload x))) 4147 // None of the supported targets knows how to perform load and any_ext 4148 // on vectors in one instruction. We only perform this transformation on 4149 // scalars. 4150 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() && 4151 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 4152 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) { 4153 bool DoXform = true; 4154 SmallVector<SDNode*, 4> SetCCs; 4155 if (!N0.hasOneUse()) 4156 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ANY_EXTEND, SetCCs, TLI); 4157 if (DoXform) { 4158 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4159 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT, 4160 LN0->getChain(), 4161 LN0->getBasePtr(), LN0->getPointerInfo(), 4162 N0.getValueType(), 4163 LN0->isVolatile(), LN0->isNonTemporal(), 4164 LN0->getAlignment()); 4165 CombineTo(N, ExtLoad); 4166 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 4167 N0.getValueType(), ExtLoad); 4168 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 4169 4170 // Extend SetCC uses if necessary. 4171 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 4172 SDNode *SetCC = SetCCs[i]; 4173 SmallVector<SDValue, 4> Ops; 4174 4175 for (unsigned j = 0; j != 2; ++j) { 4176 SDValue SOp = SetCC->getOperand(j); 4177 if (SOp == Trunc) 4178 Ops.push_back(ExtLoad); 4179 else 4180 Ops.push_back(DAG.getNode(ISD::ANY_EXTEND, 4181 N->getDebugLoc(), VT, SOp)); 4182 } 4183 4184 Ops.push_back(SetCC->getOperand(2)); 4185 CombineTo(SetCC, DAG.getNode(ISD::SETCC, N->getDebugLoc(), 4186 SetCC->getValueType(0), 4187 &Ops[0], Ops.size())); 4188 } 4189 4190 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4191 } 4192 } 4193 4194 // fold (aext (zextload x)) -> (aext (truncate (zextload x))) 4195 // fold (aext (sextload x)) -> (aext (truncate (sextload x))) 4196 // fold (aext ( extload x)) -> (aext (truncate (extload x))) 4197 if (N0.getOpcode() == ISD::LOAD && 4198 !ISD::isNON_EXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 4199 N0.hasOneUse()) { 4200 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4201 EVT MemVT = LN0->getMemoryVT(); 4202 SDValue ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), N->getDebugLoc(), 4203 VT, LN0->getChain(), LN0->getBasePtr(), 4204 LN0->getPointerInfo(), MemVT, 4205 LN0->isVolatile(), LN0->isNonTemporal(), 4206 LN0->getAlignment()); 4207 CombineTo(N, ExtLoad); 4208 CombineTo(N0.getNode(), 4209 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 4210 N0.getValueType(), ExtLoad), 4211 ExtLoad.getValue(1)); 4212 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4213 } 4214 4215 if (N0.getOpcode() == ISD::SETCC) { 4216 // aext(setcc) -> sext_in_reg(vsetcc) for vectors. 4217 // Only do this before legalize for now. 4218 if (VT.isVector() && !LegalOperations) { 4219 EVT N0VT = N0.getOperand(0).getValueType(); 4220 // We know that the # elements of the results is the same as the 4221 // # elements of the compare (and the # elements of the compare result 4222 // for that matter). Check to see that they are the same size. If so, 4223 // we know that the element size of the sext'd result matches the 4224 // element size of the compare operands. 4225 if (VT.getSizeInBits() == N0VT.getSizeInBits()) 4226 return DAG.getVSetCC(N->getDebugLoc(), VT, N0.getOperand(0), 4227 N0.getOperand(1), 4228 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 4229 // If the desired elements are smaller or larger than the source 4230 // elements we can use a matching integer vector type and then 4231 // truncate/sign extend 4232 else { 4233 EVT MatchingElementType = 4234 EVT::getIntegerVT(*DAG.getContext(), 4235 N0VT.getScalarType().getSizeInBits()); 4236 EVT MatchingVectorType = 4237 EVT::getVectorVT(*DAG.getContext(), MatchingElementType, 4238 N0VT.getVectorNumElements()); 4239 SDValue VsetCC = 4240 DAG.getVSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0), 4241 N0.getOperand(1), 4242 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 4243 return DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT); 4244 } 4245 } 4246 4247 // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 4248 SDValue SCC = 4249 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 4250 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 4251 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 4252 if (SCC.getNode()) 4253 return SCC; 4254 } 4255 4256 return SDValue(); 4257} 4258 4259/// GetDemandedBits - See if the specified operand can be simplified with the 4260/// knowledge that only the bits specified by Mask are used. If so, return the 4261/// simpler operand, otherwise return a null SDValue. 4262SDValue DAGCombiner::GetDemandedBits(SDValue V, const APInt &Mask) { 4263 switch (V.getOpcode()) { 4264 default: break; 4265 case ISD::OR: 4266 case ISD::XOR: 4267 // If the LHS or RHS don't contribute bits to the or, drop them. 4268 if (DAG.MaskedValueIsZero(V.getOperand(0), Mask)) 4269 return V.getOperand(1); 4270 if (DAG.MaskedValueIsZero(V.getOperand(1), Mask)) 4271 return V.getOperand(0); 4272 break; 4273 case ISD::SRL: 4274 // Only look at single-use SRLs. 4275 if (!V.getNode()->hasOneUse()) 4276 break; 4277 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(V.getOperand(1))) { 4278 // See if we can recursively simplify the LHS. 4279 unsigned Amt = RHSC->getZExtValue(); 4280 4281 // Watch out for shift count overflow though. 4282 if (Amt >= Mask.getBitWidth()) break; 4283 APInt NewMask = Mask << Amt; 4284 SDValue SimplifyLHS = GetDemandedBits(V.getOperand(0), NewMask); 4285 if (SimplifyLHS.getNode()) 4286 return DAG.getNode(ISD::SRL, V.getDebugLoc(), V.getValueType(), 4287 SimplifyLHS, V.getOperand(1)); 4288 } 4289 } 4290 return SDValue(); 4291} 4292 4293/// ReduceLoadWidth - If the result of a wider load is shifted to right of N 4294/// bits and then truncated to a narrower type and where N is a multiple 4295/// of number of bits of the narrower type, transform it to a narrower load 4296/// from address + N / num of bits of new type. If the result is to be 4297/// extended, also fold the extension to form a extending load. 4298SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) { 4299 unsigned Opc = N->getOpcode(); 4300 4301 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD; 4302 SDValue N0 = N->getOperand(0); 4303 EVT VT = N->getValueType(0); 4304 EVT ExtVT = VT; 4305 4306 // This transformation isn't valid for vector loads. 4307 if (VT.isVector()) 4308 return SDValue(); 4309 4310 // Special case: SIGN_EXTEND_INREG is basically truncating to ExtVT then 4311 // extended to VT. 4312 if (Opc == ISD::SIGN_EXTEND_INREG) { 4313 ExtType = ISD::SEXTLOAD; 4314 ExtVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 4315 } else if (Opc == ISD::SRL) { 4316 // Another special-case: SRL is basically zero-extending a narrower value. 4317 ExtType = ISD::ZEXTLOAD; 4318 N0 = SDValue(N, 0); 4319 ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 4320 if (!N01) return SDValue(); 4321 ExtVT = EVT::getIntegerVT(*DAG.getContext(), 4322 VT.getSizeInBits() - N01->getZExtValue()); 4323 } 4324 if (LegalOperations && !TLI.isLoadExtLegal(ExtType, ExtVT)) 4325 return SDValue(); 4326 4327 unsigned EVTBits = ExtVT.getSizeInBits(); 4328 4329 // Do not generate loads of non-round integer types since these can 4330 // be expensive (and would be wrong if the type is not byte sized). 4331 if (!ExtVT.isRound()) 4332 return SDValue(); 4333 4334 unsigned ShAmt = 0; 4335 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) { 4336 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 4337 ShAmt = N01->getZExtValue(); 4338 // Is the shift amount a multiple of size of VT? 4339 if ((ShAmt & (EVTBits-1)) == 0) { 4340 N0 = N0.getOperand(0); 4341 // Is the load width a multiple of size of VT? 4342 if ((N0.getValueType().getSizeInBits() & (EVTBits-1)) != 0) 4343 return SDValue(); 4344 } 4345 4346 // At this point, we must have a load or else we can't do the transform. 4347 if (!isa<LoadSDNode>(N0)) return SDValue(); 4348 4349 // If the shift amount is larger than the input type then we're not 4350 // accessing any of the loaded bytes. If the load was a zextload/extload 4351 // then the result of the shift+trunc is zero/undef (handled elsewhere). 4352 // If the load was a sextload then the result is a splat of the sign bit 4353 // of the extended byte. This is not worth optimizing for. 4354 if (ShAmt >= cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits()) 4355 return SDValue(); 4356 } 4357 } 4358 4359 // If the load is shifted left (and the result isn't shifted back right), 4360 // we can fold the truncate through the shift. 4361 unsigned ShLeftAmt = 0; 4362 if (ShAmt == 0 && N0.getOpcode() == ISD::SHL && N0.hasOneUse() && 4363 ExtVT == VT && TLI.isNarrowingProfitable(N0.getValueType(), VT)) { 4364 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 4365 ShLeftAmt = N01->getZExtValue(); 4366 N0 = N0.getOperand(0); 4367 } 4368 } 4369 4370 // If we haven't found a load, we can't narrow it. Don't transform one with 4371 // multiple uses, this would require adding a new load. 4372 if (!isa<LoadSDNode>(N0) || !N0.hasOneUse() || 4373 // Don't change the width of a volatile load. 4374 cast<LoadSDNode>(N0)->isVolatile()) 4375 return SDValue(); 4376 4377 // Verify that we are actually reducing a load width here. 4378 if (cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits() < EVTBits) 4379 return SDValue(); 4380 4381 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4382 EVT PtrType = N0.getOperand(1).getValueType(); 4383 4384 // For big endian targets, we need to adjust the offset to the pointer to 4385 // load the correct bytes. 4386 if (TLI.isBigEndian()) { 4387 unsigned LVTStoreBits = LN0->getMemoryVT().getStoreSizeInBits(); 4388 unsigned EVTStoreBits = ExtVT.getStoreSizeInBits(); 4389 ShAmt = LVTStoreBits - EVTStoreBits - ShAmt; 4390 } 4391 4392 uint64_t PtrOff = ShAmt / 8; 4393 unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff); 4394 SDValue NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(), 4395 PtrType, LN0->getBasePtr(), 4396 DAG.getConstant(PtrOff, PtrType)); 4397 AddToWorkList(NewPtr.getNode()); 4398 4399 SDValue Load; 4400 if (ExtType == ISD::NON_EXTLOAD) 4401 Load = DAG.getLoad(VT, N0.getDebugLoc(), LN0->getChain(), NewPtr, 4402 LN0->getPointerInfo().getWithOffset(PtrOff), 4403 LN0->isVolatile(), LN0->isNonTemporal(), NewAlign); 4404 else 4405 Load = DAG.getExtLoad(ExtType, N0.getDebugLoc(), VT, LN0->getChain(),NewPtr, 4406 LN0->getPointerInfo().getWithOffset(PtrOff), 4407 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(), 4408 NewAlign); 4409 4410 // Replace the old load's chain with the new load's chain. 4411 WorkListRemover DeadNodes(*this); 4412 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1), 4413 &DeadNodes); 4414 4415 // Shift the result left, if we've swallowed a left shift. 4416 SDValue Result = Load; 4417 if (ShLeftAmt != 0) { 4418 EVT ShImmTy = getShiftAmountTy(Result.getValueType()); 4419 if (!isUIntN(ShImmTy.getSizeInBits(), ShLeftAmt)) 4420 ShImmTy = VT; 4421 Result = DAG.getNode(ISD::SHL, N0.getDebugLoc(), VT, 4422 Result, DAG.getConstant(ShLeftAmt, ShImmTy)); 4423 } 4424 4425 // Return the new loaded value. 4426 return Result; 4427} 4428 4429SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) { 4430 SDValue N0 = N->getOperand(0); 4431 SDValue N1 = N->getOperand(1); 4432 EVT VT = N->getValueType(0); 4433 EVT EVT = cast<VTSDNode>(N1)->getVT(); 4434 unsigned VTBits = VT.getScalarType().getSizeInBits(); 4435 unsigned EVTBits = EVT.getScalarType().getSizeInBits(); 4436 4437 // fold (sext_in_reg c1) -> c1 4438 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF) 4439 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, N0, N1); 4440 4441 // If the input is already sign extended, just drop the extension. 4442 if (DAG.ComputeNumSignBits(N0) >= VTBits-EVTBits+1) 4443 return N0; 4444 4445 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2 4446 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 4447 EVT.bitsLT(cast<VTSDNode>(N0.getOperand(1))->getVT())) { 4448 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, 4449 N0.getOperand(0), N1); 4450 } 4451 4452 // fold (sext_in_reg (sext x)) -> (sext x) 4453 // fold (sext_in_reg (aext x)) -> (sext x) 4454 // if x is small enough. 4455 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) { 4456 SDValue N00 = N0.getOperand(0); 4457 if (N00.getValueType().getScalarType().getSizeInBits() <= EVTBits && 4458 (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND, VT))) 4459 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N00, N1); 4460 } 4461 4462 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero. 4463 if (DAG.MaskedValueIsZero(N0, APInt::getBitsSet(VTBits, EVTBits-1, EVTBits))) 4464 return DAG.getZeroExtendInReg(N0, N->getDebugLoc(), EVT); 4465 4466 // fold operands of sext_in_reg based on knowledge that the top bits are not 4467 // demanded. 4468 if (SimplifyDemandedBits(SDValue(N, 0))) 4469 return SDValue(N, 0); 4470 4471 // fold (sext_in_reg (load x)) -> (smaller sextload x) 4472 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits)) 4473 SDValue NarrowLoad = ReduceLoadWidth(N); 4474 if (NarrowLoad.getNode()) 4475 return NarrowLoad; 4476 4477 // fold (sext_in_reg (srl X, 24), i8) -> (sra X, 24) 4478 // fold (sext_in_reg (srl X, 23), i8) -> (sra X, 23) iff possible. 4479 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above. 4480 if (N0.getOpcode() == ISD::SRL) { 4481 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 4482 if (ShAmt->getZExtValue()+EVTBits <= VTBits) { 4483 // We can turn this into an SRA iff the input to the SRL is already sign 4484 // extended enough. 4485 unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0)); 4486 if (VTBits-(ShAmt->getZExtValue()+EVTBits) < InSignBits) 4487 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, 4488 N0.getOperand(0), N0.getOperand(1)); 4489 } 4490 } 4491 4492 // fold (sext_inreg (extload x)) -> (sextload x) 4493 if (ISD::isEXTLoad(N0.getNode()) && 4494 ISD::isUNINDEXEDLoad(N0.getNode()) && 4495 EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 4496 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 4497 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) { 4498 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4499 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 4500 LN0->getChain(), 4501 LN0->getBasePtr(), LN0->getPointerInfo(), 4502 EVT, 4503 LN0->isVolatile(), LN0->isNonTemporal(), 4504 LN0->getAlignment()); 4505 CombineTo(N, ExtLoad); 4506 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 4507 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4508 } 4509 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use 4510 if (ISD::isZEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 4511 N0.hasOneUse() && 4512 EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 4513 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 4514 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) { 4515 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4516 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 4517 LN0->getChain(), 4518 LN0->getBasePtr(), LN0->getPointerInfo(), 4519 EVT, 4520 LN0->isVolatile(), LN0->isNonTemporal(), 4521 LN0->getAlignment()); 4522 CombineTo(N, ExtLoad); 4523 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 4524 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4525 } 4526 return SDValue(); 4527} 4528 4529SDValue DAGCombiner::visitTRUNCATE(SDNode *N) { 4530 SDValue N0 = N->getOperand(0); 4531 EVT VT = N->getValueType(0); 4532 4533 // noop truncate 4534 if (N0.getValueType() == N->getValueType(0)) 4535 return N0; 4536 // fold (truncate c1) -> c1 4537 if (isa<ConstantSDNode>(N0)) 4538 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0); 4539 // fold (truncate (truncate x)) -> (truncate x) 4540 if (N0.getOpcode() == ISD::TRUNCATE) 4541 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0)); 4542 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x 4543 if (N0.getOpcode() == ISD::ZERO_EXTEND || 4544 N0.getOpcode() == ISD::SIGN_EXTEND || 4545 N0.getOpcode() == ISD::ANY_EXTEND) { 4546 if (N0.getOperand(0).getValueType().bitsLT(VT)) 4547 // if the source is smaller than the dest, we still need an extend 4548 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, 4549 N0.getOperand(0)); 4550 else if (N0.getOperand(0).getValueType().bitsGT(VT)) 4551 // if the source is larger than the dest, than we just need the truncate 4552 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0)); 4553 else 4554 // if the source and dest are the same type, we can drop both the extend 4555 // and the truncate. 4556 return N0.getOperand(0); 4557 } 4558 4559 // See if we can simplify the input to this truncate through knowledge that 4560 // only the low bits are being used. 4561 // For example "trunc (or (shl x, 8), y)" // -> trunc y 4562 // Currently we only perform this optimization on scalars because vectors 4563 // may have different active low bits. 4564 if (!VT.isVector()) { 4565 SDValue Shorter = 4566 GetDemandedBits(N0, APInt::getLowBitsSet(N0.getValueSizeInBits(), 4567 VT.getSizeInBits())); 4568 if (Shorter.getNode()) 4569 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Shorter); 4570 } 4571 // fold (truncate (load x)) -> (smaller load x) 4572 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits)) 4573 if (!LegalTypes || TLI.isTypeDesirableForOp(N0.getOpcode(), VT)) { 4574 SDValue Reduced = ReduceLoadWidth(N); 4575 if (Reduced.getNode()) 4576 return Reduced; 4577 } 4578 4579 // Simplify the operands using demanded-bits information. 4580 if (!VT.isVector() && 4581 SimplifyDemandedBits(SDValue(N, 0))) 4582 return SDValue(N, 0); 4583 4584 return SDValue(); 4585} 4586 4587static SDNode *getBuildPairElt(SDNode *N, unsigned i) { 4588 SDValue Elt = N->getOperand(i); 4589 if (Elt.getOpcode() != ISD::MERGE_VALUES) 4590 return Elt.getNode(); 4591 return Elt.getOperand(Elt.getResNo()).getNode(); 4592} 4593 4594/// CombineConsecutiveLoads - build_pair (load, load) -> load 4595/// if load locations are consecutive. 4596SDValue DAGCombiner::CombineConsecutiveLoads(SDNode *N, EVT VT) { 4597 assert(N->getOpcode() == ISD::BUILD_PAIR); 4598 4599 LoadSDNode *LD1 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 0)); 4600 LoadSDNode *LD2 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 1)); 4601 if (!LD1 || !LD2 || !ISD::isNON_EXTLoad(LD1) || !LD1->hasOneUse() || 4602 LD1->getPointerInfo().getAddrSpace() != 4603 LD2->getPointerInfo().getAddrSpace()) 4604 return SDValue(); 4605 EVT LD1VT = LD1->getValueType(0); 4606 4607 if (ISD::isNON_EXTLoad(LD2) && 4608 LD2->hasOneUse() && 4609 // If both are volatile this would reduce the number of volatile loads. 4610 // If one is volatile it might be ok, but play conservative and bail out. 4611 !LD1->isVolatile() && 4612 !LD2->isVolatile() && 4613 DAG.isConsecutiveLoad(LD2, LD1, LD1VT.getSizeInBits()/8, 1)) { 4614 unsigned Align = LD1->getAlignment(); 4615 unsigned NewAlign = TLI.getTargetData()-> 4616 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext())); 4617 4618 if (NewAlign <= Align && 4619 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) 4620 return DAG.getLoad(VT, N->getDebugLoc(), LD1->getChain(), 4621 LD1->getBasePtr(), LD1->getPointerInfo(), 4622 false, false, Align); 4623 } 4624 4625 return SDValue(); 4626} 4627 4628SDValue DAGCombiner::visitBITCAST(SDNode *N) { 4629 SDValue N0 = N->getOperand(0); 4630 EVT VT = N->getValueType(0); 4631 4632 // If the input is a BUILD_VECTOR with all constant elements, fold this now. 4633 // Only do this before legalize, since afterward the target may be depending 4634 // on the bitconvert. 4635 // First check to see if this is all constant. 4636 if (!LegalTypes && 4637 N0.getOpcode() == ISD::BUILD_VECTOR && N0.getNode()->hasOneUse() && 4638 VT.isVector()) { 4639 bool isSimple = true; 4640 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i) 4641 if (N0.getOperand(i).getOpcode() != ISD::UNDEF && 4642 N0.getOperand(i).getOpcode() != ISD::Constant && 4643 N0.getOperand(i).getOpcode() != ISD::ConstantFP) { 4644 isSimple = false; 4645 break; 4646 } 4647 4648 EVT DestEltVT = N->getValueType(0).getVectorElementType(); 4649 assert(!DestEltVT.isVector() && 4650 "Element type of vector ValueType must not be vector!"); 4651 if (isSimple) 4652 return ConstantFoldBITCASTofBUILD_VECTOR(N0.getNode(), DestEltVT); 4653 } 4654 4655 // If the input is a constant, let getNode fold it. 4656 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) { 4657 SDValue Res = DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, N0); 4658 if (Res.getNode() != N) { 4659 if (!LegalOperations || 4660 TLI.isOperationLegal(Res.getNode()->getOpcode(), VT)) 4661 return Res; 4662 4663 // Folding it resulted in an illegal node, and it's too late to 4664 // do that. Clean up the old node and forego the transformation. 4665 // Ideally this won't happen very often, because instcombine 4666 // and the earlier dagcombine runs (where illegal nodes are 4667 // permitted) should have folded most of them already. 4668 DAG.DeleteNode(Res.getNode()); 4669 } 4670 } 4671 4672 // (conv (conv x, t1), t2) -> (conv x, t2) 4673 if (N0.getOpcode() == ISD::BITCAST) 4674 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, 4675 N0.getOperand(0)); 4676 4677 // fold (conv (load x)) -> (load (conv*)x) 4678 // If the resultant load doesn't need a higher alignment than the original! 4679 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() && 4680 // Do not change the width of a volatile load. 4681 !cast<LoadSDNode>(N0)->isVolatile() && 4682 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) { 4683 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4684 unsigned Align = TLI.getTargetData()-> 4685 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext())); 4686 unsigned OrigAlign = LN0->getAlignment(); 4687 4688 if (Align <= OrigAlign) { 4689 SDValue Load = DAG.getLoad(VT, N->getDebugLoc(), LN0->getChain(), 4690 LN0->getBasePtr(), LN0->getPointerInfo(), 4691 LN0->isVolatile(), LN0->isNonTemporal(), 4692 OrigAlign); 4693 AddToWorkList(N); 4694 CombineTo(N0.getNode(), 4695 DAG.getNode(ISD::BITCAST, N0.getDebugLoc(), 4696 N0.getValueType(), Load), 4697 Load.getValue(1)); 4698 return Load; 4699 } 4700 } 4701 4702 // fold (bitconvert (fneg x)) -> (xor (bitconvert x), signbit) 4703 // fold (bitconvert (fabs x)) -> (and (bitconvert x), (not signbit)) 4704 // This often reduces constant pool loads. 4705 if ((N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FABS) && 4706 N0.getNode()->hasOneUse() && VT.isInteger() && !VT.isVector()) { 4707 SDValue NewConv = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(), VT, 4708 N0.getOperand(0)); 4709 AddToWorkList(NewConv.getNode()); 4710 4711 APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); 4712 if (N0.getOpcode() == ISD::FNEG) 4713 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, 4714 NewConv, DAG.getConstant(SignBit, VT)); 4715 assert(N0.getOpcode() == ISD::FABS); 4716 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 4717 NewConv, DAG.getConstant(~SignBit, VT)); 4718 } 4719 4720 // fold (bitconvert (fcopysign cst, x)) -> 4721 // (or (and (bitconvert x), sign), (and cst, (not sign))) 4722 // Note that we don't handle (copysign x, cst) because this can always be 4723 // folded to an fneg or fabs. 4724 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse() && 4725 isa<ConstantFPSDNode>(N0.getOperand(0)) && 4726 VT.isInteger() && !VT.isVector()) { 4727 unsigned OrigXWidth = N0.getOperand(1).getValueType().getSizeInBits(); 4728 EVT IntXVT = EVT::getIntegerVT(*DAG.getContext(), OrigXWidth); 4729 if (isTypeLegal(IntXVT)) { 4730 SDValue X = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(), 4731 IntXVT, N0.getOperand(1)); 4732 AddToWorkList(X.getNode()); 4733 4734 // If X has a different width than the result/lhs, sext it or truncate it. 4735 unsigned VTWidth = VT.getSizeInBits(); 4736 if (OrigXWidth < VTWidth) { 4737 X = DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, X); 4738 AddToWorkList(X.getNode()); 4739 } else if (OrigXWidth > VTWidth) { 4740 // To get the sign bit in the right place, we have to shift it right 4741 // before truncating. 4742 X = DAG.getNode(ISD::SRL, X.getDebugLoc(), 4743 X.getValueType(), X, 4744 DAG.getConstant(OrigXWidth-VTWidth, X.getValueType())); 4745 AddToWorkList(X.getNode()); 4746 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X); 4747 AddToWorkList(X.getNode()); 4748 } 4749 4750 APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); 4751 X = DAG.getNode(ISD::AND, X.getDebugLoc(), VT, 4752 X, DAG.getConstant(SignBit, VT)); 4753 AddToWorkList(X.getNode()); 4754 4755 SDValue Cst = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(), 4756 VT, N0.getOperand(0)); 4757 Cst = DAG.getNode(ISD::AND, Cst.getDebugLoc(), VT, 4758 Cst, DAG.getConstant(~SignBit, VT)); 4759 AddToWorkList(Cst.getNode()); 4760 4761 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, X, Cst); 4762 } 4763 } 4764 4765 // bitconvert(build_pair(ld, ld)) -> ld iff load locations are consecutive. 4766 if (N0.getOpcode() == ISD::BUILD_PAIR) { 4767 SDValue CombineLD = CombineConsecutiveLoads(N0.getNode(), VT); 4768 if (CombineLD.getNode()) 4769 return CombineLD; 4770 } 4771 4772 return SDValue(); 4773} 4774 4775SDValue DAGCombiner::visitBUILD_PAIR(SDNode *N) { 4776 EVT VT = N->getValueType(0); 4777 return CombineConsecutiveLoads(N, VT); 4778} 4779 4780/// ConstantFoldBITCASTofBUILD_VECTOR - We know that BV is a build_vector 4781/// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the 4782/// destination element value type. 4783SDValue DAGCombiner:: 4784ConstantFoldBITCASTofBUILD_VECTOR(SDNode *BV, EVT DstEltVT) { 4785 EVT SrcEltVT = BV->getValueType(0).getVectorElementType(); 4786 4787 // If this is already the right type, we're done. 4788 if (SrcEltVT == DstEltVT) return SDValue(BV, 0); 4789 4790 unsigned SrcBitSize = SrcEltVT.getSizeInBits(); 4791 unsigned DstBitSize = DstEltVT.getSizeInBits(); 4792 4793 // If this is a conversion of N elements of one type to N elements of another 4794 // type, convert each element. This handles FP<->INT cases. 4795 if (SrcBitSize == DstBitSize) { 4796 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, 4797 BV->getValueType(0).getVectorNumElements()); 4798 4799 // Due to the FP element handling below calling this routine recursively, 4800 // we can end up with a scalar-to-vector node here. 4801 if (BV->getOpcode() == ISD::SCALAR_TO_VECTOR) 4802 return DAG.getNode(ISD::SCALAR_TO_VECTOR, BV->getDebugLoc(), VT, 4803 DAG.getNode(ISD::BITCAST, BV->getDebugLoc(), 4804 DstEltVT, BV->getOperand(0))); 4805 4806 SmallVector<SDValue, 8> Ops; 4807 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 4808 SDValue Op = BV->getOperand(i); 4809 // If the vector element type is not legal, the BUILD_VECTOR operands 4810 // are promoted and implicitly truncated. Make that explicit here. 4811 if (Op.getValueType() != SrcEltVT) 4812 Op = DAG.getNode(ISD::TRUNCATE, BV->getDebugLoc(), SrcEltVT, Op); 4813 Ops.push_back(DAG.getNode(ISD::BITCAST, BV->getDebugLoc(), 4814 DstEltVT, Op)); 4815 AddToWorkList(Ops.back().getNode()); 4816 } 4817 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 4818 &Ops[0], Ops.size()); 4819 } 4820 4821 // Otherwise, we're growing or shrinking the elements. To avoid having to 4822 // handle annoying details of growing/shrinking FP values, we convert them to 4823 // int first. 4824 if (SrcEltVT.isFloatingPoint()) { 4825 // Convert the input float vector to a int vector where the elements are the 4826 // same sizes. 4827 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!"); 4828 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), SrcEltVT.getSizeInBits()); 4829 BV = ConstantFoldBITCASTofBUILD_VECTOR(BV, IntVT).getNode(); 4830 SrcEltVT = IntVT; 4831 } 4832 4833 // Now we know the input is an integer vector. If the output is a FP type, 4834 // convert to integer first, then to FP of the right size. 4835 if (DstEltVT.isFloatingPoint()) { 4836 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!"); 4837 EVT TmpVT = EVT::getIntegerVT(*DAG.getContext(), DstEltVT.getSizeInBits()); 4838 SDNode *Tmp = ConstantFoldBITCASTofBUILD_VECTOR(BV, TmpVT).getNode(); 4839 4840 // Next, convert to FP elements of the same size. 4841 return ConstantFoldBITCASTofBUILD_VECTOR(Tmp, DstEltVT); 4842 } 4843 4844 // Okay, we know the src/dst types are both integers of differing types. 4845 // Handling growing first. 4846 assert(SrcEltVT.isInteger() && DstEltVT.isInteger()); 4847 if (SrcBitSize < DstBitSize) { 4848 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize; 4849 4850 SmallVector<SDValue, 8> Ops; 4851 for (unsigned i = 0, e = BV->getNumOperands(); i != e; 4852 i += NumInputsPerOutput) { 4853 bool isLE = TLI.isLittleEndian(); 4854 APInt NewBits = APInt(DstBitSize, 0); 4855 bool EltIsUndef = true; 4856 for (unsigned j = 0; j != NumInputsPerOutput; ++j) { 4857 // Shift the previously computed bits over. 4858 NewBits <<= SrcBitSize; 4859 SDValue Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j)); 4860 if (Op.getOpcode() == ISD::UNDEF) continue; 4861 EltIsUndef = false; 4862 4863 NewBits |= cast<ConstantSDNode>(Op)->getAPIntValue(). 4864 zextOrTrunc(SrcBitSize).zext(DstBitSize); 4865 } 4866 4867 if (EltIsUndef) 4868 Ops.push_back(DAG.getUNDEF(DstEltVT)); 4869 else 4870 Ops.push_back(DAG.getConstant(NewBits, DstEltVT)); 4871 } 4872 4873 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, Ops.size()); 4874 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 4875 &Ops[0], Ops.size()); 4876 } 4877 4878 // Finally, this must be the case where we are shrinking elements: each input 4879 // turns into multiple outputs. 4880 bool isS2V = ISD::isScalarToVector(BV); 4881 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize; 4882 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, 4883 NumOutputsPerInput*BV->getNumOperands()); 4884 SmallVector<SDValue, 8> Ops; 4885 4886 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 4887 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) { 4888 for (unsigned j = 0; j != NumOutputsPerInput; ++j) 4889 Ops.push_back(DAG.getUNDEF(DstEltVT)); 4890 continue; 4891 } 4892 4893 APInt OpVal = cast<ConstantSDNode>(BV->getOperand(i))-> 4894 getAPIntValue().zextOrTrunc(SrcBitSize); 4895 4896 for (unsigned j = 0; j != NumOutputsPerInput; ++j) { 4897 APInt ThisVal = OpVal.trunc(DstBitSize); 4898 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT)); 4899 if (isS2V && i == 0 && j == 0 && ThisVal.zext(SrcBitSize) == OpVal) 4900 // Simply turn this into a SCALAR_TO_VECTOR of the new type. 4901 return DAG.getNode(ISD::SCALAR_TO_VECTOR, BV->getDebugLoc(), VT, 4902 Ops[0]); 4903 OpVal = OpVal.lshr(DstBitSize); 4904 } 4905 4906 // For big endian targets, swap the order of the pieces of each element. 4907 if (TLI.isBigEndian()) 4908 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end()); 4909 } 4910 4911 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 4912 &Ops[0], Ops.size()); 4913} 4914 4915SDValue DAGCombiner::visitFADD(SDNode *N) { 4916 SDValue N0 = N->getOperand(0); 4917 SDValue N1 = N->getOperand(1); 4918 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4919 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4920 EVT VT = N->getValueType(0); 4921 4922 // fold vector ops 4923 if (VT.isVector()) { 4924 SDValue FoldedVOp = SimplifyVBinOp(N); 4925 if (FoldedVOp.getNode()) return FoldedVOp; 4926 } 4927 4928 // fold (fadd c1, c2) -> (fadd c1, c2) 4929 if (N0CFP && N1CFP && VT != MVT::ppcf128) 4930 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N1); 4931 // canonicalize constant to RHS 4932 if (N0CFP && !N1CFP) 4933 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N1, N0); 4934 // fold (fadd A, 0) -> A 4935 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero()) 4936 return N0; 4937 // fold (fadd A, (fneg B)) -> (fsub A, B) 4938 if (isNegatibleForFree(N1, LegalOperations) == 2) 4939 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, 4940 GetNegatedExpression(N1, DAG, LegalOperations)); 4941 // fold (fadd (fneg A), B) -> (fsub B, A) 4942 if (isNegatibleForFree(N0, LegalOperations) == 2) 4943 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N1, 4944 GetNegatedExpression(N0, DAG, LegalOperations)); 4945 4946 // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2)) 4947 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FADD && 4948 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 4949 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0.getOperand(0), 4950 DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, 4951 N0.getOperand(1), N1)); 4952 4953 return SDValue(); 4954} 4955 4956SDValue DAGCombiner::visitFSUB(SDNode *N) { 4957 SDValue N0 = N->getOperand(0); 4958 SDValue N1 = N->getOperand(1); 4959 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4960 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4961 EVT VT = N->getValueType(0); 4962 4963 // fold vector ops 4964 if (VT.isVector()) { 4965 SDValue FoldedVOp = SimplifyVBinOp(N); 4966 if (FoldedVOp.getNode()) return FoldedVOp; 4967 } 4968 4969 // fold (fsub c1, c2) -> c1-c2 4970 if (N0CFP && N1CFP && VT != MVT::ppcf128) 4971 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, N1); 4972 // fold (fsub A, 0) -> A 4973 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero()) 4974 return N0; 4975 // fold (fsub 0, B) -> -B 4976 if (UnsafeFPMath && N0CFP && N0CFP->getValueAPF().isZero()) { 4977 if (isNegatibleForFree(N1, LegalOperations)) 4978 return GetNegatedExpression(N1, DAG, LegalOperations); 4979 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 4980 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N1); 4981 } 4982 // fold (fsub A, (fneg B)) -> (fadd A, B) 4983 if (isNegatibleForFree(N1, LegalOperations)) 4984 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, 4985 GetNegatedExpression(N1, DAG, LegalOperations)); 4986 4987 return SDValue(); 4988} 4989 4990SDValue DAGCombiner::visitFMUL(SDNode *N) { 4991 SDValue N0 = N->getOperand(0); 4992 SDValue N1 = N->getOperand(1); 4993 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4994 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4995 EVT VT = N->getValueType(0); 4996 4997 // fold vector ops 4998 if (VT.isVector()) { 4999 SDValue FoldedVOp = SimplifyVBinOp(N); 5000 if (FoldedVOp.getNode()) return FoldedVOp; 5001 } 5002 5003 // fold (fmul c1, c2) -> c1*c2 5004 if (N0CFP && N1CFP && VT != MVT::ppcf128) 5005 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0, N1); 5006 // canonicalize constant to RHS 5007 if (N0CFP && !N1CFP) 5008 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N1, N0); 5009 // fold (fmul A, 0) -> 0 5010 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero()) 5011 return N1; 5012 // fold (fmul A, 0) -> 0, vector edition. 5013 if (UnsafeFPMath && ISD::isBuildVectorAllZeros(N1.getNode())) 5014 return N1; 5015 // fold (fmul X, 2.0) -> (fadd X, X) 5016 if (N1CFP && N1CFP->isExactlyValue(+2.0)) 5017 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N0); 5018 // fold (fmul X, -1.0) -> (fneg X) 5019 if (N1CFP && N1CFP->isExactlyValue(-1.0)) 5020 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 5021 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N0); 5022 5023 // fold (fmul (fneg X), (fneg Y)) -> (fmul X, Y) 5024 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations)) { 5025 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations)) { 5026 // Both can be negated for free, check to see if at least one is cheaper 5027 // negated. 5028 if (LHSNeg == 2 || RHSNeg == 2) 5029 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 5030 GetNegatedExpression(N0, DAG, LegalOperations), 5031 GetNegatedExpression(N1, DAG, LegalOperations)); 5032 } 5033 } 5034 5035 // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2)) 5036 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FMUL && 5037 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 5038 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0.getOperand(0), 5039 DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 5040 N0.getOperand(1), N1)); 5041 5042 return SDValue(); 5043} 5044 5045SDValue DAGCombiner::visitFDIV(SDNode *N) { 5046 SDValue N0 = N->getOperand(0); 5047 SDValue N1 = N->getOperand(1); 5048 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5049 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 5050 EVT VT = N->getValueType(0); 5051 5052 // fold vector ops 5053 if (VT.isVector()) { 5054 SDValue FoldedVOp = SimplifyVBinOp(N); 5055 if (FoldedVOp.getNode()) return FoldedVOp; 5056 } 5057 5058 // fold (fdiv c1, c2) -> c1/c2 5059 if (N0CFP && N1CFP && VT != MVT::ppcf128) 5060 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, N0, N1); 5061 5062 5063 // (fdiv (fneg X), (fneg Y)) -> (fdiv X, Y) 5064 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations)) { 5065 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations)) { 5066 // Both can be negated for free, check to see if at least one is cheaper 5067 // negated. 5068 if (LHSNeg == 2 || RHSNeg == 2) 5069 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, 5070 GetNegatedExpression(N0, DAG, LegalOperations), 5071 GetNegatedExpression(N1, DAG, LegalOperations)); 5072 } 5073 } 5074 5075 return SDValue(); 5076} 5077 5078SDValue DAGCombiner::visitFREM(SDNode *N) { 5079 SDValue N0 = N->getOperand(0); 5080 SDValue N1 = N->getOperand(1); 5081 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5082 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 5083 EVT VT = N->getValueType(0); 5084 5085 // fold (frem c1, c2) -> fmod(c1,c2) 5086 if (N0CFP && N1CFP && VT != MVT::ppcf128) 5087 return DAG.getNode(ISD::FREM, N->getDebugLoc(), VT, N0, N1); 5088 5089 return SDValue(); 5090} 5091 5092SDValue DAGCombiner::visitFCOPYSIGN(SDNode *N) { 5093 SDValue N0 = N->getOperand(0); 5094 SDValue N1 = N->getOperand(1); 5095 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5096 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 5097 EVT VT = N->getValueType(0); 5098 5099 if (N0CFP && N1CFP && VT != MVT::ppcf128) // Constant fold 5100 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, N0, N1); 5101 5102 if (N1CFP) { 5103 const APFloat& V = N1CFP->getValueAPF(); 5104 // copysign(x, c1) -> fabs(x) iff ispos(c1) 5105 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1) 5106 if (!V.isNegative()) { 5107 if (!LegalOperations || TLI.isOperationLegal(ISD::FABS, VT)) 5108 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 5109 } else { 5110 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 5111 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, 5112 DAG.getNode(ISD::FABS, N0.getDebugLoc(), VT, N0)); 5113 } 5114 } 5115 5116 // copysign(fabs(x), y) -> copysign(x, y) 5117 // copysign(fneg(x), y) -> copysign(x, y) 5118 // copysign(copysign(x,z), y) -> copysign(x, y) 5119 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG || 5120 N0.getOpcode() == ISD::FCOPYSIGN) 5121 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 5122 N0.getOperand(0), N1); 5123 5124 // copysign(x, abs(y)) -> abs(x) 5125 if (N1.getOpcode() == ISD::FABS) 5126 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 5127 5128 // copysign(x, copysign(y,z)) -> copysign(x, z) 5129 if (N1.getOpcode() == ISD::FCOPYSIGN) 5130 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 5131 N0, N1.getOperand(1)); 5132 5133 // copysign(x, fp_extend(y)) -> copysign(x, y) 5134 // copysign(x, fp_round(y)) -> copysign(x, y) 5135 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND) 5136 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 5137 N0, N1.getOperand(0)); 5138 5139 return SDValue(); 5140} 5141 5142SDValue DAGCombiner::visitSINT_TO_FP(SDNode *N) { 5143 SDValue N0 = N->getOperand(0); 5144 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 5145 EVT VT = N->getValueType(0); 5146 EVT OpVT = N0.getValueType(); 5147 5148 // fold (sint_to_fp c1) -> c1fp 5149 if (N0C && OpVT != MVT::ppcf128 && 5150 // ...but only if the target supports immediate floating-point values 5151 (Level == llvm::Unrestricted || TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT))) 5152 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0); 5153 5154 // If the input is a legal type, and SINT_TO_FP is not legal on this target, 5155 // but UINT_TO_FP is legal on this target, try to convert. 5156 if (!TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT) && 5157 TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT)) { 5158 // If the sign bit is known to be zero, we can change this to UINT_TO_FP. 5159 if (DAG.SignBitIsZero(N0)) 5160 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0); 5161 } 5162 5163 return SDValue(); 5164} 5165 5166SDValue DAGCombiner::visitUINT_TO_FP(SDNode *N) { 5167 SDValue N0 = N->getOperand(0); 5168 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 5169 EVT VT = N->getValueType(0); 5170 EVT OpVT = N0.getValueType(); 5171 5172 // fold (uint_to_fp c1) -> c1fp 5173 if (N0C && OpVT != MVT::ppcf128 && 5174 // ...but only if the target supports immediate floating-point values 5175 (Level == llvm::Unrestricted || TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT))) 5176 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0); 5177 5178 // If the input is a legal type, and UINT_TO_FP is not legal on this target, 5179 // but SINT_TO_FP is legal on this target, try to convert. 5180 if (!TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT) && 5181 TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT)) { 5182 // If the sign bit is known to be zero, we can change this to SINT_TO_FP. 5183 if (DAG.SignBitIsZero(N0)) 5184 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0); 5185 } 5186 5187 return SDValue(); 5188} 5189 5190SDValue DAGCombiner::visitFP_TO_SINT(SDNode *N) { 5191 SDValue N0 = N->getOperand(0); 5192 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5193 EVT VT = N->getValueType(0); 5194 5195 // fold (fp_to_sint c1fp) -> c1 5196 if (N0CFP) 5197 return DAG.getNode(ISD::FP_TO_SINT, N->getDebugLoc(), VT, N0); 5198 5199 return SDValue(); 5200} 5201 5202SDValue DAGCombiner::visitFP_TO_UINT(SDNode *N) { 5203 SDValue N0 = N->getOperand(0); 5204 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5205 EVT VT = N->getValueType(0); 5206 5207 // fold (fp_to_uint c1fp) -> c1 5208 if (N0CFP && VT != MVT::ppcf128) 5209 return DAG.getNode(ISD::FP_TO_UINT, N->getDebugLoc(), VT, N0); 5210 5211 return SDValue(); 5212} 5213 5214SDValue DAGCombiner::visitFP_ROUND(SDNode *N) { 5215 SDValue N0 = N->getOperand(0); 5216 SDValue N1 = N->getOperand(1); 5217 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5218 EVT VT = N->getValueType(0); 5219 5220 // fold (fp_round c1fp) -> c1fp 5221 if (N0CFP && N0.getValueType() != MVT::ppcf128) 5222 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0, N1); 5223 5224 // fold (fp_round (fp_extend x)) -> x 5225 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType()) 5226 return N0.getOperand(0); 5227 5228 // fold (fp_round (fp_round x)) -> (fp_round x) 5229 if (N0.getOpcode() == ISD::FP_ROUND) { 5230 // This is a value preserving truncation if both round's are. 5231 bool IsTrunc = N->getConstantOperandVal(1) == 1 && 5232 N0.getNode()->getConstantOperandVal(1) == 1; 5233 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0.getOperand(0), 5234 DAG.getIntPtrConstant(IsTrunc)); 5235 } 5236 5237 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y) 5238 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse()) { 5239 SDValue Tmp = DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(), VT, 5240 N0.getOperand(0), N1); 5241 AddToWorkList(Tmp.getNode()); 5242 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 5243 Tmp, N0.getOperand(1)); 5244 } 5245 5246 return SDValue(); 5247} 5248 5249SDValue DAGCombiner::visitFP_ROUND_INREG(SDNode *N) { 5250 SDValue N0 = N->getOperand(0); 5251 EVT VT = N->getValueType(0); 5252 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 5253 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5254 5255 // fold (fp_round_inreg c1fp) -> c1fp 5256 if (N0CFP && isTypeLegal(EVT)) { 5257 SDValue Round = DAG.getConstantFP(*N0CFP->getConstantFPValue(), EVT); 5258 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, Round); 5259 } 5260 5261 return SDValue(); 5262} 5263 5264SDValue DAGCombiner::visitFP_EXTEND(SDNode *N) { 5265 SDValue N0 = N->getOperand(0); 5266 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5267 EVT VT = N->getValueType(0); 5268 5269 // If this is fp_round(fpextend), don't fold it, allow ourselves to be folded. 5270 if (N->hasOneUse() && 5271 N->use_begin()->getOpcode() == ISD::FP_ROUND) 5272 return SDValue(); 5273 5274 // fold (fp_extend c1fp) -> c1fp 5275 if (N0CFP && VT != MVT::ppcf128) 5276 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, N0); 5277 5278 // Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't affect the 5279 // value of X. 5280 if (N0.getOpcode() == ISD::FP_ROUND 5281 && N0.getNode()->getConstantOperandVal(1) == 1) { 5282 SDValue In = N0.getOperand(0); 5283 if (In.getValueType() == VT) return In; 5284 if (VT.bitsLT(In.getValueType())) 5285 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, 5286 In, N0.getOperand(1)); 5287 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, In); 5288 } 5289 5290 // fold (fpext (load x)) -> (fpext (fptrunc (extload x))) 5291 if (ISD::isNON_EXTLoad(N0.getNode()) && N0.hasOneUse() && 5292 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 5293 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) { 5294 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 5295 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT, 5296 LN0->getChain(), 5297 LN0->getBasePtr(), LN0->getPointerInfo(), 5298 N0.getValueType(), 5299 LN0->isVolatile(), LN0->isNonTemporal(), 5300 LN0->getAlignment()); 5301 CombineTo(N, ExtLoad); 5302 CombineTo(N0.getNode(), 5303 DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(), 5304 N0.getValueType(), ExtLoad, DAG.getIntPtrConstant(1)), 5305 ExtLoad.getValue(1)); 5306 return SDValue(N, 0); // Return N so it doesn't get rechecked! 5307 } 5308 5309 return SDValue(); 5310} 5311 5312SDValue DAGCombiner::visitFNEG(SDNode *N) { 5313 SDValue N0 = N->getOperand(0); 5314 EVT VT = N->getValueType(0); 5315 5316 if (isNegatibleForFree(N0, LegalOperations)) 5317 return GetNegatedExpression(N0, DAG, LegalOperations); 5318 5319 // Transform fneg(bitconvert(x)) -> bitconvert(x^sign) to avoid loading 5320 // constant pool values. 5321 if (N0.getOpcode() == ISD::BITCAST && 5322 !VT.isVector() && 5323 N0.getNode()->hasOneUse() && 5324 N0.getOperand(0).getValueType().isInteger()) { 5325 SDValue Int = N0.getOperand(0); 5326 EVT IntVT = Int.getValueType(); 5327 if (IntVT.isInteger() && !IntVT.isVector()) { 5328 Int = DAG.getNode(ISD::XOR, N0.getDebugLoc(), IntVT, Int, 5329 DAG.getConstant(APInt::getSignBit(IntVT.getSizeInBits()), IntVT)); 5330 AddToWorkList(Int.getNode()); 5331 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), 5332 VT, Int); 5333 } 5334 } 5335 5336 return SDValue(); 5337} 5338 5339SDValue DAGCombiner::visitFABS(SDNode *N) { 5340 SDValue N0 = N->getOperand(0); 5341 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5342 EVT VT = N->getValueType(0); 5343 5344 // fold (fabs c1) -> fabs(c1) 5345 if (N0CFP && VT != MVT::ppcf128) 5346 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 5347 // fold (fabs (fabs x)) -> (fabs x) 5348 if (N0.getOpcode() == ISD::FABS) 5349 return N->getOperand(0); 5350 // fold (fabs (fneg x)) -> (fabs x) 5351 // fold (fabs (fcopysign x, y)) -> (fabs x) 5352 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN) 5353 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0.getOperand(0)); 5354 5355 // Transform fabs(bitconvert(x)) -> bitconvert(x&~sign) to avoid loading 5356 // constant pool values. 5357 if (N0.getOpcode() == ISD::BITCAST && N0.getNode()->hasOneUse() && 5358 N0.getOperand(0).getValueType().isInteger() && 5359 !N0.getOperand(0).getValueType().isVector()) { 5360 SDValue Int = N0.getOperand(0); 5361 EVT IntVT = Int.getValueType(); 5362 if (IntVT.isInteger() && !IntVT.isVector()) { 5363 Int = DAG.getNode(ISD::AND, N0.getDebugLoc(), IntVT, Int, 5364 DAG.getConstant(~APInt::getSignBit(IntVT.getSizeInBits()), IntVT)); 5365 AddToWorkList(Int.getNode()); 5366 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), 5367 N->getValueType(0), Int); 5368 } 5369 } 5370 5371 return SDValue(); 5372} 5373 5374SDValue DAGCombiner::visitBRCOND(SDNode *N) { 5375 SDValue Chain = N->getOperand(0); 5376 SDValue N1 = N->getOperand(1); 5377 SDValue N2 = N->getOperand(2); 5378 5379 // If N is a constant we could fold this into a fallthrough or unconditional 5380 // branch. However that doesn't happen very often in normal code, because 5381 // Instcombine/SimplifyCFG should have handled the available opportunities. 5382 // If we did this folding here, it would be necessary to update the 5383 // MachineBasicBlock CFG, which is awkward. 5384 5385 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal 5386 // on the target. 5387 if (N1.getOpcode() == ISD::SETCC && 5388 TLI.isOperationLegalOrCustom(ISD::BR_CC, MVT::Other)) { 5389 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other, 5390 Chain, N1.getOperand(2), 5391 N1.getOperand(0), N1.getOperand(1), N2); 5392 } 5393 5394 if ((N1.hasOneUse() && N1.getOpcode() == ISD::SRL) || 5395 ((N1.getOpcode() == ISD::TRUNCATE && N1.hasOneUse()) && 5396 (N1.getOperand(0).hasOneUse() && 5397 N1.getOperand(0).getOpcode() == ISD::SRL))) { 5398 SDNode *Trunc = 0; 5399 if (N1.getOpcode() == ISD::TRUNCATE) { 5400 // Look pass the truncate. 5401 Trunc = N1.getNode(); 5402 N1 = N1.getOperand(0); 5403 } 5404 5405 // Match this pattern so that we can generate simpler code: 5406 // 5407 // %a = ... 5408 // %b = and i32 %a, 2 5409 // %c = srl i32 %b, 1 5410 // brcond i32 %c ... 5411 // 5412 // into 5413 // 5414 // %a = ... 5415 // %b = and i32 %a, 2 5416 // %c = setcc eq %b, 0 5417 // brcond %c ... 5418 // 5419 // This applies only when the AND constant value has one bit set and the 5420 // SRL constant is equal to the log2 of the AND constant. The back-end is 5421 // smart enough to convert the result into a TEST/JMP sequence. 5422 SDValue Op0 = N1.getOperand(0); 5423 SDValue Op1 = N1.getOperand(1); 5424 5425 if (Op0.getOpcode() == ISD::AND && 5426 Op1.getOpcode() == ISD::Constant) { 5427 SDValue AndOp1 = Op0.getOperand(1); 5428 5429 if (AndOp1.getOpcode() == ISD::Constant) { 5430 const APInt &AndConst = cast<ConstantSDNode>(AndOp1)->getAPIntValue(); 5431 5432 if (AndConst.isPowerOf2() && 5433 cast<ConstantSDNode>(Op1)->getAPIntValue()==AndConst.logBase2()) { 5434 SDValue SetCC = 5435 DAG.getSetCC(N->getDebugLoc(), 5436 TLI.getSetCCResultType(Op0.getValueType()), 5437 Op0, DAG.getConstant(0, Op0.getValueType()), 5438 ISD::SETNE); 5439 5440 SDValue NewBRCond = DAG.getNode(ISD::BRCOND, N->getDebugLoc(), 5441 MVT::Other, Chain, SetCC, N2); 5442 // Don't add the new BRCond into the worklist or else SimplifySelectCC 5443 // will convert it back to (X & C1) >> C2. 5444 CombineTo(N, NewBRCond, false); 5445 // Truncate is dead. 5446 if (Trunc) { 5447 removeFromWorkList(Trunc); 5448 DAG.DeleteNode(Trunc); 5449 } 5450 // Replace the uses of SRL with SETCC 5451 WorkListRemover DeadNodes(*this); 5452 DAG.ReplaceAllUsesOfValueWith(N1, SetCC, &DeadNodes); 5453 removeFromWorkList(N1.getNode()); 5454 DAG.DeleteNode(N1.getNode()); 5455 return SDValue(N, 0); // Return N so it doesn't get rechecked! 5456 } 5457 } 5458 } 5459 5460 if (Trunc) 5461 // Restore N1 if the above transformation doesn't match. 5462 N1 = N->getOperand(1); 5463 } 5464 5465 // Transform br(xor(x, y)) -> br(x != y) 5466 // Transform br(xor(xor(x,y), 1)) -> br (x == y) 5467 if (N1.hasOneUse() && N1.getOpcode() == ISD::XOR) { 5468 SDNode *TheXor = N1.getNode(); 5469 SDValue Op0 = TheXor->getOperand(0); 5470 SDValue Op1 = TheXor->getOperand(1); 5471 if (Op0.getOpcode() == Op1.getOpcode()) { 5472 // Avoid missing important xor optimizations. 5473 SDValue Tmp = visitXOR(TheXor); 5474 if (Tmp.getNode() && Tmp.getNode() != TheXor) { 5475 DEBUG(dbgs() << "\nReplacing.8 "; 5476 TheXor->dump(&DAG); 5477 dbgs() << "\nWith: "; 5478 Tmp.getNode()->dump(&DAG); 5479 dbgs() << '\n'); 5480 WorkListRemover DeadNodes(*this); 5481 DAG.ReplaceAllUsesOfValueWith(N1, Tmp, &DeadNodes); 5482 removeFromWorkList(TheXor); 5483 DAG.DeleteNode(TheXor); 5484 return DAG.getNode(ISD::BRCOND, N->getDebugLoc(), 5485 MVT::Other, Chain, Tmp, N2); 5486 } 5487 } 5488 5489 if (Op0.getOpcode() != ISD::SETCC && Op1.getOpcode() != ISD::SETCC) { 5490 bool Equal = false; 5491 if (ConstantSDNode *RHSCI = dyn_cast<ConstantSDNode>(Op0)) 5492 if (RHSCI->getAPIntValue() == 1 && Op0.hasOneUse() && 5493 Op0.getOpcode() == ISD::XOR) { 5494 TheXor = Op0.getNode(); 5495 Equal = true; 5496 } 5497 5498 EVT SetCCVT = N1.getValueType(); 5499 if (LegalTypes) 5500 SetCCVT = TLI.getSetCCResultType(SetCCVT); 5501 SDValue SetCC = DAG.getSetCC(TheXor->getDebugLoc(), 5502 SetCCVT, 5503 Op0, Op1, 5504 Equal ? ISD::SETEQ : ISD::SETNE); 5505 // Replace the uses of XOR with SETCC 5506 WorkListRemover DeadNodes(*this); 5507 DAG.ReplaceAllUsesOfValueWith(N1, SetCC, &DeadNodes); 5508 removeFromWorkList(N1.getNode()); 5509 DAG.DeleteNode(N1.getNode()); 5510 return DAG.getNode(ISD::BRCOND, N->getDebugLoc(), 5511 MVT::Other, Chain, SetCC, N2); 5512 } 5513 } 5514 5515 return SDValue(); 5516} 5517 5518// Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB. 5519// 5520SDValue DAGCombiner::visitBR_CC(SDNode *N) { 5521 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1)); 5522 SDValue CondLHS = N->getOperand(2), CondRHS = N->getOperand(3); 5523 5524 // If N is a constant we could fold this into a fallthrough or unconditional 5525 // branch. However that doesn't happen very often in normal code, because 5526 // Instcombine/SimplifyCFG should have handled the available opportunities. 5527 // If we did this folding here, it would be necessary to update the 5528 // MachineBasicBlock CFG, which is awkward. 5529 5530 // Use SimplifySetCC to simplify SETCC's. 5531 SDValue Simp = SimplifySetCC(TLI.getSetCCResultType(CondLHS.getValueType()), 5532 CondLHS, CondRHS, CC->get(), N->getDebugLoc(), 5533 false); 5534 if (Simp.getNode()) AddToWorkList(Simp.getNode()); 5535 5536 // fold to a simpler setcc 5537 if (Simp.getNode() && Simp.getOpcode() == ISD::SETCC) 5538 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other, 5539 N->getOperand(0), Simp.getOperand(2), 5540 Simp.getOperand(0), Simp.getOperand(1), 5541 N->getOperand(4)); 5542 5543 return SDValue(); 5544} 5545 5546/// CombineToPreIndexedLoadStore - Try turning a load / store into a 5547/// pre-indexed load / store when the base pointer is an add or subtract 5548/// and it has other uses besides the load / store. After the 5549/// transformation, the new indexed load / store has effectively folded 5550/// the add / subtract in and all of its other uses are redirected to the 5551/// new load / store. 5552bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) { 5553 if (!LegalOperations) 5554 return false; 5555 5556 bool isLoad = true; 5557 SDValue Ptr; 5558 EVT VT; 5559 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 5560 if (LD->isIndexed()) 5561 return false; 5562 VT = LD->getMemoryVT(); 5563 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) && 5564 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT)) 5565 return false; 5566 Ptr = LD->getBasePtr(); 5567 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 5568 if (ST->isIndexed()) 5569 return false; 5570 VT = ST->getMemoryVT(); 5571 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) && 5572 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT)) 5573 return false; 5574 Ptr = ST->getBasePtr(); 5575 isLoad = false; 5576 } else { 5577 return false; 5578 } 5579 5580 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail 5581 // out. There is no reason to make this a preinc/predec. 5582 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) || 5583 Ptr.getNode()->hasOneUse()) 5584 return false; 5585 5586 // Ask the target to do addressing mode selection. 5587 SDValue BasePtr; 5588 SDValue Offset; 5589 ISD::MemIndexedMode AM = ISD::UNINDEXED; 5590 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG)) 5591 return false; 5592 // Don't create a indexed load / store with zero offset. 5593 if (isa<ConstantSDNode>(Offset) && 5594 cast<ConstantSDNode>(Offset)->isNullValue()) 5595 return false; 5596 5597 // Try turning it into a pre-indexed load / store except when: 5598 // 1) The new base ptr is a frame index. 5599 // 2) If N is a store and the new base ptr is either the same as or is a 5600 // predecessor of the value being stored. 5601 // 3) Another use of old base ptr is a predecessor of N. If ptr is folded 5602 // that would create a cycle. 5603 // 4) All uses are load / store ops that use it as old base ptr. 5604 5605 // Check #1. Preinc'ing a frame index would require copying the stack pointer 5606 // (plus the implicit offset) to a register to preinc anyway. 5607 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr)) 5608 return false; 5609 5610 // Check #2. 5611 if (!isLoad) { 5612 SDValue Val = cast<StoreSDNode>(N)->getValue(); 5613 if (Val == BasePtr || BasePtr.getNode()->isPredecessorOf(Val.getNode())) 5614 return false; 5615 } 5616 5617 // Now check for #3 and #4. 5618 bool RealUse = false; 5619 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(), 5620 E = Ptr.getNode()->use_end(); I != E; ++I) { 5621 SDNode *Use = *I; 5622 if (Use == N) 5623 continue; 5624 if (Use->isPredecessorOf(N)) 5625 return false; 5626 5627 if (!((Use->getOpcode() == ISD::LOAD && 5628 cast<LoadSDNode>(Use)->getBasePtr() == Ptr) || 5629 (Use->getOpcode() == ISD::STORE && 5630 cast<StoreSDNode>(Use)->getBasePtr() == Ptr))) 5631 RealUse = true; 5632 } 5633 5634 if (!RealUse) 5635 return false; 5636 5637 SDValue Result; 5638 if (isLoad) 5639 Result = DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(), 5640 BasePtr, Offset, AM); 5641 else 5642 Result = DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(), 5643 BasePtr, Offset, AM); 5644 ++PreIndexedNodes; 5645 ++NodesCombined; 5646 DEBUG(dbgs() << "\nReplacing.4 "; 5647 N->dump(&DAG); 5648 dbgs() << "\nWith: "; 5649 Result.getNode()->dump(&DAG); 5650 dbgs() << '\n'); 5651 WorkListRemover DeadNodes(*this); 5652 if (isLoad) { 5653 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0), 5654 &DeadNodes); 5655 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2), 5656 &DeadNodes); 5657 } else { 5658 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1), 5659 &DeadNodes); 5660 } 5661 5662 // Finally, since the node is now dead, remove it from the graph. 5663 DAG.DeleteNode(N); 5664 5665 // Replace the uses of Ptr with uses of the updated base value. 5666 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0), 5667 &DeadNodes); 5668 removeFromWorkList(Ptr.getNode()); 5669 DAG.DeleteNode(Ptr.getNode()); 5670 5671 return true; 5672} 5673 5674/// CombineToPostIndexedLoadStore - Try to combine a load / store with a 5675/// add / sub of the base pointer node into a post-indexed load / store. 5676/// The transformation folded the add / subtract into the new indexed 5677/// load / store effectively and all of its uses are redirected to the 5678/// new load / store. 5679bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) { 5680 if (!LegalOperations) 5681 return false; 5682 5683 bool isLoad = true; 5684 SDValue Ptr; 5685 EVT VT; 5686 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 5687 if (LD->isIndexed()) 5688 return false; 5689 VT = LD->getMemoryVT(); 5690 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) && 5691 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT)) 5692 return false; 5693 Ptr = LD->getBasePtr(); 5694 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 5695 if (ST->isIndexed()) 5696 return false; 5697 VT = ST->getMemoryVT(); 5698 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) && 5699 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT)) 5700 return false; 5701 Ptr = ST->getBasePtr(); 5702 isLoad = false; 5703 } else { 5704 return false; 5705 } 5706 5707 if (Ptr.getNode()->hasOneUse()) 5708 return false; 5709 5710 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(), 5711 E = Ptr.getNode()->use_end(); I != E; ++I) { 5712 SDNode *Op = *I; 5713 if (Op == N || 5714 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB)) 5715 continue; 5716 5717 SDValue BasePtr; 5718 SDValue Offset; 5719 ISD::MemIndexedMode AM = ISD::UNINDEXED; 5720 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) { 5721 // Don't create a indexed load / store with zero offset. 5722 if (isa<ConstantSDNode>(Offset) && 5723 cast<ConstantSDNode>(Offset)->isNullValue()) 5724 continue; 5725 5726 // Try turning it into a post-indexed load / store except when 5727 // 1) All uses are load / store ops that use it as base ptr. 5728 // 2) Op must be independent of N, i.e. Op is neither a predecessor 5729 // nor a successor of N. Otherwise, if Op is folded that would 5730 // create a cycle. 5731 5732 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr)) 5733 continue; 5734 5735 // Check for #1. 5736 bool TryNext = false; 5737 for (SDNode::use_iterator II = BasePtr.getNode()->use_begin(), 5738 EE = BasePtr.getNode()->use_end(); II != EE; ++II) { 5739 SDNode *Use = *II; 5740 if (Use == Ptr.getNode()) 5741 continue; 5742 5743 // If all the uses are load / store addresses, then don't do the 5744 // transformation. 5745 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){ 5746 bool RealUse = false; 5747 for (SDNode::use_iterator III = Use->use_begin(), 5748 EEE = Use->use_end(); III != EEE; ++III) { 5749 SDNode *UseUse = *III; 5750 if (!((UseUse->getOpcode() == ISD::LOAD && 5751 cast<LoadSDNode>(UseUse)->getBasePtr().getNode() == Use) || 5752 (UseUse->getOpcode() == ISD::STORE && 5753 cast<StoreSDNode>(UseUse)->getBasePtr().getNode() == Use))) 5754 RealUse = true; 5755 } 5756 5757 if (!RealUse) { 5758 TryNext = true; 5759 break; 5760 } 5761 } 5762 } 5763 5764 if (TryNext) 5765 continue; 5766 5767 // Check for #2 5768 if (!Op->isPredecessorOf(N) && !N->isPredecessorOf(Op)) { 5769 SDValue Result = isLoad 5770 ? DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(), 5771 BasePtr, Offset, AM) 5772 : DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(), 5773 BasePtr, Offset, AM); 5774 ++PostIndexedNodes; 5775 ++NodesCombined; 5776 DEBUG(dbgs() << "\nReplacing.5 "; 5777 N->dump(&DAG); 5778 dbgs() << "\nWith: "; 5779 Result.getNode()->dump(&DAG); 5780 dbgs() << '\n'); 5781 WorkListRemover DeadNodes(*this); 5782 if (isLoad) { 5783 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0), 5784 &DeadNodes); 5785 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2), 5786 &DeadNodes); 5787 } else { 5788 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1), 5789 &DeadNodes); 5790 } 5791 5792 // Finally, since the node is now dead, remove it from the graph. 5793 DAG.DeleteNode(N); 5794 5795 // Replace the uses of Use with uses of the updated base value. 5796 DAG.ReplaceAllUsesOfValueWith(SDValue(Op, 0), 5797 Result.getValue(isLoad ? 1 : 0), 5798 &DeadNodes); 5799 removeFromWorkList(Op); 5800 DAG.DeleteNode(Op); 5801 return true; 5802 } 5803 } 5804 } 5805 5806 return false; 5807} 5808 5809SDValue DAGCombiner::visitLOAD(SDNode *N) { 5810 LoadSDNode *LD = cast<LoadSDNode>(N); 5811 SDValue Chain = LD->getChain(); 5812 SDValue Ptr = LD->getBasePtr(); 5813 5814 // If load is not volatile and there are no uses of the loaded value (and 5815 // the updated indexed value in case of indexed loads), change uses of the 5816 // chain value into uses of the chain input (i.e. delete the dead load). 5817 if (!LD->isVolatile()) { 5818 if (N->getValueType(1) == MVT::Other) { 5819 // Unindexed loads. 5820 if (N->hasNUsesOfValue(0, 0)) { 5821 // It's not safe to use the two value CombineTo variant here. e.g. 5822 // v1, chain2 = load chain1, loc 5823 // v2, chain3 = load chain2, loc 5824 // v3 = add v2, c 5825 // Now we replace use of chain2 with chain1. This makes the second load 5826 // isomorphic to the one we are deleting, and thus makes this load live. 5827 DEBUG(dbgs() << "\nReplacing.6 "; 5828 N->dump(&DAG); 5829 dbgs() << "\nWith chain: "; 5830 Chain.getNode()->dump(&DAG); 5831 dbgs() << "\n"); 5832 WorkListRemover DeadNodes(*this); 5833 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Chain, &DeadNodes); 5834 5835 if (N->use_empty()) { 5836 removeFromWorkList(N); 5837 DAG.DeleteNode(N); 5838 } 5839 5840 return SDValue(N, 0); // Return N so it doesn't get rechecked! 5841 } 5842 } else { 5843 // Indexed loads. 5844 assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?"); 5845 if (N->hasNUsesOfValue(0, 0) && N->hasNUsesOfValue(0, 1)) { 5846 SDValue Undef = DAG.getUNDEF(N->getValueType(0)); 5847 DEBUG(dbgs() << "\nReplacing.7 "; 5848 N->dump(&DAG); 5849 dbgs() << "\nWith: "; 5850 Undef.getNode()->dump(&DAG); 5851 dbgs() << " and 2 other values\n"); 5852 WorkListRemover DeadNodes(*this); 5853 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Undef, &DeadNodes); 5854 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), 5855 DAG.getUNDEF(N->getValueType(1)), 5856 &DeadNodes); 5857 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 2), Chain, &DeadNodes); 5858 removeFromWorkList(N); 5859 DAG.DeleteNode(N); 5860 return SDValue(N, 0); // Return N so it doesn't get rechecked! 5861 } 5862 } 5863 } 5864 5865 // If this load is directly stored, replace the load value with the stored 5866 // value. 5867 // TODO: Handle store large -> read small portion. 5868 // TODO: Handle TRUNCSTORE/LOADEXT 5869 if (ISD::isNormalLoad(N) && !LD->isVolatile()) { 5870 if (ISD::isNON_TRUNCStore(Chain.getNode())) { 5871 StoreSDNode *PrevST = cast<StoreSDNode>(Chain); 5872 if (PrevST->getBasePtr() == Ptr && 5873 PrevST->getValue().getValueType() == N->getValueType(0)) 5874 return CombineTo(N, Chain.getOperand(1), Chain); 5875 } 5876 } 5877 5878 // Try to infer better alignment information than the load already has. 5879 if (OptLevel != CodeGenOpt::None && LD->isUnindexed()) { 5880 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) { 5881 if (Align > LD->getAlignment()) 5882 return DAG.getExtLoad(LD->getExtensionType(), N->getDebugLoc(), 5883 LD->getValueType(0), 5884 Chain, Ptr, LD->getPointerInfo(), 5885 LD->getMemoryVT(), 5886 LD->isVolatile(), LD->isNonTemporal(), Align); 5887 } 5888 } 5889 5890 if (CombinerAA) { 5891 // Walk up chain skipping non-aliasing memory nodes. 5892 SDValue BetterChain = FindBetterChain(N, Chain); 5893 5894 // If there is a better chain. 5895 if (Chain != BetterChain) { 5896 SDValue ReplLoad; 5897 5898 // Replace the chain to void dependency. 5899 if (LD->getExtensionType() == ISD::NON_EXTLOAD) { 5900 ReplLoad = DAG.getLoad(N->getValueType(0), LD->getDebugLoc(), 5901 BetterChain, Ptr, LD->getPointerInfo(), 5902 LD->isVolatile(), LD->isNonTemporal(), 5903 LD->getAlignment()); 5904 } else { 5905 ReplLoad = DAG.getExtLoad(LD->getExtensionType(), LD->getDebugLoc(), 5906 LD->getValueType(0), 5907 BetterChain, Ptr, LD->getPointerInfo(), 5908 LD->getMemoryVT(), 5909 LD->isVolatile(), 5910 LD->isNonTemporal(), 5911 LD->getAlignment()); 5912 } 5913 5914 // Create token factor to keep old chain connected. 5915 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 5916 MVT::Other, Chain, ReplLoad.getValue(1)); 5917 5918 // Make sure the new and old chains are cleaned up. 5919 AddToWorkList(Token.getNode()); 5920 5921 // Replace uses with load result and token factor. Don't add users 5922 // to work list. 5923 return CombineTo(N, ReplLoad.getValue(0), Token, false); 5924 } 5925 } 5926 5927 // Try transforming N to an indexed load. 5928 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 5929 return SDValue(N, 0); 5930 5931 return SDValue(); 5932} 5933 5934/// CheckForMaskedLoad - Check to see if V is (and load (ptr), imm), where the 5935/// load is having specific bytes cleared out. If so, return the byte size 5936/// being masked out and the shift amount. 5937static std::pair<unsigned, unsigned> 5938CheckForMaskedLoad(SDValue V, SDValue Ptr, SDValue Chain) { 5939 std::pair<unsigned, unsigned> Result(0, 0); 5940 5941 // Check for the structure we're looking for. 5942 if (V->getOpcode() != ISD::AND || 5943 !isa<ConstantSDNode>(V->getOperand(1)) || 5944 !ISD::isNormalLoad(V->getOperand(0).getNode())) 5945 return Result; 5946 5947 // Check the chain and pointer. 5948 LoadSDNode *LD = cast<LoadSDNode>(V->getOperand(0)); 5949 if (LD->getBasePtr() != Ptr) return Result; // Not from same pointer. 5950 5951 // The store should be chained directly to the load or be an operand of a 5952 // tokenfactor. 5953 if (LD == Chain.getNode()) 5954 ; // ok. 5955 else if (Chain->getOpcode() != ISD::TokenFactor) 5956 return Result; // Fail. 5957 else { 5958 bool isOk = false; 5959 for (unsigned i = 0, e = Chain->getNumOperands(); i != e; ++i) 5960 if (Chain->getOperand(i).getNode() == LD) { 5961 isOk = true; 5962 break; 5963 } 5964 if (!isOk) return Result; 5965 } 5966 5967 // This only handles simple types. 5968 if (V.getValueType() != MVT::i16 && 5969 V.getValueType() != MVT::i32 && 5970 V.getValueType() != MVT::i64) 5971 return Result; 5972 5973 // Check the constant mask. Invert it so that the bits being masked out are 5974 // 0 and the bits being kept are 1. Use getSExtValue so that leading bits 5975 // follow the sign bit for uniformity. 5976 uint64_t NotMask = ~cast<ConstantSDNode>(V->getOperand(1))->getSExtValue(); 5977 unsigned NotMaskLZ = CountLeadingZeros_64(NotMask); 5978 if (NotMaskLZ & 7) return Result; // Must be multiple of a byte. 5979 unsigned NotMaskTZ = CountTrailingZeros_64(NotMask); 5980 if (NotMaskTZ & 7) return Result; // Must be multiple of a byte. 5981 if (NotMaskLZ == 64) return Result; // All zero mask. 5982 5983 // See if we have a continuous run of bits. If so, we have 0*1+0* 5984 if (CountTrailingOnes_64(NotMask >> NotMaskTZ)+NotMaskTZ+NotMaskLZ != 64) 5985 return Result; 5986 5987 // Adjust NotMaskLZ down to be from the actual size of the int instead of i64. 5988 if (V.getValueType() != MVT::i64 && NotMaskLZ) 5989 NotMaskLZ -= 64-V.getValueSizeInBits(); 5990 5991 unsigned MaskedBytes = (V.getValueSizeInBits()-NotMaskLZ-NotMaskTZ)/8; 5992 switch (MaskedBytes) { 5993 case 1: 5994 case 2: 5995 case 4: break; 5996 default: return Result; // All one mask, or 5-byte mask. 5997 } 5998 5999 // Verify that the first bit starts at a multiple of mask so that the access 6000 // is aligned the same as the access width. 6001 if (NotMaskTZ && NotMaskTZ/8 % MaskedBytes) return Result; 6002 6003 Result.first = MaskedBytes; 6004 Result.second = NotMaskTZ/8; 6005 return Result; 6006} 6007 6008 6009/// ShrinkLoadReplaceStoreWithStore - Check to see if IVal is something that 6010/// provides a value as specified by MaskInfo. If so, replace the specified 6011/// store with a narrower store of truncated IVal. 6012static SDNode * 6013ShrinkLoadReplaceStoreWithStore(const std::pair<unsigned, unsigned> &MaskInfo, 6014 SDValue IVal, StoreSDNode *St, 6015 DAGCombiner *DC) { 6016 unsigned NumBytes = MaskInfo.first; 6017 unsigned ByteShift = MaskInfo.second; 6018 SelectionDAG &DAG = DC->getDAG(); 6019 6020 // Check to see if IVal is all zeros in the part being masked in by the 'or' 6021 // that uses this. If not, this is not a replacement. 6022 APInt Mask = ~APInt::getBitsSet(IVal.getValueSizeInBits(), 6023 ByteShift*8, (ByteShift+NumBytes)*8); 6024 if (!DAG.MaskedValueIsZero(IVal, Mask)) return 0; 6025 6026 // Check that it is legal on the target to do this. It is legal if the new 6027 // VT we're shrinking to (i8/i16/i32) is legal or we're still before type 6028 // legalization. 6029 MVT VT = MVT::getIntegerVT(NumBytes*8); 6030 if (!DC->isTypeLegal(VT)) 6031 return 0; 6032 6033 // Okay, we can do this! Replace the 'St' store with a store of IVal that is 6034 // shifted by ByteShift and truncated down to NumBytes. 6035 if (ByteShift) 6036 IVal = DAG.getNode(ISD::SRL, IVal->getDebugLoc(), IVal.getValueType(), IVal, 6037 DAG.getConstant(ByteShift*8, 6038 DC->getShiftAmountTy(IVal.getValueType()))); 6039 6040 // Figure out the offset for the store and the alignment of the access. 6041 unsigned StOffset; 6042 unsigned NewAlign = St->getAlignment(); 6043 6044 if (DAG.getTargetLoweringInfo().isLittleEndian()) 6045 StOffset = ByteShift; 6046 else 6047 StOffset = IVal.getValueType().getStoreSize() - ByteShift - NumBytes; 6048 6049 SDValue Ptr = St->getBasePtr(); 6050 if (StOffset) { 6051 Ptr = DAG.getNode(ISD::ADD, IVal->getDebugLoc(), Ptr.getValueType(), 6052 Ptr, DAG.getConstant(StOffset, Ptr.getValueType())); 6053 NewAlign = MinAlign(NewAlign, StOffset); 6054 } 6055 6056 // Truncate down to the new size. 6057 IVal = DAG.getNode(ISD::TRUNCATE, IVal->getDebugLoc(), VT, IVal); 6058 6059 ++OpsNarrowed; 6060 return DAG.getStore(St->getChain(), St->getDebugLoc(), IVal, Ptr, 6061 St->getPointerInfo().getWithOffset(StOffset), 6062 false, false, NewAlign).getNode(); 6063} 6064 6065 6066/// ReduceLoadOpStoreWidth - Look for sequence of load / op / store where op is 6067/// one of 'or', 'xor', and 'and' of immediates. If 'op' is only touching some 6068/// of the loaded bits, try narrowing the load and store if it would end up 6069/// being a win for performance or code size. 6070SDValue DAGCombiner::ReduceLoadOpStoreWidth(SDNode *N) { 6071 StoreSDNode *ST = cast<StoreSDNode>(N); 6072 if (ST->isVolatile()) 6073 return SDValue(); 6074 6075 SDValue Chain = ST->getChain(); 6076 SDValue Value = ST->getValue(); 6077 SDValue Ptr = ST->getBasePtr(); 6078 EVT VT = Value.getValueType(); 6079 6080 if (ST->isTruncatingStore() || VT.isVector() || !Value.hasOneUse()) 6081 return SDValue(); 6082 6083 unsigned Opc = Value.getOpcode(); 6084 6085 // If this is "store (or X, Y), P" and X is "(and (load P), cst)", where cst 6086 // is a byte mask indicating a consecutive number of bytes, check to see if 6087 // Y is known to provide just those bytes. If so, we try to replace the 6088 // load + replace + store sequence with a single (narrower) store, which makes 6089 // the load dead. 6090 if (Opc == ISD::OR) { 6091 std::pair<unsigned, unsigned> MaskedLoad; 6092 MaskedLoad = CheckForMaskedLoad(Value.getOperand(0), Ptr, Chain); 6093 if (MaskedLoad.first) 6094 if (SDNode *NewST = ShrinkLoadReplaceStoreWithStore(MaskedLoad, 6095 Value.getOperand(1), ST,this)) 6096 return SDValue(NewST, 0); 6097 6098 // Or is commutative, so try swapping X and Y. 6099 MaskedLoad = CheckForMaskedLoad(Value.getOperand(1), Ptr, Chain); 6100 if (MaskedLoad.first) 6101 if (SDNode *NewST = ShrinkLoadReplaceStoreWithStore(MaskedLoad, 6102 Value.getOperand(0), ST,this)) 6103 return SDValue(NewST, 0); 6104 } 6105 6106 if ((Opc != ISD::OR && Opc != ISD::XOR && Opc != ISD::AND) || 6107 Value.getOperand(1).getOpcode() != ISD::Constant) 6108 return SDValue(); 6109 6110 SDValue N0 = Value.getOperand(0); 6111 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() && 6112 Chain == SDValue(N0.getNode(), 1)) { 6113 LoadSDNode *LD = cast<LoadSDNode>(N0); 6114 if (LD->getBasePtr() != Ptr || 6115 LD->getPointerInfo().getAddrSpace() != 6116 ST->getPointerInfo().getAddrSpace()) 6117 return SDValue(); 6118 6119 // Find the type to narrow it the load / op / store to. 6120 SDValue N1 = Value.getOperand(1); 6121 unsigned BitWidth = N1.getValueSizeInBits(); 6122 APInt Imm = cast<ConstantSDNode>(N1)->getAPIntValue(); 6123 if (Opc == ISD::AND) 6124 Imm ^= APInt::getAllOnesValue(BitWidth); 6125 if (Imm == 0 || Imm.isAllOnesValue()) 6126 return SDValue(); 6127 unsigned ShAmt = Imm.countTrailingZeros(); 6128 unsigned MSB = BitWidth - Imm.countLeadingZeros() - 1; 6129 unsigned NewBW = NextPowerOf2(MSB - ShAmt); 6130 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW); 6131 while (NewBW < BitWidth && 6132 !(TLI.isOperationLegalOrCustom(Opc, NewVT) && 6133 TLI.isNarrowingProfitable(VT, NewVT))) { 6134 NewBW = NextPowerOf2(NewBW); 6135 NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW); 6136 } 6137 if (NewBW >= BitWidth) 6138 return SDValue(); 6139 6140 // If the lsb changed does not start at the type bitwidth boundary, 6141 // start at the previous one. 6142 if (ShAmt % NewBW) 6143 ShAmt = (((ShAmt + NewBW - 1) / NewBW) * NewBW) - NewBW; 6144 APInt Mask = APInt::getBitsSet(BitWidth, ShAmt, ShAmt + NewBW); 6145 if ((Imm & Mask) == Imm) { 6146 APInt NewImm = (Imm & Mask).lshr(ShAmt).trunc(NewBW); 6147 if (Opc == ISD::AND) 6148 NewImm ^= APInt::getAllOnesValue(NewBW); 6149 uint64_t PtrOff = ShAmt / 8; 6150 // For big endian targets, we need to adjust the offset to the pointer to 6151 // load the correct bytes. 6152 if (TLI.isBigEndian()) 6153 PtrOff = (BitWidth + 7 - NewBW) / 8 - PtrOff; 6154 6155 unsigned NewAlign = MinAlign(LD->getAlignment(), PtrOff); 6156 const Type *NewVTTy = NewVT.getTypeForEVT(*DAG.getContext()); 6157 if (NewAlign < TLI.getTargetData()->getABITypeAlignment(NewVTTy)) 6158 return SDValue(); 6159 6160 SDValue NewPtr = DAG.getNode(ISD::ADD, LD->getDebugLoc(), 6161 Ptr.getValueType(), Ptr, 6162 DAG.getConstant(PtrOff, Ptr.getValueType())); 6163 SDValue NewLD = DAG.getLoad(NewVT, N0.getDebugLoc(), 6164 LD->getChain(), NewPtr, 6165 LD->getPointerInfo().getWithOffset(PtrOff), 6166 LD->isVolatile(), LD->isNonTemporal(), 6167 NewAlign); 6168 SDValue NewVal = DAG.getNode(Opc, Value.getDebugLoc(), NewVT, NewLD, 6169 DAG.getConstant(NewImm, NewVT)); 6170 SDValue NewST = DAG.getStore(Chain, N->getDebugLoc(), 6171 NewVal, NewPtr, 6172 ST->getPointerInfo().getWithOffset(PtrOff), 6173 false, false, NewAlign); 6174 6175 AddToWorkList(NewPtr.getNode()); 6176 AddToWorkList(NewLD.getNode()); 6177 AddToWorkList(NewVal.getNode()); 6178 WorkListRemover DeadNodes(*this); 6179 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), NewLD.getValue(1), 6180 &DeadNodes); 6181 ++OpsNarrowed; 6182 return NewST; 6183 } 6184 } 6185 6186 return SDValue(); 6187} 6188 6189/// TransformFPLoadStorePair - For a given floating point load / store pair, 6190/// if the load value isn't used by any other operations, then consider 6191/// transforming the pair to integer load / store operations if the target 6192/// deems the transformation profitable. 6193SDValue DAGCombiner::TransformFPLoadStorePair(SDNode *N) { 6194 StoreSDNode *ST = cast<StoreSDNode>(N); 6195 SDValue Chain = ST->getChain(); 6196 SDValue Value = ST->getValue(); 6197 if (ISD::isNormalStore(ST) && ISD::isNormalLoad(Value.getNode()) && 6198 Value.hasOneUse() && 6199 Chain == SDValue(Value.getNode(), 1)) { 6200 LoadSDNode *LD = cast<LoadSDNode>(Value); 6201 EVT VT = LD->getMemoryVT(); 6202 if (!VT.isFloatingPoint() || 6203 VT != ST->getMemoryVT() || 6204 LD->isNonTemporal() || 6205 ST->isNonTemporal() || 6206 LD->getPointerInfo().getAddrSpace() != 0 || 6207 ST->getPointerInfo().getAddrSpace() != 0) 6208 return SDValue(); 6209 6210 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits()); 6211 if (!TLI.isOperationLegal(ISD::LOAD, IntVT) || 6212 !TLI.isOperationLegal(ISD::STORE, IntVT) || 6213 !TLI.isDesirableToTransformToIntegerOp(ISD::LOAD, VT) || 6214 !TLI.isDesirableToTransformToIntegerOp(ISD::STORE, VT)) 6215 return SDValue(); 6216 6217 unsigned LDAlign = LD->getAlignment(); 6218 unsigned STAlign = ST->getAlignment(); 6219 const Type *IntVTTy = IntVT.getTypeForEVT(*DAG.getContext()); 6220 unsigned ABIAlign = TLI.getTargetData()->getABITypeAlignment(IntVTTy); 6221 if (LDAlign < ABIAlign || STAlign < ABIAlign) 6222 return SDValue(); 6223 6224 SDValue NewLD = DAG.getLoad(IntVT, Value.getDebugLoc(), 6225 LD->getChain(), LD->getBasePtr(), 6226 LD->getPointerInfo(), 6227 false, false, LDAlign); 6228 6229 SDValue NewST = DAG.getStore(NewLD.getValue(1), N->getDebugLoc(), 6230 NewLD, ST->getBasePtr(), 6231 ST->getPointerInfo(), 6232 false, false, STAlign); 6233 6234 AddToWorkList(NewLD.getNode()); 6235 AddToWorkList(NewST.getNode()); 6236 WorkListRemover DeadNodes(*this); 6237 DAG.ReplaceAllUsesOfValueWith(Value.getValue(1), NewLD.getValue(1), 6238 &DeadNodes); 6239 ++LdStFP2Int; 6240 return NewST; 6241 } 6242 6243 return SDValue(); 6244} 6245 6246SDValue DAGCombiner::visitSTORE(SDNode *N) { 6247 StoreSDNode *ST = cast<StoreSDNode>(N); 6248 SDValue Chain = ST->getChain(); 6249 SDValue Value = ST->getValue(); 6250 SDValue Ptr = ST->getBasePtr(); 6251 6252 // If this is a store of a bit convert, store the input value if the 6253 // resultant store does not need a higher alignment than the original. 6254 if (Value.getOpcode() == ISD::BITCAST && !ST->isTruncatingStore() && 6255 ST->isUnindexed()) { 6256 unsigned OrigAlign = ST->getAlignment(); 6257 EVT SVT = Value.getOperand(0).getValueType(); 6258 unsigned Align = TLI.getTargetData()-> 6259 getABITypeAlignment(SVT.getTypeForEVT(*DAG.getContext())); 6260 if (Align <= OrigAlign && 6261 ((!LegalOperations && !ST->isVolatile()) || 6262 TLI.isOperationLegalOrCustom(ISD::STORE, SVT))) 6263 return DAG.getStore(Chain, N->getDebugLoc(), Value.getOperand(0), 6264 Ptr, ST->getPointerInfo(), ST->isVolatile(), 6265 ST->isNonTemporal(), OrigAlign); 6266 } 6267 6268 // Turn 'store undef, Ptr' -> nothing. 6269 if (Value.getOpcode() == ISD::UNDEF && ST->isUnindexed()) 6270 return Chain; 6271 6272 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 6273 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) { 6274 // NOTE: If the original store is volatile, this transform must not increase 6275 // the number of stores. For example, on x86-32 an f64 can be stored in one 6276 // processor operation but an i64 (which is not legal) requires two. So the 6277 // transform should not be done in this case. 6278 if (Value.getOpcode() != ISD::TargetConstantFP) { 6279 SDValue Tmp; 6280 switch (CFP->getValueType(0).getSimpleVT().SimpleTy) { 6281 default: llvm_unreachable("Unknown FP type"); 6282 case MVT::f80: // We don't do this for these yet. 6283 case MVT::f128: 6284 case MVT::ppcf128: 6285 break; 6286 case MVT::f32: 6287 if ((isTypeLegal(MVT::i32) && !LegalOperations && !ST->isVolatile()) || 6288 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) { 6289 Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF(). 6290 bitcastToAPInt().getZExtValue(), MVT::i32); 6291 return DAG.getStore(Chain, N->getDebugLoc(), Tmp, 6292 Ptr, ST->getPointerInfo(), ST->isVolatile(), 6293 ST->isNonTemporal(), ST->getAlignment()); 6294 } 6295 break; 6296 case MVT::f64: 6297 if ((TLI.isTypeLegal(MVT::i64) && !LegalOperations && 6298 !ST->isVolatile()) || 6299 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i64)) { 6300 Tmp = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt(). 6301 getZExtValue(), MVT::i64); 6302 return DAG.getStore(Chain, N->getDebugLoc(), Tmp, 6303 Ptr, ST->getPointerInfo(), ST->isVolatile(), 6304 ST->isNonTemporal(), ST->getAlignment()); 6305 } 6306 6307 if (!ST->isVolatile() && 6308 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) { 6309 // Many FP stores are not made apparent until after legalize, e.g. for 6310 // argument passing. Since this is so common, custom legalize the 6311 // 64-bit integer store into two 32-bit stores. 6312 uint64_t Val = CFP->getValueAPF().bitcastToAPInt().getZExtValue(); 6313 SDValue Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32); 6314 SDValue Hi = DAG.getConstant(Val >> 32, MVT::i32); 6315 if (TLI.isBigEndian()) std::swap(Lo, Hi); 6316 6317 unsigned Alignment = ST->getAlignment(); 6318 bool isVolatile = ST->isVolatile(); 6319 bool isNonTemporal = ST->isNonTemporal(); 6320 6321 SDValue St0 = DAG.getStore(Chain, ST->getDebugLoc(), Lo, 6322 Ptr, ST->getPointerInfo(), 6323 isVolatile, isNonTemporal, 6324 ST->getAlignment()); 6325 Ptr = DAG.getNode(ISD::ADD, N->getDebugLoc(), Ptr.getValueType(), Ptr, 6326 DAG.getConstant(4, Ptr.getValueType())); 6327 Alignment = MinAlign(Alignment, 4U); 6328 SDValue St1 = DAG.getStore(Chain, ST->getDebugLoc(), Hi, 6329 Ptr, ST->getPointerInfo().getWithOffset(4), 6330 isVolatile, isNonTemporal, 6331 Alignment); 6332 return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, 6333 St0, St1); 6334 } 6335 6336 break; 6337 } 6338 } 6339 } 6340 6341 // Try to infer better alignment information than the store already has. 6342 if (OptLevel != CodeGenOpt::None && ST->isUnindexed()) { 6343 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) { 6344 if (Align > ST->getAlignment()) 6345 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value, 6346 Ptr, ST->getPointerInfo(), ST->getMemoryVT(), 6347 ST->isVolatile(), ST->isNonTemporal(), Align); 6348 } 6349 } 6350 6351 // Try transforming a pair floating point load / store ops to integer 6352 // load / store ops. 6353 SDValue NewST = TransformFPLoadStorePair(N); 6354 if (NewST.getNode()) 6355 return NewST; 6356 6357 if (CombinerAA) { 6358 // Walk up chain skipping non-aliasing memory nodes. 6359 SDValue BetterChain = FindBetterChain(N, Chain); 6360 6361 // If there is a better chain. 6362 if (Chain != BetterChain) { 6363 SDValue ReplStore; 6364 6365 // Replace the chain to avoid dependency. 6366 if (ST->isTruncatingStore()) { 6367 ReplStore = DAG.getTruncStore(BetterChain, N->getDebugLoc(), Value, Ptr, 6368 ST->getPointerInfo(), 6369 ST->getMemoryVT(), ST->isVolatile(), 6370 ST->isNonTemporal(), ST->getAlignment()); 6371 } else { 6372 ReplStore = DAG.getStore(BetterChain, N->getDebugLoc(), Value, Ptr, 6373 ST->getPointerInfo(), 6374 ST->isVolatile(), ST->isNonTemporal(), 6375 ST->getAlignment()); 6376 } 6377 6378 // Create token to keep both nodes around. 6379 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 6380 MVT::Other, Chain, ReplStore); 6381 6382 // Make sure the new and old chains are cleaned up. 6383 AddToWorkList(Token.getNode()); 6384 6385 // Don't add users to work list. 6386 return CombineTo(N, Token, false); 6387 } 6388 } 6389 6390 // Try transforming N to an indexed store. 6391 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 6392 return SDValue(N, 0); 6393 6394 // FIXME: is there such a thing as a truncating indexed store? 6395 if (ST->isTruncatingStore() && ST->isUnindexed() && 6396 Value.getValueType().isInteger()) { 6397 // See if we can simplify the input to this truncstore with knowledge that 6398 // only the low bits are being used. For example: 6399 // "truncstore (or (shl x, 8), y), i8" -> "truncstore y, i8" 6400 SDValue Shorter = 6401 GetDemandedBits(Value, 6402 APInt::getLowBitsSet(Value.getValueSizeInBits(), 6403 ST->getMemoryVT().getSizeInBits())); 6404 AddToWorkList(Value.getNode()); 6405 if (Shorter.getNode()) 6406 return DAG.getTruncStore(Chain, N->getDebugLoc(), Shorter, 6407 Ptr, ST->getPointerInfo(), ST->getMemoryVT(), 6408 ST->isVolatile(), ST->isNonTemporal(), 6409 ST->getAlignment()); 6410 6411 // Otherwise, see if we can simplify the operation with 6412 // SimplifyDemandedBits, which only works if the value has a single use. 6413 if (SimplifyDemandedBits(Value, 6414 APInt::getLowBitsSet( 6415 Value.getValueType().getScalarType().getSizeInBits(), 6416 ST->getMemoryVT().getScalarType().getSizeInBits()))) 6417 return SDValue(N, 0); 6418 } 6419 6420 // If this is a load followed by a store to the same location, then the store 6421 // is dead/noop. 6422 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Value)) { 6423 if (Ld->getBasePtr() == Ptr && ST->getMemoryVT() == Ld->getMemoryVT() && 6424 ST->isUnindexed() && !ST->isVolatile() && 6425 // There can't be any side effects between the load and store, such as 6426 // a call or store. 6427 Chain.reachesChainWithoutSideEffects(SDValue(Ld, 1))) { 6428 // The store is dead, remove it. 6429 return Chain; 6430 } 6431 } 6432 6433 // If this is an FP_ROUND or TRUNC followed by a store, fold this into a 6434 // truncating store. We can do this even if this is already a truncstore. 6435 if ((Value.getOpcode() == ISD::FP_ROUND || Value.getOpcode() == ISD::TRUNCATE) 6436 && Value.getNode()->hasOneUse() && ST->isUnindexed() && 6437 TLI.isTruncStoreLegal(Value.getOperand(0).getValueType(), 6438 ST->getMemoryVT())) { 6439 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value.getOperand(0), 6440 Ptr, ST->getPointerInfo(), ST->getMemoryVT(), 6441 ST->isVolatile(), ST->isNonTemporal(), 6442 ST->getAlignment()); 6443 } 6444 6445 return ReduceLoadOpStoreWidth(N); 6446} 6447 6448SDValue DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) { 6449 SDValue InVec = N->getOperand(0); 6450 SDValue InVal = N->getOperand(1); 6451 SDValue EltNo = N->getOperand(2); 6452 6453 // If the inserted element is an UNDEF, just use the input vector. 6454 if (InVal.getOpcode() == ISD::UNDEF) 6455 return InVec; 6456 6457 EVT VT = InVec.getValueType(); 6458 6459 // If we can't generate a legal BUILD_VECTOR, exit 6460 if (LegalOperations && !TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) 6461 return SDValue(); 6462 6463 // If the invec is a BUILD_VECTOR and if EltNo is a constant, build a new 6464 // vector with the inserted element. 6465 if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) { 6466 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 6467 SmallVector<SDValue, 8> Ops(InVec.getNode()->op_begin(), 6468 InVec.getNode()->op_end()); 6469 if (Elt < Ops.size()) 6470 Ops[Elt] = InVal; 6471 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 6472 VT, &Ops[0], Ops.size()); 6473 } 6474 // If the invec is an UNDEF and if EltNo is a constant, create a new 6475 // BUILD_VECTOR with undef elements and the inserted element. 6476 if (InVec.getOpcode() == ISD::UNDEF && 6477 isa<ConstantSDNode>(EltNo)) { 6478 EVT EltVT = VT.getVectorElementType(); 6479 unsigned NElts = VT.getVectorNumElements(); 6480 SmallVector<SDValue, 8> Ops(NElts, DAG.getUNDEF(EltVT)); 6481 6482 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 6483 if (Elt < Ops.size()) 6484 Ops[Elt] = InVal; 6485 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 6486 VT, &Ops[0], Ops.size()); 6487 } 6488 return SDValue(); 6489} 6490 6491SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) { 6492 // (vextract (scalar_to_vector val, 0) -> val 6493 SDValue InVec = N->getOperand(0); 6494 6495 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) { 6496 // Check if the result type doesn't match the inserted element type. A 6497 // SCALAR_TO_VECTOR may truncate the inserted element and the 6498 // EXTRACT_VECTOR_ELT may widen the extracted vector. 6499 SDValue InOp = InVec.getOperand(0); 6500 EVT NVT = N->getValueType(0); 6501 if (InOp.getValueType() != NVT) { 6502 assert(InOp.getValueType().isInteger() && NVT.isInteger()); 6503 return DAG.getSExtOrTrunc(InOp, InVec.getDebugLoc(), NVT); 6504 } 6505 return InOp; 6506 } 6507 6508 // Perform only after legalization to ensure build_vector / vector_shuffle 6509 // optimizations have already been done. 6510 if (!LegalOperations) return SDValue(); 6511 6512 // (vextract (v4f32 load $addr), c) -> (f32 load $addr+c*size) 6513 // (vextract (v4f32 s2v (f32 load $addr)), c) -> (f32 load $addr+c*size) 6514 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), 0) -> (f32 load $addr) 6515 SDValue EltNo = N->getOperand(1); 6516 6517 if (isa<ConstantSDNode>(EltNo)) { 6518 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 6519 bool NewLoad = false; 6520 bool BCNumEltsChanged = false; 6521 EVT VT = InVec.getValueType(); 6522 EVT ExtVT = VT.getVectorElementType(); 6523 EVT LVT = ExtVT; 6524 6525 if (InVec.getOpcode() == ISD::BITCAST) { 6526 EVT BCVT = InVec.getOperand(0).getValueType(); 6527 if (!BCVT.isVector() || ExtVT.bitsGT(BCVT.getVectorElementType())) 6528 return SDValue(); 6529 if (VT.getVectorNumElements() != BCVT.getVectorNumElements()) 6530 BCNumEltsChanged = true; 6531 InVec = InVec.getOperand(0); 6532 ExtVT = BCVT.getVectorElementType(); 6533 NewLoad = true; 6534 } 6535 6536 LoadSDNode *LN0 = NULL; 6537 const ShuffleVectorSDNode *SVN = NULL; 6538 if (ISD::isNormalLoad(InVec.getNode())) { 6539 LN0 = cast<LoadSDNode>(InVec); 6540 } else if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR && 6541 InVec.getOperand(0).getValueType() == ExtVT && 6542 ISD::isNormalLoad(InVec.getOperand(0).getNode())) { 6543 LN0 = cast<LoadSDNode>(InVec.getOperand(0)); 6544 } else if ((SVN = dyn_cast<ShuffleVectorSDNode>(InVec))) { 6545 // (vextract (vector_shuffle (load $addr), v2, <1, u, u, u>), 1) 6546 // => 6547 // (load $addr+1*size) 6548 6549 // If the bit convert changed the number of elements, it is unsafe 6550 // to examine the mask. 6551 if (BCNumEltsChanged) 6552 return SDValue(); 6553 6554 // Select the input vector, guarding against out of range extract vector. 6555 unsigned NumElems = VT.getVectorNumElements(); 6556 int Idx = (Elt > (int)NumElems) ? -1 : SVN->getMaskElt(Elt); 6557 InVec = (Idx < (int)NumElems) ? InVec.getOperand(0) : InVec.getOperand(1); 6558 6559 if (InVec.getOpcode() == ISD::BITCAST) 6560 InVec = InVec.getOperand(0); 6561 if (ISD::isNormalLoad(InVec.getNode())) { 6562 LN0 = cast<LoadSDNode>(InVec); 6563 Elt = (Idx < (int)NumElems) ? Idx : Idx - (int)NumElems; 6564 } 6565 } 6566 6567 if (!LN0 || !LN0->hasOneUse() || LN0->isVolatile()) 6568 return SDValue(); 6569 6570 // If Idx was -1 above, Elt is going to be -1, so just return undef. 6571 if (Elt == -1) 6572 return DAG.getUNDEF(LN0->getBasePtr().getValueType()); 6573 6574 unsigned Align = LN0->getAlignment(); 6575 if (NewLoad) { 6576 // Check the resultant load doesn't need a higher alignment than the 6577 // original load. 6578 unsigned NewAlign = 6579 TLI.getTargetData() 6580 ->getABITypeAlignment(LVT.getTypeForEVT(*DAG.getContext())); 6581 6582 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, LVT)) 6583 return SDValue(); 6584 6585 Align = NewAlign; 6586 } 6587 6588 SDValue NewPtr = LN0->getBasePtr(); 6589 unsigned PtrOff = 0; 6590 6591 if (Elt) { 6592 PtrOff = LVT.getSizeInBits() * Elt / 8; 6593 EVT PtrType = NewPtr.getValueType(); 6594 if (TLI.isBigEndian()) 6595 PtrOff = VT.getSizeInBits() / 8 - PtrOff; 6596 NewPtr = DAG.getNode(ISD::ADD, N->getDebugLoc(), PtrType, NewPtr, 6597 DAG.getConstant(PtrOff, PtrType)); 6598 } 6599 6600 return DAG.getLoad(LVT, N->getDebugLoc(), LN0->getChain(), NewPtr, 6601 LN0->getPointerInfo().getWithOffset(PtrOff), 6602 LN0->isVolatile(), LN0->isNonTemporal(), Align); 6603 } 6604 6605 return SDValue(); 6606} 6607 6608SDValue DAGCombiner::visitBUILD_VECTOR(SDNode *N) { 6609 unsigned NumInScalars = N->getNumOperands(); 6610 EVT VT = N->getValueType(0); 6611 6612 // Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT 6613 // operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from 6614 // at most two distinct vectors, turn this into a shuffle node. 6615 SDValue VecIn1, VecIn2; 6616 for (unsigned i = 0; i != NumInScalars; ++i) { 6617 // Ignore undef inputs. 6618 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 6619 6620 // If this input is something other than a EXTRACT_VECTOR_ELT with a 6621 // constant index, bail out. 6622 if (N->getOperand(i).getOpcode() != ISD::EXTRACT_VECTOR_ELT || 6623 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) { 6624 VecIn1 = VecIn2 = SDValue(0, 0); 6625 break; 6626 } 6627 6628 // If the input vector type disagrees with the result of the build_vector, 6629 // we can't make a shuffle. 6630 SDValue ExtractedFromVec = N->getOperand(i).getOperand(0); 6631 if (ExtractedFromVec.getValueType() != VT) { 6632 VecIn1 = VecIn2 = SDValue(0, 0); 6633 break; 6634 } 6635 6636 // Otherwise, remember this. We allow up to two distinct input vectors. 6637 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2) 6638 continue; 6639 6640 if (VecIn1.getNode() == 0) { 6641 VecIn1 = ExtractedFromVec; 6642 } else if (VecIn2.getNode() == 0) { 6643 VecIn2 = ExtractedFromVec; 6644 } else { 6645 // Too many inputs. 6646 VecIn1 = VecIn2 = SDValue(0, 0); 6647 break; 6648 } 6649 } 6650 6651 // If everything is good, we can make a shuffle operation. 6652 if (VecIn1.getNode()) { 6653 SmallVector<int, 8> Mask; 6654 for (unsigned i = 0; i != NumInScalars; ++i) { 6655 if (N->getOperand(i).getOpcode() == ISD::UNDEF) { 6656 Mask.push_back(-1); 6657 continue; 6658 } 6659 6660 // If extracting from the first vector, just use the index directly. 6661 SDValue Extract = N->getOperand(i); 6662 SDValue ExtVal = Extract.getOperand(1); 6663 if (Extract.getOperand(0) == VecIn1) { 6664 unsigned ExtIndex = cast<ConstantSDNode>(ExtVal)->getZExtValue(); 6665 if (ExtIndex > VT.getVectorNumElements()) 6666 return SDValue(); 6667 6668 Mask.push_back(ExtIndex); 6669 continue; 6670 } 6671 6672 // Otherwise, use InIdx + VecSize 6673 unsigned Idx = cast<ConstantSDNode>(ExtVal)->getZExtValue(); 6674 Mask.push_back(Idx+NumInScalars); 6675 } 6676 6677 // Add count and size info. 6678 if (!isTypeLegal(VT)) 6679 return SDValue(); 6680 6681 // Return the new VECTOR_SHUFFLE node. 6682 SDValue Ops[2]; 6683 Ops[0] = VecIn1; 6684 Ops[1] = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT); 6685 return DAG.getVectorShuffle(VT, N->getDebugLoc(), Ops[0], Ops[1], &Mask[0]); 6686 } 6687 6688 return SDValue(); 6689} 6690 6691SDValue DAGCombiner::visitCONCAT_VECTORS(SDNode *N) { 6692 // TODO: Check to see if this is a CONCAT_VECTORS of a bunch of 6693 // EXTRACT_SUBVECTOR operations. If so, and if the EXTRACT_SUBVECTOR vector 6694 // inputs come from at most two distinct vectors, turn this into a shuffle 6695 // node. 6696 6697 // If we only have one input vector, we don't need to do any concatenation. 6698 if (N->getNumOperands() == 1) 6699 return N->getOperand(0); 6700 6701 return SDValue(); 6702} 6703 6704SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) { 6705 EVT VT = N->getValueType(0); 6706 unsigned NumElts = VT.getVectorNumElements(); 6707 6708 SDValue N0 = N->getOperand(0); 6709 6710 assert(N0.getValueType().getVectorNumElements() == NumElts && 6711 "Vector shuffle must be normalized in DAG"); 6712 6713 // FIXME: implement canonicalizations from DAG.getVectorShuffle() 6714 6715 // If it is a splat, check if the argument vector is another splat or a 6716 // build_vector with all scalar elements the same. 6717 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N); 6718 if (SVN->isSplat() && SVN->getSplatIndex() < (int)NumElts) { 6719 SDNode *V = N0.getNode(); 6720 6721 // If this is a bit convert that changes the element type of the vector but 6722 // not the number of vector elements, look through it. Be careful not to 6723 // look though conversions that change things like v4f32 to v2f64. 6724 if (V->getOpcode() == ISD::BITCAST) { 6725 SDValue ConvInput = V->getOperand(0); 6726 if (ConvInput.getValueType().isVector() && 6727 ConvInput.getValueType().getVectorNumElements() == NumElts) 6728 V = ConvInput.getNode(); 6729 } 6730 6731 if (V->getOpcode() == ISD::BUILD_VECTOR) { 6732 assert(V->getNumOperands() == NumElts && 6733 "BUILD_VECTOR has wrong number of operands"); 6734 SDValue Base; 6735 bool AllSame = true; 6736 for (unsigned i = 0; i != NumElts; ++i) { 6737 if (V->getOperand(i).getOpcode() != ISD::UNDEF) { 6738 Base = V->getOperand(i); 6739 break; 6740 } 6741 } 6742 // Splat of <u, u, u, u>, return <u, u, u, u> 6743 if (!Base.getNode()) 6744 return N0; 6745 for (unsigned i = 0; i != NumElts; ++i) { 6746 if (V->getOperand(i) != Base) { 6747 AllSame = false; 6748 break; 6749 } 6750 } 6751 // Splat of <x, x, x, x>, return <x, x, x, x> 6752 if (AllSame) 6753 return N0; 6754 } 6755 } 6756 return SDValue(); 6757} 6758 6759SDValue DAGCombiner::visitMEMBARRIER(SDNode* N) { 6760 if (!TLI.getShouldFoldAtomicFences()) 6761 return SDValue(); 6762 6763 SDValue atomic = N->getOperand(0); 6764 switch (atomic.getOpcode()) { 6765 case ISD::ATOMIC_CMP_SWAP: 6766 case ISD::ATOMIC_SWAP: 6767 case ISD::ATOMIC_LOAD_ADD: 6768 case ISD::ATOMIC_LOAD_SUB: 6769 case ISD::ATOMIC_LOAD_AND: 6770 case ISD::ATOMIC_LOAD_OR: 6771 case ISD::ATOMIC_LOAD_XOR: 6772 case ISD::ATOMIC_LOAD_NAND: 6773 case ISD::ATOMIC_LOAD_MIN: 6774 case ISD::ATOMIC_LOAD_MAX: 6775 case ISD::ATOMIC_LOAD_UMIN: 6776 case ISD::ATOMIC_LOAD_UMAX: 6777 break; 6778 default: 6779 return SDValue(); 6780 } 6781 6782 SDValue fence = atomic.getOperand(0); 6783 if (fence.getOpcode() != ISD::MEMBARRIER) 6784 return SDValue(); 6785 6786 switch (atomic.getOpcode()) { 6787 case ISD::ATOMIC_CMP_SWAP: 6788 return SDValue(DAG.UpdateNodeOperands(atomic.getNode(), 6789 fence.getOperand(0), 6790 atomic.getOperand(1), atomic.getOperand(2), 6791 atomic.getOperand(3)), atomic.getResNo()); 6792 case ISD::ATOMIC_SWAP: 6793 case ISD::ATOMIC_LOAD_ADD: 6794 case ISD::ATOMIC_LOAD_SUB: 6795 case ISD::ATOMIC_LOAD_AND: 6796 case ISD::ATOMIC_LOAD_OR: 6797 case ISD::ATOMIC_LOAD_XOR: 6798 case ISD::ATOMIC_LOAD_NAND: 6799 case ISD::ATOMIC_LOAD_MIN: 6800 case ISD::ATOMIC_LOAD_MAX: 6801 case ISD::ATOMIC_LOAD_UMIN: 6802 case ISD::ATOMIC_LOAD_UMAX: 6803 return SDValue(DAG.UpdateNodeOperands(atomic.getNode(), 6804 fence.getOperand(0), 6805 atomic.getOperand(1), atomic.getOperand(2)), 6806 atomic.getResNo()); 6807 default: 6808 return SDValue(); 6809 } 6810} 6811 6812/// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform 6813/// an AND to a vector_shuffle with the destination vector and a zero vector. 6814/// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==> 6815/// vector_shuffle V, Zero, <0, 4, 2, 4> 6816SDValue DAGCombiner::XformToShuffleWithZero(SDNode *N) { 6817 EVT VT = N->getValueType(0); 6818 DebugLoc dl = N->getDebugLoc(); 6819 SDValue LHS = N->getOperand(0); 6820 SDValue RHS = N->getOperand(1); 6821 if (N->getOpcode() == ISD::AND) { 6822 if (RHS.getOpcode() == ISD::BITCAST) 6823 RHS = RHS.getOperand(0); 6824 if (RHS.getOpcode() == ISD::BUILD_VECTOR) { 6825 SmallVector<int, 8> Indices; 6826 unsigned NumElts = RHS.getNumOperands(); 6827 for (unsigned i = 0; i != NumElts; ++i) { 6828 SDValue Elt = RHS.getOperand(i); 6829 if (!isa<ConstantSDNode>(Elt)) 6830 return SDValue(); 6831 else if (cast<ConstantSDNode>(Elt)->isAllOnesValue()) 6832 Indices.push_back(i); 6833 else if (cast<ConstantSDNode>(Elt)->isNullValue()) 6834 Indices.push_back(NumElts); 6835 else 6836 return SDValue(); 6837 } 6838 6839 // Let's see if the target supports this vector_shuffle. 6840 EVT RVT = RHS.getValueType(); 6841 if (!TLI.isVectorClearMaskLegal(Indices, RVT)) 6842 return SDValue(); 6843 6844 // Return the new VECTOR_SHUFFLE node. 6845 EVT EltVT = RVT.getVectorElementType(); 6846 SmallVector<SDValue,8> ZeroOps(RVT.getVectorNumElements(), 6847 DAG.getConstant(0, EltVT)); 6848 SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 6849 RVT, &ZeroOps[0], ZeroOps.size()); 6850 LHS = DAG.getNode(ISD::BITCAST, dl, RVT, LHS); 6851 SDValue Shuf = DAG.getVectorShuffle(RVT, dl, LHS, Zero, &Indices[0]); 6852 return DAG.getNode(ISD::BITCAST, dl, VT, Shuf); 6853 } 6854 } 6855 6856 return SDValue(); 6857} 6858 6859/// SimplifyVBinOp - Visit a binary vector operation, like ADD. 6860SDValue DAGCombiner::SimplifyVBinOp(SDNode *N) { 6861 // After legalize, the target may be depending on adds and other 6862 // binary ops to provide legal ways to construct constants or other 6863 // things. Simplifying them may result in a loss of legality. 6864 if (LegalOperations) return SDValue(); 6865 6866 assert(N->getValueType(0).isVector() && 6867 "SimplifyVBinOp only works on vectors!"); 6868 6869 SDValue LHS = N->getOperand(0); 6870 SDValue RHS = N->getOperand(1); 6871 SDValue Shuffle = XformToShuffleWithZero(N); 6872 if (Shuffle.getNode()) return Shuffle; 6873 6874 // If the LHS and RHS are BUILD_VECTOR nodes, see if we can constant fold 6875 // this operation. 6876 if (LHS.getOpcode() == ISD::BUILD_VECTOR && 6877 RHS.getOpcode() == ISD::BUILD_VECTOR) { 6878 SmallVector<SDValue, 8> Ops; 6879 for (unsigned i = 0, e = LHS.getNumOperands(); i != e; ++i) { 6880 SDValue LHSOp = LHS.getOperand(i); 6881 SDValue RHSOp = RHS.getOperand(i); 6882 // If these two elements can't be folded, bail out. 6883 if ((LHSOp.getOpcode() != ISD::UNDEF && 6884 LHSOp.getOpcode() != ISD::Constant && 6885 LHSOp.getOpcode() != ISD::ConstantFP) || 6886 (RHSOp.getOpcode() != ISD::UNDEF && 6887 RHSOp.getOpcode() != ISD::Constant && 6888 RHSOp.getOpcode() != ISD::ConstantFP)) 6889 break; 6890 6891 // Can't fold divide by zero. 6892 if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV || 6893 N->getOpcode() == ISD::FDIV) { 6894 if ((RHSOp.getOpcode() == ISD::Constant && 6895 cast<ConstantSDNode>(RHSOp.getNode())->isNullValue()) || 6896 (RHSOp.getOpcode() == ISD::ConstantFP && 6897 cast<ConstantFPSDNode>(RHSOp.getNode())->getValueAPF().isZero())) 6898 break; 6899 } 6900 6901 EVT VT = LHSOp.getValueType(); 6902 assert(RHSOp.getValueType() == VT && 6903 "SimplifyVBinOp with different BUILD_VECTOR element types"); 6904 SDValue FoldOp = DAG.getNode(N->getOpcode(), LHS.getDebugLoc(), VT, 6905 LHSOp, RHSOp); 6906 if (FoldOp.getOpcode() != ISD::UNDEF && 6907 FoldOp.getOpcode() != ISD::Constant && 6908 FoldOp.getOpcode() != ISD::ConstantFP) 6909 break; 6910 Ops.push_back(FoldOp); 6911 AddToWorkList(FoldOp.getNode()); 6912 } 6913 6914 if (Ops.size() == LHS.getNumOperands()) 6915 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 6916 LHS.getValueType(), &Ops[0], Ops.size()); 6917 } 6918 6919 return SDValue(); 6920} 6921 6922SDValue DAGCombiner::SimplifySelect(DebugLoc DL, SDValue N0, 6923 SDValue N1, SDValue N2){ 6924 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!"); 6925 6926 SDValue SCC = SimplifySelectCC(DL, N0.getOperand(0), N0.getOperand(1), N1, N2, 6927 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 6928 6929 // If we got a simplified select_cc node back from SimplifySelectCC, then 6930 // break it down into a new SETCC node, and a new SELECT node, and then return 6931 // the SELECT node, since we were called with a SELECT node. 6932 if (SCC.getNode()) { 6933 // Check to see if we got a select_cc back (to turn into setcc/select). 6934 // Otherwise, just return whatever node we got back, like fabs. 6935 if (SCC.getOpcode() == ISD::SELECT_CC) { 6936 SDValue SETCC = DAG.getNode(ISD::SETCC, N0.getDebugLoc(), 6937 N0.getValueType(), 6938 SCC.getOperand(0), SCC.getOperand(1), 6939 SCC.getOperand(4)); 6940 AddToWorkList(SETCC.getNode()); 6941 return DAG.getNode(ISD::SELECT, SCC.getDebugLoc(), SCC.getValueType(), 6942 SCC.getOperand(2), SCC.getOperand(3), SETCC); 6943 } 6944 6945 return SCC; 6946 } 6947 return SDValue(); 6948} 6949 6950/// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS 6951/// are the two values being selected between, see if we can simplify the 6952/// select. Callers of this should assume that TheSelect is deleted if this 6953/// returns true. As such, they should return the appropriate thing (e.g. the 6954/// node) back to the top-level of the DAG combiner loop to avoid it being 6955/// looked at. 6956bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDValue LHS, 6957 SDValue RHS) { 6958 6959 // Cannot simplify select with vector condition 6960 if (TheSelect->getOperand(0).getValueType().isVector()) return false; 6961 6962 // If this is a select from two identical things, try to pull the operation 6963 // through the select. 6964 if (LHS.getOpcode() != RHS.getOpcode() || 6965 !LHS.hasOneUse() || !RHS.hasOneUse()) 6966 return false; 6967 6968 // If this is a load and the token chain is identical, replace the select 6969 // of two loads with a load through a select of the address to load from. 6970 // This triggers in things like "select bool X, 10.0, 123.0" after the FP 6971 // constants have been dropped into the constant pool. 6972 if (LHS.getOpcode() == ISD::LOAD) { 6973 LoadSDNode *LLD = cast<LoadSDNode>(LHS); 6974 LoadSDNode *RLD = cast<LoadSDNode>(RHS); 6975 6976 // Token chains must be identical. 6977 if (LHS.getOperand(0) != RHS.getOperand(0) || 6978 // Do not let this transformation reduce the number of volatile loads. 6979 LLD->isVolatile() || RLD->isVolatile() || 6980 // If this is an EXTLOAD, the VT's must match. 6981 LLD->getMemoryVT() != RLD->getMemoryVT() || 6982 // If this is an EXTLOAD, the kind of extension must match. 6983 (LLD->getExtensionType() != RLD->getExtensionType() && 6984 // The only exception is if one of the extensions is anyext. 6985 LLD->getExtensionType() != ISD::EXTLOAD && 6986 RLD->getExtensionType() != ISD::EXTLOAD) || 6987 // FIXME: this discards src value information. This is 6988 // over-conservative. It would be beneficial to be able to remember 6989 // both potential memory locations. Since we are discarding 6990 // src value info, don't do the transformation if the memory 6991 // locations are not in the default address space. 6992 LLD->getPointerInfo().getAddrSpace() != 0 || 6993 RLD->getPointerInfo().getAddrSpace() != 0) 6994 return false; 6995 6996 // Check that the select condition doesn't reach either load. If so, 6997 // folding this will induce a cycle into the DAG. If not, this is safe to 6998 // xform, so create a select of the addresses. 6999 SDValue Addr; 7000 if (TheSelect->getOpcode() == ISD::SELECT) { 7001 SDNode *CondNode = TheSelect->getOperand(0).getNode(); 7002 if ((LLD->hasAnyUseOfValue(1) && LLD->isPredecessorOf(CondNode)) || 7003 (RLD->hasAnyUseOfValue(1) && RLD->isPredecessorOf(CondNode))) 7004 return false; 7005 Addr = DAG.getNode(ISD::SELECT, TheSelect->getDebugLoc(), 7006 LLD->getBasePtr().getValueType(), 7007 TheSelect->getOperand(0), LLD->getBasePtr(), 7008 RLD->getBasePtr()); 7009 } else { // Otherwise SELECT_CC 7010 SDNode *CondLHS = TheSelect->getOperand(0).getNode(); 7011 SDNode *CondRHS = TheSelect->getOperand(1).getNode(); 7012 7013 if ((LLD->hasAnyUseOfValue(1) && 7014 (LLD->isPredecessorOf(CondLHS) || LLD->isPredecessorOf(CondRHS))) || 7015 (LLD->hasAnyUseOfValue(1) && 7016 (LLD->isPredecessorOf(CondLHS) || LLD->isPredecessorOf(CondRHS)))) 7017 return false; 7018 7019 Addr = DAG.getNode(ISD::SELECT_CC, TheSelect->getDebugLoc(), 7020 LLD->getBasePtr().getValueType(), 7021 TheSelect->getOperand(0), 7022 TheSelect->getOperand(1), 7023 LLD->getBasePtr(), RLD->getBasePtr(), 7024 TheSelect->getOperand(4)); 7025 } 7026 7027 SDValue Load; 7028 if (LLD->getExtensionType() == ISD::NON_EXTLOAD) { 7029 Load = DAG.getLoad(TheSelect->getValueType(0), 7030 TheSelect->getDebugLoc(), 7031 // FIXME: Discards pointer info. 7032 LLD->getChain(), Addr, MachinePointerInfo(), 7033 LLD->isVolatile(), LLD->isNonTemporal(), 7034 LLD->getAlignment()); 7035 } else { 7036 Load = DAG.getExtLoad(LLD->getExtensionType() == ISD::EXTLOAD ? 7037 RLD->getExtensionType() : LLD->getExtensionType(), 7038 TheSelect->getDebugLoc(), 7039 TheSelect->getValueType(0), 7040 // FIXME: Discards pointer info. 7041 LLD->getChain(), Addr, MachinePointerInfo(), 7042 LLD->getMemoryVT(), LLD->isVolatile(), 7043 LLD->isNonTemporal(), LLD->getAlignment()); 7044 } 7045 7046 // Users of the select now use the result of the load. 7047 CombineTo(TheSelect, Load); 7048 7049 // Users of the old loads now use the new load's chain. We know the 7050 // old-load value is dead now. 7051 CombineTo(LHS.getNode(), Load.getValue(0), Load.getValue(1)); 7052 CombineTo(RHS.getNode(), Load.getValue(0), Load.getValue(1)); 7053 return true; 7054 } 7055 7056 return false; 7057} 7058 7059/// SimplifySelectCC - Simplify an expression of the form (N0 cond N1) ? N2 : N3 7060/// where 'cond' is the comparison specified by CC. 7061SDValue DAGCombiner::SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, 7062 SDValue N2, SDValue N3, 7063 ISD::CondCode CC, bool NotExtCompare) { 7064 // (x ? y : y) -> y. 7065 if (N2 == N3) return N2; 7066 7067 EVT VT = N2.getValueType(); 7068 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 7069 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode()); 7070 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.getNode()); 7071 7072 // Determine if the condition we're dealing with is constant 7073 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()), 7074 N0, N1, CC, DL, false); 7075 if (SCC.getNode()) AddToWorkList(SCC.getNode()); 7076 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode()); 7077 7078 // fold select_cc true, x, y -> x 7079 if (SCCC && !SCCC->isNullValue()) 7080 return N2; 7081 // fold select_cc false, x, y -> y 7082 if (SCCC && SCCC->isNullValue()) 7083 return N3; 7084 7085 // Check to see if we can simplify the select into an fabs node 7086 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) { 7087 // Allow either -0.0 or 0.0 7088 if (CFP->getValueAPF().isZero()) { 7089 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs 7090 if ((CC == ISD::SETGE || CC == ISD::SETGT) && 7091 N0 == N2 && N3.getOpcode() == ISD::FNEG && 7092 N2 == N3.getOperand(0)) 7093 return DAG.getNode(ISD::FABS, DL, VT, N0); 7094 7095 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs 7096 if ((CC == ISD::SETLT || CC == ISD::SETLE) && 7097 N0 == N3 && N2.getOpcode() == ISD::FNEG && 7098 N2.getOperand(0) == N3) 7099 return DAG.getNode(ISD::FABS, DL, VT, N3); 7100 } 7101 } 7102 7103 // Turn "(a cond b) ? 1.0f : 2.0f" into "load (tmp + ((a cond b) ? 0 : 4)" 7104 // where "tmp" is a constant pool entry containing an array with 1.0 and 2.0 7105 // in it. This is a win when the constant is not otherwise available because 7106 // it replaces two constant pool loads with one. We only do this if the FP 7107 // type is known to be legal, because if it isn't, then we are before legalize 7108 // types an we want the other legalization to happen first (e.g. to avoid 7109 // messing with soft float) and if the ConstantFP is not legal, because if 7110 // it is legal, we may not need to store the FP constant in a constant pool. 7111 if (ConstantFPSDNode *TV = dyn_cast<ConstantFPSDNode>(N2)) 7112 if (ConstantFPSDNode *FV = dyn_cast<ConstantFPSDNode>(N3)) { 7113 if (TLI.isTypeLegal(N2.getValueType()) && 7114 (TLI.getOperationAction(ISD::ConstantFP, N2.getValueType()) != 7115 TargetLowering::Legal) && 7116 // If both constants have multiple uses, then we won't need to do an 7117 // extra load, they are likely around in registers for other users. 7118 (TV->hasOneUse() || FV->hasOneUse())) { 7119 Constant *Elts[] = { 7120 const_cast<ConstantFP*>(FV->getConstantFPValue()), 7121 const_cast<ConstantFP*>(TV->getConstantFPValue()) 7122 }; 7123 const Type *FPTy = Elts[0]->getType(); 7124 const TargetData &TD = *TLI.getTargetData(); 7125 7126 // Create a ConstantArray of the two constants. 7127 Constant *CA = ConstantArray::get(ArrayType::get(FPTy, 2), Elts, 2); 7128 SDValue CPIdx = DAG.getConstantPool(CA, TLI.getPointerTy(), 7129 TD.getPrefTypeAlignment(FPTy)); 7130 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 7131 7132 // Get the offsets to the 0 and 1 element of the array so that we can 7133 // select between them. 7134 SDValue Zero = DAG.getIntPtrConstant(0); 7135 unsigned EltSize = (unsigned)TD.getTypeAllocSize(Elts[0]->getType()); 7136 SDValue One = DAG.getIntPtrConstant(EltSize); 7137 7138 SDValue Cond = DAG.getSetCC(DL, 7139 TLI.getSetCCResultType(N0.getValueType()), 7140 N0, N1, CC); 7141 SDValue CstOffset = DAG.getNode(ISD::SELECT, DL, Zero.getValueType(), 7142 Cond, One, Zero); 7143 CPIdx = DAG.getNode(ISD::ADD, DL, TLI.getPointerTy(), CPIdx, 7144 CstOffset); 7145 return DAG.getLoad(TV->getValueType(0), DL, DAG.getEntryNode(), CPIdx, 7146 MachinePointerInfo::getConstantPool(), false, 7147 false, Alignment); 7148 7149 } 7150 } 7151 7152 // Check to see if we can perform the "gzip trick", transforming 7153 // (select_cc setlt X, 0, A, 0) -> (and (sra X, (sub size(X), 1), A) 7154 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT && 7155 N0.getValueType().isInteger() && 7156 N2.getValueType().isInteger() && 7157 (N1C->isNullValue() || // (a < 0) ? b : 0 7158 (N1C->getAPIntValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0 7159 EVT XType = N0.getValueType(); 7160 EVT AType = N2.getValueType(); 7161 if (XType.bitsGE(AType)) { 7162 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a 7163 // single-bit constant. 7164 if (N2C && ((N2C->getAPIntValue() & (N2C->getAPIntValue()-1)) == 0)) { 7165 unsigned ShCtV = N2C->getAPIntValue().logBase2(); 7166 ShCtV = XType.getSizeInBits()-ShCtV-1; 7167 SDValue ShCt = DAG.getConstant(ShCtV, 7168 getShiftAmountTy(N0.getValueType())); 7169 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), 7170 XType, N0, ShCt); 7171 AddToWorkList(Shift.getNode()); 7172 7173 if (XType.bitsGT(AType)) { 7174 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift); 7175 AddToWorkList(Shift.getNode()); 7176 } 7177 7178 return DAG.getNode(ISD::AND, DL, AType, Shift, N2); 7179 } 7180 7181 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), 7182 XType, N0, 7183 DAG.getConstant(XType.getSizeInBits()-1, 7184 getShiftAmountTy(N0.getValueType()))); 7185 AddToWorkList(Shift.getNode()); 7186 7187 if (XType.bitsGT(AType)) { 7188 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift); 7189 AddToWorkList(Shift.getNode()); 7190 } 7191 7192 return DAG.getNode(ISD::AND, DL, AType, Shift, N2); 7193 } 7194 } 7195 7196 // fold (select_cc seteq (and x, y), 0, 0, A) -> (and (shr (shl x)) A) 7197 // where y is has a single bit set. 7198 // A plaintext description would be, we can turn the SELECT_CC into an AND 7199 // when the condition can be materialized as an all-ones register. Any 7200 // single bit-test can be materialized as an all-ones register with 7201 // shift-left and shift-right-arith. 7202 if (CC == ISD::SETEQ && N0->getOpcode() == ISD::AND && 7203 N0->getValueType(0) == VT && 7204 N1C && N1C->isNullValue() && 7205 N2C && N2C->isNullValue()) { 7206 SDValue AndLHS = N0->getOperand(0); 7207 ConstantSDNode *ConstAndRHS = dyn_cast<ConstantSDNode>(N0->getOperand(1)); 7208 if (ConstAndRHS && ConstAndRHS->getAPIntValue().countPopulation() == 1) { 7209 // Shift the tested bit over the sign bit. 7210 APInt AndMask = ConstAndRHS->getAPIntValue(); 7211 SDValue ShlAmt = 7212 DAG.getConstant(AndMask.countLeadingZeros(), 7213 getShiftAmountTy(AndLHS.getValueType())); 7214 SDValue Shl = DAG.getNode(ISD::SHL, N0.getDebugLoc(), VT, AndLHS, ShlAmt); 7215 7216 // Now arithmetic right shift it all the way over, so the result is either 7217 // all-ones, or zero. 7218 SDValue ShrAmt = 7219 DAG.getConstant(AndMask.getBitWidth()-1, 7220 getShiftAmountTy(Shl.getValueType())); 7221 SDValue Shr = DAG.getNode(ISD::SRA, N0.getDebugLoc(), VT, Shl, ShrAmt); 7222 7223 return DAG.getNode(ISD::AND, DL, VT, Shr, N3); 7224 } 7225 } 7226 7227 // fold select C, 16, 0 -> shl C, 4 7228 if (N2C && N3C && N3C->isNullValue() && N2C->getAPIntValue().isPowerOf2() && 7229 TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent) { 7230 7231 // If the caller doesn't want us to simplify this into a zext of a compare, 7232 // don't do it. 7233 if (NotExtCompare && N2C->getAPIntValue() == 1) 7234 return SDValue(); 7235 7236 // Get a SetCC of the condition 7237 // FIXME: Should probably make sure that setcc is legal if we ever have a 7238 // target where it isn't. 7239 SDValue Temp, SCC; 7240 // cast from setcc result type to select result type 7241 if (LegalTypes) { 7242 SCC = DAG.getSetCC(DL, TLI.getSetCCResultType(N0.getValueType()), 7243 N0, N1, CC); 7244 if (N2.getValueType().bitsLT(SCC.getValueType())) 7245 Temp = DAG.getZeroExtendInReg(SCC, N2.getDebugLoc(), N2.getValueType()); 7246 else 7247 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(), 7248 N2.getValueType(), SCC); 7249 } else { 7250 SCC = DAG.getSetCC(N0.getDebugLoc(), MVT::i1, N0, N1, CC); 7251 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(), 7252 N2.getValueType(), SCC); 7253 } 7254 7255 AddToWorkList(SCC.getNode()); 7256 AddToWorkList(Temp.getNode()); 7257 7258 if (N2C->getAPIntValue() == 1) 7259 return Temp; 7260 7261 // shl setcc result by log2 n2c 7262 return DAG.getNode(ISD::SHL, DL, N2.getValueType(), Temp, 7263 DAG.getConstant(N2C->getAPIntValue().logBase2(), 7264 getShiftAmountTy(Temp.getValueType()))); 7265 } 7266 7267 // Check to see if this is the equivalent of setcc 7268 // FIXME: Turn all of these into setcc if setcc if setcc is legal 7269 // otherwise, go ahead with the folds. 7270 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getAPIntValue() == 1ULL)) { 7271 EVT XType = N0.getValueType(); 7272 if (!LegalOperations || 7273 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(XType))) { 7274 SDValue Res = DAG.getSetCC(DL, TLI.getSetCCResultType(XType), N0, N1, CC); 7275 if (Res.getValueType() != VT) 7276 Res = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, Res); 7277 return Res; 7278 } 7279 7280 // fold (seteq X, 0) -> (srl (ctlz X, log2(size(X)))) 7281 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ && 7282 (!LegalOperations || 7283 TLI.isOperationLegal(ISD::CTLZ, XType))) { 7284 SDValue Ctlz = DAG.getNode(ISD::CTLZ, N0.getDebugLoc(), XType, N0); 7285 return DAG.getNode(ISD::SRL, DL, XType, Ctlz, 7286 DAG.getConstant(Log2_32(XType.getSizeInBits()), 7287 getShiftAmountTy(Ctlz.getValueType()))); 7288 } 7289 // fold (setgt X, 0) -> (srl (and (-X, ~X), size(X)-1)) 7290 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) { 7291 SDValue NegN0 = DAG.getNode(ISD::SUB, N0.getDebugLoc(), 7292 XType, DAG.getConstant(0, XType), N0); 7293 SDValue NotN0 = DAG.getNOT(N0.getDebugLoc(), N0, XType); 7294 return DAG.getNode(ISD::SRL, DL, XType, 7295 DAG.getNode(ISD::AND, DL, XType, NegN0, NotN0), 7296 DAG.getConstant(XType.getSizeInBits()-1, 7297 getShiftAmountTy(XType))); 7298 } 7299 // fold (setgt X, -1) -> (xor (srl (X, size(X)-1), 1)) 7300 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) { 7301 SDValue Sign = DAG.getNode(ISD::SRL, N0.getDebugLoc(), XType, N0, 7302 DAG.getConstant(XType.getSizeInBits()-1, 7303 getShiftAmountTy(N0.getValueType()))); 7304 return DAG.getNode(ISD::XOR, DL, XType, Sign, DAG.getConstant(1, XType)); 7305 } 7306 } 7307 7308 // Check to see if this is an integer abs. 7309 // select_cc setg[te] X, 0, X, -X -> 7310 // select_cc setgt X, -1, X, -X -> 7311 // select_cc setl[te] X, 0, -X, X -> 7312 // select_cc setlt X, 1, -X, X -> 7313 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 7314 if (N1C) { 7315 ConstantSDNode *SubC = NULL; 7316 if (((N1C->isNullValue() && (CC == ISD::SETGT || CC == ISD::SETGE)) || 7317 (N1C->isAllOnesValue() && CC == ISD::SETGT)) && 7318 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1)) 7319 SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0)); 7320 else if (((N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE)) || 7321 (N1C->isOne() && CC == ISD::SETLT)) && 7322 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1)) 7323 SubC = dyn_cast<ConstantSDNode>(N2.getOperand(0)); 7324 7325 EVT XType = N0.getValueType(); 7326 if (SubC && SubC->isNullValue() && XType.isInteger()) { 7327 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), XType, 7328 N0, 7329 DAG.getConstant(XType.getSizeInBits()-1, 7330 getShiftAmountTy(N0.getValueType()))); 7331 SDValue Add = DAG.getNode(ISD::ADD, N0.getDebugLoc(), 7332 XType, N0, Shift); 7333 AddToWorkList(Shift.getNode()); 7334 AddToWorkList(Add.getNode()); 7335 return DAG.getNode(ISD::XOR, DL, XType, Add, Shift); 7336 } 7337 } 7338 7339 return SDValue(); 7340} 7341 7342/// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC. 7343SDValue DAGCombiner::SimplifySetCC(EVT VT, SDValue N0, 7344 SDValue N1, ISD::CondCode Cond, 7345 DebugLoc DL, bool foldBooleans) { 7346 TargetLowering::DAGCombinerInfo 7347 DagCombineInfo(DAG, !LegalTypes, !LegalOperations, false, this); 7348 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo, DL); 7349} 7350 7351/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 7352/// return a DAG expression to select that will generate the same value by 7353/// multiplying by a magic number. See: 7354/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 7355SDValue DAGCombiner::BuildSDIV(SDNode *N) { 7356 std::vector<SDNode*> Built; 7357 SDValue S = TLI.BuildSDIV(N, DAG, &Built); 7358 7359 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 7360 ii != ee; ++ii) 7361 AddToWorkList(*ii); 7362 return S; 7363} 7364 7365/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 7366/// return a DAG expression to select that will generate the same value by 7367/// multiplying by a magic number. See: 7368/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 7369SDValue DAGCombiner::BuildUDIV(SDNode *N) { 7370 std::vector<SDNode*> Built; 7371 SDValue S = TLI.BuildUDIV(N, DAG, &Built); 7372 7373 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 7374 ii != ee; ++ii) 7375 AddToWorkList(*ii); 7376 return S; 7377} 7378 7379/// FindBaseOffset - Return true if base is a frame index, which is known not 7380// to alias with anything but itself. Provides base object and offset as 7381// results. 7382static bool FindBaseOffset(SDValue Ptr, SDValue &Base, int64_t &Offset, 7383 const GlobalValue *&GV, void *&CV) { 7384 // Assume it is a primitive operation. 7385 Base = Ptr; Offset = 0; GV = 0; CV = 0; 7386 7387 // If it's an adding a simple constant then integrate the offset. 7388 if (Base.getOpcode() == ISD::ADD) { 7389 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) { 7390 Base = Base.getOperand(0); 7391 Offset += C->getZExtValue(); 7392 } 7393 } 7394 7395 // Return the underlying GlobalValue, and update the Offset. Return false 7396 // for GlobalAddressSDNode since the same GlobalAddress may be represented 7397 // by multiple nodes with different offsets. 7398 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Base)) { 7399 GV = G->getGlobal(); 7400 Offset += G->getOffset(); 7401 return false; 7402 } 7403 7404 // Return the underlying Constant value, and update the Offset. Return false 7405 // for ConstantSDNodes since the same constant pool entry may be represented 7406 // by multiple nodes with different offsets. 7407 if (ConstantPoolSDNode *C = dyn_cast<ConstantPoolSDNode>(Base)) { 7408 CV = C->isMachineConstantPoolEntry() ? (void *)C->getMachineCPVal() 7409 : (void *)C->getConstVal(); 7410 Offset += C->getOffset(); 7411 return false; 7412 } 7413 // If it's any of the following then it can't alias with anything but itself. 7414 return isa<FrameIndexSDNode>(Base); 7415} 7416 7417/// isAlias - Return true if there is any possibility that the two addresses 7418/// overlap. 7419bool DAGCombiner::isAlias(SDValue Ptr1, int64_t Size1, 7420 const Value *SrcValue1, int SrcValueOffset1, 7421 unsigned SrcValueAlign1, 7422 const MDNode *TBAAInfo1, 7423 SDValue Ptr2, int64_t Size2, 7424 const Value *SrcValue2, int SrcValueOffset2, 7425 unsigned SrcValueAlign2, 7426 const MDNode *TBAAInfo2) const { 7427 // If they are the same then they must be aliases. 7428 if (Ptr1 == Ptr2) return true; 7429 7430 // Gather base node and offset information. 7431 SDValue Base1, Base2; 7432 int64_t Offset1, Offset2; 7433 const GlobalValue *GV1, *GV2; 7434 void *CV1, *CV2; 7435 bool isFrameIndex1 = FindBaseOffset(Ptr1, Base1, Offset1, GV1, CV1); 7436 bool isFrameIndex2 = FindBaseOffset(Ptr2, Base2, Offset2, GV2, CV2); 7437 7438 // If they have a same base address then check to see if they overlap. 7439 if (Base1 == Base2 || (GV1 && (GV1 == GV2)) || (CV1 && (CV1 == CV2))) 7440 return !((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1); 7441 7442 // It is possible for different frame indices to alias each other, mostly 7443 // when tail call optimization reuses return address slots for arguments. 7444 // To catch this case, look up the actual index of frame indices to compute 7445 // the real alias relationship. 7446 if (isFrameIndex1 && isFrameIndex2) { 7447 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 7448 Offset1 += MFI->getObjectOffset(cast<FrameIndexSDNode>(Base1)->getIndex()); 7449 Offset2 += MFI->getObjectOffset(cast<FrameIndexSDNode>(Base2)->getIndex()); 7450 return !((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1); 7451 } 7452 7453 // Otherwise, if we know what the bases are, and they aren't identical, then 7454 // we know they cannot alias. 7455 if ((isFrameIndex1 || CV1 || GV1) && (isFrameIndex2 || CV2 || GV2)) 7456 return false; 7457 7458 // If we know required SrcValue1 and SrcValue2 have relatively large alignment 7459 // compared to the size and offset of the access, we may be able to prove they 7460 // do not alias. This check is conservative for now to catch cases created by 7461 // splitting vector types. 7462 if ((SrcValueAlign1 == SrcValueAlign2) && 7463 (SrcValueOffset1 != SrcValueOffset2) && 7464 (Size1 == Size2) && (SrcValueAlign1 > Size1)) { 7465 int64_t OffAlign1 = SrcValueOffset1 % SrcValueAlign1; 7466 int64_t OffAlign2 = SrcValueOffset2 % SrcValueAlign1; 7467 7468 // There is no overlap between these relatively aligned accesses of similar 7469 // size, return no alias. 7470 if ((OffAlign1 + Size1) <= OffAlign2 || (OffAlign2 + Size2) <= OffAlign1) 7471 return false; 7472 } 7473 7474 if (CombinerGlobalAA) { 7475 // Use alias analysis information. 7476 int64_t MinOffset = std::min(SrcValueOffset1, SrcValueOffset2); 7477 int64_t Overlap1 = Size1 + SrcValueOffset1 - MinOffset; 7478 int64_t Overlap2 = Size2 + SrcValueOffset2 - MinOffset; 7479 AliasAnalysis::AliasResult AAResult = 7480 AA.alias(AliasAnalysis::Location(SrcValue1, Overlap1, TBAAInfo1), 7481 AliasAnalysis::Location(SrcValue2, Overlap2, TBAAInfo2)); 7482 if (AAResult == AliasAnalysis::NoAlias) 7483 return false; 7484 } 7485 7486 // Otherwise we have to assume they alias. 7487 return true; 7488} 7489 7490/// FindAliasInfo - Extracts the relevant alias information from the memory 7491/// node. Returns true if the operand was a load. 7492bool DAGCombiner::FindAliasInfo(SDNode *N, 7493 SDValue &Ptr, int64_t &Size, 7494 const Value *&SrcValue, 7495 int &SrcValueOffset, 7496 unsigned &SrcValueAlign, 7497 const MDNode *&TBAAInfo) const { 7498 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 7499 Ptr = LD->getBasePtr(); 7500 Size = LD->getMemoryVT().getSizeInBits() >> 3; 7501 SrcValue = LD->getSrcValue(); 7502 SrcValueOffset = LD->getSrcValueOffset(); 7503 SrcValueAlign = LD->getOriginalAlignment(); 7504 TBAAInfo = LD->getTBAAInfo(); 7505 return true; 7506 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 7507 Ptr = ST->getBasePtr(); 7508 Size = ST->getMemoryVT().getSizeInBits() >> 3; 7509 SrcValue = ST->getSrcValue(); 7510 SrcValueOffset = ST->getSrcValueOffset(); 7511 SrcValueAlign = ST->getOriginalAlignment(); 7512 TBAAInfo = ST->getTBAAInfo(); 7513 } else { 7514 llvm_unreachable("FindAliasInfo expected a memory operand"); 7515 } 7516 7517 return false; 7518} 7519 7520/// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 7521/// looking for aliasing nodes and adding them to the Aliases vector. 7522void DAGCombiner::GatherAllAliases(SDNode *N, SDValue OriginalChain, 7523 SmallVector<SDValue, 8> &Aliases) { 7524 SmallVector<SDValue, 8> Chains; // List of chains to visit. 7525 SmallPtrSet<SDNode *, 16> Visited; // Visited node set. 7526 7527 // Get alias information for node. 7528 SDValue Ptr; 7529 int64_t Size; 7530 const Value *SrcValue; 7531 int SrcValueOffset; 7532 unsigned SrcValueAlign; 7533 const MDNode *SrcTBAAInfo; 7534 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset, 7535 SrcValueAlign, SrcTBAAInfo); 7536 7537 // Starting off. 7538 Chains.push_back(OriginalChain); 7539 unsigned Depth = 0; 7540 7541 // Look at each chain and determine if it is an alias. If so, add it to the 7542 // aliases list. If not, then continue up the chain looking for the next 7543 // candidate. 7544 while (!Chains.empty()) { 7545 SDValue Chain = Chains.back(); 7546 Chains.pop_back(); 7547 7548 // For TokenFactor nodes, look at each operand and only continue up the 7549 // chain until we find two aliases. If we've seen two aliases, assume we'll 7550 // find more and revert to original chain since the xform is unlikely to be 7551 // profitable. 7552 // 7553 // FIXME: The depth check could be made to return the last non-aliasing 7554 // chain we found before we hit a tokenfactor rather than the original 7555 // chain. 7556 if (Depth > 6 || Aliases.size() == 2) { 7557 Aliases.clear(); 7558 Aliases.push_back(OriginalChain); 7559 break; 7560 } 7561 7562 // Don't bother if we've been before. 7563 if (!Visited.insert(Chain.getNode())) 7564 continue; 7565 7566 switch (Chain.getOpcode()) { 7567 case ISD::EntryToken: 7568 // Entry token is ideal chain operand, but handled in FindBetterChain. 7569 break; 7570 7571 case ISD::LOAD: 7572 case ISD::STORE: { 7573 // Get alias information for Chain. 7574 SDValue OpPtr; 7575 int64_t OpSize; 7576 const Value *OpSrcValue; 7577 int OpSrcValueOffset; 7578 unsigned OpSrcValueAlign; 7579 const MDNode *OpSrcTBAAInfo; 7580 bool IsOpLoad = FindAliasInfo(Chain.getNode(), OpPtr, OpSize, 7581 OpSrcValue, OpSrcValueOffset, 7582 OpSrcValueAlign, 7583 OpSrcTBAAInfo); 7584 7585 // If chain is alias then stop here. 7586 if (!(IsLoad && IsOpLoad) && 7587 isAlias(Ptr, Size, SrcValue, SrcValueOffset, SrcValueAlign, 7588 SrcTBAAInfo, 7589 OpPtr, OpSize, OpSrcValue, OpSrcValueOffset, 7590 OpSrcValueAlign, OpSrcTBAAInfo)) { 7591 Aliases.push_back(Chain); 7592 } else { 7593 // Look further up the chain. 7594 Chains.push_back(Chain.getOperand(0)); 7595 ++Depth; 7596 } 7597 break; 7598 } 7599 7600 case ISD::TokenFactor: 7601 // We have to check each of the operands of the token factor for "small" 7602 // token factors, so we queue them up. Adding the operands to the queue 7603 // (stack) in reverse order maintains the original order and increases the 7604 // likelihood that getNode will find a matching token factor (CSE.) 7605 if (Chain.getNumOperands() > 16) { 7606 Aliases.push_back(Chain); 7607 break; 7608 } 7609 for (unsigned n = Chain.getNumOperands(); n;) 7610 Chains.push_back(Chain.getOperand(--n)); 7611 ++Depth; 7612 break; 7613 7614 default: 7615 // For all other instructions we will just have to take what we can get. 7616 Aliases.push_back(Chain); 7617 break; 7618 } 7619 } 7620} 7621 7622/// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking 7623/// for a better chain (aliasing node.) 7624SDValue DAGCombiner::FindBetterChain(SDNode *N, SDValue OldChain) { 7625 SmallVector<SDValue, 8> Aliases; // Ops for replacing token factor. 7626 7627 // Accumulate all the aliases to this node. 7628 GatherAllAliases(N, OldChain, Aliases); 7629 7630 if (Aliases.size() == 0) { 7631 // If no operands then chain to entry token. 7632 return DAG.getEntryNode(); 7633 } else if (Aliases.size() == 1) { 7634 // If a single operand then chain to it. We don't need to revisit it. 7635 return Aliases[0]; 7636 } 7637 7638 // Construct a custom tailored token factor. 7639 return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, 7640 &Aliases[0], Aliases.size()); 7641} 7642 7643// SelectionDAG::Combine - This is the entry point for the file. 7644// 7645void SelectionDAG::Combine(CombineLevel Level, AliasAnalysis &AA, 7646 CodeGenOpt::Level OptLevel) { 7647 /// run - This is the main entry point to this class. 7648 /// 7649 DAGCombiner(*this, AA, OptLevel).Run(Level); 7650} 7651