DAGCombiner.cpp revision bfd65a05c96988d175dec57b0b59e7dca2be04c1
1//===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by Nate Begeman and is distributed under the 6// University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run 11// both before and after the DAG is legalized. 12// 13// FIXME: Missing folds 14// sdiv, udiv, srem, urem (X, const) where X is an integer can be expanded into 15// a sequence of multiplies, shifts, and adds. This should be controlled by 16// some kind of hint from the target that int div is expensive. 17// various folds of mulh[s,u] by constants such as -1, powers of 2, etc. 18// 19// FIXME: Should add a corresponding version of fold AND with 20// ZERO_EXTEND/SIGN_EXTEND by converting them to an ANY_EXTEND node which 21// we don't have yet. 22// 23// FIXME: select C, pow2, pow2 -> something smart 24// FIXME: trunc(select X, Y, Z) -> select X, trunc(Y), trunc(Z) 25// FIXME: (select C, load A, load B) -> load (select C, A, B) 26// FIXME: Dead stores -> nuke 27// FIXME: shr X, (and Y,31) -> shr X, Y 28// FIXME: TRUNC (LOAD) -> EXT_LOAD/LOAD(smaller) 29// FIXME: mul (x, const) -> shifts + adds 30// FIXME: undef values 31// FIXME: make truncate see through SIGN_EXTEND and AND 32// FIXME: (sra (sra x, c1), c2) -> (sra x, c1+c2) 33// FIXME: verify that getNode can't return extends with an operand whose type 34// is >= to that of the extend. 35// FIXME: divide by zero is currently left unfolded. do we want to turn this 36// into an undef? 37// FIXME: select ne (select cc, 1, 0), 0, true, false -> select cc, true, false 38// FIXME: reassociate (X+C)+Y into (X+Y)+C if the inner expression has one use 39// 40//===----------------------------------------------------------------------===// 41 42#define DEBUG_TYPE "dagcombine" 43#include "llvm/ADT/Statistic.h" 44#include "llvm/CodeGen/SelectionDAG.h" 45#include "llvm/Support/Debug.h" 46#include "llvm/Support/MathExtras.h" 47#include "llvm/Target/TargetLowering.h" 48#include <algorithm> 49#include <cmath> 50using namespace llvm; 51 52namespace { 53 Statistic<> NodesCombined ("dagcombiner", "Number of dag nodes combined"); 54 55 class DAGCombiner { 56 SelectionDAG &DAG; 57 TargetLowering &TLI; 58 bool AfterLegalize; 59 60 // Worklist of all of the nodes that need to be simplified. 61 std::vector<SDNode*> WorkList; 62 63 /// AddUsersToWorkList - When an instruction is simplified, add all users of 64 /// the instruction to the work lists because they might get more simplified 65 /// now. 66 /// 67 void AddUsersToWorkList(SDNode *N) { 68 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 69 UI != UE; ++UI) 70 WorkList.push_back(*UI); 71 } 72 73 /// removeFromWorkList - remove all instances of N from the worklist. 74 void removeFromWorkList(SDNode *N) { 75 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N), 76 WorkList.end()); 77 } 78 79 SDOperand CombineTo(SDNode *N, const std::vector<SDOperand> &To) { 80 ++NodesCombined; 81 DEBUG(std::cerr << "\nReplacing "; N->dump(); 82 std::cerr << "\nWith: "; To[0].Val->dump(); 83 std::cerr << " and " << To.size()-1 << " other values\n"); 84 std::vector<SDNode*> NowDead; 85 DAG.ReplaceAllUsesWith(N, To, &NowDead); 86 87 // Push the new nodes and any users onto the worklist 88 for (unsigned i = 0, e = To.size(); i != e; ++i) { 89 WorkList.push_back(To[i].Val); 90 AddUsersToWorkList(To[i].Val); 91 } 92 93 // Nodes can end up on the worklist more than once. Make sure we do 94 // not process a node that has been replaced. 95 removeFromWorkList(N); 96 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 97 removeFromWorkList(NowDead[i]); 98 99 // Finally, since the node is now dead, remove it from the graph. 100 DAG.DeleteNode(N); 101 return SDOperand(N, 0); 102 } 103 104 SDOperand CombineTo(SDNode *N, SDOperand Res) { 105 std::vector<SDOperand> To; 106 To.push_back(Res); 107 return CombineTo(N, To); 108 } 109 110 SDOperand CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1) { 111 std::vector<SDOperand> To; 112 To.push_back(Res0); 113 To.push_back(Res1); 114 return CombineTo(N, To); 115 } 116 117 /// visit - call the node-specific routine that knows how to fold each 118 /// particular type of node. 119 SDOperand visit(SDNode *N); 120 121 // Visitation implementation - Implement dag node combining for different 122 // node types. The semantics are as follows: 123 // Return Value: 124 // SDOperand.Val == 0 - No change was made 125 // SDOperand.Val == N - N was replaced, is dead, and is already handled. 126 // otherwise - N should be replaced by the returned Operand. 127 // 128 SDOperand visitTokenFactor(SDNode *N); 129 SDOperand visitADD(SDNode *N); 130 SDOperand visitSUB(SDNode *N); 131 SDOperand visitMUL(SDNode *N); 132 SDOperand visitSDIV(SDNode *N); 133 SDOperand visitUDIV(SDNode *N); 134 SDOperand visitSREM(SDNode *N); 135 SDOperand visitUREM(SDNode *N); 136 SDOperand visitMULHU(SDNode *N); 137 SDOperand visitMULHS(SDNode *N); 138 SDOperand visitAND(SDNode *N); 139 SDOperand visitOR(SDNode *N); 140 SDOperand visitXOR(SDNode *N); 141 SDOperand visitSHL(SDNode *N); 142 SDOperand visitSRA(SDNode *N); 143 SDOperand visitSRL(SDNode *N); 144 SDOperand visitCTLZ(SDNode *N); 145 SDOperand visitCTTZ(SDNode *N); 146 SDOperand visitCTPOP(SDNode *N); 147 SDOperand visitSELECT(SDNode *N); 148 SDOperand visitSELECT_CC(SDNode *N); 149 SDOperand visitSETCC(SDNode *N); 150 SDOperand visitSIGN_EXTEND(SDNode *N); 151 SDOperand visitZERO_EXTEND(SDNode *N); 152 SDOperand visitSIGN_EXTEND_INREG(SDNode *N); 153 SDOperand visitTRUNCATE(SDNode *N); 154 155 SDOperand visitFADD(SDNode *N); 156 SDOperand visitFSUB(SDNode *N); 157 SDOperand visitFMUL(SDNode *N); 158 SDOperand visitFDIV(SDNode *N); 159 SDOperand visitFREM(SDNode *N); 160 SDOperand visitSINT_TO_FP(SDNode *N); 161 SDOperand visitUINT_TO_FP(SDNode *N); 162 SDOperand visitFP_TO_SINT(SDNode *N); 163 SDOperand visitFP_TO_UINT(SDNode *N); 164 SDOperand visitFP_ROUND(SDNode *N); 165 SDOperand visitFP_ROUND_INREG(SDNode *N); 166 SDOperand visitFP_EXTEND(SDNode *N); 167 SDOperand visitFNEG(SDNode *N); 168 SDOperand visitFABS(SDNode *N); 169 SDOperand visitBRCOND(SDNode *N); 170 SDOperand visitBRCONDTWOWAY(SDNode *N); 171 SDOperand visitBR_CC(SDNode *N); 172 SDOperand visitBRTWOWAY_CC(SDNode *N); 173 174 SDOperand visitLOAD(SDNode *N); 175 SDOperand visitSTORE(SDNode *N); 176 177 SDOperand SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2); 178 SDOperand SimplifySelectCC(SDOperand N0, SDOperand N1, SDOperand N2, 179 SDOperand N3, ISD::CondCode CC); 180 SDOperand SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1, 181 ISD::CondCode Cond, bool foldBooleans = true); 182public: 183 DAGCombiner(SelectionDAG &D) 184 : DAG(D), TLI(D.getTargetLoweringInfo()), AfterLegalize(false) {} 185 186 /// Run - runs the dag combiner on all nodes in the work list 187 void Run(bool RunningAfterLegalize); 188 }; 189} 190 191/// MaskedValueIsZero - Return true if 'Op & Mask' is known to be zero. We use 192/// this predicate to simplify operations downstream. Op and Mask are known to 193/// be the same type. 194static bool MaskedValueIsZero(const SDOperand &Op, uint64_t Mask, 195 const TargetLowering &TLI) { 196 unsigned SrcBits; 197 if (Mask == 0) return true; 198 199 // If we know the result of a setcc has the top bits zero, use this info. 200 switch (Op.getOpcode()) { 201 case ISD::Constant: 202 return (cast<ConstantSDNode>(Op)->getValue() & Mask) == 0; 203 case ISD::SETCC: 204 return ((Mask & 1) == 0) && 205 TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult; 206 case ISD::ZEXTLOAD: 207 SrcBits = MVT::getSizeInBits(cast<VTSDNode>(Op.getOperand(3))->getVT()); 208 return (Mask & ((1ULL << SrcBits)-1)) == 0; // Returning only the zext bits. 209 case ISD::ZERO_EXTEND: 210 SrcBits = MVT::getSizeInBits(Op.getOperand(0).getValueType()); 211 return MaskedValueIsZero(Op.getOperand(0),Mask & ((1ULL << SrcBits)-1),TLI); 212 case ISD::AssertZext: 213 SrcBits = MVT::getSizeInBits(cast<VTSDNode>(Op.getOperand(1))->getVT()); 214 return (Mask & ((1ULL << SrcBits)-1)) == 0; // Returning only the zext bits. 215 case ISD::AND: 216 // If either of the operands has zero bits, the result will too. 217 if (MaskedValueIsZero(Op.getOperand(1), Mask, TLI) || 218 MaskedValueIsZero(Op.getOperand(0), Mask, TLI)) 219 return true; 220 // (X & C1) & C2 == 0 iff C1 & C2 == 0. 221 if (ConstantSDNode *AndRHS = dyn_cast<ConstantSDNode>(Op.getOperand(1))) 222 return MaskedValueIsZero(Op.getOperand(0),AndRHS->getValue() & Mask, TLI); 223 return false; 224 case ISD::OR: 225 case ISD::XOR: 226 return MaskedValueIsZero(Op.getOperand(0), Mask, TLI) && 227 MaskedValueIsZero(Op.getOperand(1), Mask, TLI); 228 case ISD::SELECT: 229 return MaskedValueIsZero(Op.getOperand(1), Mask, TLI) && 230 MaskedValueIsZero(Op.getOperand(2), Mask, TLI); 231 case ISD::SELECT_CC: 232 return MaskedValueIsZero(Op.getOperand(2), Mask, TLI) && 233 MaskedValueIsZero(Op.getOperand(3), Mask, TLI); 234 case ISD::SRL: 235 // (ushr X, C1) & C2 == 0 iff X & (C2 << C1) == 0 236 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 237 uint64_t NewVal = Mask << ShAmt->getValue(); 238 SrcBits = MVT::getSizeInBits(Op.getValueType()); 239 if (SrcBits != 64) NewVal &= (1ULL << SrcBits)-1; 240 return MaskedValueIsZero(Op.getOperand(0), NewVal, TLI); 241 } 242 return false; 243 case ISD::SHL: 244 // (ushl X, C1) & C2 == 0 iff X & (C2 >> C1) == 0 245 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 246 uint64_t NewVal = Mask >> ShAmt->getValue(); 247 return MaskedValueIsZero(Op.getOperand(0), NewVal, TLI); 248 } 249 return false; 250 case ISD::ADD: 251 // (add X, Y) & C == 0 iff (X&C)|(Y&C) == 0 and all bits are low bits. 252 if ((Mask&(Mask+1)) == 0) { // All low bits 253 if (MaskedValueIsZero(Op.getOperand(0), Mask, TLI) && 254 MaskedValueIsZero(Op.getOperand(1), Mask, TLI)) 255 return true; 256 } 257 break; 258 case ISD::SUB: 259 if (ConstantSDNode *CLHS = dyn_cast<ConstantSDNode>(Op.getOperand(0))) { 260 // We know that the top bits of C-X are clear if X contains less bits 261 // than C (i.e. no wrap-around can happen). For example, 20-X is 262 // positive if we can prove that X is >= 0 and < 16. 263 unsigned Bits = MVT::getSizeInBits(CLHS->getValueType(0)); 264 if ((CLHS->getValue() & (1 << (Bits-1))) == 0) { // sign bit clear 265 unsigned NLZ = CountLeadingZeros_64(CLHS->getValue()+1); 266 uint64_t MaskV = (1ULL << (63-NLZ))-1; 267 if (MaskedValueIsZero(Op.getOperand(1), ~MaskV, TLI)) { 268 // High bits are clear this value is known to be >= C. 269 unsigned NLZ2 = CountLeadingZeros_64(CLHS->getValue()); 270 if ((Mask & ((1ULL << (64-NLZ2))-1)) == 0) 271 return true; 272 } 273 } 274 } 275 break; 276 case ISD::CTTZ: 277 case ISD::CTLZ: 278 case ISD::CTPOP: 279 // Bit counting instructions can not set the high bits of the result 280 // register. The max number of bits sets depends on the input. 281 return (Mask & (MVT::getSizeInBits(Op.getValueType())*2-1)) == 0; 282 default: break; 283 } 284 return false; 285} 286 287// isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc 288// that selects between the values 1 and 0, making it equivalent to a setcc. 289// Also, set the incoming LHS, RHS, and CC references to the appropriate 290// nodes based on the type of node we are checking. This simplifies life a 291// bit for the callers. 292static bool isSetCCEquivalent(SDOperand N, SDOperand &LHS, SDOperand &RHS, 293 SDOperand &CC) { 294 if (N.getOpcode() == ISD::SETCC) { 295 LHS = N.getOperand(0); 296 RHS = N.getOperand(1); 297 CC = N.getOperand(2); 298 return true; 299 } 300 if (N.getOpcode() == ISD::SELECT_CC && 301 N.getOperand(2).getOpcode() == ISD::Constant && 302 N.getOperand(3).getOpcode() == ISD::Constant && 303 cast<ConstantSDNode>(N.getOperand(2))->getValue() == 1 && 304 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) { 305 LHS = N.getOperand(0); 306 RHS = N.getOperand(1); 307 CC = N.getOperand(4); 308 return true; 309 } 310 return false; 311} 312 313// isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only 314// one use. If this is true, it allows the users to invert the operation for 315// free when it is profitable to do so. 316static bool isOneUseSetCC(SDOperand N) { 317 SDOperand N0, N1, N2; 318 if (isSetCCEquivalent(N, N0, N1, N2) && N.Val->hasOneUse()) 319 return true; 320 return false; 321} 322 323// FIXME: This should probably go in the ISD class rather than being duplicated 324// in several files. 325static bool isCommutativeBinOp(unsigned Opcode) { 326 switch (Opcode) { 327 case ISD::ADD: 328 case ISD::MUL: 329 case ISD::AND: 330 case ISD::OR: 331 case ISD::XOR: return true; 332 default: return false; // FIXME: Need commutative info for user ops! 333 } 334} 335 336void DAGCombiner::Run(bool RunningAfterLegalize) { 337 // set the instance variable, so that the various visit routines may use it. 338 AfterLegalize = RunningAfterLegalize; 339 340 // Add all the dag nodes to the worklist. 341 WorkList.insert(WorkList.end(), DAG.allnodes_begin(), DAG.allnodes_end()); 342 343 // Create a dummy node (which is not added to allnodes), that adds a reference 344 // to the root node, preventing it from being deleted, and tracking any 345 // changes of the root. 346 HandleSDNode Dummy(DAG.getRoot()); 347 348 // while the worklist isn't empty, inspect the node on the end of it and 349 // try and combine it. 350 while (!WorkList.empty()) { 351 SDNode *N = WorkList.back(); 352 WorkList.pop_back(); 353 354 // If N has no uses, it is dead. Make sure to revisit all N's operands once 355 // N is deleted from the DAG, since they too may now be dead or may have a 356 // reduced number of uses, allowing other xforms. 357 if (N->use_empty() && N != &Dummy) { 358 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 359 WorkList.push_back(N->getOperand(i).Val); 360 361 removeFromWorkList(N); 362 DAG.DeleteNode(N); 363 continue; 364 } 365 366 SDOperand RV = visit(N); 367 if (RV.Val) { 368 ++NodesCombined; 369 // If we get back the same node we passed in, rather than a new node or 370 // zero, we know that the node must have defined multiple values and 371 // CombineTo was used. Since CombineTo takes care of the worklist 372 // mechanics for us, we have no work to do in this case. 373 if (RV.Val != N) { 374 DEBUG(std::cerr << "\nReplacing "; N->dump(); 375 std::cerr << "\nWith: "; RV.Val->dump(); 376 std::cerr << '\n'); 377 std::vector<SDNode*> NowDead; 378 DAG.ReplaceAllUsesWith(N, std::vector<SDOperand>(1, RV), &NowDead); 379 380 // Push the new node and any users onto the worklist 381 WorkList.push_back(RV.Val); 382 AddUsersToWorkList(RV.Val); 383 384 // Nodes can end up on the worklist more than once. Make sure we do 385 // not process a node that has been replaced. 386 removeFromWorkList(N); 387 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 388 removeFromWorkList(NowDead[i]); 389 390 // Finally, since the node is now dead, remove it from the graph. 391 DAG.DeleteNode(N); 392 } 393 } 394 } 395 396 // If the root changed (e.g. it was a dead load, update the root). 397 DAG.setRoot(Dummy.getValue()); 398} 399 400SDOperand DAGCombiner::visit(SDNode *N) { 401 switch(N->getOpcode()) { 402 default: break; 403 case ISD::TokenFactor: return visitTokenFactor(N); 404 case ISD::ADD: return visitADD(N); 405 case ISD::SUB: return visitSUB(N); 406 case ISD::MUL: return visitMUL(N); 407 case ISD::SDIV: return visitSDIV(N); 408 case ISD::UDIV: return visitUDIV(N); 409 case ISD::SREM: return visitSREM(N); 410 case ISD::UREM: return visitUREM(N); 411 case ISD::MULHU: return visitMULHU(N); 412 case ISD::MULHS: return visitMULHS(N); 413 case ISD::AND: return visitAND(N); 414 case ISD::OR: return visitOR(N); 415 case ISD::XOR: return visitXOR(N); 416 case ISD::SHL: return visitSHL(N); 417 case ISD::SRA: return visitSRA(N); 418 case ISD::SRL: return visitSRL(N); 419 case ISD::CTLZ: return visitCTLZ(N); 420 case ISD::CTTZ: return visitCTTZ(N); 421 case ISD::CTPOP: return visitCTPOP(N); 422 case ISD::SELECT: return visitSELECT(N); 423 case ISD::SELECT_CC: return visitSELECT_CC(N); 424 case ISD::SETCC: return visitSETCC(N); 425 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N); 426 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N); 427 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N); 428 case ISD::TRUNCATE: return visitTRUNCATE(N); 429 case ISD::FADD: return visitFADD(N); 430 case ISD::FSUB: return visitFSUB(N); 431 case ISD::FMUL: return visitFMUL(N); 432 case ISD::FDIV: return visitFDIV(N); 433 case ISD::FREM: return visitFREM(N); 434 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N); 435 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N); 436 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N); 437 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N); 438 case ISD::FP_ROUND: return visitFP_ROUND(N); 439 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N); 440 case ISD::FP_EXTEND: return visitFP_EXTEND(N); 441 case ISD::FNEG: return visitFNEG(N); 442 case ISD::FABS: return visitFABS(N); 443 case ISD::BRCOND: return visitBRCOND(N); 444 case ISD::BRCONDTWOWAY: return visitBRCONDTWOWAY(N); 445 case ISD::BR_CC: return visitBR_CC(N); 446 case ISD::BRTWOWAY_CC: return visitBRTWOWAY_CC(N); 447 case ISD::LOAD: return visitLOAD(N); 448 case ISD::STORE: return visitSTORE(N); 449 } 450 return SDOperand(); 451} 452 453SDOperand DAGCombiner::visitTokenFactor(SDNode *N) { 454 std::vector<SDOperand> Ops; 455 bool Changed = false; 456 457 // If the token factor has two operands and one is the entry token, replace 458 // the token factor with the other operand. 459 if (N->getNumOperands() == 2) { 460 if (N->getOperand(0).getOpcode() == ISD::EntryToken) 461 return N->getOperand(1); 462 if (N->getOperand(1).getOpcode() == ISD::EntryToken) 463 return N->getOperand(0); 464 } 465 // fold (tokenfactor (tokenfactor)) -> tokenfactor 466 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { 467 SDOperand Op = N->getOperand(i); 468 if (Op.getOpcode() == ISD::TokenFactor && Op.hasOneUse()) { 469 Changed = true; 470 for (unsigned j = 0, e = Op.getNumOperands(); j != e; ++j) 471 Ops.push_back(Op.getOperand(j)); 472 } else { 473 Ops.push_back(Op); 474 } 475 } 476 if (Changed) 477 return DAG.getNode(ISD::TokenFactor, MVT::Other, Ops); 478 return SDOperand(); 479} 480 481SDOperand DAGCombiner::visitADD(SDNode *N) { 482 SDOperand N0 = N->getOperand(0); 483 SDOperand N1 = N->getOperand(1); 484 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 485 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 486 MVT::ValueType VT = N0.getValueType(); 487 488 // fold (add c1, c2) -> c1+c2 489 if (N0C && N1C) 490 return DAG.getConstant(N0C->getValue() + N1C->getValue(), VT); 491 // canonicalize constant to RHS 492 if (N0C && !N1C) { 493 std::swap(N0, N1); 494 std::swap(N0C, N1C); 495 } 496 // fold (add x, 0) -> x 497 if (N1C && N1C->isNullValue()) 498 return N0; 499 // fold (add (add x, c1), c2) -> (add x, c1+c2) 500 if (N1C && N0.getOpcode() == ISD::ADD) { 501 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0)); 502 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 503 if (N00C) 504 return DAG.getNode(ISD::ADD, VT, N0.getOperand(1), 505 DAG.getConstant(N1C->getValue()+N00C->getValue(), VT)); 506 if (N01C) 507 return DAG.getNode(ISD::ADD, VT, N0.getOperand(0), 508 DAG.getConstant(N1C->getValue()+N01C->getValue(), VT)); 509 } 510 // fold ((0-A) + B) -> B-A 511 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) && 512 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue()) 513 return DAG.getNode(ISD::SUB, VT, N1, N0.getOperand(1)); 514 // fold (A + (0-B)) -> A-B 515 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) && 516 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue()) 517 return DAG.getNode(ISD::SUB, VT, N0, N1.getOperand(1)); 518 // fold (A+(B-A)) -> B 519 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1)) 520 return N1.getOperand(0); 521 return SDOperand(); 522} 523 524SDOperand DAGCombiner::visitSUB(SDNode *N) { 525 SDOperand N0 = N->getOperand(0); 526 SDOperand N1 = N->getOperand(1); 527 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 528 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 529 530 // fold (sub c1, c2) -> c1-c2 531 if (N0C && N1C) 532 return DAG.getConstant(N0C->getValue() - N1C->getValue(), 533 N->getValueType(0)); 534 // fold (sub x, c) -> (add x, -c) 535 if (N1C) 536 return DAG.getNode(ISD::ADD, N0.getValueType(), N0, 537 DAG.getConstant(-N1C->getValue(), N0.getValueType())); 538 539 // fold (A+B)-A -> B 540 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1) 541 return N0.getOperand(1); 542 // fold (A+B)-B -> A 543 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1) 544 return N0.getOperand(0); 545 return SDOperand(); 546} 547 548SDOperand DAGCombiner::visitMUL(SDNode *N) { 549 SDOperand N0 = N->getOperand(0); 550 SDOperand N1 = N->getOperand(1); 551 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 552 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 553 MVT::ValueType VT = N0.getValueType(); 554 555 // fold (mul c1, c2) -> c1*c2 556 if (N0C && N1C) 557 return DAG.getConstant(N0C->getValue() * N1C->getValue(), 558 N->getValueType(0)); 559 // canonicalize constant to RHS 560 if (N0C && !N1C) { 561 std::swap(N0, N1); 562 std::swap(N0C, N1C); 563 } 564 // fold (mul x, 0) -> 0 565 if (N1C && N1C->isNullValue()) 566 return N1; 567 // fold (mul x, -1) -> 0-x 568 if (N1C && N1C->isAllOnesValue()) 569 return DAG.getNode(ISD::SUB, N->getValueType(0), 570 DAG.getConstant(0, N->getValueType(0)), N0); 571 // fold (mul x, (1 << c)) -> x << c 572 if (N1C && isPowerOf2_64(N1C->getValue())) 573 return DAG.getNode(ISD::SHL, N->getValueType(0), N0, 574 DAG.getConstant(Log2_64(N1C->getValue()), 575 TLI.getShiftAmountTy())); 576 // fold (mul (mul x, c1), c2) -> (mul x, c1*c2) 577 if (N1C && N0.getOpcode() == ISD::MUL) { 578 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0)); 579 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 580 if (N00C) 581 return DAG.getNode(ISD::MUL, VT, N0.getOperand(1), 582 DAG.getConstant(N1C->getValue()*N00C->getValue(), VT)); 583 if (N01C) 584 return DAG.getNode(ISD::MUL, VT, N0.getOperand(0), 585 DAG.getConstant(N1C->getValue()*N01C->getValue(), VT)); 586 } 587 return SDOperand(); 588} 589 590SDOperand DAGCombiner::visitSDIV(SDNode *N) { 591 SDOperand N0 = N->getOperand(0); 592 SDOperand N1 = N->getOperand(1); 593 MVT::ValueType VT = N->getValueType(0); 594 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 595 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 596 597 // fold (sdiv c1, c2) -> c1/c2 598 if (N0C && N1C && !N1C->isNullValue()) 599 return DAG.getConstant(N0C->getSignExtended() / N1C->getSignExtended(), 600 N->getValueType(0)); 601 // If we know the sign bits of both operands are zero, strength reduce to a 602 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2 603 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1); 604 if (MaskedValueIsZero(N1, SignBit, TLI) && 605 MaskedValueIsZero(N0, SignBit, TLI)) 606 return DAG.getNode(ISD::UDIV, N1.getValueType(), N0, N1); 607 return SDOperand(); 608} 609 610SDOperand DAGCombiner::visitUDIV(SDNode *N) { 611 SDOperand N0 = N->getOperand(0); 612 SDOperand N1 = N->getOperand(1); 613 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 614 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 615 616 // fold (udiv c1, c2) -> c1/c2 617 if (N0C && N1C && !N1C->isNullValue()) 618 return DAG.getConstant(N0C->getValue() / N1C->getValue(), 619 N->getValueType(0)); 620 // fold (udiv x, (1 << c)) -> x >>u c 621 if (N1C && isPowerOf2_64(N1C->getValue())) 622 return DAG.getNode(ISD::SRL, N->getValueType(0), N0, 623 DAG.getConstant(Log2_64(N1C->getValue()), 624 TLI.getShiftAmountTy())); 625 return SDOperand(); 626} 627 628SDOperand DAGCombiner::visitSREM(SDNode *N) { 629 SDOperand N0 = N->getOperand(0); 630 SDOperand N1 = N->getOperand(1); 631 MVT::ValueType VT = N->getValueType(0); 632 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 633 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 634 635 // fold (srem c1, c2) -> c1%c2 636 if (N0C && N1C && !N1C->isNullValue()) 637 return DAG.getConstant(N0C->getSignExtended() % N1C->getSignExtended(), 638 N->getValueType(0)); 639 // If we know the sign bits of both operands are zero, strength reduce to a 640 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15 641 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1); 642 if (MaskedValueIsZero(N1, SignBit, TLI) && 643 MaskedValueIsZero(N0, SignBit, TLI)) 644 return DAG.getNode(ISD::UREM, N1.getValueType(), N0, N1); 645 return SDOperand(); 646} 647 648SDOperand DAGCombiner::visitUREM(SDNode *N) { 649 SDOperand N0 = N->getOperand(0); 650 SDOperand N1 = N->getOperand(1); 651 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 652 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 653 654 // fold (urem c1, c2) -> c1%c2 655 if (N0C && N1C && !N1C->isNullValue()) 656 return DAG.getConstant(N0C->getValue() % N1C->getValue(), 657 N->getValueType(0)); 658 // fold (urem x, pow2) -> (and x, pow2-1) 659 if (N1C && !N1C->isNullValue() && isPowerOf2_64(N1C->getValue())) 660 return DAG.getNode(ISD::AND, N0.getValueType(), N0, 661 DAG.getConstant(N1C->getValue()-1, N1.getValueType())); 662 return SDOperand(); 663} 664 665SDOperand DAGCombiner::visitMULHS(SDNode *N) { 666 SDOperand N0 = N->getOperand(0); 667 SDOperand N1 = N->getOperand(1); 668 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 669 670 // fold (mulhs x, 0) -> 0 671 if (N1C && N1C->isNullValue()) 672 return N1; 673 // fold (mulhs x, 1) -> (sra x, size(x)-1) 674 if (N1C && N1C->getValue() == 1) 675 return DAG.getNode(ISD::SRA, N0.getValueType(), N0, 676 DAG.getConstant(MVT::getSizeInBits(N0.getValueType())-1, 677 TLI.getShiftAmountTy())); 678 return SDOperand(); 679} 680 681SDOperand DAGCombiner::visitMULHU(SDNode *N) { 682 SDOperand N0 = N->getOperand(0); 683 SDOperand N1 = N->getOperand(1); 684 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 685 686 // fold (mulhu x, 0) -> 0 687 if (N1C && N1C->isNullValue()) 688 return N1; 689 // fold (mulhu x, 1) -> 0 690 if (N1C && N1C->getValue() == 1) 691 return DAG.getConstant(0, N0.getValueType()); 692 return SDOperand(); 693} 694 695SDOperand DAGCombiner::visitAND(SDNode *N) { 696 SDOperand N0 = N->getOperand(0); 697 SDOperand N1 = N->getOperand(1); 698 SDOperand LL, LR, RL, RR, CC0, CC1; 699 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 700 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 701 MVT::ValueType VT = N1.getValueType(); 702 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 703 704 // fold (and c1, c2) -> c1&c2 705 if (N0C && N1C) 706 return DAG.getConstant(N0C->getValue() & N1C->getValue(), VT); 707 // canonicalize constant to RHS 708 if (N0C && !N1C) { 709 std::swap(N0, N1); 710 std::swap(N0C, N1C); 711 } 712 // fold (and x, -1) -> x 713 if (N1C && N1C->isAllOnesValue()) 714 return N0; 715 // if (and x, c) is known to be zero, return 0 716 if (N1C && MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits),TLI)) 717 return DAG.getConstant(0, VT); 718 // fold (and x, c) -> x iff (x & ~c) == 0 719 if (N1C && MaskedValueIsZero(N0,~N1C->getValue() & (~0ULL>>(64-OpSizeInBits)), 720 TLI)) 721 return N0; 722 // fold (and (and x, c1), c2) -> (and x, c1^c2) 723 if (N1C && N0.getOpcode() == ISD::AND) { 724 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0)); 725 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 726 if (N00C) 727 return DAG.getNode(ISD::AND, VT, N0.getOperand(1), 728 DAG.getConstant(N1C->getValue()&N00C->getValue(), VT)); 729 if (N01C) 730 return DAG.getNode(ISD::AND, VT, N0.getOperand(0), 731 DAG.getConstant(N1C->getValue()&N01C->getValue(), VT)); 732 } 733 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1) 734 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG) { 735 unsigned ExtendBits = 736 MVT::getSizeInBits(cast<VTSDNode>(N0.getOperand(1))->getVT()); 737 if ((N1C->getValue() & (~0ULL << ExtendBits)) == 0) 738 return DAG.getNode(ISD::AND, VT, N0.getOperand(0), N1); 739 } 740 // fold (and (or x, 0xFFFF), 0xFF) -> 0xFF 741 if (N0.getOpcode() == ISD::OR && N1C) 742 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 743 if ((ORI->getValue() & N1C->getValue()) == N1C->getValue()) 744 return N1; 745 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y)) 746 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 747 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 748 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 749 750 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 751 MVT::isInteger(LL.getValueType())) { 752 // fold (X == 0) & (Y == 0) -> (X|Y == 0) 753 if (cast<ConstantSDNode>(LR)->getValue() == 0 && Op1 == ISD::SETEQ) { 754 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 755 WorkList.push_back(ORNode.Val); 756 return DAG.getSetCC(VT, ORNode, LR, Op1); 757 } 758 // fold (X == -1) & (Y == -1) -> (X&Y == -1) 759 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) { 760 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL); 761 WorkList.push_back(ANDNode.Val); 762 return DAG.getSetCC(VT, ANDNode, LR, Op1); 763 } 764 // fold (X > -1) & (Y > -1) -> (X|Y > -1) 765 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) { 766 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 767 WorkList.push_back(ORNode.Val); 768 return DAG.getSetCC(VT, ORNode, LR, Op1); 769 } 770 } 771 // canonicalize equivalent to ll == rl 772 if (LL == RR && LR == RL) { 773 Op1 = ISD::getSetCCSwappedOperands(Op1); 774 std::swap(RL, RR); 775 } 776 if (LL == RL && LR == RR) { 777 bool isInteger = MVT::isInteger(LL.getValueType()); 778 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger); 779 if (Result != ISD::SETCC_INVALID) 780 return DAG.getSetCC(N0.getValueType(), LL, LR, Result); 781 } 782 } 783 // fold (and (zext x), (zext y)) -> (zext (and x, y)) 784 if (N0.getOpcode() == ISD::ZERO_EXTEND && 785 N1.getOpcode() == ISD::ZERO_EXTEND && 786 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) { 787 SDOperand ANDNode = DAG.getNode(ISD::AND, N0.getOperand(0).getValueType(), 788 N0.getOperand(0), N1.getOperand(0)); 789 WorkList.push_back(ANDNode.Val); 790 return DAG.getNode(ISD::ZERO_EXTEND, VT, ANDNode); 791 } 792 // fold (and (shl/srl x), (shl/srl y)) -> (shl/srl (and x, y)) 793 if (((N0.getOpcode() == ISD::SHL && N1.getOpcode() == ISD::SHL) || 794 (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SRL)) && 795 N0.getOperand(1) == N1.getOperand(1)) { 796 SDOperand ANDNode = DAG.getNode(ISD::AND, N0.getOperand(0).getValueType(), 797 N0.getOperand(0), N1.getOperand(0)); 798 WorkList.push_back(ANDNode.Val); 799 return DAG.getNode(N0.getOpcode(), VT, ANDNode, N0.getOperand(1)); 800 } 801 // fold (zext_inreg (extload x)) -> (zextload x) 802 if (N1C && N0.getOpcode() == ISD::EXTLOAD) { 803 MVT::ValueType EVT = cast<VTSDNode>(N0.getOperand(3))->getVT(); 804 // If we zero all the possible extended bits, then we can turn this into 805 // a zextload if we are running before legalize or the operation is legal. 806 if (MaskedValueIsZero(SDOperand(N,0), ~0ULL<<MVT::getSizeInBits(EVT),TLI) && 807 (!AfterLegalize || TLI.isOperationLegal(ISD::ZEXTLOAD, EVT))) { 808 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0), 809 N0.getOperand(1), N0.getOperand(2), 810 EVT); 811 WorkList.push_back(N); 812 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 813 return SDOperand(); 814 } 815 } 816 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use 817 if (N1C && N0.getOpcode() == ISD::SEXTLOAD && N0.Val->hasNUsesOfValue(1, 0)) { 818 MVT::ValueType EVT = cast<VTSDNode>(N0.getOperand(3))->getVT(); 819 // If we zero all the possible extended bits, then we can turn this into 820 // a zextload if we are running before legalize or the operation is legal. 821 if (MaskedValueIsZero(SDOperand(N,0), ~0ULL<<MVT::getSizeInBits(EVT),TLI) && 822 (!AfterLegalize || TLI.isOperationLegal(ISD::ZEXTLOAD, EVT))) { 823 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0), 824 N0.getOperand(1), N0.getOperand(2), 825 EVT); 826 WorkList.push_back(N); 827 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 828 return SDOperand(); 829 } 830 } 831 return SDOperand(); 832} 833 834SDOperand DAGCombiner::visitOR(SDNode *N) { 835 SDOperand N0 = N->getOperand(0); 836 SDOperand N1 = N->getOperand(1); 837 SDOperand LL, LR, RL, RR, CC0, CC1; 838 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 839 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 840 MVT::ValueType VT = N1.getValueType(); 841 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 842 843 // fold (or c1, c2) -> c1|c2 844 if (N0C && N1C) 845 return DAG.getConstant(N0C->getValue() | N1C->getValue(), 846 N->getValueType(0)); 847 // canonicalize constant to RHS 848 if (N0C && !N1C) { 849 std::swap(N0, N1); 850 std::swap(N0C, N1C); 851 } 852 // fold (or x, 0) -> x 853 if (N1C && N1C->isNullValue()) 854 return N0; 855 // fold (or x, -1) -> -1 856 if (N1C && N1C->isAllOnesValue()) 857 return N1; 858 // fold (or x, c) -> c iff (x & ~c) == 0 859 if (N1C && MaskedValueIsZero(N0,~N1C->getValue() & (~0ULL>>(64-OpSizeInBits)), 860 TLI)) 861 return N1; 862 // fold (or (or x, c1), c2) -> (or x, c1|c2) 863 if (N1C && N0.getOpcode() == ISD::OR) { 864 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0)); 865 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 866 if (N00C) 867 return DAG.getNode(ISD::OR, VT, N0.getOperand(1), 868 DAG.getConstant(N1C->getValue()|N00C->getValue(), VT)); 869 if (N01C) 870 return DAG.getNode(ISD::OR, VT, N0.getOperand(0), 871 DAG.getConstant(N1C->getValue()|N01C->getValue(), VT)); 872 } 873 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y)) 874 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 875 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 876 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 877 878 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 879 MVT::isInteger(LL.getValueType())) { 880 // fold (X != 0) | (Y != 0) -> (X|Y != 0) 881 // fold (X < 0) | (Y < 0) -> (X|Y < 0) 882 if (cast<ConstantSDNode>(LR)->getValue() == 0 && 883 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) { 884 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 885 WorkList.push_back(ORNode.Val); 886 return DAG.getSetCC(VT, ORNode, LR, Op1); 887 } 888 // fold (X != -1) | (Y != -1) -> (X&Y != -1) 889 // fold (X > -1) | (Y > -1) -> (X&Y > -1) 890 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && 891 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) { 892 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL); 893 WorkList.push_back(ANDNode.Val); 894 return DAG.getSetCC(VT, ANDNode, LR, Op1); 895 } 896 } 897 // canonicalize equivalent to ll == rl 898 if (LL == RR && LR == RL) { 899 Op1 = ISD::getSetCCSwappedOperands(Op1); 900 std::swap(RL, RR); 901 } 902 if (LL == RL && LR == RR) { 903 bool isInteger = MVT::isInteger(LL.getValueType()); 904 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger); 905 if (Result != ISD::SETCC_INVALID) 906 return DAG.getSetCC(N0.getValueType(), LL, LR, Result); 907 } 908 } 909 // fold (or (zext x), (zext y)) -> (zext (or x, y)) 910 if (N0.getOpcode() == ISD::ZERO_EXTEND && 911 N1.getOpcode() == ISD::ZERO_EXTEND && 912 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) { 913 SDOperand ORNode = DAG.getNode(ISD::OR, N0.getOperand(0).getValueType(), 914 N0.getOperand(0), N1.getOperand(0)); 915 WorkList.push_back(ORNode.Val); 916 return DAG.getNode(ISD::ZERO_EXTEND, VT, ORNode); 917 } 918 return SDOperand(); 919} 920 921SDOperand DAGCombiner::visitXOR(SDNode *N) { 922 SDOperand N0 = N->getOperand(0); 923 SDOperand N1 = N->getOperand(1); 924 SDOperand LHS, RHS, CC; 925 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 926 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 927 MVT::ValueType VT = N0.getValueType(); 928 929 // fold (xor c1, c2) -> c1^c2 930 if (N0C && N1C) 931 return DAG.getConstant(N0C->getValue() ^ N1C->getValue(), VT); 932 // canonicalize constant to RHS 933 if (N0C && !N1C) { 934 std::swap(N0, N1); 935 std::swap(N0C, N1C); 936 } 937 // fold (xor x, 0) -> x 938 if (N1C && N1C->isNullValue()) 939 return N0; 940 // fold !(x cc y) -> (x !cc y) 941 if (N1C && N1C->getValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) { 942 bool isInt = MVT::isInteger(LHS.getValueType()); 943 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(), 944 isInt); 945 if (N0.getOpcode() == ISD::SETCC) 946 return DAG.getSetCC(VT, LHS, RHS, NotCC); 947 if (N0.getOpcode() == ISD::SELECT_CC) 948 return DAG.getSelectCC(LHS, RHS, N0.getOperand(2),N0.getOperand(3),NotCC); 949 assert(0 && "Unhandled SetCC Equivalent!"); 950 abort(); 951 } 952 // fold !(x or y) -> (!x and !y) iff x or y are setcc 953 if (N1C && N1C->getValue() == 1 && 954 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 955 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1); 956 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) { 957 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 958 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS 959 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS 960 WorkList.push_back(LHS.Val); WorkList.push_back(RHS.Val); 961 return DAG.getNode(NewOpcode, VT, LHS, RHS); 962 } 963 } 964 // fold !(x or y) -> (!x and !y) iff x or y are constants 965 if (N1C && N1C->isAllOnesValue() && 966 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 967 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1); 968 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) { 969 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 970 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS 971 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS 972 WorkList.push_back(LHS.Val); WorkList.push_back(RHS.Val); 973 return DAG.getNode(NewOpcode, VT, LHS, RHS); 974 } 975 } 976 // fold (xor (xor x, c1), c2) -> (xor x, c1^c2) 977 if (N1C && N0.getOpcode() == ISD::XOR) { 978 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0)); 979 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 980 if (N00C) 981 return DAG.getNode(ISD::XOR, VT, N0.getOperand(1), 982 DAG.getConstant(N1C->getValue()^N00C->getValue(), VT)); 983 if (N01C) 984 return DAG.getNode(ISD::XOR, VT, N0.getOperand(0), 985 DAG.getConstant(N1C->getValue()^N01C->getValue(), VT)); 986 } 987 // fold (xor x, x) -> 0 988 if (N0 == N1) 989 return DAG.getConstant(0, VT); 990 // fold (xor (zext x), (zext y)) -> (zext (xor x, y)) 991 if (N0.getOpcode() == ISD::ZERO_EXTEND && 992 N1.getOpcode() == ISD::ZERO_EXTEND && 993 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) { 994 SDOperand XORNode = DAG.getNode(ISD::XOR, N0.getOperand(0).getValueType(), 995 N0.getOperand(0), N1.getOperand(0)); 996 WorkList.push_back(XORNode.Val); 997 return DAG.getNode(ISD::ZERO_EXTEND, VT, XORNode); 998 } 999 return SDOperand(); 1000} 1001 1002SDOperand DAGCombiner::visitSHL(SDNode *N) { 1003 SDOperand N0 = N->getOperand(0); 1004 SDOperand N1 = N->getOperand(1); 1005 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1006 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1007 MVT::ValueType VT = N0.getValueType(); 1008 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 1009 1010 // fold (shl c1, c2) -> c1<<c2 1011 if (N0C && N1C) 1012 return DAG.getConstant(N0C->getValue() << N1C->getValue(), VT); 1013 // fold (shl 0, x) -> 0 1014 if (N0C && N0C->isNullValue()) 1015 return N0; 1016 // fold (shl x, c >= size(x)) -> undef 1017 if (N1C && N1C->getValue() >= OpSizeInBits) 1018 return DAG.getNode(ISD::UNDEF, VT); 1019 // fold (shl x, 0) -> x 1020 if (N1C && N1C->isNullValue()) 1021 return N0; 1022 // if (shl x, c) is known to be zero, return 0 1023 if (N1C && MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits),TLI)) 1024 return DAG.getConstant(0, VT); 1025 // fold (shl (shl x, c1), c2) -> 0 or (shl x, c1+c2) 1026 if (N1C && N0.getOpcode() == ISD::SHL && 1027 N0.getOperand(1).getOpcode() == ISD::Constant) { 1028 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 1029 uint64_t c2 = N1C->getValue(); 1030 if (c1 + c2 > OpSizeInBits) 1031 return DAG.getConstant(0, VT); 1032 return DAG.getNode(ISD::SHL, VT, N0.getOperand(0), 1033 DAG.getConstant(c1 + c2, N1.getValueType())); 1034 } 1035 // fold (shl (srl x, c1), c2) -> (shl (and x, -1 << c1), c2-c1) or 1036 // (srl (and x, -1 << c1), c1-c2) 1037 if (N1C && N0.getOpcode() == ISD::SRL && 1038 N0.getOperand(1).getOpcode() == ISD::Constant) { 1039 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 1040 uint64_t c2 = N1C->getValue(); 1041 SDOperand Mask = DAG.getNode(ISD::AND, VT, N0.getOperand(0), 1042 DAG.getConstant(~0ULL << c1, VT)); 1043 if (c2 > c1) 1044 return DAG.getNode(ISD::SHL, VT, Mask, 1045 DAG.getConstant(c2-c1, N1.getValueType())); 1046 else 1047 return DAG.getNode(ISD::SRL, VT, Mask, 1048 DAG.getConstant(c1-c2, N1.getValueType())); 1049 } 1050 // fold (shl (sra x, c1), c1) -> (and x, -1 << c1) 1051 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) 1052 return DAG.getNode(ISD::AND, VT, N0.getOperand(0), 1053 DAG.getConstant(~0ULL << N1C->getValue(), VT)); 1054 return SDOperand(); 1055} 1056 1057SDOperand DAGCombiner::visitSRA(SDNode *N) { 1058 SDOperand N0 = N->getOperand(0); 1059 SDOperand N1 = N->getOperand(1); 1060 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1061 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1062 MVT::ValueType VT = N0.getValueType(); 1063 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 1064 1065 // fold (sra c1, c2) -> c1>>c2 1066 if (N0C && N1C) 1067 return DAG.getConstant(N0C->getSignExtended() >> N1C->getValue(), VT); 1068 // fold (sra 0, x) -> 0 1069 if (N0C && N0C->isNullValue()) 1070 return N0; 1071 // fold (sra -1, x) -> -1 1072 if (N0C && N0C->isAllOnesValue()) 1073 return N0; 1074 // fold (sra x, c >= size(x)) -> undef 1075 if (N1C && N1C->getValue() >= OpSizeInBits) 1076 return DAG.getNode(ISD::UNDEF, VT); 1077 // fold (sra x, 0) -> x 1078 if (N1C && N1C->isNullValue()) 1079 return N0; 1080 // If the sign bit is known to be zero, switch this to a SRL. 1081 if (MaskedValueIsZero(N0, (1ULL << (OpSizeInBits-1)), TLI)) 1082 return DAG.getNode(ISD::SRL, VT, N0, N1); 1083 return SDOperand(); 1084} 1085 1086SDOperand DAGCombiner::visitSRL(SDNode *N) { 1087 SDOperand N0 = N->getOperand(0); 1088 SDOperand N1 = N->getOperand(1); 1089 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1090 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1091 MVT::ValueType VT = N0.getValueType(); 1092 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 1093 1094 // fold (srl c1, c2) -> c1 >>u c2 1095 if (N0C && N1C) 1096 return DAG.getConstant(N0C->getValue() >> N1C->getValue(), VT); 1097 // fold (srl 0, x) -> 0 1098 if (N0C && N0C->isNullValue()) 1099 return N0; 1100 // fold (srl x, c >= size(x)) -> undef 1101 if (N1C && N1C->getValue() >= OpSizeInBits) 1102 return DAG.getNode(ISD::UNDEF, VT); 1103 // fold (srl x, 0) -> x 1104 if (N1C && N1C->isNullValue()) 1105 return N0; 1106 // if (srl x, c) is known to be zero, return 0 1107 if (N1C && MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits),TLI)) 1108 return DAG.getConstant(0, VT); 1109 // fold (srl (srl x, c1), c2) -> 0 or (srl x, c1+c2) 1110 if (N1C && N0.getOpcode() == ISD::SRL && 1111 N0.getOperand(1).getOpcode() == ISD::Constant) { 1112 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 1113 uint64_t c2 = N1C->getValue(); 1114 if (c1 + c2 > OpSizeInBits) 1115 return DAG.getConstant(0, VT); 1116 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0), 1117 DAG.getConstant(c1 + c2, N1.getValueType())); 1118 } 1119 return SDOperand(); 1120} 1121 1122SDOperand DAGCombiner::visitCTLZ(SDNode *N) { 1123 SDOperand N0 = N->getOperand(0); 1124 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1125 1126 // fold (ctlz c1) -> c2 1127 if (N0C) 1128 return DAG.getConstant(CountLeadingZeros_64(N0C->getValue()), 1129 N0.getValueType()); 1130 return SDOperand(); 1131} 1132 1133SDOperand DAGCombiner::visitCTTZ(SDNode *N) { 1134 SDOperand N0 = N->getOperand(0); 1135 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1136 1137 // fold (cttz c1) -> c2 1138 if (N0C) 1139 return DAG.getConstant(CountTrailingZeros_64(N0C->getValue()), 1140 N0.getValueType()); 1141 return SDOperand(); 1142} 1143 1144SDOperand DAGCombiner::visitCTPOP(SDNode *N) { 1145 SDOperand N0 = N->getOperand(0); 1146 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1147 1148 // fold (ctpop c1) -> c2 1149 if (N0C) 1150 return DAG.getConstant(CountPopulation_64(N0C->getValue()), 1151 N0.getValueType()); 1152 return SDOperand(); 1153} 1154 1155SDOperand DAGCombiner::visitSELECT(SDNode *N) { 1156 SDOperand N0 = N->getOperand(0); 1157 SDOperand N1 = N->getOperand(1); 1158 SDOperand N2 = N->getOperand(2); 1159 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1160 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1161 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2); 1162 MVT::ValueType VT = N->getValueType(0); 1163 1164 // fold select C, X, X -> X 1165 if (N1 == N2) 1166 return N1; 1167 // fold select true, X, Y -> X 1168 if (N0C && !N0C->isNullValue()) 1169 return N1; 1170 // fold select false, X, Y -> Y 1171 if (N0C && N0C->isNullValue()) 1172 return N2; 1173 // fold select C, 1, X -> C | X 1174 if (MVT::i1 == VT && N1C && N1C->getValue() == 1) 1175 return DAG.getNode(ISD::OR, VT, N0, N2); 1176 // fold select C, 0, X -> ~C & X 1177 // FIXME: this should check for C type == X type, not i1? 1178 if (MVT::i1 == VT && N1C && N1C->isNullValue()) { 1179 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT)); 1180 WorkList.push_back(XORNode.Val); 1181 return DAG.getNode(ISD::AND, VT, XORNode, N2); 1182 } 1183 // fold select C, X, 1 -> ~C | X 1184 if (MVT::i1 == VT && N2C && N2C->getValue() == 1) { 1185 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT)); 1186 WorkList.push_back(XORNode.Val); 1187 return DAG.getNode(ISD::OR, VT, XORNode, N1); 1188 } 1189 // fold select C, X, 0 -> C & X 1190 // FIXME: this should check for C type == X type, not i1? 1191 if (MVT::i1 == VT && N2C && N2C->isNullValue()) 1192 return DAG.getNode(ISD::AND, VT, N0, N1); 1193 // fold X ? X : Y --> X ? 1 : Y --> X | Y 1194 if (MVT::i1 == VT && N0 == N1) 1195 return DAG.getNode(ISD::OR, VT, N0, N2); 1196 // fold X ? Y : X --> X ? Y : 0 --> X & Y 1197 if (MVT::i1 == VT && N0 == N2) 1198 return DAG.getNode(ISD::AND, VT, N0, N1); 1199 // fold selects based on a setcc into other things, such as min/max/abs 1200 if (N0.getOpcode() == ISD::SETCC) 1201 return SimplifySelect(N0, N1, N2); 1202 return SDOperand(); 1203} 1204 1205SDOperand DAGCombiner::visitSELECT_CC(SDNode *N) { 1206 SDOperand N0 = N->getOperand(0); 1207 SDOperand N1 = N->getOperand(1); 1208 SDOperand N2 = N->getOperand(2); 1209 SDOperand N3 = N->getOperand(3); 1210 SDOperand N4 = N->getOperand(4); 1211 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1212 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1213 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2); 1214 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get(); 1215 1216 // Determine if the condition we're dealing with is constant 1217 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false); 1218 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val); 1219 1220 // fold select_cc lhs, rhs, x, x, cc -> x 1221 if (N2 == N3) 1222 return N2; 1223 // fold select_cc into other things, such as min/max/abs 1224 return SimplifySelectCC(N0, N1, N2, N3, CC); 1225} 1226 1227SDOperand DAGCombiner::visitSETCC(SDNode *N) { 1228 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1), 1229 cast<CondCodeSDNode>(N->getOperand(2))->get()); 1230} 1231 1232SDOperand DAGCombiner::visitSIGN_EXTEND(SDNode *N) { 1233 SDOperand N0 = N->getOperand(0); 1234 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1235 MVT::ValueType VT = N->getValueType(0); 1236 1237 // fold (sext c1) -> c1 1238 if (N0C) 1239 return DAG.getConstant(N0C->getSignExtended(), VT); 1240 // fold (sext (sext x)) -> (sext x) 1241 if (N0.getOpcode() == ISD::SIGN_EXTEND) 1242 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0.getOperand(0)); 1243 // fold (sext (sextload x)) -> (sextload x) 1244 if (N0.getOpcode() == ISD::SEXTLOAD && VT == N0.getValueType()) 1245 return N0; 1246 // fold (sext (load x)) -> (sextload x) 1247 if (N0.getOpcode() == ISD::LOAD && N0.Val->hasNUsesOfValue(1, 0)) { 1248 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N0.getOperand(0), 1249 N0.getOperand(1), N0.getOperand(2), 1250 N0.getValueType()); 1251 CombineTo(N0.Val, ExtLoad, ExtLoad.getOperand(0)); 1252 WorkList.push_back(N); 1253 return SDOperand(); 1254 } 1255 return SDOperand(); 1256} 1257 1258SDOperand DAGCombiner::visitZERO_EXTEND(SDNode *N) { 1259 SDOperand N0 = N->getOperand(0); 1260 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1261 MVT::ValueType VT = N->getValueType(0); 1262 1263 // fold (zext c1) -> c1 1264 if (N0C) 1265 return DAG.getConstant(N0C->getValue(), VT); 1266 // fold (zext (zext x)) -> (zext x) 1267 if (N0.getOpcode() == ISD::ZERO_EXTEND) 1268 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0.getOperand(0)); 1269 return SDOperand(); 1270} 1271 1272SDOperand DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) { 1273 SDOperand N0 = N->getOperand(0); 1274 SDOperand N1 = N->getOperand(1); 1275 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1276 MVT::ValueType VT = N->getValueType(0); 1277 MVT::ValueType EVT = cast<VTSDNode>(N1)->getVT(); 1278 unsigned EVTBits = MVT::getSizeInBits(EVT); 1279 1280 // fold (sext_in_reg c1) -> c1 1281 if (N0C) { 1282 SDOperand Truncate = DAG.getConstant(N0C->getValue(), EVT); 1283 return DAG.getNode(ISD::SIGN_EXTEND, VT, Truncate); 1284 } 1285 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt1 1286 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 1287 cast<VTSDNode>(N0.getOperand(1))->getVT() < EVT) { 1288 return N0; 1289 } 1290 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2 1291 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 1292 EVT < cast<VTSDNode>(N0.getOperand(1))->getVT()) { 1293 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), N1); 1294 } 1295 // fold (sext_in_reg (assert_sext x)) -> (assert_sext x) 1296 if (N0.getOpcode() == ISD::AssertSext && 1297 cast<VTSDNode>(N0.getOperand(1))->getVT() <= EVT) { 1298 return N0; 1299 } 1300 // fold (sext_in_reg (sextload x)) -> (sextload x) 1301 if (N0.getOpcode() == ISD::SEXTLOAD && 1302 cast<VTSDNode>(N0.getOperand(3))->getVT() <= EVT) { 1303 return N0; 1304 } 1305 // fold (sext_in_reg (setcc x)) -> setcc x iff (setcc x) == 0 or -1 1306 if (N0.getOpcode() == ISD::SETCC && 1307 TLI.getSetCCResultContents() == 1308 TargetLowering::ZeroOrNegativeOneSetCCResult) 1309 return N0; 1310 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is zero 1311 if (MaskedValueIsZero(N0, 1ULL << (EVTBits-1), TLI)) 1312 return DAG.getNode(ISD::AND, N0.getValueType(), N0, 1313 DAG.getConstant(~0ULL >> (64-EVTBits), VT)); 1314 // fold (sext_in_reg (srl x)) -> sra x 1315 if (N0.getOpcode() == ISD::SRL && 1316 N0.getOperand(1).getOpcode() == ISD::Constant && 1317 cast<ConstantSDNode>(N0.getOperand(1))->getValue() == EVTBits) { 1318 return DAG.getNode(ISD::SRA, N0.getValueType(), N0.getOperand(0), 1319 N0.getOperand(1)); 1320 } 1321 // fold (sext_inreg (extload x)) -> (sextload x) 1322 if (N0.getOpcode() == ISD::EXTLOAD && 1323 EVT == cast<VTSDNode>(N0.getOperand(3))->getVT() && 1324 (!AfterLegalize || TLI.isOperationLegal(ISD::SEXTLOAD, EVT))) { 1325 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N0.getOperand(0), 1326 N0.getOperand(1), N0.getOperand(2), 1327 EVT); 1328 WorkList.push_back(N); 1329 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 1330 return SDOperand(); 1331 } 1332 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use 1333 if (N0.getOpcode() == ISD::ZEXTLOAD && N0.Val->hasNUsesOfValue(1, 0) && 1334 EVT == cast<VTSDNode>(N0.getOperand(3))->getVT() && 1335 (!AfterLegalize || TLI.isOperationLegal(ISD::SEXTLOAD, EVT))) { 1336 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N0.getOperand(0), 1337 N0.getOperand(1), N0.getOperand(2), 1338 EVT); 1339 WorkList.push_back(N); 1340 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 1341 return SDOperand(); 1342 } 1343 return SDOperand(); 1344} 1345 1346SDOperand DAGCombiner::visitTRUNCATE(SDNode *N) { 1347 SDOperand N0 = N->getOperand(0); 1348 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1349 MVT::ValueType VT = N->getValueType(0); 1350 1351 // noop truncate 1352 if (N0.getValueType() == N->getValueType(0)) 1353 return N0; 1354 // fold (truncate c1) -> c1 1355 if (N0C) 1356 return DAG.getConstant(N0C->getValue(), VT); 1357 // fold (truncate (truncate x)) -> (truncate x) 1358 if (N0.getOpcode() == ISD::TRUNCATE) 1359 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0)); 1360 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x 1361 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::SIGN_EXTEND){ 1362 if (N0.getValueType() < VT) 1363 // if the source is smaller than the dest, we still need an extend 1364 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0)); 1365 else if (N0.getValueType() > VT) 1366 // if the source is larger than the dest, than we just need the truncate 1367 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0)); 1368 else 1369 // if the source and dest are the same type, we can drop both the extend 1370 // and the truncate 1371 return N0.getOperand(0); 1372 } 1373 // fold (truncate (load x)) -> (smaller load x) 1374 if (N0.getOpcode() == ISD::LOAD && N0.Val->hasNUsesOfValue(1, 0)) { 1375 assert(MVT::getSizeInBits(N0.getValueType()) > MVT::getSizeInBits(VT) && 1376 "Cannot truncate to larger type!"); 1377 MVT::ValueType PtrType = N0.getOperand(1).getValueType(); 1378 // For big endian targets, we need to add an offset to the pointer to load 1379 // the correct bytes. For little endian systems, we merely need to read 1380 // fewer bytes from the same pointer. 1381 uint64_t PtrOff = 1382 (MVT::getSizeInBits(N0.getValueType()) - MVT::getSizeInBits(VT)) / 8; 1383 SDOperand NewPtr = TLI.isLittleEndian() ? N0.getOperand(1) : 1384 DAG.getNode(ISD::ADD, PtrType, N0.getOperand(1), 1385 DAG.getConstant(PtrOff, PtrType)); 1386 WorkList.push_back(NewPtr.Val); 1387 SDOperand Load = DAG.getLoad(VT, N0.getOperand(0), NewPtr,N0.getOperand(2)); 1388 CombineTo(N0.Val, Load, Load.getOperand(0)); 1389 WorkList.push_back(N); 1390 return SDOperand(); 1391 } 1392 return SDOperand(); 1393} 1394 1395SDOperand DAGCombiner::visitFADD(SDNode *N) { 1396 SDOperand N0 = N->getOperand(0); 1397 SDOperand N1 = N->getOperand(1); 1398 MVT::ValueType VT = N->getValueType(0); 1399 1400 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0)) 1401 if (ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1)) { 1402 // fold floating point (fadd c1, c2) 1403 return DAG.getConstantFP(N0CFP->getValue() + N1CFP->getValue(), 1404 N->getValueType(0)); 1405 } 1406 // fold (A + (-B)) -> A-B 1407 if (N1.getOpcode() == ISD::FNEG) 1408 return DAG.getNode(ISD::FSUB, VT, N0, N1.getOperand(0)); 1409 1410 // fold ((-A) + B) -> B-A 1411 if (N0.getOpcode() == ISD::FNEG) 1412 return DAG.getNode(ISD::FSUB, VT, N1, N0.getOperand(0)); 1413 1414 return SDOperand(); 1415} 1416 1417SDOperand DAGCombiner::visitFSUB(SDNode *N) { 1418 SDOperand N0 = N->getOperand(0); 1419 SDOperand N1 = N->getOperand(1); 1420 MVT::ValueType VT = N->getValueType(0); 1421 1422 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0)) 1423 if (ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1)) { 1424 // fold floating point (fsub c1, c2) 1425 return DAG.getConstantFP(N0CFP->getValue() - N1CFP->getValue(), 1426 N->getValueType(0)); 1427 } 1428 // fold (A-(-B)) -> A+B 1429 if (N1.getOpcode() == ISD::FNEG) 1430 return DAG.getNode(ISD::FADD, N0.getValueType(), N0, N1.getOperand(0)); 1431 1432 return SDOperand(); 1433} 1434 1435SDOperand DAGCombiner::visitFMUL(SDNode *N) { 1436 SDOperand N0 = N->getOperand(0); 1437 SDOperand N1 = N->getOperand(1); 1438 MVT::ValueType VT = N->getValueType(0); 1439 1440 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0)) 1441 if (ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1)) { 1442 // fold floating point (fmul c1, c2) 1443 return DAG.getConstantFP(N0CFP->getValue() * N1CFP->getValue(), 1444 N->getValueType(0)); 1445 } 1446 return SDOperand(); 1447} 1448 1449SDOperand DAGCombiner::visitFDIV(SDNode *N) { 1450 SDOperand N0 = N->getOperand(0); 1451 SDOperand N1 = N->getOperand(1); 1452 MVT::ValueType VT = N->getValueType(0); 1453 1454 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0)) 1455 if (ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1)) { 1456 // fold floating point (fdiv c1, c2) 1457 return DAG.getConstantFP(N0CFP->getValue() / N1CFP->getValue(), 1458 N->getValueType(0)); 1459 } 1460 return SDOperand(); 1461} 1462 1463SDOperand DAGCombiner::visitFREM(SDNode *N) { 1464 SDOperand N0 = N->getOperand(0); 1465 SDOperand N1 = N->getOperand(1); 1466 MVT::ValueType VT = N->getValueType(0); 1467 1468 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0)) 1469 if (ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1)) { 1470 // fold floating point (frem c1, c2) -> fmod(c1, c2) 1471 return DAG.getConstantFP(fmod(N0CFP->getValue(),N1CFP->getValue()), 1472 N->getValueType(0)); 1473 } 1474 return SDOperand(); 1475} 1476 1477 1478SDOperand DAGCombiner::visitSINT_TO_FP(SDNode *N) { 1479 SDOperand N0 = N->getOperand(0); 1480 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1481 1482 // fold (sint_to_fp c1) -> c1fp 1483 if (N0C) 1484 return DAG.getConstantFP(N0C->getSignExtended(), N->getValueType(0)); 1485 return SDOperand(); 1486} 1487 1488SDOperand DAGCombiner::visitUINT_TO_FP(SDNode *N) { 1489 SDOperand N0 = N->getOperand(0); 1490 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1491 1492 // fold (uint_to_fp c1) -> c1fp 1493 if (N0C) 1494 return DAG.getConstantFP(N0C->getValue(), N->getValueType(0)); 1495 return SDOperand(); 1496} 1497 1498SDOperand DAGCombiner::visitFP_TO_SINT(SDNode *N) { 1499 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0)); 1500 1501 // fold (fp_to_sint c1fp) -> c1 1502 if (N0CFP) 1503 return DAG.getConstant((int64_t)N0CFP->getValue(), N->getValueType(0)); 1504 return SDOperand(); 1505} 1506 1507SDOperand DAGCombiner::visitFP_TO_UINT(SDNode *N) { 1508 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0)); 1509 1510 // fold (fp_to_uint c1fp) -> c1 1511 if (N0CFP) 1512 return DAG.getConstant((uint64_t)N0CFP->getValue(), N->getValueType(0)); 1513 return SDOperand(); 1514} 1515 1516SDOperand DAGCombiner::visitFP_ROUND(SDNode *N) { 1517 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0)); 1518 1519 // fold (fp_round c1fp) -> c1fp 1520 if (N0CFP) 1521 return DAG.getConstantFP(N0CFP->getValue(), N->getValueType(0)); 1522 return SDOperand(); 1523} 1524 1525SDOperand DAGCombiner::visitFP_ROUND_INREG(SDNode *N) { 1526 SDOperand N0 = N->getOperand(0); 1527 MVT::ValueType VT = N->getValueType(0); 1528 MVT::ValueType EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 1529 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 1530 1531 // fold (fp_round_inreg c1fp) -> c1fp 1532 if (N0CFP) { 1533 SDOperand Round = DAG.getConstantFP(N0CFP->getValue(), EVT); 1534 return DAG.getNode(ISD::FP_EXTEND, VT, Round); 1535 } 1536 return SDOperand(); 1537} 1538 1539SDOperand DAGCombiner::visitFP_EXTEND(SDNode *N) { 1540 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0)); 1541 1542 // fold (fp_extend c1fp) -> c1fp 1543 if (N0CFP) 1544 return DAG.getConstantFP(N0CFP->getValue(), N->getValueType(0)); 1545 return SDOperand(); 1546} 1547 1548SDOperand DAGCombiner::visitFNEG(SDNode *N) { 1549 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0)); 1550 // fold (neg c1) -> -c1 1551 if (N0CFP) 1552 return DAG.getConstantFP(-N0CFP->getValue(), N->getValueType(0)); 1553 // fold (neg (sub x, y)) -> (sub y, x) 1554 if (N->getOperand(0).getOpcode() == ISD::SUB) 1555 return DAG.getNode(ISD::SUB, N->getValueType(0), N->getOperand(1), 1556 N->getOperand(0)); 1557 // fold (neg (neg x)) -> x 1558 if (N->getOperand(0).getOpcode() == ISD::FNEG) 1559 return N->getOperand(0).getOperand(0); 1560 return SDOperand(); 1561} 1562 1563SDOperand DAGCombiner::visitFABS(SDNode *N) { 1564 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0)); 1565 // fold (fabs c1) -> fabs(c1) 1566 if (N0CFP) 1567 return DAG.getConstantFP(fabs(N0CFP->getValue()), N->getValueType(0)); 1568 // fold (fabs (fabs x)) -> (fabs x) 1569 if (N->getOperand(0).getOpcode() == ISD::FABS) 1570 return N->getOperand(0); 1571 // fold (fabs (fneg x)) -> (fabs x) 1572 if (N->getOperand(0).getOpcode() == ISD::FNEG) 1573 return DAG.getNode(ISD::FABS, N->getValueType(0), 1574 N->getOperand(0).getOperand(0)); 1575 return SDOperand(); 1576} 1577 1578SDOperand DAGCombiner::visitBRCOND(SDNode *N) { 1579 SDOperand Chain = N->getOperand(0); 1580 SDOperand N1 = N->getOperand(1); 1581 SDOperand N2 = N->getOperand(2); 1582 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1583 1584 // never taken branch, fold to chain 1585 if (N1C && N1C->isNullValue()) 1586 return Chain; 1587 // unconditional branch 1588 if (N1C && N1C->getValue() == 1) 1589 return DAG.getNode(ISD::BR, MVT::Other, Chain, N2); 1590 return SDOperand(); 1591} 1592 1593SDOperand DAGCombiner::visitBRCONDTWOWAY(SDNode *N) { 1594 SDOperand Chain = N->getOperand(0); 1595 SDOperand N1 = N->getOperand(1); 1596 SDOperand N2 = N->getOperand(2); 1597 SDOperand N3 = N->getOperand(3); 1598 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1599 1600 // unconditional branch to true mbb 1601 if (N1C && N1C->getValue() == 1) 1602 return DAG.getNode(ISD::BR, MVT::Other, Chain, N2); 1603 // unconditional branch to false mbb 1604 if (N1C && N1C->isNullValue()) 1605 return DAG.getNode(ISD::BR, MVT::Other, Chain, N3); 1606 return SDOperand(); 1607} 1608 1609// Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB. 1610// 1611SDOperand DAGCombiner::visitBR_CC(SDNode *N) { 1612 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1)); 1613 SDOperand CondLHS = N->getOperand(2), CondRHS = N->getOperand(3); 1614 1615 // Use SimplifySetCC to simplify SETCC's. 1616 SDOperand Simp = SimplifySetCC(MVT::i1, CondLHS, CondRHS, CC->get(), false); 1617 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(Simp.Val); 1618 1619 // fold br_cc true, dest -> br dest (unconditional branch) 1620 if (SCCC && SCCC->getValue()) 1621 return DAG.getNode(ISD::BR, MVT::Other, N->getOperand(0), 1622 N->getOperand(4)); 1623 // fold br_cc false, dest -> unconditional fall through 1624 if (SCCC && SCCC->isNullValue()) 1625 return N->getOperand(0); 1626 // fold to a simpler setcc 1627 if (Simp.Val && Simp.getOpcode() == ISD::SETCC) 1628 return DAG.getNode(ISD::BR_CC, MVT::Other, N->getOperand(0), 1629 Simp.getOperand(2), Simp.getOperand(0), 1630 Simp.getOperand(1), N->getOperand(4)); 1631 return SDOperand(); 1632} 1633 1634SDOperand DAGCombiner::visitBRTWOWAY_CC(SDNode *N) { 1635 SDOperand Chain = N->getOperand(0); 1636 SDOperand CCN = N->getOperand(1); 1637 SDOperand LHS = N->getOperand(2); 1638 SDOperand RHS = N->getOperand(3); 1639 SDOperand N4 = N->getOperand(4); 1640 SDOperand N5 = N->getOperand(5); 1641 1642 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), LHS, RHS, 1643 cast<CondCodeSDNode>(CCN)->get(), false); 1644 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val); 1645 1646 // fold select_cc lhs, rhs, x, x, cc -> x 1647 if (N4 == N5) 1648 return DAG.getNode(ISD::BR, MVT::Other, Chain, N4); 1649 // fold select_cc true, x, y -> x 1650 if (SCCC && SCCC->getValue()) 1651 return DAG.getNode(ISD::BR, MVT::Other, Chain, N4); 1652 // fold select_cc false, x, y -> y 1653 if (SCCC && SCCC->isNullValue()) 1654 return DAG.getNode(ISD::BR, MVT::Other, Chain, N5); 1655 // fold to a simpler setcc 1656 if (SCC.Val && SCC.getOpcode() == ISD::SETCC) 1657 return DAG.getBR2Way_CC(Chain, SCC.getOperand(2), SCC.getOperand(0), 1658 SCC.getOperand(1), N4, N5); 1659 return SDOperand(); 1660} 1661 1662SDOperand DAGCombiner::visitLOAD(SDNode *N) { 1663 SDOperand Chain = N->getOperand(0); 1664 SDOperand Ptr = N->getOperand(1); 1665 SDOperand SrcValue = N->getOperand(2); 1666 1667 // If this load is directly stored, replace the load value with the stored 1668 // value. 1669 // TODO: Handle store large -> read small portion. 1670 // TODO: Handle TRUNCSTORE/EXTLOAD 1671 if (Chain.getOpcode() == ISD::STORE && Chain.getOperand(2) == Ptr && 1672 Chain.getOperand(1).getValueType() == N->getValueType(0)) 1673 return CombineTo(N, Chain.getOperand(1), Chain); 1674 1675 return SDOperand(); 1676} 1677 1678SDOperand DAGCombiner::visitSTORE(SDNode *N) { 1679 SDOperand Chain = N->getOperand(0); 1680 SDOperand Value = N->getOperand(1); 1681 SDOperand Ptr = N->getOperand(2); 1682 SDOperand SrcValue = N->getOperand(3); 1683 1684 // If this is a store that kills a previous store, remove the previous store. 1685 if (Chain.getOpcode() == ISD::STORE && Chain.getOperand(2) == Ptr && 1686 Chain.Val->hasOneUse() /* Avoid introducing DAG cycles */) { 1687 // Create a new store of Value that replaces both stores. 1688 SDNode *PrevStore = Chain.Val; 1689 if (PrevStore->getOperand(1) == Value) // Same value multiply stored. 1690 return Chain; 1691 SDOperand NewStore = DAG.getNode(ISD::STORE, MVT::Other, 1692 PrevStore->getOperand(0), Value, Ptr, 1693 SrcValue); 1694 CombineTo(N, NewStore); // Nuke this store. 1695 CombineTo(PrevStore, NewStore); // Nuke the previous store. 1696 return SDOperand(N, 0); 1697 } 1698 1699 return SDOperand(); 1700} 1701 1702SDOperand DAGCombiner::SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2){ 1703 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!"); 1704 1705 SDOperand SCC = SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), N1, N2, 1706 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 1707 // If we got a simplified select_cc node back from SimplifySelectCC, then 1708 // break it down into a new SETCC node, and a new SELECT node, and then return 1709 // the SELECT node, since we were called with a SELECT node. 1710 if (SCC.Val) { 1711 // Check to see if we got a select_cc back (to turn into setcc/select). 1712 // Otherwise, just return whatever node we got back, like fabs. 1713 if (SCC.getOpcode() == ISD::SELECT_CC) { 1714 SDOperand SETCC = DAG.getNode(ISD::SETCC, N0.getValueType(), 1715 SCC.getOperand(0), SCC.getOperand(1), 1716 SCC.getOperand(4)); 1717 WorkList.push_back(SETCC.Val); 1718 return DAG.getNode(ISD::SELECT, SCC.getValueType(), SCC.getOperand(2), 1719 SCC.getOperand(3), SETCC); 1720 } 1721 return SCC; 1722 } 1723 return SDOperand(); 1724} 1725 1726SDOperand DAGCombiner::SimplifySelectCC(SDOperand N0, SDOperand N1, 1727 SDOperand N2, SDOperand N3, 1728 ISD::CondCode CC) { 1729 1730 MVT::ValueType VT = N2.getValueType(); 1731 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 1732 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 1733 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val); 1734 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.Val); 1735 1736 // Determine if the condition we're dealing with is constant 1737 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false); 1738 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val); 1739 1740 // fold select_cc true, x, y -> x 1741 if (SCCC && SCCC->getValue()) 1742 return N2; 1743 // fold select_cc false, x, y -> y 1744 if (SCCC && SCCC->getValue() == 0) 1745 return N3; 1746 1747 // Check to see if we can simplify the select into an fabs node 1748 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) { 1749 // Allow either -0.0 or 0.0 1750 if (CFP->getValue() == 0.0) { 1751 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs 1752 if ((CC == ISD::SETGE || CC == ISD::SETGT) && 1753 N0 == N2 && N3.getOpcode() == ISD::FNEG && 1754 N2 == N3.getOperand(0)) 1755 return DAG.getNode(ISD::FABS, VT, N0); 1756 1757 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs 1758 if ((CC == ISD::SETLT || CC == ISD::SETLE) && 1759 N0 == N3 && N2.getOpcode() == ISD::FNEG && 1760 N2.getOperand(0) == N3) 1761 return DAG.getNode(ISD::FABS, VT, N3); 1762 } 1763 } 1764 1765 // Check to see if we can perform the "gzip trick", transforming 1766 // select_cc setlt X, 0, A, 0 -> and (sra X, size(X)-1), A 1767 if (N1C && N1C->isNullValue() && N3C && N3C->isNullValue() && 1768 MVT::isInteger(N0.getValueType()) && 1769 MVT::isInteger(N2.getValueType()) && CC == ISD::SETLT) { 1770 MVT::ValueType XType = N0.getValueType(); 1771 MVT::ValueType AType = N2.getValueType(); 1772 if (XType >= AType) { 1773 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a 1774 // single-bit constant. 1775 if (N2C && ((N2C->getValue() & (N2C->getValue()-1)) == 0)) { 1776 unsigned ShCtV = Log2_64(N2C->getValue()); 1777 ShCtV = MVT::getSizeInBits(XType)-ShCtV-1; 1778 SDOperand ShCt = DAG.getConstant(ShCtV, TLI.getShiftAmountTy()); 1779 SDOperand Shift = DAG.getNode(ISD::SRL, XType, N0, ShCt); 1780 WorkList.push_back(Shift.Val); 1781 if (XType > AType) { 1782 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift); 1783 WorkList.push_back(Shift.Val); 1784 } 1785 return DAG.getNode(ISD::AND, AType, Shift, N2); 1786 } 1787 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0, 1788 DAG.getConstant(MVT::getSizeInBits(XType)-1, 1789 TLI.getShiftAmountTy())); 1790 WorkList.push_back(Shift.Val); 1791 if (XType > AType) { 1792 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift); 1793 WorkList.push_back(Shift.Val); 1794 } 1795 return DAG.getNode(ISD::AND, AType, Shift, N2); 1796 } 1797 } 1798 1799 // fold select C, 16, 0 -> shl C, 4 1800 if (N2C && N3C && N3C->isNullValue() && isPowerOf2_64(N2C->getValue()) && 1801 TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult) { 1802 // Get a SetCC of the condition 1803 // FIXME: Should probably make sure that setcc is legal if we ever have a 1804 // target where it isn't. 1805 SDOperand Temp, SCC = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC); 1806 WorkList.push_back(SCC.Val); 1807 // cast from setcc result type to select result type 1808 if (AfterLegalize) 1809 Temp = DAG.getZeroExtendInReg(SCC, N2.getValueType()); 1810 else 1811 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC); 1812 WorkList.push_back(Temp.Val); 1813 // shl setcc result by log2 n2c 1814 return DAG.getNode(ISD::SHL, N2.getValueType(), Temp, 1815 DAG.getConstant(Log2_64(N2C->getValue()), 1816 TLI.getShiftAmountTy())); 1817 } 1818 1819 // Check to see if this is the equivalent of setcc 1820 // FIXME: Turn all of these into setcc if setcc if setcc is legal 1821 // otherwise, go ahead with the folds. 1822 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getValue() == 1ULL)) { 1823 MVT::ValueType XType = N0.getValueType(); 1824 if (TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultTy())) { 1825 SDOperand Res = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC); 1826 if (Res.getValueType() != VT) 1827 Res = DAG.getNode(ISD::ZERO_EXTEND, VT, Res); 1828 return Res; 1829 } 1830 1831 // seteq X, 0 -> srl (ctlz X, log2(size(X))) 1832 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ && 1833 TLI.isOperationLegal(ISD::CTLZ, XType)) { 1834 SDOperand Ctlz = DAG.getNode(ISD::CTLZ, XType, N0); 1835 return DAG.getNode(ISD::SRL, XType, Ctlz, 1836 DAG.getConstant(Log2_32(MVT::getSizeInBits(XType)), 1837 TLI.getShiftAmountTy())); 1838 } 1839 // setgt X, 0 -> srl (and (-X, ~X), size(X)-1) 1840 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) { 1841 SDOperand NegN0 = DAG.getNode(ISD::SUB, XType, DAG.getConstant(0, XType), 1842 N0); 1843 SDOperand NotN0 = DAG.getNode(ISD::XOR, XType, N0, 1844 DAG.getConstant(~0ULL, XType)); 1845 return DAG.getNode(ISD::SRL, XType, 1846 DAG.getNode(ISD::AND, XType, NegN0, NotN0), 1847 DAG.getConstant(MVT::getSizeInBits(XType)-1, 1848 TLI.getShiftAmountTy())); 1849 } 1850 // setgt X, -1 -> xor (srl (X, size(X)-1), 1) 1851 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) { 1852 SDOperand Sign = DAG.getNode(ISD::SRL, XType, N0, 1853 DAG.getConstant(MVT::getSizeInBits(XType)-1, 1854 TLI.getShiftAmountTy())); 1855 return DAG.getNode(ISD::XOR, XType, Sign, DAG.getConstant(1, XType)); 1856 } 1857 } 1858 1859 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X -> 1860 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 1861 if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) && 1862 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1)) { 1863 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N2.getOperand(0))) { 1864 MVT::ValueType XType = N0.getValueType(); 1865 if (SubC->isNullValue() && MVT::isInteger(XType)) { 1866 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0, 1867 DAG.getConstant(MVT::getSizeInBits(XType)-1, 1868 TLI.getShiftAmountTy())); 1869 SDOperand Add = DAG.getNode(ISD::ADD, XType, N0, Shift); 1870 WorkList.push_back(Shift.Val); 1871 WorkList.push_back(Add.Val); 1872 return DAG.getNode(ISD::XOR, XType, Add, Shift); 1873 } 1874 } 1875 } 1876 1877 return SDOperand(); 1878} 1879 1880SDOperand DAGCombiner::SimplifySetCC(MVT::ValueType VT, SDOperand N0, 1881 SDOperand N1, ISD::CondCode Cond, 1882 bool foldBooleans) { 1883 // These setcc operations always fold. 1884 switch (Cond) { 1885 default: break; 1886 case ISD::SETFALSE: 1887 case ISD::SETFALSE2: return DAG.getConstant(0, VT); 1888 case ISD::SETTRUE: 1889 case ISD::SETTRUE2: return DAG.getConstant(1, VT); 1890 } 1891 1892 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val)) { 1893 uint64_t C1 = N1C->getValue(); 1894 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val)) { 1895 uint64_t C0 = N0C->getValue(); 1896 1897 // Sign extend the operands if required 1898 if (ISD::isSignedIntSetCC(Cond)) { 1899 C0 = N0C->getSignExtended(); 1900 C1 = N1C->getSignExtended(); 1901 } 1902 1903 switch (Cond) { 1904 default: assert(0 && "Unknown integer setcc!"); 1905 case ISD::SETEQ: return DAG.getConstant(C0 == C1, VT); 1906 case ISD::SETNE: return DAG.getConstant(C0 != C1, VT); 1907 case ISD::SETULT: return DAG.getConstant(C0 < C1, VT); 1908 case ISD::SETUGT: return DAG.getConstant(C0 > C1, VT); 1909 case ISD::SETULE: return DAG.getConstant(C0 <= C1, VT); 1910 case ISD::SETUGE: return DAG.getConstant(C0 >= C1, VT); 1911 case ISD::SETLT: return DAG.getConstant((int64_t)C0 < (int64_t)C1, VT); 1912 case ISD::SETGT: return DAG.getConstant((int64_t)C0 > (int64_t)C1, VT); 1913 case ISD::SETLE: return DAG.getConstant((int64_t)C0 <= (int64_t)C1, VT); 1914 case ISD::SETGE: return DAG.getConstant((int64_t)C0 >= (int64_t)C1, VT); 1915 } 1916 } else { 1917 // If the LHS is a ZERO_EXTEND, perform the comparison on the input. 1918 if (N0.getOpcode() == ISD::ZERO_EXTEND) { 1919 unsigned InSize = MVT::getSizeInBits(N0.getOperand(0).getValueType()); 1920 1921 // If the comparison constant has bits in the upper part, the 1922 // zero-extended value could never match. 1923 if (C1 & (~0ULL << InSize)) { 1924 unsigned VSize = MVT::getSizeInBits(N0.getValueType()); 1925 switch (Cond) { 1926 case ISD::SETUGT: 1927 case ISD::SETUGE: 1928 case ISD::SETEQ: return DAG.getConstant(0, VT); 1929 case ISD::SETULT: 1930 case ISD::SETULE: 1931 case ISD::SETNE: return DAG.getConstant(1, VT); 1932 case ISD::SETGT: 1933 case ISD::SETGE: 1934 // True if the sign bit of C1 is set. 1935 return DAG.getConstant((C1 & (1ULL << VSize)) != 0, VT); 1936 case ISD::SETLT: 1937 case ISD::SETLE: 1938 // True if the sign bit of C1 isn't set. 1939 return DAG.getConstant((C1 & (1ULL << VSize)) == 0, VT); 1940 default: 1941 break; 1942 } 1943 } 1944 1945 // Otherwise, we can perform the comparison with the low bits. 1946 switch (Cond) { 1947 case ISD::SETEQ: 1948 case ISD::SETNE: 1949 case ISD::SETUGT: 1950 case ISD::SETUGE: 1951 case ISD::SETULT: 1952 case ISD::SETULE: 1953 return DAG.getSetCC(VT, N0.getOperand(0), 1954 DAG.getConstant(C1, N0.getOperand(0).getValueType()), 1955 Cond); 1956 default: 1957 break; // todo, be more careful with signed comparisons 1958 } 1959 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 1960 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { 1961 MVT::ValueType ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT(); 1962 unsigned ExtSrcTyBits = MVT::getSizeInBits(ExtSrcTy); 1963 MVT::ValueType ExtDstTy = N0.getValueType(); 1964 unsigned ExtDstTyBits = MVT::getSizeInBits(ExtDstTy); 1965 1966 // If the extended part has any inconsistent bits, it cannot ever 1967 // compare equal. In other words, they have to be all ones or all 1968 // zeros. 1969 uint64_t ExtBits = 1970 (~0ULL >> (64-ExtSrcTyBits)) & (~0ULL << (ExtDstTyBits-1)); 1971 if ((C1 & ExtBits) != 0 && (C1 & ExtBits) != ExtBits) 1972 return DAG.getConstant(Cond == ISD::SETNE, VT); 1973 1974 SDOperand ZextOp; 1975 MVT::ValueType Op0Ty = N0.getOperand(0).getValueType(); 1976 if (Op0Ty == ExtSrcTy) { 1977 ZextOp = N0.getOperand(0); 1978 } else { 1979 int64_t Imm = ~0ULL >> (64-ExtSrcTyBits); 1980 ZextOp = DAG.getNode(ISD::AND, Op0Ty, N0.getOperand(0), 1981 DAG.getConstant(Imm, Op0Ty)); 1982 } 1983 WorkList.push_back(ZextOp.Val); 1984 // Otherwise, make this a use of a zext. 1985 return DAG.getSetCC(VT, ZextOp, 1986 DAG.getConstant(C1 & (~0ULL>>(64-ExtSrcTyBits)), 1987 ExtDstTy), 1988 Cond); 1989 } 1990 1991 uint64_t MinVal, MaxVal; 1992 unsigned OperandBitSize = MVT::getSizeInBits(N1C->getValueType(0)); 1993 if (ISD::isSignedIntSetCC(Cond)) { 1994 MinVal = 1ULL << (OperandBitSize-1); 1995 if (OperandBitSize != 1) // Avoid X >> 64, which is undefined. 1996 MaxVal = ~0ULL >> (65-OperandBitSize); 1997 else 1998 MaxVal = 0; 1999 } else { 2000 MinVal = 0; 2001 MaxVal = ~0ULL >> (64-OperandBitSize); 2002 } 2003 2004 // Canonicalize GE/LE comparisons to use GT/LT comparisons. 2005 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) { 2006 if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true 2007 --C1; // X >= C0 --> X > (C0-1) 2008 return DAG.getSetCC(VT, N0, DAG.getConstant(C1, N1.getValueType()), 2009 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT); 2010 } 2011 2012 if (Cond == ISD::SETLE || Cond == ISD::SETULE) { 2013 if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true 2014 ++C1; // X <= C0 --> X < (C0+1) 2015 return DAG.getSetCC(VT, N0, DAG.getConstant(C1, N1.getValueType()), 2016 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT); 2017 } 2018 2019 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal) 2020 return DAG.getConstant(0, VT); // X < MIN --> false 2021 2022 // Canonicalize setgt X, Min --> setne X, Min 2023 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal) 2024 return DAG.getSetCC(VT, N0, N1, ISD::SETNE); 2025 2026 // If we have setult X, 1, turn it into seteq X, 0 2027 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1) 2028 return DAG.getSetCC(VT, N0, DAG.getConstant(MinVal, N0.getValueType()), 2029 ISD::SETEQ); 2030 // If we have setugt X, Max-1, turn it into seteq X, Max 2031 else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1) 2032 return DAG.getSetCC(VT, N0, DAG.getConstant(MaxVal, N0.getValueType()), 2033 ISD::SETEQ); 2034 2035 // If we have "setcc X, C0", check to see if we can shrink the immediate 2036 // by changing cc. 2037 2038 // SETUGT X, SINTMAX -> SETLT X, 0 2039 if (Cond == ISD::SETUGT && OperandBitSize != 1 && 2040 C1 == (~0ULL >> (65-OperandBitSize))) 2041 return DAG.getSetCC(VT, N0, DAG.getConstant(0, N1.getValueType()), 2042 ISD::SETLT); 2043 2044 // FIXME: Implement the rest of these. 2045 2046 // Fold bit comparisons when we can. 2047 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 2048 VT == N0.getValueType() && N0.getOpcode() == ISD::AND) 2049 if (ConstantSDNode *AndRHS = 2050 dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 2051 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3 2052 // Perform the xform if the AND RHS is a single bit. 2053 if ((AndRHS->getValue() & (AndRHS->getValue()-1)) == 0) { 2054 return DAG.getNode(ISD::SRL, VT, N0, 2055 DAG.getConstant(Log2_64(AndRHS->getValue()), 2056 TLI.getShiftAmountTy())); 2057 } 2058 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getValue()) { 2059 // (X & 8) == 8 --> (X & 8) >> 3 2060 // Perform the xform if C1 is a single bit. 2061 if ((C1 & (C1-1)) == 0) { 2062 return DAG.getNode(ISD::SRL, VT, N0, 2063 DAG.getConstant(Log2_64(C1),TLI.getShiftAmountTy())); 2064 } 2065 } 2066 } 2067 } 2068 } else if (isa<ConstantSDNode>(N0.Val)) { 2069 // Ensure that the constant occurs on the RHS. 2070 return DAG.getSetCC(VT, N1, N0, ISD::getSetCCSwappedOperands(Cond)); 2071 } 2072 2073 if (ConstantFPSDNode *N0C = dyn_cast<ConstantFPSDNode>(N0.Val)) 2074 if (ConstantFPSDNode *N1C = dyn_cast<ConstantFPSDNode>(N1.Val)) { 2075 double C0 = N0C->getValue(), C1 = N1C->getValue(); 2076 2077 switch (Cond) { 2078 default: break; // FIXME: Implement the rest of these! 2079 case ISD::SETEQ: return DAG.getConstant(C0 == C1, VT); 2080 case ISD::SETNE: return DAG.getConstant(C0 != C1, VT); 2081 case ISD::SETLT: return DAG.getConstant(C0 < C1, VT); 2082 case ISD::SETGT: return DAG.getConstant(C0 > C1, VT); 2083 case ISD::SETLE: return DAG.getConstant(C0 <= C1, VT); 2084 case ISD::SETGE: return DAG.getConstant(C0 >= C1, VT); 2085 } 2086 } else { 2087 // Ensure that the constant occurs on the RHS. 2088 return DAG.getSetCC(VT, N1, N0, ISD::getSetCCSwappedOperands(Cond)); 2089 } 2090 2091 if (N0 == N1) { 2092 // We can always fold X == Y for integer setcc's. 2093 if (MVT::isInteger(N0.getValueType())) 2094 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT); 2095 unsigned UOF = ISD::getUnorderedFlavor(Cond); 2096 if (UOF == 2) // FP operators that are undefined on NaNs. 2097 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT); 2098 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond))) 2099 return DAG.getConstant(UOF, VT); 2100 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO 2101 // if it is not already. 2102 ISD::CondCode NewCond = UOF == 0 ? ISD::SETUO : ISD::SETO; 2103 if (NewCond != Cond) 2104 return DAG.getSetCC(VT, N0, N1, NewCond); 2105 } 2106 2107 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 2108 MVT::isInteger(N0.getValueType())) { 2109 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB || 2110 N0.getOpcode() == ISD::XOR) { 2111 // Simplify (X+Y) == (X+Z) --> Y == Z 2112 if (N0.getOpcode() == N1.getOpcode()) { 2113 if (N0.getOperand(0) == N1.getOperand(0)) 2114 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(1), Cond); 2115 if (N0.getOperand(1) == N1.getOperand(1)) 2116 return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(0), Cond); 2117 if (isCommutativeBinOp(N0.getOpcode())) { 2118 // If X op Y == Y op X, try other combinations. 2119 if (N0.getOperand(0) == N1.getOperand(1)) 2120 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(0), Cond); 2121 if (N0.getOperand(1) == N1.getOperand(0)) 2122 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(1), Cond); 2123 } 2124 } 2125 2126 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0. Common for condcodes. 2127 if (N0.getOpcode() == ISD::XOR) 2128 if (ConstantSDNode *XORC = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 2129 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) { 2130 // If we know that all of the inverted bits are zero, don't bother 2131 // performing the inversion. 2132 if (MaskedValueIsZero(N0.getOperand(0), ~XORC->getValue(), TLI)) 2133 return DAG.getSetCC(VT, N0.getOperand(0), 2134 DAG.getConstant(XORC->getValue()^RHSC->getValue(), 2135 N0.getValueType()), Cond); 2136 } 2137 2138 // Simplify (X+Z) == X --> Z == 0 2139 if (N0.getOperand(0) == N1) 2140 return DAG.getSetCC(VT, N0.getOperand(1), 2141 DAG.getConstant(0, N0.getValueType()), Cond); 2142 if (N0.getOperand(1) == N1) { 2143 if (isCommutativeBinOp(N0.getOpcode())) 2144 return DAG.getSetCC(VT, N0.getOperand(0), 2145 DAG.getConstant(0, N0.getValueType()), Cond); 2146 else { 2147 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!"); 2148 // (Z-X) == X --> Z == X<<1 2149 SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(), 2150 N1, 2151 DAG.getConstant(1,TLI.getShiftAmountTy())); 2152 WorkList.push_back(SH.Val); 2153 return DAG.getSetCC(VT, N0.getOperand(0), SH, Cond); 2154 } 2155 } 2156 } 2157 2158 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB || 2159 N1.getOpcode() == ISD::XOR) { 2160 // Simplify X == (X+Z) --> Z == 0 2161 if (N1.getOperand(0) == N0) { 2162 return DAG.getSetCC(VT, N1.getOperand(1), 2163 DAG.getConstant(0, N1.getValueType()), Cond); 2164 } else if (N1.getOperand(1) == N0) { 2165 if (isCommutativeBinOp(N1.getOpcode())) { 2166 return DAG.getSetCC(VT, N1.getOperand(0), 2167 DAG.getConstant(0, N1.getValueType()), Cond); 2168 } else { 2169 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!"); 2170 // X == (Z-X) --> X<<1 == Z 2171 SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(), N0, 2172 DAG.getConstant(1,TLI.getShiftAmountTy())); 2173 WorkList.push_back(SH.Val); 2174 return DAG.getSetCC(VT, SH, N1.getOperand(0), Cond); 2175 } 2176 } 2177 } 2178 } 2179 2180 // Fold away ALL boolean setcc's. 2181 SDOperand Temp; 2182 if (N0.getValueType() == MVT::i1 && foldBooleans) { 2183 switch (Cond) { 2184 default: assert(0 && "Unknown integer setcc!"); 2185 case ISD::SETEQ: // X == Y -> (X^Y)^1 2186 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, N1); 2187 N0 = DAG.getNode(ISD::XOR, MVT::i1, Temp, DAG.getConstant(1, MVT::i1)); 2188 WorkList.push_back(Temp.Val); 2189 break; 2190 case ISD::SETNE: // X != Y --> (X^Y) 2191 N0 = DAG.getNode(ISD::XOR, MVT::i1, N0, N1); 2192 break; 2193 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> X^1 & Y 2194 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> X^1 & Y 2195 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1)); 2196 N0 = DAG.getNode(ISD::AND, MVT::i1, N1, Temp); 2197 WorkList.push_back(Temp.Val); 2198 break; 2199 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> Y^1 & X 2200 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> Y^1 & X 2201 Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1)); 2202 N0 = DAG.getNode(ISD::AND, MVT::i1, N0, Temp); 2203 WorkList.push_back(Temp.Val); 2204 break; 2205 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> X^1 | Y 2206 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> X^1 | Y 2207 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1)); 2208 N0 = DAG.getNode(ISD::OR, MVT::i1, N1, Temp); 2209 WorkList.push_back(Temp.Val); 2210 break; 2211 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> Y^1 | X 2212 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> Y^1 | X 2213 Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1)); 2214 N0 = DAG.getNode(ISD::OR, MVT::i1, N0, Temp); 2215 break; 2216 } 2217 if (VT != MVT::i1) { 2218 WorkList.push_back(N0.Val); 2219 // FIXME: If running after legalize, we probably can't do this. 2220 N0 = DAG.getNode(ISD::ZERO_EXTEND, VT, N0); 2221 } 2222 return N0; 2223 } 2224 2225 // Could not fold it. 2226 return SDOperand(); 2227} 2228 2229// SelectionDAG::Combine - This is the entry point for the file. 2230// 2231void SelectionDAG::Combine(bool RunningAfterLegalize) { 2232 /// run - This is the main entry point to this class. 2233 /// 2234 DAGCombiner(*this).Run(RunningAfterLegalize); 2235} 2236