DAGCombiner.cpp revision d16c8d0d336638225378466bc17c9db156401817
1//===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run 11// both before and after the DAG is legalized. 12// 13// This pass is not a substitute for the LLVM IR instcombine pass. This pass is 14// primarily intended to handle simplification opportunities that are implicit 15// in the LLVM IR and exposed by the various codegen lowering phases. 16// 17//===----------------------------------------------------------------------===// 18 19#define DEBUG_TYPE "dagcombine" 20#include "llvm/CodeGen/SelectionDAG.h" 21#include "llvm/DerivedTypes.h" 22#include "llvm/LLVMContext.h" 23#include "llvm/CodeGen/MachineFunction.h" 24#include "llvm/CodeGen/MachineFrameInfo.h" 25#include "llvm/Analysis/AliasAnalysis.h" 26#include "llvm/Target/TargetData.h" 27#include "llvm/Target/TargetLowering.h" 28#include "llvm/Target/TargetMachine.h" 29#include "llvm/Target/TargetOptions.h" 30#include "llvm/ADT/SmallPtrSet.h" 31#include "llvm/ADT/Statistic.h" 32#include "llvm/Support/CommandLine.h" 33#include "llvm/Support/Debug.h" 34#include "llvm/Support/ErrorHandling.h" 35#include "llvm/Support/MathExtras.h" 36#include "llvm/Support/raw_ostream.h" 37#include <algorithm> 38using namespace llvm; 39 40STATISTIC(NodesCombined , "Number of dag nodes combined"); 41STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created"); 42STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created"); 43STATISTIC(OpsNarrowed , "Number of load/op/store narrowed"); 44STATISTIC(LdStFP2Int , "Number of fp load/store pairs transformed to int"); 45 46namespace { 47 static cl::opt<bool> 48 CombinerAA("combiner-alias-analysis", cl::Hidden, 49 cl::desc("Turn on alias analysis during testing")); 50 51 static cl::opt<bool> 52 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden, 53 cl::desc("Include global information in alias analysis")); 54 55//------------------------------ DAGCombiner ---------------------------------// 56 57 class DAGCombiner { 58 SelectionDAG &DAG; 59 const TargetLowering &TLI; 60 CombineLevel Level; 61 CodeGenOpt::Level OptLevel; 62 bool LegalOperations; 63 bool LegalTypes; 64 65 // Worklist of all of the nodes that need to be simplified. 66 // 67 // This has the semantics that when adding to the worklist, 68 // the item added must be next to be processed. It should 69 // also only appear once. The naive approach to this takes 70 // linear time. 71 // 72 // To reduce the insert/remove time to logarithmic, we use 73 // a set and a vector to maintain our worklist. 74 // 75 // The set contains the items on the worklist, but does not 76 // maintain the order they should be visited. 77 // 78 // The vector maintains the order nodes should be visited, but may 79 // contain duplicate or removed nodes. When choosing a node to 80 // visit, we pop off the order stack until we find an item that is 81 // also in the contents set. All operations are O(log N). 82 SmallPtrSet<SDNode*, 64> WorkListContents; 83 SmallVector<SDNode*, 64> WorkListOrder; 84 85 // AA - Used for DAG load/store alias analysis. 86 AliasAnalysis &AA; 87 88 /// AddUsersToWorkList - When an instruction is simplified, add all users of 89 /// the instruction to the work lists because they might get more simplified 90 /// now. 91 /// 92 void AddUsersToWorkList(SDNode *N) { 93 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 94 UI != UE; ++UI) 95 AddToWorkList(*UI); 96 } 97 98 /// visit - call the node-specific routine that knows how to fold each 99 /// particular type of node. 100 SDValue visit(SDNode *N); 101 102 public: 103 /// AddToWorkList - Add to the work list making sure its instance is at the 104 /// back (next to be processed.) 105 void AddToWorkList(SDNode *N) { 106 WorkListContents.insert(N); 107 WorkListOrder.push_back(N); 108 } 109 110 /// removeFromWorkList - remove all instances of N from the worklist. 111 /// 112 void removeFromWorkList(SDNode *N) { 113 WorkListContents.erase(N); 114 } 115 116 SDValue CombineTo(SDNode *N, const SDValue *To, unsigned NumTo, 117 bool AddTo = true); 118 119 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true) { 120 return CombineTo(N, &Res, 1, AddTo); 121 } 122 123 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, 124 bool AddTo = true) { 125 SDValue To[] = { Res0, Res1 }; 126 return CombineTo(N, To, 2, AddTo); 127 } 128 129 void CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO); 130 131 private: 132 133 /// SimplifyDemandedBits - Check the specified integer node value to see if 134 /// it can be simplified or if things it uses can be simplified by bit 135 /// propagation. If so, return true. 136 bool SimplifyDemandedBits(SDValue Op) { 137 unsigned BitWidth = Op.getValueType().getScalarType().getSizeInBits(); 138 APInt Demanded = APInt::getAllOnesValue(BitWidth); 139 return SimplifyDemandedBits(Op, Demanded); 140 } 141 142 bool SimplifyDemandedBits(SDValue Op, const APInt &Demanded); 143 144 bool CombineToPreIndexedLoadStore(SDNode *N); 145 bool CombineToPostIndexedLoadStore(SDNode *N); 146 147 void ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad); 148 SDValue PromoteOperand(SDValue Op, EVT PVT, bool &Replace); 149 SDValue SExtPromoteOperand(SDValue Op, EVT PVT); 150 SDValue ZExtPromoteOperand(SDValue Op, EVT PVT); 151 SDValue PromoteIntBinOp(SDValue Op); 152 SDValue PromoteIntShiftOp(SDValue Op); 153 SDValue PromoteExtend(SDValue Op); 154 bool PromoteLoad(SDValue Op); 155 156 void ExtendSetCCUses(SmallVector<SDNode*, 4> SetCCs, 157 SDValue Trunc, SDValue ExtLoad, DebugLoc DL, 158 ISD::NodeType ExtType); 159 160 /// combine - call the node-specific routine that knows how to fold each 161 /// particular type of node. If that doesn't do anything, try the 162 /// target-specific DAG combines. 163 SDValue combine(SDNode *N); 164 165 // Visitation implementation - Implement dag node combining for different 166 // node types. The semantics are as follows: 167 // Return Value: 168 // SDValue.getNode() == 0 - No change was made 169 // SDValue.getNode() == N - N was replaced, is dead and has been handled. 170 // otherwise - N should be replaced by the returned Operand. 171 // 172 SDValue visitTokenFactor(SDNode *N); 173 SDValue visitMERGE_VALUES(SDNode *N); 174 SDValue visitADD(SDNode *N); 175 SDValue visitSUB(SDNode *N); 176 SDValue visitADDC(SDNode *N); 177 SDValue visitSUBC(SDNode *N); 178 SDValue visitADDE(SDNode *N); 179 SDValue visitSUBE(SDNode *N); 180 SDValue visitMUL(SDNode *N); 181 SDValue visitSDIV(SDNode *N); 182 SDValue visitUDIV(SDNode *N); 183 SDValue visitSREM(SDNode *N); 184 SDValue visitUREM(SDNode *N); 185 SDValue visitMULHU(SDNode *N); 186 SDValue visitMULHS(SDNode *N); 187 SDValue visitSMUL_LOHI(SDNode *N); 188 SDValue visitUMUL_LOHI(SDNode *N); 189 SDValue visitSMULO(SDNode *N); 190 SDValue visitUMULO(SDNode *N); 191 SDValue visitSDIVREM(SDNode *N); 192 SDValue visitUDIVREM(SDNode *N); 193 SDValue visitAND(SDNode *N); 194 SDValue visitOR(SDNode *N); 195 SDValue visitXOR(SDNode *N); 196 SDValue SimplifyVBinOp(SDNode *N); 197 SDValue visitSHL(SDNode *N); 198 SDValue visitSRA(SDNode *N); 199 SDValue visitSRL(SDNode *N); 200 SDValue visitCTLZ(SDNode *N); 201 SDValue visitCTLZ_ZERO_UNDEF(SDNode *N); 202 SDValue visitCTTZ(SDNode *N); 203 SDValue visitCTTZ_ZERO_UNDEF(SDNode *N); 204 SDValue visitCTPOP(SDNode *N); 205 SDValue visitSELECT(SDNode *N); 206 SDValue visitSELECT_CC(SDNode *N); 207 SDValue visitSETCC(SDNode *N); 208 SDValue visitSIGN_EXTEND(SDNode *N); 209 SDValue visitZERO_EXTEND(SDNode *N); 210 SDValue visitANY_EXTEND(SDNode *N); 211 SDValue visitSIGN_EXTEND_INREG(SDNode *N); 212 SDValue visitTRUNCATE(SDNode *N); 213 SDValue visitBITCAST(SDNode *N); 214 SDValue visitBUILD_PAIR(SDNode *N); 215 SDValue visitFADD(SDNode *N); 216 SDValue visitFSUB(SDNode *N); 217 SDValue visitFMUL(SDNode *N); 218 SDValue visitFDIV(SDNode *N); 219 SDValue visitFREM(SDNode *N); 220 SDValue visitFCOPYSIGN(SDNode *N); 221 SDValue visitSINT_TO_FP(SDNode *N); 222 SDValue visitUINT_TO_FP(SDNode *N); 223 SDValue visitFP_TO_SINT(SDNode *N); 224 SDValue visitFP_TO_UINT(SDNode *N); 225 SDValue visitFP_ROUND(SDNode *N); 226 SDValue visitFP_ROUND_INREG(SDNode *N); 227 SDValue visitFP_EXTEND(SDNode *N); 228 SDValue visitFNEG(SDNode *N); 229 SDValue visitFABS(SDNode *N); 230 SDValue visitBRCOND(SDNode *N); 231 SDValue visitBR_CC(SDNode *N); 232 SDValue visitLOAD(SDNode *N); 233 SDValue visitSTORE(SDNode *N); 234 SDValue visitINSERT_VECTOR_ELT(SDNode *N); 235 SDValue visitEXTRACT_VECTOR_ELT(SDNode *N); 236 SDValue visitBUILD_VECTOR(SDNode *N); 237 SDValue visitCONCAT_VECTORS(SDNode *N); 238 SDValue visitEXTRACT_SUBVECTOR(SDNode *N); 239 SDValue visitVECTOR_SHUFFLE(SDNode *N); 240 SDValue visitMEMBARRIER(SDNode *N); 241 242 SDValue XformToShuffleWithZero(SDNode *N); 243 SDValue ReassociateOps(unsigned Opc, DebugLoc DL, SDValue LHS, SDValue RHS); 244 245 SDValue visitShiftByConstant(SDNode *N, unsigned Amt); 246 247 bool SimplifySelectOps(SDNode *SELECT, SDValue LHS, SDValue RHS); 248 SDValue SimplifyBinOpWithSameOpcodeHands(SDNode *N); 249 SDValue SimplifySelect(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2); 250 SDValue SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2, 251 SDValue N3, ISD::CondCode CC, 252 bool NotExtCompare = false); 253 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond, 254 DebugLoc DL, bool foldBooleans = true); 255 SDValue SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 256 unsigned HiOp); 257 SDValue CombineConsecutiveLoads(SDNode *N, EVT VT); 258 SDValue ConstantFoldBITCASTofBUILD_VECTOR(SDNode *, EVT); 259 SDValue BuildSDIV(SDNode *N); 260 SDValue BuildUDIV(SDNode *N); 261 SDValue MatchBSwapHWordLow(SDNode *N, SDValue N0, SDValue N1, 262 bool DemandHighBits = true); 263 SDValue MatchBSwapHWord(SDNode *N, SDValue N0, SDValue N1); 264 SDNode *MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL); 265 SDValue ReduceLoadWidth(SDNode *N); 266 SDValue ReduceLoadOpStoreWidth(SDNode *N); 267 SDValue TransformFPLoadStorePair(SDNode *N); 268 269 SDValue GetDemandedBits(SDValue V, const APInt &Mask); 270 271 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 272 /// looking for aliasing nodes and adding them to the Aliases vector. 273 void GatherAllAliases(SDNode *N, SDValue OriginalChain, 274 SmallVector<SDValue, 8> &Aliases); 275 276 /// isAlias - Return true if there is any possibility that the two addresses 277 /// overlap. 278 bool isAlias(SDValue Ptr1, int64_t Size1, 279 const Value *SrcValue1, int SrcValueOffset1, 280 unsigned SrcValueAlign1, 281 const MDNode *TBAAInfo1, 282 SDValue Ptr2, int64_t Size2, 283 const Value *SrcValue2, int SrcValueOffset2, 284 unsigned SrcValueAlign2, 285 const MDNode *TBAAInfo2) const; 286 287 /// FindAliasInfo - Extracts the relevant alias information from the memory 288 /// node. Returns true if the operand was a load. 289 bool FindAliasInfo(SDNode *N, 290 SDValue &Ptr, int64_t &Size, 291 const Value *&SrcValue, int &SrcValueOffset, 292 unsigned &SrcValueAlignment, 293 const MDNode *&TBAAInfo) const; 294 295 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, 296 /// looking for a better chain (aliasing node.) 297 SDValue FindBetterChain(SDNode *N, SDValue Chain); 298 299 public: 300 DAGCombiner(SelectionDAG &D, AliasAnalysis &A, CodeGenOpt::Level OL) 301 : DAG(D), TLI(D.getTargetLoweringInfo()), Level(BeforeLegalizeTypes), 302 OptLevel(OL), LegalOperations(false), LegalTypes(false), AA(A) {} 303 304 /// Run - runs the dag combiner on all nodes in the work list 305 void Run(CombineLevel AtLevel); 306 307 SelectionDAG &getDAG() const { return DAG; } 308 309 /// getShiftAmountTy - Returns a type large enough to hold any valid 310 /// shift amount - before type legalization these can be huge. 311 EVT getShiftAmountTy(EVT LHSTy) { 312 return LegalTypes ? TLI.getShiftAmountTy(LHSTy) : TLI.getPointerTy(); 313 } 314 315 /// isTypeLegal - This method returns true if we are running before type 316 /// legalization or if the specified VT is legal. 317 bool isTypeLegal(const EVT &VT) { 318 if (!LegalTypes) return true; 319 return TLI.isTypeLegal(VT); 320 } 321 }; 322} 323 324 325namespace { 326/// WorkListRemover - This class is a DAGUpdateListener that removes any deleted 327/// nodes from the worklist. 328class WorkListRemover : public SelectionDAG::DAGUpdateListener { 329 DAGCombiner &DC; 330public: 331 explicit WorkListRemover(DAGCombiner &dc) : DC(dc) {} 332 333 virtual void NodeDeleted(SDNode *N, SDNode *E) { 334 DC.removeFromWorkList(N); 335 } 336 337 virtual void NodeUpdated(SDNode *N) { 338 // Ignore updates. 339 } 340}; 341} 342 343//===----------------------------------------------------------------------===// 344// TargetLowering::DAGCombinerInfo implementation 345//===----------------------------------------------------------------------===// 346 347void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) { 348 ((DAGCombiner*)DC)->AddToWorkList(N); 349} 350 351void TargetLowering::DAGCombinerInfo::RemoveFromWorklist(SDNode *N) { 352 ((DAGCombiner*)DC)->removeFromWorkList(N); 353} 354 355SDValue TargetLowering::DAGCombinerInfo:: 356CombineTo(SDNode *N, const std::vector<SDValue> &To, bool AddTo) { 357 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size(), AddTo); 358} 359 360SDValue TargetLowering::DAGCombinerInfo:: 361CombineTo(SDNode *N, SDValue Res, bool AddTo) { 362 return ((DAGCombiner*)DC)->CombineTo(N, Res, AddTo); 363} 364 365 366SDValue TargetLowering::DAGCombinerInfo:: 367CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo) { 368 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1, AddTo); 369} 370 371void TargetLowering::DAGCombinerInfo:: 372CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) { 373 return ((DAGCombiner*)DC)->CommitTargetLoweringOpt(TLO); 374} 375 376//===----------------------------------------------------------------------===// 377// Helper Functions 378//===----------------------------------------------------------------------===// 379 380/// isNegatibleForFree - Return 1 if we can compute the negated form of the 381/// specified expression for the same cost as the expression itself, or 2 if we 382/// can compute the negated form more cheaply than the expression itself. 383static char isNegatibleForFree(SDValue Op, bool LegalOperations, 384 const TargetLowering &TLI, 385 const TargetOptions *Options, 386 unsigned Depth = 0) { 387 // No compile time optimizations on this type. 388 if (Op.getValueType() == MVT::ppcf128) 389 return 0; 390 391 // fneg is removable even if it has multiple uses. 392 if (Op.getOpcode() == ISD::FNEG) return 2; 393 394 // Don't allow anything with multiple uses. 395 if (!Op.hasOneUse()) return 0; 396 397 // Don't recurse exponentially. 398 if (Depth > 6) return 0; 399 400 switch (Op.getOpcode()) { 401 default: return false; 402 case ISD::ConstantFP: 403 // Don't invert constant FP values after legalize. The negated constant 404 // isn't necessarily legal. 405 return LegalOperations ? 0 : 1; 406 case ISD::FADD: 407 // FIXME: determine better conditions for this xform. 408 if (!Options->UnsafeFPMath) return 0; 409 410 // After operation legalization, it might not be legal to create new FSUBs. 411 if (LegalOperations && 412 !TLI.isOperationLegalOrCustom(ISD::FSUB, Op.getValueType())) 413 return 0; 414 415 // fold (fsub (fadd A, B)) -> (fsub (fneg A), B) 416 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI, 417 Options, Depth + 1)) 418 return V; 419 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A) 420 return isNegatibleForFree(Op.getOperand(1), LegalOperations, TLI, Options, 421 Depth + 1); 422 case ISD::FSUB: 423 // We can't turn -(A-B) into B-A when we honor signed zeros. 424 if (!Options->UnsafeFPMath) return 0; 425 426 // fold (fneg (fsub A, B)) -> (fsub B, A) 427 return 1; 428 429 case ISD::FMUL: 430 case ISD::FDIV: 431 if (Options->HonorSignDependentRoundingFPMath()) return 0; 432 433 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) or (fmul X, (fneg Y)) 434 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI, 435 Options, Depth + 1)) 436 return V; 437 438 return isNegatibleForFree(Op.getOperand(1), LegalOperations, TLI, Options, 439 Depth + 1); 440 441 case ISD::FP_EXTEND: 442 case ISD::FP_ROUND: 443 case ISD::FSIN: 444 return isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI, Options, 445 Depth + 1); 446 } 447} 448 449/// GetNegatedExpression - If isNegatibleForFree returns true, this function 450/// returns the newly negated expression. 451static SDValue GetNegatedExpression(SDValue Op, SelectionDAG &DAG, 452 bool LegalOperations, unsigned Depth = 0) { 453 // fneg is removable even if it has multiple uses. 454 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0); 455 456 // Don't allow anything with multiple uses. 457 assert(Op.hasOneUse() && "Unknown reuse!"); 458 459 assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree"); 460 switch (Op.getOpcode()) { 461 default: llvm_unreachable("Unknown code"); 462 case ISD::ConstantFP: { 463 APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF(); 464 V.changeSign(); 465 return DAG.getConstantFP(V, Op.getValueType()); 466 } 467 case ISD::FADD: 468 // FIXME: determine better conditions for this xform. 469 assert(DAG.getTarget().Options.UnsafeFPMath); 470 471 // fold (fneg (fadd A, B)) -> (fsub (fneg A), B) 472 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, 473 DAG.getTargetLoweringInfo(), 474 &DAG.getTarget().Options, Depth+1)) 475 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 476 GetNegatedExpression(Op.getOperand(0), DAG, 477 LegalOperations, Depth+1), 478 Op.getOperand(1)); 479 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A) 480 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 481 GetNegatedExpression(Op.getOperand(1), DAG, 482 LegalOperations, Depth+1), 483 Op.getOperand(0)); 484 case ISD::FSUB: 485 // We can't turn -(A-B) into B-A when we honor signed zeros. 486 assert(DAG.getTarget().Options.UnsafeFPMath); 487 488 // fold (fneg (fsub 0, B)) -> B 489 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(Op.getOperand(0))) 490 if (N0CFP->getValueAPF().isZero()) 491 return Op.getOperand(1); 492 493 // fold (fneg (fsub A, B)) -> (fsub B, A) 494 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 495 Op.getOperand(1), Op.getOperand(0)); 496 497 case ISD::FMUL: 498 case ISD::FDIV: 499 assert(!DAG.getTarget().Options.HonorSignDependentRoundingFPMath()); 500 501 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) 502 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, 503 DAG.getTargetLoweringInfo(), 504 &DAG.getTarget().Options, Depth+1)) 505 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 506 GetNegatedExpression(Op.getOperand(0), DAG, 507 LegalOperations, Depth+1), 508 Op.getOperand(1)); 509 510 // fold (fneg (fmul X, Y)) -> (fmul X, (fneg Y)) 511 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 512 Op.getOperand(0), 513 GetNegatedExpression(Op.getOperand(1), DAG, 514 LegalOperations, Depth+1)); 515 516 case ISD::FP_EXTEND: 517 case ISD::FSIN: 518 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 519 GetNegatedExpression(Op.getOperand(0), DAG, 520 LegalOperations, Depth+1)); 521 case ISD::FP_ROUND: 522 return DAG.getNode(ISD::FP_ROUND, Op.getDebugLoc(), Op.getValueType(), 523 GetNegatedExpression(Op.getOperand(0), DAG, 524 LegalOperations, Depth+1), 525 Op.getOperand(1)); 526 } 527} 528 529 530// isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc 531// that selects between the values 1 and 0, making it equivalent to a setcc. 532// Also, set the incoming LHS, RHS, and CC references to the appropriate 533// nodes based on the type of node we are checking. This simplifies life a 534// bit for the callers. 535static bool isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS, 536 SDValue &CC) { 537 if (N.getOpcode() == ISD::SETCC) { 538 LHS = N.getOperand(0); 539 RHS = N.getOperand(1); 540 CC = N.getOperand(2); 541 return true; 542 } 543 if (N.getOpcode() == ISD::SELECT_CC && 544 N.getOperand(2).getOpcode() == ISD::Constant && 545 N.getOperand(3).getOpcode() == ISD::Constant && 546 cast<ConstantSDNode>(N.getOperand(2))->getAPIntValue() == 1 && 547 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) { 548 LHS = N.getOperand(0); 549 RHS = N.getOperand(1); 550 CC = N.getOperand(4); 551 return true; 552 } 553 return false; 554} 555 556// isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only 557// one use. If this is true, it allows the users to invert the operation for 558// free when it is profitable to do so. 559static bool isOneUseSetCC(SDValue N) { 560 SDValue N0, N1, N2; 561 if (isSetCCEquivalent(N, N0, N1, N2) && N.getNode()->hasOneUse()) 562 return true; 563 return false; 564} 565 566SDValue DAGCombiner::ReassociateOps(unsigned Opc, DebugLoc DL, 567 SDValue N0, SDValue N1) { 568 EVT VT = N0.getValueType(); 569 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) { 570 if (isa<ConstantSDNode>(N1)) { 571 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2)) 572 SDValue OpNode = 573 DAG.FoldConstantArithmetic(Opc, VT, 574 cast<ConstantSDNode>(N0.getOperand(1)), 575 cast<ConstantSDNode>(N1)); 576 return DAG.getNode(Opc, DL, VT, N0.getOperand(0), OpNode); 577 } 578 if (N0.hasOneUse()) { 579 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use 580 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT, 581 N0.getOperand(0), N1); 582 AddToWorkList(OpNode.getNode()); 583 return DAG.getNode(Opc, DL, VT, OpNode, N0.getOperand(1)); 584 } 585 } 586 587 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) { 588 if (isa<ConstantSDNode>(N0)) { 589 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2)) 590 SDValue OpNode = 591 DAG.FoldConstantArithmetic(Opc, VT, 592 cast<ConstantSDNode>(N1.getOperand(1)), 593 cast<ConstantSDNode>(N0)); 594 return DAG.getNode(Opc, DL, VT, N1.getOperand(0), OpNode); 595 } 596 if (N1.hasOneUse()) { 597 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use 598 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT, 599 N1.getOperand(0), N0); 600 AddToWorkList(OpNode.getNode()); 601 return DAG.getNode(Opc, DL, VT, OpNode, N1.getOperand(1)); 602 } 603 } 604 605 return SDValue(); 606} 607 608SDValue DAGCombiner::CombineTo(SDNode *N, const SDValue *To, unsigned NumTo, 609 bool AddTo) { 610 assert(N->getNumValues() == NumTo && "Broken CombineTo call!"); 611 ++NodesCombined; 612 DEBUG(dbgs() << "\nReplacing.1 "; 613 N->dump(&DAG); 614 dbgs() << "\nWith: "; 615 To[0].getNode()->dump(&DAG); 616 dbgs() << " and " << NumTo-1 << " other values\n"; 617 for (unsigned i = 0, e = NumTo; i != e; ++i) 618 assert((!To[i].getNode() || 619 N->getValueType(i) == To[i].getValueType()) && 620 "Cannot combine value to value of different type!")); 621 WorkListRemover DeadNodes(*this); 622 DAG.ReplaceAllUsesWith(N, To, &DeadNodes); 623 624 if (AddTo) { 625 // Push the new nodes and any users onto the worklist 626 for (unsigned i = 0, e = NumTo; i != e; ++i) { 627 if (To[i].getNode()) { 628 AddToWorkList(To[i].getNode()); 629 AddUsersToWorkList(To[i].getNode()); 630 } 631 } 632 } 633 634 // Finally, if the node is now dead, remove it from the graph. The node 635 // may not be dead if the replacement process recursively simplified to 636 // something else needing this node. 637 if (N->use_empty()) { 638 // Nodes can be reintroduced into the worklist. Make sure we do not 639 // process a node that has been replaced. 640 removeFromWorkList(N); 641 642 // Finally, since the node is now dead, remove it from the graph. 643 DAG.DeleteNode(N); 644 } 645 return SDValue(N, 0); 646} 647 648void DAGCombiner:: 649CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) { 650 // Replace all uses. If any nodes become isomorphic to other nodes and 651 // are deleted, make sure to remove them from our worklist. 652 WorkListRemover DeadNodes(*this); 653 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &DeadNodes); 654 655 // Push the new node and any (possibly new) users onto the worklist. 656 AddToWorkList(TLO.New.getNode()); 657 AddUsersToWorkList(TLO.New.getNode()); 658 659 // Finally, if the node is now dead, remove it from the graph. The node 660 // may not be dead if the replacement process recursively simplified to 661 // something else needing this node. 662 if (TLO.Old.getNode()->use_empty()) { 663 removeFromWorkList(TLO.Old.getNode()); 664 665 // If the operands of this node are only used by the node, they will now 666 // be dead. Make sure to visit them first to delete dead nodes early. 667 for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands(); i != e; ++i) 668 if (TLO.Old.getNode()->getOperand(i).getNode()->hasOneUse()) 669 AddToWorkList(TLO.Old.getNode()->getOperand(i).getNode()); 670 671 DAG.DeleteNode(TLO.Old.getNode()); 672 } 673} 674 675/// SimplifyDemandedBits - Check the specified integer node value to see if 676/// it can be simplified or if things it uses can be simplified by bit 677/// propagation. If so, return true. 678bool DAGCombiner::SimplifyDemandedBits(SDValue Op, const APInt &Demanded) { 679 TargetLowering::TargetLoweringOpt TLO(DAG, LegalTypes, LegalOperations); 680 APInt KnownZero, KnownOne; 681 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO)) 682 return false; 683 684 // Revisit the node. 685 AddToWorkList(Op.getNode()); 686 687 // Replace the old value with the new one. 688 ++NodesCombined; 689 DEBUG(dbgs() << "\nReplacing.2 "; 690 TLO.Old.getNode()->dump(&DAG); 691 dbgs() << "\nWith: "; 692 TLO.New.getNode()->dump(&DAG); 693 dbgs() << '\n'); 694 695 CommitTargetLoweringOpt(TLO); 696 return true; 697} 698 699void DAGCombiner::ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad) { 700 DebugLoc dl = Load->getDebugLoc(); 701 EVT VT = Load->getValueType(0); 702 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, VT, SDValue(ExtLoad, 0)); 703 704 DEBUG(dbgs() << "\nReplacing.9 "; 705 Load->dump(&DAG); 706 dbgs() << "\nWith: "; 707 Trunc.getNode()->dump(&DAG); 708 dbgs() << '\n'); 709 WorkListRemover DeadNodes(*this); 710 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 0), Trunc, &DeadNodes); 711 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 1), SDValue(ExtLoad, 1), 712 &DeadNodes); 713 removeFromWorkList(Load); 714 DAG.DeleteNode(Load); 715 AddToWorkList(Trunc.getNode()); 716} 717 718SDValue DAGCombiner::PromoteOperand(SDValue Op, EVT PVT, bool &Replace) { 719 Replace = false; 720 DebugLoc dl = Op.getDebugLoc(); 721 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Op)) { 722 EVT MemVT = LD->getMemoryVT(); 723 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD) 724 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT) ? ISD::ZEXTLOAD 725 : ISD::EXTLOAD) 726 : LD->getExtensionType(); 727 Replace = true; 728 return DAG.getExtLoad(ExtType, dl, PVT, 729 LD->getChain(), LD->getBasePtr(), 730 LD->getPointerInfo(), 731 MemVT, LD->isVolatile(), 732 LD->isNonTemporal(), LD->getAlignment()); 733 } 734 735 unsigned Opc = Op.getOpcode(); 736 switch (Opc) { 737 default: break; 738 case ISD::AssertSext: 739 return DAG.getNode(ISD::AssertSext, dl, PVT, 740 SExtPromoteOperand(Op.getOperand(0), PVT), 741 Op.getOperand(1)); 742 case ISD::AssertZext: 743 return DAG.getNode(ISD::AssertZext, dl, PVT, 744 ZExtPromoteOperand(Op.getOperand(0), PVT), 745 Op.getOperand(1)); 746 case ISD::Constant: { 747 unsigned ExtOpc = 748 Op.getValueType().isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; 749 return DAG.getNode(ExtOpc, dl, PVT, Op); 750 } 751 } 752 753 if (!TLI.isOperationLegal(ISD::ANY_EXTEND, PVT)) 754 return SDValue(); 755 return DAG.getNode(ISD::ANY_EXTEND, dl, PVT, Op); 756} 757 758SDValue DAGCombiner::SExtPromoteOperand(SDValue Op, EVT PVT) { 759 if (!TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, PVT)) 760 return SDValue(); 761 EVT OldVT = Op.getValueType(); 762 DebugLoc dl = Op.getDebugLoc(); 763 bool Replace = false; 764 SDValue NewOp = PromoteOperand(Op, PVT, Replace); 765 if (NewOp.getNode() == 0) 766 return SDValue(); 767 AddToWorkList(NewOp.getNode()); 768 769 if (Replace) 770 ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode()); 771 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NewOp.getValueType(), NewOp, 772 DAG.getValueType(OldVT)); 773} 774 775SDValue DAGCombiner::ZExtPromoteOperand(SDValue Op, EVT PVT) { 776 EVT OldVT = Op.getValueType(); 777 DebugLoc dl = Op.getDebugLoc(); 778 bool Replace = false; 779 SDValue NewOp = PromoteOperand(Op, PVT, Replace); 780 if (NewOp.getNode() == 0) 781 return SDValue(); 782 AddToWorkList(NewOp.getNode()); 783 784 if (Replace) 785 ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode()); 786 return DAG.getZeroExtendInReg(NewOp, dl, OldVT); 787} 788 789/// PromoteIntBinOp - Promote the specified integer binary operation if the 790/// target indicates it is beneficial. e.g. On x86, it's usually better to 791/// promote i16 operations to i32 since i16 instructions are longer. 792SDValue DAGCombiner::PromoteIntBinOp(SDValue Op) { 793 if (!LegalOperations) 794 return SDValue(); 795 796 EVT VT = Op.getValueType(); 797 if (VT.isVector() || !VT.isInteger()) 798 return SDValue(); 799 800 // If operation type is 'undesirable', e.g. i16 on x86, consider 801 // promoting it. 802 unsigned Opc = Op.getOpcode(); 803 if (TLI.isTypeDesirableForOp(Opc, VT)) 804 return SDValue(); 805 806 EVT PVT = VT; 807 // Consult target whether it is a good idea to promote this operation and 808 // what's the right type to promote it to. 809 if (TLI.IsDesirableToPromoteOp(Op, PVT)) { 810 assert(PVT != VT && "Don't know what type to promote to!"); 811 812 bool Replace0 = false; 813 SDValue N0 = Op.getOperand(0); 814 SDValue NN0 = PromoteOperand(N0, PVT, Replace0); 815 if (NN0.getNode() == 0) 816 return SDValue(); 817 818 bool Replace1 = false; 819 SDValue N1 = Op.getOperand(1); 820 SDValue NN1; 821 if (N0 == N1) 822 NN1 = NN0; 823 else { 824 NN1 = PromoteOperand(N1, PVT, Replace1); 825 if (NN1.getNode() == 0) 826 return SDValue(); 827 } 828 829 AddToWorkList(NN0.getNode()); 830 if (NN1.getNode()) 831 AddToWorkList(NN1.getNode()); 832 833 if (Replace0) 834 ReplaceLoadWithPromotedLoad(N0.getNode(), NN0.getNode()); 835 if (Replace1) 836 ReplaceLoadWithPromotedLoad(N1.getNode(), NN1.getNode()); 837 838 DEBUG(dbgs() << "\nPromoting "; 839 Op.getNode()->dump(&DAG)); 840 DebugLoc dl = Op.getDebugLoc(); 841 return DAG.getNode(ISD::TRUNCATE, dl, VT, 842 DAG.getNode(Opc, dl, PVT, NN0, NN1)); 843 } 844 return SDValue(); 845} 846 847/// PromoteIntShiftOp - Promote the specified integer shift operation if the 848/// target indicates it is beneficial. e.g. On x86, it's usually better to 849/// promote i16 operations to i32 since i16 instructions are longer. 850SDValue DAGCombiner::PromoteIntShiftOp(SDValue Op) { 851 if (!LegalOperations) 852 return SDValue(); 853 854 EVT VT = Op.getValueType(); 855 if (VT.isVector() || !VT.isInteger()) 856 return SDValue(); 857 858 // If operation type is 'undesirable', e.g. i16 on x86, consider 859 // promoting it. 860 unsigned Opc = Op.getOpcode(); 861 if (TLI.isTypeDesirableForOp(Opc, VT)) 862 return SDValue(); 863 864 EVT PVT = VT; 865 // Consult target whether it is a good idea to promote this operation and 866 // what's the right type to promote it to. 867 if (TLI.IsDesirableToPromoteOp(Op, PVT)) { 868 assert(PVT != VT && "Don't know what type to promote to!"); 869 870 bool Replace = false; 871 SDValue N0 = Op.getOperand(0); 872 if (Opc == ISD::SRA) 873 N0 = SExtPromoteOperand(Op.getOperand(0), PVT); 874 else if (Opc == ISD::SRL) 875 N0 = ZExtPromoteOperand(Op.getOperand(0), PVT); 876 else 877 N0 = PromoteOperand(N0, PVT, Replace); 878 if (N0.getNode() == 0) 879 return SDValue(); 880 881 AddToWorkList(N0.getNode()); 882 if (Replace) 883 ReplaceLoadWithPromotedLoad(Op.getOperand(0).getNode(), N0.getNode()); 884 885 DEBUG(dbgs() << "\nPromoting "; 886 Op.getNode()->dump(&DAG)); 887 DebugLoc dl = Op.getDebugLoc(); 888 return DAG.getNode(ISD::TRUNCATE, dl, VT, 889 DAG.getNode(Opc, dl, PVT, N0, Op.getOperand(1))); 890 } 891 return SDValue(); 892} 893 894SDValue DAGCombiner::PromoteExtend(SDValue Op) { 895 if (!LegalOperations) 896 return SDValue(); 897 898 EVT VT = Op.getValueType(); 899 if (VT.isVector() || !VT.isInteger()) 900 return SDValue(); 901 902 // If operation type is 'undesirable', e.g. i16 on x86, consider 903 // promoting it. 904 unsigned Opc = Op.getOpcode(); 905 if (TLI.isTypeDesirableForOp(Opc, VT)) 906 return SDValue(); 907 908 EVT PVT = VT; 909 // Consult target whether it is a good idea to promote this operation and 910 // what's the right type to promote it to. 911 if (TLI.IsDesirableToPromoteOp(Op, PVT)) { 912 assert(PVT != VT && "Don't know what type to promote to!"); 913 // fold (aext (aext x)) -> (aext x) 914 // fold (aext (zext x)) -> (zext x) 915 // fold (aext (sext x)) -> (sext x) 916 DEBUG(dbgs() << "\nPromoting "; 917 Op.getNode()->dump(&DAG)); 918 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), VT, Op.getOperand(0)); 919 } 920 return SDValue(); 921} 922 923bool DAGCombiner::PromoteLoad(SDValue Op) { 924 if (!LegalOperations) 925 return false; 926 927 EVT VT = Op.getValueType(); 928 if (VT.isVector() || !VT.isInteger()) 929 return false; 930 931 // If operation type is 'undesirable', e.g. i16 on x86, consider 932 // promoting it. 933 unsigned Opc = Op.getOpcode(); 934 if (TLI.isTypeDesirableForOp(Opc, VT)) 935 return false; 936 937 EVT PVT = VT; 938 // Consult target whether it is a good idea to promote this operation and 939 // what's the right type to promote it to. 940 if (TLI.IsDesirableToPromoteOp(Op, PVT)) { 941 assert(PVT != VT && "Don't know what type to promote to!"); 942 943 DebugLoc dl = Op.getDebugLoc(); 944 SDNode *N = Op.getNode(); 945 LoadSDNode *LD = cast<LoadSDNode>(N); 946 EVT MemVT = LD->getMemoryVT(); 947 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD) 948 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT) ? ISD::ZEXTLOAD 949 : ISD::EXTLOAD) 950 : LD->getExtensionType(); 951 SDValue NewLD = DAG.getExtLoad(ExtType, dl, PVT, 952 LD->getChain(), LD->getBasePtr(), 953 LD->getPointerInfo(), 954 MemVT, LD->isVolatile(), 955 LD->isNonTemporal(), LD->getAlignment()); 956 SDValue Result = DAG.getNode(ISD::TRUNCATE, dl, VT, NewLD); 957 958 DEBUG(dbgs() << "\nPromoting "; 959 N->dump(&DAG); 960 dbgs() << "\nTo: "; 961 Result.getNode()->dump(&DAG); 962 dbgs() << '\n'); 963 WorkListRemover DeadNodes(*this); 964 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result, &DeadNodes); 965 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), NewLD.getValue(1), &DeadNodes); 966 removeFromWorkList(N); 967 DAG.DeleteNode(N); 968 AddToWorkList(Result.getNode()); 969 return true; 970 } 971 return false; 972} 973 974 975//===----------------------------------------------------------------------===// 976// Main DAG Combiner implementation 977//===----------------------------------------------------------------------===// 978 979void DAGCombiner::Run(CombineLevel AtLevel) { 980 // set the instance variables, so that the various visit routines may use it. 981 Level = AtLevel; 982 LegalOperations = Level >= AfterLegalizeVectorOps; 983 LegalTypes = Level >= AfterLegalizeTypes; 984 985 // Add all the dag nodes to the worklist. 986 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 987 E = DAG.allnodes_end(); I != E; ++I) 988 AddToWorkList(I); 989 990 // Create a dummy node (which is not added to allnodes), that adds a reference 991 // to the root node, preventing it from being deleted, and tracking any 992 // changes of the root. 993 HandleSDNode Dummy(DAG.getRoot()); 994 995 // The root of the dag may dangle to deleted nodes until the dag combiner is 996 // done. Set it to null to avoid confusion. 997 DAG.setRoot(SDValue()); 998 999 // while the worklist isn't empty, find a node and 1000 // try and combine it. 1001 while (!WorkListContents.empty()) { 1002 SDNode *N; 1003 // The WorkListOrder holds the SDNodes in order, but it may contain duplicates. 1004 // In order to avoid a linear scan, we use a set (O(log N)) to hold what the 1005 // worklist *should* contain, and check the node we want to visit is should 1006 // actually be visited. 1007 do { 1008 N = WorkListOrder.pop_back_val(); 1009 } while (!WorkListContents.erase(N)); 1010 1011 // If N has no uses, it is dead. Make sure to revisit all N's operands once 1012 // N is deleted from the DAG, since they too may now be dead or may have a 1013 // reduced number of uses, allowing other xforms. 1014 if (N->use_empty() && N != &Dummy) { 1015 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 1016 AddToWorkList(N->getOperand(i).getNode()); 1017 1018 DAG.DeleteNode(N); 1019 continue; 1020 } 1021 1022 SDValue RV = combine(N); 1023 1024 if (RV.getNode() == 0) 1025 continue; 1026 1027 ++NodesCombined; 1028 1029 // If we get back the same node we passed in, rather than a new node or 1030 // zero, we know that the node must have defined multiple values and 1031 // CombineTo was used. Since CombineTo takes care of the worklist 1032 // mechanics for us, we have no work to do in this case. 1033 if (RV.getNode() == N) 1034 continue; 1035 1036 assert(N->getOpcode() != ISD::DELETED_NODE && 1037 RV.getNode()->getOpcode() != ISD::DELETED_NODE && 1038 "Node was deleted but visit returned new node!"); 1039 1040 DEBUG(dbgs() << "\nReplacing.3 "; 1041 N->dump(&DAG); 1042 dbgs() << "\nWith: "; 1043 RV.getNode()->dump(&DAG); 1044 dbgs() << '\n'); 1045 1046 // Transfer debug value. 1047 DAG.TransferDbgValues(SDValue(N, 0), RV); 1048 WorkListRemover DeadNodes(*this); 1049 if (N->getNumValues() == RV.getNode()->getNumValues()) 1050 DAG.ReplaceAllUsesWith(N, RV.getNode(), &DeadNodes); 1051 else { 1052 assert(N->getValueType(0) == RV.getValueType() && 1053 N->getNumValues() == 1 && "Type mismatch"); 1054 SDValue OpV = RV; 1055 DAG.ReplaceAllUsesWith(N, &OpV, &DeadNodes); 1056 } 1057 1058 // Push the new node and any users onto the worklist 1059 AddToWorkList(RV.getNode()); 1060 AddUsersToWorkList(RV.getNode()); 1061 1062 // Add any uses of the old node to the worklist in case this node is the 1063 // last one that uses them. They may become dead after this node is 1064 // deleted. 1065 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 1066 AddToWorkList(N->getOperand(i).getNode()); 1067 1068 // Finally, if the node is now dead, remove it from the graph. The node 1069 // may not be dead if the replacement process recursively simplified to 1070 // something else needing this node. 1071 if (N->use_empty()) { 1072 // Nodes can be reintroduced into the worklist. Make sure we do not 1073 // process a node that has been replaced. 1074 removeFromWorkList(N); 1075 1076 // Finally, since the node is now dead, remove it from the graph. 1077 DAG.DeleteNode(N); 1078 } 1079 } 1080 1081 // If the root changed (e.g. it was a dead load, update the root). 1082 DAG.setRoot(Dummy.getValue()); 1083} 1084 1085SDValue DAGCombiner::visit(SDNode *N) { 1086 switch (N->getOpcode()) { 1087 default: break; 1088 case ISD::TokenFactor: return visitTokenFactor(N); 1089 case ISD::MERGE_VALUES: return visitMERGE_VALUES(N); 1090 case ISD::ADD: return visitADD(N); 1091 case ISD::SUB: return visitSUB(N); 1092 case ISD::ADDC: return visitADDC(N); 1093 case ISD::SUBC: return visitSUBC(N); 1094 case ISD::ADDE: return visitADDE(N); 1095 case ISD::SUBE: return visitSUBE(N); 1096 case ISD::MUL: return visitMUL(N); 1097 case ISD::SDIV: return visitSDIV(N); 1098 case ISD::UDIV: return visitUDIV(N); 1099 case ISD::SREM: return visitSREM(N); 1100 case ISD::UREM: return visitUREM(N); 1101 case ISD::MULHU: return visitMULHU(N); 1102 case ISD::MULHS: return visitMULHS(N); 1103 case ISD::SMUL_LOHI: return visitSMUL_LOHI(N); 1104 case ISD::UMUL_LOHI: return visitUMUL_LOHI(N); 1105 case ISD::SMULO: return visitSMULO(N); 1106 case ISD::UMULO: return visitUMULO(N); 1107 case ISD::SDIVREM: return visitSDIVREM(N); 1108 case ISD::UDIVREM: return visitUDIVREM(N); 1109 case ISD::AND: return visitAND(N); 1110 case ISD::OR: return visitOR(N); 1111 case ISD::XOR: return visitXOR(N); 1112 case ISD::SHL: return visitSHL(N); 1113 case ISD::SRA: return visitSRA(N); 1114 case ISD::SRL: return visitSRL(N); 1115 case ISD::CTLZ: return visitCTLZ(N); 1116 case ISD::CTLZ_ZERO_UNDEF: return visitCTLZ_ZERO_UNDEF(N); 1117 case ISD::CTTZ: return visitCTTZ(N); 1118 case ISD::CTTZ_ZERO_UNDEF: return visitCTTZ_ZERO_UNDEF(N); 1119 case ISD::CTPOP: return visitCTPOP(N); 1120 case ISD::SELECT: return visitSELECT(N); 1121 case ISD::SELECT_CC: return visitSELECT_CC(N); 1122 case ISD::SETCC: return visitSETCC(N); 1123 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N); 1124 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N); 1125 case ISD::ANY_EXTEND: return visitANY_EXTEND(N); 1126 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N); 1127 case ISD::TRUNCATE: return visitTRUNCATE(N); 1128 case ISD::BITCAST: return visitBITCAST(N); 1129 case ISD::BUILD_PAIR: return visitBUILD_PAIR(N); 1130 case ISD::FADD: return visitFADD(N); 1131 case ISD::FSUB: return visitFSUB(N); 1132 case ISD::FMUL: return visitFMUL(N); 1133 case ISD::FDIV: return visitFDIV(N); 1134 case ISD::FREM: return visitFREM(N); 1135 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N); 1136 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N); 1137 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N); 1138 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N); 1139 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N); 1140 case ISD::FP_ROUND: return visitFP_ROUND(N); 1141 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N); 1142 case ISD::FP_EXTEND: return visitFP_EXTEND(N); 1143 case ISD::FNEG: return visitFNEG(N); 1144 case ISD::FABS: return visitFABS(N); 1145 case ISD::BRCOND: return visitBRCOND(N); 1146 case ISD::BR_CC: return visitBR_CC(N); 1147 case ISD::LOAD: return visitLOAD(N); 1148 case ISD::STORE: return visitSTORE(N); 1149 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N); 1150 case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N); 1151 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N); 1152 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N); 1153 case ISD::EXTRACT_SUBVECTOR: return visitEXTRACT_SUBVECTOR(N); 1154 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N); 1155 case ISD::MEMBARRIER: return visitMEMBARRIER(N); 1156 } 1157 return SDValue(); 1158} 1159 1160SDValue DAGCombiner::combine(SDNode *N) { 1161 SDValue RV = visit(N); 1162 1163 // If nothing happened, try a target-specific DAG combine. 1164 if (RV.getNode() == 0) { 1165 assert(N->getOpcode() != ISD::DELETED_NODE && 1166 "Node was deleted but visit returned NULL!"); 1167 1168 if (N->getOpcode() >= ISD::BUILTIN_OP_END || 1169 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) { 1170 1171 // Expose the DAG combiner to the target combiner impls. 1172 TargetLowering::DAGCombinerInfo 1173 DagCombineInfo(DAG, !LegalTypes, !LegalOperations, false, this); 1174 1175 RV = TLI.PerformDAGCombine(N, DagCombineInfo); 1176 } 1177 } 1178 1179 // If nothing happened still, try promoting the operation. 1180 if (RV.getNode() == 0) { 1181 switch (N->getOpcode()) { 1182 default: break; 1183 case ISD::ADD: 1184 case ISD::SUB: 1185 case ISD::MUL: 1186 case ISD::AND: 1187 case ISD::OR: 1188 case ISD::XOR: 1189 RV = PromoteIntBinOp(SDValue(N, 0)); 1190 break; 1191 case ISD::SHL: 1192 case ISD::SRA: 1193 case ISD::SRL: 1194 RV = PromoteIntShiftOp(SDValue(N, 0)); 1195 break; 1196 case ISD::SIGN_EXTEND: 1197 case ISD::ZERO_EXTEND: 1198 case ISD::ANY_EXTEND: 1199 RV = PromoteExtend(SDValue(N, 0)); 1200 break; 1201 case ISD::LOAD: 1202 if (PromoteLoad(SDValue(N, 0))) 1203 RV = SDValue(N, 0); 1204 break; 1205 } 1206 } 1207 1208 // If N is a commutative binary node, try commuting it to enable more 1209 // sdisel CSE. 1210 if (RV.getNode() == 0 && 1211 SelectionDAG::isCommutativeBinOp(N->getOpcode()) && 1212 N->getNumValues() == 1) { 1213 SDValue N0 = N->getOperand(0); 1214 SDValue N1 = N->getOperand(1); 1215 1216 // Constant operands are canonicalized to RHS. 1217 if (isa<ConstantSDNode>(N0) || !isa<ConstantSDNode>(N1)) { 1218 SDValue Ops[] = { N1, N0 }; 1219 SDNode *CSENode = DAG.getNodeIfExists(N->getOpcode(), N->getVTList(), 1220 Ops, 2); 1221 if (CSENode) 1222 return SDValue(CSENode, 0); 1223 } 1224 } 1225 1226 return RV; 1227} 1228 1229/// getInputChainForNode - Given a node, return its input chain if it has one, 1230/// otherwise return a null sd operand. 1231static SDValue getInputChainForNode(SDNode *N) { 1232 if (unsigned NumOps = N->getNumOperands()) { 1233 if (N->getOperand(0).getValueType() == MVT::Other) 1234 return N->getOperand(0); 1235 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other) 1236 return N->getOperand(NumOps-1); 1237 for (unsigned i = 1; i < NumOps-1; ++i) 1238 if (N->getOperand(i).getValueType() == MVT::Other) 1239 return N->getOperand(i); 1240 } 1241 return SDValue(); 1242} 1243 1244SDValue DAGCombiner::visitTokenFactor(SDNode *N) { 1245 // If N has two operands, where one has an input chain equal to the other, 1246 // the 'other' chain is redundant. 1247 if (N->getNumOperands() == 2) { 1248 if (getInputChainForNode(N->getOperand(0).getNode()) == N->getOperand(1)) 1249 return N->getOperand(0); 1250 if (getInputChainForNode(N->getOperand(1).getNode()) == N->getOperand(0)) 1251 return N->getOperand(1); 1252 } 1253 1254 SmallVector<SDNode *, 8> TFs; // List of token factors to visit. 1255 SmallVector<SDValue, 8> Ops; // Ops for replacing token factor. 1256 SmallPtrSet<SDNode*, 16> SeenOps; 1257 bool Changed = false; // If we should replace this token factor. 1258 1259 // Start out with this token factor. 1260 TFs.push_back(N); 1261 1262 // Iterate through token factors. The TFs grows when new token factors are 1263 // encountered. 1264 for (unsigned i = 0; i < TFs.size(); ++i) { 1265 SDNode *TF = TFs[i]; 1266 1267 // Check each of the operands. 1268 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) { 1269 SDValue Op = TF->getOperand(i); 1270 1271 switch (Op.getOpcode()) { 1272 case ISD::EntryToken: 1273 // Entry tokens don't need to be added to the list. They are 1274 // rededundant. 1275 Changed = true; 1276 break; 1277 1278 case ISD::TokenFactor: 1279 if (Op.hasOneUse() && 1280 std::find(TFs.begin(), TFs.end(), Op.getNode()) == TFs.end()) { 1281 // Queue up for processing. 1282 TFs.push_back(Op.getNode()); 1283 // Clean up in case the token factor is removed. 1284 AddToWorkList(Op.getNode()); 1285 Changed = true; 1286 break; 1287 } 1288 // Fall thru 1289 1290 default: 1291 // Only add if it isn't already in the list. 1292 if (SeenOps.insert(Op.getNode())) 1293 Ops.push_back(Op); 1294 else 1295 Changed = true; 1296 break; 1297 } 1298 } 1299 } 1300 1301 SDValue Result; 1302 1303 // If we've change things around then replace token factor. 1304 if (Changed) { 1305 if (Ops.empty()) { 1306 // The entry token is the only possible outcome. 1307 Result = DAG.getEntryNode(); 1308 } else { 1309 // New and improved token factor. 1310 Result = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 1311 MVT::Other, &Ops[0], Ops.size()); 1312 } 1313 1314 // Don't add users to work list. 1315 return CombineTo(N, Result, false); 1316 } 1317 1318 return Result; 1319} 1320 1321/// MERGE_VALUES can always be eliminated. 1322SDValue DAGCombiner::visitMERGE_VALUES(SDNode *N) { 1323 WorkListRemover DeadNodes(*this); 1324 // Replacing results may cause a different MERGE_VALUES to suddenly 1325 // be CSE'd with N, and carry its uses with it. Iterate until no 1326 // uses remain, to ensure that the node can be safely deleted. 1327 do { 1328 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 1329 DAG.ReplaceAllUsesOfValueWith(SDValue(N, i), N->getOperand(i), 1330 &DeadNodes); 1331 } while (!N->use_empty()); 1332 removeFromWorkList(N); 1333 DAG.DeleteNode(N); 1334 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1335} 1336 1337static 1338SDValue combineShlAddConstant(DebugLoc DL, SDValue N0, SDValue N1, 1339 SelectionDAG &DAG) { 1340 EVT VT = N0.getValueType(); 1341 SDValue N00 = N0.getOperand(0); 1342 SDValue N01 = N0.getOperand(1); 1343 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01); 1344 1345 if (N01C && N00.getOpcode() == ISD::ADD && N00.getNode()->hasOneUse() && 1346 isa<ConstantSDNode>(N00.getOperand(1))) { 1347 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 1348 N0 = DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, 1349 DAG.getNode(ISD::SHL, N00.getDebugLoc(), VT, 1350 N00.getOperand(0), N01), 1351 DAG.getNode(ISD::SHL, N01.getDebugLoc(), VT, 1352 N00.getOperand(1), N01)); 1353 return DAG.getNode(ISD::ADD, DL, VT, N0, N1); 1354 } 1355 1356 return SDValue(); 1357} 1358 1359SDValue DAGCombiner::visitADD(SDNode *N) { 1360 SDValue N0 = N->getOperand(0); 1361 SDValue N1 = N->getOperand(1); 1362 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1363 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1364 EVT VT = N0.getValueType(); 1365 1366 // fold vector ops 1367 if (VT.isVector()) { 1368 SDValue FoldedVOp = SimplifyVBinOp(N); 1369 if (FoldedVOp.getNode()) return FoldedVOp; 1370 } 1371 1372 // fold (add x, undef) -> undef 1373 if (N0.getOpcode() == ISD::UNDEF) 1374 return N0; 1375 if (N1.getOpcode() == ISD::UNDEF) 1376 return N1; 1377 // fold (add c1, c2) -> c1+c2 1378 if (N0C && N1C) 1379 return DAG.FoldConstantArithmetic(ISD::ADD, VT, N0C, N1C); 1380 // canonicalize constant to RHS 1381 if (N0C && !N1C) 1382 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0); 1383 // fold (add x, 0) -> x 1384 if (N1C && N1C->isNullValue()) 1385 return N0; 1386 // fold (add Sym, c) -> Sym+c 1387 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0)) 1388 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA) && N1C && 1389 GA->getOpcode() == ISD::GlobalAddress) 1390 return DAG.getGlobalAddress(GA->getGlobal(), N1C->getDebugLoc(), VT, 1391 GA->getOffset() + 1392 (uint64_t)N1C->getSExtValue()); 1393 // fold ((c1-A)+c2) -> (c1+c2)-A 1394 if (N1C && N0.getOpcode() == ISD::SUB) 1395 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0))) 1396 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1397 DAG.getConstant(N1C->getAPIntValue()+ 1398 N0C->getAPIntValue(), VT), 1399 N0.getOperand(1)); 1400 // reassociate add 1401 SDValue RADD = ReassociateOps(ISD::ADD, N->getDebugLoc(), N0, N1); 1402 if (RADD.getNode() != 0) 1403 return RADD; 1404 // fold ((0-A) + B) -> B-A 1405 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) && 1406 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue()) 1407 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1, N0.getOperand(1)); 1408 // fold (A + (0-B)) -> A-B 1409 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) && 1410 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue()) 1411 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, N1.getOperand(1)); 1412 // fold (A+(B-A)) -> B 1413 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1)) 1414 return N1.getOperand(0); 1415 // fold ((B-A)+A) -> B 1416 if (N0.getOpcode() == ISD::SUB && N1 == N0.getOperand(1)) 1417 return N0.getOperand(0); 1418 // fold (A+(B-(A+C))) to (B-C) 1419 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD && 1420 N0 == N1.getOperand(1).getOperand(0)) 1421 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0), 1422 N1.getOperand(1).getOperand(1)); 1423 // fold (A+(B-(C+A))) to (B-C) 1424 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD && 1425 N0 == N1.getOperand(1).getOperand(1)) 1426 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0), 1427 N1.getOperand(1).getOperand(0)); 1428 // fold (A+((B-A)+or-C)) to (B+or-C) 1429 if ((N1.getOpcode() == ISD::SUB || N1.getOpcode() == ISD::ADD) && 1430 N1.getOperand(0).getOpcode() == ISD::SUB && 1431 N0 == N1.getOperand(0).getOperand(1)) 1432 return DAG.getNode(N1.getOpcode(), N->getDebugLoc(), VT, 1433 N1.getOperand(0).getOperand(0), N1.getOperand(1)); 1434 1435 // fold (A-B)+(C-D) to (A+C)-(B+D) when A or C is constant 1436 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB) { 1437 SDValue N00 = N0.getOperand(0); 1438 SDValue N01 = N0.getOperand(1); 1439 SDValue N10 = N1.getOperand(0); 1440 SDValue N11 = N1.getOperand(1); 1441 1442 if (isa<ConstantSDNode>(N00) || isa<ConstantSDNode>(N10)) 1443 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1444 DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, N00, N10), 1445 DAG.getNode(ISD::ADD, N1.getDebugLoc(), VT, N01, N11)); 1446 } 1447 1448 if (!VT.isVector() && SimplifyDemandedBits(SDValue(N, 0))) 1449 return SDValue(N, 0); 1450 1451 // fold (a+b) -> (a|b) iff a and b share no bits. 1452 if (VT.isInteger() && !VT.isVector()) { 1453 APInt LHSZero, LHSOne; 1454 APInt RHSZero, RHSOne; 1455 DAG.ComputeMaskedBits(N0, LHSZero, LHSOne); 1456 1457 if (LHSZero.getBoolValue()) { 1458 DAG.ComputeMaskedBits(N1, RHSZero, RHSOne); 1459 1460 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1461 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1462 if ((RHSZero & ~LHSZero) == ~LHSZero || (LHSZero & ~RHSZero) == ~RHSZero) 1463 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1); 1464 } 1465 } 1466 1467 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 1468 if (N0.getOpcode() == ISD::SHL && N0.getNode()->hasOneUse()) { 1469 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N0, N1, DAG); 1470 if (Result.getNode()) return Result; 1471 } 1472 if (N1.getOpcode() == ISD::SHL && N1.getNode()->hasOneUse()) { 1473 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N1, N0, DAG); 1474 if (Result.getNode()) return Result; 1475 } 1476 1477 // fold (add x, shl(0 - y, n)) -> sub(x, shl(y, n)) 1478 if (N1.getOpcode() == ISD::SHL && 1479 N1.getOperand(0).getOpcode() == ISD::SUB) 1480 if (ConstantSDNode *C = 1481 dyn_cast<ConstantSDNode>(N1.getOperand(0).getOperand(0))) 1482 if (C->getAPIntValue() == 0) 1483 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, 1484 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1485 N1.getOperand(0).getOperand(1), 1486 N1.getOperand(1))); 1487 if (N0.getOpcode() == ISD::SHL && 1488 N0.getOperand(0).getOpcode() == ISD::SUB) 1489 if (ConstantSDNode *C = 1490 dyn_cast<ConstantSDNode>(N0.getOperand(0).getOperand(0))) 1491 if (C->getAPIntValue() == 0) 1492 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1, 1493 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1494 N0.getOperand(0).getOperand(1), 1495 N0.getOperand(1))); 1496 1497 if (N1.getOpcode() == ISD::AND) { 1498 SDValue AndOp0 = N1.getOperand(0); 1499 ConstantSDNode *AndOp1 = dyn_cast<ConstantSDNode>(N1->getOperand(1)); 1500 unsigned NumSignBits = DAG.ComputeNumSignBits(AndOp0); 1501 unsigned DestBits = VT.getScalarType().getSizeInBits(); 1502 1503 // (add z, (and (sbbl x, x), 1)) -> (sub z, (sbbl x, x)) 1504 // and similar xforms where the inner op is either ~0 or 0. 1505 if (NumSignBits == DestBits && AndOp1 && AndOp1->isOne()) { 1506 DebugLoc DL = N->getDebugLoc(); 1507 return DAG.getNode(ISD::SUB, DL, VT, N->getOperand(0), AndOp0); 1508 } 1509 } 1510 1511 // add (sext i1), X -> sub X, (zext i1) 1512 if (N0.getOpcode() == ISD::SIGN_EXTEND && 1513 N0.getOperand(0).getValueType() == MVT::i1 && 1514 !TLI.isOperationLegal(ISD::SIGN_EXTEND, MVT::i1)) { 1515 DebugLoc DL = N->getDebugLoc(); 1516 SDValue ZExt = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0)); 1517 return DAG.getNode(ISD::SUB, DL, VT, N1, ZExt); 1518 } 1519 1520 return SDValue(); 1521} 1522 1523SDValue DAGCombiner::visitADDC(SDNode *N) { 1524 SDValue N0 = N->getOperand(0); 1525 SDValue N1 = N->getOperand(1); 1526 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1527 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1528 EVT VT = N0.getValueType(); 1529 1530 // If the flag result is dead, turn this into an ADD. 1531 if (!N->hasAnyUseOfValue(1)) 1532 return CombineTo(N, DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, N1), 1533 DAG.getNode(ISD::CARRY_FALSE, 1534 N->getDebugLoc(), MVT::Glue)); 1535 1536 // canonicalize constant to RHS. 1537 if (N0C && !N1C) 1538 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0); 1539 1540 // fold (addc x, 0) -> x + no carry out 1541 if (N1C && N1C->isNullValue()) 1542 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, 1543 N->getDebugLoc(), MVT::Glue)); 1544 1545 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits. 1546 APInt LHSZero, LHSOne; 1547 APInt RHSZero, RHSOne; 1548 DAG.ComputeMaskedBits(N0, LHSZero, LHSOne); 1549 1550 if (LHSZero.getBoolValue()) { 1551 DAG.ComputeMaskedBits(N1, RHSZero, RHSOne); 1552 1553 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1554 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1555 if ((RHSZero & ~LHSZero) == ~LHSZero || (LHSZero & ~RHSZero) == ~RHSZero) 1556 return CombineTo(N, DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1), 1557 DAG.getNode(ISD::CARRY_FALSE, 1558 N->getDebugLoc(), MVT::Glue)); 1559 } 1560 1561 return SDValue(); 1562} 1563 1564SDValue DAGCombiner::visitADDE(SDNode *N) { 1565 SDValue N0 = N->getOperand(0); 1566 SDValue N1 = N->getOperand(1); 1567 SDValue CarryIn = N->getOperand(2); 1568 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1569 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1570 1571 // canonicalize constant to RHS 1572 if (N0C && !N1C) 1573 return DAG.getNode(ISD::ADDE, N->getDebugLoc(), N->getVTList(), 1574 N1, N0, CarryIn); 1575 1576 // fold (adde x, y, false) -> (addc x, y) 1577 if (CarryIn.getOpcode() == ISD::CARRY_FALSE) 1578 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N0, N1); 1579 1580 return SDValue(); 1581} 1582 1583// Since it may not be valid to emit a fold to zero for vector initializers 1584// check if we can before folding. 1585static SDValue tryFoldToZero(DebugLoc DL, const TargetLowering &TLI, EVT VT, 1586 SelectionDAG &DAG, bool LegalOperations) { 1587 if (!VT.isVector()) { 1588 return DAG.getConstant(0, VT); 1589 } 1590 if (!LegalOperations || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) { 1591 // Produce a vector of zeros. 1592 SDValue El = DAG.getConstant(0, VT.getVectorElementType()); 1593 std::vector<SDValue> Ops(VT.getVectorNumElements(), El); 1594 return DAG.getNode(ISD::BUILD_VECTOR, DL, VT, 1595 &Ops[0], Ops.size()); 1596 } 1597 return SDValue(); 1598} 1599 1600SDValue DAGCombiner::visitSUB(SDNode *N) { 1601 SDValue N0 = N->getOperand(0); 1602 SDValue N1 = N->getOperand(1); 1603 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1604 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1605 ConstantSDNode *N1C1 = N1.getOpcode() != ISD::ADD ? 0 : 1606 dyn_cast<ConstantSDNode>(N1.getOperand(1).getNode()); 1607 EVT VT = N0.getValueType(); 1608 1609 // fold vector ops 1610 if (VT.isVector()) { 1611 SDValue FoldedVOp = SimplifyVBinOp(N); 1612 if (FoldedVOp.getNode()) return FoldedVOp; 1613 } 1614 1615 // fold (sub x, x) -> 0 1616 // FIXME: Refactor this and xor and other similar operations together. 1617 if (N0 == N1) 1618 return tryFoldToZero(N->getDebugLoc(), TLI, VT, DAG, LegalOperations); 1619 // fold (sub c1, c2) -> c1-c2 1620 if (N0C && N1C) 1621 return DAG.FoldConstantArithmetic(ISD::SUB, VT, N0C, N1C); 1622 // fold (sub x, c) -> (add x, -c) 1623 if (N1C) 1624 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, 1625 DAG.getConstant(-N1C->getAPIntValue(), VT)); 1626 // Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1) 1627 if (N0C && N0C->isAllOnesValue()) 1628 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0); 1629 // fold A-(A-B) -> B 1630 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(0)) 1631 return N1.getOperand(1); 1632 // fold (A+B)-A -> B 1633 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1) 1634 return N0.getOperand(1); 1635 // fold (A+B)-B -> A 1636 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1) 1637 return N0.getOperand(0); 1638 // fold C2-(A+C1) -> (C2-C1)-A 1639 if (N1.getOpcode() == ISD::ADD && N0C && N1C1) { 1640 SDValue NewC = DAG.getConstant((N0C->getAPIntValue() - N1C1->getAPIntValue()), VT); 1641 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, NewC, 1642 N1.getOperand(0)); 1643 } 1644 // fold ((A+(B+or-C))-B) -> A+or-C 1645 if (N0.getOpcode() == ISD::ADD && 1646 (N0.getOperand(1).getOpcode() == ISD::SUB || 1647 N0.getOperand(1).getOpcode() == ISD::ADD) && 1648 N0.getOperand(1).getOperand(0) == N1) 1649 return DAG.getNode(N0.getOperand(1).getOpcode(), N->getDebugLoc(), VT, 1650 N0.getOperand(0), N0.getOperand(1).getOperand(1)); 1651 // fold ((A+(C+B))-B) -> A+C 1652 if (N0.getOpcode() == ISD::ADD && 1653 N0.getOperand(1).getOpcode() == ISD::ADD && 1654 N0.getOperand(1).getOperand(1) == N1) 1655 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, 1656 N0.getOperand(0), N0.getOperand(1).getOperand(0)); 1657 // fold ((A-(B-C))-C) -> A-B 1658 if (N0.getOpcode() == ISD::SUB && 1659 N0.getOperand(1).getOpcode() == ISD::SUB && 1660 N0.getOperand(1).getOperand(1) == N1) 1661 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1662 N0.getOperand(0), N0.getOperand(1).getOperand(0)); 1663 1664 // If either operand of a sub is undef, the result is undef 1665 if (N0.getOpcode() == ISD::UNDEF) 1666 return N0; 1667 if (N1.getOpcode() == ISD::UNDEF) 1668 return N1; 1669 1670 // If the relocation model supports it, consider symbol offsets. 1671 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0)) 1672 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA)) { 1673 // fold (sub Sym, c) -> Sym-c 1674 if (N1C && GA->getOpcode() == ISD::GlobalAddress) 1675 return DAG.getGlobalAddress(GA->getGlobal(), N1C->getDebugLoc(), VT, 1676 GA->getOffset() - 1677 (uint64_t)N1C->getSExtValue()); 1678 // fold (sub Sym+c1, Sym+c2) -> c1-c2 1679 if (GlobalAddressSDNode *GB = dyn_cast<GlobalAddressSDNode>(N1)) 1680 if (GA->getGlobal() == GB->getGlobal()) 1681 return DAG.getConstant((uint64_t)GA->getOffset() - GB->getOffset(), 1682 VT); 1683 } 1684 1685 return SDValue(); 1686} 1687 1688SDValue DAGCombiner::visitSUBC(SDNode *N) { 1689 SDValue N0 = N->getOperand(0); 1690 SDValue N1 = N->getOperand(1); 1691 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1692 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1693 EVT VT = N0.getValueType(); 1694 1695 // If the flag result is dead, turn this into an SUB. 1696 if (!N->hasAnyUseOfValue(1)) 1697 return CombineTo(N, DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, N1), 1698 DAG.getNode(ISD::CARRY_FALSE, N->getDebugLoc(), 1699 MVT::Glue)); 1700 1701 // fold (subc x, x) -> 0 + no borrow 1702 if (N0 == N1) 1703 return CombineTo(N, DAG.getConstant(0, VT), 1704 DAG.getNode(ISD::CARRY_FALSE, N->getDebugLoc(), 1705 MVT::Glue)); 1706 1707 // fold (subc x, 0) -> x + no borrow 1708 if (N1C && N1C->isNullValue()) 1709 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, N->getDebugLoc(), 1710 MVT::Glue)); 1711 1712 // Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1) + no borrow 1713 if (N0C && N0C->isAllOnesValue()) 1714 return CombineTo(N, DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0), 1715 DAG.getNode(ISD::CARRY_FALSE, N->getDebugLoc(), 1716 MVT::Glue)); 1717 1718 return SDValue(); 1719} 1720 1721SDValue DAGCombiner::visitSUBE(SDNode *N) { 1722 SDValue N0 = N->getOperand(0); 1723 SDValue N1 = N->getOperand(1); 1724 SDValue CarryIn = N->getOperand(2); 1725 1726 // fold (sube x, y, false) -> (subc x, y) 1727 if (CarryIn.getOpcode() == ISD::CARRY_FALSE) 1728 return DAG.getNode(ISD::SUBC, N->getDebugLoc(), N->getVTList(), N0, N1); 1729 1730 return SDValue(); 1731} 1732 1733SDValue DAGCombiner::visitMUL(SDNode *N) { 1734 SDValue N0 = N->getOperand(0); 1735 SDValue N1 = N->getOperand(1); 1736 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1737 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1738 EVT VT = N0.getValueType(); 1739 1740 // fold vector ops 1741 if (VT.isVector()) { 1742 SDValue FoldedVOp = SimplifyVBinOp(N); 1743 if (FoldedVOp.getNode()) return FoldedVOp; 1744 } 1745 1746 // fold (mul x, undef) -> 0 1747 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1748 return DAG.getConstant(0, VT); 1749 // fold (mul c1, c2) -> c1*c2 1750 if (N0C && N1C) 1751 return DAG.FoldConstantArithmetic(ISD::MUL, VT, N0C, N1C); 1752 // canonicalize constant to RHS 1753 if (N0C && !N1C) 1754 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, N1, N0); 1755 // fold (mul x, 0) -> 0 1756 if (N1C && N1C->isNullValue()) 1757 return N1; 1758 // fold (mul x, -1) -> 0-x 1759 if (N1C && N1C->isAllOnesValue()) 1760 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1761 DAG.getConstant(0, VT), N0); 1762 // fold (mul x, (1 << c)) -> x << c 1763 if (N1C && N1C->getAPIntValue().isPowerOf2()) 1764 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 1765 DAG.getConstant(N1C->getAPIntValue().logBase2(), 1766 getShiftAmountTy(N0.getValueType()))); 1767 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c 1768 if (N1C && (-N1C->getAPIntValue()).isPowerOf2()) { 1769 unsigned Log2Val = (-N1C->getAPIntValue()).logBase2(); 1770 // FIXME: If the input is something that is easily negated (e.g. a 1771 // single-use add), we should put the negate there. 1772 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1773 DAG.getConstant(0, VT), 1774 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 1775 DAG.getConstant(Log2Val, 1776 getShiftAmountTy(N0.getValueType())))); 1777 } 1778 // (mul (shl X, c1), c2) -> (mul X, c2 << c1) 1779 if (N1C && N0.getOpcode() == ISD::SHL && 1780 isa<ConstantSDNode>(N0.getOperand(1))) { 1781 SDValue C3 = DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1782 N1, N0.getOperand(1)); 1783 AddToWorkList(C3.getNode()); 1784 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1785 N0.getOperand(0), C3); 1786 } 1787 1788 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one 1789 // use. 1790 { 1791 SDValue Sh(0,0), Y(0,0); 1792 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)). 1793 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) && 1794 N0.getNode()->hasOneUse()) { 1795 Sh = N0; Y = N1; 1796 } else if (N1.getOpcode() == ISD::SHL && 1797 isa<ConstantSDNode>(N1.getOperand(1)) && 1798 N1.getNode()->hasOneUse()) { 1799 Sh = N1; Y = N0; 1800 } 1801 1802 if (Sh.getNode()) { 1803 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1804 Sh.getOperand(0), Y); 1805 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1806 Mul, Sh.getOperand(1)); 1807 } 1808 } 1809 1810 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2) 1811 if (N1C && N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse() && 1812 isa<ConstantSDNode>(N0.getOperand(1))) 1813 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, 1814 DAG.getNode(ISD::MUL, N0.getDebugLoc(), VT, 1815 N0.getOperand(0), N1), 1816 DAG.getNode(ISD::MUL, N1.getDebugLoc(), VT, 1817 N0.getOperand(1), N1)); 1818 1819 // reassociate mul 1820 SDValue RMUL = ReassociateOps(ISD::MUL, N->getDebugLoc(), N0, N1); 1821 if (RMUL.getNode() != 0) 1822 return RMUL; 1823 1824 return SDValue(); 1825} 1826 1827SDValue DAGCombiner::visitSDIV(SDNode *N) { 1828 SDValue N0 = N->getOperand(0); 1829 SDValue N1 = N->getOperand(1); 1830 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1831 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1832 EVT VT = N->getValueType(0); 1833 1834 // fold vector ops 1835 if (VT.isVector()) { 1836 SDValue FoldedVOp = SimplifyVBinOp(N); 1837 if (FoldedVOp.getNode()) return FoldedVOp; 1838 } 1839 1840 // fold (sdiv c1, c2) -> c1/c2 1841 if (N0C && N1C && !N1C->isNullValue()) 1842 return DAG.FoldConstantArithmetic(ISD::SDIV, VT, N0C, N1C); 1843 // fold (sdiv X, 1) -> X 1844 if (N1C && N1C->getAPIntValue() == 1LL) 1845 return N0; 1846 // fold (sdiv X, -1) -> 0-X 1847 if (N1C && N1C->isAllOnesValue()) 1848 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1849 DAG.getConstant(0, VT), N0); 1850 // If we know the sign bits of both operands are zero, strength reduce to a 1851 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2 1852 if (!VT.isVector()) { 1853 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 1854 return DAG.getNode(ISD::UDIV, N->getDebugLoc(), N1.getValueType(), 1855 N0, N1); 1856 } 1857 // fold (sdiv X, pow2) -> simple ops after legalize 1858 if (N1C && !N1C->isNullValue() && 1859 (N1C->getAPIntValue().isPowerOf2() || 1860 (-N1C->getAPIntValue()).isPowerOf2())) { 1861 // If dividing by powers of two is cheap, then don't perform the following 1862 // fold. 1863 if (TLI.isPow2DivCheap()) 1864 return SDValue(); 1865 1866 unsigned lg2 = N1C->getAPIntValue().countTrailingZeros(); 1867 1868 // Splat the sign bit into the register 1869 SDValue SGN = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0, 1870 DAG.getConstant(VT.getSizeInBits()-1, 1871 getShiftAmountTy(N0.getValueType()))); 1872 AddToWorkList(SGN.getNode()); 1873 1874 // Add (N0 < 0) ? abs2 - 1 : 0; 1875 SDValue SRL = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, SGN, 1876 DAG.getConstant(VT.getSizeInBits() - lg2, 1877 getShiftAmountTy(SGN.getValueType()))); 1878 SDValue ADD = DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, SRL); 1879 AddToWorkList(SRL.getNode()); 1880 AddToWorkList(ADD.getNode()); // Divide by pow2 1881 SDValue SRA = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, ADD, 1882 DAG.getConstant(lg2, getShiftAmountTy(ADD.getValueType()))); 1883 1884 // If we're dividing by a positive value, we're done. Otherwise, we must 1885 // negate the result. 1886 if (N1C->getAPIntValue().isNonNegative()) 1887 return SRA; 1888 1889 AddToWorkList(SRA.getNode()); 1890 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1891 DAG.getConstant(0, VT), SRA); 1892 } 1893 1894 // if integer divide is expensive and we satisfy the requirements, emit an 1895 // alternate sequence. 1896 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) { 1897 SDValue Op = BuildSDIV(N); 1898 if (Op.getNode()) return Op; 1899 } 1900 1901 // undef / X -> 0 1902 if (N0.getOpcode() == ISD::UNDEF) 1903 return DAG.getConstant(0, VT); 1904 // X / undef -> undef 1905 if (N1.getOpcode() == ISD::UNDEF) 1906 return N1; 1907 1908 return SDValue(); 1909} 1910 1911SDValue DAGCombiner::visitUDIV(SDNode *N) { 1912 SDValue N0 = N->getOperand(0); 1913 SDValue N1 = N->getOperand(1); 1914 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1915 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1916 EVT VT = N->getValueType(0); 1917 1918 // fold vector ops 1919 if (VT.isVector()) { 1920 SDValue FoldedVOp = SimplifyVBinOp(N); 1921 if (FoldedVOp.getNode()) return FoldedVOp; 1922 } 1923 1924 // fold (udiv c1, c2) -> c1/c2 1925 if (N0C && N1C && !N1C->isNullValue()) 1926 return DAG.FoldConstantArithmetic(ISD::UDIV, VT, N0C, N1C); 1927 // fold (udiv x, (1 << c)) -> x >>u c 1928 if (N1C && N1C->getAPIntValue().isPowerOf2()) 1929 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, 1930 DAG.getConstant(N1C->getAPIntValue().logBase2(), 1931 getShiftAmountTy(N0.getValueType()))); 1932 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2 1933 if (N1.getOpcode() == ISD::SHL) { 1934 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1935 if (SHC->getAPIntValue().isPowerOf2()) { 1936 EVT ADDVT = N1.getOperand(1).getValueType(); 1937 SDValue Add = DAG.getNode(ISD::ADD, N->getDebugLoc(), ADDVT, 1938 N1.getOperand(1), 1939 DAG.getConstant(SHC->getAPIntValue() 1940 .logBase2(), 1941 ADDVT)); 1942 AddToWorkList(Add.getNode()); 1943 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, Add); 1944 } 1945 } 1946 } 1947 // fold (udiv x, c) -> alternate 1948 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) { 1949 SDValue Op = BuildUDIV(N); 1950 if (Op.getNode()) return Op; 1951 } 1952 1953 // undef / X -> 0 1954 if (N0.getOpcode() == ISD::UNDEF) 1955 return DAG.getConstant(0, VT); 1956 // X / undef -> undef 1957 if (N1.getOpcode() == ISD::UNDEF) 1958 return N1; 1959 1960 return SDValue(); 1961} 1962 1963SDValue DAGCombiner::visitSREM(SDNode *N) { 1964 SDValue N0 = N->getOperand(0); 1965 SDValue N1 = N->getOperand(1); 1966 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1967 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1968 EVT VT = N->getValueType(0); 1969 1970 // fold (srem c1, c2) -> c1%c2 1971 if (N0C && N1C && !N1C->isNullValue()) 1972 return DAG.FoldConstantArithmetic(ISD::SREM, VT, N0C, N1C); 1973 // If we know the sign bits of both operands are zero, strength reduce to a 1974 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15 1975 if (!VT.isVector()) { 1976 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 1977 return DAG.getNode(ISD::UREM, N->getDebugLoc(), VT, N0, N1); 1978 } 1979 1980 // If X/C can be simplified by the division-by-constant logic, lower 1981 // X%C to the equivalent of X-X/C*C. 1982 if (N1C && !N1C->isNullValue()) { 1983 SDValue Div = DAG.getNode(ISD::SDIV, N->getDebugLoc(), VT, N0, N1); 1984 AddToWorkList(Div.getNode()); 1985 SDValue OptimizedDiv = combine(Div.getNode()); 1986 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) { 1987 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1988 OptimizedDiv, N1); 1989 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul); 1990 AddToWorkList(Mul.getNode()); 1991 return Sub; 1992 } 1993 } 1994 1995 // undef % X -> 0 1996 if (N0.getOpcode() == ISD::UNDEF) 1997 return DAG.getConstant(0, VT); 1998 // X % undef -> undef 1999 if (N1.getOpcode() == ISD::UNDEF) 2000 return N1; 2001 2002 return SDValue(); 2003} 2004 2005SDValue DAGCombiner::visitUREM(SDNode *N) { 2006 SDValue N0 = N->getOperand(0); 2007 SDValue N1 = N->getOperand(1); 2008 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2009 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2010 EVT VT = N->getValueType(0); 2011 2012 // fold (urem c1, c2) -> c1%c2 2013 if (N0C && N1C && !N1C->isNullValue()) 2014 return DAG.FoldConstantArithmetic(ISD::UREM, VT, N0C, N1C); 2015 // fold (urem x, pow2) -> (and x, pow2-1) 2016 if (N1C && !N1C->isNullValue() && N1C->getAPIntValue().isPowerOf2()) 2017 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, 2018 DAG.getConstant(N1C->getAPIntValue()-1,VT)); 2019 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1)) 2020 if (N1.getOpcode() == ISD::SHL) { 2021 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 2022 if (SHC->getAPIntValue().isPowerOf2()) { 2023 SDValue Add = 2024 DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, 2025 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), 2026 VT)); 2027 AddToWorkList(Add.getNode()); 2028 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, Add); 2029 } 2030 } 2031 } 2032 2033 // If X/C can be simplified by the division-by-constant logic, lower 2034 // X%C to the equivalent of X-X/C*C. 2035 if (N1C && !N1C->isNullValue()) { 2036 SDValue Div = DAG.getNode(ISD::UDIV, N->getDebugLoc(), VT, N0, N1); 2037 AddToWorkList(Div.getNode()); 2038 SDValue OptimizedDiv = combine(Div.getNode()); 2039 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) { 2040 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 2041 OptimizedDiv, N1); 2042 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul); 2043 AddToWorkList(Mul.getNode()); 2044 return Sub; 2045 } 2046 } 2047 2048 // undef % X -> 0 2049 if (N0.getOpcode() == ISD::UNDEF) 2050 return DAG.getConstant(0, VT); 2051 // X % undef -> undef 2052 if (N1.getOpcode() == ISD::UNDEF) 2053 return N1; 2054 2055 return SDValue(); 2056} 2057 2058SDValue DAGCombiner::visitMULHS(SDNode *N) { 2059 SDValue N0 = N->getOperand(0); 2060 SDValue N1 = N->getOperand(1); 2061 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2062 EVT VT = N->getValueType(0); 2063 DebugLoc DL = N->getDebugLoc(); 2064 2065 // fold (mulhs x, 0) -> 0 2066 if (N1C && N1C->isNullValue()) 2067 return N1; 2068 // fold (mulhs x, 1) -> (sra x, size(x)-1) 2069 if (N1C && N1C->getAPIntValue() == 1) 2070 return DAG.getNode(ISD::SRA, N->getDebugLoc(), N0.getValueType(), N0, 2071 DAG.getConstant(N0.getValueType().getSizeInBits() - 1, 2072 getShiftAmountTy(N0.getValueType()))); 2073 // fold (mulhs x, undef) -> 0 2074 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 2075 return DAG.getConstant(0, VT); 2076 2077 // If the type twice as wide is legal, transform the mulhs to a wider multiply 2078 // plus a shift. 2079 if (VT.isSimple() && !VT.isVector()) { 2080 MVT Simple = VT.getSimpleVT(); 2081 unsigned SimpleSize = Simple.getSizeInBits(); 2082 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2); 2083 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { 2084 N0 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N0); 2085 N1 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N1); 2086 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1); 2087 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1, 2088 DAG.getConstant(SimpleSize, getShiftAmountTy(N1.getValueType()))); 2089 return DAG.getNode(ISD::TRUNCATE, DL, VT, N1); 2090 } 2091 } 2092 2093 return SDValue(); 2094} 2095 2096SDValue DAGCombiner::visitMULHU(SDNode *N) { 2097 SDValue N0 = N->getOperand(0); 2098 SDValue N1 = N->getOperand(1); 2099 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2100 EVT VT = N->getValueType(0); 2101 DebugLoc DL = N->getDebugLoc(); 2102 2103 // fold (mulhu x, 0) -> 0 2104 if (N1C && N1C->isNullValue()) 2105 return N1; 2106 // fold (mulhu x, 1) -> 0 2107 if (N1C && N1C->getAPIntValue() == 1) 2108 return DAG.getConstant(0, N0.getValueType()); 2109 // fold (mulhu x, undef) -> 0 2110 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 2111 return DAG.getConstant(0, VT); 2112 2113 // If the type twice as wide is legal, transform the mulhu to a wider multiply 2114 // plus a shift. 2115 if (VT.isSimple() && !VT.isVector()) { 2116 MVT Simple = VT.getSimpleVT(); 2117 unsigned SimpleSize = Simple.getSizeInBits(); 2118 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2); 2119 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { 2120 N0 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N0); 2121 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N1); 2122 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1); 2123 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1, 2124 DAG.getConstant(SimpleSize, getShiftAmountTy(N1.getValueType()))); 2125 return DAG.getNode(ISD::TRUNCATE, DL, VT, N1); 2126 } 2127 } 2128 2129 return SDValue(); 2130} 2131 2132/// SimplifyNodeWithTwoResults - Perform optimizations common to nodes that 2133/// compute two values. LoOp and HiOp give the opcodes for the two computations 2134/// that are being performed. Return true if a simplification was made. 2135/// 2136SDValue DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 2137 unsigned HiOp) { 2138 // If the high half is not needed, just compute the low half. 2139 bool HiExists = N->hasAnyUseOfValue(1); 2140 if (!HiExists && 2141 (!LegalOperations || 2142 TLI.isOperationLegal(LoOp, N->getValueType(0)))) { 2143 SDValue Res = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0), 2144 N->op_begin(), N->getNumOperands()); 2145 return CombineTo(N, Res, Res); 2146 } 2147 2148 // If the low half is not needed, just compute the high half. 2149 bool LoExists = N->hasAnyUseOfValue(0); 2150 if (!LoExists && 2151 (!LegalOperations || 2152 TLI.isOperationLegal(HiOp, N->getValueType(1)))) { 2153 SDValue Res = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1), 2154 N->op_begin(), N->getNumOperands()); 2155 return CombineTo(N, Res, Res); 2156 } 2157 2158 // If both halves are used, return as it is. 2159 if (LoExists && HiExists) 2160 return SDValue(); 2161 2162 // If the two computed results can be simplified separately, separate them. 2163 if (LoExists) { 2164 SDValue Lo = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0), 2165 N->op_begin(), N->getNumOperands()); 2166 AddToWorkList(Lo.getNode()); 2167 SDValue LoOpt = combine(Lo.getNode()); 2168 if (LoOpt.getNode() && LoOpt.getNode() != Lo.getNode() && 2169 (!LegalOperations || 2170 TLI.isOperationLegal(LoOpt.getOpcode(), LoOpt.getValueType()))) 2171 return CombineTo(N, LoOpt, LoOpt); 2172 } 2173 2174 if (HiExists) { 2175 SDValue Hi = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1), 2176 N->op_begin(), N->getNumOperands()); 2177 AddToWorkList(Hi.getNode()); 2178 SDValue HiOpt = combine(Hi.getNode()); 2179 if (HiOpt.getNode() && HiOpt != Hi && 2180 (!LegalOperations || 2181 TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType()))) 2182 return CombineTo(N, HiOpt, HiOpt); 2183 } 2184 2185 return SDValue(); 2186} 2187 2188SDValue DAGCombiner::visitSMUL_LOHI(SDNode *N) { 2189 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS); 2190 if (Res.getNode()) return Res; 2191 2192 EVT VT = N->getValueType(0); 2193 DebugLoc DL = N->getDebugLoc(); 2194 2195 // If the type twice as wide is legal, transform the mulhu to a wider multiply 2196 // plus a shift. 2197 if (VT.isSimple() && !VT.isVector()) { 2198 MVT Simple = VT.getSimpleVT(); 2199 unsigned SimpleSize = Simple.getSizeInBits(); 2200 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2); 2201 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { 2202 SDValue Lo = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(0)); 2203 SDValue Hi = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(1)); 2204 Lo = DAG.getNode(ISD::MUL, DL, NewVT, Lo, Hi); 2205 // Compute the high part as N1. 2206 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo, 2207 DAG.getConstant(SimpleSize, getShiftAmountTy(Lo.getValueType()))); 2208 Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi); 2209 // Compute the low part as N0. 2210 Lo = DAG.getNode(ISD::TRUNCATE, DL, VT, Lo); 2211 return CombineTo(N, Lo, Hi); 2212 } 2213 } 2214 2215 return SDValue(); 2216} 2217 2218SDValue DAGCombiner::visitUMUL_LOHI(SDNode *N) { 2219 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU); 2220 if (Res.getNode()) return Res; 2221 2222 EVT VT = N->getValueType(0); 2223 DebugLoc DL = N->getDebugLoc(); 2224 2225 // If the type twice as wide is legal, transform the mulhu to a wider multiply 2226 // plus a shift. 2227 if (VT.isSimple() && !VT.isVector()) { 2228 MVT Simple = VT.getSimpleVT(); 2229 unsigned SimpleSize = Simple.getSizeInBits(); 2230 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2); 2231 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { 2232 SDValue Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(0)); 2233 SDValue Hi = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(1)); 2234 Lo = DAG.getNode(ISD::MUL, DL, NewVT, Lo, Hi); 2235 // Compute the high part as N1. 2236 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo, 2237 DAG.getConstant(SimpleSize, getShiftAmountTy(Lo.getValueType()))); 2238 Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi); 2239 // Compute the low part as N0. 2240 Lo = DAG.getNode(ISD::TRUNCATE, DL, VT, Lo); 2241 return CombineTo(N, Lo, Hi); 2242 } 2243 } 2244 2245 return SDValue(); 2246} 2247 2248SDValue DAGCombiner::visitSMULO(SDNode *N) { 2249 // (smulo x, 2) -> (saddo x, x) 2250 if (ConstantSDNode *C2 = dyn_cast<ConstantSDNode>(N->getOperand(1))) 2251 if (C2->getAPIntValue() == 2) 2252 return DAG.getNode(ISD::SADDO, N->getDebugLoc(), N->getVTList(), 2253 N->getOperand(0), N->getOperand(0)); 2254 2255 return SDValue(); 2256} 2257 2258SDValue DAGCombiner::visitUMULO(SDNode *N) { 2259 // (umulo x, 2) -> (uaddo x, x) 2260 if (ConstantSDNode *C2 = dyn_cast<ConstantSDNode>(N->getOperand(1))) 2261 if (C2->getAPIntValue() == 2) 2262 return DAG.getNode(ISD::UADDO, N->getDebugLoc(), N->getVTList(), 2263 N->getOperand(0), N->getOperand(0)); 2264 2265 return SDValue(); 2266} 2267 2268SDValue DAGCombiner::visitSDIVREM(SDNode *N) { 2269 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM); 2270 if (Res.getNode()) return Res; 2271 2272 return SDValue(); 2273} 2274 2275SDValue DAGCombiner::visitUDIVREM(SDNode *N) { 2276 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM); 2277 if (Res.getNode()) return Res; 2278 2279 return SDValue(); 2280} 2281 2282/// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with 2283/// two operands of the same opcode, try to simplify it. 2284SDValue DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) { 2285 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1); 2286 EVT VT = N0.getValueType(); 2287 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!"); 2288 2289 // Bail early if none of these transforms apply. 2290 if (N0.getNode()->getNumOperands() == 0) return SDValue(); 2291 2292 // For each of OP in AND/OR/XOR: 2293 // fold (OP (zext x), (zext y)) -> (zext (OP x, y)) 2294 // fold (OP (sext x), (sext y)) -> (sext (OP x, y)) 2295 // fold (OP (aext x), (aext y)) -> (aext (OP x, y)) 2296 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y)) (if trunc isn't free) 2297 // 2298 // do not sink logical op inside of a vector extend, since it may combine 2299 // into a vsetcc. 2300 EVT Op0VT = N0.getOperand(0).getValueType(); 2301 if ((N0.getOpcode() == ISD::ZERO_EXTEND || 2302 N0.getOpcode() == ISD::SIGN_EXTEND || 2303 // Avoid infinite looping with PromoteIntBinOp. 2304 (N0.getOpcode() == ISD::ANY_EXTEND && 2305 (!LegalTypes || TLI.isTypeDesirableForOp(N->getOpcode(), Op0VT))) || 2306 (N0.getOpcode() == ISD::TRUNCATE && 2307 (!TLI.isZExtFree(VT, Op0VT) || 2308 !TLI.isTruncateFree(Op0VT, VT)) && 2309 TLI.isTypeLegal(Op0VT))) && 2310 !VT.isVector() && 2311 Op0VT == N1.getOperand(0).getValueType() && 2312 (!LegalOperations || TLI.isOperationLegal(N->getOpcode(), Op0VT))) { 2313 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(), 2314 N0.getOperand(0).getValueType(), 2315 N0.getOperand(0), N1.getOperand(0)); 2316 AddToWorkList(ORNode.getNode()); 2317 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, ORNode); 2318 } 2319 2320 // For each of OP in SHL/SRL/SRA/AND... 2321 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z) 2322 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z) 2323 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z) 2324 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL || 2325 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) && 2326 N0.getOperand(1) == N1.getOperand(1)) { 2327 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(), 2328 N0.getOperand(0).getValueType(), 2329 N0.getOperand(0), N1.getOperand(0)); 2330 AddToWorkList(ORNode.getNode()); 2331 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, 2332 ORNode, N0.getOperand(1)); 2333 } 2334 2335 // Simplify xor/and/or (bitcast(A), bitcast(B)) -> bitcast(op (A,B)) 2336 // Only perform this optimization after type legalization and before 2337 // LegalizeVectorOprs. LegalizeVectorOprs promotes vector operations by 2338 // adding bitcasts. For example (xor v4i32) is promoted to (v2i64), and 2339 // we don't want to undo this promotion. 2340 // We also handle SCALAR_TO_VECTOR because xor/or/and operations are cheaper 2341 // on scalars. 2342 if ((N0.getOpcode() == ISD::BITCAST || N0.getOpcode() == ISD::SCALAR_TO_VECTOR) 2343 && Level == AfterLegalizeVectorOps) { 2344 SDValue In0 = N0.getOperand(0); 2345 SDValue In1 = N1.getOperand(0); 2346 EVT In0Ty = In0.getValueType(); 2347 EVT In1Ty = In1.getValueType(); 2348 // If both incoming values are integers, and the original types are the same. 2349 if (In0Ty.isInteger() && In1Ty.isInteger() && In0Ty == In1Ty) { 2350 SDValue Op = DAG.getNode(N->getOpcode(), N->getDebugLoc(), In0Ty, In0, In1); 2351 SDValue BC = DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, Op); 2352 AddToWorkList(Op.getNode()); 2353 return BC; 2354 } 2355 } 2356 2357 // Xor/and/or are indifferent to the swizzle operation (shuffle of one value). 2358 // Simplify xor/and/or (shuff(A), shuff(B)) -> shuff(op (A,B)) 2359 // If both shuffles use the same mask, and both shuffle within a single 2360 // vector, then it is worthwhile to move the swizzle after the operation. 2361 // The type-legalizer generates this pattern when loading illegal 2362 // vector types from memory. In many cases this allows additional shuffle 2363 // optimizations. 2364 if (N0.getOpcode() == ISD::VECTOR_SHUFFLE && Level < AfterLegalizeDAG) { 2365 ShuffleVectorSDNode *SVN0 = cast<ShuffleVectorSDNode>(N0); 2366 ShuffleVectorSDNode *SVN1 = cast<ShuffleVectorSDNode>(N1); 2367 SDValue In0 = SVN0->getOperand(0); 2368 SDValue In1 = SVN1->getOperand(0); 2369 EVT In0Ty = In0.getValueType(); 2370 EVT In1Ty = In1.getValueType(); 2371 2372 unsigned NumElts = VT.getVectorNumElements(); 2373 // Check that both shuffles are swizzles. 2374 bool SingleVecShuff = (N0.getOperand(1).getOpcode() == ISD::UNDEF && 2375 N1.getOperand(1).getOpcode() == ISD::UNDEF); 2376 2377 // Check that both shuffles use the same mask. The masks are known to be of 2378 // the same length because the result vector type is the same. 2379 bool SameMask = true; 2380 for (unsigned i = 0; i != NumElts; ++i) { 2381 int Idx0 = SVN0->getMaskElt(i); 2382 int Idx1 = SVN1->getMaskElt(i); 2383 if (Idx0 != Idx1) { 2384 SameMask = false; 2385 break; 2386 } 2387 } 2388 2389 if (SameMask && SingleVecShuff && In0Ty == In1Ty) { 2390 SDValue Op = DAG.getNode(N->getOpcode(), N->getDebugLoc(), VT, In0, In1); 2391 SDValue Shuff = DAG.getVectorShuffle(VT, N->getDebugLoc(), Op, 2392 DAG.getUNDEF(VT), &SVN0->getMask()[0]); 2393 AddToWorkList(Op.getNode()); 2394 return Shuff; 2395 } 2396 } 2397 return SDValue(); 2398} 2399 2400SDValue DAGCombiner::visitAND(SDNode *N) { 2401 SDValue N0 = N->getOperand(0); 2402 SDValue N1 = N->getOperand(1); 2403 SDValue LL, LR, RL, RR, CC0, CC1; 2404 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2405 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2406 EVT VT = N1.getValueType(); 2407 unsigned BitWidth = VT.getScalarType().getSizeInBits(); 2408 2409 // fold vector ops 2410 if (VT.isVector()) { 2411 SDValue FoldedVOp = SimplifyVBinOp(N); 2412 if (FoldedVOp.getNode()) return FoldedVOp; 2413 } 2414 2415 // fold (and x, undef) -> 0 2416 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 2417 return DAG.getConstant(0, VT); 2418 // fold (and c1, c2) -> c1&c2 2419 if (N0C && N1C) 2420 return DAG.FoldConstantArithmetic(ISD::AND, VT, N0C, N1C); 2421 // canonicalize constant to RHS 2422 if (N0C && !N1C) 2423 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N1, N0); 2424 // fold (and x, -1) -> x 2425 if (N1C && N1C->isAllOnesValue()) 2426 return N0; 2427 // if (and x, c) is known to be zero, return 0 2428 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0), 2429 APInt::getAllOnesValue(BitWidth))) 2430 return DAG.getConstant(0, VT); 2431 // reassociate and 2432 SDValue RAND = ReassociateOps(ISD::AND, N->getDebugLoc(), N0, N1); 2433 if (RAND.getNode() != 0) 2434 return RAND; 2435 // fold (and (or x, C), D) -> D if (C & D) == D 2436 if (N1C && N0.getOpcode() == ISD::OR) 2437 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 2438 if ((ORI->getAPIntValue() & N1C->getAPIntValue()) == N1C->getAPIntValue()) 2439 return N1; 2440 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits. 2441 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 2442 SDValue N0Op0 = N0.getOperand(0); 2443 APInt Mask = ~N1C->getAPIntValue(); 2444 Mask = Mask.trunc(N0Op0.getValueSizeInBits()); 2445 if (DAG.MaskedValueIsZero(N0Op0, Mask)) { 2446 SDValue Zext = DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), 2447 N0.getValueType(), N0Op0); 2448 2449 // Replace uses of the AND with uses of the Zero extend node. 2450 CombineTo(N, Zext); 2451 2452 // We actually want to replace all uses of the any_extend with the 2453 // zero_extend, to avoid duplicating things. This will later cause this 2454 // AND to be folded. 2455 CombineTo(N0.getNode(), Zext); 2456 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2457 } 2458 } 2459 // similarly fold (and (X (load ([non_ext|any_ext|zero_ext] V))), c) -> 2460 // (X (load ([non_ext|zero_ext] V))) if 'and' only clears top bits which must 2461 // already be zero by virtue of the width of the base type of the load. 2462 // 2463 // the 'X' node here can either be nothing or an extract_vector_elt to catch 2464 // more cases. 2465 if ((N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT && 2466 N0.getOperand(0).getOpcode() == ISD::LOAD) || 2467 N0.getOpcode() == ISD::LOAD) { 2468 LoadSDNode *Load = cast<LoadSDNode>( (N0.getOpcode() == ISD::LOAD) ? 2469 N0 : N0.getOperand(0) ); 2470 2471 // Get the constant (if applicable) the zero'th operand is being ANDed with. 2472 // This can be a pure constant or a vector splat, in which case we treat the 2473 // vector as a scalar and use the splat value. 2474 APInt Constant = APInt::getNullValue(1); 2475 if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(N1)) { 2476 Constant = C->getAPIntValue(); 2477 } else if (BuildVectorSDNode *Vector = dyn_cast<BuildVectorSDNode>(N1)) { 2478 APInt SplatValue, SplatUndef; 2479 unsigned SplatBitSize; 2480 bool HasAnyUndefs; 2481 bool IsSplat = Vector->isConstantSplat(SplatValue, SplatUndef, 2482 SplatBitSize, HasAnyUndefs); 2483 if (IsSplat) { 2484 // Undef bits can contribute to a possible optimisation if set, so 2485 // set them. 2486 SplatValue |= SplatUndef; 2487 2488 // The splat value may be something like "0x00FFFFFF", which means 0 for 2489 // the first vector value and FF for the rest, repeating. We need a mask 2490 // that will apply equally to all members of the vector, so AND all the 2491 // lanes of the constant together. 2492 EVT VT = Vector->getValueType(0); 2493 unsigned BitWidth = VT.getVectorElementType().getSizeInBits(); 2494 Constant = APInt::getAllOnesValue(BitWidth); 2495 for (unsigned i = 0, n = VT.getVectorNumElements(); i < n; ++i) 2496 Constant &= SplatValue.lshr(i*BitWidth).zextOrTrunc(BitWidth); 2497 } 2498 } 2499 2500 // If we want to change an EXTLOAD to a ZEXTLOAD, ensure a ZEXTLOAD is 2501 // actually legal and isn't going to get expanded, else this is a false 2502 // optimisation. 2503 bool CanZextLoadProfitably = TLI.isLoadExtLegal(ISD::ZEXTLOAD, 2504 Load->getMemoryVT()); 2505 2506 // Resize the constant to the same size as the original memory access before 2507 // extension. If it is still the AllOnesValue then this AND is completely 2508 // unneeded. 2509 Constant = 2510 Constant.zextOrTrunc(Load->getMemoryVT().getScalarType().getSizeInBits()); 2511 2512 bool B; 2513 switch (Load->getExtensionType()) { 2514 default: B = false; break; 2515 case ISD::EXTLOAD: B = CanZextLoadProfitably; break; 2516 case ISD::ZEXTLOAD: 2517 case ISD::NON_EXTLOAD: B = true; break; 2518 } 2519 2520 if (B && Constant.isAllOnesValue()) { 2521 // If the load type was an EXTLOAD, convert to ZEXTLOAD in order to 2522 // preserve semantics once we get rid of the AND. 2523 SDValue NewLoad(Load, 0); 2524 if (Load->getExtensionType() == ISD::EXTLOAD) { 2525 NewLoad = DAG.getLoad(Load->getAddressingMode(), ISD::ZEXTLOAD, 2526 Load->getValueType(0), Load->getDebugLoc(), 2527 Load->getChain(), Load->getBasePtr(), 2528 Load->getOffset(), Load->getMemoryVT(), 2529 Load->getMemOperand()); 2530 // Replace uses of the EXTLOAD with the new ZEXTLOAD. 2531 CombineTo(Load, NewLoad.getValue(0), NewLoad.getValue(1)); 2532 } 2533 2534 // Fold the AND away, taking care not to fold to the old load node if we 2535 // replaced it. 2536 CombineTo(N, (N0.getNode() == Load) ? NewLoad : N0); 2537 2538 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2539 } 2540 } 2541 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y)) 2542 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 2543 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 2544 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 2545 2546 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 2547 LL.getValueType().isInteger()) { 2548 // fold (and (seteq X, 0), (seteq Y, 0)) -> (seteq (or X, Y), 0) 2549 if (cast<ConstantSDNode>(LR)->isNullValue() && Op1 == ISD::SETEQ) { 2550 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(), 2551 LR.getValueType(), LL, RL); 2552 AddToWorkList(ORNode.getNode()); 2553 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 2554 } 2555 // fold (and (seteq X, -1), (seteq Y, -1)) -> (seteq (and X, Y), -1) 2556 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) { 2557 SDValue ANDNode = DAG.getNode(ISD::AND, N0.getDebugLoc(), 2558 LR.getValueType(), LL, RL); 2559 AddToWorkList(ANDNode.getNode()); 2560 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1); 2561 } 2562 // fold (and (setgt X, -1), (setgt Y, -1)) -> (setgt (or X, Y), -1) 2563 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) { 2564 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(), 2565 LR.getValueType(), LL, RL); 2566 AddToWorkList(ORNode.getNode()); 2567 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 2568 } 2569 } 2570 // canonicalize equivalent to ll == rl 2571 if (LL == RR && LR == RL) { 2572 Op1 = ISD::getSetCCSwappedOperands(Op1); 2573 std::swap(RL, RR); 2574 } 2575 if (LL == RL && LR == RR) { 2576 bool isInteger = LL.getValueType().isInteger(); 2577 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger); 2578 if (Result != ISD::SETCC_INVALID && 2579 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType()))) 2580 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(), 2581 LL, LR, Result); 2582 } 2583 } 2584 2585 // Simplify: (and (op x...), (op y...)) -> (op (and x, y)) 2586 if (N0.getOpcode() == N1.getOpcode()) { 2587 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 2588 if (Tmp.getNode()) return Tmp; 2589 } 2590 2591 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1) 2592 // fold (and (sra)) -> (and (srl)) when possible. 2593 if (!VT.isVector() && 2594 SimplifyDemandedBits(SDValue(N, 0))) 2595 return SDValue(N, 0); 2596 2597 // fold (zext_inreg (extload x)) -> (zextload x) 2598 if (ISD::isEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode())) { 2599 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2600 EVT MemVT = LN0->getMemoryVT(); 2601 // If we zero all the possible extended bits, then we can turn this into 2602 // a zextload if we are running before legalize or the operation is legal. 2603 unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits(); 2604 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 2605 BitWidth - MemVT.getScalarType().getSizeInBits())) && 2606 ((!LegalOperations && !LN0->isVolatile()) || 2607 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) { 2608 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT, 2609 LN0->getChain(), LN0->getBasePtr(), 2610 LN0->getPointerInfo(), MemVT, 2611 LN0->isVolatile(), LN0->isNonTemporal(), 2612 LN0->getAlignment()); 2613 AddToWorkList(N); 2614 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 2615 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2616 } 2617 } 2618 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use 2619 if (ISD::isSEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 2620 N0.hasOneUse()) { 2621 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2622 EVT MemVT = LN0->getMemoryVT(); 2623 // If we zero all the possible extended bits, then we can turn this into 2624 // a zextload if we are running before legalize or the operation is legal. 2625 unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits(); 2626 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 2627 BitWidth - MemVT.getScalarType().getSizeInBits())) && 2628 ((!LegalOperations && !LN0->isVolatile()) || 2629 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) { 2630 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT, 2631 LN0->getChain(), 2632 LN0->getBasePtr(), LN0->getPointerInfo(), 2633 MemVT, 2634 LN0->isVolatile(), LN0->isNonTemporal(), 2635 LN0->getAlignment()); 2636 AddToWorkList(N); 2637 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 2638 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2639 } 2640 } 2641 2642 // fold (and (load x), 255) -> (zextload x, i8) 2643 // fold (and (extload x, i16), 255) -> (zextload x, i8) 2644 // fold (and (any_ext (extload x, i16)), 255) -> (zextload x, i8) 2645 if (N1C && (N0.getOpcode() == ISD::LOAD || 2646 (N0.getOpcode() == ISD::ANY_EXTEND && 2647 N0.getOperand(0).getOpcode() == ISD::LOAD))) { 2648 bool HasAnyExt = N0.getOpcode() == ISD::ANY_EXTEND; 2649 LoadSDNode *LN0 = HasAnyExt 2650 ? cast<LoadSDNode>(N0.getOperand(0)) 2651 : cast<LoadSDNode>(N0); 2652 if (LN0->getExtensionType() != ISD::SEXTLOAD && 2653 LN0->isUnindexed() && N0.hasOneUse() && LN0->hasOneUse()) { 2654 uint32_t ActiveBits = N1C->getAPIntValue().getActiveBits(); 2655 if (ActiveBits > 0 && APIntOps::isMask(ActiveBits, N1C->getAPIntValue())){ 2656 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), ActiveBits); 2657 EVT LoadedVT = LN0->getMemoryVT(); 2658 2659 if (ExtVT == LoadedVT && 2660 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) { 2661 EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT; 2662 2663 SDValue NewLoad = 2664 DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), LoadResultTy, 2665 LN0->getChain(), LN0->getBasePtr(), 2666 LN0->getPointerInfo(), 2667 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(), 2668 LN0->getAlignment()); 2669 AddToWorkList(N); 2670 CombineTo(LN0, NewLoad, NewLoad.getValue(1)); 2671 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2672 } 2673 2674 // Do not change the width of a volatile load. 2675 // Do not generate loads of non-round integer types since these can 2676 // be expensive (and would be wrong if the type is not byte sized). 2677 if (!LN0->isVolatile() && LoadedVT.bitsGT(ExtVT) && ExtVT.isRound() && 2678 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) { 2679 EVT PtrType = LN0->getOperand(1).getValueType(); 2680 2681 unsigned Alignment = LN0->getAlignment(); 2682 SDValue NewPtr = LN0->getBasePtr(); 2683 2684 // For big endian targets, we need to add an offset to the pointer 2685 // to load the correct bytes. For little endian systems, we merely 2686 // need to read fewer bytes from the same pointer. 2687 if (TLI.isBigEndian()) { 2688 unsigned LVTStoreBytes = LoadedVT.getStoreSize(); 2689 unsigned EVTStoreBytes = ExtVT.getStoreSize(); 2690 unsigned PtrOff = LVTStoreBytes - EVTStoreBytes; 2691 NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(), PtrType, 2692 NewPtr, DAG.getConstant(PtrOff, PtrType)); 2693 Alignment = MinAlign(Alignment, PtrOff); 2694 } 2695 2696 AddToWorkList(NewPtr.getNode()); 2697 2698 EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT; 2699 SDValue Load = 2700 DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), LoadResultTy, 2701 LN0->getChain(), NewPtr, 2702 LN0->getPointerInfo(), 2703 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(), 2704 Alignment); 2705 AddToWorkList(N); 2706 CombineTo(LN0, Load, Load.getValue(1)); 2707 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2708 } 2709 } 2710 } 2711 } 2712 2713 return SDValue(); 2714} 2715 2716/// MatchBSwapHWord - Match (a >> 8) | (a << 8) as (bswap a) >> 16 2717/// 2718SDValue DAGCombiner::MatchBSwapHWordLow(SDNode *N, SDValue N0, SDValue N1, 2719 bool DemandHighBits) { 2720 if (!LegalOperations) 2721 return SDValue(); 2722 2723 EVT VT = N->getValueType(0); 2724 if (VT != MVT::i64 && VT != MVT::i32 && VT != MVT::i16) 2725 return SDValue(); 2726 if (!TLI.isOperationLegal(ISD::BSWAP, VT)) 2727 return SDValue(); 2728 2729 // Recognize (and (shl a, 8), 0xff), (and (srl a, 8), 0xff00) 2730 bool LookPassAnd0 = false; 2731 bool LookPassAnd1 = false; 2732 if (N0.getOpcode() == ISD::AND && N0.getOperand(0).getOpcode() == ISD::SRL) 2733 std::swap(N0, N1); 2734 if (N1.getOpcode() == ISD::AND && N1.getOperand(0).getOpcode() == ISD::SHL) 2735 std::swap(N0, N1); 2736 if (N0.getOpcode() == ISD::AND) { 2737 if (!N0.getNode()->hasOneUse()) 2738 return SDValue(); 2739 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2740 if (!N01C || N01C->getZExtValue() != 0xFF00) 2741 return SDValue(); 2742 N0 = N0.getOperand(0); 2743 LookPassAnd0 = true; 2744 } 2745 2746 if (N1.getOpcode() == ISD::AND) { 2747 if (!N1.getNode()->hasOneUse()) 2748 return SDValue(); 2749 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1)); 2750 if (!N11C || N11C->getZExtValue() != 0xFF) 2751 return SDValue(); 2752 N1 = N1.getOperand(0); 2753 LookPassAnd1 = true; 2754 } 2755 2756 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL) 2757 std::swap(N0, N1); 2758 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL) 2759 return SDValue(); 2760 if (!N0.getNode()->hasOneUse() || 2761 !N1.getNode()->hasOneUse()) 2762 return SDValue(); 2763 2764 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2765 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1)); 2766 if (!N01C || !N11C) 2767 return SDValue(); 2768 if (N01C->getZExtValue() != 8 || N11C->getZExtValue() != 8) 2769 return SDValue(); 2770 2771 // Look for (shl (and a, 0xff), 8), (srl (and a, 0xff00), 8) 2772 SDValue N00 = N0->getOperand(0); 2773 if (!LookPassAnd0 && N00.getOpcode() == ISD::AND) { 2774 if (!N00.getNode()->hasOneUse()) 2775 return SDValue(); 2776 ConstantSDNode *N001C = dyn_cast<ConstantSDNode>(N00.getOperand(1)); 2777 if (!N001C || N001C->getZExtValue() != 0xFF) 2778 return SDValue(); 2779 N00 = N00.getOperand(0); 2780 LookPassAnd0 = true; 2781 } 2782 2783 SDValue N10 = N1->getOperand(0); 2784 if (!LookPassAnd1 && N10.getOpcode() == ISD::AND) { 2785 if (!N10.getNode()->hasOneUse()) 2786 return SDValue(); 2787 ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N10.getOperand(1)); 2788 if (!N101C || N101C->getZExtValue() != 0xFF00) 2789 return SDValue(); 2790 N10 = N10.getOperand(0); 2791 LookPassAnd1 = true; 2792 } 2793 2794 if (N00 != N10) 2795 return SDValue(); 2796 2797 // Make sure everything beyond the low halfword is zero since the SRL 16 2798 // will clear the top bits. 2799 unsigned OpSizeInBits = VT.getSizeInBits(); 2800 if (DemandHighBits && OpSizeInBits > 16 && 2801 (!LookPassAnd0 || !LookPassAnd1) && 2802 !DAG.MaskedValueIsZero(N10, APInt::getHighBitsSet(OpSizeInBits, 16))) 2803 return SDValue(); 2804 2805 SDValue Res = DAG.getNode(ISD::BSWAP, N->getDebugLoc(), VT, N00); 2806 if (OpSizeInBits > 16) 2807 Res = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, Res, 2808 DAG.getConstant(OpSizeInBits-16, getShiftAmountTy(VT))); 2809 return Res; 2810} 2811 2812/// isBSwapHWordElement - Return true if the specified node is an element 2813/// that makes up a 32-bit packed halfword byteswap. i.e. 2814/// ((x&0xff)<<8)|((x&0xff00)>>8)|((x&0x00ff0000)<<8)|((x&0xff000000)>>8) 2815static bool isBSwapHWordElement(SDValue N, SmallVector<SDNode*,4> &Parts) { 2816 if (!N.getNode()->hasOneUse()) 2817 return false; 2818 2819 unsigned Opc = N.getOpcode(); 2820 if (Opc != ISD::AND && Opc != ISD::SHL && Opc != ISD::SRL) 2821 return false; 2822 2823 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N.getOperand(1)); 2824 if (!N1C) 2825 return false; 2826 2827 unsigned Num; 2828 switch (N1C->getZExtValue()) { 2829 default: 2830 return false; 2831 case 0xFF: Num = 0; break; 2832 case 0xFF00: Num = 1; break; 2833 case 0xFF0000: Num = 2; break; 2834 case 0xFF000000: Num = 3; break; 2835 } 2836 2837 // Look for (x & 0xff) << 8 as well as ((x << 8) & 0xff00). 2838 SDValue N0 = N.getOperand(0); 2839 if (Opc == ISD::AND) { 2840 if (Num == 0 || Num == 2) { 2841 // (x >> 8) & 0xff 2842 // (x >> 8) & 0xff0000 2843 if (N0.getOpcode() != ISD::SRL) 2844 return false; 2845 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2846 if (!C || C->getZExtValue() != 8) 2847 return false; 2848 } else { 2849 // (x << 8) & 0xff00 2850 // (x << 8) & 0xff000000 2851 if (N0.getOpcode() != ISD::SHL) 2852 return false; 2853 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2854 if (!C || C->getZExtValue() != 8) 2855 return false; 2856 } 2857 } else if (Opc == ISD::SHL) { 2858 // (x & 0xff) << 8 2859 // (x & 0xff0000) << 8 2860 if (Num != 0 && Num != 2) 2861 return false; 2862 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N.getOperand(1)); 2863 if (!C || C->getZExtValue() != 8) 2864 return false; 2865 } else { // Opc == ISD::SRL 2866 // (x & 0xff00) >> 8 2867 // (x & 0xff000000) >> 8 2868 if (Num != 1 && Num != 3) 2869 return false; 2870 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N.getOperand(1)); 2871 if (!C || C->getZExtValue() != 8) 2872 return false; 2873 } 2874 2875 if (Parts[Num]) 2876 return false; 2877 2878 Parts[Num] = N0.getOperand(0).getNode(); 2879 return true; 2880} 2881 2882/// MatchBSwapHWord - Match a 32-bit packed halfword bswap. That is 2883/// ((x&0xff)<<8)|((x&0xff00)>>8)|((x&0x00ff0000)<<8)|((x&0xff000000)>>8) 2884/// => (rotl (bswap x), 16) 2885SDValue DAGCombiner::MatchBSwapHWord(SDNode *N, SDValue N0, SDValue N1) { 2886 if (!LegalOperations) 2887 return SDValue(); 2888 2889 EVT VT = N->getValueType(0); 2890 if (VT != MVT::i32) 2891 return SDValue(); 2892 if (!TLI.isOperationLegal(ISD::BSWAP, VT)) 2893 return SDValue(); 2894 2895 SmallVector<SDNode*,4> Parts(4, (SDNode*)0); 2896 // Look for either 2897 // (or (or (and), (and)), (or (and), (and))) 2898 // (or (or (or (and), (and)), (and)), (and)) 2899 if (N0.getOpcode() != ISD::OR) 2900 return SDValue(); 2901 SDValue N00 = N0.getOperand(0); 2902 SDValue N01 = N0.getOperand(1); 2903 2904 if (N1.getOpcode() == ISD::OR) { 2905 // (or (or (and), (and)), (or (and), (and))) 2906 SDValue N000 = N00.getOperand(0); 2907 if (!isBSwapHWordElement(N000, Parts)) 2908 return SDValue(); 2909 2910 SDValue N001 = N00.getOperand(1); 2911 if (!isBSwapHWordElement(N001, Parts)) 2912 return SDValue(); 2913 SDValue N010 = N01.getOperand(0); 2914 if (!isBSwapHWordElement(N010, Parts)) 2915 return SDValue(); 2916 SDValue N011 = N01.getOperand(1); 2917 if (!isBSwapHWordElement(N011, Parts)) 2918 return SDValue(); 2919 } else { 2920 // (or (or (or (and), (and)), (and)), (and)) 2921 if (!isBSwapHWordElement(N1, Parts)) 2922 return SDValue(); 2923 if (!isBSwapHWordElement(N01, Parts)) 2924 return SDValue(); 2925 if (N00.getOpcode() != ISD::OR) 2926 return SDValue(); 2927 SDValue N000 = N00.getOperand(0); 2928 if (!isBSwapHWordElement(N000, Parts)) 2929 return SDValue(); 2930 SDValue N001 = N00.getOperand(1); 2931 if (!isBSwapHWordElement(N001, Parts)) 2932 return SDValue(); 2933 } 2934 2935 // Make sure the parts are all coming from the same node. 2936 if (Parts[0] != Parts[1] || Parts[0] != Parts[2] || Parts[0] != Parts[3]) 2937 return SDValue(); 2938 2939 SDValue BSwap = DAG.getNode(ISD::BSWAP, N->getDebugLoc(), VT, 2940 SDValue(Parts[0],0)); 2941 2942 // Result of the bswap should be rotated by 16. If it's not legal, than 2943 // do (x << 16) | (x >> 16). 2944 SDValue ShAmt = DAG.getConstant(16, getShiftAmountTy(VT)); 2945 if (TLI.isOperationLegalOrCustom(ISD::ROTL, VT)) 2946 return DAG.getNode(ISD::ROTL, N->getDebugLoc(), VT, BSwap, ShAmt); 2947 else if (TLI.isOperationLegalOrCustom(ISD::ROTR, VT)) 2948 return DAG.getNode(ISD::ROTR, N->getDebugLoc(), VT, BSwap, ShAmt); 2949 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, 2950 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, BSwap, ShAmt), 2951 DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, BSwap, ShAmt)); 2952} 2953 2954SDValue DAGCombiner::visitOR(SDNode *N) { 2955 SDValue N0 = N->getOperand(0); 2956 SDValue N1 = N->getOperand(1); 2957 SDValue LL, LR, RL, RR, CC0, CC1; 2958 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2959 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2960 EVT VT = N1.getValueType(); 2961 2962 // fold vector ops 2963 if (VT.isVector()) { 2964 SDValue FoldedVOp = SimplifyVBinOp(N); 2965 if (FoldedVOp.getNode()) return FoldedVOp; 2966 } 2967 2968 // fold (or x, undef) -> -1 2969 if (!LegalOperations && 2970 (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)) { 2971 EVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT; 2972 return DAG.getConstant(APInt::getAllOnesValue(EltVT.getSizeInBits()), VT); 2973 } 2974 // fold (or c1, c2) -> c1|c2 2975 if (N0C && N1C) 2976 return DAG.FoldConstantArithmetic(ISD::OR, VT, N0C, N1C); 2977 // canonicalize constant to RHS 2978 if (N0C && !N1C) 2979 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N1, N0); 2980 // fold (or x, 0) -> x 2981 if (N1C && N1C->isNullValue()) 2982 return N0; 2983 // fold (or x, -1) -> -1 2984 if (N1C && N1C->isAllOnesValue()) 2985 return N1; 2986 // fold (or x, c) -> c iff (x & ~c) == 0 2987 if (N1C && DAG.MaskedValueIsZero(N0, ~N1C->getAPIntValue())) 2988 return N1; 2989 2990 // Recognize halfword bswaps as (bswap + rotl 16) or (bswap + shl 16) 2991 SDValue BSwap = MatchBSwapHWord(N, N0, N1); 2992 if (BSwap.getNode() != 0) 2993 return BSwap; 2994 BSwap = MatchBSwapHWordLow(N, N0, N1); 2995 if (BSwap.getNode() != 0) 2996 return BSwap; 2997 2998 // reassociate or 2999 SDValue ROR = ReassociateOps(ISD::OR, N->getDebugLoc(), N0, N1); 3000 if (ROR.getNode() != 0) 3001 return ROR; 3002 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2) 3003 // iff (c1 & c2) == 0. 3004 if (N1C && N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() && 3005 isa<ConstantSDNode>(N0.getOperand(1))) { 3006 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1)); 3007 if ((C1->getAPIntValue() & N1C->getAPIntValue()) != 0) 3008 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 3009 DAG.getNode(ISD::OR, N0.getDebugLoc(), VT, 3010 N0.getOperand(0), N1), 3011 DAG.FoldConstantArithmetic(ISD::OR, VT, N1C, C1)); 3012 } 3013 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y)) 3014 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 3015 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 3016 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 3017 3018 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 3019 LL.getValueType().isInteger()) { 3020 // fold (or (setne X, 0), (setne Y, 0)) -> (setne (or X, Y), 0) 3021 // fold (or (setlt X, 0), (setlt Y, 0)) -> (setne (or X, Y), 0) 3022 if (cast<ConstantSDNode>(LR)->isNullValue() && 3023 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) { 3024 SDValue ORNode = DAG.getNode(ISD::OR, LR.getDebugLoc(), 3025 LR.getValueType(), LL, RL); 3026 AddToWorkList(ORNode.getNode()); 3027 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 3028 } 3029 // fold (or (setne X, -1), (setne Y, -1)) -> (setne (and X, Y), -1) 3030 // fold (or (setgt X, -1), (setgt Y -1)) -> (setgt (and X, Y), -1) 3031 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && 3032 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) { 3033 SDValue ANDNode = DAG.getNode(ISD::AND, LR.getDebugLoc(), 3034 LR.getValueType(), LL, RL); 3035 AddToWorkList(ANDNode.getNode()); 3036 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1); 3037 } 3038 } 3039 // canonicalize equivalent to ll == rl 3040 if (LL == RR && LR == RL) { 3041 Op1 = ISD::getSetCCSwappedOperands(Op1); 3042 std::swap(RL, RR); 3043 } 3044 if (LL == RL && LR == RR) { 3045 bool isInteger = LL.getValueType().isInteger(); 3046 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger); 3047 if (Result != ISD::SETCC_INVALID && 3048 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType()))) 3049 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(), 3050 LL, LR, Result); 3051 } 3052 } 3053 3054 // Simplify: (or (op x...), (op y...)) -> (op (or x, y)) 3055 if (N0.getOpcode() == N1.getOpcode()) { 3056 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 3057 if (Tmp.getNode()) return Tmp; 3058 } 3059 3060 // (or (and X, C1), (and Y, C2)) -> (and (or X, Y), C3) if possible. 3061 if (N0.getOpcode() == ISD::AND && 3062 N1.getOpcode() == ISD::AND && 3063 N0.getOperand(1).getOpcode() == ISD::Constant && 3064 N1.getOperand(1).getOpcode() == ISD::Constant && 3065 // Don't increase # computations. 3066 (N0.getNode()->hasOneUse() || N1.getNode()->hasOneUse())) { 3067 // We can only do this xform if we know that bits from X that are set in C2 3068 // but not in C1 are already zero. Likewise for Y. 3069 const APInt &LHSMask = 3070 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 3071 const APInt &RHSMask = 3072 cast<ConstantSDNode>(N1.getOperand(1))->getAPIntValue(); 3073 3074 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) && 3075 DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) { 3076 SDValue X = DAG.getNode(ISD::OR, N0.getDebugLoc(), VT, 3077 N0.getOperand(0), N1.getOperand(0)); 3078 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, X, 3079 DAG.getConstant(LHSMask | RHSMask, VT)); 3080 } 3081 } 3082 3083 // See if this is some rotate idiom. 3084 if (SDNode *Rot = MatchRotate(N0, N1, N->getDebugLoc())) 3085 return SDValue(Rot, 0); 3086 3087 // Simplify the operands using demanded-bits information. 3088 if (!VT.isVector() && 3089 SimplifyDemandedBits(SDValue(N, 0))) 3090 return SDValue(N, 0); 3091 3092 return SDValue(); 3093} 3094 3095/// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present. 3096static bool MatchRotateHalf(SDValue Op, SDValue &Shift, SDValue &Mask) { 3097 if (Op.getOpcode() == ISD::AND) { 3098 if (isa<ConstantSDNode>(Op.getOperand(1))) { 3099 Mask = Op.getOperand(1); 3100 Op = Op.getOperand(0); 3101 } else { 3102 return false; 3103 } 3104 } 3105 3106 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) { 3107 Shift = Op; 3108 return true; 3109 } 3110 3111 return false; 3112} 3113 3114// MatchRotate - Handle an 'or' of two operands. If this is one of the many 3115// idioms for rotate, and if the target supports rotation instructions, generate 3116// a rot[lr]. 3117SDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL) { 3118 // Must be a legal type. Expanded 'n promoted things won't work with rotates. 3119 EVT VT = LHS.getValueType(); 3120 if (!TLI.isTypeLegal(VT)) return 0; 3121 3122 // The target must have at least one rotate flavor. 3123 bool HasROTL = TLI.isOperationLegalOrCustom(ISD::ROTL, VT); 3124 bool HasROTR = TLI.isOperationLegalOrCustom(ISD::ROTR, VT); 3125 if (!HasROTL && !HasROTR) return 0; 3126 3127 // Match "(X shl/srl V1) & V2" where V2 may not be present. 3128 SDValue LHSShift; // The shift. 3129 SDValue LHSMask; // AND value if any. 3130 if (!MatchRotateHalf(LHS, LHSShift, LHSMask)) 3131 return 0; // Not part of a rotate. 3132 3133 SDValue RHSShift; // The shift. 3134 SDValue RHSMask; // AND value if any. 3135 if (!MatchRotateHalf(RHS, RHSShift, RHSMask)) 3136 return 0; // Not part of a rotate. 3137 3138 if (LHSShift.getOperand(0) != RHSShift.getOperand(0)) 3139 return 0; // Not shifting the same value. 3140 3141 if (LHSShift.getOpcode() == RHSShift.getOpcode()) 3142 return 0; // Shifts must disagree. 3143 3144 // Canonicalize shl to left side in a shl/srl pair. 3145 if (RHSShift.getOpcode() == ISD::SHL) { 3146 std::swap(LHS, RHS); 3147 std::swap(LHSShift, RHSShift); 3148 std::swap(LHSMask , RHSMask ); 3149 } 3150 3151 unsigned OpSizeInBits = VT.getSizeInBits(); 3152 SDValue LHSShiftArg = LHSShift.getOperand(0); 3153 SDValue LHSShiftAmt = LHSShift.getOperand(1); 3154 SDValue RHSShiftAmt = RHSShift.getOperand(1); 3155 3156 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1) 3157 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2) 3158 if (LHSShiftAmt.getOpcode() == ISD::Constant && 3159 RHSShiftAmt.getOpcode() == ISD::Constant) { 3160 uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getZExtValue(); 3161 uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getZExtValue(); 3162 if ((LShVal + RShVal) != OpSizeInBits) 3163 return 0; 3164 3165 SDValue Rot; 3166 if (HasROTL) 3167 Rot = DAG.getNode(ISD::ROTL, DL, VT, LHSShiftArg, LHSShiftAmt); 3168 else 3169 Rot = DAG.getNode(ISD::ROTR, DL, VT, LHSShiftArg, RHSShiftAmt); 3170 3171 // If there is an AND of either shifted operand, apply it to the result. 3172 if (LHSMask.getNode() || RHSMask.getNode()) { 3173 APInt Mask = APInt::getAllOnesValue(OpSizeInBits); 3174 3175 if (LHSMask.getNode()) { 3176 APInt RHSBits = APInt::getLowBitsSet(OpSizeInBits, LShVal); 3177 Mask &= cast<ConstantSDNode>(LHSMask)->getAPIntValue() | RHSBits; 3178 } 3179 if (RHSMask.getNode()) { 3180 APInt LHSBits = APInt::getHighBitsSet(OpSizeInBits, RShVal); 3181 Mask &= cast<ConstantSDNode>(RHSMask)->getAPIntValue() | LHSBits; 3182 } 3183 3184 Rot = DAG.getNode(ISD::AND, DL, VT, Rot, DAG.getConstant(Mask, VT)); 3185 } 3186 3187 return Rot.getNode(); 3188 } 3189 3190 // If there is a mask here, and we have a variable shift, we can't be sure 3191 // that we're masking out the right stuff. 3192 if (LHSMask.getNode() || RHSMask.getNode()) 3193 return 0; 3194 3195 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y) 3196 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y)) 3197 if (RHSShiftAmt.getOpcode() == ISD::SUB && 3198 LHSShiftAmt == RHSShiftAmt.getOperand(1)) { 3199 if (ConstantSDNode *SUBC = 3200 dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) { 3201 if (SUBC->getAPIntValue() == OpSizeInBits) { 3202 if (HasROTL) 3203 return DAG.getNode(ISD::ROTL, DL, VT, 3204 LHSShiftArg, LHSShiftAmt).getNode(); 3205 else 3206 return DAG.getNode(ISD::ROTR, DL, VT, 3207 LHSShiftArg, RHSShiftAmt).getNode(); 3208 } 3209 } 3210 } 3211 3212 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y) 3213 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y)) 3214 if (LHSShiftAmt.getOpcode() == ISD::SUB && 3215 RHSShiftAmt == LHSShiftAmt.getOperand(1)) { 3216 if (ConstantSDNode *SUBC = 3217 dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) { 3218 if (SUBC->getAPIntValue() == OpSizeInBits) { 3219 if (HasROTR) 3220 return DAG.getNode(ISD::ROTR, DL, VT, 3221 LHSShiftArg, RHSShiftAmt).getNode(); 3222 else 3223 return DAG.getNode(ISD::ROTL, DL, VT, 3224 LHSShiftArg, LHSShiftAmt).getNode(); 3225 } 3226 } 3227 } 3228 3229 // Look for sign/zext/any-extended or truncate cases: 3230 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 3231 || LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 3232 || LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND 3233 || LHSShiftAmt.getOpcode() == ISD::TRUNCATE) && 3234 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 3235 || RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 3236 || RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND 3237 || RHSShiftAmt.getOpcode() == ISD::TRUNCATE)) { 3238 SDValue LExtOp0 = LHSShiftAmt.getOperand(0); 3239 SDValue RExtOp0 = RHSShiftAmt.getOperand(0); 3240 if (RExtOp0.getOpcode() == ISD::SUB && 3241 RExtOp0.getOperand(1) == LExtOp0) { 3242 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 3243 // (rotl x, y) 3244 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 3245 // (rotr x, (sub 32, y)) 3246 if (ConstantSDNode *SUBC = 3247 dyn_cast<ConstantSDNode>(RExtOp0.getOperand(0))) { 3248 if (SUBC->getAPIntValue() == OpSizeInBits) { 3249 return DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT, 3250 LHSShiftArg, 3251 HasROTL ? LHSShiftAmt : RHSShiftAmt).getNode(); 3252 } 3253 } 3254 } else if (LExtOp0.getOpcode() == ISD::SUB && 3255 RExtOp0 == LExtOp0.getOperand(1)) { 3256 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) -> 3257 // (rotr x, y) 3258 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) -> 3259 // (rotl x, (sub 32, y)) 3260 if (ConstantSDNode *SUBC = 3261 dyn_cast<ConstantSDNode>(LExtOp0.getOperand(0))) { 3262 if (SUBC->getAPIntValue() == OpSizeInBits) { 3263 return DAG.getNode(HasROTR ? ISD::ROTR : ISD::ROTL, DL, VT, 3264 LHSShiftArg, 3265 HasROTR ? RHSShiftAmt : LHSShiftAmt).getNode(); 3266 } 3267 } 3268 } 3269 } 3270 3271 return 0; 3272} 3273 3274SDValue DAGCombiner::visitXOR(SDNode *N) { 3275 SDValue N0 = N->getOperand(0); 3276 SDValue N1 = N->getOperand(1); 3277 SDValue LHS, RHS, CC; 3278 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3279 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3280 EVT VT = N0.getValueType(); 3281 3282 // fold vector ops 3283 if (VT.isVector()) { 3284 SDValue FoldedVOp = SimplifyVBinOp(N); 3285 if (FoldedVOp.getNode()) return FoldedVOp; 3286 } 3287 3288 // fold (xor undef, undef) -> 0. This is a common idiom (misuse). 3289 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF) 3290 return DAG.getConstant(0, VT); 3291 // fold (xor x, undef) -> undef 3292 if (N0.getOpcode() == ISD::UNDEF) 3293 return N0; 3294 if (N1.getOpcode() == ISD::UNDEF) 3295 return N1; 3296 // fold (xor c1, c2) -> c1^c2 3297 if (N0C && N1C) 3298 return DAG.FoldConstantArithmetic(ISD::XOR, VT, N0C, N1C); 3299 // canonicalize constant to RHS 3300 if (N0C && !N1C) 3301 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0); 3302 // fold (xor x, 0) -> x 3303 if (N1C && N1C->isNullValue()) 3304 return N0; 3305 // reassociate xor 3306 SDValue RXOR = ReassociateOps(ISD::XOR, N->getDebugLoc(), N0, N1); 3307 if (RXOR.getNode() != 0) 3308 return RXOR; 3309 3310 // fold !(x cc y) -> (x !cc y) 3311 if (N1C && N1C->getAPIntValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) { 3312 bool isInt = LHS.getValueType().isInteger(); 3313 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(), 3314 isInt); 3315 3316 if (!LegalOperations || TLI.isCondCodeLegal(NotCC, LHS.getValueType())) { 3317 switch (N0.getOpcode()) { 3318 default: 3319 llvm_unreachable("Unhandled SetCC Equivalent!"); 3320 case ISD::SETCC: 3321 return DAG.getSetCC(N->getDebugLoc(), VT, LHS, RHS, NotCC); 3322 case ISD::SELECT_CC: 3323 return DAG.getSelectCC(N->getDebugLoc(), LHS, RHS, N0.getOperand(2), 3324 N0.getOperand(3), NotCC); 3325 } 3326 } 3327 } 3328 3329 // fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y))) 3330 if (N1C && N1C->getAPIntValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND && 3331 N0.getNode()->hasOneUse() && 3332 isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){ 3333 SDValue V = N0.getOperand(0); 3334 V = DAG.getNode(ISD::XOR, N0.getDebugLoc(), V.getValueType(), V, 3335 DAG.getConstant(1, V.getValueType())); 3336 AddToWorkList(V.getNode()); 3337 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, V); 3338 } 3339 3340 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are setcc 3341 if (N1C && N1C->getAPIntValue() == 1 && VT == MVT::i1 && 3342 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 3343 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1); 3344 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) { 3345 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 3346 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS 3347 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS 3348 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode()); 3349 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS); 3350 } 3351 } 3352 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are constants 3353 if (N1C && N1C->isAllOnesValue() && 3354 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 3355 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1); 3356 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) { 3357 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 3358 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS 3359 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS 3360 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode()); 3361 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS); 3362 } 3363 } 3364 // fold (xor (xor x, c1), c2) -> (xor x, (xor c1, c2)) 3365 if (N1C && N0.getOpcode() == ISD::XOR) { 3366 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0)); 3367 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 3368 if (N00C) 3369 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(1), 3370 DAG.getConstant(N1C->getAPIntValue() ^ 3371 N00C->getAPIntValue(), VT)); 3372 if (N01C) 3373 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(0), 3374 DAG.getConstant(N1C->getAPIntValue() ^ 3375 N01C->getAPIntValue(), VT)); 3376 } 3377 // fold (xor x, x) -> 0 3378 if (N0 == N1) 3379 return tryFoldToZero(N->getDebugLoc(), TLI, VT, DAG, LegalOperations); 3380 3381 // Simplify: xor (op x...), (op y...) -> (op (xor x, y)) 3382 if (N0.getOpcode() == N1.getOpcode()) { 3383 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 3384 if (Tmp.getNode()) return Tmp; 3385 } 3386 3387 // Simplify the expression using non-local knowledge. 3388 if (!VT.isVector() && 3389 SimplifyDemandedBits(SDValue(N, 0))) 3390 return SDValue(N, 0); 3391 3392 return SDValue(); 3393} 3394 3395/// visitShiftByConstant - Handle transforms common to the three shifts, when 3396/// the shift amount is a constant. 3397SDValue DAGCombiner::visitShiftByConstant(SDNode *N, unsigned Amt) { 3398 SDNode *LHS = N->getOperand(0).getNode(); 3399 if (!LHS->hasOneUse()) return SDValue(); 3400 3401 // We want to pull some binops through shifts, so that we have (and (shift)) 3402 // instead of (shift (and)), likewise for add, or, xor, etc. This sort of 3403 // thing happens with address calculations, so it's important to canonicalize 3404 // it. 3405 bool HighBitSet = false; // Can we transform this if the high bit is set? 3406 3407 switch (LHS->getOpcode()) { 3408 default: return SDValue(); 3409 case ISD::OR: 3410 case ISD::XOR: 3411 HighBitSet = false; // We can only transform sra if the high bit is clear. 3412 break; 3413 case ISD::AND: 3414 HighBitSet = true; // We can only transform sra if the high bit is set. 3415 break; 3416 case ISD::ADD: 3417 if (N->getOpcode() != ISD::SHL) 3418 return SDValue(); // only shl(add) not sr[al](add). 3419 HighBitSet = false; // We can only transform sra if the high bit is clear. 3420 break; 3421 } 3422 3423 // We require the RHS of the binop to be a constant as well. 3424 ConstantSDNode *BinOpCst = dyn_cast<ConstantSDNode>(LHS->getOperand(1)); 3425 if (!BinOpCst) return SDValue(); 3426 3427 // FIXME: disable this unless the input to the binop is a shift by a constant. 3428 // If it is not a shift, it pessimizes some common cases like: 3429 // 3430 // void foo(int *X, int i) { X[i & 1235] = 1; } 3431 // int bar(int *X, int i) { return X[i & 255]; } 3432 SDNode *BinOpLHSVal = LHS->getOperand(0).getNode(); 3433 if ((BinOpLHSVal->getOpcode() != ISD::SHL && 3434 BinOpLHSVal->getOpcode() != ISD::SRA && 3435 BinOpLHSVal->getOpcode() != ISD::SRL) || 3436 !isa<ConstantSDNode>(BinOpLHSVal->getOperand(1))) 3437 return SDValue(); 3438 3439 EVT VT = N->getValueType(0); 3440 3441 // If this is a signed shift right, and the high bit is modified by the 3442 // logical operation, do not perform the transformation. The highBitSet 3443 // boolean indicates the value of the high bit of the constant which would 3444 // cause it to be modified for this operation. 3445 if (N->getOpcode() == ISD::SRA) { 3446 bool BinOpRHSSignSet = BinOpCst->getAPIntValue().isNegative(); 3447 if (BinOpRHSSignSet != HighBitSet) 3448 return SDValue(); 3449 } 3450 3451 // Fold the constants, shifting the binop RHS by the shift amount. 3452 SDValue NewRHS = DAG.getNode(N->getOpcode(), LHS->getOperand(1).getDebugLoc(), 3453 N->getValueType(0), 3454 LHS->getOperand(1), N->getOperand(1)); 3455 3456 // Create the new shift. 3457 SDValue NewShift = DAG.getNode(N->getOpcode(), 3458 LHS->getOperand(0).getDebugLoc(), 3459 VT, LHS->getOperand(0), N->getOperand(1)); 3460 3461 // Create the new binop. 3462 return DAG.getNode(LHS->getOpcode(), N->getDebugLoc(), VT, NewShift, NewRHS); 3463} 3464 3465SDValue DAGCombiner::visitSHL(SDNode *N) { 3466 SDValue N0 = N->getOperand(0); 3467 SDValue N1 = N->getOperand(1); 3468 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3469 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3470 EVT VT = N0.getValueType(); 3471 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits(); 3472 3473 // fold (shl c1, c2) -> c1<<c2 3474 if (N0C && N1C) 3475 return DAG.FoldConstantArithmetic(ISD::SHL, VT, N0C, N1C); 3476 // fold (shl 0, x) -> 0 3477 if (N0C && N0C->isNullValue()) 3478 return N0; 3479 // fold (shl x, c >= size(x)) -> undef 3480 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 3481 return DAG.getUNDEF(VT); 3482 // fold (shl x, 0) -> x 3483 if (N1C && N1C->isNullValue()) 3484 return N0; 3485 // fold (shl undef, x) -> 0 3486 if (N0.getOpcode() == ISD::UNDEF) 3487 return DAG.getConstant(0, VT); 3488 // if (shl x, c) is known to be zero, return 0 3489 if (DAG.MaskedValueIsZero(SDValue(N, 0), 3490 APInt::getAllOnesValue(OpSizeInBits))) 3491 return DAG.getConstant(0, VT); 3492 // fold (shl x, (trunc (and y, c))) -> (shl x, (and (trunc y), (trunc c))). 3493 if (N1.getOpcode() == ISD::TRUNCATE && 3494 N1.getOperand(0).getOpcode() == ISD::AND && 3495 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 3496 SDValue N101 = N1.getOperand(0).getOperand(1); 3497 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 3498 EVT TruncVT = N1.getValueType(); 3499 SDValue N100 = N1.getOperand(0).getOperand(0); 3500 APInt TruncC = N101C->getAPIntValue(); 3501 TruncC = TruncC.trunc(TruncVT.getSizeInBits()); 3502 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 3503 DAG.getNode(ISD::AND, N->getDebugLoc(), TruncVT, 3504 DAG.getNode(ISD::TRUNCATE, 3505 N->getDebugLoc(), 3506 TruncVT, N100), 3507 DAG.getConstant(TruncC, TruncVT))); 3508 } 3509 } 3510 3511 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 3512 return SDValue(N, 0); 3513 3514 // fold (shl (shl x, c1), c2) -> 0 or (shl x, (add c1, c2)) 3515 if (N1C && N0.getOpcode() == ISD::SHL && 3516 N0.getOperand(1).getOpcode() == ISD::Constant) { 3517 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 3518 uint64_t c2 = N1C->getZExtValue(); 3519 if (c1 + c2 >= OpSizeInBits) 3520 return DAG.getConstant(0, VT); 3521 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0.getOperand(0), 3522 DAG.getConstant(c1 + c2, N1.getValueType())); 3523 } 3524 3525 // fold (shl (ext (shl x, c1)), c2) -> (ext (shl x, (add c1, c2))) 3526 // For this to be valid, the second form must not preserve any of the bits 3527 // that are shifted out by the inner shift in the first form. This means 3528 // the outer shift size must be >= the number of bits added by the ext. 3529 // As a corollary, we don't care what kind of ext it is. 3530 if (N1C && (N0.getOpcode() == ISD::ZERO_EXTEND || 3531 N0.getOpcode() == ISD::ANY_EXTEND || 3532 N0.getOpcode() == ISD::SIGN_EXTEND) && 3533 N0.getOperand(0).getOpcode() == ISD::SHL && 3534 isa<ConstantSDNode>(N0.getOperand(0)->getOperand(1))) { 3535 uint64_t c1 = 3536 cast<ConstantSDNode>(N0.getOperand(0)->getOperand(1))->getZExtValue(); 3537 uint64_t c2 = N1C->getZExtValue(); 3538 EVT InnerShiftVT = N0.getOperand(0).getValueType(); 3539 uint64_t InnerShiftSize = InnerShiftVT.getScalarType().getSizeInBits(); 3540 if (c2 >= OpSizeInBits - InnerShiftSize) { 3541 if (c1 + c2 >= OpSizeInBits) 3542 return DAG.getConstant(0, VT); 3543 return DAG.getNode(ISD::SHL, N0->getDebugLoc(), VT, 3544 DAG.getNode(N0.getOpcode(), N0->getDebugLoc(), VT, 3545 N0.getOperand(0)->getOperand(0)), 3546 DAG.getConstant(c1 + c2, N1.getValueType())); 3547 } 3548 } 3549 3550 // fold (shl (srl x, c1), c2) -> (and (shl x, (sub c2, c1), MASK) or 3551 // (and (srl x, (sub c1, c2), MASK) 3552 // Only fold this if the inner shift has no other uses -- if it does, folding 3553 // this will increase the total number of instructions. 3554 if (N1C && N0.getOpcode() == ISD::SRL && N0.hasOneUse() && 3555 N0.getOperand(1).getOpcode() == ISD::Constant) { 3556 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 3557 if (c1 < VT.getSizeInBits()) { 3558 uint64_t c2 = N1C->getZExtValue(); 3559 APInt Mask = APInt::getHighBitsSet(VT.getSizeInBits(), 3560 VT.getSizeInBits() - c1); 3561 SDValue Shift; 3562 if (c2 > c1) { 3563 Mask = Mask.shl(c2-c1); 3564 Shift = DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0.getOperand(0), 3565 DAG.getConstant(c2-c1, N1.getValueType())); 3566 } else { 3567 Mask = Mask.lshr(c1-c2); 3568 Shift = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), 3569 DAG.getConstant(c1-c2, N1.getValueType())); 3570 } 3571 return DAG.getNode(ISD::AND, N0.getDebugLoc(), VT, Shift, 3572 DAG.getConstant(Mask, VT)); 3573 } 3574 } 3575 // fold (shl (sra x, c1), c1) -> (and x, (shl -1, c1)) 3576 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) { 3577 SDValue HiBitsMask = 3578 DAG.getConstant(APInt::getHighBitsSet(VT.getSizeInBits(), 3579 VT.getSizeInBits() - 3580 N1C->getZExtValue()), 3581 VT); 3582 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0), 3583 HiBitsMask); 3584 } 3585 3586 if (N1C) { 3587 SDValue NewSHL = visitShiftByConstant(N, N1C->getZExtValue()); 3588 if (NewSHL.getNode()) 3589 return NewSHL; 3590 } 3591 3592 return SDValue(); 3593} 3594 3595SDValue DAGCombiner::visitSRA(SDNode *N) { 3596 SDValue N0 = N->getOperand(0); 3597 SDValue N1 = N->getOperand(1); 3598 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3599 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3600 EVT VT = N0.getValueType(); 3601 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits(); 3602 3603 // fold (sra c1, c2) -> (sra c1, c2) 3604 if (N0C && N1C) 3605 return DAG.FoldConstantArithmetic(ISD::SRA, VT, N0C, N1C); 3606 // fold (sra 0, x) -> 0 3607 if (N0C && N0C->isNullValue()) 3608 return N0; 3609 // fold (sra -1, x) -> -1 3610 if (N0C && N0C->isAllOnesValue()) 3611 return N0; 3612 // fold (sra x, (setge c, size(x))) -> undef 3613 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 3614 return DAG.getUNDEF(VT); 3615 // fold (sra x, 0) -> x 3616 if (N1C && N1C->isNullValue()) 3617 return N0; 3618 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports 3619 // sext_inreg. 3620 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) { 3621 unsigned LowBits = OpSizeInBits - (unsigned)N1C->getZExtValue(); 3622 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), LowBits); 3623 if (VT.isVector()) 3624 ExtVT = EVT::getVectorVT(*DAG.getContext(), 3625 ExtVT, VT.getVectorNumElements()); 3626 if ((!LegalOperations || 3627 TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, ExtVT))) 3628 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, 3629 N0.getOperand(0), DAG.getValueType(ExtVT)); 3630 } 3631 3632 // fold (sra (sra x, c1), c2) -> (sra x, (add c1, c2)) 3633 if (N1C && N0.getOpcode() == ISD::SRA) { 3634 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 3635 unsigned Sum = N1C->getZExtValue() + C1->getZExtValue(); 3636 if (Sum >= OpSizeInBits) Sum = OpSizeInBits-1; 3637 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0.getOperand(0), 3638 DAG.getConstant(Sum, N1C->getValueType(0))); 3639 } 3640 } 3641 3642 // fold (sra (shl X, m), (sub result_size, n)) 3643 // -> (sign_extend (trunc (shl X, (sub (sub result_size, n), m)))) for 3644 // result_size - n != m. 3645 // If truncate is free for the target sext(shl) is likely to result in better 3646 // code. 3647 if (N0.getOpcode() == ISD::SHL) { 3648 // Get the two constanst of the shifts, CN0 = m, CN = n. 3649 const ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 3650 if (N01C && N1C) { 3651 // Determine what the truncate's result bitsize and type would be. 3652 EVT TruncVT = 3653 EVT::getIntegerVT(*DAG.getContext(), 3654 OpSizeInBits - N1C->getZExtValue()); 3655 // Determine the residual right-shift amount. 3656 signed ShiftAmt = N1C->getZExtValue() - N01C->getZExtValue(); 3657 3658 // If the shift is not a no-op (in which case this should be just a sign 3659 // extend already), the truncated to type is legal, sign_extend is legal 3660 // on that type, and the truncate to that type is both legal and free, 3661 // perform the transform. 3662 if ((ShiftAmt > 0) && 3663 TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND, TruncVT) && 3664 TLI.isOperationLegalOrCustom(ISD::TRUNCATE, VT) && 3665 TLI.isTruncateFree(VT, TruncVT)) { 3666 3667 SDValue Amt = DAG.getConstant(ShiftAmt, 3668 getShiftAmountTy(N0.getOperand(0).getValueType())); 3669 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, 3670 N0.getOperand(0), Amt); 3671 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), TruncVT, 3672 Shift); 3673 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), 3674 N->getValueType(0), Trunc); 3675 } 3676 } 3677 } 3678 3679 // fold (sra x, (trunc (and y, c))) -> (sra x, (and (trunc y), (trunc c))). 3680 if (N1.getOpcode() == ISD::TRUNCATE && 3681 N1.getOperand(0).getOpcode() == ISD::AND && 3682 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 3683 SDValue N101 = N1.getOperand(0).getOperand(1); 3684 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 3685 EVT TruncVT = N1.getValueType(); 3686 SDValue N100 = N1.getOperand(0).getOperand(0); 3687 APInt TruncC = N101C->getAPIntValue(); 3688 TruncC = TruncC.trunc(TruncVT.getScalarType().getSizeInBits()); 3689 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0, 3690 DAG.getNode(ISD::AND, N->getDebugLoc(), 3691 TruncVT, 3692 DAG.getNode(ISD::TRUNCATE, 3693 N->getDebugLoc(), 3694 TruncVT, N100), 3695 DAG.getConstant(TruncC, TruncVT))); 3696 } 3697 } 3698 3699 // fold (sra (trunc (sr x, c1)), c2) -> (trunc (sra x, c1+c2)) 3700 // if c1 is equal to the number of bits the trunc removes 3701 if (N0.getOpcode() == ISD::TRUNCATE && 3702 (N0.getOperand(0).getOpcode() == ISD::SRL || 3703 N0.getOperand(0).getOpcode() == ISD::SRA) && 3704 N0.getOperand(0).hasOneUse() && 3705 N0.getOperand(0).getOperand(1).hasOneUse() && 3706 N1C && isa<ConstantSDNode>(N0.getOperand(0).getOperand(1))) { 3707 EVT LargeVT = N0.getOperand(0).getValueType(); 3708 ConstantSDNode *LargeShiftAmt = 3709 cast<ConstantSDNode>(N0.getOperand(0).getOperand(1)); 3710 3711 if (LargeVT.getScalarType().getSizeInBits() - OpSizeInBits == 3712 LargeShiftAmt->getZExtValue()) { 3713 SDValue Amt = 3714 DAG.getConstant(LargeShiftAmt->getZExtValue() + N1C->getZExtValue(), 3715 getShiftAmountTy(N0.getOperand(0).getOperand(0).getValueType())); 3716 SDValue SRA = DAG.getNode(ISD::SRA, N->getDebugLoc(), LargeVT, 3717 N0.getOperand(0).getOperand(0), Amt); 3718 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, SRA); 3719 } 3720 } 3721 3722 // Simplify, based on bits shifted out of the LHS. 3723 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 3724 return SDValue(N, 0); 3725 3726 3727 // If the sign bit is known to be zero, switch this to a SRL. 3728 if (DAG.SignBitIsZero(N0)) 3729 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, N1); 3730 3731 if (N1C) { 3732 SDValue NewSRA = visitShiftByConstant(N, N1C->getZExtValue()); 3733 if (NewSRA.getNode()) 3734 return NewSRA; 3735 } 3736 3737 return SDValue(); 3738} 3739 3740SDValue DAGCombiner::visitSRL(SDNode *N) { 3741 SDValue N0 = N->getOperand(0); 3742 SDValue N1 = N->getOperand(1); 3743 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3744 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3745 EVT VT = N0.getValueType(); 3746 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits(); 3747 3748 // fold (srl c1, c2) -> c1 >>u c2 3749 if (N0C && N1C) 3750 return DAG.FoldConstantArithmetic(ISD::SRL, VT, N0C, N1C); 3751 // fold (srl 0, x) -> 0 3752 if (N0C && N0C->isNullValue()) 3753 return N0; 3754 // fold (srl x, c >= size(x)) -> undef 3755 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 3756 return DAG.getUNDEF(VT); 3757 // fold (srl x, 0) -> x 3758 if (N1C && N1C->isNullValue()) 3759 return N0; 3760 // if (srl x, c) is known to be zero, return 0 3761 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0), 3762 APInt::getAllOnesValue(OpSizeInBits))) 3763 return DAG.getConstant(0, VT); 3764 3765 // fold (srl (srl x, c1), c2) -> 0 or (srl x, (add c1, c2)) 3766 if (N1C && N0.getOpcode() == ISD::SRL && 3767 N0.getOperand(1).getOpcode() == ISD::Constant) { 3768 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 3769 uint64_t c2 = N1C->getZExtValue(); 3770 if (c1 + c2 >= OpSizeInBits) 3771 return DAG.getConstant(0, VT); 3772 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), 3773 DAG.getConstant(c1 + c2, N1.getValueType())); 3774 } 3775 3776 // fold (srl (trunc (srl x, c1)), c2) -> 0 or (trunc (srl x, (add c1, c2))) 3777 if (N1C && N0.getOpcode() == ISD::TRUNCATE && 3778 N0.getOperand(0).getOpcode() == ISD::SRL && 3779 isa<ConstantSDNode>(N0.getOperand(0)->getOperand(1))) { 3780 uint64_t c1 = 3781 cast<ConstantSDNode>(N0.getOperand(0)->getOperand(1))->getZExtValue(); 3782 uint64_t c2 = N1C->getZExtValue(); 3783 EVT InnerShiftVT = N0.getOperand(0).getValueType(); 3784 EVT ShiftCountVT = N0.getOperand(0)->getOperand(1).getValueType(); 3785 uint64_t InnerShiftSize = InnerShiftVT.getScalarType().getSizeInBits(); 3786 // This is only valid if the OpSizeInBits + c1 = size of inner shift. 3787 if (c1 + OpSizeInBits == InnerShiftSize) { 3788 if (c1 + c2 >= InnerShiftSize) 3789 return DAG.getConstant(0, VT); 3790 return DAG.getNode(ISD::TRUNCATE, N0->getDebugLoc(), VT, 3791 DAG.getNode(ISD::SRL, N0->getDebugLoc(), InnerShiftVT, 3792 N0.getOperand(0)->getOperand(0), 3793 DAG.getConstant(c1 + c2, ShiftCountVT))); 3794 } 3795 } 3796 3797 // fold (srl (shl x, c), c) -> (and x, cst2) 3798 if (N1C && N0.getOpcode() == ISD::SHL && N0.getOperand(1) == N1 && 3799 N0.getValueSizeInBits() <= 64) { 3800 uint64_t ShAmt = N1C->getZExtValue()+64-N0.getValueSizeInBits(); 3801 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0), 3802 DAG.getConstant(~0ULL >> ShAmt, VT)); 3803 } 3804 3805 3806 // fold (srl (anyextend x), c) -> (anyextend (srl x, c)) 3807 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 3808 // Shifting in all undef bits? 3809 EVT SmallVT = N0.getOperand(0).getValueType(); 3810 if (N1C->getZExtValue() >= SmallVT.getSizeInBits()) 3811 return DAG.getUNDEF(VT); 3812 3813 if (!LegalTypes || TLI.isTypeDesirableForOp(ISD::SRL, SmallVT)) { 3814 uint64_t ShiftAmt = N1C->getZExtValue(); 3815 SDValue SmallShift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), SmallVT, 3816 N0.getOperand(0), 3817 DAG.getConstant(ShiftAmt, getShiftAmountTy(SmallVT))); 3818 AddToWorkList(SmallShift.getNode()); 3819 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, SmallShift); 3820 } 3821 } 3822 3823 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign 3824 // bit, which is unmodified by sra. 3825 if (N1C && N1C->getZExtValue() + 1 == VT.getSizeInBits()) { 3826 if (N0.getOpcode() == ISD::SRA) 3827 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), N1); 3828 } 3829 3830 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit). 3831 if (N1C && N0.getOpcode() == ISD::CTLZ && 3832 N1C->getAPIntValue() == Log2_32(VT.getSizeInBits())) { 3833 APInt KnownZero, KnownOne; 3834 DAG.ComputeMaskedBits(N0.getOperand(0), KnownZero, KnownOne); 3835 3836 // If any of the input bits are KnownOne, then the input couldn't be all 3837 // zeros, thus the result of the srl will always be zero. 3838 if (KnownOne.getBoolValue()) return DAG.getConstant(0, VT); 3839 3840 // If all of the bits input the to ctlz node are known to be zero, then 3841 // the result of the ctlz is "32" and the result of the shift is one. 3842 APInt UnknownBits = ~KnownZero; 3843 if (UnknownBits == 0) return DAG.getConstant(1, VT); 3844 3845 // Otherwise, check to see if there is exactly one bit input to the ctlz. 3846 if ((UnknownBits & (UnknownBits - 1)) == 0) { 3847 // Okay, we know that only that the single bit specified by UnknownBits 3848 // could be set on input to the CTLZ node. If this bit is set, the SRL 3849 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair 3850 // to an SRL/XOR pair, which is likely to simplify more. 3851 unsigned ShAmt = UnknownBits.countTrailingZeros(); 3852 SDValue Op = N0.getOperand(0); 3853 3854 if (ShAmt) { 3855 Op = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, Op, 3856 DAG.getConstant(ShAmt, getShiftAmountTy(Op.getValueType()))); 3857 AddToWorkList(Op.getNode()); 3858 } 3859 3860 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, 3861 Op, DAG.getConstant(1, VT)); 3862 } 3863 } 3864 3865 // fold (srl x, (trunc (and y, c))) -> (srl x, (and (trunc y), (trunc c))). 3866 if (N1.getOpcode() == ISD::TRUNCATE && 3867 N1.getOperand(0).getOpcode() == ISD::AND && 3868 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 3869 SDValue N101 = N1.getOperand(0).getOperand(1); 3870 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 3871 EVT TruncVT = N1.getValueType(); 3872 SDValue N100 = N1.getOperand(0).getOperand(0); 3873 APInt TruncC = N101C->getAPIntValue(); 3874 TruncC = TruncC.trunc(TruncVT.getSizeInBits()); 3875 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, 3876 DAG.getNode(ISD::AND, N->getDebugLoc(), 3877 TruncVT, 3878 DAG.getNode(ISD::TRUNCATE, 3879 N->getDebugLoc(), 3880 TruncVT, N100), 3881 DAG.getConstant(TruncC, TruncVT))); 3882 } 3883 } 3884 3885 // fold operands of srl based on knowledge that the low bits are not 3886 // demanded. 3887 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 3888 return SDValue(N, 0); 3889 3890 if (N1C) { 3891 SDValue NewSRL = visitShiftByConstant(N, N1C->getZExtValue()); 3892 if (NewSRL.getNode()) 3893 return NewSRL; 3894 } 3895 3896 // Attempt to convert a srl of a load into a narrower zero-extending load. 3897 SDValue NarrowLoad = ReduceLoadWidth(N); 3898 if (NarrowLoad.getNode()) 3899 return NarrowLoad; 3900 3901 // Here is a common situation. We want to optimize: 3902 // 3903 // %a = ... 3904 // %b = and i32 %a, 2 3905 // %c = srl i32 %b, 1 3906 // brcond i32 %c ... 3907 // 3908 // into 3909 // 3910 // %a = ... 3911 // %b = and %a, 2 3912 // %c = setcc eq %b, 0 3913 // brcond %c ... 3914 // 3915 // However when after the source operand of SRL is optimized into AND, the SRL 3916 // itself may not be optimized further. Look for it and add the BRCOND into 3917 // the worklist. 3918 if (N->hasOneUse()) { 3919 SDNode *Use = *N->use_begin(); 3920 if (Use->getOpcode() == ISD::BRCOND) 3921 AddToWorkList(Use); 3922 else if (Use->getOpcode() == ISD::TRUNCATE && Use->hasOneUse()) { 3923 // Also look pass the truncate. 3924 Use = *Use->use_begin(); 3925 if (Use->getOpcode() == ISD::BRCOND) 3926 AddToWorkList(Use); 3927 } 3928 } 3929 3930 return SDValue(); 3931} 3932 3933SDValue DAGCombiner::visitCTLZ(SDNode *N) { 3934 SDValue N0 = N->getOperand(0); 3935 EVT VT = N->getValueType(0); 3936 3937 // fold (ctlz c1) -> c2 3938 if (isa<ConstantSDNode>(N0)) 3939 return DAG.getNode(ISD::CTLZ, N->getDebugLoc(), VT, N0); 3940 return SDValue(); 3941} 3942 3943SDValue DAGCombiner::visitCTLZ_ZERO_UNDEF(SDNode *N) { 3944 SDValue N0 = N->getOperand(0); 3945 EVT VT = N->getValueType(0); 3946 3947 // fold (ctlz_zero_undef c1) -> c2 3948 if (isa<ConstantSDNode>(N0)) 3949 return DAG.getNode(ISD::CTLZ_ZERO_UNDEF, N->getDebugLoc(), VT, N0); 3950 return SDValue(); 3951} 3952 3953SDValue DAGCombiner::visitCTTZ(SDNode *N) { 3954 SDValue N0 = N->getOperand(0); 3955 EVT VT = N->getValueType(0); 3956 3957 // fold (cttz c1) -> c2 3958 if (isa<ConstantSDNode>(N0)) 3959 return DAG.getNode(ISD::CTTZ, N->getDebugLoc(), VT, N0); 3960 return SDValue(); 3961} 3962 3963SDValue DAGCombiner::visitCTTZ_ZERO_UNDEF(SDNode *N) { 3964 SDValue N0 = N->getOperand(0); 3965 EVT VT = N->getValueType(0); 3966 3967 // fold (cttz_zero_undef c1) -> c2 3968 if (isa<ConstantSDNode>(N0)) 3969 return DAG.getNode(ISD::CTTZ_ZERO_UNDEF, N->getDebugLoc(), VT, N0); 3970 return SDValue(); 3971} 3972 3973SDValue DAGCombiner::visitCTPOP(SDNode *N) { 3974 SDValue N0 = N->getOperand(0); 3975 EVT VT = N->getValueType(0); 3976 3977 // fold (ctpop c1) -> c2 3978 if (isa<ConstantSDNode>(N0)) 3979 return DAG.getNode(ISD::CTPOP, N->getDebugLoc(), VT, N0); 3980 return SDValue(); 3981} 3982 3983SDValue DAGCombiner::visitSELECT(SDNode *N) { 3984 SDValue N0 = N->getOperand(0); 3985 SDValue N1 = N->getOperand(1); 3986 SDValue N2 = N->getOperand(2); 3987 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3988 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3989 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2); 3990 EVT VT = N->getValueType(0); 3991 EVT VT0 = N0.getValueType(); 3992 3993 // fold (select C, X, X) -> X 3994 if (N1 == N2) 3995 return N1; 3996 // fold (select true, X, Y) -> X 3997 if (N0C && !N0C->isNullValue()) 3998 return N1; 3999 // fold (select false, X, Y) -> Y 4000 if (N0C && N0C->isNullValue()) 4001 return N2; 4002 // fold (select C, 1, X) -> (or C, X) 4003 if (VT == MVT::i1 && N1C && N1C->getAPIntValue() == 1) 4004 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2); 4005 // fold (select C, 0, 1) -> (xor C, 1) 4006 if (VT.isInteger() && 4007 (VT0 == MVT::i1 || 4008 (VT0.isInteger() && 4009 TLI.getBooleanContents(false) == TargetLowering::ZeroOrOneBooleanContent)) && 4010 N1C && N2C && N1C->isNullValue() && N2C->getAPIntValue() == 1) { 4011 SDValue XORNode; 4012 if (VT == VT0) 4013 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT0, 4014 N0, DAG.getConstant(1, VT0)); 4015 XORNode = DAG.getNode(ISD::XOR, N0.getDebugLoc(), VT0, 4016 N0, DAG.getConstant(1, VT0)); 4017 AddToWorkList(XORNode.getNode()); 4018 if (VT.bitsGT(VT0)) 4019 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, XORNode); 4020 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, XORNode); 4021 } 4022 // fold (select C, 0, X) -> (and (not C), X) 4023 if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) { 4024 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT); 4025 AddToWorkList(NOTNode.getNode()); 4026 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, NOTNode, N2); 4027 } 4028 // fold (select C, X, 1) -> (or (not C), X) 4029 if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getAPIntValue() == 1) { 4030 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT); 4031 AddToWorkList(NOTNode.getNode()); 4032 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, NOTNode, N1); 4033 } 4034 // fold (select C, X, 0) -> (and C, X) 4035 if (VT == MVT::i1 && N2C && N2C->isNullValue()) 4036 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1); 4037 // fold (select X, X, Y) -> (or X, Y) 4038 // fold (select X, 1, Y) -> (or X, Y) 4039 if (VT == MVT::i1 && (N0 == N1 || (N1C && N1C->getAPIntValue() == 1))) 4040 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2); 4041 // fold (select X, Y, X) -> (and X, Y) 4042 // fold (select X, Y, 0) -> (and X, Y) 4043 if (VT == MVT::i1 && (N0 == N2 || (N2C && N2C->getAPIntValue() == 0))) 4044 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1); 4045 4046 // If we can fold this based on the true/false value, do so. 4047 if (SimplifySelectOps(N, N1, N2)) 4048 return SDValue(N, 0); // Don't revisit N. 4049 4050 // fold selects based on a setcc into other things, such as min/max/abs 4051 if (N0.getOpcode() == ISD::SETCC) { 4052 // FIXME: 4053 // Check against MVT::Other for SELECT_CC, which is a workaround for targets 4054 // having to say they don't support SELECT_CC on every type the DAG knows 4055 // about, since there is no way to mark an opcode illegal at all value types 4056 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other) && 4057 TLI.isOperationLegalOrCustom(ISD::SELECT_CC, VT)) 4058 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT, 4059 N0.getOperand(0), N0.getOperand(1), 4060 N1, N2, N0.getOperand(2)); 4061 return SimplifySelect(N->getDebugLoc(), N0, N1, N2); 4062 } 4063 4064 return SDValue(); 4065} 4066 4067SDValue DAGCombiner::visitSELECT_CC(SDNode *N) { 4068 SDValue N0 = N->getOperand(0); 4069 SDValue N1 = N->getOperand(1); 4070 SDValue N2 = N->getOperand(2); 4071 SDValue N3 = N->getOperand(3); 4072 SDValue N4 = N->getOperand(4); 4073 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get(); 4074 4075 // fold select_cc lhs, rhs, x, x, cc -> x 4076 if (N2 == N3) 4077 return N2; 4078 4079 // Determine if the condition we're dealing with is constant 4080 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()), 4081 N0, N1, CC, N->getDebugLoc(), false); 4082 if (SCC.getNode()) AddToWorkList(SCC.getNode()); 4083 4084 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode())) { 4085 if (!SCCC->isNullValue()) 4086 return N2; // cond always true -> true val 4087 else 4088 return N3; // cond always false -> false val 4089 } 4090 4091 // Fold to a simpler select_cc 4092 if (SCC.getNode() && SCC.getOpcode() == ISD::SETCC) 4093 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), N2.getValueType(), 4094 SCC.getOperand(0), SCC.getOperand(1), N2, N3, 4095 SCC.getOperand(2)); 4096 4097 // If we can fold this based on the true/false value, do so. 4098 if (SimplifySelectOps(N, N2, N3)) 4099 return SDValue(N, 0); // Don't revisit N. 4100 4101 // fold select_cc into other things, such as min/max/abs 4102 return SimplifySelectCC(N->getDebugLoc(), N0, N1, N2, N3, CC); 4103} 4104 4105SDValue DAGCombiner::visitSETCC(SDNode *N) { 4106 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1), 4107 cast<CondCodeSDNode>(N->getOperand(2))->get(), 4108 N->getDebugLoc()); 4109} 4110 4111// ExtendUsesToFormExtLoad - Trying to extend uses of a load to enable this: 4112// "fold ({s|z|a}ext (load x)) -> ({s|z|a}ext (truncate ({s|z|a}extload x)))" 4113// transformation. Returns true if extension are possible and the above 4114// mentioned transformation is profitable. 4115static bool ExtendUsesToFormExtLoad(SDNode *N, SDValue N0, 4116 unsigned ExtOpc, 4117 SmallVector<SDNode*, 4> &ExtendNodes, 4118 const TargetLowering &TLI) { 4119 bool HasCopyToRegUses = false; 4120 bool isTruncFree = TLI.isTruncateFree(N->getValueType(0), N0.getValueType()); 4121 for (SDNode::use_iterator UI = N0.getNode()->use_begin(), 4122 UE = N0.getNode()->use_end(); 4123 UI != UE; ++UI) { 4124 SDNode *User = *UI; 4125 if (User == N) 4126 continue; 4127 if (UI.getUse().getResNo() != N0.getResNo()) 4128 continue; 4129 // FIXME: Only extend SETCC N, N and SETCC N, c for now. 4130 if (ExtOpc != ISD::ANY_EXTEND && User->getOpcode() == ISD::SETCC) { 4131 ISD::CondCode CC = cast<CondCodeSDNode>(User->getOperand(2))->get(); 4132 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC)) 4133 // Sign bits will be lost after a zext. 4134 return false; 4135 bool Add = false; 4136 for (unsigned i = 0; i != 2; ++i) { 4137 SDValue UseOp = User->getOperand(i); 4138 if (UseOp == N0) 4139 continue; 4140 if (!isa<ConstantSDNode>(UseOp)) 4141 return false; 4142 Add = true; 4143 } 4144 if (Add) 4145 ExtendNodes.push_back(User); 4146 continue; 4147 } 4148 // If truncates aren't free and there are users we can't 4149 // extend, it isn't worthwhile. 4150 if (!isTruncFree) 4151 return false; 4152 // Remember if this value is live-out. 4153 if (User->getOpcode() == ISD::CopyToReg) 4154 HasCopyToRegUses = true; 4155 } 4156 4157 if (HasCopyToRegUses) { 4158 bool BothLiveOut = false; 4159 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 4160 UI != UE; ++UI) { 4161 SDUse &Use = UI.getUse(); 4162 if (Use.getResNo() == 0 && Use.getUser()->getOpcode() == ISD::CopyToReg) { 4163 BothLiveOut = true; 4164 break; 4165 } 4166 } 4167 if (BothLiveOut) 4168 // Both unextended and extended values are live out. There had better be 4169 // a good reason for the transformation. 4170 return ExtendNodes.size(); 4171 } 4172 return true; 4173} 4174 4175void DAGCombiner::ExtendSetCCUses(SmallVector<SDNode*, 4> SetCCs, 4176 SDValue Trunc, SDValue ExtLoad, DebugLoc DL, 4177 ISD::NodeType ExtType) { 4178 // Extend SetCC uses if necessary. 4179 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 4180 SDNode *SetCC = SetCCs[i]; 4181 SmallVector<SDValue, 4> Ops; 4182 4183 for (unsigned j = 0; j != 2; ++j) { 4184 SDValue SOp = SetCC->getOperand(j); 4185 if (SOp == Trunc) 4186 Ops.push_back(ExtLoad); 4187 else 4188 Ops.push_back(DAG.getNode(ExtType, DL, ExtLoad->getValueType(0), SOp)); 4189 } 4190 4191 Ops.push_back(SetCC->getOperand(2)); 4192 CombineTo(SetCC, DAG.getNode(ISD::SETCC, DL, SetCC->getValueType(0), 4193 &Ops[0], Ops.size())); 4194 } 4195} 4196 4197SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) { 4198 SDValue N0 = N->getOperand(0); 4199 EVT VT = N->getValueType(0); 4200 4201 // fold (sext c1) -> c1 4202 if (isa<ConstantSDNode>(N0)) 4203 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N0); 4204 4205 // fold (sext (sext x)) -> (sext x) 4206 // fold (sext (aext x)) -> (sext x) 4207 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 4208 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, 4209 N0.getOperand(0)); 4210 4211 if (N0.getOpcode() == ISD::TRUNCATE) { 4212 // fold (sext (truncate (load x))) -> (sext (smaller load x)) 4213 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n))) 4214 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 4215 if (NarrowLoad.getNode()) { 4216 SDNode* oye = N0.getNode()->getOperand(0).getNode(); 4217 if (NarrowLoad.getNode() != N0.getNode()) { 4218 CombineTo(N0.getNode(), NarrowLoad); 4219 // CombineTo deleted the truncate, if needed, but not what's under it. 4220 AddToWorkList(oye); 4221 } 4222 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4223 } 4224 4225 // See if the value being truncated is already sign extended. If so, just 4226 // eliminate the trunc/sext pair. 4227 SDValue Op = N0.getOperand(0); 4228 unsigned OpBits = Op.getValueType().getScalarType().getSizeInBits(); 4229 unsigned MidBits = N0.getValueType().getScalarType().getSizeInBits(); 4230 unsigned DestBits = VT.getScalarType().getSizeInBits(); 4231 unsigned NumSignBits = DAG.ComputeNumSignBits(Op); 4232 4233 if (OpBits == DestBits) { 4234 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign 4235 // bits, it is already ready. 4236 if (NumSignBits > DestBits-MidBits) 4237 return Op; 4238 } else if (OpBits < DestBits) { 4239 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign 4240 // bits, just sext from i32. 4241 if (NumSignBits > OpBits-MidBits) 4242 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, Op); 4243 } else { 4244 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign 4245 // bits, just truncate to i32. 4246 if (NumSignBits > OpBits-MidBits) 4247 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op); 4248 } 4249 4250 // fold (sext (truncate x)) -> (sextinreg x). 4251 if (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, 4252 N0.getValueType())) { 4253 if (OpBits < DestBits) 4254 Op = DAG.getNode(ISD::ANY_EXTEND, N0.getDebugLoc(), VT, Op); 4255 else if (OpBits > DestBits) 4256 Op = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), VT, Op); 4257 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, Op, 4258 DAG.getValueType(N0.getValueType())); 4259 } 4260 } 4261 4262 // fold (sext (load x)) -> (sext (truncate (sextload x))) 4263 // None of the supported targets knows how to perform load and sign extend 4264 // on vectors in one instruction. We only perform this transformation on 4265 // scalars. 4266 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() && 4267 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 4268 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()))) { 4269 bool DoXform = true; 4270 SmallVector<SDNode*, 4> SetCCs; 4271 if (!N0.hasOneUse()) 4272 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::SIGN_EXTEND, SetCCs, TLI); 4273 if (DoXform) { 4274 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4275 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 4276 LN0->getChain(), 4277 LN0->getBasePtr(), LN0->getPointerInfo(), 4278 N0.getValueType(), 4279 LN0->isVolatile(), LN0->isNonTemporal(), 4280 LN0->getAlignment()); 4281 CombineTo(N, ExtLoad); 4282 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 4283 N0.getValueType(), ExtLoad); 4284 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 4285 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(), 4286 ISD::SIGN_EXTEND); 4287 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4288 } 4289 } 4290 4291 // fold (sext (sextload x)) -> (sext (truncate (sextload x))) 4292 // fold (sext ( extload x)) -> (sext (truncate (sextload x))) 4293 if ((ISD::isSEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) && 4294 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) { 4295 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4296 EVT MemVT = LN0->getMemoryVT(); 4297 if ((!LegalOperations && !LN0->isVolatile()) || 4298 TLI.isLoadExtLegal(ISD::SEXTLOAD, MemVT)) { 4299 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 4300 LN0->getChain(), 4301 LN0->getBasePtr(), LN0->getPointerInfo(), 4302 MemVT, 4303 LN0->isVolatile(), LN0->isNonTemporal(), 4304 LN0->getAlignment()); 4305 CombineTo(N, ExtLoad); 4306 CombineTo(N0.getNode(), 4307 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 4308 N0.getValueType(), ExtLoad), 4309 ExtLoad.getValue(1)); 4310 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4311 } 4312 } 4313 4314 // fold (sext (and/or/xor (load x), cst)) -> 4315 // (and/or/xor (sextload x), (sext cst)) 4316 if ((N0.getOpcode() == ISD::AND || N0.getOpcode() == ISD::OR || 4317 N0.getOpcode() == ISD::XOR) && 4318 isa<LoadSDNode>(N0.getOperand(0)) && 4319 N0.getOperand(1).getOpcode() == ISD::Constant && 4320 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()) && 4321 (!LegalOperations && TLI.isOperationLegal(N0.getOpcode(), VT))) { 4322 LoadSDNode *LN0 = cast<LoadSDNode>(N0.getOperand(0)); 4323 if (LN0->getExtensionType() != ISD::ZEXTLOAD) { 4324 bool DoXform = true; 4325 SmallVector<SDNode*, 4> SetCCs; 4326 if (!N0.hasOneUse()) 4327 DoXform = ExtendUsesToFormExtLoad(N, N0.getOperand(0), ISD::SIGN_EXTEND, 4328 SetCCs, TLI); 4329 if (DoXform) { 4330 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, LN0->getDebugLoc(), VT, 4331 LN0->getChain(), LN0->getBasePtr(), 4332 LN0->getPointerInfo(), 4333 LN0->getMemoryVT(), 4334 LN0->isVolatile(), 4335 LN0->isNonTemporal(), 4336 LN0->getAlignment()); 4337 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 4338 Mask = Mask.sext(VT.getSizeInBits()); 4339 SDValue And = DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, 4340 ExtLoad, DAG.getConstant(Mask, VT)); 4341 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, 4342 N0.getOperand(0).getDebugLoc(), 4343 N0.getOperand(0).getValueType(), ExtLoad); 4344 CombineTo(N, And); 4345 CombineTo(N0.getOperand(0).getNode(), Trunc, ExtLoad.getValue(1)); 4346 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(), 4347 ISD::SIGN_EXTEND); 4348 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4349 } 4350 } 4351 } 4352 4353 if (N0.getOpcode() == ISD::SETCC) { 4354 // sext(setcc) -> sext_in_reg(vsetcc) for vectors. 4355 // Only do this before legalize for now. 4356 if (VT.isVector() && !LegalOperations) { 4357 EVT N0VT = N0.getOperand(0).getValueType(); 4358 // We know that the # elements of the results is the same as the 4359 // # elements of the compare (and the # elements of the compare result 4360 // for that matter). Check to see that they are the same size. If so, 4361 // we know that the element size of the sext'd result matches the 4362 // element size of the compare operands. 4363 if (VT.getSizeInBits() == N0VT.getSizeInBits()) 4364 return DAG.getSetCC(N->getDebugLoc(), VT, N0.getOperand(0), 4365 N0.getOperand(1), 4366 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 4367 // If the desired elements are smaller or larger than the source 4368 // elements we can use a matching integer vector type and then 4369 // truncate/sign extend 4370 else { 4371 EVT MatchingElementType = 4372 EVT::getIntegerVT(*DAG.getContext(), 4373 N0VT.getScalarType().getSizeInBits()); 4374 EVT MatchingVectorType = 4375 EVT::getVectorVT(*DAG.getContext(), MatchingElementType, 4376 N0VT.getVectorNumElements()); 4377 SDValue VsetCC = 4378 DAG.getSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0), 4379 N0.getOperand(1), 4380 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 4381 return DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT); 4382 } 4383 } 4384 4385 // sext(setcc x, y, cc) -> (select_cc x, y, -1, 0, cc) 4386 unsigned ElementWidth = VT.getScalarType().getSizeInBits(); 4387 SDValue NegOne = 4388 DAG.getConstant(APInt::getAllOnesValue(ElementWidth), VT); 4389 SDValue SCC = 4390 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 4391 NegOne, DAG.getConstant(0, VT), 4392 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 4393 if (SCC.getNode()) return SCC; 4394 if (!LegalOperations || 4395 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(VT))) 4396 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT, 4397 DAG.getSetCC(N->getDebugLoc(), 4398 TLI.getSetCCResultType(VT), 4399 N0.getOperand(0), N0.getOperand(1), 4400 cast<CondCodeSDNode>(N0.getOperand(2))->get()), 4401 NegOne, DAG.getConstant(0, VT)); 4402 } 4403 4404 // fold (sext x) -> (zext x) if the sign bit is known zero. 4405 if ((!LegalOperations || TLI.isOperationLegal(ISD::ZERO_EXTEND, VT)) && 4406 DAG.SignBitIsZero(N0)) 4407 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0); 4408 4409 return SDValue(); 4410} 4411 4412SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) { 4413 SDValue N0 = N->getOperand(0); 4414 EVT VT = N->getValueType(0); 4415 4416 // fold (zext c1) -> c1 4417 if (isa<ConstantSDNode>(N0)) 4418 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0); 4419 // fold (zext (zext x)) -> (zext x) 4420 // fold (zext (aext x)) -> (zext x) 4421 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 4422 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, 4423 N0.getOperand(0)); 4424 4425 // fold (zext (truncate x)) -> (zext x) or 4426 // (zext (truncate x)) -> (truncate x) 4427 // This is valid when the truncated bits of x are already zero. 4428 // FIXME: We should extend this to work for vectors too. 4429 if (N0.getOpcode() == ISD::TRUNCATE && !VT.isVector()) { 4430 SDValue Op = N0.getOperand(0); 4431 APInt TruncatedBits 4432 = APInt::getBitsSet(Op.getValueSizeInBits(), 4433 N0.getValueSizeInBits(), 4434 std::min(Op.getValueSizeInBits(), 4435 VT.getSizeInBits())); 4436 APInt KnownZero, KnownOne; 4437 DAG.ComputeMaskedBits(Op, KnownZero, KnownOne); 4438 if (TruncatedBits == (KnownZero & TruncatedBits)) { 4439 if (VT.bitsGT(Op.getValueType())) 4440 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, Op); 4441 if (VT.bitsLT(Op.getValueType())) 4442 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op); 4443 4444 return Op; 4445 } 4446 } 4447 4448 // fold (zext (truncate (load x))) -> (zext (smaller load x)) 4449 // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n))) 4450 if (N0.getOpcode() == ISD::TRUNCATE) { 4451 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 4452 if (NarrowLoad.getNode()) { 4453 SDNode* oye = N0.getNode()->getOperand(0).getNode(); 4454 if (NarrowLoad.getNode() != N0.getNode()) { 4455 CombineTo(N0.getNode(), NarrowLoad); 4456 // CombineTo deleted the truncate, if needed, but not what's under it. 4457 AddToWorkList(oye); 4458 } 4459 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4460 } 4461 } 4462 4463 // fold (zext (truncate x)) -> (and x, mask) 4464 if (N0.getOpcode() == ISD::TRUNCATE && 4465 (!LegalOperations || TLI.isOperationLegal(ISD::AND, VT))) { 4466 4467 // fold (zext (truncate (load x))) -> (zext (smaller load x)) 4468 // fold (zext (truncate (srl (load x), c))) -> (zext (smaller load (x+c/n))) 4469 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 4470 if (NarrowLoad.getNode()) { 4471 SDNode* oye = N0.getNode()->getOperand(0).getNode(); 4472 if (NarrowLoad.getNode() != N0.getNode()) { 4473 CombineTo(N0.getNode(), NarrowLoad); 4474 // CombineTo deleted the truncate, if needed, but not what's under it. 4475 AddToWorkList(oye); 4476 } 4477 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4478 } 4479 4480 SDValue Op = N0.getOperand(0); 4481 if (Op.getValueType().bitsLT(VT)) { 4482 Op = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, Op); 4483 } else if (Op.getValueType().bitsGT(VT)) { 4484 Op = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op); 4485 } 4486 return DAG.getZeroExtendInReg(Op, N->getDebugLoc(), 4487 N0.getValueType().getScalarType()); 4488 } 4489 4490 // Fold (zext (and (trunc x), cst)) -> (and x, cst), 4491 // if either of the casts is not free. 4492 if (N0.getOpcode() == ISD::AND && 4493 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 4494 N0.getOperand(1).getOpcode() == ISD::Constant && 4495 (!TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(), 4496 N0.getValueType()) || 4497 !TLI.isZExtFree(N0.getValueType(), VT))) { 4498 SDValue X = N0.getOperand(0).getOperand(0); 4499 if (X.getValueType().bitsLT(VT)) { 4500 X = DAG.getNode(ISD::ANY_EXTEND, X.getDebugLoc(), VT, X); 4501 } else if (X.getValueType().bitsGT(VT)) { 4502 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X); 4503 } 4504 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 4505 Mask = Mask.zext(VT.getSizeInBits()); 4506 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 4507 X, DAG.getConstant(Mask, VT)); 4508 } 4509 4510 // fold (zext (load x)) -> (zext (truncate (zextload x))) 4511 // None of the supported targets knows how to perform load and vector_zext 4512 // on vectors in one instruction. We only perform this transformation on 4513 // scalars. 4514 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() && 4515 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 4516 TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()))) { 4517 bool DoXform = true; 4518 SmallVector<SDNode*, 4> SetCCs; 4519 if (!N0.hasOneUse()) 4520 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ZERO_EXTEND, SetCCs, TLI); 4521 if (DoXform) { 4522 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4523 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT, 4524 LN0->getChain(), 4525 LN0->getBasePtr(), LN0->getPointerInfo(), 4526 N0.getValueType(), 4527 LN0->isVolatile(), LN0->isNonTemporal(), 4528 LN0->getAlignment()); 4529 CombineTo(N, ExtLoad); 4530 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 4531 N0.getValueType(), ExtLoad); 4532 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 4533 4534 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(), 4535 ISD::ZERO_EXTEND); 4536 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4537 } 4538 } 4539 4540 // fold (zext (and/or/xor (load x), cst)) -> 4541 // (and/or/xor (zextload x), (zext cst)) 4542 if ((N0.getOpcode() == ISD::AND || N0.getOpcode() == ISD::OR || 4543 N0.getOpcode() == ISD::XOR) && 4544 isa<LoadSDNode>(N0.getOperand(0)) && 4545 N0.getOperand(1).getOpcode() == ISD::Constant && 4546 TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()) && 4547 (!LegalOperations && TLI.isOperationLegal(N0.getOpcode(), VT))) { 4548 LoadSDNode *LN0 = cast<LoadSDNode>(N0.getOperand(0)); 4549 if (LN0->getExtensionType() != ISD::SEXTLOAD) { 4550 bool DoXform = true; 4551 SmallVector<SDNode*, 4> SetCCs; 4552 if (!N0.hasOneUse()) 4553 DoXform = ExtendUsesToFormExtLoad(N, N0.getOperand(0), ISD::ZERO_EXTEND, 4554 SetCCs, TLI); 4555 if (DoXform) { 4556 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), VT, 4557 LN0->getChain(), LN0->getBasePtr(), 4558 LN0->getPointerInfo(), 4559 LN0->getMemoryVT(), 4560 LN0->isVolatile(), 4561 LN0->isNonTemporal(), 4562 LN0->getAlignment()); 4563 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 4564 Mask = Mask.zext(VT.getSizeInBits()); 4565 SDValue And = DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, 4566 ExtLoad, DAG.getConstant(Mask, VT)); 4567 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, 4568 N0.getOperand(0).getDebugLoc(), 4569 N0.getOperand(0).getValueType(), ExtLoad); 4570 CombineTo(N, And); 4571 CombineTo(N0.getOperand(0).getNode(), Trunc, ExtLoad.getValue(1)); 4572 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(), 4573 ISD::ZERO_EXTEND); 4574 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4575 } 4576 } 4577 } 4578 4579 // fold (zext (zextload x)) -> (zext (truncate (zextload x))) 4580 // fold (zext ( extload x)) -> (zext (truncate (zextload x))) 4581 if ((ISD::isZEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) && 4582 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) { 4583 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4584 EVT MemVT = LN0->getMemoryVT(); 4585 if ((!LegalOperations && !LN0->isVolatile()) || 4586 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT)) { 4587 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT, 4588 LN0->getChain(), 4589 LN0->getBasePtr(), LN0->getPointerInfo(), 4590 MemVT, 4591 LN0->isVolatile(), LN0->isNonTemporal(), 4592 LN0->getAlignment()); 4593 CombineTo(N, ExtLoad); 4594 CombineTo(N0.getNode(), 4595 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), N0.getValueType(), 4596 ExtLoad), 4597 ExtLoad.getValue(1)); 4598 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4599 } 4600 } 4601 4602 if (N0.getOpcode() == ISD::SETCC) { 4603 if (!LegalOperations && VT.isVector()) { 4604 // zext(setcc) -> (and (vsetcc), (1, 1, ...) for vectors. 4605 // Only do this before legalize for now. 4606 EVT N0VT = N0.getOperand(0).getValueType(); 4607 EVT EltVT = VT.getVectorElementType(); 4608 SmallVector<SDValue,8> OneOps(VT.getVectorNumElements(), 4609 DAG.getConstant(1, EltVT)); 4610 if (VT.getSizeInBits() == N0VT.getSizeInBits()) 4611 // We know that the # elements of the results is the same as the 4612 // # elements of the compare (and the # elements of the compare result 4613 // for that matter). Check to see that they are the same size. If so, 4614 // we know that the element size of the sext'd result matches the 4615 // element size of the compare operands. 4616 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 4617 DAG.getSetCC(N->getDebugLoc(), VT, N0.getOperand(0), 4618 N0.getOperand(1), 4619 cast<CondCodeSDNode>(N0.getOperand(2))->get()), 4620 DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT, 4621 &OneOps[0], OneOps.size())); 4622 4623 // If the desired elements are smaller or larger than the source 4624 // elements we can use a matching integer vector type and then 4625 // truncate/sign extend 4626 EVT MatchingElementType = 4627 EVT::getIntegerVT(*DAG.getContext(), 4628 N0VT.getScalarType().getSizeInBits()); 4629 EVT MatchingVectorType = 4630 EVT::getVectorVT(*DAG.getContext(), MatchingElementType, 4631 N0VT.getVectorNumElements()); 4632 SDValue VsetCC = 4633 DAG.getSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0), 4634 N0.getOperand(1), 4635 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 4636 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 4637 DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT), 4638 DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT, 4639 &OneOps[0], OneOps.size())); 4640 } 4641 4642 // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 4643 SDValue SCC = 4644 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 4645 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 4646 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 4647 if (SCC.getNode()) return SCC; 4648 } 4649 4650 // (zext (shl (zext x), cst)) -> (shl (zext x), cst) 4651 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL) && 4652 isa<ConstantSDNode>(N0.getOperand(1)) && 4653 N0.getOperand(0).getOpcode() == ISD::ZERO_EXTEND && 4654 N0.hasOneUse()) { 4655 SDValue ShAmt = N0.getOperand(1); 4656 unsigned ShAmtVal = cast<ConstantSDNode>(ShAmt)->getZExtValue(); 4657 if (N0.getOpcode() == ISD::SHL) { 4658 SDValue InnerZExt = N0.getOperand(0); 4659 // If the original shl may be shifting out bits, do not perform this 4660 // transformation. 4661 unsigned KnownZeroBits = InnerZExt.getValueType().getSizeInBits() - 4662 InnerZExt.getOperand(0).getValueType().getSizeInBits(); 4663 if (ShAmtVal > KnownZeroBits) 4664 return SDValue(); 4665 } 4666 4667 DebugLoc DL = N->getDebugLoc(); 4668 4669 // Ensure that the shift amount is wide enough for the shifted value. 4670 if (VT.getSizeInBits() >= 256) 4671 ShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, ShAmt); 4672 4673 return DAG.getNode(N0.getOpcode(), DL, VT, 4674 DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0)), 4675 ShAmt); 4676 } 4677 4678 return SDValue(); 4679} 4680 4681SDValue DAGCombiner::visitANY_EXTEND(SDNode *N) { 4682 SDValue N0 = N->getOperand(0); 4683 EVT VT = N->getValueType(0); 4684 4685 // fold (aext c1) -> c1 4686 if (isa<ConstantSDNode>(N0)) 4687 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, N0); 4688 // fold (aext (aext x)) -> (aext x) 4689 // fold (aext (zext x)) -> (zext x) 4690 // fold (aext (sext x)) -> (sext x) 4691 if (N0.getOpcode() == ISD::ANY_EXTEND || 4692 N0.getOpcode() == ISD::ZERO_EXTEND || 4693 N0.getOpcode() == ISD::SIGN_EXTEND) 4694 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, N0.getOperand(0)); 4695 4696 // fold (aext (truncate (load x))) -> (aext (smaller load x)) 4697 // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n))) 4698 if (N0.getOpcode() == ISD::TRUNCATE) { 4699 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 4700 if (NarrowLoad.getNode()) { 4701 SDNode* oye = N0.getNode()->getOperand(0).getNode(); 4702 if (NarrowLoad.getNode() != N0.getNode()) { 4703 CombineTo(N0.getNode(), NarrowLoad); 4704 // CombineTo deleted the truncate, if needed, but not what's under it. 4705 AddToWorkList(oye); 4706 } 4707 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4708 } 4709 } 4710 4711 // fold (aext (truncate x)) 4712 if (N0.getOpcode() == ISD::TRUNCATE) { 4713 SDValue TruncOp = N0.getOperand(0); 4714 if (TruncOp.getValueType() == VT) 4715 return TruncOp; // x iff x size == zext size. 4716 if (TruncOp.getValueType().bitsGT(VT)) 4717 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, TruncOp); 4718 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, TruncOp); 4719 } 4720 4721 // Fold (aext (and (trunc x), cst)) -> (and x, cst) 4722 // if the trunc is not free. 4723 if (N0.getOpcode() == ISD::AND && 4724 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 4725 N0.getOperand(1).getOpcode() == ISD::Constant && 4726 !TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(), 4727 N0.getValueType())) { 4728 SDValue X = N0.getOperand(0).getOperand(0); 4729 if (X.getValueType().bitsLT(VT)) { 4730 X = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, X); 4731 } else if (X.getValueType().bitsGT(VT)) { 4732 X = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, X); 4733 } 4734 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 4735 Mask = Mask.zext(VT.getSizeInBits()); 4736 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 4737 X, DAG.getConstant(Mask, VT)); 4738 } 4739 4740 // fold (aext (load x)) -> (aext (truncate (extload x))) 4741 // None of the supported targets knows how to perform load and any_ext 4742 // on vectors in one instruction. We only perform this transformation on 4743 // scalars. 4744 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() && 4745 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 4746 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) { 4747 bool DoXform = true; 4748 SmallVector<SDNode*, 4> SetCCs; 4749 if (!N0.hasOneUse()) 4750 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ANY_EXTEND, SetCCs, TLI); 4751 if (DoXform) { 4752 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4753 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT, 4754 LN0->getChain(), 4755 LN0->getBasePtr(), LN0->getPointerInfo(), 4756 N0.getValueType(), 4757 LN0->isVolatile(), LN0->isNonTemporal(), 4758 LN0->getAlignment()); 4759 CombineTo(N, ExtLoad); 4760 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 4761 N0.getValueType(), ExtLoad); 4762 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 4763 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(), 4764 ISD::ANY_EXTEND); 4765 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4766 } 4767 } 4768 4769 // fold (aext (zextload x)) -> (aext (truncate (zextload x))) 4770 // fold (aext (sextload x)) -> (aext (truncate (sextload x))) 4771 // fold (aext ( extload x)) -> (aext (truncate (extload x))) 4772 if (N0.getOpcode() == ISD::LOAD && 4773 !ISD::isNON_EXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 4774 N0.hasOneUse()) { 4775 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4776 EVT MemVT = LN0->getMemoryVT(); 4777 SDValue ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), N->getDebugLoc(), 4778 VT, LN0->getChain(), LN0->getBasePtr(), 4779 LN0->getPointerInfo(), MemVT, 4780 LN0->isVolatile(), LN0->isNonTemporal(), 4781 LN0->getAlignment()); 4782 CombineTo(N, ExtLoad); 4783 CombineTo(N0.getNode(), 4784 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 4785 N0.getValueType(), ExtLoad), 4786 ExtLoad.getValue(1)); 4787 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4788 } 4789 4790 if (N0.getOpcode() == ISD::SETCC) { 4791 // aext(setcc) -> sext_in_reg(vsetcc) for vectors. 4792 // Only do this before legalize for now. 4793 if (VT.isVector() && !LegalOperations) { 4794 EVT N0VT = N0.getOperand(0).getValueType(); 4795 // We know that the # elements of the results is the same as the 4796 // # elements of the compare (and the # elements of the compare result 4797 // for that matter). Check to see that they are the same size. If so, 4798 // we know that the element size of the sext'd result matches the 4799 // element size of the compare operands. 4800 if (VT.getSizeInBits() == N0VT.getSizeInBits()) 4801 return DAG.getSetCC(N->getDebugLoc(), VT, N0.getOperand(0), 4802 N0.getOperand(1), 4803 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 4804 // If the desired elements are smaller or larger than the source 4805 // elements we can use a matching integer vector type and then 4806 // truncate/sign extend 4807 else { 4808 EVT MatchingElementType = 4809 EVT::getIntegerVT(*DAG.getContext(), 4810 N0VT.getScalarType().getSizeInBits()); 4811 EVT MatchingVectorType = 4812 EVT::getVectorVT(*DAG.getContext(), MatchingElementType, 4813 N0VT.getVectorNumElements()); 4814 SDValue VsetCC = 4815 DAG.getSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0), 4816 N0.getOperand(1), 4817 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 4818 return DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT); 4819 } 4820 } 4821 4822 // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 4823 SDValue SCC = 4824 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 4825 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 4826 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 4827 if (SCC.getNode()) 4828 return SCC; 4829 } 4830 4831 return SDValue(); 4832} 4833 4834/// GetDemandedBits - See if the specified operand can be simplified with the 4835/// knowledge that only the bits specified by Mask are used. If so, return the 4836/// simpler operand, otherwise return a null SDValue. 4837SDValue DAGCombiner::GetDemandedBits(SDValue V, const APInt &Mask) { 4838 switch (V.getOpcode()) { 4839 default: break; 4840 case ISD::Constant: { 4841 const ConstantSDNode *CV = cast<ConstantSDNode>(V.getNode()); 4842 assert(CV != 0 && "Const value should be ConstSDNode."); 4843 const APInt &CVal = CV->getAPIntValue(); 4844 APInt NewVal = CVal & Mask; 4845 if (NewVal != CVal) { 4846 return DAG.getConstant(NewVal, V.getValueType()); 4847 } 4848 break; 4849 } 4850 case ISD::OR: 4851 case ISD::XOR: 4852 // If the LHS or RHS don't contribute bits to the or, drop them. 4853 if (DAG.MaskedValueIsZero(V.getOperand(0), Mask)) 4854 return V.getOperand(1); 4855 if (DAG.MaskedValueIsZero(V.getOperand(1), Mask)) 4856 return V.getOperand(0); 4857 break; 4858 case ISD::SRL: 4859 // Only look at single-use SRLs. 4860 if (!V.getNode()->hasOneUse()) 4861 break; 4862 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(V.getOperand(1))) { 4863 // See if we can recursively simplify the LHS. 4864 unsigned Amt = RHSC->getZExtValue(); 4865 4866 // Watch out for shift count overflow though. 4867 if (Amt >= Mask.getBitWidth()) break; 4868 APInt NewMask = Mask << Amt; 4869 SDValue SimplifyLHS = GetDemandedBits(V.getOperand(0), NewMask); 4870 if (SimplifyLHS.getNode()) 4871 return DAG.getNode(ISD::SRL, V.getDebugLoc(), V.getValueType(), 4872 SimplifyLHS, V.getOperand(1)); 4873 } 4874 } 4875 return SDValue(); 4876} 4877 4878/// ReduceLoadWidth - If the result of a wider load is shifted to right of N 4879/// bits and then truncated to a narrower type and where N is a multiple 4880/// of number of bits of the narrower type, transform it to a narrower load 4881/// from address + N / num of bits of new type. If the result is to be 4882/// extended, also fold the extension to form a extending load. 4883SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) { 4884 unsigned Opc = N->getOpcode(); 4885 4886 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD; 4887 SDValue N0 = N->getOperand(0); 4888 EVT VT = N->getValueType(0); 4889 EVT ExtVT = VT; 4890 4891 // This transformation isn't valid for vector loads. 4892 if (VT.isVector()) 4893 return SDValue(); 4894 4895 // Special case: SIGN_EXTEND_INREG is basically truncating to ExtVT then 4896 // extended to VT. 4897 if (Opc == ISD::SIGN_EXTEND_INREG) { 4898 ExtType = ISD::SEXTLOAD; 4899 ExtVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 4900 } else if (Opc == ISD::SRL) { 4901 // Another special-case: SRL is basically zero-extending a narrower value. 4902 ExtType = ISD::ZEXTLOAD; 4903 N0 = SDValue(N, 0); 4904 ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 4905 if (!N01) return SDValue(); 4906 ExtVT = EVT::getIntegerVT(*DAG.getContext(), 4907 VT.getSizeInBits() - N01->getZExtValue()); 4908 } 4909 if (LegalOperations && !TLI.isLoadExtLegal(ExtType, ExtVT)) 4910 return SDValue(); 4911 4912 unsigned EVTBits = ExtVT.getSizeInBits(); 4913 4914 // Do not generate loads of non-round integer types since these can 4915 // be expensive (and would be wrong if the type is not byte sized). 4916 if (!ExtVT.isRound()) 4917 return SDValue(); 4918 4919 unsigned ShAmt = 0; 4920 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) { 4921 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 4922 ShAmt = N01->getZExtValue(); 4923 // Is the shift amount a multiple of size of VT? 4924 if ((ShAmt & (EVTBits-1)) == 0) { 4925 N0 = N0.getOperand(0); 4926 // Is the load width a multiple of size of VT? 4927 if ((N0.getValueType().getSizeInBits() & (EVTBits-1)) != 0) 4928 return SDValue(); 4929 } 4930 4931 // At this point, we must have a load or else we can't do the transform. 4932 if (!isa<LoadSDNode>(N0)) return SDValue(); 4933 4934 // If the shift amount is larger than the input type then we're not 4935 // accessing any of the loaded bytes. If the load was a zextload/extload 4936 // then the result of the shift+trunc is zero/undef (handled elsewhere). 4937 // If the load was a sextload then the result is a splat of the sign bit 4938 // of the extended byte. This is not worth optimizing for. 4939 if (ShAmt >= cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits()) 4940 return SDValue(); 4941 } 4942 } 4943 4944 // If the load is shifted left (and the result isn't shifted back right), 4945 // we can fold the truncate through the shift. 4946 unsigned ShLeftAmt = 0; 4947 if (ShAmt == 0 && N0.getOpcode() == ISD::SHL && N0.hasOneUse() && 4948 ExtVT == VT && TLI.isNarrowingProfitable(N0.getValueType(), VT)) { 4949 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 4950 ShLeftAmt = N01->getZExtValue(); 4951 N0 = N0.getOperand(0); 4952 } 4953 } 4954 4955 // If we haven't found a load, we can't narrow it. Don't transform one with 4956 // multiple uses, this would require adding a new load. 4957 if (!isa<LoadSDNode>(N0) || !N0.hasOneUse() || 4958 // Don't change the width of a volatile load. 4959 cast<LoadSDNode>(N0)->isVolatile()) 4960 return SDValue(); 4961 4962 // Verify that we are actually reducing a load width here. 4963 if (cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits() < EVTBits) 4964 return SDValue(); 4965 4966 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4967 EVT PtrType = N0.getOperand(1).getValueType(); 4968 4969 // For big endian targets, we need to adjust the offset to the pointer to 4970 // load the correct bytes. 4971 if (TLI.isBigEndian()) { 4972 unsigned LVTStoreBits = LN0->getMemoryVT().getStoreSizeInBits(); 4973 unsigned EVTStoreBits = ExtVT.getStoreSizeInBits(); 4974 ShAmt = LVTStoreBits - EVTStoreBits - ShAmt; 4975 } 4976 4977 uint64_t PtrOff = ShAmt / 8; 4978 unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff); 4979 SDValue NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(), 4980 PtrType, LN0->getBasePtr(), 4981 DAG.getConstant(PtrOff, PtrType)); 4982 AddToWorkList(NewPtr.getNode()); 4983 4984 SDValue Load; 4985 if (ExtType == ISD::NON_EXTLOAD) 4986 Load = DAG.getLoad(VT, N0.getDebugLoc(), LN0->getChain(), NewPtr, 4987 LN0->getPointerInfo().getWithOffset(PtrOff), 4988 LN0->isVolatile(), LN0->isNonTemporal(), 4989 LN0->isInvariant(), NewAlign); 4990 else 4991 Load = DAG.getExtLoad(ExtType, N0.getDebugLoc(), VT, LN0->getChain(),NewPtr, 4992 LN0->getPointerInfo().getWithOffset(PtrOff), 4993 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(), 4994 NewAlign); 4995 4996 // Replace the old load's chain with the new load's chain. 4997 WorkListRemover DeadNodes(*this); 4998 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1), 4999 &DeadNodes); 5000 5001 // Shift the result left, if we've swallowed a left shift. 5002 SDValue Result = Load; 5003 if (ShLeftAmt != 0) { 5004 EVT ShImmTy = getShiftAmountTy(Result.getValueType()); 5005 if (!isUIntN(ShImmTy.getSizeInBits(), ShLeftAmt)) 5006 ShImmTy = VT; 5007 Result = DAG.getNode(ISD::SHL, N0.getDebugLoc(), VT, 5008 Result, DAG.getConstant(ShLeftAmt, ShImmTy)); 5009 } 5010 5011 // Return the new loaded value. 5012 return Result; 5013} 5014 5015SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) { 5016 SDValue N0 = N->getOperand(0); 5017 SDValue N1 = N->getOperand(1); 5018 EVT VT = N->getValueType(0); 5019 EVT EVT = cast<VTSDNode>(N1)->getVT(); 5020 unsigned VTBits = VT.getScalarType().getSizeInBits(); 5021 unsigned EVTBits = EVT.getScalarType().getSizeInBits(); 5022 5023 // fold (sext_in_reg c1) -> c1 5024 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF) 5025 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, N0, N1); 5026 5027 // If the input is already sign extended, just drop the extension. 5028 if (DAG.ComputeNumSignBits(N0) >= VTBits-EVTBits+1) 5029 return N0; 5030 5031 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2 5032 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 5033 EVT.bitsLT(cast<VTSDNode>(N0.getOperand(1))->getVT())) { 5034 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, 5035 N0.getOperand(0), N1); 5036 } 5037 5038 // fold (sext_in_reg (sext x)) -> (sext x) 5039 // fold (sext_in_reg (aext x)) -> (sext x) 5040 // if x is small enough. 5041 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) { 5042 SDValue N00 = N0.getOperand(0); 5043 if (N00.getValueType().getScalarType().getSizeInBits() <= EVTBits && 5044 (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND, VT))) 5045 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N00, N1); 5046 } 5047 5048 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero. 5049 if (DAG.MaskedValueIsZero(N0, APInt::getBitsSet(VTBits, EVTBits-1, EVTBits))) 5050 return DAG.getZeroExtendInReg(N0, N->getDebugLoc(), EVT); 5051 5052 // fold operands of sext_in_reg based on knowledge that the top bits are not 5053 // demanded. 5054 if (SimplifyDemandedBits(SDValue(N, 0))) 5055 return SDValue(N, 0); 5056 5057 // fold (sext_in_reg (load x)) -> (smaller sextload x) 5058 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits)) 5059 SDValue NarrowLoad = ReduceLoadWidth(N); 5060 if (NarrowLoad.getNode()) 5061 return NarrowLoad; 5062 5063 // fold (sext_in_reg (srl X, 24), i8) -> (sra X, 24) 5064 // fold (sext_in_reg (srl X, 23), i8) -> (sra X, 23) iff possible. 5065 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above. 5066 if (N0.getOpcode() == ISD::SRL) { 5067 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 5068 if (ShAmt->getZExtValue()+EVTBits <= VTBits) { 5069 // We can turn this into an SRA iff the input to the SRL is already sign 5070 // extended enough. 5071 unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0)); 5072 if (VTBits-(ShAmt->getZExtValue()+EVTBits) < InSignBits) 5073 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, 5074 N0.getOperand(0), N0.getOperand(1)); 5075 } 5076 } 5077 5078 // fold (sext_inreg (extload x)) -> (sextload x) 5079 if (ISD::isEXTLoad(N0.getNode()) && 5080 ISD::isUNINDEXEDLoad(N0.getNode()) && 5081 EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 5082 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 5083 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) { 5084 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 5085 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 5086 LN0->getChain(), 5087 LN0->getBasePtr(), LN0->getPointerInfo(), 5088 EVT, 5089 LN0->isVolatile(), LN0->isNonTemporal(), 5090 LN0->getAlignment()); 5091 CombineTo(N, ExtLoad); 5092 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 5093 return SDValue(N, 0); // Return N so it doesn't get rechecked! 5094 } 5095 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use 5096 if (ISD::isZEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 5097 N0.hasOneUse() && 5098 EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 5099 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 5100 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) { 5101 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 5102 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 5103 LN0->getChain(), 5104 LN0->getBasePtr(), LN0->getPointerInfo(), 5105 EVT, 5106 LN0->isVolatile(), LN0->isNonTemporal(), 5107 LN0->getAlignment()); 5108 CombineTo(N, ExtLoad); 5109 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 5110 return SDValue(N, 0); // Return N so it doesn't get rechecked! 5111 } 5112 5113 // Form (sext_inreg (bswap >> 16)) or (sext_inreg (rotl (bswap) 16)) 5114 if (EVTBits <= 16 && N0.getOpcode() == ISD::OR) { 5115 SDValue BSwap = MatchBSwapHWordLow(N0.getNode(), N0.getOperand(0), 5116 N0.getOperand(1), false); 5117 if (BSwap.getNode() != 0) 5118 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, 5119 BSwap, N1); 5120 } 5121 5122 return SDValue(); 5123} 5124 5125SDValue DAGCombiner::visitTRUNCATE(SDNode *N) { 5126 SDValue N0 = N->getOperand(0); 5127 EVT VT = N->getValueType(0); 5128 bool isLE = TLI.isLittleEndian(); 5129 5130 // noop truncate 5131 if (N0.getValueType() == N->getValueType(0)) 5132 return N0; 5133 // fold (truncate c1) -> c1 5134 if (isa<ConstantSDNode>(N0)) 5135 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0); 5136 // fold (truncate (truncate x)) -> (truncate x) 5137 if (N0.getOpcode() == ISD::TRUNCATE) 5138 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0)); 5139 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x 5140 if (N0.getOpcode() == ISD::ZERO_EXTEND || 5141 N0.getOpcode() == ISD::SIGN_EXTEND || 5142 N0.getOpcode() == ISD::ANY_EXTEND) { 5143 if (N0.getOperand(0).getValueType().bitsLT(VT)) 5144 // if the source is smaller than the dest, we still need an extend 5145 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, 5146 N0.getOperand(0)); 5147 else if (N0.getOperand(0).getValueType().bitsGT(VT)) 5148 // if the source is larger than the dest, than we just need the truncate 5149 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0)); 5150 else 5151 // if the source and dest are the same type, we can drop both the extend 5152 // and the truncate. 5153 return N0.getOperand(0); 5154 } 5155 5156 // Fold extract-and-trunc into a narrow extract. For example: 5157 // i64 x = EXTRACT_VECTOR_ELT(v2i64 val, i32 1) 5158 // i32 y = TRUNCATE(i64 x) 5159 // -- becomes -- 5160 // v16i8 b = BITCAST (v2i64 val) 5161 // i8 x = EXTRACT_VECTOR_ELT(v16i8 b, i32 8) 5162 // 5163 // Note: We only run this optimization after type legalization (which often 5164 // creates this pattern) and before operation legalization after which 5165 // we need to be more careful about the vector instructions that we generate. 5166 if (N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT && 5167 LegalTypes && !LegalOperations && N0->hasOneUse()) { 5168 5169 EVT VecTy = N0.getOperand(0).getValueType(); 5170 EVT ExTy = N0.getValueType(); 5171 EVT TrTy = N->getValueType(0); 5172 5173 unsigned NumElem = VecTy.getVectorNumElements(); 5174 unsigned SizeRatio = ExTy.getSizeInBits()/TrTy.getSizeInBits(); 5175 5176 EVT NVT = EVT::getVectorVT(*DAG.getContext(), TrTy, SizeRatio * NumElem); 5177 assert(NVT.getSizeInBits() == VecTy.getSizeInBits() && "Invalid Size"); 5178 5179 SDValue EltNo = N0->getOperand(1); 5180 if (isa<ConstantSDNode>(EltNo) && isTypeLegal(NVT)) { 5181 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 5182 5183 int Index = isLE ? (Elt*SizeRatio) : (Elt*SizeRatio + (SizeRatio-1)); 5184 5185 SDValue V = DAG.getNode(ISD::BITCAST, N->getDebugLoc(), 5186 NVT, N0.getOperand(0)); 5187 5188 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, 5189 N->getDebugLoc(), TrTy, V, 5190 DAG.getConstant(Index, MVT::i32)); 5191 } 5192 } 5193 5194 // See if we can simplify the input to this truncate through knowledge that 5195 // only the low bits are being used. 5196 // For example "trunc (or (shl x, 8), y)" // -> trunc y 5197 // Currently we only perform this optimization on scalars because vectors 5198 // may have different active low bits. 5199 if (!VT.isVector()) { 5200 SDValue Shorter = 5201 GetDemandedBits(N0, APInt::getLowBitsSet(N0.getValueSizeInBits(), 5202 VT.getSizeInBits())); 5203 if (Shorter.getNode()) 5204 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Shorter); 5205 } 5206 // fold (truncate (load x)) -> (smaller load x) 5207 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits)) 5208 if (!LegalTypes || TLI.isTypeDesirableForOp(N0.getOpcode(), VT)) { 5209 SDValue Reduced = ReduceLoadWidth(N); 5210 if (Reduced.getNode()) 5211 return Reduced; 5212 } 5213 5214 // Simplify the operands using demanded-bits information. 5215 if (!VT.isVector() && 5216 SimplifyDemandedBits(SDValue(N, 0))) 5217 return SDValue(N, 0); 5218 5219 return SDValue(); 5220} 5221 5222static SDNode *getBuildPairElt(SDNode *N, unsigned i) { 5223 SDValue Elt = N->getOperand(i); 5224 if (Elt.getOpcode() != ISD::MERGE_VALUES) 5225 return Elt.getNode(); 5226 return Elt.getOperand(Elt.getResNo()).getNode(); 5227} 5228 5229/// CombineConsecutiveLoads - build_pair (load, load) -> load 5230/// if load locations are consecutive. 5231SDValue DAGCombiner::CombineConsecutiveLoads(SDNode *N, EVT VT) { 5232 assert(N->getOpcode() == ISD::BUILD_PAIR); 5233 5234 LoadSDNode *LD1 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 0)); 5235 LoadSDNode *LD2 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 1)); 5236 if (!LD1 || !LD2 || !ISD::isNON_EXTLoad(LD1) || !LD1->hasOneUse() || 5237 LD1->getPointerInfo().getAddrSpace() != 5238 LD2->getPointerInfo().getAddrSpace()) 5239 return SDValue(); 5240 EVT LD1VT = LD1->getValueType(0); 5241 5242 if (ISD::isNON_EXTLoad(LD2) && 5243 LD2->hasOneUse() && 5244 // If both are volatile this would reduce the number of volatile loads. 5245 // If one is volatile it might be ok, but play conservative and bail out. 5246 !LD1->isVolatile() && 5247 !LD2->isVolatile() && 5248 DAG.isConsecutiveLoad(LD2, LD1, LD1VT.getSizeInBits()/8, 1)) { 5249 unsigned Align = LD1->getAlignment(); 5250 unsigned NewAlign = TLI.getTargetData()-> 5251 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext())); 5252 5253 if (NewAlign <= Align && 5254 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) 5255 return DAG.getLoad(VT, N->getDebugLoc(), LD1->getChain(), 5256 LD1->getBasePtr(), LD1->getPointerInfo(), 5257 false, false, false, Align); 5258 } 5259 5260 return SDValue(); 5261} 5262 5263SDValue DAGCombiner::visitBITCAST(SDNode *N) { 5264 SDValue N0 = N->getOperand(0); 5265 EVT VT = N->getValueType(0); 5266 5267 // If the input is a BUILD_VECTOR with all constant elements, fold this now. 5268 // Only do this before legalize, since afterward the target may be depending 5269 // on the bitconvert. 5270 // First check to see if this is all constant. 5271 if (!LegalTypes && 5272 N0.getOpcode() == ISD::BUILD_VECTOR && N0.getNode()->hasOneUse() && 5273 VT.isVector()) { 5274 bool isSimple = true; 5275 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i) 5276 if (N0.getOperand(i).getOpcode() != ISD::UNDEF && 5277 N0.getOperand(i).getOpcode() != ISD::Constant && 5278 N0.getOperand(i).getOpcode() != ISD::ConstantFP) { 5279 isSimple = false; 5280 break; 5281 } 5282 5283 EVT DestEltVT = N->getValueType(0).getVectorElementType(); 5284 assert(!DestEltVT.isVector() && 5285 "Element type of vector ValueType must not be vector!"); 5286 if (isSimple) 5287 return ConstantFoldBITCASTofBUILD_VECTOR(N0.getNode(), DestEltVT); 5288 } 5289 5290 // If the input is a constant, let getNode fold it. 5291 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) { 5292 SDValue Res = DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, N0); 5293 if (Res.getNode() != N) { 5294 if (!LegalOperations || 5295 TLI.isOperationLegal(Res.getNode()->getOpcode(), VT)) 5296 return Res; 5297 5298 // Folding it resulted in an illegal node, and it's too late to 5299 // do that. Clean up the old node and forego the transformation. 5300 // Ideally this won't happen very often, because instcombine 5301 // and the earlier dagcombine runs (where illegal nodes are 5302 // permitted) should have folded most of them already. 5303 DAG.DeleteNode(Res.getNode()); 5304 } 5305 } 5306 5307 // (conv (conv x, t1), t2) -> (conv x, t2) 5308 if (N0.getOpcode() == ISD::BITCAST) 5309 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, 5310 N0.getOperand(0)); 5311 5312 // fold (conv (load x)) -> (load (conv*)x) 5313 // If the resultant load doesn't need a higher alignment than the original! 5314 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() && 5315 // Do not change the width of a volatile load. 5316 !cast<LoadSDNode>(N0)->isVolatile() && 5317 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) { 5318 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 5319 unsigned Align = TLI.getTargetData()-> 5320 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext())); 5321 unsigned OrigAlign = LN0->getAlignment(); 5322 5323 if (Align <= OrigAlign) { 5324 SDValue Load = DAG.getLoad(VT, N->getDebugLoc(), LN0->getChain(), 5325 LN0->getBasePtr(), LN0->getPointerInfo(), 5326 LN0->isVolatile(), LN0->isNonTemporal(), 5327 LN0->isInvariant(), OrigAlign); 5328 AddToWorkList(N); 5329 CombineTo(N0.getNode(), 5330 DAG.getNode(ISD::BITCAST, N0.getDebugLoc(), 5331 N0.getValueType(), Load), 5332 Load.getValue(1)); 5333 return Load; 5334 } 5335 } 5336 5337 // fold (bitconvert (fneg x)) -> (xor (bitconvert x), signbit) 5338 // fold (bitconvert (fabs x)) -> (and (bitconvert x), (not signbit)) 5339 // This often reduces constant pool loads. 5340 if (((N0.getOpcode() == ISD::FNEG && !TLI.isFNegFree(VT)) || 5341 (N0.getOpcode() == ISD::FABS && !TLI.isFAbsFree(VT))) && 5342 N0.getNode()->hasOneUse() && VT.isInteger() && !VT.isVector()) { 5343 SDValue NewConv = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(), VT, 5344 N0.getOperand(0)); 5345 AddToWorkList(NewConv.getNode()); 5346 5347 APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); 5348 if (N0.getOpcode() == ISD::FNEG) 5349 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, 5350 NewConv, DAG.getConstant(SignBit, VT)); 5351 assert(N0.getOpcode() == ISD::FABS); 5352 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 5353 NewConv, DAG.getConstant(~SignBit, VT)); 5354 } 5355 5356 // fold (bitconvert (fcopysign cst, x)) -> 5357 // (or (and (bitconvert x), sign), (and cst, (not sign))) 5358 // Note that we don't handle (copysign x, cst) because this can always be 5359 // folded to an fneg or fabs. 5360 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse() && 5361 isa<ConstantFPSDNode>(N0.getOperand(0)) && 5362 VT.isInteger() && !VT.isVector()) { 5363 unsigned OrigXWidth = N0.getOperand(1).getValueType().getSizeInBits(); 5364 EVT IntXVT = EVT::getIntegerVT(*DAG.getContext(), OrigXWidth); 5365 if (isTypeLegal(IntXVT)) { 5366 SDValue X = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(), 5367 IntXVT, N0.getOperand(1)); 5368 AddToWorkList(X.getNode()); 5369 5370 // If X has a different width than the result/lhs, sext it or truncate it. 5371 unsigned VTWidth = VT.getSizeInBits(); 5372 if (OrigXWidth < VTWidth) { 5373 X = DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, X); 5374 AddToWorkList(X.getNode()); 5375 } else if (OrigXWidth > VTWidth) { 5376 // To get the sign bit in the right place, we have to shift it right 5377 // before truncating. 5378 X = DAG.getNode(ISD::SRL, X.getDebugLoc(), 5379 X.getValueType(), X, 5380 DAG.getConstant(OrigXWidth-VTWidth, X.getValueType())); 5381 AddToWorkList(X.getNode()); 5382 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X); 5383 AddToWorkList(X.getNode()); 5384 } 5385 5386 APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); 5387 X = DAG.getNode(ISD::AND, X.getDebugLoc(), VT, 5388 X, DAG.getConstant(SignBit, VT)); 5389 AddToWorkList(X.getNode()); 5390 5391 SDValue Cst = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(), 5392 VT, N0.getOperand(0)); 5393 Cst = DAG.getNode(ISD::AND, Cst.getDebugLoc(), VT, 5394 Cst, DAG.getConstant(~SignBit, VT)); 5395 AddToWorkList(Cst.getNode()); 5396 5397 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, X, Cst); 5398 } 5399 } 5400 5401 // bitconvert(build_pair(ld, ld)) -> ld iff load locations are consecutive. 5402 if (N0.getOpcode() == ISD::BUILD_PAIR) { 5403 SDValue CombineLD = CombineConsecutiveLoads(N0.getNode(), VT); 5404 if (CombineLD.getNode()) 5405 return CombineLD; 5406 } 5407 5408 return SDValue(); 5409} 5410 5411SDValue DAGCombiner::visitBUILD_PAIR(SDNode *N) { 5412 EVT VT = N->getValueType(0); 5413 return CombineConsecutiveLoads(N, VT); 5414} 5415 5416/// ConstantFoldBITCASTofBUILD_VECTOR - We know that BV is a build_vector 5417/// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the 5418/// destination element value type. 5419SDValue DAGCombiner:: 5420ConstantFoldBITCASTofBUILD_VECTOR(SDNode *BV, EVT DstEltVT) { 5421 EVT SrcEltVT = BV->getValueType(0).getVectorElementType(); 5422 5423 // If this is already the right type, we're done. 5424 if (SrcEltVT == DstEltVT) return SDValue(BV, 0); 5425 5426 unsigned SrcBitSize = SrcEltVT.getSizeInBits(); 5427 unsigned DstBitSize = DstEltVT.getSizeInBits(); 5428 5429 // If this is a conversion of N elements of one type to N elements of another 5430 // type, convert each element. This handles FP<->INT cases. 5431 if (SrcBitSize == DstBitSize) { 5432 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, 5433 BV->getValueType(0).getVectorNumElements()); 5434 5435 // Due to the FP element handling below calling this routine recursively, 5436 // we can end up with a scalar-to-vector node here. 5437 if (BV->getOpcode() == ISD::SCALAR_TO_VECTOR) 5438 return DAG.getNode(ISD::SCALAR_TO_VECTOR, BV->getDebugLoc(), VT, 5439 DAG.getNode(ISD::BITCAST, BV->getDebugLoc(), 5440 DstEltVT, BV->getOperand(0))); 5441 5442 SmallVector<SDValue, 8> Ops; 5443 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 5444 SDValue Op = BV->getOperand(i); 5445 // If the vector element type is not legal, the BUILD_VECTOR operands 5446 // are promoted and implicitly truncated. Make that explicit here. 5447 if (Op.getValueType() != SrcEltVT) 5448 Op = DAG.getNode(ISD::TRUNCATE, BV->getDebugLoc(), SrcEltVT, Op); 5449 Ops.push_back(DAG.getNode(ISD::BITCAST, BV->getDebugLoc(), 5450 DstEltVT, Op)); 5451 AddToWorkList(Ops.back().getNode()); 5452 } 5453 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 5454 &Ops[0], Ops.size()); 5455 } 5456 5457 // Otherwise, we're growing or shrinking the elements. To avoid having to 5458 // handle annoying details of growing/shrinking FP values, we convert them to 5459 // int first. 5460 if (SrcEltVT.isFloatingPoint()) { 5461 // Convert the input float vector to a int vector where the elements are the 5462 // same sizes. 5463 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!"); 5464 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), SrcEltVT.getSizeInBits()); 5465 BV = ConstantFoldBITCASTofBUILD_VECTOR(BV, IntVT).getNode(); 5466 SrcEltVT = IntVT; 5467 } 5468 5469 // Now we know the input is an integer vector. If the output is a FP type, 5470 // convert to integer first, then to FP of the right size. 5471 if (DstEltVT.isFloatingPoint()) { 5472 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!"); 5473 EVT TmpVT = EVT::getIntegerVT(*DAG.getContext(), DstEltVT.getSizeInBits()); 5474 SDNode *Tmp = ConstantFoldBITCASTofBUILD_VECTOR(BV, TmpVT).getNode(); 5475 5476 // Next, convert to FP elements of the same size. 5477 return ConstantFoldBITCASTofBUILD_VECTOR(Tmp, DstEltVT); 5478 } 5479 5480 // Okay, we know the src/dst types are both integers of differing types. 5481 // Handling growing first. 5482 assert(SrcEltVT.isInteger() && DstEltVT.isInteger()); 5483 if (SrcBitSize < DstBitSize) { 5484 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize; 5485 5486 SmallVector<SDValue, 8> Ops; 5487 for (unsigned i = 0, e = BV->getNumOperands(); i != e; 5488 i += NumInputsPerOutput) { 5489 bool isLE = TLI.isLittleEndian(); 5490 APInt NewBits = APInt(DstBitSize, 0); 5491 bool EltIsUndef = true; 5492 for (unsigned j = 0; j != NumInputsPerOutput; ++j) { 5493 // Shift the previously computed bits over. 5494 NewBits <<= SrcBitSize; 5495 SDValue Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j)); 5496 if (Op.getOpcode() == ISD::UNDEF) continue; 5497 EltIsUndef = false; 5498 5499 NewBits |= cast<ConstantSDNode>(Op)->getAPIntValue(). 5500 zextOrTrunc(SrcBitSize).zext(DstBitSize); 5501 } 5502 5503 if (EltIsUndef) 5504 Ops.push_back(DAG.getUNDEF(DstEltVT)); 5505 else 5506 Ops.push_back(DAG.getConstant(NewBits, DstEltVT)); 5507 } 5508 5509 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, Ops.size()); 5510 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 5511 &Ops[0], Ops.size()); 5512 } 5513 5514 // Finally, this must be the case where we are shrinking elements: each input 5515 // turns into multiple outputs. 5516 bool isS2V = ISD::isScalarToVector(BV); 5517 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize; 5518 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, 5519 NumOutputsPerInput*BV->getNumOperands()); 5520 SmallVector<SDValue, 8> Ops; 5521 5522 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 5523 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) { 5524 for (unsigned j = 0; j != NumOutputsPerInput; ++j) 5525 Ops.push_back(DAG.getUNDEF(DstEltVT)); 5526 continue; 5527 } 5528 5529 APInt OpVal = cast<ConstantSDNode>(BV->getOperand(i))-> 5530 getAPIntValue().zextOrTrunc(SrcBitSize); 5531 5532 for (unsigned j = 0; j != NumOutputsPerInput; ++j) { 5533 APInt ThisVal = OpVal.trunc(DstBitSize); 5534 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT)); 5535 if (isS2V && i == 0 && j == 0 && ThisVal.zext(SrcBitSize) == OpVal) 5536 // Simply turn this into a SCALAR_TO_VECTOR of the new type. 5537 return DAG.getNode(ISD::SCALAR_TO_VECTOR, BV->getDebugLoc(), VT, 5538 Ops[0]); 5539 OpVal = OpVal.lshr(DstBitSize); 5540 } 5541 5542 // For big endian targets, swap the order of the pieces of each element. 5543 if (TLI.isBigEndian()) 5544 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end()); 5545 } 5546 5547 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 5548 &Ops[0], Ops.size()); 5549} 5550 5551SDValue DAGCombiner::visitFADD(SDNode *N) { 5552 SDValue N0 = N->getOperand(0); 5553 SDValue N1 = N->getOperand(1); 5554 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5555 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 5556 EVT VT = N->getValueType(0); 5557 5558 // fold vector ops 5559 if (VT.isVector()) { 5560 SDValue FoldedVOp = SimplifyVBinOp(N); 5561 if (FoldedVOp.getNode()) return FoldedVOp; 5562 } 5563 5564 // fold (fadd c1, c2) -> (fadd c1, c2) 5565 if (N0CFP && N1CFP && VT != MVT::ppcf128) 5566 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N1); 5567 // canonicalize constant to RHS 5568 if (N0CFP && !N1CFP) 5569 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N1, N0); 5570 // fold (fadd A, 0) -> A 5571 if (DAG.getTarget().Options.UnsafeFPMath && N1CFP && 5572 N1CFP->getValueAPF().isZero()) 5573 return N0; 5574 // fold (fadd A, (fneg B)) -> (fsub A, B) 5575 if ((!LegalOperations || TLI.isOperationLegalOrCustom(ISD::FSUB, VT)) && 5576 isNegatibleForFree(N1, LegalOperations, TLI, &DAG.getTarget().Options) == 2) 5577 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, 5578 GetNegatedExpression(N1, DAG, LegalOperations)); 5579 // fold (fadd (fneg A), B) -> (fsub B, A) 5580 if ((!LegalOperations || TLI.isOperationLegalOrCustom(ISD::FSUB, VT)) && 5581 isNegatibleForFree(N0, LegalOperations, TLI, &DAG.getTarget().Options) == 2) 5582 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N1, 5583 GetNegatedExpression(N0, DAG, LegalOperations)); 5584 5585 // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2)) 5586 if (DAG.getTarget().Options.UnsafeFPMath && N1CFP && 5587 N0.getOpcode() == ISD::FADD && N0.getNode()->hasOneUse() && 5588 isa<ConstantFPSDNode>(N0.getOperand(1))) 5589 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0.getOperand(0), 5590 DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, 5591 N0.getOperand(1), N1)); 5592 5593 return SDValue(); 5594} 5595 5596SDValue DAGCombiner::visitFSUB(SDNode *N) { 5597 SDValue N0 = N->getOperand(0); 5598 SDValue N1 = N->getOperand(1); 5599 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5600 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 5601 EVT VT = N->getValueType(0); 5602 5603 // fold vector ops 5604 if (VT.isVector()) { 5605 SDValue FoldedVOp = SimplifyVBinOp(N); 5606 if (FoldedVOp.getNode()) return FoldedVOp; 5607 } 5608 5609 // fold (fsub c1, c2) -> c1-c2 5610 if (N0CFP && N1CFP && VT != MVT::ppcf128) 5611 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, N1); 5612 // fold (fsub A, 0) -> A 5613 if (DAG.getTarget().Options.UnsafeFPMath && 5614 N1CFP && N1CFP->getValueAPF().isZero()) 5615 return N0; 5616 // fold (fsub 0, B) -> -B 5617 if (DAG.getTarget().Options.UnsafeFPMath && 5618 N0CFP && N0CFP->getValueAPF().isZero()) { 5619 if (isNegatibleForFree(N1, LegalOperations, TLI, &DAG.getTarget().Options)) 5620 return GetNegatedExpression(N1, DAG, LegalOperations); 5621 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 5622 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N1); 5623 } 5624 // fold (fsub A, (fneg B)) -> (fadd A, B) 5625 if (isNegatibleForFree(N1, LegalOperations, TLI, &DAG.getTarget().Options)) 5626 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, 5627 GetNegatedExpression(N1, DAG, LegalOperations)); 5628 5629 // If 'unsafe math' is enabled, fold 5630 // (fsub x, (fadd x, y)) -> (fneg y) & 5631 // (fsub x, (fadd y, x)) -> (fneg y) 5632 if (DAG.getTarget().Options.UnsafeFPMath) { 5633 if (N1.getOpcode() == ISD::FADD) { 5634 SDValue N10 = N1->getOperand(0); 5635 SDValue N11 = N1->getOperand(1); 5636 5637 if (N10 == N0 && isNegatibleForFree(N11, LegalOperations, TLI, 5638 &DAG.getTarget().Options)) 5639 return GetNegatedExpression(N11, DAG, LegalOperations); 5640 else if (N11 == N0 && isNegatibleForFree(N10, LegalOperations, TLI, 5641 &DAG.getTarget().Options)) 5642 return GetNegatedExpression(N10, DAG, LegalOperations); 5643 } 5644 } 5645 5646 return SDValue(); 5647} 5648 5649SDValue DAGCombiner::visitFMUL(SDNode *N) { 5650 SDValue N0 = N->getOperand(0); 5651 SDValue N1 = N->getOperand(1); 5652 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5653 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 5654 EVT VT = N->getValueType(0); 5655 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 5656 5657 // fold vector ops 5658 if (VT.isVector()) { 5659 SDValue FoldedVOp = SimplifyVBinOp(N); 5660 if (FoldedVOp.getNode()) return FoldedVOp; 5661 } 5662 5663 // fold (fmul c1, c2) -> c1*c2 5664 if (N0CFP && N1CFP && VT != MVT::ppcf128) 5665 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0, N1); 5666 // canonicalize constant to RHS 5667 if (N0CFP && !N1CFP) 5668 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N1, N0); 5669 // fold (fmul A, 0) -> 0 5670 if (DAG.getTarget().Options.UnsafeFPMath && 5671 N1CFP && N1CFP->getValueAPF().isZero()) 5672 return N1; 5673 // fold (fmul A, 0) -> 0, vector edition. 5674 if (DAG.getTarget().Options.UnsafeFPMath && 5675 ISD::isBuildVectorAllZeros(N1.getNode())) 5676 return N1; 5677 // fold (fmul X, 2.0) -> (fadd X, X) 5678 if (N1CFP && N1CFP->isExactlyValue(+2.0)) 5679 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N0); 5680 // fold (fmul X, -1.0) -> (fneg X) 5681 if (N1CFP && N1CFP->isExactlyValue(-1.0)) 5682 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 5683 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N0); 5684 5685 // fold (fmul (fneg X), (fneg Y)) -> (fmul X, Y) 5686 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations, TLI, 5687 &DAG.getTarget().Options)) { 5688 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations, TLI, 5689 &DAG.getTarget().Options)) { 5690 // Both can be negated for free, check to see if at least one is cheaper 5691 // negated. 5692 if (LHSNeg == 2 || RHSNeg == 2) 5693 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 5694 GetNegatedExpression(N0, DAG, LegalOperations), 5695 GetNegatedExpression(N1, DAG, LegalOperations)); 5696 } 5697 } 5698 5699 // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2)) 5700 if (DAG.getTarget().Options.UnsafeFPMath && 5701 N1CFP && N0.getOpcode() == ISD::FMUL && 5702 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 5703 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0.getOperand(0), 5704 DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 5705 N0.getOperand(1), N1)); 5706 5707 return SDValue(); 5708} 5709 5710SDValue DAGCombiner::visitFDIV(SDNode *N) { 5711 SDValue N0 = N->getOperand(0); 5712 SDValue N1 = N->getOperand(1); 5713 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5714 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 5715 EVT VT = N->getValueType(0); 5716 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 5717 5718 // fold vector ops 5719 if (VT.isVector()) { 5720 SDValue FoldedVOp = SimplifyVBinOp(N); 5721 if (FoldedVOp.getNode()) return FoldedVOp; 5722 } 5723 5724 // fold (fdiv c1, c2) -> c1/c2 5725 if (N0CFP && N1CFP && VT != MVT::ppcf128) 5726 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, N0, N1); 5727 5728 // fold (fdiv X, c2) -> fmul X, 1/c2 if there is no precision loss or if 5729 // losing precision is acceptable. 5730 if (N1CFP && VT != MVT::ppcf128) { 5731 // Compute the reciprocal 1.0 / c2. 5732 APFloat N1APF = N1CFP->getValueAPF(); 5733 APFloat Recip(N1APF.getSemantics(), 1); // 1.0 5734 APFloat::opStatus st = Recip.divide(N1APF, APFloat::rmNearestTiesToEven); 5735 // Only do the transform if the reciprocal is not too horrible (eg not NaN). 5736 if (st == APFloat::opOK || (st == APFloat::opInexact && 5737 DAG.getTarget().Options.UnsafeFPMath)) 5738 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0, 5739 DAG.getConstantFP(Recip, VT)); 5740 } 5741 5742 // (fdiv (fneg X), (fneg Y)) -> (fdiv X, Y) 5743 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations, TLI, 5744 &DAG.getTarget().Options)) { 5745 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations, TLI, 5746 &DAG.getTarget().Options)) { 5747 // Both can be negated for free, check to see if at least one is cheaper 5748 // negated. 5749 if (LHSNeg == 2 || RHSNeg == 2) 5750 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, 5751 GetNegatedExpression(N0, DAG, LegalOperations), 5752 GetNegatedExpression(N1, DAG, LegalOperations)); 5753 } 5754 } 5755 5756 return SDValue(); 5757} 5758 5759SDValue DAGCombiner::visitFREM(SDNode *N) { 5760 SDValue N0 = N->getOperand(0); 5761 SDValue N1 = N->getOperand(1); 5762 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5763 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 5764 EVT VT = N->getValueType(0); 5765 5766 // fold (frem c1, c2) -> fmod(c1,c2) 5767 if (N0CFP && N1CFP && VT != MVT::ppcf128) 5768 return DAG.getNode(ISD::FREM, N->getDebugLoc(), VT, N0, N1); 5769 5770 return SDValue(); 5771} 5772 5773SDValue DAGCombiner::visitFCOPYSIGN(SDNode *N) { 5774 SDValue N0 = N->getOperand(0); 5775 SDValue N1 = N->getOperand(1); 5776 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5777 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 5778 EVT VT = N->getValueType(0); 5779 5780 if (N0CFP && N1CFP && VT != MVT::ppcf128) // Constant fold 5781 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, N0, N1); 5782 5783 if (N1CFP) { 5784 const APFloat& V = N1CFP->getValueAPF(); 5785 // copysign(x, c1) -> fabs(x) iff ispos(c1) 5786 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1) 5787 if (!V.isNegative()) { 5788 if (!LegalOperations || TLI.isOperationLegal(ISD::FABS, VT)) 5789 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 5790 } else { 5791 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 5792 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, 5793 DAG.getNode(ISD::FABS, N0.getDebugLoc(), VT, N0)); 5794 } 5795 } 5796 5797 // copysign(fabs(x), y) -> copysign(x, y) 5798 // copysign(fneg(x), y) -> copysign(x, y) 5799 // copysign(copysign(x,z), y) -> copysign(x, y) 5800 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG || 5801 N0.getOpcode() == ISD::FCOPYSIGN) 5802 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 5803 N0.getOperand(0), N1); 5804 5805 // copysign(x, abs(y)) -> abs(x) 5806 if (N1.getOpcode() == ISD::FABS) 5807 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 5808 5809 // copysign(x, copysign(y,z)) -> copysign(x, z) 5810 if (N1.getOpcode() == ISD::FCOPYSIGN) 5811 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 5812 N0, N1.getOperand(1)); 5813 5814 // copysign(x, fp_extend(y)) -> copysign(x, y) 5815 // copysign(x, fp_round(y)) -> copysign(x, y) 5816 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND) 5817 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 5818 N0, N1.getOperand(0)); 5819 5820 return SDValue(); 5821} 5822 5823SDValue DAGCombiner::visitSINT_TO_FP(SDNode *N) { 5824 SDValue N0 = N->getOperand(0); 5825 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 5826 EVT VT = N->getValueType(0); 5827 EVT OpVT = N0.getValueType(); 5828 5829 // fold (sint_to_fp c1) -> c1fp 5830 if (N0C && OpVT != MVT::ppcf128 && 5831 // ...but only if the target supports immediate floating-point values 5832 (!LegalOperations || 5833 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT))) 5834 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0); 5835 5836 // If the input is a legal type, and SINT_TO_FP is not legal on this target, 5837 // but UINT_TO_FP is legal on this target, try to convert. 5838 if (!TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT) && 5839 TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT)) { 5840 // If the sign bit is known to be zero, we can change this to UINT_TO_FP. 5841 if (DAG.SignBitIsZero(N0)) 5842 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0); 5843 } 5844 5845 return SDValue(); 5846} 5847 5848SDValue DAGCombiner::visitUINT_TO_FP(SDNode *N) { 5849 SDValue N0 = N->getOperand(0); 5850 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 5851 EVT VT = N->getValueType(0); 5852 EVT OpVT = N0.getValueType(); 5853 5854 // fold (uint_to_fp c1) -> c1fp 5855 if (N0C && OpVT != MVT::ppcf128 && 5856 // ...but only if the target supports immediate floating-point values 5857 (!LegalOperations || 5858 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT))) 5859 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0); 5860 5861 // If the input is a legal type, and UINT_TO_FP is not legal on this target, 5862 // but SINT_TO_FP is legal on this target, try to convert. 5863 if (!TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT) && 5864 TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT)) { 5865 // If the sign bit is known to be zero, we can change this to SINT_TO_FP. 5866 if (DAG.SignBitIsZero(N0)) 5867 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0); 5868 } 5869 5870 return SDValue(); 5871} 5872 5873SDValue DAGCombiner::visitFP_TO_SINT(SDNode *N) { 5874 SDValue N0 = N->getOperand(0); 5875 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5876 EVT VT = N->getValueType(0); 5877 5878 // fold (fp_to_sint c1fp) -> c1 5879 if (N0CFP) 5880 return DAG.getNode(ISD::FP_TO_SINT, N->getDebugLoc(), VT, N0); 5881 5882 return SDValue(); 5883} 5884 5885SDValue DAGCombiner::visitFP_TO_UINT(SDNode *N) { 5886 SDValue N0 = N->getOperand(0); 5887 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5888 EVT VT = N->getValueType(0); 5889 5890 // fold (fp_to_uint c1fp) -> c1 5891 if (N0CFP && VT != MVT::ppcf128) 5892 return DAG.getNode(ISD::FP_TO_UINT, N->getDebugLoc(), VT, N0); 5893 5894 return SDValue(); 5895} 5896 5897SDValue DAGCombiner::visitFP_ROUND(SDNode *N) { 5898 SDValue N0 = N->getOperand(0); 5899 SDValue N1 = N->getOperand(1); 5900 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5901 EVT VT = N->getValueType(0); 5902 5903 // fold (fp_round c1fp) -> c1fp 5904 if (N0CFP && N0.getValueType() != MVT::ppcf128) 5905 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0, N1); 5906 5907 // fold (fp_round (fp_extend x)) -> x 5908 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType()) 5909 return N0.getOperand(0); 5910 5911 // fold (fp_round (fp_round x)) -> (fp_round x) 5912 if (N0.getOpcode() == ISD::FP_ROUND) { 5913 // This is a value preserving truncation if both round's are. 5914 bool IsTrunc = N->getConstantOperandVal(1) == 1 && 5915 N0.getNode()->getConstantOperandVal(1) == 1; 5916 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0.getOperand(0), 5917 DAG.getIntPtrConstant(IsTrunc)); 5918 } 5919 5920 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y) 5921 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse()) { 5922 SDValue Tmp = DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(), VT, 5923 N0.getOperand(0), N1); 5924 AddToWorkList(Tmp.getNode()); 5925 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 5926 Tmp, N0.getOperand(1)); 5927 } 5928 5929 return SDValue(); 5930} 5931 5932SDValue DAGCombiner::visitFP_ROUND_INREG(SDNode *N) { 5933 SDValue N0 = N->getOperand(0); 5934 EVT VT = N->getValueType(0); 5935 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 5936 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5937 5938 // fold (fp_round_inreg c1fp) -> c1fp 5939 if (N0CFP && isTypeLegal(EVT)) { 5940 SDValue Round = DAG.getConstantFP(*N0CFP->getConstantFPValue(), EVT); 5941 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, Round); 5942 } 5943 5944 return SDValue(); 5945} 5946 5947SDValue DAGCombiner::visitFP_EXTEND(SDNode *N) { 5948 SDValue N0 = N->getOperand(0); 5949 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5950 EVT VT = N->getValueType(0); 5951 5952 // If this is fp_round(fpextend), don't fold it, allow ourselves to be folded. 5953 if (N->hasOneUse() && 5954 N->use_begin()->getOpcode() == ISD::FP_ROUND) 5955 return SDValue(); 5956 5957 // fold (fp_extend c1fp) -> c1fp 5958 if (N0CFP && VT != MVT::ppcf128) 5959 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, N0); 5960 5961 // Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't affect the 5962 // value of X. 5963 if (N0.getOpcode() == ISD::FP_ROUND 5964 && N0.getNode()->getConstantOperandVal(1) == 1) { 5965 SDValue In = N0.getOperand(0); 5966 if (In.getValueType() == VT) return In; 5967 if (VT.bitsLT(In.getValueType())) 5968 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, 5969 In, N0.getOperand(1)); 5970 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, In); 5971 } 5972 5973 // fold (fpext (load x)) -> (fpext (fptrunc (extload x))) 5974 if (ISD::isNON_EXTLoad(N0.getNode()) && N0.hasOneUse() && 5975 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 5976 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) { 5977 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 5978 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT, 5979 LN0->getChain(), 5980 LN0->getBasePtr(), LN0->getPointerInfo(), 5981 N0.getValueType(), 5982 LN0->isVolatile(), LN0->isNonTemporal(), 5983 LN0->getAlignment()); 5984 CombineTo(N, ExtLoad); 5985 CombineTo(N0.getNode(), 5986 DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(), 5987 N0.getValueType(), ExtLoad, DAG.getIntPtrConstant(1)), 5988 ExtLoad.getValue(1)); 5989 return SDValue(N, 0); // Return N so it doesn't get rechecked! 5990 } 5991 5992 return SDValue(); 5993} 5994 5995SDValue DAGCombiner::visitFNEG(SDNode *N) { 5996 SDValue N0 = N->getOperand(0); 5997 EVT VT = N->getValueType(0); 5998 5999 if (isNegatibleForFree(N0, LegalOperations, DAG.getTargetLoweringInfo(), 6000 &DAG.getTarget().Options)) 6001 return GetNegatedExpression(N0, DAG, LegalOperations); 6002 6003 // Transform fneg(bitconvert(x)) -> bitconvert(x^sign) to avoid loading 6004 // constant pool values. 6005 if (!TLI.isFNegFree(VT) && N0.getOpcode() == ISD::BITCAST && 6006 !VT.isVector() && 6007 N0.getNode()->hasOneUse() && 6008 N0.getOperand(0).getValueType().isInteger()) { 6009 SDValue Int = N0.getOperand(0); 6010 EVT IntVT = Int.getValueType(); 6011 if (IntVT.isInteger() && !IntVT.isVector()) { 6012 Int = DAG.getNode(ISD::XOR, N0.getDebugLoc(), IntVT, Int, 6013 DAG.getConstant(APInt::getSignBit(IntVT.getSizeInBits()), IntVT)); 6014 AddToWorkList(Int.getNode()); 6015 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), 6016 VT, Int); 6017 } 6018 } 6019 6020 return SDValue(); 6021} 6022 6023SDValue DAGCombiner::visitFABS(SDNode *N) { 6024 SDValue N0 = N->getOperand(0); 6025 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6026 EVT VT = N->getValueType(0); 6027 6028 // fold (fabs c1) -> fabs(c1) 6029 if (N0CFP && VT != MVT::ppcf128) 6030 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 6031 // fold (fabs (fabs x)) -> (fabs x) 6032 if (N0.getOpcode() == ISD::FABS) 6033 return N->getOperand(0); 6034 // fold (fabs (fneg x)) -> (fabs x) 6035 // fold (fabs (fcopysign x, y)) -> (fabs x) 6036 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN) 6037 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0.getOperand(0)); 6038 6039 // Transform fabs(bitconvert(x)) -> bitconvert(x&~sign) to avoid loading 6040 // constant pool values. 6041 if (!TLI.isFAbsFree(VT) && 6042 N0.getOpcode() == ISD::BITCAST && N0.getNode()->hasOneUse() && 6043 N0.getOperand(0).getValueType().isInteger() && 6044 !N0.getOperand(0).getValueType().isVector()) { 6045 SDValue Int = N0.getOperand(0); 6046 EVT IntVT = Int.getValueType(); 6047 if (IntVT.isInteger() && !IntVT.isVector()) { 6048 Int = DAG.getNode(ISD::AND, N0.getDebugLoc(), IntVT, Int, 6049 DAG.getConstant(~APInt::getSignBit(IntVT.getSizeInBits()), IntVT)); 6050 AddToWorkList(Int.getNode()); 6051 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), 6052 N->getValueType(0), Int); 6053 } 6054 } 6055 6056 return SDValue(); 6057} 6058 6059SDValue DAGCombiner::visitBRCOND(SDNode *N) { 6060 SDValue Chain = N->getOperand(0); 6061 SDValue N1 = N->getOperand(1); 6062 SDValue N2 = N->getOperand(2); 6063 6064 // If N is a constant we could fold this into a fallthrough or unconditional 6065 // branch. However that doesn't happen very often in normal code, because 6066 // Instcombine/SimplifyCFG should have handled the available opportunities. 6067 // If we did this folding here, it would be necessary to update the 6068 // MachineBasicBlock CFG, which is awkward. 6069 6070 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal 6071 // on the target. 6072 if (N1.getOpcode() == ISD::SETCC && 6073 TLI.isOperationLegalOrCustom(ISD::BR_CC, MVT::Other)) { 6074 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other, 6075 Chain, N1.getOperand(2), 6076 N1.getOperand(0), N1.getOperand(1), N2); 6077 } 6078 6079 if ((N1.hasOneUse() && N1.getOpcode() == ISD::SRL) || 6080 ((N1.getOpcode() == ISD::TRUNCATE && N1.hasOneUse()) && 6081 (N1.getOperand(0).hasOneUse() && 6082 N1.getOperand(0).getOpcode() == ISD::SRL))) { 6083 SDNode *Trunc = 0; 6084 if (N1.getOpcode() == ISD::TRUNCATE) { 6085 // Look pass the truncate. 6086 Trunc = N1.getNode(); 6087 N1 = N1.getOperand(0); 6088 } 6089 6090 // Match this pattern so that we can generate simpler code: 6091 // 6092 // %a = ... 6093 // %b = and i32 %a, 2 6094 // %c = srl i32 %b, 1 6095 // brcond i32 %c ... 6096 // 6097 // into 6098 // 6099 // %a = ... 6100 // %b = and i32 %a, 2 6101 // %c = setcc eq %b, 0 6102 // brcond %c ... 6103 // 6104 // This applies only when the AND constant value has one bit set and the 6105 // SRL constant is equal to the log2 of the AND constant. The back-end is 6106 // smart enough to convert the result into a TEST/JMP sequence. 6107 SDValue Op0 = N1.getOperand(0); 6108 SDValue Op1 = N1.getOperand(1); 6109 6110 if (Op0.getOpcode() == ISD::AND && 6111 Op1.getOpcode() == ISD::Constant) { 6112 SDValue AndOp1 = Op0.getOperand(1); 6113 6114 if (AndOp1.getOpcode() == ISD::Constant) { 6115 const APInt &AndConst = cast<ConstantSDNode>(AndOp1)->getAPIntValue(); 6116 6117 if (AndConst.isPowerOf2() && 6118 cast<ConstantSDNode>(Op1)->getAPIntValue()==AndConst.logBase2()) { 6119 SDValue SetCC = 6120 DAG.getSetCC(N->getDebugLoc(), 6121 TLI.getSetCCResultType(Op0.getValueType()), 6122 Op0, DAG.getConstant(0, Op0.getValueType()), 6123 ISD::SETNE); 6124 6125 SDValue NewBRCond = DAG.getNode(ISD::BRCOND, N->getDebugLoc(), 6126 MVT::Other, Chain, SetCC, N2); 6127 // Don't add the new BRCond into the worklist or else SimplifySelectCC 6128 // will convert it back to (X & C1) >> C2. 6129 CombineTo(N, NewBRCond, false); 6130 // Truncate is dead. 6131 if (Trunc) { 6132 removeFromWorkList(Trunc); 6133 DAG.DeleteNode(Trunc); 6134 } 6135 // Replace the uses of SRL with SETCC 6136 WorkListRemover DeadNodes(*this); 6137 DAG.ReplaceAllUsesOfValueWith(N1, SetCC, &DeadNodes); 6138 removeFromWorkList(N1.getNode()); 6139 DAG.DeleteNode(N1.getNode()); 6140 return SDValue(N, 0); // Return N so it doesn't get rechecked! 6141 } 6142 } 6143 } 6144 6145 if (Trunc) 6146 // Restore N1 if the above transformation doesn't match. 6147 N1 = N->getOperand(1); 6148 } 6149 6150 // Transform br(xor(x, y)) -> br(x != y) 6151 // Transform br(xor(xor(x,y), 1)) -> br (x == y) 6152 if (N1.hasOneUse() && N1.getOpcode() == ISD::XOR) { 6153 SDNode *TheXor = N1.getNode(); 6154 SDValue Op0 = TheXor->getOperand(0); 6155 SDValue Op1 = TheXor->getOperand(1); 6156 if (Op0.getOpcode() == Op1.getOpcode()) { 6157 // Avoid missing important xor optimizations. 6158 SDValue Tmp = visitXOR(TheXor); 6159 if (Tmp.getNode() && Tmp.getNode() != TheXor) { 6160 DEBUG(dbgs() << "\nReplacing.8 "; 6161 TheXor->dump(&DAG); 6162 dbgs() << "\nWith: "; 6163 Tmp.getNode()->dump(&DAG); 6164 dbgs() << '\n'); 6165 WorkListRemover DeadNodes(*this); 6166 DAG.ReplaceAllUsesOfValueWith(N1, Tmp, &DeadNodes); 6167 removeFromWorkList(TheXor); 6168 DAG.DeleteNode(TheXor); 6169 return DAG.getNode(ISD::BRCOND, N->getDebugLoc(), 6170 MVT::Other, Chain, Tmp, N2); 6171 } 6172 } 6173 6174 if (Op0.getOpcode() != ISD::SETCC && Op1.getOpcode() != ISD::SETCC) { 6175 bool Equal = false; 6176 if (ConstantSDNode *RHSCI = dyn_cast<ConstantSDNode>(Op0)) 6177 if (RHSCI->getAPIntValue() == 1 && Op0.hasOneUse() && 6178 Op0.getOpcode() == ISD::XOR) { 6179 TheXor = Op0.getNode(); 6180 Equal = true; 6181 } 6182 6183 EVT SetCCVT = N1.getValueType(); 6184 if (LegalTypes) 6185 SetCCVT = TLI.getSetCCResultType(SetCCVT); 6186 SDValue SetCC = DAG.getSetCC(TheXor->getDebugLoc(), 6187 SetCCVT, 6188 Op0, Op1, 6189 Equal ? ISD::SETEQ : ISD::SETNE); 6190 // Replace the uses of XOR with SETCC 6191 WorkListRemover DeadNodes(*this); 6192 DAG.ReplaceAllUsesOfValueWith(N1, SetCC, &DeadNodes); 6193 removeFromWorkList(N1.getNode()); 6194 DAG.DeleteNode(N1.getNode()); 6195 return DAG.getNode(ISD::BRCOND, N->getDebugLoc(), 6196 MVT::Other, Chain, SetCC, N2); 6197 } 6198 } 6199 6200 return SDValue(); 6201} 6202 6203// Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB. 6204// 6205SDValue DAGCombiner::visitBR_CC(SDNode *N) { 6206 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1)); 6207 SDValue CondLHS = N->getOperand(2), CondRHS = N->getOperand(3); 6208 6209 // If N is a constant we could fold this into a fallthrough or unconditional 6210 // branch. However that doesn't happen very often in normal code, because 6211 // Instcombine/SimplifyCFG should have handled the available opportunities. 6212 // If we did this folding here, it would be necessary to update the 6213 // MachineBasicBlock CFG, which is awkward. 6214 6215 // Use SimplifySetCC to simplify SETCC's. 6216 SDValue Simp = SimplifySetCC(TLI.getSetCCResultType(CondLHS.getValueType()), 6217 CondLHS, CondRHS, CC->get(), N->getDebugLoc(), 6218 false); 6219 if (Simp.getNode()) AddToWorkList(Simp.getNode()); 6220 6221 // fold to a simpler setcc 6222 if (Simp.getNode() && Simp.getOpcode() == ISD::SETCC) 6223 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other, 6224 N->getOperand(0), Simp.getOperand(2), 6225 Simp.getOperand(0), Simp.getOperand(1), 6226 N->getOperand(4)); 6227 6228 return SDValue(); 6229} 6230 6231/// canFoldInAddressingMode - Return true if 'Use' is a load or a store that 6232/// uses N as its base pointer and that N may be folded in the load / store 6233/// addressing mode. 6234static bool canFoldInAddressingMode(SDNode *N, SDNode *Use, 6235 SelectionDAG &DAG, 6236 const TargetLowering &TLI) { 6237 EVT VT; 6238 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Use)) { 6239 if (LD->isIndexed() || LD->getBasePtr().getNode() != N) 6240 return false; 6241 VT = Use->getValueType(0); 6242 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(Use)) { 6243 if (ST->isIndexed() || ST->getBasePtr().getNode() != N) 6244 return false; 6245 VT = ST->getValue().getValueType(); 6246 } else 6247 return false; 6248 6249 TargetLowering::AddrMode AM; 6250 if (N->getOpcode() == ISD::ADD) { 6251 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1)); 6252 if (Offset) 6253 // [reg +/- imm] 6254 AM.BaseOffs = Offset->getSExtValue(); 6255 else 6256 // [reg +/- reg] 6257 AM.Scale = 1; 6258 } else if (N->getOpcode() == ISD::SUB) { 6259 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1)); 6260 if (Offset) 6261 // [reg +/- imm] 6262 AM.BaseOffs = -Offset->getSExtValue(); 6263 else 6264 // [reg +/- reg] 6265 AM.Scale = 1; 6266 } else 6267 return false; 6268 6269 return TLI.isLegalAddressingMode(AM, VT.getTypeForEVT(*DAG.getContext())); 6270} 6271 6272/// CombineToPreIndexedLoadStore - Try turning a load / store into a 6273/// pre-indexed load / store when the base pointer is an add or subtract 6274/// and it has other uses besides the load / store. After the 6275/// transformation, the new indexed load / store has effectively folded 6276/// the add / subtract in and all of its other uses are redirected to the 6277/// new load / store. 6278bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) { 6279 if (Level < AfterLegalizeDAG) 6280 return false; 6281 6282 bool isLoad = true; 6283 SDValue Ptr; 6284 EVT VT; 6285 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 6286 if (LD->isIndexed()) 6287 return false; 6288 VT = LD->getMemoryVT(); 6289 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) && 6290 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT)) 6291 return false; 6292 Ptr = LD->getBasePtr(); 6293 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 6294 if (ST->isIndexed()) 6295 return false; 6296 VT = ST->getMemoryVT(); 6297 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) && 6298 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT)) 6299 return false; 6300 Ptr = ST->getBasePtr(); 6301 isLoad = false; 6302 } else { 6303 return false; 6304 } 6305 6306 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail 6307 // out. There is no reason to make this a preinc/predec. 6308 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) || 6309 Ptr.getNode()->hasOneUse()) 6310 return false; 6311 6312 // Ask the target to do addressing mode selection. 6313 SDValue BasePtr; 6314 SDValue Offset; 6315 ISD::MemIndexedMode AM = ISD::UNINDEXED; 6316 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG)) 6317 return false; 6318 // Don't create a indexed load / store with zero offset. 6319 if (isa<ConstantSDNode>(Offset) && 6320 cast<ConstantSDNode>(Offset)->isNullValue()) 6321 return false; 6322 6323 // Try turning it into a pre-indexed load / store except when: 6324 // 1) The new base ptr is a frame index. 6325 // 2) If N is a store and the new base ptr is either the same as or is a 6326 // predecessor of the value being stored. 6327 // 3) Another use of old base ptr is a predecessor of N. If ptr is folded 6328 // that would create a cycle. 6329 // 4) All uses are load / store ops that use it as old base ptr. 6330 6331 // Check #1. Preinc'ing a frame index would require copying the stack pointer 6332 // (plus the implicit offset) to a register to preinc anyway. 6333 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr)) 6334 return false; 6335 6336 // Check #2. 6337 if (!isLoad) { 6338 SDValue Val = cast<StoreSDNode>(N)->getValue(); 6339 if (Val == BasePtr || BasePtr.getNode()->isPredecessorOf(Val.getNode())) 6340 return false; 6341 } 6342 6343 // Now check for #3 and #4. 6344 bool RealUse = false; 6345 6346 // Caches for hasPredecessorHelper 6347 SmallPtrSet<const SDNode *, 32> Visited; 6348 SmallVector<const SDNode *, 16> Worklist; 6349 6350 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(), 6351 E = Ptr.getNode()->use_end(); I != E; ++I) { 6352 SDNode *Use = *I; 6353 if (Use == N) 6354 continue; 6355 if (N->hasPredecessorHelper(Use, Visited, Worklist)) 6356 return false; 6357 6358 // If Ptr may be folded in addressing mode of other use, then it's 6359 // not profitable to do this transformation. 6360 if (!canFoldInAddressingMode(Ptr.getNode(), Use, DAG, TLI)) 6361 RealUse = true; 6362 } 6363 6364 if (!RealUse) 6365 return false; 6366 6367 SDValue Result; 6368 if (isLoad) 6369 Result = DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(), 6370 BasePtr, Offset, AM); 6371 else 6372 Result = DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(), 6373 BasePtr, Offset, AM); 6374 ++PreIndexedNodes; 6375 ++NodesCombined; 6376 DEBUG(dbgs() << "\nReplacing.4 "; 6377 N->dump(&DAG); 6378 dbgs() << "\nWith: "; 6379 Result.getNode()->dump(&DAG); 6380 dbgs() << '\n'); 6381 WorkListRemover DeadNodes(*this); 6382 if (isLoad) { 6383 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0), 6384 &DeadNodes); 6385 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2), 6386 &DeadNodes); 6387 } else { 6388 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1), 6389 &DeadNodes); 6390 } 6391 6392 // Finally, since the node is now dead, remove it from the graph. 6393 DAG.DeleteNode(N); 6394 6395 // Replace the uses of Ptr with uses of the updated base value. 6396 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0), 6397 &DeadNodes); 6398 removeFromWorkList(Ptr.getNode()); 6399 DAG.DeleteNode(Ptr.getNode()); 6400 6401 return true; 6402} 6403 6404/// CombineToPostIndexedLoadStore - Try to combine a load / store with a 6405/// add / sub of the base pointer node into a post-indexed load / store. 6406/// The transformation folded the add / subtract into the new indexed 6407/// load / store effectively and all of its uses are redirected to the 6408/// new load / store. 6409bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) { 6410 if (Level < AfterLegalizeDAG) 6411 return false; 6412 6413 bool isLoad = true; 6414 SDValue Ptr; 6415 EVT VT; 6416 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 6417 if (LD->isIndexed()) 6418 return false; 6419 VT = LD->getMemoryVT(); 6420 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) && 6421 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT)) 6422 return false; 6423 Ptr = LD->getBasePtr(); 6424 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 6425 if (ST->isIndexed()) 6426 return false; 6427 VT = ST->getMemoryVT(); 6428 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) && 6429 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT)) 6430 return false; 6431 Ptr = ST->getBasePtr(); 6432 isLoad = false; 6433 } else { 6434 return false; 6435 } 6436 6437 if (Ptr.getNode()->hasOneUse()) 6438 return false; 6439 6440 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(), 6441 E = Ptr.getNode()->use_end(); I != E; ++I) { 6442 SDNode *Op = *I; 6443 if (Op == N || 6444 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB)) 6445 continue; 6446 6447 SDValue BasePtr; 6448 SDValue Offset; 6449 ISD::MemIndexedMode AM = ISD::UNINDEXED; 6450 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) { 6451 // Don't create a indexed load / store with zero offset. 6452 if (isa<ConstantSDNode>(Offset) && 6453 cast<ConstantSDNode>(Offset)->isNullValue()) 6454 continue; 6455 6456 // Try turning it into a post-indexed load / store except when 6457 // 1) All uses are load / store ops that use it as base ptr (and 6458 // it may be folded as addressing mmode). 6459 // 2) Op must be independent of N, i.e. Op is neither a predecessor 6460 // nor a successor of N. Otherwise, if Op is folded that would 6461 // create a cycle. 6462 6463 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr)) 6464 continue; 6465 6466 // Check for #1. 6467 bool TryNext = false; 6468 for (SDNode::use_iterator II = BasePtr.getNode()->use_begin(), 6469 EE = BasePtr.getNode()->use_end(); II != EE; ++II) { 6470 SDNode *Use = *II; 6471 if (Use == Ptr.getNode()) 6472 continue; 6473 6474 // If all the uses are load / store addresses, then don't do the 6475 // transformation. 6476 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){ 6477 bool RealUse = false; 6478 for (SDNode::use_iterator III = Use->use_begin(), 6479 EEE = Use->use_end(); III != EEE; ++III) { 6480 SDNode *UseUse = *III; 6481 if (!canFoldInAddressingMode(Use, UseUse, DAG, TLI)) 6482 RealUse = true; 6483 } 6484 6485 if (!RealUse) { 6486 TryNext = true; 6487 break; 6488 } 6489 } 6490 } 6491 6492 if (TryNext) 6493 continue; 6494 6495 // Check for #2 6496 if (!Op->isPredecessorOf(N) && !N->isPredecessorOf(Op)) { 6497 SDValue Result = isLoad 6498 ? DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(), 6499 BasePtr, Offset, AM) 6500 : DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(), 6501 BasePtr, Offset, AM); 6502 ++PostIndexedNodes; 6503 ++NodesCombined; 6504 DEBUG(dbgs() << "\nReplacing.5 "; 6505 N->dump(&DAG); 6506 dbgs() << "\nWith: "; 6507 Result.getNode()->dump(&DAG); 6508 dbgs() << '\n'); 6509 WorkListRemover DeadNodes(*this); 6510 if (isLoad) { 6511 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0), 6512 &DeadNodes); 6513 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2), 6514 &DeadNodes); 6515 } else { 6516 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1), 6517 &DeadNodes); 6518 } 6519 6520 // Finally, since the node is now dead, remove it from the graph. 6521 DAG.DeleteNode(N); 6522 6523 // Replace the uses of Use with uses of the updated base value. 6524 DAG.ReplaceAllUsesOfValueWith(SDValue(Op, 0), 6525 Result.getValue(isLoad ? 1 : 0), 6526 &DeadNodes); 6527 removeFromWorkList(Op); 6528 DAG.DeleteNode(Op); 6529 return true; 6530 } 6531 } 6532 } 6533 6534 return false; 6535} 6536 6537SDValue DAGCombiner::visitLOAD(SDNode *N) { 6538 LoadSDNode *LD = cast<LoadSDNode>(N); 6539 SDValue Chain = LD->getChain(); 6540 SDValue Ptr = LD->getBasePtr(); 6541 6542 // If load is not volatile and there are no uses of the loaded value (and 6543 // the updated indexed value in case of indexed loads), change uses of the 6544 // chain value into uses of the chain input (i.e. delete the dead load). 6545 if (!LD->isVolatile()) { 6546 if (N->getValueType(1) == MVT::Other) { 6547 // Unindexed loads. 6548 if (!N->hasAnyUseOfValue(0)) { 6549 // It's not safe to use the two value CombineTo variant here. e.g. 6550 // v1, chain2 = load chain1, loc 6551 // v2, chain3 = load chain2, loc 6552 // v3 = add v2, c 6553 // Now we replace use of chain2 with chain1. This makes the second load 6554 // isomorphic to the one we are deleting, and thus makes this load live. 6555 DEBUG(dbgs() << "\nReplacing.6 "; 6556 N->dump(&DAG); 6557 dbgs() << "\nWith chain: "; 6558 Chain.getNode()->dump(&DAG); 6559 dbgs() << "\n"); 6560 WorkListRemover DeadNodes(*this); 6561 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Chain, &DeadNodes); 6562 6563 if (N->use_empty()) { 6564 removeFromWorkList(N); 6565 DAG.DeleteNode(N); 6566 } 6567 6568 return SDValue(N, 0); // Return N so it doesn't get rechecked! 6569 } 6570 } else { 6571 // Indexed loads. 6572 assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?"); 6573 if (!N->hasAnyUseOfValue(0) && !N->hasAnyUseOfValue(1)) { 6574 SDValue Undef = DAG.getUNDEF(N->getValueType(0)); 6575 DEBUG(dbgs() << "\nReplacing.7 "; 6576 N->dump(&DAG); 6577 dbgs() << "\nWith: "; 6578 Undef.getNode()->dump(&DAG); 6579 dbgs() << " and 2 other values\n"); 6580 WorkListRemover DeadNodes(*this); 6581 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Undef, &DeadNodes); 6582 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), 6583 DAG.getUNDEF(N->getValueType(1)), 6584 &DeadNodes); 6585 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 2), Chain, &DeadNodes); 6586 removeFromWorkList(N); 6587 DAG.DeleteNode(N); 6588 return SDValue(N, 0); // Return N so it doesn't get rechecked! 6589 } 6590 } 6591 } 6592 6593 // If this load is directly stored, replace the load value with the stored 6594 // value. 6595 // TODO: Handle store large -> read small portion. 6596 // TODO: Handle TRUNCSTORE/LOADEXT 6597 if (ISD::isNormalLoad(N) && !LD->isVolatile()) { 6598 if (ISD::isNON_TRUNCStore(Chain.getNode())) { 6599 StoreSDNode *PrevST = cast<StoreSDNode>(Chain); 6600 if (PrevST->getBasePtr() == Ptr && 6601 PrevST->getValue().getValueType() == N->getValueType(0)) 6602 return CombineTo(N, Chain.getOperand(1), Chain); 6603 } 6604 } 6605 6606 // Try to infer better alignment information than the load already has. 6607 if (OptLevel != CodeGenOpt::None && LD->isUnindexed()) { 6608 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) { 6609 if (Align > LD->getAlignment()) 6610 return DAG.getExtLoad(LD->getExtensionType(), N->getDebugLoc(), 6611 LD->getValueType(0), 6612 Chain, Ptr, LD->getPointerInfo(), 6613 LD->getMemoryVT(), 6614 LD->isVolatile(), LD->isNonTemporal(), Align); 6615 } 6616 } 6617 6618 if (CombinerAA) { 6619 // Walk up chain skipping non-aliasing memory nodes. 6620 SDValue BetterChain = FindBetterChain(N, Chain); 6621 6622 // If there is a better chain. 6623 if (Chain != BetterChain) { 6624 SDValue ReplLoad; 6625 6626 // Replace the chain to void dependency. 6627 if (LD->getExtensionType() == ISD::NON_EXTLOAD) { 6628 ReplLoad = DAG.getLoad(N->getValueType(0), LD->getDebugLoc(), 6629 BetterChain, Ptr, LD->getPointerInfo(), 6630 LD->isVolatile(), LD->isNonTemporal(), 6631 LD->isInvariant(), LD->getAlignment()); 6632 } else { 6633 ReplLoad = DAG.getExtLoad(LD->getExtensionType(), LD->getDebugLoc(), 6634 LD->getValueType(0), 6635 BetterChain, Ptr, LD->getPointerInfo(), 6636 LD->getMemoryVT(), 6637 LD->isVolatile(), 6638 LD->isNonTemporal(), 6639 LD->getAlignment()); 6640 } 6641 6642 // Create token factor to keep old chain connected. 6643 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 6644 MVT::Other, Chain, ReplLoad.getValue(1)); 6645 6646 // Make sure the new and old chains are cleaned up. 6647 AddToWorkList(Token.getNode()); 6648 6649 // Replace uses with load result and token factor. Don't add users 6650 // to work list. 6651 return CombineTo(N, ReplLoad.getValue(0), Token, false); 6652 } 6653 } 6654 6655 // Try transforming N to an indexed load. 6656 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 6657 return SDValue(N, 0); 6658 6659 return SDValue(); 6660} 6661 6662/// CheckForMaskedLoad - Check to see if V is (and load (ptr), imm), where the 6663/// load is having specific bytes cleared out. If so, return the byte size 6664/// being masked out and the shift amount. 6665static std::pair<unsigned, unsigned> 6666CheckForMaskedLoad(SDValue V, SDValue Ptr, SDValue Chain) { 6667 std::pair<unsigned, unsigned> Result(0, 0); 6668 6669 // Check for the structure we're looking for. 6670 if (V->getOpcode() != ISD::AND || 6671 !isa<ConstantSDNode>(V->getOperand(1)) || 6672 !ISD::isNormalLoad(V->getOperand(0).getNode())) 6673 return Result; 6674 6675 // Check the chain and pointer. 6676 LoadSDNode *LD = cast<LoadSDNode>(V->getOperand(0)); 6677 if (LD->getBasePtr() != Ptr) return Result; // Not from same pointer. 6678 6679 // The store should be chained directly to the load or be an operand of a 6680 // tokenfactor. 6681 if (LD == Chain.getNode()) 6682 ; // ok. 6683 else if (Chain->getOpcode() != ISD::TokenFactor) 6684 return Result; // Fail. 6685 else { 6686 bool isOk = false; 6687 for (unsigned i = 0, e = Chain->getNumOperands(); i != e; ++i) 6688 if (Chain->getOperand(i).getNode() == LD) { 6689 isOk = true; 6690 break; 6691 } 6692 if (!isOk) return Result; 6693 } 6694 6695 // This only handles simple types. 6696 if (V.getValueType() != MVT::i16 && 6697 V.getValueType() != MVT::i32 && 6698 V.getValueType() != MVT::i64) 6699 return Result; 6700 6701 // Check the constant mask. Invert it so that the bits being masked out are 6702 // 0 and the bits being kept are 1. Use getSExtValue so that leading bits 6703 // follow the sign bit for uniformity. 6704 uint64_t NotMask = ~cast<ConstantSDNode>(V->getOperand(1))->getSExtValue(); 6705 unsigned NotMaskLZ = CountLeadingZeros_64(NotMask); 6706 if (NotMaskLZ & 7) return Result; // Must be multiple of a byte. 6707 unsigned NotMaskTZ = CountTrailingZeros_64(NotMask); 6708 if (NotMaskTZ & 7) return Result; // Must be multiple of a byte. 6709 if (NotMaskLZ == 64) return Result; // All zero mask. 6710 6711 // See if we have a continuous run of bits. If so, we have 0*1+0* 6712 if (CountTrailingOnes_64(NotMask >> NotMaskTZ)+NotMaskTZ+NotMaskLZ != 64) 6713 return Result; 6714 6715 // Adjust NotMaskLZ down to be from the actual size of the int instead of i64. 6716 if (V.getValueType() != MVT::i64 && NotMaskLZ) 6717 NotMaskLZ -= 64-V.getValueSizeInBits(); 6718 6719 unsigned MaskedBytes = (V.getValueSizeInBits()-NotMaskLZ-NotMaskTZ)/8; 6720 switch (MaskedBytes) { 6721 case 1: 6722 case 2: 6723 case 4: break; 6724 default: return Result; // All one mask, or 5-byte mask. 6725 } 6726 6727 // Verify that the first bit starts at a multiple of mask so that the access 6728 // is aligned the same as the access width. 6729 if (NotMaskTZ && NotMaskTZ/8 % MaskedBytes) return Result; 6730 6731 Result.first = MaskedBytes; 6732 Result.second = NotMaskTZ/8; 6733 return Result; 6734} 6735 6736 6737/// ShrinkLoadReplaceStoreWithStore - Check to see if IVal is something that 6738/// provides a value as specified by MaskInfo. If so, replace the specified 6739/// store with a narrower store of truncated IVal. 6740static SDNode * 6741ShrinkLoadReplaceStoreWithStore(const std::pair<unsigned, unsigned> &MaskInfo, 6742 SDValue IVal, StoreSDNode *St, 6743 DAGCombiner *DC) { 6744 unsigned NumBytes = MaskInfo.first; 6745 unsigned ByteShift = MaskInfo.second; 6746 SelectionDAG &DAG = DC->getDAG(); 6747 6748 // Check to see if IVal is all zeros in the part being masked in by the 'or' 6749 // that uses this. If not, this is not a replacement. 6750 APInt Mask = ~APInt::getBitsSet(IVal.getValueSizeInBits(), 6751 ByteShift*8, (ByteShift+NumBytes)*8); 6752 if (!DAG.MaskedValueIsZero(IVal, Mask)) return 0; 6753 6754 // Check that it is legal on the target to do this. It is legal if the new 6755 // VT we're shrinking to (i8/i16/i32) is legal or we're still before type 6756 // legalization. 6757 MVT VT = MVT::getIntegerVT(NumBytes*8); 6758 if (!DC->isTypeLegal(VT)) 6759 return 0; 6760 6761 // Okay, we can do this! Replace the 'St' store with a store of IVal that is 6762 // shifted by ByteShift and truncated down to NumBytes. 6763 if (ByteShift) 6764 IVal = DAG.getNode(ISD::SRL, IVal->getDebugLoc(), IVal.getValueType(), IVal, 6765 DAG.getConstant(ByteShift*8, 6766 DC->getShiftAmountTy(IVal.getValueType()))); 6767 6768 // Figure out the offset for the store and the alignment of the access. 6769 unsigned StOffset; 6770 unsigned NewAlign = St->getAlignment(); 6771 6772 if (DAG.getTargetLoweringInfo().isLittleEndian()) 6773 StOffset = ByteShift; 6774 else 6775 StOffset = IVal.getValueType().getStoreSize() - ByteShift - NumBytes; 6776 6777 SDValue Ptr = St->getBasePtr(); 6778 if (StOffset) { 6779 Ptr = DAG.getNode(ISD::ADD, IVal->getDebugLoc(), Ptr.getValueType(), 6780 Ptr, DAG.getConstant(StOffset, Ptr.getValueType())); 6781 NewAlign = MinAlign(NewAlign, StOffset); 6782 } 6783 6784 // Truncate down to the new size. 6785 IVal = DAG.getNode(ISD::TRUNCATE, IVal->getDebugLoc(), VT, IVal); 6786 6787 ++OpsNarrowed; 6788 return DAG.getStore(St->getChain(), St->getDebugLoc(), IVal, Ptr, 6789 St->getPointerInfo().getWithOffset(StOffset), 6790 false, false, NewAlign).getNode(); 6791} 6792 6793 6794/// ReduceLoadOpStoreWidth - Look for sequence of load / op / store where op is 6795/// one of 'or', 'xor', and 'and' of immediates. If 'op' is only touching some 6796/// of the loaded bits, try narrowing the load and store if it would end up 6797/// being a win for performance or code size. 6798SDValue DAGCombiner::ReduceLoadOpStoreWidth(SDNode *N) { 6799 StoreSDNode *ST = cast<StoreSDNode>(N); 6800 if (ST->isVolatile()) 6801 return SDValue(); 6802 6803 SDValue Chain = ST->getChain(); 6804 SDValue Value = ST->getValue(); 6805 SDValue Ptr = ST->getBasePtr(); 6806 EVT VT = Value.getValueType(); 6807 6808 if (ST->isTruncatingStore() || VT.isVector() || !Value.hasOneUse()) 6809 return SDValue(); 6810 6811 unsigned Opc = Value.getOpcode(); 6812 6813 // If this is "store (or X, Y), P" and X is "(and (load P), cst)", where cst 6814 // is a byte mask indicating a consecutive number of bytes, check to see if 6815 // Y is known to provide just those bytes. If so, we try to replace the 6816 // load + replace + store sequence with a single (narrower) store, which makes 6817 // the load dead. 6818 if (Opc == ISD::OR) { 6819 std::pair<unsigned, unsigned> MaskedLoad; 6820 MaskedLoad = CheckForMaskedLoad(Value.getOperand(0), Ptr, Chain); 6821 if (MaskedLoad.first) 6822 if (SDNode *NewST = ShrinkLoadReplaceStoreWithStore(MaskedLoad, 6823 Value.getOperand(1), ST,this)) 6824 return SDValue(NewST, 0); 6825 6826 // Or is commutative, so try swapping X and Y. 6827 MaskedLoad = CheckForMaskedLoad(Value.getOperand(1), Ptr, Chain); 6828 if (MaskedLoad.first) 6829 if (SDNode *NewST = ShrinkLoadReplaceStoreWithStore(MaskedLoad, 6830 Value.getOperand(0), ST,this)) 6831 return SDValue(NewST, 0); 6832 } 6833 6834 if ((Opc != ISD::OR && Opc != ISD::XOR && Opc != ISD::AND) || 6835 Value.getOperand(1).getOpcode() != ISD::Constant) 6836 return SDValue(); 6837 6838 SDValue N0 = Value.getOperand(0); 6839 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() && 6840 Chain == SDValue(N0.getNode(), 1)) { 6841 LoadSDNode *LD = cast<LoadSDNode>(N0); 6842 if (LD->getBasePtr() != Ptr || 6843 LD->getPointerInfo().getAddrSpace() != 6844 ST->getPointerInfo().getAddrSpace()) 6845 return SDValue(); 6846 6847 // Find the type to narrow it the load / op / store to. 6848 SDValue N1 = Value.getOperand(1); 6849 unsigned BitWidth = N1.getValueSizeInBits(); 6850 APInt Imm = cast<ConstantSDNode>(N1)->getAPIntValue(); 6851 if (Opc == ISD::AND) 6852 Imm ^= APInt::getAllOnesValue(BitWidth); 6853 if (Imm == 0 || Imm.isAllOnesValue()) 6854 return SDValue(); 6855 unsigned ShAmt = Imm.countTrailingZeros(); 6856 unsigned MSB = BitWidth - Imm.countLeadingZeros() - 1; 6857 unsigned NewBW = NextPowerOf2(MSB - ShAmt); 6858 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW); 6859 while (NewBW < BitWidth && 6860 !(TLI.isOperationLegalOrCustom(Opc, NewVT) && 6861 TLI.isNarrowingProfitable(VT, NewVT))) { 6862 NewBW = NextPowerOf2(NewBW); 6863 NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW); 6864 } 6865 if (NewBW >= BitWidth) 6866 return SDValue(); 6867 6868 // If the lsb changed does not start at the type bitwidth boundary, 6869 // start at the previous one. 6870 if (ShAmt % NewBW) 6871 ShAmt = (((ShAmt + NewBW - 1) / NewBW) * NewBW) - NewBW; 6872 APInt Mask = APInt::getBitsSet(BitWidth, ShAmt, ShAmt + NewBW); 6873 if ((Imm & Mask) == Imm) { 6874 APInt NewImm = (Imm & Mask).lshr(ShAmt).trunc(NewBW); 6875 if (Opc == ISD::AND) 6876 NewImm ^= APInt::getAllOnesValue(NewBW); 6877 uint64_t PtrOff = ShAmt / 8; 6878 // For big endian targets, we need to adjust the offset to the pointer to 6879 // load the correct bytes. 6880 if (TLI.isBigEndian()) 6881 PtrOff = (BitWidth + 7 - NewBW) / 8 - PtrOff; 6882 6883 unsigned NewAlign = MinAlign(LD->getAlignment(), PtrOff); 6884 Type *NewVTTy = NewVT.getTypeForEVT(*DAG.getContext()); 6885 if (NewAlign < TLI.getTargetData()->getABITypeAlignment(NewVTTy)) 6886 return SDValue(); 6887 6888 SDValue NewPtr = DAG.getNode(ISD::ADD, LD->getDebugLoc(), 6889 Ptr.getValueType(), Ptr, 6890 DAG.getConstant(PtrOff, Ptr.getValueType())); 6891 SDValue NewLD = DAG.getLoad(NewVT, N0.getDebugLoc(), 6892 LD->getChain(), NewPtr, 6893 LD->getPointerInfo().getWithOffset(PtrOff), 6894 LD->isVolatile(), LD->isNonTemporal(), 6895 LD->isInvariant(), NewAlign); 6896 SDValue NewVal = DAG.getNode(Opc, Value.getDebugLoc(), NewVT, NewLD, 6897 DAG.getConstant(NewImm, NewVT)); 6898 SDValue NewST = DAG.getStore(Chain, N->getDebugLoc(), 6899 NewVal, NewPtr, 6900 ST->getPointerInfo().getWithOffset(PtrOff), 6901 false, false, NewAlign); 6902 6903 AddToWorkList(NewPtr.getNode()); 6904 AddToWorkList(NewLD.getNode()); 6905 AddToWorkList(NewVal.getNode()); 6906 WorkListRemover DeadNodes(*this); 6907 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), NewLD.getValue(1), 6908 &DeadNodes); 6909 ++OpsNarrowed; 6910 return NewST; 6911 } 6912 } 6913 6914 return SDValue(); 6915} 6916 6917/// TransformFPLoadStorePair - For a given floating point load / store pair, 6918/// if the load value isn't used by any other operations, then consider 6919/// transforming the pair to integer load / store operations if the target 6920/// deems the transformation profitable. 6921SDValue DAGCombiner::TransformFPLoadStorePair(SDNode *N) { 6922 StoreSDNode *ST = cast<StoreSDNode>(N); 6923 SDValue Chain = ST->getChain(); 6924 SDValue Value = ST->getValue(); 6925 if (ISD::isNormalStore(ST) && ISD::isNormalLoad(Value.getNode()) && 6926 Value.hasOneUse() && 6927 Chain == SDValue(Value.getNode(), 1)) { 6928 LoadSDNode *LD = cast<LoadSDNode>(Value); 6929 EVT VT = LD->getMemoryVT(); 6930 if (!VT.isFloatingPoint() || 6931 VT != ST->getMemoryVT() || 6932 LD->isNonTemporal() || 6933 ST->isNonTemporal() || 6934 LD->getPointerInfo().getAddrSpace() != 0 || 6935 ST->getPointerInfo().getAddrSpace() != 0) 6936 return SDValue(); 6937 6938 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits()); 6939 if (!TLI.isOperationLegal(ISD::LOAD, IntVT) || 6940 !TLI.isOperationLegal(ISD::STORE, IntVT) || 6941 !TLI.isDesirableToTransformToIntegerOp(ISD::LOAD, VT) || 6942 !TLI.isDesirableToTransformToIntegerOp(ISD::STORE, VT)) 6943 return SDValue(); 6944 6945 unsigned LDAlign = LD->getAlignment(); 6946 unsigned STAlign = ST->getAlignment(); 6947 Type *IntVTTy = IntVT.getTypeForEVT(*DAG.getContext()); 6948 unsigned ABIAlign = TLI.getTargetData()->getABITypeAlignment(IntVTTy); 6949 if (LDAlign < ABIAlign || STAlign < ABIAlign) 6950 return SDValue(); 6951 6952 SDValue NewLD = DAG.getLoad(IntVT, Value.getDebugLoc(), 6953 LD->getChain(), LD->getBasePtr(), 6954 LD->getPointerInfo(), 6955 false, false, false, LDAlign); 6956 6957 SDValue NewST = DAG.getStore(NewLD.getValue(1), N->getDebugLoc(), 6958 NewLD, ST->getBasePtr(), 6959 ST->getPointerInfo(), 6960 false, false, STAlign); 6961 6962 AddToWorkList(NewLD.getNode()); 6963 AddToWorkList(NewST.getNode()); 6964 WorkListRemover DeadNodes(*this); 6965 DAG.ReplaceAllUsesOfValueWith(Value.getValue(1), NewLD.getValue(1), 6966 &DeadNodes); 6967 ++LdStFP2Int; 6968 return NewST; 6969 } 6970 6971 return SDValue(); 6972} 6973 6974SDValue DAGCombiner::visitSTORE(SDNode *N) { 6975 StoreSDNode *ST = cast<StoreSDNode>(N); 6976 SDValue Chain = ST->getChain(); 6977 SDValue Value = ST->getValue(); 6978 SDValue Ptr = ST->getBasePtr(); 6979 6980 // If this is a store of a bit convert, store the input value if the 6981 // resultant store does not need a higher alignment than the original. 6982 if (Value.getOpcode() == ISD::BITCAST && !ST->isTruncatingStore() && 6983 ST->isUnindexed()) { 6984 unsigned OrigAlign = ST->getAlignment(); 6985 EVT SVT = Value.getOperand(0).getValueType(); 6986 unsigned Align = TLI.getTargetData()-> 6987 getABITypeAlignment(SVT.getTypeForEVT(*DAG.getContext())); 6988 if (Align <= OrigAlign && 6989 ((!LegalOperations && !ST->isVolatile()) || 6990 TLI.isOperationLegalOrCustom(ISD::STORE, SVT))) 6991 return DAG.getStore(Chain, N->getDebugLoc(), Value.getOperand(0), 6992 Ptr, ST->getPointerInfo(), ST->isVolatile(), 6993 ST->isNonTemporal(), OrigAlign); 6994 } 6995 6996 // Turn 'store undef, Ptr' -> nothing. 6997 if (Value.getOpcode() == ISD::UNDEF && ST->isUnindexed()) 6998 return Chain; 6999 7000 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 7001 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) { 7002 // NOTE: If the original store is volatile, this transform must not increase 7003 // the number of stores. For example, on x86-32 an f64 can be stored in one 7004 // processor operation but an i64 (which is not legal) requires two. So the 7005 // transform should not be done in this case. 7006 if (Value.getOpcode() != ISD::TargetConstantFP) { 7007 SDValue Tmp; 7008 switch (CFP->getValueType(0).getSimpleVT().SimpleTy) { 7009 default: llvm_unreachable("Unknown FP type"); 7010 case MVT::f80: // We don't do this for these yet. 7011 case MVT::f128: 7012 case MVT::ppcf128: 7013 break; 7014 case MVT::f32: 7015 if ((isTypeLegal(MVT::i32) && !LegalOperations && !ST->isVolatile()) || 7016 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) { 7017 Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF(). 7018 bitcastToAPInt().getZExtValue(), MVT::i32); 7019 return DAG.getStore(Chain, N->getDebugLoc(), Tmp, 7020 Ptr, ST->getPointerInfo(), ST->isVolatile(), 7021 ST->isNonTemporal(), ST->getAlignment()); 7022 } 7023 break; 7024 case MVT::f64: 7025 if ((TLI.isTypeLegal(MVT::i64) && !LegalOperations && 7026 !ST->isVolatile()) || 7027 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i64)) { 7028 Tmp = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt(). 7029 getZExtValue(), MVT::i64); 7030 return DAG.getStore(Chain, N->getDebugLoc(), Tmp, 7031 Ptr, ST->getPointerInfo(), ST->isVolatile(), 7032 ST->isNonTemporal(), ST->getAlignment()); 7033 } 7034 7035 if (!ST->isVolatile() && 7036 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) { 7037 // Many FP stores are not made apparent until after legalize, e.g. for 7038 // argument passing. Since this is so common, custom legalize the 7039 // 64-bit integer store into two 32-bit stores. 7040 uint64_t Val = CFP->getValueAPF().bitcastToAPInt().getZExtValue(); 7041 SDValue Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32); 7042 SDValue Hi = DAG.getConstant(Val >> 32, MVT::i32); 7043 if (TLI.isBigEndian()) std::swap(Lo, Hi); 7044 7045 unsigned Alignment = ST->getAlignment(); 7046 bool isVolatile = ST->isVolatile(); 7047 bool isNonTemporal = ST->isNonTemporal(); 7048 7049 SDValue St0 = DAG.getStore(Chain, ST->getDebugLoc(), Lo, 7050 Ptr, ST->getPointerInfo(), 7051 isVolatile, isNonTemporal, 7052 ST->getAlignment()); 7053 Ptr = DAG.getNode(ISD::ADD, N->getDebugLoc(), Ptr.getValueType(), Ptr, 7054 DAG.getConstant(4, Ptr.getValueType())); 7055 Alignment = MinAlign(Alignment, 4U); 7056 SDValue St1 = DAG.getStore(Chain, ST->getDebugLoc(), Hi, 7057 Ptr, ST->getPointerInfo().getWithOffset(4), 7058 isVolatile, isNonTemporal, 7059 Alignment); 7060 return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, 7061 St0, St1); 7062 } 7063 7064 break; 7065 } 7066 } 7067 } 7068 7069 // Try to infer better alignment information than the store already has. 7070 if (OptLevel != CodeGenOpt::None && ST->isUnindexed()) { 7071 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) { 7072 if (Align > ST->getAlignment()) 7073 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value, 7074 Ptr, ST->getPointerInfo(), ST->getMemoryVT(), 7075 ST->isVolatile(), ST->isNonTemporal(), Align); 7076 } 7077 } 7078 7079 // Try transforming a pair floating point load / store ops to integer 7080 // load / store ops. 7081 SDValue NewST = TransformFPLoadStorePair(N); 7082 if (NewST.getNode()) 7083 return NewST; 7084 7085 if (CombinerAA) { 7086 // Walk up chain skipping non-aliasing memory nodes. 7087 SDValue BetterChain = FindBetterChain(N, Chain); 7088 7089 // If there is a better chain. 7090 if (Chain != BetterChain) { 7091 SDValue ReplStore; 7092 7093 // Replace the chain to avoid dependency. 7094 if (ST->isTruncatingStore()) { 7095 ReplStore = DAG.getTruncStore(BetterChain, N->getDebugLoc(), Value, Ptr, 7096 ST->getPointerInfo(), 7097 ST->getMemoryVT(), ST->isVolatile(), 7098 ST->isNonTemporal(), ST->getAlignment()); 7099 } else { 7100 ReplStore = DAG.getStore(BetterChain, N->getDebugLoc(), Value, Ptr, 7101 ST->getPointerInfo(), 7102 ST->isVolatile(), ST->isNonTemporal(), 7103 ST->getAlignment()); 7104 } 7105 7106 // Create token to keep both nodes around. 7107 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 7108 MVT::Other, Chain, ReplStore); 7109 7110 // Make sure the new and old chains are cleaned up. 7111 AddToWorkList(Token.getNode()); 7112 7113 // Don't add users to work list. 7114 return CombineTo(N, Token, false); 7115 } 7116 } 7117 7118 // Try transforming N to an indexed store. 7119 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 7120 return SDValue(N, 0); 7121 7122 // FIXME: is there such a thing as a truncating indexed store? 7123 if (ST->isTruncatingStore() && ST->isUnindexed() && 7124 Value.getValueType().isInteger()) { 7125 // See if we can simplify the input to this truncstore with knowledge that 7126 // only the low bits are being used. For example: 7127 // "truncstore (or (shl x, 8), y), i8" -> "truncstore y, i8" 7128 SDValue Shorter = 7129 GetDemandedBits(Value, 7130 APInt::getLowBitsSet( 7131 Value.getValueType().getScalarType().getSizeInBits(), 7132 ST->getMemoryVT().getScalarType().getSizeInBits())); 7133 AddToWorkList(Value.getNode()); 7134 if (Shorter.getNode()) 7135 return DAG.getTruncStore(Chain, N->getDebugLoc(), Shorter, 7136 Ptr, ST->getPointerInfo(), ST->getMemoryVT(), 7137 ST->isVolatile(), ST->isNonTemporal(), 7138 ST->getAlignment()); 7139 7140 // Otherwise, see if we can simplify the operation with 7141 // SimplifyDemandedBits, which only works if the value has a single use. 7142 if (SimplifyDemandedBits(Value, 7143 APInt::getLowBitsSet( 7144 Value.getValueType().getScalarType().getSizeInBits(), 7145 ST->getMemoryVT().getScalarType().getSizeInBits()))) 7146 return SDValue(N, 0); 7147 } 7148 7149 // If this is a load followed by a store to the same location, then the store 7150 // is dead/noop. 7151 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Value)) { 7152 if (Ld->getBasePtr() == Ptr && ST->getMemoryVT() == Ld->getMemoryVT() && 7153 ST->isUnindexed() && !ST->isVolatile() && 7154 // There can't be any side effects between the load and store, such as 7155 // a call or store. 7156 Chain.reachesChainWithoutSideEffects(SDValue(Ld, 1))) { 7157 // The store is dead, remove it. 7158 return Chain; 7159 } 7160 } 7161 7162 // If this is an FP_ROUND or TRUNC followed by a store, fold this into a 7163 // truncating store. We can do this even if this is already a truncstore. 7164 if ((Value.getOpcode() == ISD::FP_ROUND || Value.getOpcode() == ISD::TRUNCATE) 7165 && Value.getNode()->hasOneUse() && ST->isUnindexed() && 7166 TLI.isTruncStoreLegal(Value.getOperand(0).getValueType(), 7167 ST->getMemoryVT())) { 7168 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value.getOperand(0), 7169 Ptr, ST->getPointerInfo(), ST->getMemoryVT(), 7170 ST->isVolatile(), ST->isNonTemporal(), 7171 ST->getAlignment()); 7172 } 7173 7174 return ReduceLoadOpStoreWidth(N); 7175} 7176 7177SDValue DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) { 7178 SDValue InVec = N->getOperand(0); 7179 SDValue InVal = N->getOperand(1); 7180 SDValue EltNo = N->getOperand(2); 7181 DebugLoc dl = N->getDebugLoc(); 7182 7183 // If the inserted element is an UNDEF, just use the input vector. 7184 if (InVal.getOpcode() == ISD::UNDEF) 7185 return InVec; 7186 7187 EVT VT = InVec.getValueType(); 7188 7189 // If we can't generate a legal BUILD_VECTOR, exit 7190 if (LegalOperations && !TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) 7191 return SDValue(); 7192 7193 // Check that we know which element is being inserted 7194 if (!isa<ConstantSDNode>(EltNo)) 7195 return SDValue(); 7196 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 7197 7198 // Check that the operand is a BUILD_VECTOR (or UNDEF, which can essentially 7199 // be converted to a BUILD_VECTOR). Fill in the Ops vector with the 7200 // vector elements. 7201 SmallVector<SDValue, 8> Ops; 7202 if (InVec.getOpcode() == ISD::BUILD_VECTOR) { 7203 Ops.append(InVec.getNode()->op_begin(), 7204 InVec.getNode()->op_end()); 7205 } else if (InVec.getOpcode() == ISD::UNDEF) { 7206 unsigned NElts = VT.getVectorNumElements(); 7207 Ops.append(NElts, DAG.getUNDEF(InVal.getValueType())); 7208 } else { 7209 return SDValue(); 7210 } 7211 7212 // Insert the element 7213 if (Elt < Ops.size()) { 7214 // All the operands of BUILD_VECTOR must have the same type; 7215 // we enforce that here. 7216 EVT OpVT = Ops[0].getValueType(); 7217 if (InVal.getValueType() != OpVT) 7218 InVal = OpVT.bitsGT(InVal.getValueType()) ? 7219 DAG.getNode(ISD::ANY_EXTEND, dl, OpVT, InVal) : 7220 DAG.getNode(ISD::TRUNCATE, dl, OpVT, InVal); 7221 Ops[Elt] = InVal; 7222 } 7223 7224 // Return the new vector 7225 return DAG.getNode(ISD::BUILD_VECTOR, dl, 7226 VT, &Ops[0], Ops.size()); 7227} 7228 7229SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) { 7230 // (vextract (scalar_to_vector val, 0) -> val 7231 SDValue InVec = N->getOperand(0); 7232 EVT VT = InVec.getValueType(); 7233 EVT NVT = N->getValueType(0); 7234 7235 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) { 7236 // Check if the result type doesn't match the inserted element type. A 7237 // SCALAR_TO_VECTOR may truncate the inserted element and the 7238 // EXTRACT_VECTOR_ELT may widen the extracted vector. 7239 SDValue InOp = InVec.getOperand(0); 7240 if (InOp.getValueType() != NVT) { 7241 assert(InOp.getValueType().isInteger() && NVT.isInteger()); 7242 return DAG.getSExtOrTrunc(InOp, InVec.getDebugLoc(), NVT); 7243 } 7244 return InOp; 7245 } 7246 7247 SDValue EltNo = N->getOperand(1); 7248 bool ConstEltNo = isa<ConstantSDNode>(EltNo); 7249 7250 // Transform: (EXTRACT_VECTOR_ELT( VECTOR_SHUFFLE )) -> EXTRACT_VECTOR_ELT. 7251 // We only perform this optimization before the op legalization phase because 7252 // we may introduce new vector instructions which are not backed by TD patterns. 7253 // For example on AVX, extracting elements from a wide vector without using 7254 // extract_subvector. 7255 if (InVec.getOpcode() == ISD::VECTOR_SHUFFLE 7256 && ConstEltNo && !LegalOperations) { 7257 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 7258 int NumElem = VT.getVectorNumElements(); 7259 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(InVec); 7260 // Find the new index to extract from. 7261 int OrigElt = SVOp->getMaskElt(Elt); 7262 7263 // Extracting an undef index is undef. 7264 if (OrigElt == -1) 7265 return DAG.getUNDEF(NVT); 7266 7267 // Select the right vector half to extract from. 7268 if (OrigElt < NumElem) { 7269 InVec = InVec->getOperand(0); 7270 } else { 7271 InVec = InVec->getOperand(1); 7272 OrigElt -= NumElem; 7273 } 7274 7275 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, N->getDebugLoc(), NVT, 7276 InVec, DAG.getConstant(OrigElt, MVT::i32)); 7277 } 7278 7279 // Perform only after legalization to ensure build_vector / vector_shuffle 7280 // optimizations have already been done. 7281 if (!LegalOperations) return SDValue(); 7282 7283 // (vextract (v4f32 load $addr), c) -> (f32 load $addr+c*size) 7284 // (vextract (v4f32 s2v (f32 load $addr)), c) -> (f32 load $addr+c*size) 7285 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), 0) -> (f32 load $addr) 7286 7287 if (ConstEltNo) { 7288 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 7289 bool NewLoad = false; 7290 bool BCNumEltsChanged = false; 7291 EVT ExtVT = VT.getVectorElementType(); 7292 EVT LVT = ExtVT; 7293 7294 // If the result of load has to be truncated, then it's not necessarily 7295 // profitable. 7296 if (NVT.bitsLT(LVT) && !TLI.isTruncateFree(LVT, NVT)) 7297 return SDValue(); 7298 7299 if (InVec.getOpcode() == ISD::BITCAST) { 7300 // Don't duplicate a load with other uses. 7301 if (!InVec.hasOneUse()) 7302 return SDValue(); 7303 7304 EVT BCVT = InVec.getOperand(0).getValueType(); 7305 if (!BCVT.isVector() || ExtVT.bitsGT(BCVT.getVectorElementType())) 7306 return SDValue(); 7307 if (VT.getVectorNumElements() != BCVT.getVectorNumElements()) 7308 BCNumEltsChanged = true; 7309 InVec = InVec.getOperand(0); 7310 ExtVT = BCVT.getVectorElementType(); 7311 NewLoad = true; 7312 } 7313 7314 LoadSDNode *LN0 = NULL; 7315 const ShuffleVectorSDNode *SVN = NULL; 7316 if (ISD::isNormalLoad(InVec.getNode())) { 7317 LN0 = cast<LoadSDNode>(InVec); 7318 } else if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR && 7319 InVec.getOperand(0).getValueType() == ExtVT && 7320 ISD::isNormalLoad(InVec.getOperand(0).getNode())) { 7321 // Don't duplicate a load with other uses. 7322 if (!InVec.hasOneUse()) 7323 return SDValue(); 7324 7325 LN0 = cast<LoadSDNode>(InVec.getOperand(0)); 7326 } else if ((SVN = dyn_cast<ShuffleVectorSDNode>(InVec))) { 7327 // (vextract (vector_shuffle (load $addr), v2, <1, u, u, u>), 1) 7328 // => 7329 // (load $addr+1*size) 7330 7331 // Don't duplicate a load with other uses. 7332 if (!InVec.hasOneUse()) 7333 return SDValue(); 7334 7335 // If the bit convert changed the number of elements, it is unsafe 7336 // to examine the mask. 7337 if (BCNumEltsChanged) 7338 return SDValue(); 7339 7340 // Select the input vector, guarding against out of range extract vector. 7341 unsigned NumElems = VT.getVectorNumElements(); 7342 int Idx = (Elt > (int)NumElems) ? -1 : SVN->getMaskElt(Elt); 7343 InVec = (Idx < (int)NumElems) ? InVec.getOperand(0) : InVec.getOperand(1); 7344 7345 if (InVec.getOpcode() == ISD::BITCAST) { 7346 // Don't duplicate a load with other uses. 7347 if (!InVec.hasOneUse()) 7348 return SDValue(); 7349 7350 InVec = InVec.getOperand(0); 7351 } 7352 if (ISD::isNormalLoad(InVec.getNode())) { 7353 LN0 = cast<LoadSDNode>(InVec); 7354 Elt = (Idx < (int)NumElems) ? Idx : Idx - (int)NumElems; 7355 } 7356 } 7357 7358 // Make sure we found a non-volatile load and the extractelement is 7359 // the only use. 7360 if (!LN0 || !LN0->hasNUsesOfValue(1,0) || LN0->isVolatile()) 7361 return SDValue(); 7362 7363 // If Idx was -1 above, Elt is going to be -1, so just return undef. 7364 if (Elt == -1) 7365 return DAG.getUNDEF(LVT); 7366 7367 unsigned Align = LN0->getAlignment(); 7368 if (NewLoad) { 7369 // Check the resultant load doesn't need a higher alignment than the 7370 // original load. 7371 unsigned NewAlign = 7372 TLI.getTargetData() 7373 ->getABITypeAlignment(LVT.getTypeForEVT(*DAG.getContext())); 7374 7375 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, LVT)) 7376 return SDValue(); 7377 7378 Align = NewAlign; 7379 } 7380 7381 SDValue NewPtr = LN0->getBasePtr(); 7382 unsigned PtrOff = 0; 7383 7384 if (Elt) { 7385 PtrOff = LVT.getSizeInBits() * Elt / 8; 7386 EVT PtrType = NewPtr.getValueType(); 7387 if (TLI.isBigEndian()) 7388 PtrOff = VT.getSizeInBits() / 8 - PtrOff; 7389 NewPtr = DAG.getNode(ISD::ADD, N->getDebugLoc(), PtrType, NewPtr, 7390 DAG.getConstant(PtrOff, PtrType)); 7391 } 7392 7393 // The replacement we need to do here is a little tricky: we need to 7394 // replace an extractelement of a load with a load. 7395 // Use ReplaceAllUsesOfValuesWith to do the replacement. 7396 // Note that this replacement assumes that the extractvalue is the only 7397 // use of the load; that's okay because we don't want to perform this 7398 // transformation in other cases anyway. 7399 SDValue Load; 7400 SDValue Chain; 7401 if (NVT.bitsGT(LVT)) { 7402 // If the result type of vextract is wider than the load, then issue an 7403 // extending load instead. 7404 ISD::LoadExtType ExtType = TLI.isLoadExtLegal(ISD::ZEXTLOAD, LVT) 7405 ? ISD::ZEXTLOAD : ISD::EXTLOAD; 7406 Load = DAG.getExtLoad(ExtType, N->getDebugLoc(), NVT, LN0->getChain(), 7407 NewPtr, LN0->getPointerInfo().getWithOffset(PtrOff), 7408 LVT, LN0->isVolatile(), LN0->isNonTemporal(),Align); 7409 Chain = Load.getValue(1); 7410 } else { 7411 Load = DAG.getLoad(LVT, N->getDebugLoc(), LN0->getChain(), NewPtr, 7412 LN0->getPointerInfo().getWithOffset(PtrOff), 7413 LN0->isVolatile(), LN0->isNonTemporal(), 7414 LN0->isInvariant(), Align); 7415 Chain = Load.getValue(1); 7416 if (NVT.bitsLT(LVT)) 7417 Load = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), NVT, Load); 7418 else 7419 Load = DAG.getNode(ISD::BITCAST, N->getDebugLoc(), NVT, Load); 7420 } 7421 WorkListRemover DeadNodes(*this); 7422 SDValue From[] = { SDValue(N, 0), SDValue(LN0,1) }; 7423 SDValue To[] = { Load, Chain }; 7424 DAG.ReplaceAllUsesOfValuesWith(From, To, 2, &DeadNodes); 7425 // Since we're explcitly calling ReplaceAllUses, add the new node to the 7426 // worklist explicitly as well. 7427 AddToWorkList(Load.getNode()); 7428 AddUsersToWorkList(Load.getNode()); // Add users too 7429 // Make sure to revisit this node to clean it up; it will usually be dead. 7430 AddToWorkList(N); 7431 return SDValue(N, 0); 7432 } 7433 7434 return SDValue(); 7435} 7436 7437SDValue DAGCombiner::visitBUILD_VECTOR(SDNode *N) { 7438 unsigned NumInScalars = N->getNumOperands(); 7439 DebugLoc dl = N->getDebugLoc(); 7440 EVT VT = N->getValueType(0); 7441 // Check to see if this is a BUILD_VECTOR of a bunch of values 7442 // which come from any_extend or zero_extend nodes. If so, we can create 7443 // a new BUILD_VECTOR using bit-casts which may enable other BUILD_VECTOR 7444 // optimizations. We do not handle sign-extend because we can't fill the sign 7445 // using shuffles. 7446 EVT SourceType = MVT::Other; 7447 bool AllAnyExt = true; 7448 bool AllUndef = true; 7449 for (unsigned i = 0; i != NumInScalars; ++i) { 7450 SDValue In = N->getOperand(i); 7451 // Ignore undef inputs. 7452 if (In.getOpcode() == ISD::UNDEF) continue; 7453 AllUndef = false; 7454 7455 bool AnyExt = In.getOpcode() == ISD::ANY_EXTEND; 7456 bool ZeroExt = In.getOpcode() == ISD::ZERO_EXTEND; 7457 7458 // Abort if the element is not an extension. 7459 if (!ZeroExt && !AnyExt) { 7460 SourceType = MVT::Other; 7461 break; 7462 } 7463 7464 // The input is a ZeroExt or AnyExt. Check the original type. 7465 EVT InTy = In.getOperand(0).getValueType(); 7466 7467 // Check that all of the widened source types are the same. 7468 if (SourceType == MVT::Other) 7469 // First time. 7470 SourceType = InTy; 7471 else if (InTy != SourceType) { 7472 // Multiple income types. Abort. 7473 SourceType = MVT::Other; 7474 break; 7475 } 7476 7477 // Check if all of the extends are ANY_EXTENDs. 7478 AllAnyExt &= AnyExt; 7479 } 7480 7481 if (AllUndef) 7482 return DAG.getUNDEF(VT); 7483 7484 // In order to have valid types, all of the inputs must be extended from the 7485 // same source type and all of the inputs must be any or zero extend. 7486 // Scalar sizes must be a power of two. 7487 EVT OutScalarTy = N->getValueType(0).getScalarType(); 7488 bool ValidTypes = SourceType != MVT::Other && 7489 isPowerOf2_32(OutScalarTy.getSizeInBits()) && 7490 isPowerOf2_32(SourceType.getSizeInBits()); 7491 7492 // We perform this optimization post type-legalization because 7493 // the type-legalizer often scalarizes integer-promoted vectors. 7494 // Performing this optimization before may create bit-casts which 7495 // will be type-legalized to complex code sequences. 7496 // We perform this optimization only before the operation legalizer because we 7497 // may introduce illegal operations. 7498 // Create a new simpler BUILD_VECTOR sequence which other optimizations can 7499 // turn into a single shuffle instruction. 7500 if ((Level == AfterLegalizeVectorOps || Level == AfterLegalizeTypes) && 7501 ValidTypes) { 7502 bool isLE = TLI.isLittleEndian(); 7503 unsigned ElemRatio = OutScalarTy.getSizeInBits()/SourceType.getSizeInBits(); 7504 assert(ElemRatio > 1 && "Invalid element size ratio"); 7505 SDValue Filler = AllAnyExt ? DAG.getUNDEF(SourceType): 7506 DAG.getConstant(0, SourceType); 7507 7508 unsigned NewBVElems = ElemRatio * N->getValueType(0).getVectorNumElements(); 7509 SmallVector<SDValue, 8> Ops(NewBVElems, Filler); 7510 7511 // Populate the new build_vector 7512 for (unsigned i=0; i < N->getNumOperands(); ++i) { 7513 SDValue Cast = N->getOperand(i); 7514 assert((Cast.getOpcode() == ISD::ANY_EXTEND || 7515 Cast.getOpcode() == ISD::ZERO_EXTEND || 7516 Cast.getOpcode() == ISD::UNDEF) && "Invalid cast opcode"); 7517 SDValue In; 7518 if (Cast.getOpcode() == ISD::UNDEF) 7519 In = DAG.getUNDEF(SourceType); 7520 else 7521 In = Cast->getOperand(0); 7522 unsigned Index = isLE ? (i * ElemRatio) : 7523 (i * ElemRatio + (ElemRatio - 1)); 7524 7525 assert(Index < Ops.size() && "Invalid index"); 7526 Ops[Index] = In; 7527 } 7528 7529 // The type of the new BUILD_VECTOR node. 7530 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), SourceType, NewBVElems); 7531 assert(VecVT.getSizeInBits() == N->getValueType(0).getSizeInBits() && 7532 "Invalid vector size"); 7533 // Check if the new vector type is legal. 7534 if (!isTypeLegal(VecVT)) return SDValue(); 7535 7536 // Make the new BUILD_VECTOR. 7537 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 7538 VecVT, &Ops[0], Ops.size()); 7539 7540 // The new BUILD_VECTOR node has the potential to be further optimized. 7541 AddToWorkList(BV.getNode()); 7542 // Bitcast to the desired type. 7543 return DAG.getNode(ISD::BITCAST, dl, N->getValueType(0), BV); 7544 } 7545 7546 // Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT 7547 // operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from 7548 // at most two distinct vectors, turn this into a shuffle node. 7549 7550 // May only combine to shuffle after legalize if shuffle is legal. 7551 if (LegalOperations && 7552 !TLI.isOperationLegalOrCustom(ISD::VECTOR_SHUFFLE, VT)) 7553 return SDValue(); 7554 7555 SDValue VecIn1, VecIn2; 7556 for (unsigned i = 0; i != NumInScalars; ++i) { 7557 // Ignore undef inputs. 7558 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 7559 7560 // If this input is something other than a EXTRACT_VECTOR_ELT with a 7561 // constant index, bail out. 7562 if (N->getOperand(i).getOpcode() != ISD::EXTRACT_VECTOR_ELT || 7563 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) { 7564 VecIn1 = VecIn2 = SDValue(0, 0); 7565 break; 7566 } 7567 7568 // We allow up to two distinct input vectors. 7569 SDValue ExtractedFromVec = N->getOperand(i).getOperand(0); 7570 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2) 7571 continue; 7572 7573 if (VecIn1.getNode() == 0) { 7574 VecIn1 = ExtractedFromVec; 7575 } else if (VecIn2.getNode() == 0) { 7576 VecIn2 = ExtractedFromVec; 7577 } else { 7578 // Too many inputs. 7579 VecIn1 = VecIn2 = SDValue(0, 0); 7580 break; 7581 } 7582 } 7583 7584 // If everything is good, we can make a shuffle operation. 7585 if (VecIn1.getNode()) { 7586 SmallVector<int, 8> Mask; 7587 for (unsigned i = 0; i != NumInScalars; ++i) { 7588 if (N->getOperand(i).getOpcode() == ISD::UNDEF) { 7589 Mask.push_back(-1); 7590 continue; 7591 } 7592 7593 // If extracting from the first vector, just use the index directly. 7594 SDValue Extract = N->getOperand(i); 7595 SDValue ExtVal = Extract.getOperand(1); 7596 if (Extract.getOperand(0) == VecIn1) { 7597 unsigned ExtIndex = cast<ConstantSDNode>(ExtVal)->getZExtValue(); 7598 if (ExtIndex > VT.getVectorNumElements()) 7599 return SDValue(); 7600 7601 Mask.push_back(ExtIndex); 7602 continue; 7603 } 7604 7605 // Otherwise, use InIdx + VecSize 7606 unsigned Idx = cast<ConstantSDNode>(ExtVal)->getZExtValue(); 7607 Mask.push_back(Idx+NumInScalars); 7608 } 7609 7610 // We can't generate a shuffle node with mismatched input and output types. 7611 // Attempt to transform a single input vector to the correct type. 7612 if ((VT != VecIn1.getValueType())) { 7613 // We don't support shuffeling between TWO values of different types. 7614 if (VecIn2.getNode() != 0) 7615 return SDValue(); 7616 7617 // We only support widening of vectors which are half the size of the 7618 // output registers. For example XMM->YMM widening on X86 with AVX. 7619 if (VecIn1.getValueType().getSizeInBits()*2 != VT.getSizeInBits()) 7620 return SDValue(); 7621 7622 // Widen the input vector by adding undef values. 7623 VecIn1 = DAG.getNode(ISD::CONCAT_VECTORS, N->getDebugLoc(), VT, 7624 VecIn1, DAG.getUNDEF(VecIn1.getValueType())); 7625 } 7626 7627 // If VecIn2 is unused then change it to undef. 7628 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT); 7629 7630 // Check that we were able to transform all incoming values to the same type. 7631 if (VecIn2.getValueType() != VecIn1.getValueType() || 7632 VecIn1.getValueType() != VT) 7633 return SDValue(); 7634 7635 // Only type-legal BUILD_VECTOR nodes are converted to shuffle nodes. 7636 if (!isTypeLegal(VT)) 7637 return SDValue(); 7638 7639 // Return the new VECTOR_SHUFFLE node. 7640 SDValue Ops[2]; 7641 Ops[0] = VecIn1; 7642 Ops[1] = VecIn2; 7643 return DAG.getVectorShuffle(VT, N->getDebugLoc(), Ops[0], Ops[1], &Mask[0]); 7644 } 7645 7646 return SDValue(); 7647} 7648 7649SDValue DAGCombiner::visitCONCAT_VECTORS(SDNode *N) { 7650 // TODO: Check to see if this is a CONCAT_VECTORS of a bunch of 7651 // EXTRACT_SUBVECTOR operations. If so, and if the EXTRACT_SUBVECTOR vector 7652 // inputs come from at most two distinct vectors, turn this into a shuffle 7653 // node. 7654 7655 // If we only have one input vector, we don't need to do any concatenation. 7656 if (N->getNumOperands() == 1) 7657 return N->getOperand(0); 7658 7659 return SDValue(); 7660} 7661 7662SDValue DAGCombiner::visitEXTRACT_SUBVECTOR(SDNode* N) { 7663 EVT NVT = N->getValueType(0); 7664 SDValue V = N->getOperand(0); 7665 7666 if (V->getOpcode() == ISD::INSERT_SUBVECTOR) { 7667 // Handle only simple case where vector being inserted and vector 7668 // being extracted are of same type, and are half size of larger vectors. 7669 EVT BigVT = V->getOperand(0).getValueType(); 7670 EVT SmallVT = V->getOperand(1).getValueType(); 7671 if (NVT != SmallVT || NVT.getSizeInBits()*2 != BigVT.getSizeInBits()) 7672 return SDValue(); 7673 7674 // Only handle cases where both indexes are constants with the same type. 7675 ConstantSDNode *InsIdx = dyn_cast<ConstantSDNode>(N->getOperand(1)); 7676 ConstantSDNode *ExtIdx = dyn_cast<ConstantSDNode>(V->getOperand(2)); 7677 7678 if (InsIdx && ExtIdx && 7679 InsIdx->getValueType(0).getSizeInBits() <= 64 && 7680 ExtIdx->getValueType(0).getSizeInBits() <= 64) { 7681 // Combine: 7682 // (extract_subvec (insert_subvec V1, V2, InsIdx), ExtIdx) 7683 // Into: 7684 // indices are equal => V1 7685 // otherwise => (extract_subvec V1, ExtIdx) 7686 if (InsIdx->getZExtValue() == ExtIdx->getZExtValue()) 7687 return V->getOperand(1); 7688 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, N->getDebugLoc(), NVT, 7689 V->getOperand(0), N->getOperand(1)); 7690 } 7691 } 7692 7693 return SDValue(); 7694} 7695 7696SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) { 7697 EVT VT = N->getValueType(0); 7698 unsigned NumElts = VT.getVectorNumElements(); 7699 7700 SDValue N0 = N->getOperand(0); 7701 SDValue N1 = N->getOperand(1); 7702 7703 assert(N0.getValueType().getVectorNumElements() == NumElts && 7704 "Vector shuffle must be normalized in DAG"); 7705 7706 // Canonicalize shuffle undef, undef -> undef 7707 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF) 7708 return DAG.getUNDEF(VT); 7709 7710 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N); 7711 7712 // Canonicalize shuffle v, v -> v, undef 7713 if (N0 == N1) { 7714 SmallVector<int, 8> NewMask; 7715 for (unsigned i = 0; i != NumElts; ++i) { 7716 int Idx = SVN->getMaskElt(i); 7717 if (Idx >= (int)NumElts) Idx -= NumElts; 7718 NewMask.push_back(Idx); 7719 } 7720 return DAG.getVectorShuffle(VT, N->getDebugLoc(), N0, DAG.getUNDEF(VT), 7721 &NewMask[0]); 7722 } 7723 7724 // Canonicalize shuffle undef, v -> v, undef. Commute the shuffle mask. 7725 if (N0.getOpcode() == ISD::UNDEF) { 7726 SmallVector<int, 8> NewMask; 7727 for (unsigned i = 0; i != NumElts; ++i) { 7728 int Idx = SVN->getMaskElt(i); 7729 if (Idx < 0) 7730 NewMask.push_back(Idx); 7731 else if (Idx < (int)NumElts) 7732 NewMask.push_back(Idx + NumElts); 7733 else 7734 NewMask.push_back(Idx - NumElts); 7735 } 7736 return DAG.getVectorShuffle(VT, N->getDebugLoc(), N1, DAG.getUNDEF(VT), 7737 &NewMask[0]); 7738 } 7739 7740 // Remove references to rhs if it is undef 7741 if (N1.getOpcode() == ISD::UNDEF) { 7742 bool Changed = false; 7743 SmallVector<int, 8> NewMask; 7744 for (unsigned i = 0; i != NumElts; ++i) { 7745 int Idx = SVN->getMaskElt(i); 7746 if (Idx >= (int)NumElts) { 7747 Idx = -1; 7748 Changed = true; 7749 } 7750 NewMask.push_back(Idx); 7751 } 7752 if (Changed) 7753 return DAG.getVectorShuffle(VT, N->getDebugLoc(), N0, N1, &NewMask[0]); 7754 } 7755 7756 // If it is a splat, check if the argument vector is another splat or a 7757 // build_vector with all scalar elements the same. 7758 if (SVN->isSplat() && SVN->getSplatIndex() < (int)NumElts) { 7759 SDNode *V = N0.getNode(); 7760 7761 // If this is a bit convert that changes the element type of the vector but 7762 // not the number of vector elements, look through it. Be careful not to 7763 // look though conversions that change things like v4f32 to v2f64. 7764 if (V->getOpcode() == ISD::BITCAST) { 7765 SDValue ConvInput = V->getOperand(0); 7766 if (ConvInput.getValueType().isVector() && 7767 ConvInput.getValueType().getVectorNumElements() == NumElts) 7768 V = ConvInput.getNode(); 7769 } 7770 7771 if (V->getOpcode() == ISD::BUILD_VECTOR) { 7772 assert(V->getNumOperands() == NumElts && 7773 "BUILD_VECTOR has wrong number of operands"); 7774 SDValue Base; 7775 bool AllSame = true; 7776 for (unsigned i = 0; i != NumElts; ++i) { 7777 if (V->getOperand(i).getOpcode() != ISD::UNDEF) { 7778 Base = V->getOperand(i); 7779 break; 7780 } 7781 } 7782 // Splat of <u, u, u, u>, return <u, u, u, u> 7783 if (!Base.getNode()) 7784 return N0; 7785 for (unsigned i = 0; i != NumElts; ++i) { 7786 if (V->getOperand(i) != Base) { 7787 AllSame = false; 7788 break; 7789 } 7790 } 7791 // Splat of <x, x, x, x>, return <x, x, x, x> 7792 if (AllSame) 7793 return N0; 7794 } 7795 } 7796 7797 // If this shuffle node is simply a swizzle of another shuffle node, 7798 // and it reverses the swizzle of the previous shuffle then we can 7799 // optimize shuffle(shuffle(x, undef), undef) -> x. 7800 if (N0.getOpcode() == ISD::VECTOR_SHUFFLE && Level < AfterLegalizeDAG && 7801 N1.getOpcode() == ISD::UNDEF) { 7802 7803 ShuffleVectorSDNode *OtherSV = cast<ShuffleVectorSDNode>(N0); 7804 7805 // Shuffle nodes can only reverse shuffles with a single non-undef value. 7806 if (N0.getOperand(1).getOpcode() != ISD::UNDEF) 7807 return SDValue(); 7808 7809 // The incoming shuffle must be of the same type as the result of the current 7810 // shuffle. 7811 if (OtherSV->getOperand(0).getValueType() != VT) 7812 return SDValue(); 7813 7814 EVT InVT = N0.getValueType(); 7815 int InNumElts = InVT.getVectorNumElements(); 7816 7817 for (unsigned i = 0; i != NumElts; ++i) { 7818 int Idx = SVN->getMaskElt(i); 7819 // If we access the second (undef) operand then this index can be 7820 // canonicalized to undef as well. 7821 if (Idx >= InNumElts) 7822 Idx = -1; 7823 // Next, this index comes from the first value, which is the incoming 7824 // shuffle. Adopt the incoming index. 7825 if (Idx >= 0) 7826 Idx = OtherSV->getMaskElt(Idx); 7827 7828 // The combined shuffle must map each index to itself. 7829 if (Idx != i && Idx != -1) 7830 return SDValue(); 7831 } 7832 7833 return OtherSV->getOperand(0); 7834 } 7835 7836 return SDValue(); 7837} 7838 7839SDValue DAGCombiner::visitMEMBARRIER(SDNode* N) { 7840 if (!TLI.getShouldFoldAtomicFences()) 7841 return SDValue(); 7842 7843 SDValue atomic = N->getOperand(0); 7844 switch (atomic.getOpcode()) { 7845 case ISD::ATOMIC_CMP_SWAP: 7846 case ISD::ATOMIC_SWAP: 7847 case ISD::ATOMIC_LOAD_ADD: 7848 case ISD::ATOMIC_LOAD_SUB: 7849 case ISD::ATOMIC_LOAD_AND: 7850 case ISD::ATOMIC_LOAD_OR: 7851 case ISD::ATOMIC_LOAD_XOR: 7852 case ISD::ATOMIC_LOAD_NAND: 7853 case ISD::ATOMIC_LOAD_MIN: 7854 case ISD::ATOMIC_LOAD_MAX: 7855 case ISD::ATOMIC_LOAD_UMIN: 7856 case ISD::ATOMIC_LOAD_UMAX: 7857 break; 7858 default: 7859 return SDValue(); 7860 } 7861 7862 SDValue fence = atomic.getOperand(0); 7863 if (fence.getOpcode() != ISD::MEMBARRIER) 7864 return SDValue(); 7865 7866 switch (atomic.getOpcode()) { 7867 case ISD::ATOMIC_CMP_SWAP: 7868 return SDValue(DAG.UpdateNodeOperands(atomic.getNode(), 7869 fence.getOperand(0), 7870 atomic.getOperand(1), atomic.getOperand(2), 7871 atomic.getOperand(3)), atomic.getResNo()); 7872 case ISD::ATOMIC_SWAP: 7873 case ISD::ATOMIC_LOAD_ADD: 7874 case ISD::ATOMIC_LOAD_SUB: 7875 case ISD::ATOMIC_LOAD_AND: 7876 case ISD::ATOMIC_LOAD_OR: 7877 case ISD::ATOMIC_LOAD_XOR: 7878 case ISD::ATOMIC_LOAD_NAND: 7879 case ISD::ATOMIC_LOAD_MIN: 7880 case ISD::ATOMIC_LOAD_MAX: 7881 case ISD::ATOMIC_LOAD_UMIN: 7882 case ISD::ATOMIC_LOAD_UMAX: 7883 return SDValue(DAG.UpdateNodeOperands(atomic.getNode(), 7884 fence.getOperand(0), 7885 atomic.getOperand(1), atomic.getOperand(2)), 7886 atomic.getResNo()); 7887 default: 7888 return SDValue(); 7889 } 7890} 7891 7892/// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform 7893/// an AND to a vector_shuffle with the destination vector and a zero vector. 7894/// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==> 7895/// vector_shuffle V, Zero, <0, 4, 2, 4> 7896SDValue DAGCombiner::XformToShuffleWithZero(SDNode *N) { 7897 EVT VT = N->getValueType(0); 7898 DebugLoc dl = N->getDebugLoc(); 7899 SDValue LHS = N->getOperand(0); 7900 SDValue RHS = N->getOperand(1); 7901 if (N->getOpcode() == ISD::AND) { 7902 if (RHS.getOpcode() == ISD::BITCAST) 7903 RHS = RHS.getOperand(0); 7904 if (RHS.getOpcode() == ISD::BUILD_VECTOR) { 7905 SmallVector<int, 8> Indices; 7906 unsigned NumElts = RHS.getNumOperands(); 7907 for (unsigned i = 0; i != NumElts; ++i) { 7908 SDValue Elt = RHS.getOperand(i); 7909 if (!isa<ConstantSDNode>(Elt)) 7910 return SDValue(); 7911 else if (cast<ConstantSDNode>(Elt)->isAllOnesValue()) 7912 Indices.push_back(i); 7913 else if (cast<ConstantSDNode>(Elt)->isNullValue()) 7914 Indices.push_back(NumElts); 7915 else 7916 return SDValue(); 7917 } 7918 7919 // Let's see if the target supports this vector_shuffle. 7920 EVT RVT = RHS.getValueType(); 7921 if (!TLI.isVectorClearMaskLegal(Indices, RVT)) 7922 return SDValue(); 7923 7924 // Return the new VECTOR_SHUFFLE node. 7925 EVT EltVT = RVT.getVectorElementType(); 7926 SmallVector<SDValue,8> ZeroOps(RVT.getVectorNumElements(), 7927 DAG.getConstant(0, EltVT)); 7928 SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 7929 RVT, &ZeroOps[0], ZeroOps.size()); 7930 LHS = DAG.getNode(ISD::BITCAST, dl, RVT, LHS); 7931 SDValue Shuf = DAG.getVectorShuffle(RVT, dl, LHS, Zero, &Indices[0]); 7932 return DAG.getNode(ISD::BITCAST, dl, VT, Shuf); 7933 } 7934 } 7935 7936 return SDValue(); 7937} 7938 7939/// SimplifyVBinOp - Visit a binary vector operation, like ADD. 7940SDValue DAGCombiner::SimplifyVBinOp(SDNode *N) { 7941 // After legalize, the target may be depending on adds and other 7942 // binary ops to provide legal ways to construct constants or other 7943 // things. Simplifying them may result in a loss of legality. 7944 if (LegalOperations) return SDValue(); 7945 7946 assert(N->getValueType(0).isVector() && 7947 "SimplifyVBinOp only works on vectors!"); 7948 7949 SDValue LHS = N->getOperand(0); 7950 SDValue RHS = N->getOperand(1); 7951 SDValue Shuffle = XformToShuffleWithZero(N); 7952 if (Shuffle.getNode()) return Shuffle; 7953 7954 // If the LHS and RHS are BUILD_VECTOR nodes, see if we can constant fold 7955 // this operation. 7956 if (LHS.getOpcode() == ISD::BUILD_VECTOR && 7957 RHS.getOpcode() == ISD::BUILD_VECTOR) { 7958 SmallVector<SDValue, 8> Ops; 7959 for (unsigned i = 0, e = LHS.getNumOperands(); i != e; ++i) { 7960 SDValue LHSOp = LHS.getOperand(i); 7961 SDValue RHSOp = RHS.getOperand(i); 7962 // If these two elements can't be folded, bail out. 7963 if ((LHSOp.getOpcode() != ISD::UNDEF && 7964 LHSOp.getOpcode() != ISD::Constant && 7965 LHSOp.getOpcode() != ISD::ConstantFP) || 7966 (RHSOp.getOpcode() != ISD::UNDEF && 7967 RHSOp.getOpcode() != ISD::Constant && 7968 RHSOp.getOpcode() != ISD::ConstantFP)) 7969 break; 7970 7971 // Can't fold divide by zero. 7972 if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV || 7973 N->getOpcode() == ISD::FDIV) { 7974 if ((RHSOp.getOpcode() == ISD::Constant && 7975 cast<ConstantSDNode>(RHSOp.getNode())->isNullValue()) || 7976 (RHSOp.getOpcode() == ISD::ConstantFP && 7977 cast<ConstantFPSDNode>(RHSOp.getNode())->getValueAPF().isZero())) 7978 break; 7979 } 7980 7981 EVT VT = LHSOp.getValueType(); 7982 EVT RVT = RHSOp.getValueType(); 7983 if (RVT != VT) { 7984 // Integer BUILD_VECTOR operands may have types larger than the element 7985 // size (e.g., when the element type is not legal). Prior to type 7986 // legalization, the types may not match between the two BUILD_VECTORS. 7987 // Truncate one of the operands to make them match. 7988 if (RVT.getSizeInBits() > VT.getSizeInBits()) { 7989 RHSOp = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, RHSOp); 7990 } else { 7991 LHSOp = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), RVT, LHSOp); 7992 VT = RVT; 7993 } 7994 } 7995 SDValue FoldOp = DAG.getNode(N->getOpcode(), LHS.getDebugLoc(), VT, 7996 LHSOp, RHSOp); 7997 if (FoldOp.getOpcode() != ISD::UNDEF && 7998 FoldOp.getOpcode() != ISD::Constant && 7999 FoldOp.getOpcode() != ISD::ConstantFP) 8000 break; 8001 Ops.push_back(FoldOp); 8002 AddToWorkList(FoldOp.getNode()); 8003 } 8004 8005 if (Ops.size() == LHS.getNumOperands()) 8006 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 8007 LHS.getValueType(), &Ops[0], Ops.size()); 8008 } 8009 8010 return SDValue(); 8011} 8012 8013SDValue DAGCombiner::SimplifySelect(DebugLoc DL, SDValue N0, 8014 SDValue N1, SDValue N2){ 8015 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!"); 8016 8017 SDValue SCC = SimplifySelectCC(DL, N0.getOperand(0), N0.getOperand(1), N1, N2, 8018 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 8019 8020 // If we got a simplified select_cc node back from SimplifySelectCC, then 8021 // break it down into a new SETCC node, and a new SELECT node, and then return 8022 // the SELECT node, since we were called with a SELECT node. 8023 if (SCC.getNode()) { 8024 // Check to see if we got a select_cc back (to turn into setcc/select). 8025 // Otherwise, just return whatever node we got back, like fabs. 8026 if (SCC.getOpcode() == ISD::SELECT_CC) { 8027 SDValue SETCC = DAG.getNode(ISD::SETCC, N0.getDebugLoc(), 8028 N0.getValueType(), 8029 SCC.getOperand(0), SCC.getOperand(1), 8030 SCC.getOperand(4)); 8031 AddToWorkList(SETCC.getNode()); 8032 return DAG.getNode(ISD::SELECT, SCC.getDebugLoc(), SCC.getValueType(), 8033 SCC.getOperand(2), SCC.getOperand(3), SETCC); 8034 } 8035 8036 return SCC; 8037 } 8038 return SDValue(); 8039} 8040 8041/// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS 8042/// are the two values being selected between, see if we can simplify the 8043/// select. Callers of this should assume that TheSelect is deleted if this 8044/// returns true. As such, they should return the appropriate thing (e.g. the 8045/// node) back to the top-level of the DAG combiner loop to avoid it being 8046/// looked at. 8047bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDValue LHS, 8048 SDValue RHS) { 8049 8050 // Cannot simplify select with vector condition 8051 if (TheSelect->getOperand(0).getValueType().isVector()) return false; 8052 8053 // If this is a select from two identical things, try to pull the operation 8054 // through the select. 8055 if (LHS.getOpcode() != RHS.getOpcode() || 8056 !LHS.hasOneUse() || !RHS.hasOneUse()) 8057 return false; 8058 8059 // If this is a load and the token chain is identical, replace the select 8060 // of two loads with a load through a select of the address to load from. 8061 // This triggers in things like "select bool X, 10.0, 123.0" after the FP 8062 // constants have been dropped into the constant pool. 8063 if (LHS.getOpcode() == ISD::LOAD) { 8064 LoadSDNode *LLD = cast<LoadSDNode>(LHS); 8065 LoadSDNode *RLD = cast<LoadSDNode>(RHS); 8066 8067 // Token chains must be identical. 8068 if (LHS.getOperand(0) != RHS.getOperand(0) || 8069 // Do not let this transformation reduce the number of volatile loads. 8070 LLD->isVolatile() || RLD->isVolatile() || 8071 // If this is an EXTLOAD, the VT's must match. 8072 LLD->getMemoryVT() != RLD->getMemoryVT() || 8073 // If this is an EXTLOAD, the kind of extension must match. 8074 (LLD->getExtensionType() != RLD->getExtensionType() && 8075 // The only exception is if one of the extensions is anyext. 8076 LLD->getExtensionType() != ISD::EXTLOAD && 8077 RLD->getExtensionType() != ISD::EXTLOAD) || 8078 // FIXME: this discards src value information. This is 8079 // over-conservative. It would be beneficial to be able to remember 8080 // both potential memory locations. Since we are discarding 8081 // src value info, don't do the transformation if the memory 8082 // locations are not in the default address space. 8083 LLD->getPointerInfo().getAddrSpace() != 0 || 8084 RLD->getPointerInfo().getAddrSpace() != 0) 8085 return false; 8086 8087 // Check that the select condition doesn't reach either load. If so, 8088 // folding this will induce a cycle into the DAG. If not, this is safe to 8089 // xform, so create a select of the addresses. 8090 SDValue Addr; 8091 if (TheSelect->getOpcode() == ISD::SELECT) { 8092 SDNode *CondNode = TheSelect->getOperand(0).getNode(); 8093 if ((LLD->hasAnyUseOfValue(1) && LLD->isPredecessorOf(CondNode)) || 8094 (RLD->hasAnyUseOfValue(1) && RLD->isPredecessorOf(CondNode))) 8095 return false; 8096 Addr = DAG.getNode(ISD::SELECT, TheSelect->getDebugLoc(), 8097 LLD->getBasePtr().getValueType(), 8098 TheSelect->getOperand(0), LLD->getBasePtr(), 8099 RLD->getBasePtr()); 8100 } else { // Otherwise SELECT_CC 8101 SDNode *CondLHS = TheSelect->getOperand(0).getNode(); 8102 SDNode *CondRHS = TheSelect->getOperand(1).getNode(); 8103 8104 if ((LLD->hasAnyUseOfValue(1) && 8105 (LLD->isPredecessorOf(CondLHS) || LLD->isPredecessorOf(CondRHS))) || 8106 (RLD->hasAnyUseOfValue(1) && 8107 (RLD->isPredecessorOf(CondLHS) || RLD->isPredecessorOf(CondRHS)))) 8108 return false; 8109 8110 Addr = DAG.getNode(ISD::SELECT_CC, TheSelect->getDebugLoc(), 8111 LLD->getBasePtr().getValueType(), 8112 TheSelect->getOperand(0), 8113 TheSelect->getOperand(1), 8114 LLD->getBasePtr(), RLD->getBasePtr(), 8115 TheSelect->getOperand(4)); 8116 } 8117 8118 SDValue Load; 8119 if (LLD->getExtensionType() == ISD::NON_EXTLOAD) { 8120 Load = DAG.getLoad(TheSelect->getValueType(0), 8121 TheSelect->getDebugLoc(), 8122 // FIXME: Discards pointer info. 8123 LLD->getChain(), Addr, MachinePointerInfo(), 8124 LLD->isVolatile(), LLD->isNonTemporal(), 8125 LLD->isInvariant(), LLD->getAlignment()); 8126 } else { 8127 Load = DAG.getExtLoad(LLD->getExtensionType() == ISD::EXTLOAD ? 8128 RLD->getExtensionType() : LLD->getExtensionType(), 8129 TheSelect->getDebugLoc(), 8130 TheSelect->getValueType(0), 8131 // FIXME: Discards pointer info. 8132 LLD->getChain(), Addr, MachinePointerInfo(), 8133 LLD->getMemoryVT(), LLD->isVolatile(), 8134 LLD->isNonTemporal(), LLD->getAlignment()); 8135 } 8136 8137 // Users of the select now use the result of the load. 8138 CombineTo(TheSelect, Load); 8139 8140 // Users of the old loads now use the new load's chain. We know the 8141 // old-load value is dead now. 8142 CombineTo(LHS.getNode(), Load.getValue(0), Load.getValue(1)); 8143 CombineTo(RHS.getNode(), Load.getValue(0), Load.getValue(1)); 8144 return true; 8145 } 8146 8147 return false; 8148} 8149 8150/// SimplifySelectCC - Simplify an expression of the form (N0 cond N1) ? N2 : N3 8151/// where 'cond' is the comparison specified by CC. 8152SDValue DAGCombiner::SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, 8153 SDValue N2, SDValue N3, 8154 ISD::CondCode CC, bool NotExtCompare) { 8155 // (x ? y : y) -> y. 8156 if (N2 == N3) return N2; 8157 8158 EVT VT = N2.getValueType(); 8159 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 8160 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode()); 8161 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.getNode()); 8162 8163 // Determine if the condition we're dealing with is constant 8164 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()), 8165 N0, N1, CC, DL, false); 8166 if (SCC.getNode()) AddToWorkList(SCC.getNode()); 8167 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode()); 8168 8169 // fold select_cc true, x, y -> x 8170 if (SCCC && !SCCC->isNullValue()) 8171 return N2; 8172 // fold select_cc false, x, y -> y 8173 if (SCCC && SCCC->isNullValue()) 8174 return N3; 8175 8176 // Check to see if we can simplify the select into an fabs node 8177 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) { 8178 // Allow either -0.0 or 0.0 8179 if (CFP->getValueAPF().isZero()) { 8180 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs 8181 if ((CC == ISD::SETGE || CC == ISD::SETGT) && 8182 N0 == N2 && N3.getOpcode() == ISD::FNEG && 8183 N2 == N3.getOperand(0)) 8184 return DAG.getNode(ISD::FABS, DL, VT, N0); 8185 8186 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs 8187 if ((CC == ISD::SETLT || CC == ISD::SETLE) && 8188 N0 == N3 && N2.getOpcode() == ISD::FNEG && 8189 N2.getOperand(0) == N3) 8190 return DAG.getNode(ISD::FABS, DL, VT, N3); 8191 } 8192 } 8193 8194 // Turn "(a cond b) ? 1.0f : 2.0f" into "load (tmp + ((a cond b) ? 0 : 4)" 8195 // where "tmp" is a constant pool entry containing an array with 1.0 and 2.0 8196 // in it. This is a win when the constant is not otherwise available because 8197 // it replaces two constant pool loads with one. We only do this if the FP 8198 // type is known to be legal, because if it isn't, then we are before legalize 8199 // types an we want the other legalization to happen first (e.g. to avoid 8200 // messing with soft float) and if the ConstantFP is not legal, because if 8201 // it is legal, we may not need to store the FP constant in a constant pool. 8202 if (ConstantFPSDNode *TV = dyn_cast<ConstantFPSDNode>(N2)) 8203 if (ConstantFPSDNode *FV = dyn_cast<ConstantFPSDNode>(N3)) { 8204 if (TLI.isTypeLegal(N2.getValueType()) && 8205 (TLI.getOperationAction(ISD::ConstantFP, N2.getValueType()) != 8206 TargetLowering::Legal) && 8207 // If both constants have multiple uses, then we won't need to do an 8208 // extra load, they are likely around in registers for other users. 8209 (TV->hasOneUse() || FV->hasOneUse())) { 8210 Constant *Elts[] = { 8211 const_cast<ConstantFP*>(FV->getConstantFPValue()), 8212 const_cast<ConstantFP*>(TV->getConstantFPValue()) 8213 }; 8214 Type *FPTy = Elts[0]->getType(); 8215 const TargetData &TD = *TLI.getTargetData(); 8216 8217 // Create a ConstantArray of the two constants. 8218 Constant *CA = ConstantArray::get(ArrayType::get(FPTy, 2), Elts); 8219 SDValue CPIdx = DAG.getConstantPool(CA, TLI.getPointerTy(), 8220 TD.getPrefTypeAlignment(FPTy)); 8221 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 8222 8223 // Get the offsets to the 0 and 1 element of the array so that we can 8224 // select between them. 8225 SDValue Zero = DAG.getIntPtrConstant(0); 8226 unsigned EltSize = (unsigned)TD.getTypeAllocSize(Elts[0]->getType()); 8227 SDValue One = DAG.getIntPtrConstant(EltSize); 8228 8229 SDValue Cond = DAG.getSetCC(DL, 8230 TLI.getSetCCResultType(N0.getValueType()), 8231 N0, N1, CC); 8232 AddToWorkList(Cond.getNode()); 8233 SDValue CstOffset = DAG.getNode(ISD::SELECT, DL, Zero.getValueType(), 8234 Cond, One, Zero); 8235 AddToWorkList(CstOffset.getNode()); 8236 CPIdx = DAG.getNode(ISD::ADD, DL, TLI.getPointerTy(), CPIdx, 8237 CstOffset); 8238 AddToWorkList(CPIdx.getNode()); 8239 return DAG.getLoad(TV->getValueType(0), DL, DAG.getEntryNode(), CPIdx, 8240 MachinePointerInfo::getConstantPool(), false, 8241 false, false, Alignment); 8242 8243 } 8244 } 8245 8246 // Check to see if we can perform the "gzip trick", transforming 8247 // (select_cc setlt X, 0, A, 0) -> (and (sra X, (sub size(X), 1), A) 8248 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT && 8249 (N1C->isNullValue() || // (a < 0) ? b : 0 8250 (N1C->getAPIntValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0 8251 EVT XType = N0.getValueType(); 8252 EVT AType = N2.getValueType(); 8253 if (XType.bitsGE(AType)) { 8254 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a 8255 // single-bit constant. 8256 if (N2C && ((N2C->getAPIntValue() & (N2C->getAPIntValue()-1)) == 0)) { 8257 unsigned ShCtV = N2C->getAPIntValue().logBase2(); 8258 ShCtV = XType.getSizeInBits()-ShCtV-1; 8259 SDValue ShCt = DAG.getConstant(ShCtV, 8260 getShiftAmountTy(N0.getValueType())); 8261 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), 8262 XType, N0, ShCt); 8263 AddToWorkList(Shift.getNode()); 8264 8265 if (XType.bitsGT(AType)) { 8266 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift); 8267 AddToWorkList(Shift.getNode()); 8268 } 8269 8270 return DAG.getNode(ISD::AND, DL, AType, Shift, N2); 8271 } 8272 8273 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), 8274 XType, N0, 8275 DAG.getConstant(XType.getSizeInBits()-1, 8276 getShiftAmountTy(N0.getValueType()))); 8277 AddToWorkList(Shift.getNode()); 8278 8279 if (XType.bitsGT(AType)) { 8280 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift); 8281 AddToWorkList(Shift.getNode()); 8282 } 8283 8284 return DAG.getNode(ISD::AND, DL, AType, Shift, N2); 8285 } 8286 } 8287 8288 // fold (select_cc seteq (and x, y), 0, 0, A) -> (and (shr (shl x)) A) 8289 // where y is has a single bit set. 8290 // A plaintext description would be, we can turn the SELECT_CC into an AND 8291 // when the condition can be materialized as an all-ones register. Any 8292 // single bit-test can be materialized as an all-ones register with 8293 // shift-left and shift-right-arith. 8294 if (CC == ISD::SETEQ && N0->getOpcode() == ISD::AND && 8295 N0->getValueType(0) == VT && 8296 N1C && N1C->isNullValue() && 8297 N2C && N2C->isNullValue()) { 8298 SDValue AndLHS = N0->getOperand(0); 8299 ConstantSDNode *ConstAndRHS = dyn_cast<ConstantSDNode>(N0->getOperand(1)); 8300 if (ConstAndRHS && ConstAndRHS->getAPIntValue().countPopulation() == 1) { 8301 // Shift the tested bit over the sign bit. 8302 APInt AndMask = ConstAndRHS->getAPIntValue(); 8303 SDValue ShlAmt = 8304 DAG.getConstant(AndMask.countLeadingZeros(), 8305 getShiftAmountTy(AndLHS.getValueType())); 8306 SDValue Shl = DAG.getNode(ISD::SHL, N0.getDebugLoc(), VT, AndLHS, ShlAmt); 8307 8308 // Now arithmetic right shift it all the way over, so the result is either 8309 // all-ones, or zero. 8310 SDValue ShrAmt = 8311 DAG.getConstant(AndMask.getBitWidth()-1, 8312 getShiftAmountTy(Shl.getValueType())); 8313 SDValue Shr = DAG.getNode(ISD::SRA, N0.getDebugLoc(), VT, Shl, ShrAmt); 8314 8315 return DAG.getNode(ISD::AND, DL, VT, Shr, N3); 8316 } 8317 } 8318 8319 // fold select C, 16, 0 -> shl C, 4 8320 if (N2C && N3C && N3C->isNullValue() && N2C->getAPIntValue().isPowerOf2() && 8321 TLI.getBooleanContents(N0.getValueType().isVector()) == 8322 TargetLowering::ZeroOrOneBooleanContent) { 8323 8324 // If the caller doesn't want us to simplify this into a zext of a compare, 8325 // don't do it. 8326 if (NotExtCompare && N2C->getAPIntValue() == 1) 8327 return SDValue(); 8328 8329 // Get a SetCC of the condition 8330 // FIXME: Should probably make sure that setcc is legal if we ever have a 8331 // target where it isn't. 8332 SDValue Temp, SCC; 8333 // cast from setcc result type to select result type 8334 if (LegalTypes) { 8335 SCC = DAG.getSetCC(DL, TLI.getSetCCResultType(N0.getValueType()), 8336 N0, N1, CC); 8337 if (N2.getValueType().bitsLT(SCC.getValueType())) 8338 Temp = DAG.getZeroExtendInReg(SCC, N2.getDebugLoc(), N2.getValueType()); 8339 else 8340 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(), 8341 N2.getValueType(), SCC); 8342 } else { 8343 SCC = DAG.getSetCC(N0.getDebugLoc(), MVT::i1, N0, N1, CC); 8344 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(), 8345 N2.getValueType(), SCC); 8346 } 8347 8348 AddToWorkList(SCC.getNode()); 8349 AddToWorkList(Temp.getNode()); 8350 8351 if (N2C->getAPIntValue() == 1) 8352 return Temp; 8353 8354 // shl setcc result by log2 n2c 8355 return DAG.getNode(ISD::SHL, DL, N2.getValueType(), Temp, 8356 DAG.getConstant(N2C->getAPIntValue().logBase2(), 8357 getShiftAmountTy(Temp.getValueType()))); 8358 } 8359 8360 // Check to see if this is the equivalent of setcc 8361 // FIXME: Turn all of these into setcc if setcc if setcc is legal 8362 // otherwise, go ahead with the folds. 8363 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getAPIntValue() == 1ULL)) { 8364 EVT XType = N0.getValueType(); 8365 if (!LegalOperations || 8366 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(XType))) { 8367 SDValue Res = DAG.getSetCC(DL, TLI.getSetCCResultType(XType), N0, N1, CC); 8368 if (Res.getValueType() != VT) 8369 Res = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, Res); 8370 return Res; 8371 } 8372 8373 // fold (seteq X, 0) -> (srl (ctlz X, log2(size(X)))) 8374 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ && 8375 (!LegalOperations || 8376 TLI.isOperationLegal(ISD::CTLZ, XType))) { 8377 SDValue Ctlz = DAG.getNode(ISD::CTLZ, N0.getDebugLoc(), XType, N0); 8378 return DAG.getNode(ISD::SRL, DL, XType, Ctlz, 8379 DAG.getConstant(Log2_32(XType.getSizeInBits()), 8380 getShiftAmountTy(Ctlz.getValueType()))); 8381 } 8382 // fold (setgt X, 0) -> (srl (and (-X, ~X), size(X)-1)) 8383 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) { 8384 SDValue NegN0 = DAG.getNode(ISD::SUB, N0.getDebugLoc(), 8385 XType, DAG.getConstant(0, XType), N0); 8386 SDValue NotN0 = DAG.getNOT(N0.getDebugLoc(), N0, XType); 8387 return DAG.getNode(ISD::SRL, DL, XType, 8388 DAG.getNode(ISD::AND, DL, XType, NegN0, NotN0), 8389 DAG.getConstant(XType.getSizeInBits()-1, 8390 getShiftAmountTy(XType))); 8391 } 8392 // fold (setgt X, -1) -> (xor (srl (X, size(X)-1), 1)) 8393 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) { 8394 SDValue Sign = DAG.getNode(ISD::SRL, N0.getDebugLoc(), XType, N0, 8395 DAG.getConstant(XType.getSizeInBits()-1, 8396 getShiftAmountTy(N0.getValueType()))); 8397 return DAG.getNode(ISD::XOR, DL, XType, Sign, DAG.getConstant(1, XType)); 8398 } 8399 } 8400 8401 // Check to see if this is an integer abs. 8402 // select_cc setg[te] X, 0, X, -X -> 8403 // select_cc setgt X, -1, X, -X -> 8404 // select_cc setl[te] X, 0, -X, X -> 8405 // select_cc setlt X, 1, -X, X -> 8406 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 8407 if (N1C) { 8408 ConstantSDNode *SubC = NULL; 8409 if (((N1C->isNullValue() && (CC == ISD::SETGT || CC == ISD::SETGE)) || 8410 (N1C->isAllOnesValue() && CC == ISD::SETGT)) && 8411 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1)) 8412 SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0)); 8413 else if (((N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE)) || 8414 (N1C->isOne() && CC == ISD::SETLT)) && 8415 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1)) 8416 SubC = dyn_cast<ConstantSDNode>(N2.getOperand(0)); 8417 8418 EVT XType = N0.getValueType(); 8419 if (SubC && SubC->isNullValue() && XType.isInteger()) { 8420 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), XType, 8421 N0, 8422 DAG.getConstant(XType.getSizeInBits()-1, 8423 getShiftAmountTy(N0.getValueType()))); 8424 SDValue Add = DAG.getNode(ISD::ADD, N0.getDebugLoc(), 8425 XType, N0, Shift); 8426 AddToWorkList(Shift.getNode()); 8427 AddToWorkList(Add.getNode()); 8428 return DAG.getNode(ISD::XOR, DL, XType, Add, Shift); 8429 } 8430 } 8431 8432 return SDValue(); 8433} 8434 8435/// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC. 8436SDValue DAGCombiner::SimplifySetCC(EVT VT, SDValue N0, 8437 SDValue N1, ISD::CondCode Cond, 8438 DebugLoc DL, bool foldBooleans) { 8439 TargetLowering::DAGCombinerInfo 8440 DagCombineInfo(DAG, !LegalTypes, !LegalOperations, false, this); 8441 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo, DL); 8442} 8443 8444/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 8445/// return a DAG expression to select that will generate the same value by 8446/// multiplying by a magic number. See: 8447/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 8448SDValue DAGCombiner::BuildSDIV(SDNode *N) { 8449 std::vector<SDNode*> Built; 8450 SDValue S = TLI.BuildSDIV(N, DAG, LegalOperations, &Built); 8451 8452 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 8453 ii != ee; ++ii) 8454 AddToWorkList(*ii); 8455 return S; 8456} 8457 8458/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 8459/// return a DAG expression to select that will generate the same value by 8460/// multiplying by a magic number. See: 8461/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 8462SDValue DAGCombiner::BuildUDIV(SDNode *N) { 8463 std::vector<SDNode*> Built; 8464 SDValue S = TLI.BuildUDIV(N, DAG, LegalOperations, &Built); 8465 8466 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 8467 ii != ee; ++ii) 8468 AddToWorkList(*ii); 8469 return S; 8470} 8471 8472/// FindBaseOffset - Return true if base is a frame index, which is known not 8473// to alias with anything but itself. Provides base object and offset as 8474// results. 8475static bool FindBaseOffset(SDValue Ptr, SDValue &Base, int64_t &Offset, 8476 const GlobalValue *&GV, void *&CV) { 8477 // Assume it is a primitive operation. 8478 Base = Ptr; Offset = 0; GV = 0; CV = 0; 8479 8480 // If it's an adding a simple constant then integrate the offset. 8481 if (Base.getOpcode() == ISD::ADD) { 8482 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) { 8483 Base = Base.getOperand(0); 8484 Offset += C->getZExtValue(); 8485 } 8486 } 8487 8488 // Return the underlying GlobalValue, and update the Offset. Return false 8489 // for GlobalAddressSDNode since the same GlobalAddress may be represented 8490 // by multiple nodes with different offsets. 8491 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Base)) { 8492 GV = G->getGlobal(); 8493 Offset += G->getOffset(); 8494 return false; 8495 } 8496 8497 // Return the underlying Constant value, and update the Offset. Return false 8498 // for ConstantSDNodes since the same constant pool entry may be represented 8499 // by multiple nodes with different offsets. 8500 if (ConstantPoolSDNode *C = dyn_cast<ConstantPoolSDNode>(Base)) { 8501 CV = C->isMachineConstantPoolEntry() ? (void *)C->getMachineCPVal() 8502 : (void *)C->getConstVal(); 8503 Offset += C->getOffset(); 8504 return false; 8505 } 8506 // If it's any of the following then it can't alias with anything but itself. 8507 return isa<FrameIndexSDNode>(Base); 8508} 8509 8510/// isAlias - Return true if there is any possibility that the two addresses 8511/// overlap. 8512bool DAGCombiner::isAlias(SDValue Ptr1, int64_t Size1, 8513 const Value *SrcValue1, int SrcValueOffset1, 8514 unsigned SrcValueAlign1, 8515 const MDNode *TBAAInfo1, 8516 SDValue Ptr2, int64_t Size2, 8517 const Value *SrcValue2, int SrcValueOffset2, 8518 unsigned SrcValueAlign2, 8519 const MDNode *TBAAInfo2) const { 8520 // If they are the same then they must be aliases. 8521 if (Ptr1 == Ptr2) return true; 8522 8523 // Gather base node and offset information. 8524 SDValue Base1, Base2; 8525 int64_t Offset1, Offset2; 8526 const GlobalValue *GV1, *GV2; 8527 void *CV1, *CV2; 8528 bool isFrameIndex1 = FindBaseOffset(Ptr1, Base1, Offset1, GV1, CV1); 8529 bool isFrameIndex2 = FindBaseOffset(Ptr2, Base2, Offset2, GV2, CV2); 8530 8531 // If they have a same base address then check to see if they overlap. 8532 if (Base1 == Base2 || (GV1 && (GV1 == GV2)) || (CV1 && (CV1 == CV2))) 8533 return !((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1); 8534 8535 // It is possible for different frame indices to alias each other, mostly 8536 // when tail call optimization reuses return address slots for arguments. 8537 // To catch this case, look up the actual index of frame indices to compute 8538 // the real alias relationship. 8539 if (isFrameIndex1 && isFrameIndex2) { 8540 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 8541 Offset1 += MFI->getObjectOffset(cast<FrameIndexSDNode>(Base1)->getIndex()); 8542 Offset2 += MFI->getObjectOffset(cast<FrameIndexSDNode>(Base2)->getIndex()); 8543 return !((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1); 8544 } 8545 8546 // Otherwise, if we know what the bases are, and they aren't identical, then 8547 // we know they cannot alias. 8548 if ((isFrameIndex1 || CV1 || GV1) && (isFrameIndex2 || CV2 || GV2)) 8549 return false; 8550 8551 // If we know required SrcValue1 and SrcValue2 have relatively large alignment 8552 // compared to the size and offset of the access, we may be able to prove they 8553 // do not alias. This check is conservative for now to catch cases created by 8554 // splitting vector types. 8555 if ((SrcValueAlign1 == SrcValueAlign2) && 8556 (SrcValueOffset1 != SrcValueOffset2) && 8557 (Size1 == Size2) && (SrcValueAlign1 > Size1)) { 8558 int64_t OffAlign1 = SrcValueOffset1 % SrcValueAlign1; 8559 int64_t OffAlign2 = SrcValueOffset2 % SrcValueAlign1; 8560 8561 // There is no overlap between these relatively aligned accesses of similar 8562 // size, return no alias. 8563 if ((OffAlign1 + Size1) <= OffAlign2 || (OffAlign2 + Size2) <= OffAlign1) 8564 return false; 8565 } 8566 8567 if (CombinerGlobalAA) { 8568 // Use alias analysis information. 8569 int64_t MinOffset = std::min(SrcValueOffset1, SrcValueOffset2); 8570 int64_t Overlap1 = Size1 + SrcValueOffset1 - MinOffset; 8571 int64_t Overlap2 = Size2 + SrcValueOffset2 - MinOffset; 8572 AliasAnalysis::AliasResult AAResult = 8573 AA.alias(AliasAnalysis::Location(SrcValue1, Overlap1, TBAAInfo1), 8574 AliasAnalysis::Location(SrcValue2, Overlap2, TBAAInfo2)); 8575 if (AAResult == AliasAnalysis::NoAlias) 8576 return false; 8577 } 8578 8579 // Otherwise we have to assume they alias. 8580 return true; 8581} 8582 8583/// FindAliasInfo - Extracts the relevant alias information from the memory 8584/// node. Returns true if the operand was a load. 8585bool DAGCombiner::FindAliasInfo(SDNode *N, 8586 SDValue &Ptr, int64_t &Size, 8587 const Value *&SrcValue, 8588 int &SrcValueOffset, 8589 unsigned &SrcValueAlign, 8590 const MDNode *&TBAAInfo) const { 8591 LSBaseSDNode *LS = cast<LSBaseSDNode>(N); 8592 8593 Ptr = LS->getBasePtr(); 8594 Size = LS->getMemoryVT().getSizeInBits() >> 3; 8595 SrcValue = LS->getSrcValue(); 8596 SrcValueOffset = LS->getSrcValueOffset(); 8597 SrcValueAlign = LS->getOriginalAlignment(); 8598 TBAAInfo = LS->getTBAAInfo(); 8599 return isa<LoadSDNode>(LS); 8600} 8601 8602/// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 8603/// looking for aliasing nodes and adding them to the Aliases vector. 8604void DAGCombiner::GatherAllAliases(SDNode *N, SDValue OriginalChain, 8605 SmallVector<SDValue, 8> &Aliases) { 8606 SmallVector<SDValue, 8> Chains; // List of chains to visit. 8607 SmallPtrSet<SDNode *, 16> Visited; // Visited node set. 8608 8609 // Get alias information for node. 8610 SDValue Ptr; 8611 int64_t Size; 8612 const Value *SrcValue; 8613 int SrcValueOffset; 8614 unsigned SrcValueAlign; 8615 const MDNode *SrcTBAAInfo; 8616 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset, 8617 SrcValueAlign, SrcTBAAInfo); 8618 8619 // Starting off. 8620 Chains.push_back(OriginalChain); 8621 unsigned Depth = 0; 8622 8623 // Look at each chain and determine if it is an alias. If so, add it to the 8624 // aliases list. If not, then continue up the chain looking for the next 8625 // candidate. 8626 while (!Chains.empty()) { 8627 SDValue Chain = Chains.back(); 8628 Chains.pop_back(); 8629 8630 // For TokenFactor nodes, look at each operand and only continue up the 8631 // chain until we find two aliases. If we've seen two aliases, assume we'll 8632 // find more and revert to original chain since the xform is unlikely to be 8633 // profitable. 8634 // 8635 // FIXME: The depth check could be made to return the last non-aliasing 8636 // chain we found before we hit a tokenfactor rather than the original 8637 // chain. 8638 if (Depth > 6 || Aliases.size() == 2) { 8639 Aliases.clear(); 8640 Aliases.push_back(OriginalChain); 8641 break; 8642 } 8643 8644 // Don't bother if we've been before. 8645 if (!Visited.insert(Chain.getNode())) 8646 continue; 8647 8648 switch (Chain.getOpcode()) { 8649 case ISD::EntryToken: 8650 // Entry token is ideal chain operand, but handled in FindBetterChain. 8651 break; 8652 8653 case ISD::LOAD: 8654 case ISD::STORE: { 8655 // Get alias information for Chain. 8656 SDValue OpPtr; 8657 int64_t OpSize; 8658 const Value *OpSrcValue; 8659 int OpSrcValueOffset; 8660 unsigned OpSrcValueAlign; 8661 const MDNode *OpSrcTBAAInfo; 8662 bool IsOpLoad = FindAliasInfo(Chain.getNode(), OpPtr, OpSize, 8663 OpSrcValue, OpSrcValueOffset, 8664 OpSrcValueAlign, 8665 OpSrcTBAAInfo); 8666 8667 // If chain is alias then stop here. 8668 if (!(IsLoad && IsOpLoad) && 8669 isAlias(Ptr, Size, SrcValue, SrcValueOffset, SrcValueAlign, 8670 SrcTBAAInfo, 8671 OpPtr, OpSize, OpSrcValue, OpSrcValueOffset, 8672 OpSrcValueAlign, OpSrcTBAAInfo)) { 8673 Aliases.push_back(Chain); 8674 } else { 8675 // Look further up the chain. 8676 Chains.push_back(Chain.getOperand(0)); 8677 ++Depth; 8678 } 8679 break; 8680 } 8681 8682 case ISD::TokenFactor: 8683 // We have to check each of the operands of the token factor for "small" 8684 // token factors, so we queue them up. Adding the operands to the queue 8685 // (stack) in reverse order maintains the original order and increases the 8686 // likelihood that getNode will find a matching token factor (CSE.) 8687 if (Chain.getNumOperands() > 16) { 8688 Aliases.push_back(Chain); 8689 break; 8690 } 8691 for (unsigned n = Chain.getNumOperands(); n;) 8692 Chains.push_back(Chain.getOperand(--n)); 8693 ++Depth; 8694 break; 8695 8696 default: 8697 // For all other instructions we will just have to take what we can get. 8698 Aliases.push_back(Chain); 8699 break; 8700 } 8701 } 8702} 8703 8704/// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking 8705/// for a better chain (aliasing node.) 8706SDValue DAGCombiner::FindBetterChain(SDNode *N, SDValue OldChain) { 8707 SmallVector<SDValue, 8> Aliases; // Ops for replacing token factor. 8708 8709 // Accumulate all the aliases to this node. 8710 GatherAllAliases(N, OldChain, Aliases); 8711 8712 // If no operands then chain to entry token. 8713 if (Aliases.size() == 0) 8714 return DAG.getEntryNode(); 8715 8716 // If a single operand then chain to it. We don't need to revisit it. 8717 if (Aliases.size() == 1) 8718 return Aliases[0]; 8719 8720 // Construct a custom tailored token factor. 8721 return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, 8722 &Aliases[0], Aliases.size()); 8723} 8724 8725// SelectionDAG::Combine - This is the entry point for the file. 8726// 8727void SelectionDAG::Combine(CombineLevel Level, AliasAnalysis &AA, 8728 CodeGenOpt::Level OptLevel) { 8729 /// run - This is the main entry point to this class. 8730 /// 8731 DAGCombiner(*this, AA, OptLevel).Run(Level); 8732} 8733