DAGCombiner.cpp revision d693cafcfb9e67ba7040cb810e4409a166421482
1//===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run 11// both before and after the DAG is legalized. 12// 13// This pass is not a substitute for the LLVM IR instcombine pass. This pass is 14// primarily intended to handle simplification opportunities that are implicit 15// in the LLVM IR and exposed by the various codegen lowering phases. 16// 17//===----------------------------------------------------------------------===// 18 19#define DEBUG_TYPE "dagcombine" 20#include "llvm/CodeGen/SelectionDAG.h" 21#include "llvm/DerivedTypes.h" 22#include "llvm/LLVMContext.h" 23#include "llvm/CodeGen/MachineFunction.h" 24#include "llvm/CodeGen/MachineFrameInfo.h" 25#include "llvm/Analysis/AliasAnalysis.h" 26#include "llvm/Target/TargetData.h" 27#include "llvm/Target/TargetLowering.h" 28#include "llvm/Target/TargetMachine.h" 29#include "llvm/Target/TargetOptions.h" 30#include "llvm/ADT/SmallPtrSet.h" 31#include "llvm/ADT/Statistic.h" 32#include "llvm/Support/CommandLine.h" 33#include "llvm/Support/Debug.h" 34#include "llvm/Support/ErrorHandling.h" 35#include "llvm/Support/MathExtras.h" 36#include "llvm/Support/raw_ostream.h" 37#include <algorithm> 38using namespace llvm; 39 40STATISTIC(NodesCombined , "Number of dag nodes combined"); 41STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created"); 42STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created"); 43STATISTIC(OpsNarrowed , "Number of load/op/store narrowed"); 44STATISTIC(LdStFP2Int , "Number of fp load/store pairs transformed to int"); 45 46namespace { 47 static cl::opt<bool> 48 CombinerAA("combiner-alias-analysis", cl::Hidden, 49 cl::desc("Turn on alias analysis during testing")); 50 51 static cl::opt<bool> 52 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden, 53 cl::desc("Include global information in alias analysis")); 54 55//------------------------------ DAGCombiner ---------------------------------// 56 57 class DAGCombiner { 58 SelectionDAG &DAG; 59 const TargetLowering &TLI; 60 CombineLevel Level; 61 CodeGenOpt::Level OptLevel; 62 bool LegalOperations; 63 bool LegalTypes; 64 65 // Worklist of all of the nodes that need to be simplified. 66 // 67 // This has the semantics that when adding to the worklist, 68 // the item added must be next to be processed. It should 69 // also only appear once. The naive approach to this takes 70 // linear time. 71 // 72 // To reduce the insert/remove time to logarithmic, we use 73 // a set and a vector to maintain our worklist. 74 // 75 // The set contains the items on the worklist, but does not 76 // maintain the order they should be visited. 77 // 78 // The vector maintains the order nodes should be visited, but may 79 // contain duplicate or removed nodes. When choosing a node to 80 // visit, we pop off the order stack until we find an item that is 81 // also in the contents set. All operations are O(log N). 82 SmallPtrSet<SDNode*, 64> WorkListContents; 83 SmallVector<SDNode*, 64> WorkListOrder; 84 85 // AA - Used for DAG load/store alias analysis. 86 AliasAnalysis &AA; 87 88 /// AddUsersToWorkList - When an instruction is simplified, add all users of 89 /// the instruction to the work lists because they might get more simplified 90 /// now. 91 /// 92 void AddUsersToWorkList(SDNode *N) { 93 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 94 UI != UE; ++UI) 95 AddToWorkList(*UI); 96 } 97 98 /// visit - call the node-specific routine that knows how to fold each 99 /// particular type of node. 100 SDValue visit(SDNode *N); 101 102 public: 103 /// AddToWorkList - Add to the work list making sure its instance is at the 104 /// back (next to be processed.) 105 void AddToWorkList(SDNode *N) { 106 WorkListContents.insert(N); 107 WorkListOrder.push_back(N); 108 } 109 110 /// removeFromWorkList - remove all instances of N from the worklist. 111 /// 112 void removeFromWorkList(SDNode *N) { 113 WorkListContents.erase(N); 114 } 115 116 SDValue CombineTo(SDNode *N, const SDValue *To, unsigned NumTo, 117 bool AddTo = true); 118 119 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true) { 120 return CombineTo(N, &Res, 1, AddTo); 121 } 122 123 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, 124 bool AddTo = true) { 125 SDValue To[] = { Res0, Res1 }; 126 return CombineTo(N, To, 2, AddTo); 127 } 128 129 void CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO); 130 131 private: 132 133 /// SimplifyDemandedBits - Check the specified integer node value to see if 134 /// it can be simplified or if things it uses can be simplified by bit 135 /// propagation. If so, return true. 136 bool SimplifyDemandedBits(SDValue Op) { 137 unsigned BitWidth = Op.getValueType().getScalarType().getSizeInBits(); 138 APInt Demanded = APInt::getAllOnesValue(BitWidth); 139 return SimplifyDemandedBits(Op, Demanded); 140 } 141 142 bool SimplifyDemandedBits(SDValue Op, const APInt &Demanded); 143 144 bool CombineToPreIndexedLoadStore(SDNode *N); 145 bool CombineToPostIndexedLoadStore(SDNode *N); 146 147 void ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad); 148 SDValue PromoteOperand(SDValue Op, EVT PVT, bool &Replace); 149 SDValue SExtPromoteOperand(SDValue Op, EVT PVT); 150 SDValue ZExtPromoteOperand(SDValue Op, EVT PVT); 151 SDValue PromoteIntBinOp(SDValue Op); 152 SDValue PromoteIntShiftOp(SDValue Op); 153 SDValue PromoteExtend(SDValue Op); 154 bool PromoteLoad(SDValue Op); 155 156 void ExtendSetCCUses(SmallVector<SDNode*, 4> SetCCs, 157 SDValue Trunc, SDValue ExtLoad, DebugLoc DL, 158 ISD::NodeType ExtType); 159 160 /// combine - call the node-specific routine that knows how to fold each 161 /// particular type of node. If that doesn't do anything, try the 162 /// target-specific DAG combines. 163 SDValue combine(SDNode *N); 164 165 // Visitation implementation - Implement dag node combining for different 166 // node types. The semantics are as follows: 167 // Return Value: 168 // SDValue.getNode() == 0 - No change was made 169 // SDValue.getNode() == N - N was replaced, is dead and has been handled. 170 // otherwise - N should be replaced by the returned Operand. 171 // 172 SDValue visitTokenFactor(SDNode *N); 173 SDValue visitMERGE_VALUES(SDNode *N); 174 SDValue visitADD(SDNode *N); 175 SDValue visitSUB(SDNode *N); 176 SDValue visitADDC(SDNode *N); 177 SDValue visitSUBC(SDNode *N); 178 SDValue visitADDE(SDNode *N); 179 SDValue visitSUBE(SDNode *N); 180 SDValue visitMUL(SDNode *N); 181 SDValue visitSDIV(SDNode *N); 182 SDValue visitUDIV(SDNode *N); 183 SDValue visitSREM(SDNode *N); 184 SDValue visitUREM(SDNode *N); 185 SDValue visitMULHU(SDNode *N); 186 SDValue visitMULHS(SDNode *N); 187 SDValue visitSMUL_LOHI(SDNode *N); 188 SDValue visitUMUL_LOHI(SDNode *N); 189 SDValue visitSMULO(SDNode *N); 190 SDValue visitUMULO(SDNode *N); 191 SDValue visitSDIVREM(SDNode *N); 192 SDValue visitUDIVREM(SDNode *N); 193 SDValue visitAND(SDNode *N); 194 SDValue visitOR(SDNode *N); 195 SDValue visitXOR(SDNode *N); 196 SDValue SimplifyVBinOp(SDNode *N); 197 SDValue visitSHL(SDNode *N); 198 SDValue visitSRA(SDNode *N); 199 SDValue visitSRL(SDNode *N); 200 SDValue visitCTLZ(SDNode *N); 201 SDValue visitCTLZ_ZERO_UNDEF(SDNode *N); 202 SDValue visitCTTZ(SDNode *N); 203 SDValue visitCTTZ_ZERO_UNDEF(SDNode *N); 204 SDValue visitCTPOP(SDNode *N); 205 SDValue visitSELECT(SDNode *N); 206 SDValue visitSELECT_CC(SDNode *N); 207 SDValue visitSETCC(SDNode *N); 208 SDValue visitSIGN_EXTEND(SDNode *N); 209 SDValue visitZERO_EXTEND(SDNode *N); 210 SDValue visitANY_EXTEND(SDNode *N); 211 SDValue visitSIGN_EXTEND_INREG(SDNode *N); 212 SDValue visitTRUNCATE(SDNode *N); 213 SDValue visitBITCAST(SDNode *N); 214 SDValue visitBUILD_PAIR(SDNode *N); 215 SDValue visitFADD(SDNode *N); 216 SDValue visitFSUB(SDNode *N); 217 SDValue visitFMUL(SDNode *N); 218 SDValue visitFMA(SDNode *N); 219 SDValue visitFDIV(SDNode *N); 220 SDValue visitFREM(SDNode *N); 221 SDValue visitFCOPYSIGN(SDNode *N); 222 SDValue visitSINT_TO_FP(SDNode *N); 223 SDValue visitUINT_TO_FP(SDNode *N); 224 SDValue visitFP_TO_SINT(SDNode *N); 225 SDValue visitFP_TO_UINT(SDNode *N); 226 SDValue visitFP_ROUND(SDNode *N); 227 SDValue visitFP_ROUND_INREG(SDNode *N); 228 SDValue visitFP_EXTEND(SDNode *N); 229 SDValue visitFNEG(SDNode *N); 230 SDValue visitFABS(SDNode *N); 231 SDValue visitBRCOND(SDNode *N); 232 SDValue visitBR_CC(SDNode *N); 233 SDValue visitLOAD(SDNode *N); 234 SDValue visitSTORE(SDNode *N); 235 SDValue visitINSERT_VECTOR_ELT(SDNode *N); 236 SDValue visitEXTRACT_VECTOR_ELT(SDNode *N); 237 SDValue visitBUILD_VECTOR(SDNode *N); 238 SDValue visitCONCAT_VECTORS(SDNode *N); 239 SDValue visitEXTRACT_SUBVECTOR(SDNode *N); 240 SDValue visitVECTOR_SHUFFLE(SDNode *N); 241 SDValue visitMEMBARRIER(SDNode *N); 242 243 SDValue XformToShuffleWithZero(SDNode *N); 244 SDValue ReassociateOps(unsigned Opc, DebugLoc DL, SDValue LHS, SDValue RHS); 245 246 SDValue visitShiftByConstant(SDNode *N, unsigned Amt); 247 248 bool SimplifySelectOps(SDNode *SELECT, SDValue LHS, SDValue RHS); 249 SDValue SimplifyBinOpWithSameOpcodeHands(SDNode *N); 250 SDValue SimplifySelect(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2); 251 SDValue SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2, 252 SDValue N3, ISD::CondCode CC, 253 bool NotExtCompare = false); 254 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond, 255 DebugLoc DL, bool foldBooleans = true); 256 SDValue SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 257 unsigned HiOp); 258 SDValue CombineConsecutiveLoads(SDNode *N, EVT VT); 259 SDValue ConstantFoldBITCASTofBUILD_VECTOR(SDNode *, EVT); 260 SDValue BuildSDIV(SDNode *N); 261 SDValue BuildUDIV(SDNode *N); 262 SDValue MatchBSwapHWordLow(SDNode *N, SDValue N0, SDValue N1, 263 bool DemandHighBits = true); 264 SDValue MatchBSwapHWord(SDNode *N, SDValue N0, SDValue N1); 265 SDNode *MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL); 266 SDValue ReduceLoadWidth(SDNode *N); 267 SDValue ReduceLoadOpStoreWidth(SDNode *N); 268 SDValue TransformFPLoadStorePair(SDNode *N); 269 270 SDValue GetDemandedBits(SDValue V, const APInt &Mask); 271 272 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 273 /// looking for aliasing nodes and adding them to the Aliases vector. 274 void GatherAllAliases(SDNode *N, SDValue OriginalChain, 275 SmallVector<SDValue, 8> &Aliases); 276 277 /// isAlias - Return true if there is any possibility that the two addresses 278 /// overlap. 279 bool isAlias(SDValue Ptr1, int64_t Size1, 280 const Value *SrcValue1, int SrcValueOffset1, 281 unsigned SrcValueAlign1, 282 const MDNode *TBAAInfo1, 283 SDValue Ptr2, int64_t Size2, 284 const Value *SrcValue2, int SrcValueOffset2, 285 unsigned SrcValueAlign2, 286 const MDNode *TBAAInfo2) const; 287 288 /// FindAliasInfo - Extracts the relevant alias information from the memory 289 /// node. Returns true if the operand was a load. 290 bool FindAliasInfo(SDNode *N, 291 SDValue &Ptr, int64_t &Size, 292 const Value *&SrcValue, int &SrcValueOffset, 293 unsigned &SrcValueAlignment, 294 const MDNode *&TBAAInfo) const; 295 296 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, 297 /// looking for a better chain (aliasing node.) 298 SDValue FindBetterChain(SDNode *N, SDValue Chain); 299 300 public: 301 DAGCombiner(SelectionDAG &D, AliasAnalysis &A, CodeGenOpt::Level OL) 302 : DAG(D), TLI(D.getTargetLoweringInfo()), Level(BeforeLegalizeTypes), 303 OptLevel(OL), LegalOperations(false), LegalTypes(false), AA(A) {} 304 305 /// Run - runs the dag combiner on all nodes in the work list 306 void Run(CombineLevel AtLevel); 307 308 SelectionDAG &getDAG() const { return DAG; } 309 310 /// getShiftAmountTy - Returns a type large enough to hold any valid 311 /// shift amount - before type legalization these can be huge. 312 EVT getShiftAmountTy(EVT LHSTy) { 313 return LegalTypes ? TLI.getShiftAmountTy(LHSTy) : TLI.getPointerTy(); 314 } 315 316 /// isTypeLegal - This method returns true if we are running before type 317 /// legalization or if the specified VT is legal. 318 bool isTypeLegal(const EVT &VT) { 319 if (!LegalTypes) return true; 320 return TLI.isTypeLegal(VT); 321 } 322 }; 323} 324 325 326namespace { 327/// WorkListRemover - This class is a DAGUpdateListener that removes any deleted 328/// nodes from the worklist. 329class WorkListRemover : public SelectionDAG::DAGUpdateListener { 330 DAGCombiner &DC; 331public: 332 explicit WorkListRemover(DAGCombiner &dc) 333 : SelectionDAG::DAGUpdateListener(dc.getDAG()), DC(dc) {} 334 335 virtual void NodeDeleted(SDNode *N, SDNode *E) { 336 DC.removeFromWorkList(N); 337 } 338}; 339} 340 341//===----------------------------------------------------------------------===// 342// TargetLowering::DAGCombinerInfo implementation 343//===----------------------------------------------------------------------===// 344 345void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) { 346 ((DAGCombiner*)DC)->AddToWorkList(N); 347} 348 349void TargetLowering::DAGCombinerInfo::RemoveFromWorklist(SDNode *N) { 350 ((DAGCombiner*)DC)->removeFromWorkList(N); 351} 352 353SDValue TargetLowering::DAGCombinerInfo:: 354CombineTo(SDNode *N, const std::vector<SDValue> &To, bool AddTo) { 355 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size(), AddTo); 356} 357 358SDValue TargetLowering::DAGCombinerInfo:: 359CombineTo(SDNode *N, SDValue Res, bool AddTo) { 360 return ((DAGCombiner*)DC)->CombineTo(N, Res, AddTo); 361} 362 363 364SDValue TargetLowering::DAGCombinerInfo:: 365CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo) { 366 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1, AddTo); 367} 368 369void TargetLowering::DAGCombinerInfo:: 370CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) { 371 return ((DAGCombiner*)DC)->CommitTargetLoweringOpt(TLO); 372} 373 374//===----------------------------------------------------------------------===// 375// Helper Functions 376//===----------------------------------------------------------------------===// 377 378/// isNegatibleForFree - Return 1 if we can compute the negated form of the 379/// specified expression for the same cost as the expression itself, or 2 if we 380/// can compute the negated form more cheaply than the expression itself. 381static char isNegatibleForFree(SDValue Op, bool LegalOperations, 382 const TargetLowering &TLI, 383 const TargetOptions *Options, 384 unsigned Depth = 0) { 385 // No compile time optimizations on this type. 386 if (Op.getValueType() == MVT::ppcf128) 387 return 0; 388 389 // fneg is removable even if it has multiple uses. 390 if (Op.getOpcode() == ISD::FNEG) return 2; 391 392 // Don't allow anything with multiple uses. 393 if (!Op.hasOneUse()) return 0; 394 395 // Don't recurse exponentially. 396 if (Depth > 6) return 0; 397 398 switch (Op.getOpcode()) { 399 default: return false; 400 case ISD::ConstantFP: 401 // Don't invert constant FP values after legalize. The negated constant 402 // isn't necessarily legal. 403 return LegalOperations ? 0 : 1; 404 case ISD::FADD: 405 // FIXME: determine better conditions for this xform. 406 if (!Options->UnsafeFPMath) return 0; 407 408 // After operation legalization, it might not be legal to create new FSUBs. 409 if (LegalOperations && 410 !TLI.isOperationLegalOrCustom(ISD::FSUB, Op.getValueType())) 411 return 0; 412 413 // fold (fsub (fadd A, B)) -> (fsub (fneg A), B) 414 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI, 415 Options, Depth + 1)) 416 return V; 417 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A) 418 return isNegatibleForFree(Op.getOperand(1), LegalOperations, TLI, Options, 419 Depth + 1); 420 case ISD::FSUB: 421 // We can't turn -(A-B) into B-A when we honor signed zeros. 422 if (!Options->UnsafeFPMath) return 0; 423 424 // fold (fneg (fsub A, B)) -> (fsub B, A) 425 return 1; 426 427 case ISD::FMUL: 428 case ISD::FDIV: 429 if (Options->HonorSignDependentRoundingFPMath()) return 0; 430 431 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) or (fmul X, (fneg Y)) 432 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI, 433 Options, Depth + 1)) 434 return V; 435 436 return isNegatibleForFree(Op.getOperand(1), LegalOperations, TLI, Options, 437 Depth + 1); 438 439 case ISD::FP_EXTEND: 440 case ISD::FP_ROUND: 441 case ISD::FSIN: 442 return isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI, Options, 443 Depth + 1); 444 } 445} 446 447/// GetNegatedExpression - If isNegatibleForFree returns true, this function 448/// returns the newly negated expression. 449static SDValue GetNegatedExpression(SDValue Op, SelectionDAG &DAG, 450 bool LegalOperations, unsigned Depth = 0) { 451 // fneg is removable even if it has multiple uses. 452 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0); 453 454 // Don't allow anything with multiple uses. 455 assert(Op.hasOneUse() && "Unknown reuse!"); 456 457 assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree"); 458 switch (Op.getOpcode()) { 459 default: llvm_unreachable("Unknown code"); 460 case ISD::ConstantFP: { 461 APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF(); 462 V.changeSign(); 463 return DAG.getConstantFP(V, Op.getValueType()); 464 } 465 case ISD::FADD: 466 // FIXME: determine better conditions for this xform. 467 assert(DAG.getTarget().Options.UnsafeFPMath); 468 469 // fold (fneg (fadd A, B)) -> (fsub (fneg A), B) 470 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, 471 DAG.getTargetLoweringInfo(), 472 &DAG.getTarget().Options, Depth+1)) 473 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 474 GetNegatedExpression(Op.getOperand(0), DAG, 475 LegalOperations, Depth+1), 476 Op.getOperand(1)); 477 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A) 478 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 479 GetNegatedExpression(Op.getOperand(1), DAG, 480 LegalOperations, Depth+1), 481 Op.getOperand(0)); 482 case ISD::FSUB: 483 // We can't turn -(A-B) into B-A when we honor signed zeros. 484 assert(DAG.getTarget().Options.UnsafeFPMath); 485 486 // fold (fneg (fsub 0, B)) -> B 487 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(Op.getOperand(0))) 488 if (N0CFP->getValueAPF().isZero()) 489 return Op.getOperand(1); 490 491 // fold (fneg (fsub A, B)) -> (fsub B, A) 492 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 493 Op.getOperand(1), Op.getOperand(0)); 494 495 case ISD::FMUL: 496 case ISD::FDIV: 497 assert(!DAG.getTarget().Options.HonorSignDependentRoundingFPMath()); 498 499 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) 500 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, 501 DAG.getTargetLoweringInfo(), 502 &DAG.getTarget().Options, Depth+1)) 503 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 504 GetNegatedExpression(Op.getOperand(0), DAG, 505 LegalOperations, Depth+1), 506 Op.getOperand(1)); 507 508 // fold (fneg (fmul X, Y)) -> (fmul X, (fneg Y)) 509 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 510 Op.getOperand(0), 511 GetNegatedExpression(Op.getOperand(1), DAG, 512 LegalOperations, Depth+1)); 513 514 case ISD::FP_EXTEND: 515 case ISD::FSIN: 516 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 517 GetNegatedExpression(Op.getOperand(0), DAG, 518 LegalOperations, Depth+1)); 519 case ISD::FP_ROUND: 520 return DAG.getNode(ISD::FP_ROUND, Op.getDebugLoc(), Op.getValueType(), 521 GetNegatedExpression(Op.getOperand(0), DAG, 522 LegalOperations, Depth+1), 523 Op.getOperand(1)); 524 } 525} 526 527 528// isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc 529// that selects between the values 1 and 0, making it equivalent to a setcc. 530// Also, set the incoming LHS, RHS, and CC references to the appropriate 531// nodes based on the type of node we are checking. This simplifies life a 532// bit for the callers. 533static bool isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS, 534 SDValue &CC) { 535 if (N.getOpcode() == ISD::SETCC) { 536 LHS = N.getOperand(0); 537 RHS = N.getOperand(1); 538 CC = N.getOperand(2); 539 return true; 540 } 541 if (N.getOpcode() == ISD::SELECT_CC && 542 N.getOperand(2).getOpcode() == ISD::Constant && 543 N.getOperand(3).getOpcode() == ISD::Constant && 544 cast<ConstantSDNode>(N.getOperand(2))->getAPIntValue() == 1 && 545 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) { 546 LHS = N.getOperand(0); 547 RHS = N.getOperand(1); 548 CC = N.getOperand(4); 549 return true; 550 } 551 return false; 552} 553 554// isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only 555// one use. If this is true, it allows the users to invert the operation for 556// free when it is profitable to do so. 557static bool isOneUseSetCC(SDValue N) { 558 SDValue N0, N1, N2; 559 if (isSetCCEquivalent(N, N0, N1, N2) && N.getNode()->hasOneUse()) 560 return true; 561 return false; 562} 563 564SDValue DAGCombiner::ReassociateOps(unsigned Opc, DebugLoc DL, 565 SDValue N0, SDValue N1) { 566 EVT VT = N0.getValueType(); 567 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) { 568 if (isa<ConstantSDNode>(N1)) { 569 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2)) 570 SDValue OpNode = 571 DAG.FoldConstantArithmetic(Opc, VT, 572 cast<ConstantSDNode>(N0.getOperand(1)), 573 cast<ConstantSDNode>(N1)); 574 return DAG.getNode(Opc, DL, VT, N0.getOperand(0), OpNode); 575 } 576 if (N0.hasOneUse()) { 577 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use 578 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT, 579 N0.getOperand(0), N1); 580 AddToWorkList(OpNode.getNode()); 581 return DAG.getNode(Opc, DL, VT, OpNode, N0.getOperand(1)); 582 } 583 } 584 585 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) { 586 if (isa<ConstantSDNode>(N0)) { 587 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2)) 588 SDValue OpNode = 589 DAG.FoldConstantArithmetic(Opc, VT, 590 cast<ConstantSDNode>(N1.getOperand(1)), 591 cast<ConstantSDNode>(N0)); 592 return DAG.getNode(Opc, DL, VT, N1.getOperand(0), OpNode); 593 } 594 if (N1.hasOneUse()) { 595 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use 596 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT, 597 N1.getOperand(0), N0); 598 AddToWorkList(OpNode.getNode()); 599 return DAG.getNode(Opc, DL, VT, OpNode, N1.getOperand(1)); 600 } 601 } 602 603 return SDValue(); 604} 605 606SDValue DAGCombiner::CombineTo(SDNode *N, const SDValue *To, unsigned NumTo, 607 bool AddTo) { 608 assert(N->getNumValues() == NumTo && "Broken CombineTo call!"); 609 ++NodesCombined; 610 DEBUG(dbgs() << "\nReplacing.1 "; 611 N->dump(&DAG); 612 dbgs() << "\nWith: "; 613 To[0].getNode()->dump(&DAG); 614 dbgs() << " and " << NumTo-1 << " other values\n"; 615 for (unsigned i = 0, e = NumTo; i != e; ++i) 616 assert((!To[i].getNode() || 617 N->getValueType(i) == To[i].getValueType()) && 618 "Cannot combine value to value of different type!")); 619 WorkListRemover DeadNodes(*this); 620 DAG.ReplaceAllUsesWith(N, To); 621 if (AddTo) { 622 // Push the new nodes and any users onto the worklist 623 for (unsigned i = 0, e = NumTo; i != e; ++i) { 624 if (To[i].getNode()) { 625 AddToWorkList(To[i].getNode()); 626 AddUsersToWorkList(To[i].getNode()); 627 } 628 } 629 } 630 631 // Finally, if the node is now dead, remove it from the graph. The node 632 // may not be dead if the replacement process recursively simplified to 633 // something else needing this node. 634 if (N->use_empty()) { 635 // Nodes can be reintroduced into the worklist. Make sure we do not 636 // process a node that has been replaced. 637 removeFromWorkList(N); 638 639 // Finally, since the node is now dead, remove it from the graph. 640 DAG.DeleteNode(N); 641 } 642 return SDValue(N, 0); 643} 644 645void DAGCombiner:: 646CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) { 647 // Replace all uses. If any nodes become isomorphic to other nodes and 648 // are deleted, make sure to remove them from our worklist. 649 WorkListRemover DeadNodes(*this); 650 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New); 651 652 // Push the new node and any (possibly new) users onto the worklist. 653 AddToWorkList(TLO.New.getNode()); 654 AddUsersToWorkList(TLO.New.getNode()); 655 656 // Finally, if the node is now dead, remove it from the graph. The node 657 // may not be dead if the replacement process recursively simplified to 658 // something else needing this node. 659 if (TLO.Old.getNode()->use_empty()) { 660 removeFromWorkList(TLO.Old.getNode()); 661 662 // If the operands of this node are only used by the node, they will now 663 // be dead. Make sure to visit them first to delete dead nodes early. 664 for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands(); i != e; ++i) 665 if (TLO.Old.getNode()->getOperand(i).getNode()->hasOneUse()) 666 AddToWorkList(TLO.Old.getNode()->getOperand(i).getNode()); 667 668 DAG.DeleteNode(TLO.Old.getNode()); 669 } 670} 671 672/// SimplifyDemandedBits - Check the specified integer node value to see if 673/// it can be simplified or if things it uses can be simplified by bit 674/// propagation. If so, return true. 675bool DAGCombiner::SimplifyDemandedBits(SDValue Op, const APInt &Demanded) { 676 TargetLowering::TargetLoweringOpt TLO(DAG, LegalTypes, LegalOperations); 677 APInt KnownZero, KnownOne; 678 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO)) 679 return false; 680 681 // Revisit the node. 682 AddToWorkList(Op.getNode()); 683 684 // Replace the old value with the new one. 685 ++NodesCombined; 686 DEBUG(dbgs() << "\nReplacing.2 "; 687 TLO.Old.getNode()->dump(&DAG); 688 dbgs() << "\nWith: "; 689 TLO.New.getNode()->dump(&DAG); 690 dbgs() << '\n'); 691 692 CommitTargetLoweringOpt(TLO); 693 return true; 694} 695 696void DAGCombiner::ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad) { 697 DebugLoc dl = Load->getDebugLoc(); 698 EVT VT = Load->getValueType(0); 699 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, VT, SDValue(ExtLoad, 0)); 700 701 DEBUG(dbgs() << "\nReplacing.9 "; 702 Load->dump(&DAG); 703 dbgs() << "\nWith: "; 704 Trunc.getNode()->dump(&DAG); 705 dbgs() << '\n'); 706 WorkListRemover DeadNodes(*this); 707 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 0), Trunc); 708 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 1), SDValue(ExtLoad, 1)); 709 removeFromWorkList(Load); 710 DAG.DeleteNode(Load); 711 AddToWorkList(Trunc.getNode()); 712} 713 714SDValue DAGCombiner::PromoteOperand(SDValue Op, EVT PVT, bool &Replace) { 715 Replace = false; 716 DebugLoc dl = Op.getDebugLoc(); 717 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Op)) { 718 EVT MemVT = LD->getMemoryVT(); 719 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD) 720 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT) ? ISD::ZEXTLOAD 721 : ISD::EXTLOAD) 722 : LD->getExtensionType(); 723 Replace = true; 724 return DAG.getExtLoad(ExtType, dl, PVT, 725 LD->getChain(), LD->getBasePtr(), 726 LD->getPointerInfo(), 727 MemVT, LD->isVolatile(), 728 LD->isNonTemporal(), LD->getAlignment()); 729 } 730 731 unsigned Opc = Op.getOpcode(); 732 switch (Opc) { 733 default: break; 734 case ISD::AssertSext: 735 return DAG.getNode(ISD::AssertSext, dl, PVT, 736 SExtPromoteOperand(Op.getOperand(0), PVT), 737 Op.getOperand(1)); 738 case ISD::AssertZext: 739 return DAG.getNode(ISD::AssertZext, dl, PVT, 740 ZExtPromoteOperand(Op.getOperand(0), PVT), 741 Op.getOperand(1)); 742 case ISD::Constant: { 743 unsigned ExtOpc = 744 Op.getValueType().isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; 745 return DAG.getNode(ExtOpc, dl, PVT, Op); 746 } 747 } 748 749 if (!TLI.isOperationLegal(ISD::ANY_EXTEND, PVT)) 750 return SDValue(); 751 return DAG.getNode(ISD::ANY_EXTEND, dl, PVT, Op); 752} 753 754SDValue DAGCombiner::SExtPromoteOperand(SDValue Op, EVT PVT) { 755 if (!TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, PVT)) 756 return SDValue(); 757 EVT OldVT = Op.getValueType(); 758 DebugLoc dl = Op.getDebugLoc(); 759 bool Replace = false; 760 SDValue NewOp = PromoteOperand(Op, PVT, Replace); 761 if (NewOp.getNode() == 0) 762 return SDValue(); 763 AddToWorkList(NewOp.getNode()); 764 765 if (Replace) 766 ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode()); 767 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NewOp.getValueType(), NewOp, 768 DAG.getValueType(OldVT)); 769} 770 771SDValue DAGCombiner::ZExtPromoteOperand(SDValue Op, EVT PVT) { 772 EVT OldVT = Op.getValueType(); 773 DebugLoc dl = Op.getDebugLoc(); 774 bool Replace = false; 775 SDValue NewOp = PromoteOperand(Op, PVT, Replace); 776 if (NewOp.getNode() == 0) 777 return SDValue(); 778 AddToWorkList(NewOp.getNode()); 779 780 if (Replace) 781 ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode()); 782 return DAG.getZeroExtendInReg(NewOp, dl, OldVT); 783} 784 785/// PromoteIntBinOp - Promote the specified integer binary operation if the 786/// target indicates it is beneficial. e.g. On x86, it's usually better to 787/// promote i16 operations to i32 since i16 instructions are longer. 788SDValue DAGCombiner::PromoteIntBinOp(SDValue Op) { 789 if (!LegalOperations) 790 return SDValue(); 791 792 EVT VT = Op.getValueType(); 793 if (VT.isVector() || !VT.isInteger()) 794 return SDValue(); 795 796 // If operation type is 'undesirable', e.g. i16 on x86, consider 797 // promoting it. 798 unsigned Opc = Op.getOpcode(); 799 if (TLI.isTypeDesirableForOp(Opc, VT)) 800 return SDValue(); 801 802 EVT PVT = VT; 803 // Consult target whether it is a good idea to promote this operation and 804 // what's the right type to promote it to. 805 if (TLI.IsDesirableToPromoteOp(Op, PVT)) { 806 assert(PVT != VT && "Don't know what type to promote to!"); 807 808 bool Replace0 = false; 809 SDValue N0 = Op.getOperand(0); 810 SDValue NN0 = PromoteOperand(N0, PVT, Replace0); 811 if (NN0.getNode() == 0) 812 return SDValue(); 813 814 bool Replace1 = false; 815 SDValue N1 = Op.getOperand(1); 816 SDValue NN1; 817 if (N0 == N1) 818 NN1 = NN0; 819 else { 820 NN1 = PromoteOperand(N1, PVT, Replace1); 821 if (NN1.getNode() == 0) 822 return SDValue(); 823 } 824 825 AddToWorkList(NN0.getNode()); 826 if (NN1.getNode()) 827 AddToWorkList(NN1.getNode()); 828 829 if (Replace0) 830 ReplaceLoadWithPromotedLoad(N0.getNode(), NN0.getNode()); 831 if (Replace1) 832 ReplaceLoadWithPromotedLoad(N1.getNode(), NN1.getNode()); 833 834 DEBUG(dbgs() << "\nPromoting "; 835 Op.getNode()->dump(&DAG)); 836 DebugLoc dl = Op.getDebugLoc(); 837 return DAG.getNode(ISD::TRUNCATE, dl, VT, 838 DAG.getNode(Opc, dl, PVT, NN0, NN1)); 839 } 840 return SDValue(); 841} 842 843/// PromoteIntShiftOp - Promote the specified integer shift operation if the 844/// target indicates it is beneficial. e.g. On x86, it's usually better to 845/// promote i16 operations to i32 since i16 instructions are longer. 846SDValue DAGCombiner::PromoteIntShiftOp(SDValue Op) { 847 if (!LegalOperations) 848 return SDValue(); 849 850 EVT VT = Op.getValueType(); 851 if (VT.isVector() || !VT.isInteger()) 852 return SDValue(); 853 854 // If operation type is 'undesirable', e.g. i16 on x86, consider 855 // promoting it. 856 unsigned Opc = Op.getOpcode(); 857 if (TLI.isTypeDesirableForOp(Opc, VT)) 858 return SDValue(); 859 860 EVT PVT = VT; 861 // Consult target whether it is a good idea to promote this operation and 862 // what's the right type to promote it to. 863 if (TLI.IsDesirableToPromoteOp(Op, PVT)) { 864 assert(PVT != VT && "Don't know what type to promote to!"); 865 866 bool Replace = false; 867 SDValue N0 = Op.getOperand(0); 868 if (Opc == ISD::SRA) 869 N0 = SExtPromoteOperand(Op.getOperand(0), PVT); 870 else if (Opc == ISD::SRL) 871 N0 = ZExtPromoteOperand(Op.getOperand(0), PVT); 872 else 873 N0 = PromoteOperand(N0, PVT, Replace); 874 if (N0.getNode() == 0) 875 return SDValue(); 876 877 AddToWorkList(N0.getNode()); 878 if (Replace) 879 ReplaceLoadWithPromotedLoad(Op.getOperand(0).getNode(), N0.getNode()); 880 881 DEBUG(dbgs() << "\nPromoting "; 882 Op.getNode()->dump(&DAG)); 883 DebugLoc dl = Op.getDebugLoc(); 884 return DAG.getNode(ISD::TRUNCATE, dl, VT, 885 DAG.getNode(Opc, dl, PVT, N0, Op.getOperand(1))); 886 } 887 return SDValue(); 888} 889 890SDValue DAGCombiner::PromoteExtend(SDValue Op) { 891 if (!LegalOperations) 892 return SDValue(); 893 894 EVT VT = Op.getValueType(); 895 if (VT.isVector() || !VT.isInteger()) 896 return SDValue(); 897 898 // If operation type is 'undesirable', e.g. i16 on x86, consider 899 // promoting it. 900 unsigned Opc = Op.getOpcode(); 901 if (TLI.isTypeDesirableForOp(Opc, VT)) 902 return SDValue(); 903 904 EVT PVT = VT; 905 // Consult target whether it is a good idea to promote this operation and 906 // what's the right type to promote it to. 907 if (TLI.IsDesirableToPromoteOp(Op, PVT)) { 908 assert(PVT != VT && "Don't know what type to promote to!"); 909 // fold (aext (aext x)) -> (aext x) 910 // fold (aext (zext x)) -> (zext x) 911 // fold (aext (sext x)) -> (sext x) 912 DEBUG(dbgs() << "\nPromoting "; 913 Op.getNode()->dump(&DAG)); 914 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), VT, Op.getOperand(0)); 915 } 916 return SDValue(); 917} 918 919bool DAGCombiner::PromoteLoad(SDValue Op) { 920 if (!LegalOperations) 921 return false; 922 923 EVT VT = Op.getValueType(); 924 if (VT.isVector() || !VT.isInteger()) 925 return false; 926 927 // If operation type is 'undesirable', e.g. i16 on x86, consider 928 // promoting it. 929 unsigned Opc = Op.getOpcode(); 930 if (TLI.isTypeDesirableForOp(Opc, VT)) 931 return false; 932 933 EVT PVT = VT; 934 // Consult target whether it is a good idea to promote this operation and 935 // what's the right type to promote it to. 936 if (TLI.IsDesirableToPromoteOp(Op, PVT)) { 937 assert(PVT != VT && "Don't know what type to promote to!"); 938 939 DebugLoc dl = Op.getDebugLoc(); 940 SDNode *N = Op.getNode(); 941 LoadSDNode *LD = cast<LoadSDNode>(N); 942 EVT MemVT = LD->getMemoryVT(); 943 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD) 944 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT) ? ISD::ZEXTLOAD 945 : ISD::EXTLOAD) 946 : LD->getExtensionType(); 947 SDValue NewLD = DAG.getExtLoad(ExtType, dl, PVT, 948 LD->getChain(), LD->getBasePtr(), 949 LD->getPointerInfo(), 950 MemVT, LD->isVolatile(), 951 LD->isNonTemporal(), LD->getAlignment()); 952 SDValue Result = DAG.getNode(ISD::TRUNCATE, dl, VT, NewLD); 953 954 DEBUG(dbgs() << "\nPromoting "; 955 N->dump(&DAG); 956 dbgs() << "\nTo: "; 957 Result.getNode()->dump(&DAG); 958 dbgs() << '\n'); 959 WorkListRemover DeadNodes(*this); 960 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result); 961 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), NewLD.getValue(1)); 962 removeFromWorkList(N); 963 DAG.DeleteNode(N); 964 AddToWorkList(Result.getNode()); 965 return true; 966 } 967 return false; 968} 969 970 971//===----------------------------------------------------------------------===// 972// Main DAG Combiner implementation 973//===----------------------------------------------------------------------===// 974 975void DAGCombiner::Run(CombineLevel AtLevel) { 976 // set the instance variables, so that the various visit routines may use it. 977 Level = AtLevel; 978 LegalOperations = Level >= AfterLegalizeVectorOps; 979 LegalTypes = Level >= AfterLegalizeTypes; 980 981 // Add all the dag nodes to the worklist. 982 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 983 E = DAG.allnodes_end(); I != E; ++I) 984 AddToWorkList(I); 985 986 // Create a dummy node (which is not added to allnodes), that adds a reference 987 // to the root node, preventing it from being deleted, and tracking any 988 // changes of the root. 989 HandleSDNode Dummy(DAG.getRoot()); 990 991 // The root of the dag may dangle to deleted nodes until the dag combiner is 992 // done. Set it to null to avoid confusion. 993 DAG.setRoot(SDValue()); 994 995 // while the worklist isn't empty, find a node and 996 // try and combine it. 997 while (!WorkListContents.empty()) { 998 SDNode *N; 999 // The WorkListOrder holds the SDNodes in order, but it may contain duplicates. 1000 // In order to avoid a linear scan, we use a set (O(log N)) to hold what the 1001 // worklist *should* contain, and check the node we want to visit is should 1002 // actually be visited. 1003 do { 1004 N = WorkListOrder.pop_back_val(); 1005 } while (!WorkListContents.erase(N)); 1006 1007 // If N has no uses, it is dead. Make sure to revisit all N's operands once 1008 // N is deleted from the DAG, since they too may now be dead or may have a 1009 // reduced number of uses, allowing other xforms. 1010 if (N->use_empty() && N != &Dummy) { 1011 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 1012 AddToWorkList(N->getOperand(i).getNode()); 1013 1014 DAG.DeleteNode(N); 1015 continue; 1016 } 1017 1018 SDValue RV = combine(N); 1019 1020 if (RV.getNode() == 0) 1021 continue; 1022 1023 ++NodesCombined; 1024 1025 // If we get back the same node we passed in, rather than a new node or 1026 // zero, we know that the node must have defined multiple values and 1027 // CombineTo was used. Since CombineTo takes care of the worklist 1028 // mechanics for us, we have no work to do in this case. 1029 if (RV.getNode() == N) 1030 continue; 1031 1032 assert(N->getOpcode() != ISD::DELETED_NODE && 1033 RV.getNode()->getOpcode() != ISD::DELETED_NODE && 1034 "Node was deleted but visit returned new node!"); 1035 1036 DEBUG(dbgs() << "\nReplacing.3 "; 1037 N->dump(&DAG); 1038 dbgs() << "\nWith: "; 1039 RV.getNode()->dump(&DAG); 1040 dbgs() << '\n'); 1041 1042 // Transfer debug value. 1043 DAG.TransferDbgValues(SDValue(N, 0), RV); 1044 WorkListRemover DeadNodes(*this); 1045 if (N->getNumValues() == RV.getNode()->getNumValues()) 1046 DAG.ReplaceAllUsesWith(N, RV.getNode()); 1047 else { 1048 assert(N->getValueType(0) == RV.getValueType() && 1049 N->getNumValues() == 1 && "Type mismatch"); 1050 SDValue OpV = RV; 1051 DAG.ReplaceAllUsesWith(N, &OpV); 1052 } 1053 1054 // Push the new node and any users onto the worklist 1055 AddToWorkList(RV.getNode()); 1056 AddUsersToWorkList(RV.getNode()); 1057 1058 // Add any uses of the old node to the worklist in case this node is the 1059 // last one that uses them. They may become dead after this node is 1060 // deleted. 1061 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 1062 AddToWorkList(N->getOperand(i).getNode()); 1063 1064 // Finally, if the node is now dead, remove it from the graph. The node 1065 // may not be dead if the replacement process recursively simplified to 1066 // something else needing this node. 1067 if (N->use_empty()) { 1068 // Nodes can be reintroduced into the worklist. Make sure we do not 1069 // process a node that has been replaced. 1070 removeFromWorkList(N); 1071 1072 // Finally, since the node is now dead, remove it from the graph. 1073 DAG.DeleteNode(N); 1074 } 1075 } 1076 1077 // If the root changed (e.g. it was a dead load, update the root). 1078 DAG.setRoot(Dummy.getValue()); 1079 DAG.RemoveDeadNodes(); 1080} 1081 1082SDValue DAGCombiner::visit(SDNode *N) { 1083 switch (N->getOpcode()) { 1084 default: break; 1085 case ISD::TokenFactor: return visitTokenFactor(N); 1086 case ISD::MERGE_VALUES: return visitMERGE_VALUES(N); 1087 case ISD::ADD: return visitADD(N); 1088 case ISD::SUB: return visitSUB(N); 1089 case ISD::ADDC: return visitADDC(N); 1090 case ISD::SUBC: return visitSUBC(N); 1091 case ISD::ADDE: return visitADDE(N); 1092 case ISD::SUBE: return visitSUBE(N); 1093 case ISD::MUL: return visitMUL(N); 1094 case ISD::SDIV: return visitSDIV(N); 1095 case ISD::UDIV: return visitUDIV(N); 1096 case ISD::SREM: return visitSREM(N); 1097 case ISD::UREM: return visitUREM(N); 1098 case ISD::MULHU: return visitMULHU(N); 1099 case ISD::MULHS: return visitMULHS(N); 1100 case ISD::SMUL_LOHI: return visitSMUL_LOHI(N); 1101 case ISD::UMUL_LOHI: return visitUMUL_LOHI(N); 1102 case ISD::SMULO: return visitSMULO(N); 1103 case ISD::UMULO: return visitUMULO(N); 1104 case ISD::SDIVREM: return visitSDIVREM(N); 1105 case ISD::UDIVREM: return visitUDIVREM(N); 1106 case ISD::AND: return visitAND(N); 1107 case ISD::OR: return visitOR(N); 1108 case ISD::XOR: return visitXOR(N); 1109 case ISD::SHL: return visitSHL(N); 1110 case ISD::SRA: return visitSRA(N); 1111 case ISD::SRL: return visitSRL(N); 1112 case ISD::CTLZ: return visitCTLZ(N); 1113 case ISD::CTLZ_ZERO_UNDEF: return visitCTLZ_ZERO_UNDEF(N); 1114 case ISD::CTTZ: return visitCTTZ(N); 1115 case ISD::CTTZ_ZERO_UNDEF: return visitCTTZ_ZERO_UNDEF(N); 1116 case ISD::CTPOP: return visitCTPOP(N); 1117 case ISD::SELECT: return visitSELECT(N); 1118 case ISD::SELECT_CC: return visitSELECT_CC(N); 1119 case ISD::SETCC: return visitSETCC(N); 1120 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N); 1121 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N); 1122 case ISD::ANY_EXTEND: return visitANY_EXTEND(N); 1123 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N); 1124 case ISD::TRUNCATE: return visitTRUNCATE(N); 1125 case ISD::BITCAST: return visitBITCAST(N); 1126 case ISD::BUILD_PAIR: return visitBUILD_PAIR(N); 1127 case ISD::FADD: return visitFADD(N); 1128 case ISD::FSUB: return visitFSUB(N); 1129 case ISD::FMUL: return visitFMUL(N); 1130 case ISD::FMA: return visitFMA(N); 1131 case ISD::FDIV: return visitFDIV(N); 1132 case ISD::FREM: return visitFREM(N); 1133 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N); 1134 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N); 1135 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N); 1136 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N); 1137 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N); 1138 case ISD::FP_ROUND: return visitFP_ROUND(N); 1139 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N); 1140 case ISD::FP_EXTEND: return visitFP_EXTEND(N); 1141 case ISD::FNEG: return visitFNEG(N); 1142 case ISD::FABS: return visitFABS(N); 1143 case ISD::BRCOND: return visitBRCOND(N); 1144 case ISD::BR_CC: return visitBR_CC(N); 1145 case ISD::LOAD: return visitLOAD(N); 1146 case ISD::STORE: return visitSTORE(N); 1147 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N); 1148 case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N); 1149 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N); 1150 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N); 1151 case ISD::EXTRACT_SUBVECTOR: return visitEXTRACT_SUBVECTOR(N); 1152 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N); 1153 case ISD::MEMBARRIER: return visitMEMBARRIER(N); 1154 } 1155 return SDValue(); 1156} 1157 1158SDValue DAGCombiner::combine(SDNode *N) { 1159 SDValue RV = visit(N); 1160 1161 // If nothing happened, try a target-specific DAG combine. 1162 if (RV.getNode() == 0) { 1163 assert(N->getOpcode() != ISD::DELETED_NODE && 1164 "Node was deleted but visit returned NULL!"); 1165 1166 if (N->getOpcode() >= ISD::BUILTIN_OP_END || 1167 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) { 1168 1169 // Expose the DAG combiner to the target combiner impls. 1170 TargetLowering::DAGCombinerInfo 1171 DagCombineInfo(DAG, !LegalTypes, !LegalOperations, false, this); 1172 1173 RV = TLI.PerformDAGCombine(N, DagCombineInfo); 1174 } 1175 } 1176 1177 // If nothing happened still, try promoting the operation. 1178 if (RV.getNode() == 0) { 1179 switch (N->getOpcode()) { 1180 default: break; 1181 case ISD::ADD: 1182 case ISD::SUB: 1183 case ISD::MUL: 1184 case ISD::AND: 1185 case ISD::OR: 1186 case ISD::XOR: 1187 RV = PromoteIntBinOp(SDValue(N, 0)); 1188 break; 1189 case ISD::SHL: 1190 case ISD::SRA: 1191 case ISD::SRL: 1192 RV = PromoteIntShiftOp(SDValue(N, 0)); 1193 break; 1194 case ISD::SIGN_EXTEND: 1195 case ISD::ZERO_EXTEND: 1196 case ISD::ANY_EXTEND: 1197 RV = PromoteExtend(SDValue(N, 0)); 1198 break; 1199 case ISD::LOAD: 1200 if (PromoteLoad(SDValue(N, 0))) 1201 RV = SDValue(N, 0); 1202 break; 1203 } 1204 } 1205 1206 // If N is a commutative binary node, try commuting it to enable more 1207 // sdisel CSE. 1208 if (RV.getNode() == 0 && 1209 SelectionDAG::isCommutativeBinOp(N->getOpcode()) && 1210 N->getNumValues() == 1) { 1211 SDValue N0 = N->getOperand(0); 1212 SDValue N1 = N->getOperand(1); 1213 1214 // Constant operands are canonicalized to RHS. 1215 if (isa<ConstantSDNode>(N0) || !isa<ConstantSDNode>(N1)) { 1216 SDValue Ops[] = { N1, N0 }; 1217 SDNode *CSENode = DAG.getNodeIfExists(N->getOpcode(), N->getVTList(), 1218 Ops, 2); 1219 if (CSENode) 1220 return SDValue(CSENode, 0); 1221 } 1222 } 1223 1224 return RV; 1225} 1226 1227/// getInputChainForNode - Given a node, return its input chain if it has one, 1228/// otherwise return a null sd operand. 1229static SDValue getInputChainForNode(SDNode *N) { 1230 if (unsigned NumOps = N->getNumOperands()) { 1231 if (N->getOperand(0).getValueType() == MVT::Other) 1232 return N->getOperand(0); 1233 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other) 1234 return N->getOperand(NumOps-1); 1235 for (unsigned i = 1; i < NumOps-1; ++i) 1236 if (N->getOperand(i).getValueType() == MVT::Other) 1237 return N->getOperand(i); 1238 } 1239 return SDValue(); 1240} 1241 1242SDValue DAGCombiner::visitTokenFactor(SDNode *N) { 1243 // If N has two operands, where one has an input chain equal to the other, 1244 // the 'other' chain is redundant. 1245 if (N->getNumOperands() == 2) { 1246 if (getInputChainForNode(N->getOperand(0).getNode()) == N->getOperand(1)) 1247 return N->getOperand(0); 1248 if (getInputChainForNode(N->getOperand(1).getNode()) == N->getOperand(0)) 1249 return N->getOperand(1); 1250 } 1251 1252 SmallVector<SDNode *, 8> TFs; // List of token factors to visit. 1253 SmallVector<SDValue, 8> Ops; // Ops for replacing token factor. 1254 SmallPtrSet<SDNode*, 16> SeenOps; 1255 bool Changed = false; // If we should replace this token factor. 1256 1257 // Start out with this token factor. 1258 TFs.push_back(N); 1259 1260 // Iterate through token factors. The TFs grows when new token factors are 1261 // encountered. 1262 for (unsigned i = 0; i < TFs.size(); ++i) { 1263 SDNode *TF = TFs[i]; 1264 1265 // Check each of the operands. 1266 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) { 1267 SDValue Op = TF->getOperand(i); 1268 1269 switch (Op.getOpcode()) { 1270 case ISD::EntryToken: 1271 // Entry tokens don't need to be added to the list. They are 1272 // rededundant. 1273 Changed = true; 1274 break; 1275 1276 case ISD::TokenFactor: 1277 if (Op.hasOneUse() && 1278 std::find(TFs.begin(), TFs.end(), Op.getNode()) == TFs.end()) { 1279 // Queue up for processing. 1280 TFs.push_back(Op.getNode()); 1281 // Clean up in case the token factor is removed. 1282 AddToWorkList(Op.getNode()); 1283 Changed = true; 1284 break; 1285 } 1286 // Fall thru 1287 1288 default: 1289 // Only add if it isn't already in the list. 1290 if (SeenOps.insert(Op.getNode())) 1291 Ops.push_back(Op); 1292 else 1293 Changed = true; 1294 break; 1295 } 1296 } 1297 } 1298 1299 SDValue Result; 1300 1301 // If we've change things around then replace token factor. 1302 if (Changed) { 1303 if (Ops.empty()) { 1304 // The entry token is the only possible outcome. 1305 Result = DAG.getEntryNode(); 1306 } else { 1307 // New and improved token factor. 1308 Result = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 1309 MVT::Other, &Ops[0], Ops.size()); 1310 } 1311 1312 // Don't add users to work list. 1313 return CombineTo(N, Result, false); 1314 } 1315 1316 return Result; 1317} 1318 1319/// MERGE_VALUES can always be eliminated. 1320SDValue DAGCombiner::visitMERGE_VALUES(SDNode *N) { 1321 WorkListRemover DeadNodes(*this); 1322 // Replacing results may cause a different MERGE_VALUES to suddenly 1323 // be CSE'd with N, and carry its uses with it. Iterate until no 1324 // uses remain, to ensure that the node can be safely deleted. 1325 do { 1326 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 1327 DAG.ReplaceAllUsesOfValueWith(SDValue(N, i), N->getOperand(i)); 1328 } while (!N->use_empty()); 1329 removeFromWorkList(N); 1330 DAG.DeleteNode(N); 1331 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1332} 1333 1334static 1335SDValue combineShlAddConstant(DebugLoc DL, SDValue N0, SDValue N1, 1336 SelectionDAG &DAG) { 1337 EVT VT = N0.getValueType(); 1338 SDValue N00 = N0.getOperand(0); 1339 SDValue N01 = N0.getOperand(1); 1340 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01); 1341 1342 if (N01C && N00.getOpcode() == ISD::ADD && N00.getNode()->hasOneUse() && 1343 isa<ConstantSDNode>(N00.getOperand(1))) { 1344 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 1345 N0 = DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, 1346 DAG.getNode(ISD::SHL, N00.getDebugLoc(), VT, 1347 N00.getOperand(0), N01), 1348 DAG.getNode(ISD::SHL, N01.getDebugLoc(), VT, 1349 N00.getOperand(1), N01)); 1350 return DAG.getNode(ISD::ADD, DL, VT, N0, N1); 1351 } 1352 1353 return SDValue(); 1354} 1355 1356SDValue DAGCombiner::visitADD(SDNode *N) { 1357 SDValue N0 = N->getOperand(0); 1358 SDValue N1 = N->getOperand(1); 1359 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1360 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1361 EVT VT = N0.getValueType(); 1362 1363 // fold vector ops 1364 if (VT.isVector()) { 1365 SDValue FoldedVOp = SimplifyVBinOp(N); 1366 if (FoldedVOp.getNode()) return FoldedVOp; 1367 } 1368 1369 // fold (add x, undef) -> undef 1370 if (N0.getOpcode() == ISD::UNDEF) 1371 return N0; 1372 if (N1.getOpcode() == ISD::UNDEF) 1373 return N1; 1374 // fold (add c1, c2) -> c1+c2 1375 if (N0C && N1C) 1376 return DAG.FoldConstantArithmetic(ISD::ADD, VT, N0C, N1C); 1377 // canonicalize constant to RHS 1378 if (N0C && !N1C) 1379 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0); 1380 // fold (add x, 0) -> x 1381 if (N1C && N1C->isNullValue()) 1382 return N0; 1383 // fold (add Sym, c) -> Sym+c 1384 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0)) 1385 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA) && N1C && 1386 GA->getOpcode() == ISD::GlobalAddress) 1387 return DAG.getGlobalAddress(GA->getGlobal(), N1C->getDebugLoc(), VT, 1388 GA->getOffset() + 1389 (uint64_t)N1C->getSExtValue()); 1390 // fold ((c1-A)+c2) -> (c1+c2)-A 1391 if (N1C && N0.getOpcode() == ISD::SUB) 1392 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0))) 1393 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1394 DAG.getConstant(N1C->getAPIntValue()+ 1395 N0C->getAPIntValue(), VT), 1396 N0.getOperand(1)); 1397 // reassociate add 1398 SDValue RADD = ReassociateOps(ISD::ADD, N->getDebugLoc(), N0, N1); 1399 if (RADD.getNode() != 0) 1400 return RADD; 1401 // fold ((0-A) + B) -> B-A 1402 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) && 1403 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue()) 1404 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1, N0.getOperand(1)); 1405 // fold (A + (0-B)) -> A-B 1406 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) && 1407 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue()) 1408 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, N1.getOperand(1)); 1409 // fold (A+(B-A)) -> B 1410 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1)) 1411 return N1.getOperand(0); 1412 // fold ((B-A)+A) -> B 1413 if (N0.getOpcode() == ISD::SUB && N1 == N0.getOperand(1)) 1414 return N0.getOperand(0); 1415 // fold (A+(B-(A+C))) to (B-C) 1416 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD && 1417 N0 == N1.getOperand(1).getOperand(0)) 1418 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0), 1419 N1.getOperand(1).getOperand(1)); 1420 // fold (A+(B-(C+A))) to (B-C) 1421 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD && 1422 N0 == N1.getOperand(1).getOperand(1)) 1423 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0), 1424 N1.getOperand(1).getOperand(0)); 1425 // fold (A+((B-A)+or-C)) to (B+or-C) 1426 if ((N1.getOpcode() == ISD::SUB || N1.getOpcode() == ISD::ADD) && 1427 N1.getOperand(0).getOpcode() == ISD::SUB && 1428 N0 == N1.getOperand(0).getOperand(1)) 1429 return DAG.getNode(N1.getOpcode(), N->getDebugLoc(), VT, 1430 N1.getOperand(0).getOperand(0), N1.getOperand(1)); 1431 1432 // fold (A-B)+(C-D) to (A+C)-(B+D) when A or C is constant 1433 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB) { 1434 SDValue N00 = N0.getOperand(0); 1435 SDValue N01 = N0.getOperand(1); 1436 SDValue N10 = N1.getOperand(0); 1437 SDValue N11 = N1.getOperand(1); 1438 1439 if (isa<ConstantSDNode>(N00) || isa<ConstantSDNode>(N10)) 1440 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1441 DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, N00, N10), 1442 DAG.getNode(ISD::ADD, N1.getDebugLoc(), VT, N01, N11)); 1443 } 1444 1445 if (!VT.isVector() && SimplifyDemandedBits(SDValue(N, 0))) 1446 return SDValue(N, 0); 1447 1448 // fold (a+b) -> (a|b) iff a and b share no bits. 1449 if (VT.isInteger() && !VT.isVector()) { 1450 APInt LHSZero, LHSOne; 1451 APInt RHSZero, RHSOne; 1452 DAG.ComputeMaskedBits(N0, LHSZero, LHSOne); 1453 1454 if (LHSZero.getBoolValue()) { 1455 DAG.ComputeMaskedBits(N1, RHSZero, RHSOne); 1456 1457 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1458 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1459 if ((RHSZero & ~LHSZero) == ~LHSZero || (LHSZero & ~RHSZero) == ~RHSZero) 1460 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1); 1461 } 1462 } 1463 1464 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 1465 if (N0.getOpcode() == ISD::SHL && N0.getNode()->hasOneUse()) { 1466 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N0, N1, DAG); 1467 if (Result.getNode()) return Result; 1468 } 1469 if (N1.getOpcode() == ISD::SHL && N1.getNode()->hasOneUse()) { 1470 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N1, N0, DAG); 1471 if (Result.getNode()) return Result; 1472 } 1473 1474 // fold (add x, shl(0 - y, n)) -> sub(x, shl(y, n)) 1475 if (N1.getOpcode() == ISD::SHL && 1476 N1.getOperand(0).getOpcode() == ISD::SUB) 1477 if (ConstantSDNode *C = 1478 dyn_cast<ConstantSDNode>(N1.getOperand(0).getOperand(0))) 1479 if (C->getAPIntValue() == 0) 1480 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, 1481 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1482 N1.getOperand(0).getOperand(1), 1483 N1.getOperand(1))); 1484 if (N0.getOpcode() == ISD::SHL && 1485 N0.getOperand(0).getOpcode() == ISD::SUB) 1486 if (ConstantSDNode *C = 1487 dyn_cast<ConstantSDNode>(N0.getOperand(0).getOperand(0))) 1488 if (C->getAPIntValue() == 0) 1489 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1, 1490 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1491 N0.getOperand(0).getOperand(1), 1492 N0.getOperand(1))); 1493 1494 if (N1.getOpcode() == ISD::AND) { 1495 SDValue AndOp0 = N1.getOperand(0); 1496 ConstantSDNode *AndOp1 = dyn_cast<ConstantSDNode>(N1->getOperand(1)); 1497 unsigned NumSignBits = DAG.ComputeNumSignBits(AndOp0); 1498 unsigned DestBits = VT.getScalarType().getSizeInBits(); 1499 1500 // (add z, (and (sbbl x, x), 1)) -> (sub z, (sbbl x, x)) 1501 // and similar xforms where the inner op is either ~0 or 0. 1502 if (NumSignBits == DestBits && AndOp1 && AndOp1->isOne()) { 1503 DebugLoc DL = N->getDebugLoc(); 1504 return DAG.getNode(ISD::SUB, DL, VT, N->getOperand(0), AndOp0); 1505 } 1506 } 1507 1508 // add (sext i1), X -> sub X, (zext i1) 1509 if (N0.getOpcode() == ISD::SIGN_EXTEND && 1510 N0.getOperand(0).getValueType() == MVT::i1 && 1511 !TLI.isOperationLegal(ISD::SIGN_EXTEND, MVT::i1)) { 1512 DebugLoc DL = N->getDebugLoc(); 1513 SDValue ZExt = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0)); 1514 return DAG.getNode(ISD::SUB, DL, VT, N1, ZExt); 1515 } 1516 1517 return SDValue(); 1518} 1519 1520SDValue DAGCombiner::visitADDC(SDNode *N) { 1521 SDValue N0 = N->getOperand(0); 1522 SDValue N1 = N->getOperand(1); 1523 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1524 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1525 EVT VT = N0.getValueType(); 1526 1527 // If the flag result is dead, turn this into an ADD. 1528 if (!N->hasAnyUseOfValue(1)) 1529 return CombineTo(N, DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, N1), 1530 DAG.getNode(ISD::CARRY_FALSE, 1531 N->getDebugLoc(), MVT::Glue)); 1532 1533 // canonicalize constant to RHS. 1534 if (N0C && !N1C) 1535 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0); 1536 1537 // fold (addc x, 0) -> x + no carry out 1538 if (N1C && N1C->isNullValue()) 1539 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, 1540 N->getDebugLoc(), MVT::Glue)); 1541 1542 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits. 1543 APInt LHSZero, LHSOne; 1544 APInt RHSZero, RHSOne; 1545 DAG.ComputeMaskedBits(N0, LHSZero, LHSOne); 1546 1547 if (LHSZero.getBoolValue()) { 1548 DAG.ComputeMaskedBits(N1, RHSZero, RHSOne); 1549 1550 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1551 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1552 if ((RHSZero & ~LHSZero) == ~LHSZero || (LHSZero & ~RHSZero) == ~RHSZero) 1553 return CombineTo(N, DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1), 1554 DAG.getNode(ISD::CARRY_FALSE, 1555 N->getDebugLoc(), MVT::Glue)); 1556 } 1557 1558 return SDValue(); 1559} 1560 1561SDValue DAGCombiner::visitADDE(SDNode *N) { 1562 SDValue N0 = N->getOperand(0); 1563 SDValue N1 = N->getOperand(1); 1564 SDValue CarryIn = N->getOperand(2); 1565 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1566 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1567 1568 // canonicalize constant to RHS 1569 if (N0C && !N1C) 1570 return DAG.getNode(ISD::ADDE, N->getDebugLoc(), N->getVTList(), 1571 N1, N0, CarryIn); 1572 1573 // fold (adde x, y, false) -> (addc x, y) 1574 if (CarryIn.getOpcode() == ISD::CARRY_FALSE) 1575 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N0, N1); 1576 1577 return SDValue(); 1578} 1579 1580// Since it may not be valid to emit a fold to zero for vector initializers 1581// check if we can before folding. 1582static SDValue tryFoldToZero(DebugLoc DL, const TargetLowering &TLI, EVT VT, 1583 SelectionDAG &DAG, bool LegalOperations) { 1584 if (!VT.isVector()) { 1585 return DAG.getConstant(0, VT); 1586 } 1587 if (!LegalOperations || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) { 1588 // Produce a vector of zeros. 1589 SDValue El = DAG.getConstant(0, VT.getVectorElementType()); 1590 std::vector<SDValue> Ops(VT.getVectorNumElements(), El); 1591 return DAG.getNode(ISD::BUILD_VECTOR, DL, VT, 1592 &Ops[0], Ops.size()); 1593 } 1594 return SDValue(); 1595} 1596 1597SDValue DAGCombiner::visitSUB(SDNode *N) { 1598 SDValue N0 = N->getOperand(0); 1599 SDValue N1 = N->getOperand(1); 1600 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1601 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1602 ConstantSDNode *N1C1 = N1.getOpcode() != ISD::ADD ? 0 : 1603 dyn_cast<ConstantSDNode>(N1.getOperand(1).getNode()); 1604 EVT VT = N0.getValueType(); 1605 1606 // fold vector ops 1607 if (VT.isVector()) { 1608 SDValue FoldedVOp = SimplifyVBinOp(N); 1609 if (FoldedVOp.getNode()) return FoldedVOp; 1610 } 1611 1612 // fold (sub x, x) -> 0 1613 // FIXME: Refactor this and xor and other similar operations together. 1614 if (N0 == N1) 1615 return tryFoldToZero(N->getDebugLoc(), TLI, VT, DAG, LegalOperations); 1616 // fold (sub c1, c2) -> c1-c2 1617 if (N0C && N1C) 1618 return DAG.FoldConstantArithmetic(ISD::SUB, VT, N0C, N1C); 1619 // fold (sub x, c) -> (add x, -c) 1620 if (N1C) 1621 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, 1622 DAG.getConstant(-N1C->getAPIntValue(), VT)); 1623 // Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1) 1624 if (N0C && N0C->isAllOnesValue()) 1625 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0); 1626 // fold A-(A-B) -> B 1627 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(0)) 1628 return N1.getOperand(1); 1629 // fold (A+B)-A -> B 1630 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1) 1631 return N0.getOperand(1); 1632 // fold (A+B)-B -> A 1633 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1) 1634 return N0.getOperand(0); 1635 // fold C2-(A+C1) -> (C2-C1)-A 1636 if (N1.getOpcode() == ISD::ADD && N0C && N1C1) { 1637 SDValue NewC = DAG.getConstant((N0C->getAPIntValue() - N1C1->getAPIntValue()), VT); 1638 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, NewC, 1639 N1.getOperand(0)); 1640 } 1641 // fold ((A+(B+or-C))-B) -> A+or-C 1642 if (N0.getOpcode() == ISD::ADD && 1643 (N0.getOperand(1).getOpcode() == ISD::SUB || 1644 N0.getOperand(1).getOpcode() == ISD::ADD) && 1645 N0.getOperand(1).getOperand(0) == N1) 1646 return DAG.getNode(N0.getOperand(1).getOpcode(), N->getDebugLoc(), VT, 1647 N0.getOperand(0), N0.getOperand(1).getOperand(1)); 1648 // fold ((A+(C+B))-B) -> A+C 1649 if (N0.getOpcode() == ISD::ADD && 1650 N0.getOperand(1).getOpcode() == ISD::ADD && 1651 N0.getOperand(1).getOperand(1) == N1) 1652 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, 1653 N0.getOperand(0), N0.getOperand(1).getOperand(0)); 1654 // fold ((A-(B-C))-C) -> A-B 1655 if (N0.getOpcode() == ISD::SUB && 1656 N0.getOperand(1).getOpcode() == ISD::SUB && 1657 N0.getOperand(1).getOperand(1) == N1) 1658 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1659 N0.getOperand(0), N0.getOperand(1).getOperand(0)); 1660 1661 // If either operand of a sub is undef, the result is undef 1662 if (N0.getOpcode() == ISD::UNDEF) 1663 return N0; 1664 if (N1.getOpcode() == ISD::UNDEF) 1665 return N1; 1666 1667 // If the relocation model supports it, consider symbol offsets. 1668 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0)) 1669 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA)) { 1670 // fold (sub Sym, c) -> Sym-c 1671 if (N1C && GA->getOpcode() == ISD::GlobalAddress) 1672 return DAG.getGlobalAddress(GA->getGlobal(), N1C->getDebugLoc(), VT, 1673 GA->getOffset() - 1674 (uint64_t)N1C->getSExtValue()); 1675 // fold (sub Sym+c1, Sym+c2) -> c1-c2 1676 if (GlobalAddressSDNode *GB = dyn_cast<GlobalAddressSDNode>(N1)) 1677 if (GA->getGlobal() == GB->getGlobal()) 1678 return DAG.getConstant((uint64_t)GA->getOffset() - GB->getOffset(), 1679 VT); 1680 } 1681 1682 return SDValue(); 1683} 1684 1685SDValue DAGCombiner::visitSUBC(SDNode *N) { 1686 SDValue N0 = N->getOperand(0); 1687 SDValue N1 = N->getOperand(1); 1688 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1689 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1690 EVT VT = N0.getValueType(); 1691 1692 // If the flag result is dead, turn this into an SUB. 1693 if (!N->hasAnyUseOfValue(1)) 1694 return CombineTo(N, DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, N1), 1695 DAG.getNode(ISD::CARRY_FALSE, N->getDebugLoc(), 1696 MVT::Glue)); 1697 1698 // fold (subc x, x) -> 0 + no borrow 1699 if (N0 == N1) 1700 return CombineTo(N, DAG.getConstant(0, VT), 1701 DAG.getNode(ISD::CARRY_FALSE, N->getDebugLoc(), 1702 MVT::Glue)); 1703 1704 // fold (subc x, 0) -> x + no borrow 1705 if (N1C && N1C->isNullValue()) 1706 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, N->getDebugLoc(), 1707 MVT::Glue)); 1708 1709 // Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1) + no borrow 1710 if (N0C && N0C->isAllOnesValue()) 1711 return CombineTo(N, DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0), 1712 DAG.getNode(ISD::CARRY_FALSE, N->getDebugLoc(), 1713 MVT::Glue)); 1714 1715 return SDValue(); 1716} 1717 1718SDValue DAGCombiner::visitSUBE(SDNode *N) { 1719 SDValue N0 = N->getOperand(0); 1720 SDValue N1 = N->getOperand(1); 1721 SDValue CarryIn = N->getOperand(2); 1722 1723 // fold (sube x, y, false) -> (subc x, y) 1724 if (CarryIn.getOpcode() == ISD::CARRY_FALSE) 1725 return DAG.getNode(ISD::SUBC, N->getDebugLoc(), N->getVTList(), N0, N1); 1726 1727 return SDValue(); 1728} 1729 1730SDValue DAGCombiner::visitMUL(SDNode *N) { 1731 SDValue N0 = N->getOperand(0); 1732 SDValue N1 = N->getOperand(1); 1733 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1734 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1735 EVT VT = N0.getValueType(); 1736 1737 // fold vector ops 1738 if (VT.isVector()) { 1739 SDValue FoldedVOp = SimplifyVBinOp(N); 1740 if (FoldedVOp.getNode()) return FoldedVOp; 1741 } 1742 1743 // fold (mul x, undef) -> 0 1744 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1745 return DAG.getConstant(0, VT); 1746 // fold (mul c1, c2) -> c1*c2 1747 if (N0C && N1C) 1748 return DAG.FoldConstantArithmetic(ISD::MUL, VT, N0C, N1C); 1749 // canonicalize constant to RHS 1750 if (N0C && !N1C) 1751 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, N1, N0); 1752 // fold (mul x, 0) -> 0 1753 if (N1C && N1C->isNullValue()) 1754 return N1; 1755 // fold (mul x, -1) -> 0-x 1756 if (N1C && N1C->isAllOnesValue()) 1757 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1758 DAG.getConstant(0, VT), N0); 1759 // fold (mul x, (1 << c)) -> x << c 1760 if (N1C && N1C->getAPIntValue().isPowerOf2()) 1761 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 1762 DAG.getConstant(N1C->getAPIntValue().logBase2(), 1763 getShiftAmountTy(N0.getValueType()))); 1764 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c 1765 if (N1C && (-N1C->getAPIntValue()).isPowerOf2()) { 1766 unsigned Log2Val = (-N1C->getAPIntValue()).logBase2(); 1767 // FIXME: If the input is something that is easily negated (e.g. a 1768 // single-use add), we should put the negate there. 1769 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1770 DAG.getConstant(0, VT), 1771 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 1772 DAG.getConstant(Log2Val, 1773 getShiftAmountTy(N0.getValueType())))); 1774 } 1775 // (mul (shl X, c1), c2) -> (mul X, c2 << c1) 1776 if (N1C && N0.getOpcode() == ISD::SHL && 1777 isa<ConstantSDNode>(N0.getOperand(1))) { 1778 SDValue C3 = DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1779 N1, N0.getOperand(1)); 1780 AddToWorkList(C3.getNode()); 1781 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1782 N0.getOperand(0), C3); 1783 } 1784 1785 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one 1786 // use. 1787 { 1788 SDValue Sh(0,0), Y(0,0); 1789 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)). 1790 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) && 1791 N0.getNode()->hasOneUse()) { 1792 Sh = N0; Y = N1; 1793 } else if (N1.getOpcode() == ISD::SHL && 1794 isa<ConstantSDNode>(N1.getOperand(1)) && 1795 N1.getNode()->hasOneUse()) { 1796 Sh = N1; Y = N0; 1797 } 1798 1799 if (Sh.getNode()) { 1800 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1801 Sh.getOperand(0), Y); 1802 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1803 Mul, Sh.getOperand(1)); 1804 } 1805 } 1806 1807 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2) 1808 if (N1C && N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse() && 1809 isa<ConstantSDNode>(N0.getOperand(1))) 1810 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, 1811 DAG.getNode(ISD::MUL, N0.getDebugLoc(), VT, 1812 N0.getOperand(0), N1), 1813 DAG.getNode(ISD::MUL, N1.getDebugLoc(), VT, 1814 N0.getOperand(1), N1)); 1815 1816 // reassociate mul 1817 SDValue RMUL = ReassociateOps(ISD::MUL, N->getDebugLoc(), N0, N1); 1818 if (RMUL.getNode() != 0) 1819 return RMUL; 1820 1821 return SDValue(); 1822} 1823 1824SDValue DAGCombiner::visitSDIV(SDNode *N) { 1825 SDValue N0 = N->getOperand(0); 1826 SDValue N1 = N->getOperand(1); 1827 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1828 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1829 EVT VT = N->getValueType(0); 1830 1831 // fold vector ops 1832 if (VT.isVector()) { 1833 SDValue FoldedVOp = SimplifyVBinOp(N); 1834 if (FoldedVOp.getNode()) return FoldedVOp; 1835 } 1836 1837 // fold (sdiv c1, c2) -> c1/c2 1838 if (N0C && N1C && !N1C->isNullValue()) 1839 return DAG.FoldConstantArithmetic(ISD::SDIV, VT, N0C, N1C); 1840 // fold (sdiv X, 1) -> X 1841 if (N1C && N1C->getAPIntValue() == 1LL) 1842 return N0; 1843 // fold (sdiv X, -1) -> 0-X 1844 if (N1C && N1C->isAllOnesValue()) 1845 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1846 DAG.getConstant(0, VT), N0); 1847 // If we know the sign bits of both operands are zero, strength reduce to a 1848 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2 1849 if (!VT.isVector()) { 1850 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 1851 return DAG.getNode(ISD::UDIV, N->getDebugLoc(), N1.getValueType(), 1852 N0, N1); 1853 } 1854 // fold (sdiv X, pow2) -> simple ops after legalize 1855 if (N1C && !N1C->isNullValue() && 1856 (N1C->getAPIntValue().isPowerOf2() || 1857 (-N1C->getAPIntValue()).isPowerOf2())) { 1858 // If dividing by powers of two is cheap, then don't perform the following 1859 // fold. 1860 if (TLI.isPow2DivCheap()) 1861 return SDValue(); 1862 1863 unsigned lg2 = N1C->getAPIntValue().countTrailingZeros(); 1864 1865 // Splat the sign bit into the register 1866 SDValue SGN = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0, 1867 DAG.getConstant(VT.getSizeInBits()-1, 1868 getShiftAmountTy(N0.getValueType()))); 1869 AddToWorkList(SGN.getNode()); 1870 1871 // Add (N0 < 0) ? abs2 - 1 : 0; 1872 SDValue SRL = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, SGN, 1873 DAG.getConstant(VT.getSizeInBits() - lg2, 1874 getShiftAmountTy(SGN.getValueType()))); 1875 SDValue ADD = DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, SRL); 1876 AddToWorkList(SRL.getNode()); 1877 AddToWorkList(ADD.getNode()); // Divide by pow2 1878 SDValue SRA = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, ADD, 1879 DAG.getConstant(lg2, getShiftAmountTy(ADD.getValueType()))); 1880 1881 // If we're dividing by a positive value, we're done. Otherwise, we must 1882 // negate the result. 1883 if (N1C->getAPIntValue().isNonNegative()) 1884 return SRA; 1885 1886 AddToWorkList(SRA.getNode()); 1887 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1888 DAG.getConstant(0, VT), SRA); 1889 } 1890 1891 // if integer divide is expensive and we satisfy the requirements, emit an 1892 // alternate sequence. 1893 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) { 1894 SDValue Op = BuildSDIV(N); 1895 if (Op.getNode()) return Op; 1896 } 1897 1898 // undef / X -> 0 1899 if (N0.getOpcode() == ISD::UNDEF) 1900 return DAG.getConstant(0, VT); 1901 // X / undef -> undef 1902 if (N1.getOpcode() == ISD::UNDEF) 1903 return N1; 1904 1905 return SDValue(); 1906} 1907 1908SDValue DAGCombiner::visitUDIV(SDNode *N) { 1909 SDValue N0 = N->getOperand(0); 1910 SDValue N1 = N->getOperand(1); 1911 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1912 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1913 EVT VT = N->getValueType(0); 1914 1915 // fold vector ops 1916 if (VT.isVector()) { 1917 SDValue FoldedVOp = SimplifyVBinOp(N); 1918 if (FoldedVOp.getNode()) return FoldedVOp; 1919 } 1920 1921 // fold (udiv c1, c2) -> c1/c2 1922 if (N0C && N1C && !N1C->isNullValue()) 1923 return DAG.FoldConstantArithmetic(ISD::UDIV, VT, N0C, N1C); 1924 // fold (udiv x, (1 << c)) -> x >>u c 1925 if (N1C && N1C->getAPIntValue().isPowerOf2()) 1926 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, 1927 DAG.getConstant(N1C->getAPIntValue().logBase2(), 1928 getShiftAmountTy(N0.getValueType()))); 1929 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2 1930 if (N1.getOpcode() == ISD::SHL) { 1931 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1932 if (SHC->getAPIntValue().isPowerOf2()) { 1933 EVT ADDVT = N1.getOperand(1).getValueType(); 1934 SDValue Add = DAG.getNode(ISD::ADD, N->getDebugLoc(), ADDVT, 1935 N1.getOperand(1), 1936 DAG.getConstant(SHC->getAPIntValue() 1937 .logBase2(), 1938 ADDVT)); 1939 AddToWorkList(Add.getNode()); 1940 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, Add); 1941 } 1942 } 1943 } 1944 // fold (udiv x, c) -> alternate 1945 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) { 1946 SDValue Op = BuildUDIV(N); 1947 if (Op.getNode()) return Op; 1948 } 1949 1950 // undef / X -> 0 1951 if (N0.getOpcode() == ISD::UNDEF) 1952 return DAG.getConstant(0, VT); 1953 // X / undef -> undef 1954 if (N1.getOpcode() == ISD::UNDEF) 1955 return N1; 1956 1957 return SDValue(); 1958} 1959 1960SDValue DAGCombiner::visitSREM(SDNode *N) { 1961 SDValue N0 = N->getOperand(0); 1962 SDValue N1 = N->getOperand(1); 1963 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1964 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1965 EVT VT = N->getValueType(0); 1966 1967 // fold (srem c1, c2) -> c1%c2 1968 if (N0C && N1C && !N1C->isNullValue()) 1969 return DAG.FoldConstantArithmetic(ISD::SREM, VT, N0C, N1C); 1970 // If we know the sign bits of both operands are zero, strength reduce to a 1971 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15 1972 if (!VT.isVector()) { 1973 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 1974 return DAG.getNode(ISD::UREM, N->getDebugLoc(), VT, N0, N1); 1975 } 1976 1977 // If X/C can be simplified by the division-by-constant logic, lower 1978 // X%C to the equivalent of X-X/C*C. 1979 if (N1C && !N1C->isNullValue()) { 1980 SDValue Div = DAG.getNode(ISD::SDIV, N->getDebugLoc(), VT, N0, N1); 1981 AddToWorkList(Div.getNode()); 1982 SDValue OptimizedDiv = combine(Div.getNode()); 1983 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) { 1984 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1985 OptimizedDiv, N1); 1986 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul); 1987 AddToWorkList(Mul.getNode()); 1988 return Sub; 1989 } 1990 } 1991 1992 // undef % X -> 0 1993 if (N0.getOpcode() == ISD::UNDEF) 1994 return DAG.getConstant(0, VT); 1995 // X % undef -> undef 1996 if (N1.getOpcode() == ISD::UNDEF) 1997 return N1; 1998 1999 return SDValue(); 2000} 2001 2002SDValue DAGCombiner::visitUREM(SDNode *N) { 2003 SDValue N0 = N->getOperand(0); 2004 SDValue N1 = N->getOperand(1); 2005 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2006 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2007 EVT VT = N->getValueType(0); 2008 2009 // fold (urem c1, c2) -> c1%c2 2010 if (N0C && N1C && !N1C->isNullValue()) 2011 return DAG.FoldConstantArithmetic(ISD::UREM, VT, N0C, N1C); 2012 // fold (urem x, pow2) -> (and x, pow2-1) 2013 if (N1C && !N1C->isNullValue() && N1C->getAPIntValue().isPowerOf2()) 2014 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, 2015 DAG.getConstant(N1C->getAPIntValue()-1,VT)); 2016 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1)) 2017 if (N1.getOpcode() == ISD::SHL) { 2018 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 2019 if (SHC->getAPIntValue().isPowerOf2()) { 2020 SDValue Add = 2021 DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, 2022 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), 2023 VT)); 2024 AddToWorkList(Add.getNode()); 2025 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, Add); 2026 } 2027 } 2028 } 2029 2030 // If X/C can be simplified by the division-by-constant logic, lower 2031 // X%C to the equivalent of X-X/C*C. 2032 if (N1C && !N1C->isNullValue()) { 2033 SDValue Div = DAG.getNode(ISD::UDIV, N->getDebugLoc(), VT, N0, N1); 2034 AddToWorkList(Div.getNode()); 2035 SDValue OptimizedDiv = combine(Div.getNode()); 2036 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) { 2037 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 2038 OptimizedDiv, N1); 2039 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul); 2040 AddToWorkList(Mul.getNode()); 2041 return Sub; 2042 } 2043 } 2044 2045 // undef % X -> 0 2046 if (N0.getOpcode() == ISD::UNDEF) 2047 return DAG.getConstant(0, VT); 2048 // X % undef -> undef 2049 if (N1.getOpcode() == ISD::UNDEF) 2050 return N1; 2051 2052 return SDValue(); 2053} 2054 2055SDValue DAGCombiner::visitMULHS(SDNode *N) { 2056 SDValue N0 = N->getOperand(0); 2057 SDValue N1 = N->getOperand(1); 2058 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2059 EVT VT = N->getValueType(0); 2060 DebugLoc DL = N->getDebugLoc(); 2061 2062 // fold (mulhs x, 0) -> 0 2063 if (N1C && N1C->isNullValue()) 2064 return N1; 2065 // fold (mulhs x, 1) -> (sra x, size(x)-1) 2066 if (N1C && N1C->getAPIntValue() == 1) 2067 return DAG.getNode(ISD::SRA, N->getDebugLoc(), N0.getValueType(), N0, 2068 DAG.getConstant(N0.getValueType().getSizeInBits() - 1, 2069 getShiftAmountTy(N0.getValueType()))); 2070 // fold (mulhs x, undef) -> 0 2071 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 2072 return DAG.getConstant(0, VT); 2073 2074 // If the type twice as wide is legal, transform the mulhs to a wider multiply 2075 // plus a shift. 2076 if (VT.isSimple() && !VT.isVector()) { 2077 MVT Simple = VT.getSimpleVT(); 2078 unsigned SimpleSize = Simple.getSizeInBits(); 2079 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2); 2080 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { 2081 N0 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N0); 2082 N1 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N1); 2083 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1); 2084 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1, 2085 DAG.getConstant(SimpleSize, getShiftAmountTy(N1.getValueType()))); 2086 return DAG.getNode(ISD::TRUNCATE, DL, VT, N1); 2087 } 2088 } 2089 2090 return SDValue(); 2091} 2092 2093SDValue DAGCombiner::visitMULHU(SDNode *N) { 2094 SDValue N0 = N->getOperand(0); 2095 SDValue N1 = N->getOperand(1); 2096 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2097 EVT VT = N->getValueType(0); 2098 DebugLoc DL = N->getDebugLoc(); 2099 2100 // fold (mulhu x, 0) -> 0 2101 if (N1C && N1C->isNullValue()) 2102 return N1; 2103 // fold (mulhu x, 1) -> 0 2104 if (N1C && N1C->getAPIntValue() == 1) 2105 return DAG.getConstant(0, N0.getValueType()); 2106 // fold (mulhu x, undef) -> 0 2107 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 2108 return DAG.getConstant(0, VT); 2109 2110 // If the type twice as wide is legal, transform the mulhu to a wider multiply 2111 // plus a shift. 2112 if (VT.isSimple() && !VT.isVector()) { 2113 MVT Simple = VT.getSimpleVT(); 2114 unsigned SimpleSize = Simple.getSizeInBits(); 2115 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2); 2116 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { 2117 N0 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N0); 2118 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N1); 2119 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1); 2120 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1, 2121 DAG.getConstant(SimpleSize, getShiftAmountTy(N1.getValueType()))); 2122 return DAG.getNode(ISD::TRUNCATE, DL, VT, N1); 2123 } 2124 } 2125 2126 return SDValue(); 2127} 2128 2129/// SimplifyNodeWithTwoResults - Perform optimizations common to nodes that 2130/// compute two values. LoOp and HiOp give the opcodes for the two computations 2131/// that are being performed. Return true if a simplification was made. 2132/// 2133SDValue DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 2134 unsigned HiOp) { 2135 // If the high half is not needed, just compute the low half. 2136 bool HiExists = N->hasAnyUseOfValue(1); 2137 if (!HiExists && 2138 (!LegalOperations || 2139 TLI.isOperationLegal(LoOp, N->getValueType(0)))) { 2140 SDValue Res = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0), 2141 N->op_begin(), N->getNumOperands()); 2142 return CombineTo(N, Res, Res); 2143 } 2144 2145 // If the low half is not needed, just compute the high half. 2146 bool LoExists = N->hasAnyUseOfValue(0); 2147 if (!LoExists && 2148 (!LegalOperations || 2149 TLI.isOperationLegal(HiOp, N->getValueType(1)))) { 2150 SDValue Res = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1), 2151 N->op_begin(), N->getNumOperands()); 2152 return CombineTo(N, Res, Res); 2153 } 2154 2155 // If both halves are used, return as it is. 2156 if (LoExists && HiExists) 2157 return SDValue(); 2158 2159 // If the two computed results can be simplified separately, separate them. 2160 if (LoExists) { 2161 SDValue Lo = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0), 2162 N->op_begin(), N->getNumOperands()); 2163 AddToWorkList(Lo.getNode()); 2164 SDValue LoOpt = combine(Lo.getNode()); 2165 if (LoOpt.getNode() && LoOpt.getNode() != Lo.getNode() && 2166 (!LegalOperations || 2167 TLI.isOperationLegal(LoOpt.getOpcode(), LoOpt.getValueType()))) 2168 return CombineTo(N, LoOpt, LoOpt); 2169 } 2170 2171 if (HiExists) { 2172 SDValue Hi = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1), 2173 N->op_begin(), N->getNumOperands()); 2174 AddToWorkList(Hi.getNode()); 2175 SDValue HiOpt = combine(Hi.getNode()); 2176 if (HiOpt.getNode() && HiOpt != Hi && 2177 (!LegalOperations || 2178 TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType()))) 2179 return CombineTo(N, HiOpt, HiOpt); 2180 } 2181 2182 return SDValue(); 2183} 2184 2185SDValue DAGCombiner::visitSMUL_LOHI(SDNode *N) { 2186 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS); 2187 if (Res.getNode()) return Res; 2188 2189 EVT VT = N->getValueType(0); 2190 DebugLoc DL = N->getDebugLoc(); 2191 2192 // If the type twice as wide is legal, transform the mulhu to a wider multiply 2193 // plus a shift. 2194 if (VT.isSimple() && !VT.isVector()) { 2195 MVT Simple = VT.getSimpleVT(); 2196 unsigned SimpleSize = Simple.getSizeInBits(); 2197 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2); 2198 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { 2199 SDValue Lo = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(0)); 2200 SDValue Hi = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(1)); 2201 Lo = DAG.getNode(ISD::MUL, DL, NewVT, Lo, Hi); 2202 // Compute the high part as N1. 2203 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo, 2204 DAG.getConstant(SimpleSize, getShiftAmountTy(Lo.getValueType()))); 2205 Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi); 2206 // Compute the low part as N0. 2207 Lo = DAG.getNode(ISD::TRUNCATE, DL, VT, Lo); 2208 return CombineTo(N, Lo, Hi); 2209 } 2210 } 2211 2212 return SDValue(); 2213} 2214 2215SDValue DAGCombiner::visitUMUL_LOHI(SDNode *N) { 2216 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU); 2217 if (Res.getNode()) return Res; 2218 2219 EVT VT = N->getValueType(0); 2220 DebugLoc DL = N->getDebugLoc(); 2221 2222 // If the type twice as wide is legal, transform the mulhu to a wider multiply 2223 // plus a shift. 2224 if (VT.isSimple() && !VT.isVector()) { 2225 MVT Simple = VT.getSimpleVT(); 2226 unsigned SimpleSize = Simple.getSizeInBits(); 2227 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2); 2228 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { 2229 SDValue Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(0)); 2230 SDValue Hi = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(1)); 2231 Lo = DAG.getNode(ISD::MUL, DL, NewVT, Lo, Hi); 2232 // Compute the high part as N1. 2233 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo, 2234 DAG.getConstant(SimpleSize, getShiftAmountTy(Lo.getValueType()))); 2235 Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi); 2236 // Compute the low part as N0. 2237 Lo = DAG.getNode(ISD::TRUNCATE, DL, VT, Lo); 2238 return CombineTo(N, Lo, Hi); 2239 } 2240 } 2241 2242 return SDValue(); 2243} 2244 2245SDValue DAGCombiner::visitSMULO(SDNode *N) { 2246 // (smulo x, 2) -> (saddo x, x) 2247 if (ConstantSDNode *C2 = dyn_cast<ConstantSDNode>(N->getOperand(1))) 2248 if (C2->getAPIntValue() == 2) 2249 return DAG.getNode(ISD::SADDO, N->getDebugLoc(), N->getVTList(), 2250 N->getOperand(0), N->getOperand(0)); 2251 2252 return SDValue(); 2253} 2254 2255SDValue DAGCombiner::visitUMULO(SDNode *N) { 2256 // (umulo x, 2) -> (uaddo x, x) 2257 if (ConstantSDNode *C2 = dyn_cast<ConstantSDNode>(N->getOperand(1))) 2258 if (C2->getAPIntValue() == 2) 2259 return DAG.getNode(ISD::UADDO, N->getDebugLoc(), N->getVTList(), 2260 N->getOperand(0), N->getOperand(0)); 2261 2262 return SDValue(); 2263} 2264 2265SDValue DAGCombiner::visitSDIVREM(SDNode *N) { 2266 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM); 2267 if (Res.getNode()) return Res; 2268 2269 return SDValue(); 2270} 2271 2272SDValue DAGCombiner::visitUDIVREM(SDNode *N) { 2273 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM); 2274 if (Res.getNode()) return Res; 2275 2276 return SDValue(); 2277} 2278 2279/// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with 2280/// two operands of the same opcode, try to simplify it. 2281SDValue DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) { 2282 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1); 2283 EVT VT = N0.getValueType(); 2284 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!"); 2285 2286 // Bail early if none of these transforms apply. 2287 if (N0.getNode()->getNumOperands() == 0) return SDValue(); 2288 2289 // For each of OP in AND/OR/XOR: 2290 // fold (OP (zext x), (zext y)) -> (zext (OP x, y)) 2291 // fold (OP (sext x), (sext y)) -> (sext (OP x, y)) 2292 // fold (OP (aext x), (aext y)) -> (aext (OP x, y)) 2293 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y)) (if trunc isn't free) 2294 // 2295 // do not sink logical op inside of a vector extend, since it may combine 2296 // into a vsetcc. 2297 EVT Op0VT = N0.getOperand(0).getValueType(); 2298 if ((N0.getOpcode() == ISD::ZERO_EXTEND || 2299 N0.getOpcode() == ISD::SIGN_EXTEND || 2300 // Avoid infinite looping with PromoteIntBinOp. 2301 (N0.getOpcode() == ISD::ANY_EXTEND && 2302 (!LegalTypes || TLI.isTypeDesirableForOp(N->getOpcode(), Op0VT))) || 2303 (N0.getOpcode() == ISD::TRUNCATE && 2304 (!TLI.isZExtFree(VT, Op0VT) || 2305 !TLI.isTruncateFree(Op0VT, VT)) && 2306 TLI.isTypeLegal(Op0VT))) && 2307 !VT.isVector() && 2308 Op0VT == N1.getOperand(0).getValueType() && 2309 (!LegalOperations || TLI.isOperationLegal(N->getOpcode(), Op0VT))) { 2310 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(), 2311 N0.getOperand(0).getValueType(), 2312 N0.getOperand(0), N1.getOperand(0)); 2313 AddToWorkList(ORNode.getNode()); 2314 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, ORNode); 2315 } 2316 2317 // For each of OP in SHL/SRL/SRA/AND... 2318 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z) 2319 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z) 2320 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z) 2321 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL || 2322 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) && 2323 N0.getOperand(1) == N1.getOperand(1)) { 2324 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(), 2325 N0.getOperand(0).getValueType(), 2326 N0.getOperand(0), N1.getOperand(0)); 2327 AddToWorkList(ORNode.getNode()); 2328 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, 2329 ORNode, N0.getOperand(1)); 2330 } 2331 2332 // Simplify xor/and/or (bitcast(A), bitcast(B)) -> bitcast(op (A,B)) 2333 // Only perform this optimization after type legalization and before 2334 // LegalizeVectorOprs. LegalizeVectorOprs promotes vector operations by 2335 // adding bitcasts. For example (xor v4i32) is promoted to (v2i64), and 2336 // we don't want to undo this promotion. 2337 // We also handle SCALAR_TO_VECTOR because xor/or/and operations are cheaper 2338 // on scalars. 2339 if ((N0.getOpcode() == ISD::BITCAST || N0.getOpcode() == ISD::SCALAR_TO_VECTOR) 2340 && Level == AfterLegalizeVectorOps) { 2341 SDValue In0 = N0.getOperand(0); 2342 SDValue In1 = N1.getOperand(0); 2343 EVT In0Ty = In0.getValueType(); 2344 EVT In1Ty = In1.getValueType(); 2345 // If both incoming values are integers, and the original types are the same. 2346 if (In0Ty.isInteger() && In1Ty.isInteger() && In0Ty == In1Ty) { 2347 SDValue Op = DAG.getNode(N->getOpcode(), N->getDebugLoc(), In0Ty, In0, In1); 2348 SDValue BC = DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, Op); 2349 AddToWorkList(Op.getNode()); 2350 return BC; 2351 } 2352 } 2353 2354 // Xor/and/or are indifferent to the swizzle operation (shuffle of one value). 2355 // Simplify xor/and/or (shuff(A), shuff(B)) -> shuff(op (A,B)) 2356 // If both shuffles use the same mask, and both shuffle within a single 2357 // vector, then it is worthwhile to move the swizzle after the operation. 2358 // The type-legalizer generates this pattern when loading illegal 2359 // vector types from memory. In many cases this allows additional shuffle 2360 // optimizations. 2361 if (N0.getOpcode() == ISD::VECTOR_SHUFFLE && Level < AfterLegalizeDAG && 2362 N0.getOperand(1).getOpcode() == ISD::UNDEF && 2363 N1.getOperand(1).getOpcode() == ISD::UNDEF) { 2364 ShuffleVectorSDNode *SVN0 = cast<ShuffleVectorSDNode>(N0); 2365 ShuffleVectorSDNode *SVN1 = cast<ShuffleVectorSDNode>(N1); 2366 2367 assert(N0.getOperand(0).getValueType() == N1.getOperand(1).getValueType() && 2368 "Inputs to shuffles are not the same type"); 2369 2370 unsigned NumElts = VT.getVectorNumElements(); 2371 2372 // Check that both shuffles use the same mask. The masks are known to be of 2373 // the same length because the result vector type is the same. 2374 bool SameMask = true; 2375 for (unsigned i = 0; i != NumElts; ++i) { 2376 int Idx0 = SVN0->getMaskElt(i); 2377 int Idx1 = SVN1->getMaskElt(i); 2378 if (Idx0 != Idx1) { 2379 SameMask = false; 2380 break; 2381 } 2382 } 2383 2384 if (SameMask) { 2385 SDValue Op = DAG.getNode(N->getOpcode(), N->getDebugLoc(), VT, 2386 N0.getOperand(0), N1.getOperand(0)); 2387 AddToWorkList(Op.getNode()); 2388 return DAG.getVectorShuffle(VT, N->getDebugLoc(), Op, 2389 DAG.getUNDEF(VT), &SVN0->getMask()[0]); 2390 } 2391 } 2392 2393 return SDValue(); 2394} 2395 2396SDValue DAGCombiner::visitAND(SDNode *N) { 2397 SDValue N0 = N->getOperand(0); 2398 SDValue N1 = N->getOperand(1); 2399 SDValue LL, LR, RL, RR, CC0, CC1; 2400 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2401 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2402 EVT VT = N1.getValueType(); 2403 unsigned BitWidth = VT.getScalarType().getSizeInBits(); 2404 2405 // fold vector ops 2406 if (VT.isVector()) { 2407 SDValue FoldedVOp = SimplifyVBinOp(N); 2408 if (FoldedVOp.getNode()) return FoldedVOp; 2409 } 2410 2411 // fold (and x, undef) -> 0 2412 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 2413 return DAG.getConstant(0, VT); 2414 // fold (and c1, c2) -> c1&c2 2415 if (N0C && N1C) 2416 return DAG.FoldConstantArithmetic(ISD::AND, VT, N0C, N1C); 2417 // canonicalize constant to RHS 2418 if (N0C && !N1C) 2419 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N1, N0); 2420 // fold (and x, -1) -> x 2421 if (N1C && N1C->isAllOnesValue()) 2422 return N0; 2423 // if (and x, c) is known to be zero, return 0 2424 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0), 2425 APInt::getAllOnesValue(BitWidth))) 2426 return DAG.getConstant(0, VT); 2427 // reassociate and 2428 SDValue RAND = ReassociateOps(ISD::AND, N->getDebugLoc(), N0, N1); 2429 if (RAND.getNode() != 0) 2430 return RAND; 2431 // fold (and (or x, C), D) -> D if (C & D) == D 2432 if (N1C && N0.getOpcode() == ISD::OR) 2433 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 2434 if ((ORI->getAPIntValue() & N1C->getAPIntValue()) == N1C->getAPIntValue()) 2435 return N1; 2436 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits. 2437 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 2438 SDValue N0Op0 = N0.getOperand(0); 2439 APInt Mask = ~N1C->getAPIntValue(); 2440 Mask = Mask.trunc(N0Op0.getValueSizeInBits()); 2441 if (DAG.MaskedValueIsZero(N0Op0, Mask)) { 2442 SDValue Zext = DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), 2443 N0.getValueType(), N0Op0); 2444 2445 // Replace uses of the AND with uses of the Zero extend node. 2446 CombineTo(N, Zext); 2447 2448 // We actually want to replace all uses of the any_extend with the 2449 // zero_extend, to avoid duplicating things. This will later cause this 2450 // AND to be folded. 2451 CombineTo(N0.getNode(), Zext); 2452 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2453 } 2454 } 2455 // similarly fold (and (X (load ([non_ext|any_ext|zero_ext] V))), c) -> 2456 // (X (load ([non_ext|zero_ext] V))) if 'and' only clears top bits which must 2457 // already be zero by virtue of the width of the base type of the load. 2458 // 2459 // the 'X' node here can either be nothing or an extract_vector_elt to catch 2460 // more cases. 2461 if ((N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT && 2462 N0.getOperand(0).getOpcode() == ISD::LOAD) || 2463 N0.getOpcode() == ISD::LOAD) { 2464 LoadSDNode *Load = cast<LoadSDNode>( (N0.getOpcode() == ISD::LOAD) ? 2465 N0 : N0.getOperand(0) ); 2466 2467 // Get the constant (if applicable) the zero'th operand is being ANDed with. 2468 // This can be a pure constant or a vector splat, in which case we treat the 2469 // vector as a scalar and use the splat value. 2470 APInt Constant = APInt::getNullValue(1); 2471 if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(N1)) { 2472 Constant = C->getAPIntValue(); 2473 } else if (BuildVectorSDNode *Vector = dyn_cast<BuildVectorSDNode>(N1)) { 2474 APInt SplatValue, SplatUndef; 2475 unsigned SplatBitSize; 2476 bool HasAnyUndefs; 2477 bool IsSplat = Vector->isConstantSplat(SplatValue, SplatUndef, 2478 SplatBitSize, HasAnyUndefs); 2479 if (IsSplat) { 2480 // Undef bits can contribute to a possible optimisation if set, so 2481 // set them. 2482 SplatValue |= SplatUndef; 2483 2484 // The splat value may be something like "0x00FFFFFF", which means 0 for 2485 // the first vector value and FF for the rest, repeating. We need a mask 2486 // that will apply equally to all members of the vector, so AND all the 2487 // lanes of the constant together. 2488 EVT VT = Vector->getValueType(0); 2489 unsigned BitWidth = VT.getVectorElementType().getSizeInBits(); 2490 Constant = APInt::getAllOnesValue(BitWidth); 2491 for (unsigned i = 0, n = VT.getVectorNumElements(); i < n; ++i) 2492 Constant &= SplatValue.lshr(i*BitWidth).zextOrTrunc(BitWidth); 2493 } 2494 } 2495 2496 // If we want to change an EXTLOAD to a ZEXTLOAD, ensure a ZEXTLOAD is 2497 // actually legal and isn't going to get expanded, else this is a false 2498 // optimisation. 2499 bool CanZextLoadProfitably = TLI.isLoadExtLegal(ISD::ZEXTLOAD, 2500 Load->getMemoryVT()); 2501 2502 // Resize the constant to the same size as the original memory access before 2503 // extension. If it is still the AllOnesValue then this AND is completely 2504 // unneeded. 2505 Constant = 2506 Constant.zextOrTrunc(Load->getMemoryVT().getScalarType().getSizeInBits()); 2507 2508 bool B; 2509 switch (Load->getExtensionType()) { 2510 default: B = false; break; 2511 case ISD::EXTLOAD: B = CanZextLoadProfitably; break; 2512 case ISD::ZEXTLOAD: 2513 case ISD::NON_EXTLOAD: B = true; break; 2514 } 2515 2516 if (B && Constant.isAllOnesValue()) { 2517 // If the load type was an EXTLOAD, convert to ZEXTLOAD in order to 2518 // preserve semantics once we get rid of the AND. 2519 SDValue NewLoad(Load, 0); 2520 if (Load->getExtensionType() == ISD::EXTLOAD) { 2521 NewLoad = DAG.getLoad(Load->getAddressingMode(), ISD::ZEXTLOAD, 2522 Load->getValueType(0), Load->getDebugLoc(), 2523 Load->getChain(), Load->getBasePtr(), 2524 Load->getOffset(), Load->getMemoryVT(), 2525 Load->getMemOperand()); 2526 // Replace uses of the EXTLOAD with the new ZEXTLOAD. 2527 CombineTo(Load, NewLoad.getValue(0), NewLoad.getValue(1)); 2528 } 2529 2530 // Fold the AND away, taking care not to fold to the old load node if we 2531 // replaced it. 2532 CombineTo(N, (N0.getNode() == Load) ? NewLoad : N0); 2533 2534 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2535 } 2536 } 2537 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y)) 2538 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 2539 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 2540 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 2541 2542 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 2543 LL.getValueType().isInteger()) { 2544 // fold (and (seteq X, 0), (seteq Y, 0)) -> (seteq (or X, Y), 0) 2545 if (cast<ConstantSDNode>(LR)->isNullValue() && Op1 == ISD::SETEQ) { 2546 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(), 2547 LR.getValueType(), LL, RL); 2548 AddToWorkList(ORNode.getNode()); 2549 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 2550 } 2551 // fold (and (seteq X, -1), (seteq Y, -1)) -> (seteq (and X, Y), -1) 2552 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) { 2553 SDValue ANDNode = DAG.getNode(ISD::AND, N0.getDebugLoc(), 2554 LR.getValueType(), LL, RL); 2555 AddToWorkList(ANDNode.getNode()); 2556 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1); 2557 } 2558 // fold (and (setgt X, -1), (setgt Y, -1)) -> (setgt (or X, Y), -1) 2559 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) { 2560 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(), 2561 LR.getValueType(), LL, RL); 2562 AddToWorkList(ORNode.getNode()); 2563 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 2564 } 2565 } 2566 // canonicalize equivalent to ll == rl 2567 if (LL == RR && LR == RL) { 2568 Op1 = ISD::getSetCCSwappedOperands(Op1); 2569 std::swap(RL, RR); 2570 } 2571 if (LL == RL && LR == RR) { 2572 bool isInteger = LL.getValueType().isInteger(); 2573 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger); 2574 if (Result != ISD::SETCC_INVALID && 2575 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType()))) 2576 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(), 2577 LL, LR, Result); 2578 } 2579 } 2580 2581 // Simplify: (and (op x...), (op y...)) -> (op (and x, y)) 2582 if (N0.getOpcode() == N1.getOpcode()) { 2583 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 2584 if (Tmp.getNode()) return Tmp; 2585 } 2586 2587 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1) 2588 // fold (and (sra)) -> (and (srl)) when possible. 2589 if (!VT.isVector() && 2590 SimplifyDemandedBits(SDValue(N, 0))) 2591 return SDValue(N, 0); 2592 2593 // fold (zext_inreg (extload x)) -> (zextload x) 2594 if (ISD::isEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode())) { 2595 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2596 EVT MemVT = LN0->getMemoryVT(); 2597 // If we zero all the possible extended bits, then we can turn this into 2598 // a zextload if we are running before legalize or the operation is legal. 2599 unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits(); 2600 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 2601 BitWidth - MemVT.getScalarType().getSizeInBits())) && 2602 ((!LegalOperations && !LN0->isVolatile()) || 2603 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) { 2604 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT, 2605 LN0->getChain(), LN0->getBasePtr(), 2606 LN0->getPointerInfo(), MemVT, 2607 LN0->isVolatile(), LN0->isNonTemporal(), 2608 LN0->getAlignment()); 2609 AddToWorkList(N); 2610 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 2611 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2612 } 2613 } 2614 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use 2615 if (ISD::isSEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 2616 N0.hasOneUse()) { 2617 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2618 EVT MemVT = LN0->getMemoryVT(); 2619 // If we zero all the possible extended bits, then we can turn this into 2620 // a zextload if we are running before legalize or the operation is legal. 2621 unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits(); 2622 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 2623 BitWidth - MemVT.getScalarType().getSizeInBits())) && 2624 ((!LegalOperations && !LN0->isVolatile()) || 2625 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) { 2626 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT, 2627 LN0->getChain(), 2628 LN0->getBasePtr(), LN0->getPointerInfo(), 2629 MemVT, 2630 LN0->isVolatile(), LN0->isNonTemporal(), 2631 LN0->getAlignment()); 2632 AddToWorkList(N); 2633 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 2634 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2635 } 2636 } 2637 2638 // fold (and (load x), 255) -> (zextload x, i8) 2639 // fold (and (extload x, i16), 255) -> (zextload x, i8) 2640 // fold (and (any_ext (extload x, i16)), 255) -> (zextload x, i8) 2641 if (N1C && (N0.getOpcode() == ISD::LOAD || 2642 (N0.getOpcode() == ISD::ANY_EXTEND && 2643 N0.getOperand(0).getOpcode() == ISD::LOAD))) { 2644 bool HasAnyExt = N0.getOpcode() == ISD::ANY_EXTEND; 2645 LoadSDNode *LN0 = HasAnyExt 2646 ? cast<LoadSDNode>(N0.getOperand(0)) 2647 : cast<LoadSDNode>(N0); 2648 if (LN0->getExtensionType() != ISD::SEXTLOAD && 2649 LN0->isUnindexed() && N0.hasOneUse() && LN0->hasOneUse()) { 2650 uint32_t ActiveBits = N1C->getAPIntValue().getActiveBits(); 2651 if (ActiveBits > 0 && APIntOps::isMask(ActiveBits, N1C->getAPIntValue())){ 2652 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), ActiveBits); 2653 EVT LoadedVT = LN0->getMemoryVT(); 2654 2655 if (ExtVT == LoadedVT && 2656 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) { 2657 EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT; 2658 2659 SDValue NewLoad = 2660 DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), LoadResultTy, 2661 LN0->getChain(), LN0->getBasePtr(), 2662 LN0->getPointerInfo(), 2663 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(), 2664 LN0->getAlignment()); 2665 AddToWorkList(N); 2666 CombineTo(LN0, NewLoad, NewLoad.getValue(1)); 2667 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2668 } 2669 2670 // Do not change the width of a volatile load. 2671 // Do not generate loads of non-round integer types since these can 2672 // be expensive (and would be wrong if the type is not byte sized). 2673 if (!LN0->isVolatile() && LoadedVT.bitsGT(ExtVT) && ExtVT.isRound() && 2674 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) { 2675 EVT PtrType = LN0->getOperand(1).getValueType(); 2676 2677 unsigned Alignment = LN0->getAlignment(); 2678 SDValue NewPtr = LN0->getBasePtr(); 2679 2680 // For big endian targets, we need to add an offset to the pointer 2681 // to load the correct bytes. For little endian systems, we merely 2682 // need to read fewer bytes from the same pointer. 2683 if (TLI.isBigEndian()) { 2684 unsigned LVTStoreBytes = LoadedVT.getStoreSize(); 2685 unsigned EVTStoreBytes = ExtVT.getStoreSize(); 2686 unsigned PtrOff = LVTStoreBytes - EVTStoreBytes; 2687 NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(), PtrType, 2688 NewPtr, DAG.getConstant(PtrOff, PtrType)); 2689 Alignment = MinAlign(Alignment, PtrOff); 2690 } 2691 2692 AddToWorkList(NewPtr.getNode()); 2693 2694 EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT; 2695 SDValue Load = 2696 DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), LoadResultTy, 2697 LN0->getChain(), NewPtr, 2698 LN0->getPointerInfo(), 2699 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(), 2700 Alignment); 2701 AddToWorkList(N); 2702 CombineTo(LN0, Load, Load.getValue(1)); 2703 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2704 } 2705 } 2706 } 2707 } 2708 2709 return SDValue(); 2710} 2711 2712/// MatchBSwapHWord - Match (a >> 8) | (a << 8) as (bswap a) >> 16 2713/// 2714SDValue DAGCombiner::MatchBSwapHWordLow(SDNode *N, SDValue N0, SDValue N1, 2715 bool DemandHighBits) { 2716 if (!LegalOperations) 2717 return SDValue(); 2718 2719 EVT VT = N->getValueType(0); 2720 if (VT != MVT::i64 && VT != MVT::i32 && VT != MVT::i16) 2721 return SDValue(); 2722 if (!TLI.isOperationLegal(ISD::BSWAP, VT)) 2723 return SDValue(); 2724 2725 // Recognize (and (shl a, 8), 0xff), (and (srl a, 8), 0xff00) 2726 bool LookPassAnd0 = false; 2727 bool LookPassAnd1 = false; 2728 if (N0.getOpcode() == ISD::AND && N0.getOperand(0).getOpcode() == ISD::SRL) 2729 std::swap(N0, N1); 2730 if (N1.getOpcode() == ISD::AND && N1.getOperand(0).getOpcode() == ISD::SHL) 2731 std::swap(N0, N1); 2732 if (N0.getOpcode() == ISD::AND) { 2733 if (!N0.getNode()->hasOneUse()) 2734 return SDValue(); 2735 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2736 if (!N01C || N01C->getZExtValue() != 0xFF00) 2737 return SDValue(); 2738 N0 = N0.getOperand(0); 2739 LookPassAnd0 = true; 2740 } 2741 2742 if (N1.getOpcode() == ISD::AND) { 2743 if (!N1.getNode()->hasOneUse()) 2744 return SDValue(); 2745 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1)); 2746 if (!N11C || N11C->getZExtValue() != 0xFF) 2747 return SDValue(); 2748 N1 = N1.getOperand(0); 2749 LookPassAnd1 = true; 2750 } 2751 2752 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL) 2753 std::swap(N0, N1); 2754 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL) 2755 return SDValue(); 2756 if (!N0.getNode()->hasOneUse() || 2757 !N1.getNode()->hasOneUse()) 2758 return SDValue(); 2759 2760 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2761 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1)); 2762 if (!N01C || !N11C) 2763 return SDValue(); 2764 if (N01C->getZExtValue() != 8 || N11C->getZExtValue() != 8) 2765 return SDValue(); 2766 2767 // Look for (shl (and a, 0xff), 8), (srl (and a, 0xff00), 8) 2768 SDValue N00 = N0->getOperand(0); 2769 if (!LookPassAnd0 && N00.getOpcode() == ISD::AND) { 2770 if (!N00.getNode()->hasOneUse()) 2771 return SDValue(); 2772 ConstantSDNode *N001C = dyn_cast<ConstantSDNode>(N00.getOperand(1)); 2773 if (!N001C || N001C->getZExtValue() != 0xFF) 2774 return SDValue(); 2775 N00 = N00.getOperand(0); 2776 LookPassAnd0 = true; 2777 } 2778 2779 SDValue N10 = N1->getOperand(0); 2780 if (!LookPassAnd1 && N10.getOpcode() == ISD::AND) { 2781 if (!N10.getNode()->hasOneUse()) 2782 return SDValue(); 2783 ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N10.getOperand(1)); 2784 if (!N101C || N101C->getZExtValue() != 0xFF00) 2785 return SDValue(); 2786 N10 = N10.getOperand(0); 2787 LookPassAnd1 = true; 2788 } 2789 2790 if (N00 != N10) 2791 return SDValue(); 2792 2793 // Make sure everything beyond the low halfword is zero since the SRL 16 2794 // will clear the top bits. 2795 unsigned OpSizeInBits = VT.getSizeInBits(); 2796 if (DemandHighBits && OpSizeInBits > 16 && 2797 (!LookPassAnd0 || !LookPassAnd1) && 2798 !DAG.MaskedValueIsZero(N10, APInt::getHighBitsSet(OpSizeInBits, 16))) 2799 return SDValue(); 2800 2801 SDValue Res = DAG.getNode(ISD::BSWAP, N->getDebugLoc(), VT, N00); 2802 if (OpSizeInBits > 16) 2803 Res = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, Res, 2804 DAG.getConstant(OpSizeInBits-16, getShiftAmountTy(VT))); 2805 return Res; 2806} 2807 2808/// isBSwapHWordElement - Return true if the specified node is an element 2809/// that makes up a 32-bit packed halfword byteswap. i.e. 2810/// ((x&0xff)<<8)|((x&0xff00)>>8)|((x&0x00ff0000)<<8)|((x&0xff000000)>>8) 2811static bool isBSwapHWordElement(SDValue N, SmallVector<SDNode*,4> &Parts) { 2812 if (!N.getNode()->hasOneUse()) 2813 return false; 2814 2815 unsigned Opc = N.getOpcode(); 2816 if (Opc != ISD::AND && Opc != ISD::SHL && Opc != ISD::SRL) 2817 return false; 2818 2819 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N.getOperand(1)); 2820 if (!N1C) 2821 return false; 2822 2823 unsigned Num; 2824 switch (N1C->getZExtValue()) { 2825 default: 2826 return false; 2827 case 0xFF: Num = 0; break; 2828 case 0xFF00: Num = 1; break; 2829 case 0xFF0000: Num = 2; break; 2830 case 0xFF000000: Num = 3; break; 2831 } 2832 2833 // Look for (x & 0xff) << 8 as well as ((x << 8) & 0xff00). 2834 SDValue N0 = N.getOperand(0); 2835 if (Opc == ISD::AND) { 2836 if (Num == 0 || Num == 2) { 2837 // (x >> 8) & 0xff 2838 // (x >> 8) & 0xff0000 2839 if (N0.getOpcode() != ISD::SRL) 2840 return false; 2841 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2842 if (!C || C->getZExtValue() != 8) 2843 return false; 2844 } else { 2845 // (x << 8) & 0xff00 2846 // (x << 8) & 0xff000000 2847 if (N0.getOpcode() != ISD::SHL) 2848 return false; 2849 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2850 if (!C || C->getZExtValue() != 8) 2851 return false; 2852 } 2853 } else if (Opc == ISD::SHL) { 2854 // (x & 0xff) << 8 2855 // (x & 0xff0000) << 8 2856 if (Num != 0 && Num != 2) 2857 return false; 2858 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N.getOperand(1)); 2859 if (!C || C->getZExtValue() != 8) 2860 return false; 2861 } else { // Opc == ISD::SRL 2862 // (x & 0xff00) >> 8 2863 // (x & 0xff000000) >> 8 2864 if (Num != 1 && Num != 3) 2865 return false; 2866 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N.getOperand(1)); 2867 if (!C || C->getZExtValue() != 8) 2868 return false; 2869 } 2870 2871 if (Parts[Num]) 2872 return false; 2873 2874 Parts[Num] = N0.getOperand(0).getNode(); 2875 return true; 2876} 2877 2878/// MatchBSwapHWord - Match a 32-bit packed halfword bswap. That is 2879/// ((x&0xff)<<8)|((x&0xff00)>>8)|((x&0x00ff0000)<<8)|((x&0xff000000)>>8) 2880/// => (rotl (bswap x), 16) 2881SDValue DAGCombiner::MatchBSwapHWord(SDNode *N, SDValue N0, SDValue N1) { 2882 if (!LegalOperations) 2883 return SDValue(); 2884 2885 EVT VT = N->getValueType(0); 2886 if (VT != MVT::i32) 2887 return SDValue(); 2888 if (!TLI.isOperationLegal(ISD::BSWAP, VT)) 2889 return SDValue(); 2890 2891 SmallVector<SDNode*,4> Parts(4, (SDNode*)0); 2892 // Look for either 2893 // (or (or (and), (and)), (or (and), (and))) 2894 // (or (or (or (and), (and)), (and)), (and)) 2895 if (N0.getOpcode() != ISD::OR) 2896 return SDValue(); 2897 SDValue N00 = N0.getOperand(0); 2898 SDValue N01 = N0.getOperand(1); 2899 2900 if (N1.getOpcode() == ISD::OR) { 2901 // (or (or (and), (and)), (or (and), (and))) 2902 SDValue N000 = N00.getOperand(0); 2903 if (!isBSwapHWordElement(N000, Parts)) 2904 return SDValue(); 2905 2906 SDValue N001 = N00.getOperand(1); 2907 if (!isBSwapHWordElement(N001, Parts)) 2908 return SDValue(); 2909 SDValue N010 = N01.getOperand(0); 2910 if (!isBSwapHWordElement(N010, Parts)) 2911 return SDValue(); 2912 SDValue N011 = N01.getOperand(1); 2913 if (!isBSwapHWordElement(N011, Parts)) 2914 return SDValue(); 2915 } else { 2916 // (or (or (or (and), (and)), (and)), (and)) 2917 if (!isBSwapHWordElement(N1, Parts)) 2918 return SDValue(); 2919 if (!isBSwapHWordElement(N01, Parts)) 2920 return SDValue(); 2921 if (N00.getOpcode() != ISD::OR) 2922 return SDValue(); 2923 SDValue N000 = N00.getOperand(0); 2924 if (!isBSwapHWordElement(N000, Parts)) 2925 return SDValue(); 2926 SDValue N001 = N00.getOperand(1); 2927 if (!isBSwapHWordElement(N001, Parts)) 2928 return SDValue(); 2929 } 2930 2931 // Make sure the parts are all coming from the same node. 2932 if (Parts[0] != Parts[1] || Parts[0] != Parts[2] || Parts[0] != Parts[3]) 2933 return SDValue(); 2934 2935 SDValue BSwap = DAG.getNode(ISD::BSWAP, N->getDebugLoc(), VT, 2936 SDValue(Parts[0],0)); 2937 2938 // Result of the bswap should be rotated by 16. If it's not legal, than 2939 // do (x << 16) | (x >> 16). 2940 SDValue ShAmt = DAG.getConstant(16, getShiftAmountTy(VT)); 2941 if (TLI.isOperationLegalOrCustom(ISD::ROTL, VT)) 2942 return DAG.getNode(ISD::ROTL, N->getDebugLoc(), VT, BSwap, ShAmt); 2943 else if (TLI.isOperationLegalOrCustom(ISD::ROTR, VT)) 2944 return DAG.getNode(ISD::ROTR, N->getDebugLoc(), VT, BSwap, ShAmt); 2945 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, 2946 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, BSwap, ShAmt), 2947 DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, BSwap, ShAmt)); 2948} 2949 2950SDValue DAGCombiner::visitOR(SDNode *N) { 2951 SDValue N0 = N->getOperand(0); 2952 SDValue N1 = N->getOperand(1); 2953 SDValue LL, LR, RL, RR, CC0, CC1; 2954 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2955 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2956 EVT VT = N1.getValueType(); 2957 2958 // fold vector ops 2959 if (VT.isVector()) { 2960 SDValue FoldedVOp = SimplifyVBinOp(N); 2961 if (FoldedVOp.getNode()) return FoldedVOp; 2962 } 2963 2964 // fold (or x, undef) -> -1 2965 if (!LegalOperations && 2966 (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)) { 2967 EVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT; 2968 return DAG.getConstant(APInt::getAllOnesValue(EltVT.getSizeInBits()), VT); 2969 } 2970 // fold (or c1, c2) -> c1|c2 2971 if (N0C && N1C) 2972 return DAG.FoldConstantArithmetic(ISD::OR, VT, N0C, N1C); 2973 // canonicalize constant to RHS 2974 if (N0C && !N1C) 2975 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N1, N0); 2976 // fold (or x, 0) -> x 2977 if (N1C && N1C->isNullValue()) 2978 return N0; 2979 // fold (or x, -1) -> -1 2980 if (N1C && N1C->isAllOnesValue()) 2981 return N1; 2982 // fold (or x, c) -> c iff (x & ~c) == 0 2983 if (N1C && DAG.MaskedValueIsZero(N0, ~N1C->getAPIntValue())) 2984 return N1; 2985 2986 // Recognize halfword bswaps as (bswap + rotl 16) or (bswap + shl 16) 2987 SDValue BSwap = MatchBSwapHWord(N, N0, N1); 2988 if (BSwap.getNode() != 0) 2989 return BSwap; 2990 BSwap = MatchBSwapHWordLow(N, N0, N1); 2991 if (BSwap.getNode() != 0) 2992 return BSwap; 2993 2994 // reassociate or 2995 SDValue ROR = ReassociateOps(ISD::OR, N->getDebugLoc(), N0, N1); 2996 if (ROR.getNode() != 0) 2997 return ROR; 2998 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2) 2999 // iff (c1 & c2) == 0. 3000 if (N1C && N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() && 3001 isa<ConstantSDNode>(N0.getOperand(1))) { 3002 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1)); 3003 if ((C1->getAPIntValue() & N1C->getAPIntValue()) != 0) 3004 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 3005 DAG.getNode(ISD::OR, N0.getDebugLoc(), VT, 3006 N0.getOperand(0), N1), 3007 DAG.FoldConstantArithmetic(ISD::OR, VT, N1C, C1)); 3008 } 3009 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y)) 3010 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 3011 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 3012 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 3013 3014 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 3015 LL.getValueType().isInteger()) { 3016 // fold (or (setne X, 0), (setne Y, 0)) -> (setne (or X, Y), 0) 3017 // fold (or (setlt X, 0), (setlt Y, 0)) -> (setne (or X, Y), 0) 3018 if (cast<ConstantSDNode>(LR)->isNullValue() && 3019 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) { 3020 SDValue ORNode = DAG.getNode(ISD::OR, LR.getDebugLoc(), 3021 LR.getValueType(), LL, RL); 3022 AddToWorkList(ORNode.getNode()); 3023 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 3024 } 3025 // fold (or (setne X, -1), (setne Y, -1)) -> (setne (and X, Y), -1) 3026 // fold (or (setgt X, -1), (setgt Y -1)) -> (setgt (and X, Y), -1) 3027 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && 3028 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) { 3029 SDValue ANDNode = DAG.getNode(ISD::AND, LR.getDebugLoc(), 3030 LR.getValueType(), LL, RL); 3031 AddToWorkList(ANDNode.getNode()); 3032 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1); 3033 } 3034 } 3035 // canonicalize equivalent to ll == rl 3036 if (LL == RR && LR == RL) { 3037 Op1 = ISD::getSetCCSwappedOperands(Op1); 3038 std::swap(RL, RR); 3039 } 3040 if (LL == RL && LR == RR) { 3041 bool isInteger = LL.getValueType().isInteger(); 3042 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger); 3043 if (Result != ISD::SETCC_INVALID && 3044 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType()))) 3045 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(), 3046 LL, LR, Result); 3047 } 3048 } 3049 3050 // Simplify: (or (op x...), (op y...)) -> (op (or x, y)) 3051 if (N0.getOpcode() == N1.getOpcode()) { 3052 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 3053 if (Tmp.getNode()) return Tmp; 3054 } 3055 3056 // (or (and X, C1), (and Y, C2)) -> (and (or X, Y), C3) if possible. 3057 if (N0.getOpcode() == ISD::AND && 3058 N1.getOpcode() == ISD::AND && 3059 N0.getOperand(1).getOpcode() == ISD::Constant && 3060 N1.getOperand(1).getOpcode() == ISD::Constant && 3061 // Don't increase # computations. 3062 (N0.getNode()->hasOneUse() || N1.getNode()->hasOneUse())) { 3063 // We can only do this xform if we know that bits from X that are set in C2 3064 // but not in C1 are already zero. Likewise for Y. 3065 const APInt &LHSMask = 3066 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 3067 const APInt &RHSMask = 3068 cast<ConstantSDNode>(N1.getOperand(1))->getAPIntValue(); 3069 3070 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) && 3071 DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) { 3072 SDValue X = DAG.getNode(ISD::OR, N0.getDebugLoc(), VT, 3073 N0.getOperand(0), N1.getOperand(0)); 3074 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, X, 3075 DAG.getConstant(LHSMask | RHSMask, VT)); 3076 } 3077 } 3078 3079 // See if this is some rotate idiom. 3080 if (SDNode *Rot = MatchRotate(N0, N1, N->getDebugLoc())) 3081 return SDValue(Rot, 0); 3082 3083 // Simplify the operands using demanded-bits information. 3084 if (!VT.isVector() && 3085 SimplifyDemandedBits(SDValue(N, 0))) 3086 return SDValue(N, 0); 3087 3088 return SDValue(); 3089} 3090 3091/// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present. 3092static bool MatchRotateHalf(SDValue Op, SDValue &Shift, SDValue &Mask) { 3093 if (Op.getOpcode() == ISD::AND) { 3094 if (isa<ConstantSDNode>(Op.getOperand(1))) { 3095 Mask = Op.getOperand(1); 3096 Op = Op.getOperand(0); 3097 } else { 3098 return false; 3099 } 3100 } 3101 3102 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) { 3103 Shift = Op; 3104 return true; 3105 } 3106 3107 return false; 3108} 3109 3110// MatchRotate - Handle an 'or' of two operands. If this is one of the many 3111// idioms for rotate, and if the target supports rotation instructions, generate 3112// a rot[lr]. 3113SDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL) { 3114 // Must be a legal type. Expanded 'n promoted things won't work with rotates. 3115 EVT VT = LHS.getValueType(); 3116 if (!TLI.isTypeLegal(VT)) return 0; 3117 3118 // The target must have at least one rotate flavor. 3119 bool HasROTL = TLI.isOperationLegalOrCustom(ISD::ROTL, VT); 3120 bool HasROTR = TLI.isOperationLegalOrCustom(ISD::ROTR, VT); 3121 if (!HasROTL && !HasROTR) return 0; 3122 3123 // Match "(X shl/srl V1) & V2" where V2 may not be present. 3124 SDValue LHSShift; // The shift. 3125 SDValue LHSMask; // AND value if any. 3126 if (!MatchRotateHalf(LHS, LHSShift, LHSMask)) 3127 return 0; // Not part of a rotate. 3128 3129 SDValue RHSShift; // The shift. 3130 SDValue RHSMask; // AND value if any. 3131 if (!MatchRotateHalf(RHS, RHSShift, RHSMask)) 3132 return 0; // Not part of a rotate. 3133 3134 if (LHSShift.getOperand(0) != RHSShift.getOperand(0)) 3135 return 0; // Not shifting the same value. 3136 3137 if (LHSShift.getOpcode() == RHSShift.getOpcode()) 3138 return 0; // Shifts must disagree. 3139 3140 // Canonicalize shl to left side in a shl/srl pair. 3141 if (RHSShift.getOpcode() == ISD::SHL) { 3142 std::swap(LHS, RHS); 3143 std::swap(LHSShift, RHSShift); 3144 std::swap(LHSMask , RHSMask ); 3145 } 3146 3147 unsigned OpSizeInBits = VT.getSizeInBits(); 3148 SDValue LHSShiftArg = LHSShift.getOperand(0); 3149 SDValue LHSShiftAmt = LHSShift.getOperand(1); 3150 SDValue RHSShiftAmt = RHSShift.getOperand(1); 3151 3152 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1) 3153 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2) 3154 if (LHSShiftAmt.getOpcode() == ISD::Constant && 3155 RHSShiftAmt.getOpcode() == ISD::Constant) { 3156 uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getZExtValue(); 3157 uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getZExtValue(); 3158 if ((LShVal + RShVal) != OpSizeInBits) 3159 return 0; 3160 3161 SDValue Rot; 3162 if (HasROTL) 3163 Rot = DAG.getNode(ISD::ROTL, DL, VT, LHSShiftArg, LHSShiftAmt); 3164 else 3165 Rot = DAG.getNode(ISD::ROTR, DL, VT, LHSShiftArg, RHSShiftAmt); 3166 3167 // If there is an AND of either shifted operand, apply it to the result. 3168 if (LHSMask.getNode() || RHSMask.getNode()) { 3169 APInt Mask = APInt::getAllOnesValue(OpSizeInBits); 3170 3171 if (LHSMask.getNode()) { 3172 APInt RHSBits = APInt::getLowBitsSet(OpSizeInBits, LShVal); 3173 Mask &= cast<ConstantSDNode>(LHSMask)->getAPIntValue() | RHSBits; 3174 } 3175 if (RHSMask.getNode()) { 3176 APInt LHSBits = APInt::getHighBitsSet(OpSizeInBits, RShVal); 3177 Mask &= cast<ConstantSDNode>(RHSMask)->getAPIntValue() | LHSBits; 3178 } 3179 3180 Rot = DAG.getNode(ISD::AND, DL, VT, Rot, DAG.getConstant(Mask, VT)); 3181 } 3182 3183 return Rot.getNode(); 3184 } 3185 3186 // If there is a mask here, and we have a variable shift, we can't be sure 3187 // that we're masking out the right stuff. 3188 if (LHSMask.getNode() || RHSMask.getNode()) 3189 return 0; 3190 3191 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y) 3192 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y)) 3193 if (RHSShiftAmt.getOpcode() == ISD::SUB && 3194 LHSShiftAmt == RHSShiftAmt.getOperand(1)) { 3195 if (ConstantSDNode *SUBC = 3196 dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) { 3197 if (SUBC->getAPIntValue() == OpSizeInBits) { 3198 if (HasROTL) 3199 return DAG.getNode(ISD::ROTL, DL, VT, 3200 LHSShiftArg, LHSShiftAmt).getNode(); 3201 else 3202 return DAG.getNode(ISD::ROTR, DL, VT, 3203 LHSShiftArg, RHSShiftAmt).getNode(); 3204 } 3205 } 3206 } 3207 3208 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y) 3209 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y)) 3210 if (LHSShiftAmt.getOpcode() == ISD::SUB && 3211 RHSShiftAmt == LHSShiftAmt.getOperand(1)) { 3212 if (ConstantSDNode *SUBC = 3213 dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) { 3214 if (SUBC->getAPIntValue() == OpSizeInBits) { 3215 if (HasROTR) 3216 return DAG.getNode(ISD::ROTR, DL, VT, 3217 LHSShiftArg, RHSShiftAmt).getNode(); 3218 else 3219 return DAG.getNode(ISD::ROTL, DL, VT, 3220 LHSShiftArg, LHSShiftAmt).getNode(); 3221 } 3222 } 3223 } 3224 3225 // Look for sign/zext/any-extended or truncate cases: 3226 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 3227 || LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 3228 || LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND 3229 || LHSShiftAmt.getOpcode() == ISD::TRUNCATE) && 3230 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 3231 || RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 3232 || RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND 3233 || RHSShiftAmt.getOpcode() == ISD::TRUNCATE)) { 3234 SDValue LExtOp0 = LHSShiftAmt.getOperand(0); 3235 SDValue RExtOp0 = RHSShiftAmt.getOperand(0); 3236 if (RExtOp0.getOpcode() == ISD::SUB && 3237 RExtOp0.getOperand(1) == LExtOp0) { 3238 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 3239 // (rotl x, y) 3240 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 3241 // (rotr x, (sub 32, y)) 3242 if (ConstantSDNode *SUBC = 3243 dyn_cast<ConstantSDNode>(RExtOp0.getOperand(0))) { 3244 if (SUBC->getAPIntValue() == OpSizeInBits) { 3245 return DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT, 3246 LHSShiftArg, 3247 HasROTL ? LHSShiftAmt : RHSShiftAmt).getNode(); 3248 } 3249 } 3250 } else if (LExtOp0.getOpcode() == ISD::SUB && 3251 RExtOp0 == LExtOp0.getOperand(1)) { 3252 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) -> 3253 // (rotr x, y) 3254 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) -> 3255 // (rotl x, (sub 32, y)) 3256 if (ConstantSDNode *SUBC = 3257 dyn_cast<ConstantSDNode>(LExtOp0.getOperand(0))) { 3258 if (SUBC->getAPIntValue() == OpSizeInBits) { 3259 return DAG.getNode(HasROTR ? ISD::ROTR : ISD::ROTL, DL, VT, 3260 LHSShiftArg, 3261 HasROTR ? RHSShiftAmt : LHSShiftAmt).getNode(); 3262 } 3263 } 3264 } 3265 } 3266 3267 return 0; 3268} 3269 3270SDValue DAGCombiner::visitXOR(SDNode *N) { 3271 SDValue N0 = N->getOperand(0); 3272 SDValue N1 = N->getOperand(1); 3273 SDValue LHS, RHS, CC; 3274 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3275 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3276 EVT VT = N0.getValueType(); 3277 3278 // fold vector ops 3279 if (VT.isVector()) { 3280 SDValue FoldedVOp = SimplifyVBinOp(N); 3281 if (FoldedVOp.getNode()) return FoldedVOp; 3282 } 3283 3284 // fold (xor undef, undef) -> 0. This is a common idiom (misuse). 3285 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF) 3286 return DAG.getConstant(0, VT); 3287 // fold (xor x, undef) -> undef 3288 if (N0.getOpcode() == ISD::UNDEF) 3289 return N0; 3290 if (N1.getOpcode() == ISD::UNDEF) 3291 return N1; 3292 // fold (xor c1, c2) -> c1^c2 3293 if (N0C && N1C) 3294 return DAG.FoldConstantArithmetic(ISD::XOR, VT, N0C, N1C); 3295 // canonicalize constant to RHS 3296 if (N0C && !N1C) 3297 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0); 3298 // fold (xor x, 0) -> x 3299 if (N1C && N1C->isNullValue()) 3300 return N0; 3301 // reassociate xor 3302 SDValue RXOR = ReassociateOps(ISD::XOR, N->getDebugLoc(), N0, N1); 3303 if (RXOR.getNode() != 0) 3304 return RXOR; 3305 3306 // fold !(x cc y) -> (x !cc y) 3307 if (N1C && N1C->getAPIntValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) { 3308 bool isInt = LHS.getValueType().isInteger(); 3309 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(), 3310 isInt); 3311 3312 if (!LegalOperations || TLI.isCondCodeLegal(NotCC, LHS.getValueType())) { 3313 switch (N0.getOpcode()) { 3314 default: 3315 llvm_unreachable("Unhandled SetCC Equivalent!"); 3316 case ISD::SETCC: 3317 return DAG.getSetCC(N->getDebugLoc(), VT, LHS, RHS, NotCC); 3318 case ISD::SELECT_CC: 3319 return DAG.getSelectCC(N->getDebugLoc(), LHS, RHS, N0.getOperand(2), 3320 N0.getOperand(3), NotCC); 3321 } 3322 } 3323 } 3324 3325 // fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y))) 3326 if (N1C && N1C->getAPIntValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND && 3327 N0.getNode()->hasOneUse() && 3328 isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){ 3329 SDValue V = N0.getOperand(0); 3330 V = DAG.getNode(ISD::XOR, N0.getDebugLoc(), V.getValueType(), V, 3331 DAG.getConstant(1, V.getValueType())); 3332 AddToWorkList(V.getNode()); 3333 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, V); 3334 } 3335 3336 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are setcc 3337 if (N1C && N1C->getAPIntValue() == 1 && VT == MVT::i1 && 3338 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 3339 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1); 3340 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) { 3341 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 3342 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS 3343 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS 3344 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode()); 3345 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS); 3346 } 3347 } 3348 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are constants 3349 if (N1C && N1C->isAllOnesValue() && 3350 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 3351 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1); 3352 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) { 3353 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 3354 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS 3355 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS 3356 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode()); 3357 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS); 3358 } 3359 } 3360 // fold (xor (xor x, c1), c2) -> (xor x, (xor c1, c2)) 3361 if (N1C && N0.getOpcode() == ISD::XOR) { 3362 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0)); 3363 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 3364 if (N00C) 3365 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(1), 3366 DAG.getConstant(N1C->getAPIntValue() ^ 3367 N00C->getAPIntValue(), VT)); 3368 if (N01C) 3369 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(0), 3370 DAG.getConstant(N1C->getAPIntValue() ^ 3371 N01C->getAPIntValue(), VT)); 3372 } 3373 // fold (xor x, x) -> 0 3374 if (N0 == N1) 3375 return tryFoldToZero(N->getDebugLoc(), TLI, VT, DAG, LegalOperations); 3376 3377 // Simplify: xor (op x...), (op y...) -> (op (xor x, y)) 3378 if (N0.getOpcode() == N1.getOpcode()) { 3379 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 3380 if (Tmp.getNode()) return Tmp; 3381 } 3382 3383 // Simplify the expression using non-local knowledge. 3384 if (!VT.isVector() && 3385 SimplifyDemandedBits(SDValue(N, 0))) 3386 return SDValue(N, 0); 3387 3388 return SDValue(); 3389} 3390 3391/// visitShiftByConstant - Handle transforms common to the three shifts, when 3392/// the shift amount is a constant. 3393SDValue DAGCombiner::visitShiftByConstant(SDNode *N, unsigned Amt) { 3394 SDNode *LHS = N->getOperand(0).getNode(); 3395 if (!LHS->hasOneUse()) return SDValue(); 3396 3397 // We want to pull some binops through shifts, so that we have (and (shift)) 3398 // instead of (shift (and)), likewise for add, or, xor, etc. This sort of 3399 // thing happens with address calculations, so it's important to canonicalize 3400 // it. 3401 bool HighBitSet = false; // Can we transform this if the high bit is set? 3402 3403 switch (LHS->getOpcode()) { 3404 default: return SDValue(); 3405 case ISD::OR: 3406 case ISD::XOR: 3407 HighBitSet = false; // We can only transform sra if the high bit is clear. 3408 break; 3409 case ISD::AND: 3410 HighBitSet = true; // We can only transform sra if the high bit is set. 3411 break; 3412 case ISD::ADD: 3413 if (N->getOpcode() != ISD::SHL) 3414 return SDValue(); // only shl(add) not sr[al](add). 3415 HighBitSet = false; // We can only transform sra if the high bit is clear. 3416 break; 3417 } 3418 3419 // We require the RHS of the binop to be a constant as well. 3420 ConstantSDNode *BinOpCst = dyn_cast<ConstantSDNode>(LHS->getOperand(1)); 3421 if (!BinOpCst) return SDValue(); 3422 3423 // FIXME: disable this unless the input to the binop is a shift by a constant. 3424 // If it is not a shift, it pessimizes some common cases like: 3425 // 3426 // void foo(int *X, int i) { X[i & 1235] = 1; } 3427 // int bar(int *X, int i) { return X[i & 255]; } 3428 SDNode *BinOpLHSVal = LHS->getOperand(0).getNode(); 3429 if ((BinOpLHSVal->getOpcode() != ISD::SHL && 3430 BinOpLHSVal->getOpcode() != ISD::SRA && 3431 BinOpLHSVal->getOpcode() != ISD::SRL) || 3432 !isa<ConstantSDNode>(BinOpLHSVal->getOperand(1))) 3433 return SDValue(); 3434 3435 EVT VT = N->getValueType(0); 3436 3437 // If this is a signed shift right, and the high bit is modified by the 3438 // logical operation, do not perform the transformation. The highBitSet 3439 // boolean indicates the value of the high bit of the constant which would 3440 // cause it to be modified for this operation. 3441 if (N->getOpcode() == ISD::SRA) { 3442 bool BinOpRHSSignSet = BinOpCst->getAPIntValue().isNegative(); 3443 if (BinOpRHSSignSet != HighBitSet) 3444 return SDValue(); 3445 } 3446 3447 // Fold the constants, shifting the binop RHS by the shift amount. 3448 SDValue NewRHS = DAG.getNode(N->getOpcode(), LHS->getOperand(1).getDebugLoc(), 3449 N->getValueType(0), 3450 LHS->getOperand(1), N->getOperand(1)); 3451 3452 // Create the new shift. 3453 SDValue NewShift = DAG.getNode(N->getOpcode(), 3454 LHS->getOperand(0).getDebugLoc(), 3455 VT, LHS->getOperand(0), N->getOperand(1)); 3456 3457 // Create the new binop. 3458 return DAG.getNode(LHS->getOpcode(), N->getDebugLoc(), VT, NewShift, NewRHS); 3459} 3460 3461SDValue DAGCombiner::visitSHL(SDNode *N) { 3462 SDValue N0 = N->getOperand(0); 3463 SDValue N1 = N->getOperand(1); 3464 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3465 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3466 EVT VT = N0.getValueType(); 3467 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits(); 3468 3469 // fold (shl c1, c2) -> c1<<c2 3470 if (N0C && N1C) 3471 return DAG.FoldConstantArithmetic(ISD::SHL, VT, N0C, N1C); 3472 // fold (shl 0, x) -> 0 3473 if (N0C && N0C->isNullValue()) 3474 return N0; 3475 // fold (shl x, c >= size(x)) -> undef 3476 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 3477 return DAG.getUNDEF(VT); 3478 // fold (shl x, 0) -> x 3479 if (N1C && N1C->isNullValue()) 3480 return N0; 3481 // fold (shl undef, x) -> 0 3482 if (N0.getOpcode() == ISD::UNDEF) 3483 return DAG.getConstant(0, VT); 3484 // if (shl x, c) is known to be zero, return 0 3485 if (DAG.MaskedValueIsZero(SDValue(N, 0), 3486 APInt::getAllOnesValue(OpSizeInBits))) 3487 return DAG.getConstant(0, VT); 3488 // fold (shl x, (trunc (and y, c))) -> (shl x, (and (trunc y), (trunc c))). 3489 if (N1.getOpcode() == ISD::TRUNCATE && 3490 N1.getOperand(0).getOpcode() == ISD::AND && 3491 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 3492 SDValue N101 = N1.getOperand(0).getOperand(1); 3493 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 3494 EVT TruncVT = N1.getValueType(); 3495 SDValue N100 = N1.getOperand(0).getOperand(0); 3496 APInt TruncC = N101C->getAPIntValue(); 3497 TruncC = TruncC.trunc(TruncVT.getSizeInBits()); 3498 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 3499 DAG.getNode(ISD::AND, N->getDebugLoc(), TruncVT, 3500 DAG.getNode(ISD::TRUNCATE, 3501 N->getDebugLoc(), 3502 TruncVT, N100), 3503 DAG.getConstant(TruncC, TruncVT))); 3504 } 3505 } 3506 3507 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 3508 return SDValue(N, 0); 3509 3510 // fold (shl (shl x, c1), c2) -> 0 or (shl x, (add c1, c2)) 3511 if (N1C && N0.getOpcode() == ISD::SHL && 3512 N0.getOperand(1).getOpcode() == ISD::Constant) { 3513 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 3514 uint64_t c2 = N1C->getZExtValue(); 3515 if (c1 + c2 >= OpSizeInBits) 3516 return DAG.getConstant(0, VT); 3517 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0.getOperand(0), 3518 DAG.getConstant(c1 + c2, N1.getValueType())); 3519 } 3520 3521 // fold (shl (ext (shl x, c1)), c2) -> (ext (shl x, (add c1, c2))) 3522 // For this to be valid, the second form must not preserve any of the bits 3523 // that are shifted out by the inner shift in the first form. This means 3524 // the outer shift size must be >= the number of bits added by the ext. 3525 // As a corollary, we don't care what kind of ext it is. 3526 if (N1C && (N0.getOpcode() == ISD::ZERO_EXTEND || 3527 N0.getOpcode() == ISD::ANY_EXTEND || 3528 N0.getOpcode() == ISD::SIGN_EXTEND) && 3529 N0.getOperand(0).getOpcode() == ISD::SHL && 3530 isa<ConstantSDNode>(N0.getOperand(0)->getOperand(1))) { 3531 uint64_t c1 = 3532 cast<ConstantSDNode>(N0.getOperand(0)->getOperand(1))->getZExtValue(); 3533 uint64_t c2 = N1C->getZExtValue(); 3534 EVT InnerShiftVT = N0.getOperand(0).getValueType(); 3535 uint64_t InnerShiftSize = InnerShiftVT.getScalarType().getSizeInBits(); 3536 if (c2 >= OpSizeInBits - InnerShiftSize) { 3537 if (c1 + c2 >= OpSizeInBits) 3538 return DAG.getConstant(0, VT); 3539 return DAG.getNode(ISD::SHL, N0->getDebugLoc(), VT, 3540 DAG.getNode(N0.getOpcode(), N0->getDebugLoc(), VT, 3541 N0.getOperand(0)->getOperand(0)), 3542 DAG.getConstant(c1 + c2, N1.getValueType())); 3543 } 3544 } 3545 3546 // fold (shl (srl x, c1), c2) -> (and (shl x, (sub c2, c1), MASK) or 3547 // (and (srl x, (sub c1, c2), MASK) 3548 // Only fold this if the inner shift has no other uses -- if it does, folding 3549 // this will increase the total number of instructions. 3550 if (N1C && N0.getOpcode() == ISD::SRL && N0.hasOneUse() && 3551 N0.getOperand(1).getOpcode() == ISD::Constant) { 3552 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 3553 if (c1 < VT.getSizeInBits()) { 3554 uint64_t c2 = N1C->getZExtValue(); 3555 APInt Mask = APInt::getHighBitsSet(VT.getSizeInBits(), 3556 VT.getSizeInBits() - c1); 3557 SDValue Shift; 3558 if (c2 > c1) { 3559 Mask = Mask.shl(c2-c1); 3560 Shift = DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0.getOperand(0), 3561 DAG.getConstant(c2-c1, N1.getValueType())); 3562 } else { 3563 Mask = Mask.lshr(c1-c2); 3564 Shift = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), 3565 DAG.getConstant(c1-c2, N1.getValueType())); 3566 } 3567 return DAG.getNode(ISD::AND, N0.getDebugLoc(), VT, Shift, 3568 DAG.getConstant(Mask, VT)); 3569 } 3570 } 3571 // fold (shl (sra x, c1), c1) -> (and x, (shl -1, c1)) 3572 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) { 3573 SDValue HiBitsMask = 3574 DAG.getConstant(APInt::getHighBitsSet(VT.getSizeInBits(), 3575 VT.getSizeInBits() - 3576 N1C->getZExtValue()), 3577 VT); 3578 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0), 3579 HiBitsMask); 3580 } 3581 3582 if (N1C) { 3583 SDValue NewSHL = visitShiftByConstant(N, N1C->getZExtValue()); 3584 if (NewSHL.getNode()) 3585 return NewSHL; 3586 } 3587 3588 return SDValue(); 3589} 3590 3591SDValue DAGCombiner::visitSRA(SDNode *N) { 3592 SDValue N0 = N->getOperand(0); 3593 SDValue N1 = N->getOperand(1); 3594 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3595 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3596 EVT VT = N0.getValueType(); 3597 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits(); 3598 3599 // fold (sra c1, c2) -> (sra c1, c2) 3600 if (N0C && N1C) 3601 return DAG.FoldConstantArithmetic(ISD::SRA, VT, N0C, N1C); 3602 // fold (sra 0, x) -> 0 3603 if (N0C && N0C->isNullValue()) 3604 return N0; 3605 // fold (sra -1, x) -> -1 3606 if (N0C && N0C->isAllOnesValue()) 3607 return N0; 3608 // fold (sra x, (setge c, size(x))) -> undef 3609 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 3610 return DAG.getUNDEF(VT); 3611 // fold (sra x, 0) -> x 3612 if (N1C && N1C->isNullValue()) 3613 return N0; 3614 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports 3615 // sext_inreg. 3616 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) { 3617 unsigned LowBits = OpSizeInBits - (unsigned)N1C->getZExtValue(); 3618 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), LowBits); 3619 if (VT.isVector()) 3620 ExtVT = EVT::getVectorVT(*DAG.getContext(), 3621 ExtVT, VT.getVectorNumElements()); 3622 if ((!LegalOperations || 3623 TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, ExtVT))) 3624 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, 3625 N0.getOperand(0), DAG.getValueType(ExtVT)); 3626 } 3627 3628 // fold (sra (sra x, c1), c2) -> (sra x, (add c1, c2)) 3629 if (N1C && N0.getOpcode() == ISD::SRA) { 3630 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 3631 unsigned Sum = N1C->getZExtValue() + C1->getZExtValue(); 3632 if (Sum >= OpSizeInBits) Sum = OpSizeInBits-1; 3633 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0.getOperand(0), 3634 DAG.getConstant(Sum, N1C->getValueType(0))); 3635 } 3636 } 3637 3638 // fold (sra (shl X, m), (sub result_size, n)) 3639 // -> (sign_extend (trunc (shl X, (sub (sub result_size, n), m)))) for 3640 // result_size - n != m. 3641 // If truncate is free for the target sext(shl) is likely to result in better 3642 // code. 3643 if (N0.getOpcode() == ISD::SHL) { 3644 // Get the two constanst of the shifts, CN0 = m, CN = n. 3645 const ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 3646 if (N01C && N1C) { 3647 // Determine what the truncate's result bitsize and type would be. 3648 EVT TruncVT = 3649 EVT::getIntegerVT(*DAG.getContext(), 3650 OpSizeInBits - N1C->getZExtValue()); 3651 // Determine the residual right-shift amount. 3652 signed ShiftAmt = N1C->getZExtValue() - N01C->getZExtValue(); 3653 3654 // If the shift is not a no-op (in which case this should be just a sign 3655 // extend already), the truncated to type is legal, sign_extend is legal 3656 // on that type, and the truncate to that type is both legal and free, 3657 // perform the transform. 3658 if ((ShiftAmt > 0) && 3659 TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND, TruncVT) && 3660 TLI.isOperationLegalOrCustom(ISD::TRUNCATE, VT) && 3661 TLI.isTruncateFree(VT, TruncVT)) { 3662 3663 SDValue Amt = DAG.getConstant(ShiftAmt, 3664 getShiftAmountTy(N0.getOperand(0).getValueType())); 3665 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, 3666 N0.getOperand(0), Amt); 3667 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), TruncVT, 3668 Shift); 3669 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), 3670 N->getValueType(0), Trunc); 3671 } 3672 } 3673 } 3674 3675 // fold (sra x, (trunc (and y, c))) -> (sra x, (and (trunc y), (trunc c))). 3676 if (N1.getOpcode() == ISD::TRUNCATE && 3677 N1.getOperand(0).getOpcode() == ISD::AND && 3678 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 3679 SDValue N101 = N1.getOperand(0).getOperand(1); 3680 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 3681 EVT TruncVT = N1.getValueType(); 3682 SDValue N100 = N1.getOperand(0).getOperand(0); 3683 APInt TruncC = N101C->getAPIntValue(); 3684 TruncC = TruncC.trunc(TruncVT.getScalarType().getSizeInBits()); 3685 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0, 3686 DAG.getNode(ISD::AND, N->getDebugLoc(), 3687 TruncVT, 3688 DAG.getNode(ISD::TRUNCATE, 3689 N->getDebugLoc(), 3690 TruncVT, N100), 3691 DAG.getConstant(TruncC, TruncVT))); 3692 } 3693 } 3694 3695 // fold (sra (trunc (sr x, c1)), c2) -> (trunc (sra x, c1+c2)) 3696 // if c1 is equal to the number of bits the trunc removes 3697 if (N0.getOpcode() == ISD::TRUNCATE && 3698 (N0.getOperand(0).getOpcode() == ISD::SRL || 3699 N0.getOperand(0).getOpcode() == ISD::SRA) && 3700 N0.getOperand(0).hasOneUse() && 3701 N0.getOperand(0).getOperand(1).hasOneUse() && 3702 N1C && isa<ConstantSDNode>(N0.getOperand(0).getOperand(1))) { 3703 EVT LargeVT = N0.getOperand(0).getValueType(); 3704 ConstantSDNode *LargeShiftAmt = 3705 cast<ConstantSDNode>(N0.getOperand(0).getOperand(1)); 3706 3707 if (LargeVT.getScalarType().getSizeInBits() - OpSizeInBits == 3708 LargeShiftAmt->getZExtValue()) { 3709 SDValue Amt = 3710 DAG.getConstant(LargeShiftAmt->getZExtValue() + N1C->getZExtValue(), 3711 getShiftAmountTy(N0.getOperand(0).getOperand(0).getValueType())); 3712 SDValue SRA = DAG.getNode(ISD::SRA, N->getDebugLoc(), LargeVT, 3713 N0.getOperand(0).getOperand(0), Amt); 3714 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, SRA); 3715 } 3716 } 3717 3718 // Simplify, based on bits shifted out of the LHS. 3719 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 3720 return SDValue(N, 0); 3721 3722 3723 // If the sign bit is known to be zero, switch this to a SRL. 3724 if (DAG.SignBitIsZero(N0)) 3725 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, N1); 3726 3727 if (N1C) { 3728 SDValue NewSRA = visitShiftByConstant(N, N1C->getZExtValue()); 3729 if (NewSRA.getNode()) 3730 return NewSRA; 3731 } 3732 3733 return SDValue(); 3734} 3735 3736SDValue DAGCombiner::visitSRL(SDNode *N) { 3737 SDValue N0 = N->getOperand(0); 3738 SDValue N1 = N->getOperand(1); 3739 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3740 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3741 EVT VT = N0.getValueType(); 3742 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits(); 3743 3744 // fold (srl c1, c2) -> c1 >>u c2 3745 if (N0C && N1C) 3746 return DAG.FoldConstantArithmetic(ISD::SRL, VT, N0C, N1C); 3747 // fold (srl 0, x) -> 0 3748 if (N0C && N0C->isNullValue()) 3749 return N0; 3750 // fold (srl x, c >= size(x)) -> undef 3751 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 3752 return DAG.getUNDEF(VT); 3753 // fold (srl x, 0) -> x 3754 if (N1C && N1C->isNullValue()) 3755 return N0; 3756 // if (srl x, c) is known to be zero, return 0 3757 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0), 3758 APInt::getAllOnesValue(OpSizeInBits))) 3759 return DAG.getConstant(0, VT); 3760 3761 // fold (srl (srl x, c1), c2) -> 0 or (srl x, (add c1, c2)) 3762 if (N1C && N0.getOpcode() == ISD::SRL && 3763 N0.getOperand(1).getOpcode() == ISD::Constant) { 3764 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 3765 uint64_t c2 = N1C->getZExtValue(); 3766 if (c1 + c2 >= OpSizeInBits) 3767 return DAG.getConstant(0, VT); 3768 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), 3769 DAG.getConstant(c1 + c2, N1.getValueType())); 3770 } 3771 3772 // fold (srl (trunc (srl x, c1)), c2) -> 0 or (trunc (srl x, (add c1, c2))) 3773 if (N1C && N0.getOpcode() == ISD::TRUNCATE && 3774 N0.getOperand(0).getOpcode() == ISD::SRL && 3775 isa<ConstantSDNode>(N0.getOperand(0)->getOperand(1))) { 3776 uint64_t c1 = 3777 cast<ConstantSDNode>(N0.getOperand(0)->getOperand(1))->getZExtValue(); 3778 uint64_t c2 = N1C->getZExtValue(); 3779 EVT InnerShiftVT = N0.getOperand(0).getValueType(); 3780 EVT ShiftCountVT = N0.getOperand(0)->getOperand(1).getValueType(); 3781 uint64_t InnerShiftSize = InnerShiftVT.getScalarType().getSizeInBits(); 3782 // This is only valid if the OpSizeInBits + c1 = size of inner shift. 3783 if (c1 + OpSizeInBits == InnerShiftSize) { 3784 if (c1 + c2 >= InnerShiftSize) 3785 return DAG.getConstant(0, VT); 3786 return DAG.getNode(ISD::TRUNCATE, N0->getDebugLoc(), VT, 3787 DAG.getNode(ISD::SRL, N0->getDebugLoc(), InnerShiftVT, 3788 N0.getOperand(0)->getOperand(0), 3789 DAG.getConstant(c1 + c2, ShiftCountVT))); 3790 } 3791 } 3792 3793 // fold (srl (shl x, c), c) -> (and x, cst2) 3794 if (N1C && N0.getOpcode() == ISD::SHL && N0.getOperand(1) == N1 && 3795 N0.getValueSizeInBits() <= 64) { 3796 uint64_t ShAmt = N1C->getZExtValue()+64-N0.getValueSizeInBits(); 3797 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0), 3798 DAG.getConstant(~0ULL >> ShAmt, VT)); 3799 } 3800 3801 3802 // fold (srl (anyextend x), c) -> (anyextend (srl x, c)) 3803 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 3804 // Shifting in all undef bits? 3805 EVT SmallVT = N0.getOperand(0).getValueType(); 3806 if (N1C->getZExtValue() >= SmallVT.getSizeInBits()) 3807 return DAG.getUNDEF(VT); 3808 3809 if (!LegalTypes || TLI.isTypeDesirableForOp(ISD::SRL, SmallVT)) { 3810 uint64_t ShiftAmt = N1C->getZExtValue(); 3811 SDValue SmallShift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), SmallVT, 3812 N0.getOperand(0), 3813 DAG.getConstant(ShiftAmt, getShiftAmountTy(SmallVT))); 3814 AddToWorkList(SmallShift.getNode()); 3815 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, SmallShift); 3816 } 3817 } 3818 3819 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign 3820 // bit, which is unmodified by sra. 3821 if (N1C && N1C->getZExtValue() + 1 == VT.getSizeInBits()) { 3822 if (N0.getOpcode() == ISD::SRA) 3823 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), N1); 3824 } 3825 3826 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit). 3827 if (N1C && N0.getOpcode() == ISD::CTLZ && 3828 N1C->getAPIntValue() == Log2_32(VT.getSizeInBits())) { 3829 APInt KnownZero, KnownOne; 3830 DAG.ComputeMaskedBits(N0.getOperand(0), KnownZero, KnownOne); 3831 3832 // If any of the input bits are KnownOne, then the input couldn't be all 3833 // zeros, thus the result of the srl will always be zero. 3834 if (KnownOne.getBoolValue()) return DAG.getConstant(0, VT); 3835 3836 // If all of the bits input the to ctlz node are known to be zero, then 3837 // the result of the ctlz is "32" and the result of the shift is one. 3838 APInt UnknownBits = ~KnownZero; 3839 if (UnknownBits == 0) return DAG.getConstant(1, VT); 3840 3841 // Otherwise, check to see if there is exactly one bit input to the ctlz. 3842 if ((UnknownBits & (UnknownBits - 1)) == 0) { 3843 // Okay, we know that only that the single bit specified by UnknownBits 3844 // could be set on input to the CTLZ node. If this bit is set, the SRL 3845 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair 3846 // to an SRL/XOR pair, which is likely to simplify more. 3847 unsigned ShAmt = UnknownBits.countTrailingZeros(); 3848 SDValue Op = N0.getOperand(0); 3849 3850 if (ShAmt) { 3851 Op = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, Op, 3852 DAG.getConstant(ShAmt, getShiftAmountTy(Op.getValueType()))); 3853 AddToWorkList(Op.getNode()); 3854 } 3855 3856 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, 3857 Op, DAG.getConstant(1, VT)); 3858 } 3859 } 3860 3861 // fold (srl x, (trunc (and y, c))) -> (srl x, (and (trunc y), (trunc c))). 3862 if (N1.getOpcode() == ISD::TRUNCATE && 3863 N1.getOperand(0).getOpcode() == ISD::AND && 3864 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 3865 SDValue N101 = N1.getOperand(0).getOperand(1); 3866 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 3867 EVT TruncVT = N1.getValueType(); 3868 SDValue N100 = N1.getOperand(0).getOperand(0); 3869 APInt TruncC = N101C->getAPIntValue(); 3870 TruncC = TruncC.trunc(TruncVT.getSizeInBits()); 3871 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, 3872 DAG.getNode(ISD::AND, N->getDebugLoc(), 3873 TruncVT, 3874 DAG.getNode(ISD::TRUNCATE, 3875 N->getDebugLoc(), 3876 TruncVT, N100), 3877 DAG.getConstant(TruncC, TruncVT))); 3878 } 3879 } 3880 3881 // fold operands of srl based on knowledge that the low bits are not 3882 // demanded. 3883 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 3884 return SDValue(N, 0); 3885 3886 if (N1C) { 3887 SDValue NewSRL = visitShiftByConstant(N, N1C->getZExtValue()); 3888 if (NewSRL.getNode()) 3889 return NewSRL; 3890 } 3891 3892 // Attempt to convert a srl of a load into a narrower zero-extending load. 3893 SDValue NarrowLoad = ReduceLoadWidth(N); 3894 if (NarrowLoad.getNode()) 3895 return NarrowLoad; 3896 3897 // Here is a common situation. We want to optimize: 3898 // 3899 // %a = ... 3900 // %b = and i32 %a, 2 3901 // %c = srl i32 %b, 1 3902 // brcond i32 %c ... 3903 // 3904 // into 3905 // 3906 // %a = ... 3907 // %b = and %a, 2 3908 // %c = setcc eq %b, 0 3909 // brcond %c ... 3910 // 3911 // However when after the source operand of SRL is optimized into AND, the SRL 3912 // itself may not be optimized further. Look for it and add the BRCOND into 3913 // the worklist. 3914 if (N->hasOneUse()) { 3915 SDNode *Use = *N->use_begin(); 3916 if (Use->getOpcode() == ISD::BRCOND) 3917 AddToWorkList(Use); 3918 else if (Use->getOpcode() == ISD::TRUNCATE && Use->hasOneUse()) { 3919 // Also look pass the truncate. 3920 Use = *Use->use_begin(); 3921 if (Use->getOpcode() == ISD::BRCOND) 3922 AddToWorkList(Use); 3923 } 3924 } 3925 3926 return SDValue(); 3927} 3928 3929SDValue DAGCombiner::visitCTLZ(SDNode *N) { 3930 SDValue N0 = N->getOperand(0); 3931 EVT VT = N->getValueType(0); 3932 3933 // fold (ctlz c1) -> c2 3934 if (isa<ConstantSDNode>(N0)) 3935 return DAG.getNode(ISD::CTLZ, N->getDebugLoc(), VT, N0); 3936 return SDValue(); 3937} 3938 3939SDValue DAGCombiner::visitCTLZ_ZERO_UNDEF(SDNode *N) { 3940 SDValue N0 = N->getOperand(0); 3941 EVT VT = N->getValueType(0); 3942 3943 // fold (ctlz_zero_undef c1) -> c2 3944 if (isa<ConstantSDNode>(N0)) 3945 return DAG.getNode(ISD::CTLZ_ZERO_UNDEF, N->getDebugLoc(), VT, N0); 3946 return SDValue(); 3947} 3948 3949SDValue DAGCombiner::visitCTTZ(SDNode *N) { 3950 SDValue N0 = N->getOperand(0); 3951 EVT VT = N->getValueType(0); 3952 3953 // fold (cttz c1) -> c2 3954 if (isa<ConstantSDNode>(N0)) 3955 return DAG.getNode(ISD::CTTZ, N->getDebugLoc(), VT, N0); 3956 return SDValue(); 3957} 3958 3959SDValue DAGCombiner::visitCTTZ_ZERO_UNDEF(SDNode *N) { 3960 SDValue N0 = N->getOperand(0); 3961 EVT VT = N->getValueType(0); 3962 3963 // fold (cttz_zero_undef c1) -> c2 3964 if (isa<ConstantSDNode>(N0)) 3965 return DAG.getNode(ISD::CTTZ_ZERO_UNDEF, N->getDebugLoc(), VT, N0); 3966 return SDValue(); 3967} 3968 3969SDValue DAGCombiner::visitCTPOP(SDNode *N) { 3970 SDValue N0 = N->getOperand(0); 3971 EVT VT = N->getValueType(0); 3972 3973 // fold (ctpop c1) -> c2 3974 if (isa<ConstantSDNode>(N0)) 3975 return DAG.getNode(ISD::CTPOP, N->getDebugLoc(), VT, N0); 3976 return SDValue(); 3977} 3978 3979SDValue DAGCombiner::visitSELECT(SDNode *N) { 3980 SDValue N0 = N->getOperand(0); 3981 SDValue N1 = N->getOperand(1); 3982 SDValue N2 = N->getOperand(2); 3983 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3984 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3985 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2); 3986 EVT VT = N->getValueType(0); 3987 EVT VT0 = N0.getValueType(); 3988 3989 // fold (select C, X, X) -> X 3990 if (N1 == N2) 3991 return N1; 3992 // fold (select true, X, Y) -> X 3993 if (N0C && !N0C->isNullValue()) 3994 return N1; 3995 // fold (select false, X, Y) -> Y 3996 if (N0C && N0C->isNullValue()) 3997 return N2; 3998 // fold (select C, 1, X) -> (or C, X) 3999 if (VT == MVT::i1 && N1C && N1C->getAPIntValue() == 1) 4000 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2); 4001 // fold (select C, 0, 1) -> (xor C, 1) 4002 if (VT.isInteger() && 4003 (VT0 == MVT::i1 || 4004 (VT0.isInteger() && 4005 TLI.getBooleanContents(false) == TargetLowering::ZeroOrOneBooleanContent)) && 4006 N1C && N2C && N1C->isNullValue() && N2C->getAPIntValue() == 1) { 4007 SDValue XORNode; 4008 if (VT == VT0) 4009 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT0, 4010 N0, DAG.getConstant(1, VT0)); 4011 XORNode = DAG.getNode(ISD::XOR, N0.getDebugLoc(), VT0, 4012 N0, DAG.getConstant(1, VT0)); 4013 AddToWorkList(XORNode.getNode()); 4014 if (VT.bitsGT(VT0)) 4015 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, XORNode); 4016 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, XORNode); 4017 } 4018 // fold (select C, 0, X) -> (and (not C), X) 4019 if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) { 4020 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT); 4021 AddToWorkList(NOTNode.getNode()); 4022 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, NOTNode, N2); 4023 } 4024 // fold (select C, X, 1) -> (or (not C), X) 4025 if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getAPIntValue() == 1) { 4026 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT); 4027 AddToWorkList(NOTNode.getNode()); 4028 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, NOTNode, N1); 4029 } 4030 // fold (select C, X, 0) -> (and C, X) 4031 if (VT == MVT::i1 && N2C && N2C->isNullValue()) 4032 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1); 4033 // fold (select X, X, Y) -> (or X, Y) 4034 // fold (select X, 1, Y) -> (or X, Y) 4035 if (VT == MVT::i1 && (N0 == N1 || (N1C && N1C->getAPIntValue() == 1))) 4036 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2); 4037 // fold (select X, Y, X) -> (and X, Y) 4038 // fold (select X, Y, 0) -> (and X, Y) 4039 if (VT == MVT::i1 && (N0 == N2 || (N2C && N2C->getAPIntValue() == 0))) 4040 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1); 4041 4042 // If we can fold this based on the true/false value, do so. 4043 if (SimplifySelectOps(N, N1, N2)) 4044 return SDValue(N, 0); // Don't revisit N. 4045 4046 // fold selects based on a setcc into other things, such as min/max/abs 4047 if (N0.getOpcode() == ISD::SETCC) { 4048 // FIXME: 4049 // Check against MVT::Other for SELECT_CC, which is a workaround for targets 4050 // having to say they don't support SELECT_CC on every type the DAG knows 4051 // about, since there is no way to mark an opcode illegal at all value types 4052 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other) && 4053 TLI.isOperationLegalOrCustom(ISD::SELECT_CC, VT)) 4054 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT, 4055 N0.getOperand(0), N0.getOperand(1), 4056 N1, N2, N0.getOperand(2)); 4057 return SimplifySelect(N->getDebugLoc(), N0, N1, N2); 4058 } 4059 4060 return SDValue(); 4061} 4062 4063SDValue DAGCombiner::visitSELECT_CC(SDNode *N) { 4064 SDValue N0 = N->getOperand(0); 4065 SDValue N1 = N->getOperand(1); 4066 SDValue N2 = N->getOperand(2); 4067 SDValue N3 = N->getOperand(3); 4068 SDValue N4 = N->getOperand(4); 4069 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get(); 4070 4071 // fold select_cc lhs, rhs, x, x, cc -> x 4072 if (N2 == N3) 4073 return N2; 4074 4075 // Determine if the condition we're dealing with is constant 4076 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()), 4077 N0, N1, CC, N->getDebugLoc(), false); 4078 if (SCC.getNode()) AddToWorkList(SCC.getNode()); 4079 4080 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode())) { 4081 if (!SCCC->isNullValue()) 4082 return N2; // cond always true -> true val 4083 else 4084 return N3; // cond always false -> false val 4085 } 4086 4087 // Fold to a simpler select_cc 4088 if (SCC.getNode() && SCC.getOpcode() == ISD::SETCC) 4089 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), N2.getValueType(), 4090 SCC.getOperand(0), SCC.getOperand(1), N2, N3, 4091 SCC.getOperand(2)); 4092 4093 // If we can fold this based on the true/false value, do so. 4094 if (SimplifySelectOps(N, N2, N3)) 4095 return SDValue(N, 0); // Don't revisit N. 4096 4097 // fold select_cc into other things, such as min/max/abs 4098 return SimplifySelectCC(N->getDebugLoc(), N0, N1, N2, N3, CC); 4099} 4100 4101SDValue DAGCombiner::visitSETCC(SDNode *N) { 4102 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1), 4103 cast<CondCodeSDNode>(N->getOperand(2))->get(), 4104 N->getDebugLoc()); 4105} 4106 4107// ExtendUsesToFormExtLoad - Trying to extend uses of a load to enable this: 4108// "fold ({s|z|a}ext (load x)) -> ({s|z|a}ext (truncate ({s|z|a}extload x)))" 4109// transformation. Returns true if extension are possible and the above 4110// mentioned transformation is profitable. 4111static bool ExtendUsesToFormExtLoad(SDNode *N, SDValue N0, 4112 unsigned ExtOpc, 4113 SmallVector<SDNode*, 4> &ExtendNodes, 4114 const TargetLowering &TLI) { 4115 bool HasCopyToRegUses = false; 4116 bool isTruncFree = TLI.isTruncateFree(N->getValueType(0), N0.getValueType()); 4117 for (SDNode::use_iterator UI = N0.getNode()->use_begin(), 4118 UE = N0.getNode()->use_end(); 4119 UI != UE; ++UI) { 4120 SDNode *User = *UI; 4121 if (User == N) 4122 continue; 4123 if (UI.getUse().getResNo() != N0.getResNo()) 4124 continue; 4125 // FIXME: Only extend SETCC N, N and SETCC N, c for now. 4126 if (ExtOpc != ISD::ANY_EXTEND && User->getOpcode() == ISD::SETCC) { 4127 ISD::CondCode CC = cast<CondCodeSDNode>(User->getOperand(2))->get(); 4128 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC)) 4129 // Sign bits will be lost after a zext. 4130 return false; 4131 bool Add = false; 4132 for (unsigned i = 0; i != 2; ++i) { 4133 SDValue UseOp = User->getOperand(i); 4134 if (UseOp == N0) 4135 continue; 4136 if (!isa<ConstantSDNode>(UseOp)) 4137 return false; 4138 Add = true; 4139 } 4140 if (Add) 4141 ExtendNodes.push_back(User); 4142 continue; 4143 } 4144 // If truncates aren't free and there are users we can't 4145 // extend, it isn't worthwhile. 4146 if (!isTruncFree) 4147 return false; 4148 // Remember if this value is live-out. 4149 if (User->getOpcode() == ISD::CopyToReg) 4150 HasCopyToRegUses = true; 4151 } 4152 4153 if (HasCopyToRegUses) { 4154 bool BothLiveOut = false; 4155 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 4156 UI != UE; ++UI) { 4157 SDUse &Use = UI.getUse(); 4158 if (Use.getResNo() == 0 && Use.getUser()->getOpcode() == ISD::CopyToReg) { 4159 BothLiveOut = true; 4160 break; 4161 } 4162 } 4163 if (BothLiveOut) 4164 // Both unextended and extended values are live out. There had better be 4165 // a good reason for the transformation. 4166 return ExtendNodes.size(); 4167 } 4168 return true; 4169} 4170 4171void DAGCombiner::ExtendSetCCUses(SmallVector<SDNode*, 4> SetCCs, 4172 SDValue Trunc, SDValue ExtLoad, DebugLoc DL, 4173 ISD::NodeType ExtType) { 4174 // Extend SetCC uses if necessary. 4175 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 4176 SDNode *SetCC = SetCCs[i]; 4177 SmallVector<SDValue, 4> Ops; 4178 4179 for (unsigned j = 0; j != 2; ++j) { 4180 SDValue SOp = SetCC->getOperand(j); 4181 if (SOp == Trunc) 4182 Ops.push_back(ExtLoad); 4183 else 4184 Ops.push_back(DAG.getNode(ExtType, DL, ExtLoad->getValueType(0), SOp)); 4185 } 4186 4187 Ops.push_back(SetCC->getOperand(2)); 4188 CombineTo(SetCC, DAG.getNode(ISD::SETCC, DL, SetCC->getValueType(0), 4189 &Ops[0], Ops.size())); 4190 } 4191} 4192 4193SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) { 4194 SDValue N0 = N->getOperand(0); 4195 EVT VT = N->getValueType(0); 4196 4197 // fold (sext c1) -> c1 4198 if (isa<ConstantSDNode>(N0)) 4199 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N0); 4200 4201 // fold (sext (sext x)) -> (sext x) 4202 // fold (sext (aext x)) -> (sext x) 4203 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 4204 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, 4205 N0.getOperand(0)); 4206 4207 if (N0.getOpcode() == ISD::TRUNCATE) { 4208 // fold (sext (truncate (load x))) -> (sext (smaller load x)) 4209 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n))) 4210 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 4211 if (NarrowLoad.getNode()) { 4212 SDNode* oye = N0.getNode()->getOperand(0).getNode(); 4213 if (NarrowLoad.getNode() != N0.getNode()) { 4214 CombineTo(N0.getNode(), NarrowLoad); 4215 // CombineTo deleted the truncate, if needed, but not what's under it. 4216 AddToWorkList(oye); 4217 } 4218 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4219 } 4220 4221 // See if the value being truncated is already sign extended. If so, just 4222 // eliminate the trunc/sext pair. 4223 SDValue Op = N0.getOperand(0); 4224 unsigned OpBits = Op.getValueType().getScalarType().getSizeInBits(); 4225 unsigned MidBits = N0.getValueType().getScalarType().getSizeInBits(); 4226 unsigned DestBits = VT.getScalarType().getSizeInBits(); 4227 unsigned NumSignBits = DAG.ComputeNumSignBits(Op); 4228 4229 if (OpBits == DestBits) { 4230 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign 4231 // bits, it is already ready. 4232 if (NumSignBits > DestBits-MidBits) 4233 return Op; 4234 } else if (OpBits < DestBits) { 4235 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign 4236 // bits, just sext from i32. 4237 if (NumSignBits > OpBits-MidBits) 4238 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, Op); 4239 } else { 4240 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign 4241 // bits, just truncate to i32. 4242 if (NumSignBits > OpBits-MidBits) 4243 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op); 4244 } 4245 4246 // fold (sext (truncate x)) -> (sextinreg x). 4247 if (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, 4248 N0.getValueType())) { 4249 if (OpBits < DestBits) 4250 Op = DAG.getNode(ISD::ANY_EXTEND, N0.getDebugLoc(), VT, Op); 4251 else if (OpBits > DestBits) 4252 Op = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), VT, Op); 4253 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, Op, 4254 DAG.getValueType(N0.getValueType())); 4255 } 4256 } 4257 4258 // fold (sext (load x)) -> (sext (truncate (sextload x))) 4259 // None of the supported targets knows how to perform load and sign extend 4260 // on vectors in one instruction. We only perform this transformation on 4261 // scalars. 4262 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() && 4263 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 4264 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()))) { 4265 bool DoXform = true; 4266 SmallVector<SDNode*, 4> SetCCs; 4267 if (!N0.hasOneUse()) 4268 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::SIGN_EXTEND, SetCCs, TLI); 4269 if (DoXform) { 4270 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4271 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 4272 LN0->getChain(), 4273 LN0->getBasePtr(), LN0->getPointerInfo(), 4274 N0.getValueType(), 4275 LN0->isVolatile(), LN0->isNonTemporal(), 4276 LN0->getAlignment()); 4277 CombineTo(N, ExtLoad); 4278 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 4279 N0.getValueType(), ExtLoad); 4280 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 4281 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(), 4282 ISD::SIGN_EXTEND); 4283 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4284 } 4285 } 4286 4287 // fold (sext (sextload x)) -> (sext (truncate (sextload x))) 4288 // fold (sext ( extload x)) -> (sext (truncate (sextload x))) 4289 if ((ISD::isSEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) && 4290 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) { 4291 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4292 EVT MemVT = LN0->getMemoryVT(); 4293 if ((!LegalOperations && !LN0->isVolatile()) || 4294 TLI.isLoadExtLegal(ISD::SEXTLOAD, MemVT)) { 4295 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 4296 LN0->getChain(), 4297 LN0->getBasePtr(), LN0->getPointerInfo(), 4298 MemVT, 4299 LN0->isVolatile(), LN0->isNonTemporal(), 4300 LN0->getAlignment()); 4301 CombineTo(N, ExtLoad); 4302 CombineTo(N0.getNode(), 4303 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 4304 N0.getValueType(), ExtLoad), 4305 ExtLoad.getValue(1)); 4306 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4307 } 4308 } 4309 4310 // fold (sext (and/or/xor (load x), cst)) -> 4311 // (and/or/xor (sextload x), (sext cst)) 4312 if ((N0.getOpcode() == ISD::AND || N0.getOpcode() == ISD::OR || 4313 N0.getOpcode() == ISD::XOR) && 4314 isa<LoadSDNode>(N0.getOperand(0)) && 4315 N0.getOperand(1).getOpcode() == ISD::Constant && 4316 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()) && 4317 (!LegalOperations && TLI.isOperationLegal(N0.getOpcode(), VT))) { 4318 LoadSDNode *LN0 = cast<LoadSDNode>(N0.getOperand(0)); 4319 if (LN0->getExtensionType() != ISD::ZEXTLOAD) { 4320 bool DoXform = true; 4321 SmallVector<SDNode*, 4> SetCCs; 4322 if (!N0.hasOneUse()) 4323 DoXform = ExtendUsesToFormExtLoad(N, N0.getOperand(0), ISD::SIGN_EXTEND, 4324 SetCCs, TLI); 4325 if (DoXform) { 4326 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, LN0->getDebugLoc(), VT, 4327 LN0->getChain(), LN0->getBasePtr(), 4328 LN0->getPointerInfo(), 4329 LN0->getMemoryVT(), 4330 LN0->isVolatile(), 4331 LN0->isNonTemporal(), 4332 LN0->getAlignment()); 4333 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 4334 Mask = Mask.sext(VT.getSizeInBits()); 4335 SDValue And = DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, 4336 ExtLoad, DAG.getConstant(Mask, VT)); 4337 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, 4338 N0.getOperand(0).getDebugLoc(), 4339 N0.getOperand(0).getValueType(), ExtLoad); 4340 CombineTo(N, And); 4341 CombineTo(N0.getOperand(0).getNode(), Trunc, ExtLoad.getValue(1)); 4342 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(), 4343 ISD::SIGN_EXTEND); 4344 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4345 } 4346 } 4347 } 4348 4349 if (N0.getOpcode() == ISD::SETCC) { 4350 // sext(setcc) -> sext_in_reg(vsetcc) for vectors. 4351 // Only do this before legalize for now. 4352 if (VT.isVector() && !LegalOperations) { 4353 EVT N0VT = N0.getOperand(0).getValueType(); 4354 // On some architectures (such as SSE/NEON/etc) the SETCC result type is 4355 // of the same size as the compared operands. Only optimize sext(setcc()) 4356 // if this is the case. 4357 EVT SVT = TLI.getSetCCResultType(N0VT); 4358 4359 // We know that the # elements of the results is the same as the 4360 // # elements of the compare (and the # elements of the compare result 4361 // for that matter). Check to see that they are the same size. If so, 4362 // we know that the element size of the sext'd result matches the 4363 // element size of the compare operands. 4364 if (VT.getSizeInBits() == SVT.getSizeInBits()) 4365 return DAG.getSetCC(N->getDebugLoc(), VT, N0.getOperand(0), 4366 N0.getOperand(1), 4367 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 4368 // If the desired elements are smaller or larger than the source 4369 // elements we can use a matching integer vector type and then 4370 // truncate/sign extend 4371 else { 4372 EVT MatchingElementType = 4373 EVT::getIntegerVT(*DAG.getContext(), 4374 N0VT.getScalarType().getSizeInBits()); 4375 EVT MatchingVectorType = 4376 EVT::getVectorVT(*DAG.getContext(), MatchingElementType, 4377 N0VT.getVectorNumElements()); 4378 4379 if (SVT == MatchingVectorType) { 4380 SDValue VsetCC = DAG.getSetCC(N->getDebugLoc(), MatchingVectorType, 4381 N0.getOperand(0), N0.getOperand(1), 4382 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 4383 return DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT); 4384 } 4385 } 4386 } 4387 4388 // sext(setcc x, y, cc) -> (select_cc x, y, -1, 0, cc) 4389 unsigned ElementWidth = VT.getScalarType().getSizeInBits(); 4390 SDValue NegOne = 4391 DAG.getConstant(APInt::getAllOnesValue(ElementWidth), VT); 4392 SDValue SCC = 4393 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 4394 NegOne, DAG.getConstant(0, VT), 4395 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 4396 if (SCC.getNode()) return SCC; 4397 if (!LegalOperations || 4398 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(VT))) 4399 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT, 4400 DAG.getSetCC(N->getDebugLoc(), 4401 TLI.getSetCCResultType(VT), 4402 N0.getOperand(0), N0.getOperand(1), 4403 cast<CondCodeSDNode>(N0.getOperand(2))->get()), 4404 NegOne, DAG.getConstant(0, VT)); 4405 } 4406 4407 // fold (sext x) -> (zext x) if the sign bit is known zero. 4408 if ((!LegalOperations || TLI.isOperationLegal(ISD::ZERO_EXTEND, VT)) && 4409 DAG.SignBitIsZero(N0)) 4410 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0); 4411 4412 return SDValue(); 4413} 4414 4415// isTruncateOf - If N is a truncate of some other value, return true, record 4416// the value being truncated in Op and which of Op's bits are zero in KnownZero. 4417// This function computes KnownZero to avoid a duplicated call to 4418// ComputeMaskedBits in the caller. 4419static bool isTruncateOf(SelectionDAG &DAG, SDValue N, SDValue &Op, 4420 APInt &KnownZero) { 4421 APInt KnownOne; 4422 if (N->getOpcode() == ISD::TRUNCATE) { 4423 Op = N->getOperand(0); 4424 DAG.ComputeMaskedBits(Op, KnownZero, KnownOne); 4425 return true; 4426 } 4427 4428 if (N->getOpcode() != ISD::SETCC || N->getValueType(0) != MVT::i1 || 4429 cast<CondCodeSDNode>(N->getOperand(2))->get() != ISD::SETNE) 4430 return false; 4431 4432 SDValue Op0 = N->getOperand(0); 4433 SDValue Op1 = N->getOperand(1); 4434 assert(Op0.getValueType() == Op1.getValueType()); 4435 4436 ConstantSDNode *COp0 = dyn_cast<ConstantSDNode>(Op0); 4437 ConstantSDNode *COp1 = dyn_cast<ConstantSDNode>(Op1); 4438 if (COp0 && COp0->isNullValue()) 4439 Op = Op1; 4440 else if (COp1 && COp1->isNullValue()) 4441 Op = Op0; 4442 else 4443 return false; 4444 4445 DAG.ComputeMaskedBits(Op, KnownZero, KnownOne); 4446 4447 if (!(KnownZero | APInt(Op.getValueSizeInBits(), 1)).isAllOnesValue()) 4448 return false; 4449 4450 return true; 4451} 4452 4453SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) { 4454 SDValue N0 = N->getOperand(0); 4455 EVT VT = N->getValueType(0); 4456 4457 // fold (zext c1) -> c1 4458 if (isa<ConstantSDNode>(N0)) 4459 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0); 4460 // fold (zext (zext x)) -> (zext x) 4461 // fold (zext (aext x)) -> (zext x) 4462 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 4463 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, 4464 N0.getOperand(0)); 4465 4466 // fold (zext (truncate x)) -> (zext x) or 4467 // (zext (truncate x)) -> (truncate x) 4468 // This is valid when the truncated bits of x are already zero. 4469 // FIXME: We should extend this to work for vectors too. 4470 SDValue Op; 4471 APInt KnownZero; 4472 if (!VT.isVector() && isTruncateOf(DAG, N0, Op, KnownZero)) { 4473 APInt TruncatedBits = 4474 (Op.getValueSizeInBits() == N0.getValueSizeInBits()) ? 4475 APInt(Op.getValueSizeInBits(), 0) : 4476 APInt::getBitsSet(Op.getValueSizeInBits(), 4477 N0.getValueSizeInBits(), 4478 std::min(Op.getValueSizeInBits(), 4479 VT.getSizeInBits())); 4480 if (TruncatedBits == (KnownZero & TruncatedBits)) { 4481 if (VT.bitsGT(Op.getValueType())) 4482 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, Op); 4483 if (VT.bitsLT(Op.getValueType())) 4484 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op); 4485 4486 return Op; 4487 } 4488 } 4489 4490 // fold (zext (truncate (load x))) -> (zext (smaller load x)) 4491 // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n))) 4492 if (N0.getOpcode() == ISD::TRUNCATE) { 4493 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 4494 if (NarrowLoad.getNode()) { 4495 SDNode* oye = N0.getNode()->getOperand(0).getNode(); 4496 if (NarrowLoad.getNode() != N0.getNode()) { 4497 CombineTo(N0.getNode(), NarrowLoad); 4498 // CombineTo deleted the truncate, if needed, but not what's under it. 4499 AddToWorkList(oye); 4500 } 4501 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4502 } 4503 } 4504 4505 // fold (zext (truncate x)) -> (and x, mask) 4506 if (N0.getOpcode() == ISD::TRUNCATE && 4507 (!LegalOperations || TLI.isOperationLegal(ISD::AND, VT))) { 4508 4509 // fold (zext (truncate (load x))) -> (zext (smaller load x)) 4510 // fold (zext (truncate (srl (load x), c))) -> (zext (smaller load (x+c/n))) 4511 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 4512 if (NarrowLoad.getNode()) { 4513 SDNode* oye = N0.getNode()->getOperand(0).getNode(); 4514 if (NarrowLoad.getNode() != N0.getNode()) { 4515 CombineTo(N0.getNode(), NarrowLoad); 4516 // CombineTo deleted the truncate, if needed, but not what's under it. 4517 AddToWorkList(oye); 4518 } 4519 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4520 } 4521 4522 SDValue Op = N0.getOperand(0); 4523 if (Op.getValueType().bitsLT(VT)) { 4524 Op = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, Op); 4525 AddToWorkList(Op.getNode()); 4526 } else if (Op.getValueType().bitsGT(VT)) { 4527 Op = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op); 4528 AddToWorkList(Op.getNode()); 4529 } 4530 return DAG.getZeroExtendInReg(Op, N->getDebugLoc(), 4531 N0.getValueType().getScalarType()); 4532 } 4533 4534 // Fold (zext (and (trunc x), cst)) -> (and x, cst), 4535 // if either of the casts is not free. 4536 if (N0.getOpcode() == ISD::AND && 4537 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 4538 N0.getOperand(1).getOpcode() == ISD::Constant && 4539 (!TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(), 4540 N0.getValueType()) || 4541 !TLI.isZExtFree(N0.getValueType(), VT))) { 4542 SDValue X = N0.getOperand(0).getOperand(0); 4543 if (X.getValueType().bitsLT(VT)) { 4544 X = DAG.getNode(ISD::ANY_EXTEND, X.getDebugLoc(), VT, X); 4545 } else if (X.getValueType().bitsGT(VT)) { 4546 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X); 4547 } 4548 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 4549 Mask = Mask.zext(VT.getSizeInBits()); 4550 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 4551 X, DAG.getConstant(Mask, VT)); 4552 } 4553 4554 // fold (zext (load x)) -> (zext (truncate (zextload x))) 4555 // None of the supported targets knows how to perform load and vector_zext 4556 // on vectors in one instruction. We only perform this transformation on 4557 // scalars. 4558 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() && 4559 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 4560 TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()))) { 4561 bool DoXform = true; 4562 SmallVector<SDNode*, 4> SetCCs; 4563 if (!N0.hasOneUse()) 4564 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ZERO_EXTEND, SetCCs, TLI); 4565 if (DoXform) { 4566 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4567 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT, 4568 LN0->getChain(), 4569 LN0->getBasePtr(), LN0->getPointerInfo(), 4570 N0.getValueType(), 4571 LN0->isVolatile(), LN0->isNonTemporal(), 4572 LN0->getAlignment()); 4573 CombineTo(N, ExtLoad); 4574 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 4575 N0.getValueType(), ExtLoad); 4576 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 4577 4578 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(), 4579 ISD::ZERO_EXTEND); 4580 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4581 } 4582 } 4583 4584 // fold (zext (and/or/xor (load x), cst)) -> 4585 // (and/or/xor (zextload x), (zext cst)) 4586 if ((N0.getOpcode() == ISD::AND || N0.getOpcode() == ISD::OR || 4587 N0.getOpcode() == ISD::XOR) && 4588 isa<LoadSDNode>(N0.getOperand(0)) && 4589 N0.getOperand(1).getOpcode() == ISD::Constant && 4590 TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()) && 4591 (!LegalOperations && TLI.isOperationLegal(N0.getOpcode(), VT))) { 4592 LoadSDNode *LN0 = cast<LoadSDNode>(N0.getOperand(0)); 4593 if (LN0->getExtensionType() != ISD::SEXTLOAD) { 4594 bool DoXform = true; 4595 SmallVector<SDNode*, 4> SetCCs; 4596 if (!N0.hasOneUse()) 4597 DoXform = ExtendUsesToFormExtLoad(N, N0.getOperand(0), ISD::ZERO_EXTEND, 4598 SetCCs, TLI); 4599 if (DoXform) { 4600 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), VT, 4601 LN0->getChain(), LN0->getBasePtr(), 4602 LN0->getPointerInfo(), 4603 LN0->getMemoryVT(), 4604 LN0->isVolatile(), 4605 LN0->isNonTemporal(), 4606 LN0->getAlignment()); 4607 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 4608 Mask = Mask.zext(VT.getSizeInBits()); 4609 SDValue And = DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, 4610 ExtLoad, DAG.getConstant(Mask, VT)); 4611 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, 4612 N0.getOperand(0).getDebugLoc(), 4613 N0.getOperand(0).getValueType(), ExtLoad); 4614 CombineTo(N, And); 4615 CombineTo(N0.getOperand(0).getNode(), Trunc, ExtLoad.getValue(1)); 4616 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(), 4617 ISD::ZERO_EXTEND); 4618 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4619 } 4620 } 4621 } 4622 4623 // fold (zext (zextload x)) -> (zext (truncate (zextload x))) 4624 // fold (zext ( extload x)) -> (zext (truncate (zextload x))) 4625 if ((ISD::isZEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) && 4626 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) { 4627 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4628 EVT MemVT = LN0->getMemoryVT(); 4629 if ((!LegalOperations && !LN0->isVolatile()) || 4630 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT)) { 4631 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT, 4632 LN0->getChain(), 4633 LN0->getBasePtr(), LN0->getPointerInfo(), 4634 MemVT, 4635 LN0->isVolatile(), LN0->isNonTemporal(), 4636 LN0->getAlignment()); 4637 CombineTo(N, ExtLoad); 4638 CombineTo(N0.getNode(), 4639 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), N0.getValueType(), 4640 ExtLoad), 4641 ExtLoad.getValue(1)); 4642 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4643 } 4644 } 4645 4646 if (N0.getOpcode() == ISD::SETCC) { 4647 if (!LegalOperations && VT.isVector()) { 4648 // zext(setcc) -> (and (vsetcc), (1, 1, ...) for vectors. 4649 // Only do this before legalize for now. 4650 EVT N0VT = N0.getOperand(0).getValueType(); 4651 EVT EltVT = VT.getVectorElementType(); 4652 SmallVector<SDValue,8> OneOps(VT.getVectorNumElements(), 4653 DAG.getConstant(1, EltVT)); 4654 if (VT.getSizeInBits() == N0VT.getSizeInBits()) 4655 // We know that the # elements of the results is the same as the 4656 // # elements of the compare (and the # elements of the compare result 4657 // for that matter). Check to see that they are the same size. If so, 4658 // we know that the element size of the sext'd result matches the 4659 // element size of the compare operands. 4660 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 4661 DAG.getSetCC(N->getDebugLoc(), VT, N0.getOperand(0), 4662 N0.getOperand(1), 4663 cast<CondCodeSDNode>(N0.getOperand(2))->get()), 4664 DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT, 4665 &OneOps[0], OneOps.size())); 4666 4667 // If the desired elements are smaller or larger than the source 4668 // elements we can use a matching integer vector type and then 4669 // truncate/sign extend 4670 EVT MatchingElementType = 4671 EVT::getIntegerVT(*DAG.getContext(), 4672 N0VT.getScalarType().getSizeInBits()); 4673 EVT MatchingVectorType = 4674 EVT::getVectorVT(*DAG.getContext(), MatchingElementType, 4675 N0VT.getVectorNumElements()); 4676 SDValue VsetCC = 4677 DAG.getSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0), 4678 N0.getOperand(1), 4679 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 4680 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 4681 DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT), 4682 DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT, 4683 &OneOps[0], OneOps.size())); 4684 } 4685 4686 // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 4687 SDValue SCC = 4688 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 4689 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 4690 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 4691 if (SCC.getNode()) return SCC; 4692 } 4693 4694 // (zext (shl (zext x), cst)) -> (shl (zext x), cst) 4695 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL) && 4696 isa<ConstantSDNode>(N0.getOperand(1)) && 4697 N0.getOperand(0).getOpcode() == ISD::ZERO_EXTEND && 4698 N0.hasOneUse()) { 4699 SDValue ShAmt = N0.getOperand(1); 4700 unsigned ShAmtVal = cast<ConstantSDNode>(ShAmt)->getZExtValue(); 4701 if (N0.getOpcode() == ISD::SHL) { 4702 SDValue InnerZExt = N0.getOperand(0); 4703 // If the original shl may be shifting out bits, do not perform this 4704 // transformation. 4705 unsigned KnownZeroBits = InnerZExt.getValueType().getSizeInBits() - 4706 InnerZExt.getOperand(0).getValueType().getSizeInBits(); 4707 if (ShAmtVal > KnownZeroBits) 4708 return SDValue(); 4709 } 4710 4711 DebugLoc DL = N->getDebugLoc(); 4712 4713 // Ensure that the shift amount is wide enough for the shifted value. 4714 if (VT.getSizeInBits() >= 256) 4715 ShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, ShAmt); 4716 4717 return DAG.getNode(N0.getOpcode(), DL, VT, 4718 DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0)), 4719 ShAmt); 4720 } 4721 4722 return SDValue(); 4723} 4724 4725SDValue DAGCombiner::visitANY_EXTEND(SDNode *N) { 4726 SDValue N0 = N->getOperand(0); 4727 EVT VT = N->getValueType(0); 4728 4729 // fold (aext c1) -> c1 4730 if (isa<ConstantSDNode>(N0)) 4731 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, N0); 4732 // fold (aext (aext x)) -> (aext x) 4733 // fold (aext (zext x)) -> (zext x) 4734 // fold (aext (sext x)) -> (sext x) 4735 if (N0.getOpcode() == ISD::ANY_EXTEND || 4736 N0.getOpcode() == ISD::ZERO_EXTEND || 4737 N0.getOpcode() == ISD::SIGN_EXTEND) 4738 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, N0.getOperand(0)); 4739 4740 // fold (aext (truncate (load x))) -> (aext (smaller load x)) 4741 // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n))) 4742 if (N0.getOpcode() == ISD::TRUNCATE) { 4743 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 4744 if (NarrowLoad.getNode()) { 4745 SDNode* oye = N0.getNode()->getOperand(0).getNode(); 4746 if (NarrowLoad.getNode() != N0.getNode()) { 4747 CombineTo(N0.getNode(), NarrowLoad); 4748 // CombineTo deleted the truncate, if needed, but not what's under it. 4749 AddToWorkList(oye); 4750 } 4751 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4752 } 4753 } 4754 4755 // fold (aext (truncate x)) 4756 if (N0.getOpcode() == ISD::TRUNCATE) { 4757 SDValue TruncOp = N0.getOperand(0); 4758 if (TruncOp.getValueType() == VT) 4759 return TruncOp; // x iff x size == zext size. 4760 if (TruncOp.getValueType().bitsGT(VT)) 4761 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, TruncOp); 4762 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, TruncOp); 4763 } 4764 4765 // Fold (aext (and (trunc x), cst)) -> (and x, cst) 4766 // if the trunc is not free. 4767 if (N0.getOpcode() == ISD::AND && 4768 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 4769 N0.getOperand(1).getOpcode() == ISD::Constant && 4770 !TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(), 4771 N0.getValueType())) { 4772 SDValue X = N0.getOperand(0).getOperand(0); 4773 if (X.getValueType().bitsLT(VT)) { 4774 X = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, X); 4775 } else if (X.getValueType().bitsGT(VT)) { 4776 X = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, X); 4777 } 4778 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 4779 Mask = Mask.zext(VT.getSizeInBits()); 4780 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 4781 X, DAG.getConstant(Mask, VT)); 4782 } 4783 4784 // fold (aext (load x)) -> (aext (truncate (extload x))) 4785 // None of the supported targets knows how to perform load and any_ext 4786 // on vectors in one instruction. We only perform this transformation on 4787 // scalars. 4788 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() && 4789 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 4790 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) { 4791 bool DoXform = true; 4792 SmallVector<SDNode*, 4> SetCCs; 4793 if (!N0.hasOneUse()) 4794 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ANY_EXTEND, SetCCs, TLI); 4795 if (DoXform) { 4796 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4797 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT, 4798 LN0->getChain(), 4799 LN0->getBasePtr(), LN0->getPointerInfo(), 4800 N0.getValueType(), 4801 LN0->isVolatile(), LN0->isNonTemporal(), 4802 LN0->getAlignment()); 4803 CombineTo(N, ExtLoad); 4804 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 4805 N0.getValueType(), ExtLoad); 4806 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 4807 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(), 4808 ISD::ANY_EXTEND); 4809 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4810 } 4811 } 4812 4813 // fold (aext (zextload x)) -> (aext (truncate (zextload x))) 4814 // fold (aext (sextload x)) -> (aext (truncate (sextload x))) 4815 // fold (aext ( extload x)) -> (aext (truncate (extload x))) 4816 if (N0.getOpcode() == ISD::LOAD && 4817 !ISD::isNON_EXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 4818 N0.hasOneUse()) { 4819 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4820 EVT MemVT = LN0->getMemoryVT(); 4821 SDValue ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), N->getDebugLoc(), 4822 VT, LN0->getChain(), LN0->getBasePtr(), 4823 LN0->getPointerInfo(), MemVT, 4824 LN0->isVolatile(), LN0->isNonTemporal(), 4825 LN0->getAlignment()); 4826 CombineTo(N, ExtLoad); 4827 CombineTo(N0.getNode(), 4828 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 4829 N0.getValueType(), ExtLoad), 4830 ExtLoad.getValue(1)); 4831 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4832 } 4833 4834 if (N0.getOpcode() == ISD::SETCC) { 4835 // aext(setcc) -> sext_in_reg(vsetcc) for vectors. 4836 // Only do this before legalize for now. 4837 if (VT.isVector() && !LegalOperations) { 4838 EVT N0VT = N0.getOperand(0).getValueType(); 4839 // We know that the # elements of the results is the same as the 4840 // # elements of the compare (and the # elements of the compare result 4841 // for that matter). Check to see that they are the same size. If so, 4842 // we know that the element size of the sext'd result matches the 4843 // element size of the compare operands. 4844 if (VT.getSizeInBits() == N0VT.getSizeInBits()) 4845 return DAG.getSetCC(N->getDebugLoc(), VT, N0.getOperand(0), 4846 N0.getOperand(1), 4847 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 4848 // If the desired elements are smaller or larger than the source 4849 // elements we can use a matching integer vector type and then 4850 // truncate/sign extend 4851 else { 4852 EVT MatchingElementType = 4853 EVT::getIntegerVT(*DAG.getContext(), 4854 N0VT.getScalarType().getSizeInBits()); 4855 EVT MatchingVectorType = 4856 EVT::getVectorVT(*DAG.getContext(), MatchingElementType, 4857 N0VT.getVectorNumElements()); 4858 SDValue VsetCC = 4859 DAG.getSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0), 4860 N0.getOperand(1), 4861 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 4862 return DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT); 4863 } 4864 } 4865 4866 // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 4867 SDValue SCC = 4868 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 4869 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 4870 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 4871 if (SCC.getNode()) 4872 return SCC; 4873 } 4874 4875 return SDValue(); 4876} 4877 4878/// GetDemandedBits - See if the specified operand can be simplified with the 4879/// knowledge that only the bits specified by Mask are used. If so, return the 4880/// simpler operand, otherwise return a null SDValue. 4881SDValue DAGCombiner::GetDemandedBits(SDValue V, const APInt &Mask) { 4882 switch (V.getOpcode()) { 4883 default: break; 4884 case ISD::Constant: { 4885 const ConstantSDNode *CV = cast<ConstantSDNode>(V.getNode()); 4886 assert(CV != 0 && "Const value should be ConstSDNode."); 4887 const APInt &CVal = CV->getAPIntValue(); 4888 APInt NewVal = CVal & Mask; 4889 if (NewVal != CVal) { 4890 return DAG.getConstant(NewVal, V.getValueType()); 4891 } 4892 break; 4893 } 4894 case ISD::OR: 4895 case ISD::XOR: 4896 // If the LHS or RHS don't contribute bits to the or, drop them. 4897 if (DAG.MaskedValueIsZero(V.getOperand(0), Mask)) 4898 return V.getOperand(1); 4899 if (DAG.MaskedValueIsZero(V.getOperand(1), Mask)) 4900 return V.getOperand(0); 4901 break; 4902 case ISD::SRL: 4903 // Only look at single-use SRLs. 4904 if (!V.getNode()->hasOneUse()) 4905 break; 4906 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(V.getOperand(1))) { 4907 // See if we can recursively simplify the LHS. 4908 unsigned Amt = RHSC->getZExtValue(); 4909 4910 // Watch out for shift count overflow though. 4911 if (Amt >= Mask.getBitWidth()) break; 4912 APInt NewMask = Mask << Amt; 4913 SDValue SimplifyLHS = GetDemandedBits(V.getOperand(0), NewMask); 4914 if (SimplifyLHS.getNode()) 4915 return DAG.getNode(ISD::SRL, V.getDebugLoc(), V.getValueType(), 4916 SimplifyLHS, V.getOperand(1)); 4917 } 4918 } 4919 return SDValue(); 4920} 4921 4922/// ReduceLoadWidth - If the result of a wider load is shifted to right of N 4923/// bits and then truncated to a narrower type and where N is a multiple 4924/// of number of bits of the narrower type, transform it to a narrower load 4925/// from address + N / num of bits of new type. If the result is to be 4926/// extended, also fold the extension to form a extending load. 4927SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) { 4928 unsigned Opc = N->getOpcode(); 4929 4930 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD; 4931 SDValue N0 = N->getOperand(0); 4932 EVT VT = N->getValueType(0); 4933 EVT ExtVT = VT; 4934 4935 // This transformation isn't valid for vector loads. 4936 if (VT.isVector()) 4937 return SDValue(); 4938 4939 // Special case: SIGN_EXTEND_INREG is basically truncating to ExtVT then 4940 // extended to VT. 4941 if (Opc == ISD::SIGN_EXTEND_INREG) { 4942 ExtType = ISD::SEXTLOAD; 4943 ExtVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 4944 } else if (Opc == ISD::SRL) { 4945 // Another special-case: SRL is basically zero-extending a narrower value. 4946 ExtType = ISD::ZEXTLOAD; 4947 N0 = SDValue(N, 0); 4948 ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 4949 if (!N01) return SDValue(); 4950 ExtVT = EVT::getIntegerVT(*DAG.getContext(), 4951 VT.getSizeInBits() - N01->getZExtValue()); 4952 } 4953 if (LegalOperations && !TLI.isLoadExtLegal(ExtType, ExtVT)) 4954 return SDValue(); 4955 4956 unsigned EVTBits = ExtVT.getSizeInBits(); 4957 4958 // Do not generate loads of non-round integer types since these can 4959 // be expensive (and would be wrong if the type is not byte sized). 4960 if (!ExtVT.isRound()) 4961 return SDValue(); 4962 4963 unsigned ShAmt = 0; 4964 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) { 4965 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 4966 ShAmt = N01->getZExtValue(); 4967 // Is the shift amount a multiple of size of VT? 4968 if ((ShAmt & (EVTBits-1)) == 0) { 4969 N0 = N0.getOperand(0); 4970 // Is the load width a multiple of size of VT? 4971 if ((N0.getValueType().getSizeInBits() & (EVTBits-1)) != 0) 4972 return SDValue(); 4973 } 4974 4975 // At this point, we must have a load or else we can't do the transform. 4976 if (!isa<LoadSDNode>(N0)) return SDValue(); 4977 4978 // If the shift amount is larger than the input type then we're not 4979 // accessing any of the loaded bytes. If the load was a zextload/extload 4980 // then the result of the shift+trunc is zero/undef (handled elsewhere). 4981 // If the load was a sextload then the result is a splat of the sign bit 4982 // of the extended byte. This is not worth optimizing for. 4983 if (ShAmt >= cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits()) 4984 return SDValue(); 4985 } 4986 } 4987 4988 // If the load is shifted left (and the result isn't shifted back right), 4989 // we can fold the truncate through the shift. 4990 unsigned ShLeftAmt = 0; 4991 if (ShAmt == 0 && N0.getOpcode() == ISD::SHL && N0.hasOneUse() && 4992 ExtVT == VT && TLI.isNarrowingProfitable(N0.getValueType(), VT)) { 4993 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 4994 ShLeftAmt = N01->getZExtValue(); 4995 N0 = N0.getOperand(0); 4996 } 4997 } 4998 4999 // If we haven't found a load, we can't narrow it. Don't transform one with 5000 // multiple uses, this would require adding a new load. 5001 if (!isa<LoadSDNode>(N0) || !N0.hasOneUse() || 5002 // Don't change the width of a volatile load. 5003 cast<LoadSDNode>(N0)->isVolatile()) 5004 return SDValue(); 5005 5006 // Verify that we are actually reducing a load width here. 5007 if (cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits() < EVTBits) 5008 return SDValue(); 5009 5010 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 5011 EVT PtrType = N0.getOperand(1).getValueType(); 5012 5013 // For big endian targets, we need to adjust the offset to the pointer to 5014 // load the correct bytes. 5015 if (TLI.isBigEndian()) { 5016 unsigned LVTStoreBits = LN0->getMemoryVT().getStoreSizeInBits(); 5017 unsigned EVTStoreBits = ExtVT.getStoreSizeInBits(); 5018 ShAmt = LVTStoreBits - EVTStoreBits - ShAmt; 5019 } 5020 5021 uint64_t PtrOff = ShAmt / 8; 5022 unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff); 5023 SDValue NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(), 5024 PtrType, LN0->getBasePtr(), 5025 DAG.getConstant(PtrOff, PtrType)); 5026 AddToWorkList(NewPtr.getNode()); 5027 5028 SDValue Load; 5029 if (ExtType == ISD::NON_EXTLOAD) 5030 Load = DAG.getLoad(VT, N0.getDebugLoc(), LN0->getChain(), NewPtr, 5031 LN0->getPointerInfo().getWithOffset(PtrOff), 5032 LN0->isVolatile(), LN0->isNonTemporal(), 5033 LN0->isInvariant(), NewAlign); 5034 else 5035 Load = DAG.getExtLoad(ExtType, N0.getDebugLoc(), VT, LN0->getChain(),NewPtr, 5036 LN0->getPointerInfo().getWithOffset(PtrOff), 5037 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(), 5038 NewAlign); 5039 5040 // Replace the old load's chain with the new load's chain. 5041 WorkListRemover DeadNodes(*this); 5042 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1)); 5043 5044 // Shift the result left, if we've swallowed a left shift. 5045 SDValue Result = Load; 5046 if (ShLeftAmt != 0) { 5047 EVT ShImmTy = getShiftAmountTy(Result.getValueType()); 5048 if (!isUIntN(ShImmTy.getSizeInBits(), ShLeftAmt)) 5049 ShImmTy = VT; 5050 Result = DAG.getNode(ISD::SHL, N0.getDebugLoc(), VT, 5051 Result, DAG.getConstant(ShLeftAmt, ShImmTy)); 5052 } 5053 5054 // Return the new loaded value. 5055 return Result; 5056} 5057 5058SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) { 5059 SDValue N0 = N->getOperand(0); 5060 SDValue N1 = N->getOperand(1); 5061 EVT VT = N->getValueType(0); 5062 EVT EVT = cast<VTSDNode>(N1)->getVT(); 5063 unsigned VTBits = VT.getScalarType().getSizeInBits(); 5064 unsigned EVTBits = EVT.getScalarType().getSizeInBits(); 5065 5066 // fold (sext_in_reg c1) -> c1 5067 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF) 5068 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, N0, N1); 5069 5070 // If the input is already sign extended, just drop the extension. 5071 if (DAG.ComputeNumSignBits(N0) >= VTBits-EVTBits+1) 5072 return N0; 5073 5074 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2 5075 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 5076 EVT.bitsLT(cast<VTSDNode>(N0.getOperand(1))->getVT())) { 5077 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, 5078 N0.getOperand(0), N1); 5079 } 5080 5081 // fold (sext_in_reg (sext x)) -> (sext x) 5082 // fold (sext_in_reg (aext x)) -> (sext x) 5083 // if x is small enough. 5084 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) { 5085 SDValue N00 = N0.getOperand(0); 5086 if (N00.getValueType().getScalarType().getSizeInBits() <= EVTBits && 5087 (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND, VT))) 5088 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N00, N1); 5089 } 5090 5091 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero. 5092 if (DAG.MaskedValueIsZero(N0, APInt::getBitsSet(VTBits, EVTBits-1, EVTBits))) 5093 return DAG.getZeroExtendInReg(N0, N->getDebugLoc(), EVT); 5094 5095 // fold operands of sext_in_reg based on knowledge that the top bits are not 5096 // demanded. 5097 if (SimplifyDemandedBits(SDValue(N, 0))) 5098 return SDValue(N, 0); 5099 5100 // fold (sext_in_reg (load x)) -> (smaller sextload x) 5101 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits)) 5102 SDValue NarrowLoad = ReduceLoadWidth(N); 5103 if (NarrowLoad.getNode()) 5104 return NarrowLoad; 5105 5106 // fold (sext_in_reg (srl X, 24), i8) -> (sra X, 24) 5107 // fold (sext_in_reg (srl X, 23), i8) -> (sra X, 23) iff possible. 5108 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above. 5109 if (N0.getOpcode() == ISD::SRL) { 5110 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 5111 if (ShAmt->getZExtValue()+EVTBits <= VTBits) { 5112 // We can turn this into an SRA iff the input to the SRL is already sign 5113 // extended enough. 5114 unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0)); 5115 if (VTBits-(ShAmt->getZExtValue()+EVTBits) < InSignBits) 5116 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, 5117 N0.getOperand(0), N0.getOperand(1)); 5118 } 5119 } 5120 5121 // fold (sext_inreg (extload x)) -> (sextload x) 5122 if (ISD::isEXTLoad(N0.getNode()) && 5123 ISD::isUNINDEXEDLoad(N0.getNode()) && 5124 EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 5125 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 5126 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) { 5127 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 5128 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 5129 LN0->getChain(), 5130 LN0->getBasePtr(), LN0->getPointerInfo(), 5131 EVT, 5132 LN0->isVolatile(), LN0->isNonTemporal(), 5133 LN0->getAlignment()); 5134 CombineTo(N, ExtLoad); 5135 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 5136 return SDValue(N, 0); // Return N so it doesn't get rechecked! 5137 } 5138 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use 5139 if (ISD::isZEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 5140 N0.hasOneUse() && 5141 EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 5142 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 5143 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) { 5144 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 5145 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 5146 LN0->getChain(), 5147 LN0->getBasePtr(), LN0->getPointerInfo(), 5148 EVT, 5149 LN0->isVolatile(), LN0->isNonTemporal(), 5150 LN0->getAlignment()); 5151 CombineTo(N, ExtLoad); 5152 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 5153 return SDValue(N, 0); // Return N so it doesn't get rechecked! 5154 } 5155 5156 // Form (sext_inreg (bswap >> 16)) or (sext_inreg (rotl (bswap) 16)) 5157 if (EVTBits <= 16 && N0.getOpcode() == ISD::OR) { 5158 SDValue BSwap = MatchBSwapHWordLow(N0.getNode(), N0.getOperand(0), 5159 N0.getOperand(1), false); 5160 if (BSwap.getNode() != 0) 5161 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, 5162 BSwap, N1); 5163 } 5164 5165 return SDValue(); 5166} 5167 5168SDValue DAGCombiner::visitTRUNCATE(SDNode *N) { 5169 SDValue N0 = N->getOperand(0); 5170 EVT VT = N->getValueType(0); 5171 bool isLE = TLI.isLittleEndian(); 5172 5173 // noop truncate 5174 if (N0.getValueType() == N->getValueType(0)) 5175 return N0; 5176 // fold (truncate c1) -> c1 5177 if (isa<ConstantSDNode>(N0)) 5178 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0); 5179 // fold (truncate (truncate x)) -> (truncate x) 5180 if (N0.getOpcode() == ISD::TRUNCATE) 5181 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0)); 5182 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x 5183 if (N0.getOpcode() == ISD::ZERO_EXTEND || 5184 N0.getOpcode() == ISD::SIGN_EXTEND || 5185 N0.getOpcode() == ISD::ANY_EXTEND) { 5186 if (N0.getOperand(0).getValueType().bitsLT(VT)) 5187 // if the source is smaller than the dest, we still need an extend 5188 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, 5189 N0.getOperand(0)); 5190 else if (N0.getOperand(0).getValueType().bitsGT(VT)) 5191 // if the source is larger than the dest, than we just need the truncate 5192 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0)); 5193 else 5194 // if the source and dest are the same type, we can drop both the extend 5195 // and the truncate. 5196 return N0.getOperand(0); 5197 } 5198 5199 // Fold extract-and-trunc into a narrow extract. For example: 5200 // i64 x = EXTRACT_VECTOR_ELT(v2i64 val, i32 1) 5201 // i32 y = TRUNCATE(i64 x) 5202 // -- becomes -- 5203 // v16i8 b = BITCAST (v2i64 val) 5204 // i8 x = EXTRACT_VECTOR_ELT(v16i8 b, i32 8) 5205 // 5206 // Note: We only run this optimization after type legalization (which often 5207 // creates this pattern) and before operation legalization after which 5208 // we need to be more careful about the vector instructions that we generate. 5209 if (N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT && 5210 LegalTypes && !LegalOperations && N0->hasOneUse()) { 5211 5212 EVT VecTy = N0.getOperand(0).getValueType(); 5213 EVT ExTy = N0.getValueType(); 5214 EVT TrTy = N->getValueType(0); 5215 5216 unsigned NumElem = VecTy.getVectorNumElements(); 5217 unsigned SizeRatio = ExTy.getSizeInBits()/TrTy.getSizeInBits(); 5218 5219 EVT NVT = EVT::getVectorVT(*DAG.getContext(), TrTy, SizeRatio * NumElem); 5220 assert(NVT.getSizeInBits() == VecTy.getSizeInBits() && "Invalid Size"); 5221 5222 SDValue EltNo = N0->getOperand(1); 5223 if (isa<ConstantSDNode>(EltNo) && isTypeLegal(NVT)) { 5224 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 5225 EVT IndexTy = N0->getOperand(1).getValueType(); 5226 int Index = isLE ? (Elt*SizeRatio) : (Elt*SizeRatio + (SizeRatio-1)); 5227 5228 SDValue V = DAG.getNode(ISD::BITCAST, N->getDebugLoc(), 5229 NVT, N0.getOperand(0)); 5230 5231 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, 5232 N->getDebugLoc(), TrTy, V, 5233 DAG.getConstant(Index, IndexTy)); 5234 } 5235 } 5236 5237 // See if we can simplify the input to this truncate through knowledge that 5238 // only the low bits are being used. 5239 // For example "trunc (or (shl x, 8), y)" // -> trunc y 5240 // Currently we only perform this optimization on scalars because vectors 5241 // may have different active low bits. 5242 if (!VT.isVector()) { 5243 SDValue Shorter = 5244 GetDemandedBits(N0, APInt::getLowBitsSet(N0.getValueSizeInBits(), 5245 VT.getSizeInBits())); 5246 if (Shorter.getNode()) 5247 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Shorter); 5248 } 5249 // fold (truncate (load x)) -> (smaller load x) 5250 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits)) 5251 if (!LegalTypes || TLI.isTypeDesirableForOp(N0.getOpcode(), VT)) { 5252 SDValue Reduced = ReduceLoadWidth(N); 5253 if (Reduced.getNode()) 5254 return Reduced; 5255 } 5256 5257 // Simplify the operands using demanded-bits information. 5258 if (!VT.isVector() && 5259 SimplifyDemandedBits(SDValue(N, 0))) 5260 return SDValue(N, 0); 5261 5262 return SDValue(); 5263} 5264 5265static SDNode *getBuildPairElt(SDNode *N, unsigned i) { 5266 SDValue Elt = N->getOperand(i); 5267 if (Elt.getOpcode() != ISD::MERGE_VALUES) 5268 return Elt.getNode(); 5269 return Elt.getOperand(Elt.getResNo()).getNode(); 5270} 5271 5272/// CombineConsecutiveLoads - build_pair (load, load) -> load 5273/// if load locations are consecutive. 5274SDValue DAGCombiner::CombineConsecutiveLoads(SDNode *N, EVT VT) { 5275 assert(N->getOpcode() == ISD::BUILD_PAIR); 5276 5277 LoadSDNode *LD1 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 0)); 5278 LoadSDNode *LD2 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 1)); 5279 if (!LD1 || !LD2 || !ISD::isNON_EXTLoad(LD1) || !LD1->hasOneUse() || 5280 LD1->getPointerInfo().getAddrSpace() != 5281 LD2->getPointerInfo().getAddrSpace()) 5282 return SDValue(); 5283 EVT LD1VT = LD1->getValueType(0); 5284 5285 if (ISD::isNON_EXTLoad(LD2) && 5286 LD2->hasOneUse() && 5287 // If both are volatile this would reduce the number of volatile loads. 5288 // If one is volatile it might be ok, but play conservative and bail out. 5289 !LD1->isVolatile() && 5290 !LD2->isVolatile() && 5291 DAG.isConsecutiveLoad(LD2, LD1, LD1VT.getSizeInBits()/8, 1)) { 5292 unsigned Align = LD1->getAlignment(); 5293 unsigned NewAlign = TLI.getTargetData()-> 5294 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext())); 5295 5296 if (NewAlign <= Align && 5297 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) 5298 return DAG.getLoad(VT, N->getDebugLoc(), LD1->getChain(), 5299 LD1->getBasePtr(), LD1->getPointerInfo(), 5300 false, false, false, Align); 5301 } 5302 5303 return SDValue(); 5304} 5305 5306SDValue DAGCombiner::visitBITCAST(SDNode *N) { 5307 SDValue N0 = N->getOperand(0); 5308 EVT VT = N->getValueType(0); 5309 5310 // If the input is a BUILD_VECTOR with all constant elements, fold this now. 5311 // Only do this before legalize, since afterward the target may be depending 5312 // on the bitconvert. 5313 // First check to see if this is all constant. 5314 if (!LegalTypes && 5315 N0.getOpcode() == ISD::BUILD_VECTOR && N0.getNode()->hasOneUse() && 5316 VT.isVector()) { 5317 bool isSimple = true; 5318 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i) 5319 if (N0.getOperand(i).getOpcode() != ISD::UNDEF && 5320 N0.getOperand(i).getOpcode() != ISD::Constant && 5321 N0.getOperand(i).getOpcode() != ISD::ConstantFP) { 5322 isSimple = false; 5323 break; 5324 } 5325 5326 EVT DestEltVT = N->getValueType(0).getVectorElementType(); 5327 assert(!DestEltVT.isVector() && 5328 "Element type of vector ValueType must not be vector!"); 5329 if (isSimple) 5330 return ConstantFoldBITCASTofBUILD_VECTOR(N0.getNode(), DestEltVT); 5331 } 5332 5333 // If the input is a constant, let getNode fold it. 5334 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) { 5335 SDValue Res = DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, N0); 5336 if (Res.getNode() != N) { 5337 if (!LegalOperations || 5338 TLI.isOperationLegal(Res.getNode()->getOpcode(), VT)) 5339 return Res; 5340 5341 // Folding it resulted in an illegal node, and it's too late to 5342 // do that. Clean up the old node and forego the transformation. 5343 // Ideally this won't happen very often, because instcombine 5344 // and the earlier dagcombine runs (where illegal nodes are 5345 // permitted) should have folded most of them already. 5346 DAG.DeleteNode(Res.getNode()); 5347 } 5348 } 5349 5350 // (conv (conv x, t1), t2) -> (conv x, t2) 5351 if (N0.getOpcode() == ISD::BITCAST) 5352 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, 5353 N0.getOperand(0)); 5354 5355 // fold (conv (load x)) -> (load (conv*)x) 5356 // If the resultant load doesn't need a higher alignment than the original! 5357 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() && 5358 // Do not change the width of a volatile load. 5359 !cast<LoadSDNode>(N0)->isVolatile() && 5360 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) { 5361 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 5362 unsigned Align = TLI.getTargetData()-> 5363 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext())); 5364 unsigned OrigAlign = LN0->getAlignment(); 5365 5366 if (Align <= OrigAlign) { 5367 SDValue Load = DAG.getLoad(VT, N->getDebugLoc(), LN0->getChain(), 5368 LN0->getBasePtr(), LN0->getPointerInfo(), 5369 LN0->isVolatile(), LN0->isNonTemporal(), 5370 LN0->isInvariant(), OrigAlign); 5371 AddToWorkList(N); 5372 CombineTo(N0.getNode(), 5373 DAG.getNode(ISD::BITCAST, N0.getDebugLoc(), 5374 N0.getValueType(), Load), 5375 Load.getValue(1)); 5376 return Load; 5377 } 5378 } 5379 5380 // fold (bitconvert (fneg x)) -> (xor (bitconvert x), signbit) 5381 // fold (bitconvert (fabs x)) -> (and (bitconvert x), (not signbit)) 5382 // This often reduces constant pool loads. 5383 if (((N0.getOpcode() == ISD::FNEG && !TLI.isFNegFree(VT)) || 5384 (N0.getOpcode() == ISD::FABS && !TLI.isFAbsFree(VT))) && 5385 N0.getNode()->hasOneUse() && VT.isInteger() && !VT.isVector()) { 5386 SDValue NewConv = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(), VT, 5387 N0.getOperand(0)); 5388 AddToWorkList(NewConv.getNode()); 5389 5390 APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); 5391 if (N0.getOpcode() == ISD::FNEG) 5392 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, 5393 NewConv, DAG.getConstant(SignBit, VT)); 5394 assert(N0.getOpcode() == ISD::FABS); 5395 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 5396 NewConv, DAG.getConstant(~SignBit, VT)); 5397 } 5398 5399 // fold (bitconvert (fcopysign cst, x)) -> 5400 // (or (and (bitconvert x), sign), (and cst, (not sign))) 5401 // Note that we don't handle (copysign x, cst) because this can always be 5402 // folded to an fneg or fabs. 5403 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse() && 5404 isa<ConstantFPSDNode>(N0.getOperand(0)) && 5405 VT.isInteger() && !VT.isVector()) { 5406 unsigned OrigXWidth = N0.getOperand(1).getValueType().getSizeInBits(); 5407 EVT IntXVT = EVT::getIntegerVT(*DAG.getContext(), OrigXWidth); 5408 if (isTypeLegal(IntXVT)) { 5409 SDValue X = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(), 5410 IntXVT, N0.getOperand(1)); 5411 AddToWorkList(X.getNode()); 5412 5413 // If X has a different width than the result/lhs, sext it or truncate it. 5414 unsigned VTWidth = VT.getSizeInBits(); 5415 if (OrigXWidth < VTWidth) { 5416 X = DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, X); 5417 AddToWorkList(X.getNode()); 5418 } else if (OrigXWidth > VTWidth) { 5419 // To get the sign bit in the right place, we have to shift it right 5420 // before truncating. 5421 X = DAG.getNode(ISD::SRL, X.getDebugLoc(), 5422 X.getValueType(), X, 5423 DAG.getConstant(OrigXWidth-VTWidth, X.getValueType())); 5424 AddToWorkList(X.getNode()); 5425 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X); 5426 AddToWorkList(X.getNode()); 5427 } 5428 5429 APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); 5430 X = DAG.getNode(ISD::AND, X.getDebugLoc(), VT, 5431 X, DAG.getConstant(SignBit, VT)); 5432 AddToWorkList(X.getNode()); 5433 5434 SDValue Cst = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(), 5435 VT, N0.getOperand(0)); 5436 Cst = DAG.getNode(ISD::AND, Cst.getDebugLoc(), VT, 5437 Cst, DAG.getConstant(~SignBit, VT)); 5438 AddToWorkList(Cst.getNode()); 5439 5440 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, X, Cst); 5441 } 5442 } 5443 5444 // bitconvert(build_pair(ld, ld)) -> ld iff load locations are consecutive. 5445 if (N0.getOpcode() == ISD::BUILD_PAIR) { 5446 SDValue CombineLD = CombineConsecutiveLoads(N0.getNode(), VT); 5447 if (CombineLD.getNode()) 5448 return CombineLD; 5449 } 5450 5451 return SDValue(); 5452} 5453 5454SDValue DAGCombiner::visitBUILD_PAIR(SDNode *N) { 5455 EVT VT = N->getValueType(0); 5456 return CombineConsecutiveLoads(N, VT); 5457} 5458 5459/// ConstantFoldBITCASTofBUILD_VECTOR - We know that BV is a build_vector 5460/// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the 5461/// destination element value type. 5462SDValue DAGCombiner:: 5463ConstantFoldBITCASTofBUILD_VECTOR(SDNode *BV, EVT DstEltVT) { 5464 EVT SrcEltVT = BV->getValueType(0).getVectorElementType(); 5465 5466 // If this is already the right type, we're done. 5467 if (SrcEltVT == DstEltVT) return SDValue(BV, 0); 5468 5469 unsigned SrcBitSize = SrcEltVT.getSizeInBits(); 5470 unsigned DstBitSize = DstEltVT.getSizeInBits(); 5471 5472 // If this is a conversion of N elements of one type to N elements of another 5473 // type, convert each element. This handles FP<->INT cases. 5474 if (SrcBitSize == DstBitSize) { 5475 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, 5476 BV->getValueType(0).getVectorNumElements()); 5477 5478 // Due to the FP element handling below calling this routine recursively, 5479 // we can end up with a scalar-to-vector node here. 5480 if (BV->getOpcode() == ISD::SCALAR_TO_VECTOR) 5481 return DAG.getNode(ISD::SCALAR_TO_VECTOR, BV->getDebugLoc(), VT, 5482 DAG.getNode(ISD::BITCAST, BV->getDebugLoc(), 5483 DstEltVT, BV->getOperand(0))); 5484 5485 SmallVector<SDValue, 8> Ops; 5486 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 5487 SDValue Op = BV->getOperand(i); 5488 // If the vector element type is not legal, the BUILD_VECTOR operands 5489 // are promoted and implicitly truncated. Make that explicit here. 5490 if (Op.getValueType() != SrcEltVT) 5491 Op = DAG.getNode(ISD::TRUNCATE, BV->getDebugLoc(), SrcEltVT, Op); 5492 Ops.push_back(DAG.getNode(ISD::BITCAST, BV->getDebugLoc(), 5493 DstEltVT, Op)); 5494 AddToWorkList(Ops.back().getNode()); 5495 } 5496 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 5497 &Ops[0], Ops.size()); 5498 } 5499 5500 // Otherwise, we're growing or shrinking the elements. To avoid having to 5501 // handle annoying details of growing/shrinking FP values, we convert them to 5502 // int first. 5503 if (SrcEltVT.isFloatingPoint()) { 5504 // Convert the input float vector to a int vector where the elements are the 5505 // same sizes. 5506 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!"); 5507 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), SrcEltVT.getSizeInBits()); 5508 BV = ConstantFoldBITCASTofBUILD_VECTOR(BV, IntVT).getNode(); 5509 SrcEltVT = IntVT; 5510 } 5511 5512 // Now we know the input is an integer vector. If the output is a FP type, 5513 // convert to integer first, then to FP of the right size. 5514 if (DstEltVT.isFloatingPoint()) { 5515 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!"); 5516 EVT TmpVT = EVT::getIntegerVT(*DAG.getContext(), DstEltVT.getSizeInBits()); 5517 SDNode *Tmp = ConstantFoldBITCASTofBUILD_VECTOR(BV, TmpVT).getNode(); 5518 5519 // Next, convert to FP elements of the same size. 5520 return ConstantFoldBITCASTofBUILD_VECTOR(Tmp, DstEltVT); 5521 } 5522 5523 // Okay, we know the src/dst types are both integers of differing types. 5524 // Handling growing first. 5525 assert(SrcEltVT.isInteger() && DstEltVT.isInteger()); 5526 if (SrcBitSize < DstBitSize) { 5527 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize; 5528 5529 SmallVector<SDValue, 8> Ops; 5530 for (unsigned i = 0, e = BV->getNumOperands(); i != e; 5531 i += NumInputsPerOutput) { 5532 bool isLE = TLI.isLittleEndian(); 5533 APInt NewBits = APInt(DstBitSize, 0); 5534 bool EltIsUndef = true; 5535 for (unsigned j = 0; j != NumInputsPerOutput; ++j) { 5536 // Shift the previously computed bits over. 5537 NewBits <<= SrcBitSize; 5538 SDValue Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j)); 5539 if (Op.getOpcode() == ISD::UNDEF) continue; 5540 EltIsUndef = false; 5541 5542 NewBits |= cast<ConstantSDNode>(Op)->getAPIntValue(). 5543 zextOrTrunc(SrcBitSize).zext(DstBitSize); 5544 } 5545 5546 if (EltIsUndef) 5547 Ops.push_back(DAG.getUNDEF(DstEltVT)); 5548 else 5549 Ops.push_back(DAG.getConstant(NewBits, DstEltVT)); 5550 } 5551 5552 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, Ops.size()); 5553 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 5554 &Ops[0], Ops.size()); 5555 } 5556 5557 // Finally, this must be the case where we are shrinking elements: each input 5558 // turns into multiple outputs. 5559 bool isS2V = ISD::isScalarToVector(BV); 5560 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize; 5561 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, 5562 NumOutputsPerInput*BV->getNumOperands()); 5563 SmallVector<SDValue, 8> Ops; 5564 5565 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 5566 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) { 5567 for (unsigned j = 0; j != NumOutputsPerInput; ++j) 5568 Ops.push_back(DAG.getUNDEF(DstEltVT)); 5569 continue; 5570 } 5571 5572 APInt OpVal = cast<ConstantSDNode>(BV->getOperand(i))-> 5573 getAPIntValue().zextOrTrunc(SrcBitSize); 5574 5575 for (unsigned j = 0; j != NumOutputsPerInput; ++j) { 5576 APInt ThisVal = OpVal.trunc(DstBitSize); 5577 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT)); 5578 if (isS2V && i == 0 && j == 0 && ThisVal.zext(SrcBitSize) == OpVal) 5579 // Simply turn this into a SCALAR_TO_VECTOR of the new type. 5580 return DAG.getNode(ISD::SCALAR_TO_VECTOR, BV->getDebugLoc(), VT, 5581 Ops[0]); 5582 OpVal = OpVal.lshr(DstBitSize); 5583 } 5584 5585 // For big endian targets, swap the order of the pieces of each element. 5586 if (TLI.isBigEndian()) 5587 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end()); 5588 } 5589 5590 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 5591 &Ops[0], Ops.size()); 5592} 5593 5594SDValue DAGCombiner::visitFADD(SDNode *N) { 5595 SDValue N0 = N->getOperand(0); 5596 SDValue N1 = N->getOperand(1); 5597 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5598 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 5599 EVT VT = N->getValueType(0); 5600 5601 // fold vector ops 5602 if (VT.isVector()) { 5603 SDValue FoldedVOp = SimplifyVBinOp(N); 5604 if (FoldedVOp.getNode()) return FoldedVOp; 5605 } 5606 5607 // fold (fadd c1, c2) -> c1 + c2 5608 if (N0CFP && N1CFP && VT != MVT::ppcf128) 5609 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N1); 5610 // canonicalize constant to RHS 5611 if (N0CFP && !N1CFP) 5612 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N1, N0); 5613 // fold (fadd A, 0) -> A 5614 if (DAG.getTarget().Options.UnsafeFPMath && N1CFP && 5615 N1CFP->getValueAPF().isZero()) 5616 return N0; 5617 // fold (fadd A, (fneg B)) -> (fsub A, B) 5618 if ((!LegalOperations || TLI.isOperationLegalOrCustom(ISD::FSUB, VT)) && 5619 isNegatibleForFree(N1, LegalOperations, TLI, &DAG.getTarget().Options) == 2) 5620 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, 5621 GetNegatedExpression(N1, DAG, LegalOperations)); 5622 // fold (fadd (fneg A), B) -> (fsub B, A) 5623 if ((!LegalOperations || TLI.isOperationLegalOrCustom(ISD::FSUB, VT)) && 5624 isNegatibleForFree(N0, LegalOperations, TLI, &DAG.getTarget().Options) == 2) 5625 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N1, 5626 GetNegatedExpression(N0, DAG, LegalOperations)); 5627 5628 // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2)) 5629 if (DAG.getTarget().Options.UnsafeFPMath && N1CFP && 5630 N0.getOpcode() == ISD::FADD && N0.getNode()->hasOneUse() && 5631 isa<ConstantFPSDNode>(N0.getOperand(1))) 5632 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0.getOperand(0), 5633 DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, 5634 N0.getOperand(1), N1)); 5635 5636 // FADD -> FMA combines: 5637 if ((DAG.getTarget().Options.AllowExcessFPPrecision || 5638 DAG.getTarget().Options.UnsafeFPMath) && 5639 DAG.getTarget().getTargetLowering()->isFMAFasterThanMulAndAdd(VT) && 5640 TLI.isOperationLegal(ISD::FMA, VT)) { 5641 5642 // fold (fadd (fmul x, y), z) -> (fma x, y, z) 5643 if (N0.getOpcode() == ISD::FMUL && N0->hasOneUse()) { 5644 return DAG.getNode(ISD::FMA, N->getDebugLoc(), VT, 5645 N0.getOperand(0), N0.getOperand(1), N1); 5646 } 5647 5648 // fold (fadd x, (fmul y, z)) -> (fma x, y, z) 5649 // Note: Commutes FADD operands. 5650 if (N1.getOpcode() == ISD::FMUL && N1->hasOneUse()) { 5651 return DAG.getNode(ISD::FMA, N->getDebugLoc(), VT, 5652 N1.getOperand(0), N1.getOperand(1), N0); 5653 } 5654 } 5655 5656 return SDValue(); 5657} 5658 5659SDValue DAGCombiner::visitFSUB(SDNode *N) { 5660 SDValue N0 = N->getOperand(0); 5661 SDValue N1 = N->getOperand(1); 5662 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5663 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 5664 EVT VT = N->getValueType(0); 5665 5666 // fold vector ops 5667 if (VT.isVector()) { 5668 SDValue FoldedVOp = SimplifyVBinOp(N); 5669 if (FoldedVOp.getNode()) return FoldedVOp; 5670 } 5671 5672 // fold (fsub c1, c2) -> c1-c2 5673 if (N0CFP && N1CFP && VT != MVT::ppcf128) 5674 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, N1); 5675 // fold (fsub A, 0) -> A 5676 if (DAG.getTarget().Options.UnsafeFPMath && 5677 N1CFP && N1CFP->getValueAPF().isZero()) 5678 return N0; 5679 // fold (fsub 0, B) -> -B 5680 if (DAG.getTarget().Options.UnsafeFPMath && 5681 N0CFP && N0CFP->getValueAPF().isZero()) { 5682 if (isNegatibleForFree(N1, LegalOperations, TLI, &DAG.getTarget().Options)) 5683 return GetNegatedExpression(N1, DAG, LegalOperations); 5684 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 5685 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N1); 5686 } 5687 // fold (fsub A, (fneg B)) -> (fadd A, B) 5688 if (isNegatibleForFree(N1, LegalOperations, TLI, &DAG.getTarget().Options)) 5689 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, 5690 GetNegatedExpression(N1, DAG, LegalOperations)); 5691 5692 // If 'unsafe math' is enabled, fold 5693 // (fsub x, x) -> 0.0 & 5694 // (fsub x, (fadd x, y)) -> (fneg y) & 5695 // (fsub x, (fadd y, x)) -> (fneg y) 5696 if (DAG.getTarget().Options.UnsafeFPMath) { 5697 if (N0 == N1) 5698 return DAG.getConstantFP(0.0f, VT); 5699 5700 if (N1.getOpcode() == ISD::FADD) { 5701 SDValue N10 = N1->getOperand(0); 5702 SDValue N11 = N1->getOperand(1); 5703 5704 if (N10 == N0 && isNegatibleForFree(N11, LegalOperations, TLI, 5705 &DAG.getTarget().Options)) 5706 return GetNegatedExpression(N11, DAG, LegalOperations); 5707 else if (N11 == N0 && isNegatibleForFree(N10, LegalOperations, TLI, 5708 &DAG.getTarget().Options)) 5709 return GetNegatedExpression(N10, DAG, LegalOperations); 5710 } 5711 } 5712 5713 // FSUB -> FMA combines: 5714 if ((DAG.getTarget().Options.AllowExcessFPPrecision || 5715 DAG.getTarget().Options.UnsafeFPMath) && 5716 DAG.getTarget().getTargetLowering()->isFMAFasterThanMulAndAdd(VT) && 5717 TLI.isOperationLegal(ISD::FMA, VT)) { 5718 5719 // fold (fsub (fmul x, y), z) -> (fma x, y, (fneg z)) 5720 if (N0.getOpcode() == ISD::FMUL && N0->hasOneUse()) { 5721 return DAG.getNode(ISD::FMA, N->getDebugLoc(), VT, 5722 N0.getOperand(0), N0.getOperand(1), 5723 DAG.getNode(ISD::FNEG, N1->getDebugLoc(), VT, N1)); 5724 } 5725 5726 // fold (fsub x, (fmul y, z)) -> (fma (fneg y), z, x) 5727 // Note: Commutes FSUB operands. 5728 if (N1.getOpcode() == ISD::FMUL && N1->hasOneUse()) { 5729 return DAG.getNode(ISD::FMA, N->getDebugLoc(), VT, 5730 DAG.getNode(ISD::FNEG, N1->getDebugLoc(), VT, 5731 N1.getOperand(0)), 5732 N1.getOperand(1), N0); 5733 } 5734 } 5735 5736 return SDValue(); 5737} 5738 5739SDValue DAGCombiner::visitFMUL(SDNode *N) { 5740 SDValue N0 = N->getOperand(0); 5741 SDValue N1 = N->getOperand(1); 5742 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5743 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 5744 EVT VT = N->getValueType(0); 5745 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 5746 5747 // fold vector ops 5748 if (VT.isVector()) { 5749 SDValue FoldedVOp = SimplifyVBinOp(N); 5750 if (FoldedVOp.getNode()) return FoldedVOp; 5751 } 5752 5753 // fold (fmul c1, c2) -> c1*c2 5754 if (N0CFP && N1CFP && VT != MVT::ppcf128) 5755 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0, N1); 5756 // canonicalize constant to RHS 5757 if (N0CFP && !N1CFP) 5758 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N1, N0); 5759 // fold (fmul A, 0) -> 0 5760 if (DAG.getTarget().Options.UnsafeFPMath && 5761 N1CFP && N1CFP->getValueAPF().isZero()) 5762 return N1; 5763 // fold (fmul A, 0) -> 0, vector edition. 5764 if (DAG.getTarget().Options.UnsafeFPMath && 5765 ISD::isBuildVectorAllZeros(N1.getNode())) 5766 return N1; 5767 // fold (fmul A, 1.0) -> A 5768 if (N1CFP && N1CFP->isExactlyValue(1.0)) 5769 return N0; 5770 // fold (fmul X, 2.0) -> (fadd X, X) 5771 if (N1CFP && N1CFP->isExactlyValue(+2.0)) 5772 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N0); 5773 // fold (fmul X, -1.0) -> (fneg X) 5774 if (N1CFP && N1CFP->isExactlyValue(-1.0)) 5775 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 5776 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N0); 5777 5778 // fold (fmul (fneg X), (fneg Y)) -> (fmul X, Y) 5779 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations, TLI, 5780 &DAG.getTarget().Options)) { 5781 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations, TLI, 5782 &DAG.getTarget().Options)) { 5783 // Both can be negated for free, check to see if at least one is cheaper 5784 // negated. 5785 if (LHSNeg == 2 || RHSNeg == 2) 5786 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 5787 GetNegatedExpression(N0, DAG, LegalOperations), 5788 GetNegatedExpression(N1, DAG, LegalOperations)); 5789 } 5790 } 5791 5792 // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2)) 5793 if (DAG.getTarget().Options.UnsafeFPMath && 5794 N1CFP && N0.getOpcode() == ISD::FMUL && 5795 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 5796 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0.getOperand(0), 5797 DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 5798 N0.getOperand(1), N1)); 5799 5800 return SDValue(); 5801} 5802 5803SDValue DAGCombiner::visitFMA(SDNode *N) { 5804 SDValue N0 = N->getOperand(0); 5805 SDValue N1 = N->getOperand(1); 5806 SDValue N2 = N->getOperand(2); 5807 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5808 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 5809 EVT VT = N->getValueType(0); 5810 5811 if (N0CFP && N0CFP->isExactlyValue(1.0)) 5812 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N1, N2); 5813 if (N1CFP && N1CFP->isExactlyValue(1.0)) 5814 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N2); 5815 5816 // Canonicalize (fma c, x, y) -> (fma x, c, y) 5817 if (N0CFP && !N1CFP) 5818 return DAG.getNode(ISD::FMA, N->getDebugLoc(), VT, N1, N0, N2); 5819 5820 return SDValue(); 5821} 5822 5823SDValue DAGCombiner::visitFDIV(SDNode *N) { 5824 SDValue N0 = N->getOperand(0); 5825 SDValue N1 = N->getOperand(1); 5826 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5827 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 5828 EVT VT = N->getValueType(0); 5829 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 5830 5831 // fold vector ops 5832 if (VT.isVector()) { 5833 SDValue FoldedVOp = SimplifyVBinOp(N); 5834 if (FoldedVOp.getNode()) return FoldedVOp; 5835 } 5836 5837 // fold (fdiv c1, c2) -> c1/c2 5838 if (N0CFP && N1CFP && VT != MVT::ppcf128) 5839 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, N0, N1); 5840 5841 // fold (fdiv X, c2) -> fmul X, 1/c2 if losing precision is acceptable. 5842 if (N1CFP && VT != MVT::ppcf128 && DAG.getTarget().Options.UnsafeFPMath) { 5843 // Compute the reciprocal 1.0 / c2. 5844 APFloat N1APF = N1CFP->getValueAPF(); 5845 APFloat Recip(N1APF.getSemantics(), 1); // 1.0 5846 APFloat::opStatus st = Recip.divide(N1APF, APFloat::rmNearestTiesToEven); 5847 // Only do the transform if the reciprocal is a legal fp immediate that 5848 // isn't too nasty (eg NaN, denormal, ...). 5849 if ((st == APFloat::opOK || st == APFloat::opInexact) && // Not too nasty 5850 (!LegalOperations || 5851 // FIXME: custom lowering of ConstantFP might fail (see e.g. ARM 5852 // backend)... we should handle this gracefully after Legalize. 5853 // TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT) || 5854 TLI.isOperationLegal(llvm::ISD::ConstantFP, VT) || 5855 TLI.isFPImmLegal(Recip, VT))) 5856 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0, 5857 DAG.getConstantFP(Recip, VT)); 5858 } 5859 5860 // (fdiv (fneg X), (fneg Y)) -> (fdiv X, Y) 5861 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations, TLI, 5862 &DAG.getTarget().Options)) { 5863 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations, TLI, 5864 &DAG.getTarget().Options)) { 5865 // Both can be negated for free, check to see if at least one is cheaper 5866 // negated. 5867 if (LHSNeg == 2 || RHSNeg == 2) 5868 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, 5869 GetNegatedExpression(N0, DAG, LegalOperations), 5870 GetNegatedExpression(N1, DAG, LegalOperations)); 5871 } 5872 } 5873 5874 return SDValue(); 5875} 5876 5877SDValue DAGCombiner::visitFREM(SDNode *N) { 5878 SDValue N0 = N->getOperand(0); 5879 SDValue N1 = N->getOperand(1); 5880 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5881 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 5882 EVT VT = N->getValueType(0); 5883 5884 // fold (frem c1, c2) -> fmod(c1,c2) 5885 if (N0CFP && N1CFP && VT != MVT::ppcf128) 5886 return DAG.getNode(ISD::FREM, N->getDebugLoc(), VT, N0, N1); 5887 5888 return SDValue(); 5889} 5890 5891SDValue DAGCombiner::visitFCOPYSIGN(SDNode *N) { 5892 SDValue N0 = N->getOperand(0); 5893 SDValue N1 = N->getOperand(1); 5894 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5895 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 5896 EVT VT = N->getValueType(0); 5897 5898 if (N0CFP && N1CFP && VT != MVT::ppcf128) // Constant fold 5899 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, N0, N1); 5900 5901 if (N1CFP) { 5902 const APFloat& V = N1CFP->getValueAPF(); 5903 // copysign(x, c1) -> fabs(x) iff ispos(c1) 5904 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1) 5905 if (!V.isNegative()) { 5906 if (!LegalOperations || TLI.isOperationLegal(ISD::FABS, VT)) 5907 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 5908 } else { 5909 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 5910 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, 5911 DAG.getNode(ISD::FABS, N0.getDebugLoc(), VT, N0)); 5912 } 5913 } 5914 5915 // copysign(fabs(x), y) -> copysign(x, y) 5916 // copysign(fneg(x), y) -> copysign(x, y) 5917 // copysign(copysign(x,z), y) -> copysign(x, y) 5918 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG || 5919 N0.getOpcode() == ISD::FCOPYSIGN) 5920 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 5921 N0.getOperand(0), N1); 5922 5923 // copysign(x, abs(y)) -> abs(x) 5924 if (N1.getOpcode() == ISD::FABS) 5925 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 5926 5927 // copysign(x, copysign(y,z)) -> copysign(x, z) 5928 if (N1.getOpcode() == ISD::FCOPYSIGN) 5929 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 5930 N0, N1.getOperand(1)); 5931 5932 // copysign(x, fp_extend(y)) -> copysign(x, y) 5933 // copysign(x, fp_round(y)) -> copysign(x, y) 5934 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND) 5935 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 5936 N0, N1.getOperand(0)); 5937 5938 return SDValue(); 5939} 5940 5941SDValue DAGCombiner::visitSINT_TO_FP(SDNode *N) { 5942 SDValue N0 = N->getOperand(0); 5943 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 5944 EVT VT = N->getValueType(0); 5945 EVT OpVT = N0.getValueType(); 5946 5947 // fold (sint_to_fp c1) -> c1fp 5948 if (N0C && OpVT != MVT::ppcf128 && 5949 // ...but only if the target supports immediate floating-point values 5950 (!LegalOperations || 5951 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT))) 5952 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0); 5953 5954 // If the input is a legal type, and SINT_TO_FP is not legal on this target, 5955 // but UINT_TO_FP is legal on this target, try to convert. 5956 if (!TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT) && 5957 TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT)) { 5958 // If the sign bit is known to be zero, we can change this to UINT_TO_FP. 5959 if (DAG.SignBitIsZero(N0)) 5960 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0); 5961 } 5962 5963 return SDValue(); 5964} 5965 5966SDValue DAGCombiner::visitUINT_TO_FP(SDNode *N) { 5967 SDValue N0 = N->getOperand(0); 5968 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 5969 EVT VT = N->getValueType(0); 5970 EVT OpVT = N0.getValueType(); 5971 5972 // fold (uint_to_fp c1) -> c1fp 5973 if (N0C && OpVT != MVT::ppcf128 && 5974 // ...but only if the target supports immediate floating-point values 5975 (!LegalOperations || 5976 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT))) 5977 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0); 5978 5979 // If the input is a legal type, and UINT_TO_FP is not legal on this target, 5980 // but SINT_TO_FP is legal on this target, try to convert. 5981 if (!TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT) && 5982 TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT)) { 5983 // If the sign bit is known to be zero, we can change this to SINT_TO_FP. 5984 if (DAG.SignBitIsZero(N0)) 5985 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0); 5986 } 5987 5988 return SDValue(); 5989} 5990 5991SDValue DAGCombiner::visitFP_TO_SINT(SDNode *N) { 5992 SDValue N0 = N->getOperand(0); 5993 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5994 EVT VT = N->getValueType(0); 5995 5996 // fold (fp_to_sint c1fp) -> c1 5997 if (N0CFP) 5998 return DAG.getNode(ISD::FP_TO_SINT, N->getDebugLoc(), VT, N0); 5999 6000 return SDValue(); 6001} 6002 6003SDValue DAGCombiner::visitFP_TO_UINT(SDNode *N) { 6004 SDValue N0 = N->getOperand(0); 6005 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6006 EVT VT = N->getValueType(0); 6007 6008 // fold (fp_to_uint c1fp) -> c1 6009 if (N0CFP && VT != MVT::ppcf128) 6010 return DAG.getNode(ISD::FP_TO_UINT, N->getDebugLoc(), VT, N0); 6011 6012 return SDValue(); 6013} 6014 6015SDValue DAGCombiner::visitFP_ROUND(SDNode *N) { 6016 SDValue N0 = N->getOperand(0); 6017 SDValue N1 = N->getOperand(1); 6018 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6019 EVT VT = N->getValueType(0); 6020 6021 // fold (fp_round c1fp) -> c1fp 6022 if (N0CFP && N0.getValueType() != MVT::ppcf128) 6023 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0, N1); 6024 6025 // fold (fp_round (fp_extend x)) -> x 6026 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType()) 6027 return N0.getOperand(0); 6028 6029 // fold (fp_round (fp_round x)) -> (fp_round x) 6030 if (N0.getOpcode() == ISD::FP_ROUND) { 6031 // This is a value preserving truncation if both round's are. 6032 bool IsTrunc = N->getConstantOperandVal(1) == 1 && 6033 N0.getNode()->getConstantOperandVal(1) == 1; 6034 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0.getOperand(0), 6035 DAG.getIntPtrConstant(IsTrunc)); 6036 } 6037 6038 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y) 6039 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse()) { 6040 SDValue Tmp = DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(), VT, 6041 N0.getOperand(0), N1); 6042 AddToWorkList(Tmp.getNode()); 6043 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 6044 Tmp, N0.getOperand(1)); 6045 } 6046 6047 return SDValue(); 6048} 6049 6050SDValue DAGCombiner::visitFP_ROUND_INREG(SDNode *N) { 6051 SDValue N0 = N->getOperand(0); 6052 EVT VT = N->getValueType(0); 6053 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 6054 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6055 6056 // fold (fp_round_inreg c1fp) -> c1fp 6057 if (N0CFP && isTypeLegal(EVT)) { 6058 SDValue Round = DAG.getConstantFP(*N0CFP->getConstantFPValue(), EVT); 6059 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, Round); 6060 } 6061 6062 return SDValue(); 6063} 6064 6065SDValue DAGCombiner::visitFP_EXTEND(SDNode *N) { 6066 SDValue N0 = N->getOperand(0); 6067 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6068 EVT VT = N->getValueType(0); 6069 6070 // If this is fp_round(fpextend), don't fold it, allow ourselves to be folded. 6071 if (N->hasOneUse() && 6072 N->use_begin()->getOpcode() == ISD::FP_ROUND) 6073 return SDValue(); 6074 6075 // fold (fp_extend c1fp) -> c1fp 6076 if (N0CFP && VT != MVT::ppcf128) 6077 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, N0); 6078 6079 // Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't affect the 6080 // value of X. 6081 if (N0.getOpcode() == ISD::FP_ROUND 6082 && N0.getNode()->getConstantOperandVal(1) == 1) { 6083 SDValue In = N0.getOperand(0); 6084 if (In.getValueType() == VT) return In; 6085 if (VT.bitsLT(In.getValueType())) 6086 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, 6087 In, N0.getOperand(1)); 6088 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, In); 6089 } 6090 6091 // fold (fpext (load x)) -> (fpext (fptrunc (extload x))) 6092 if (ISD::isNON_EXTLoad(N0.getNode()) && N0.hasOneUse() && 6093 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 6094 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) { 6095 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 6096 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT, 6097 LN0->getChain(), 6098 LN0->getBasePtr(), LN0->getPointerInfo(), 6099 N0.getValueType(), 6100 LN0->isVolatile(), LN0->isNonTemporal(), 6101 LN0->getAlignment()); 6102 CombineTo(N, ExtLoad); 6103 CombineTo(N0.getNode(), 6104 DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(), 6105 N0.getValueType(), ExtLoad, DAG.getIntPtrConstant(1)), 6106 ExtLoad.getValue(1)); 6107 return SDValue(N, 0); // Return N so it doesn't get rechecked! 6108 } 6109 6110 return SDValue(); 6111} 6112 6113SDValue DAGCombiner::visitFNEG(SDNode *N) { 6114 SDValue N0 = N->getOperand(0); 6115 EVT VT = N->getValueType(0); 6116 6117 if (isNegatibleForFree(N0, LegalOperations, DAG.getTargetLoweringInfo(), 6118 &DAG.getTarget().Options)) 6119 return GetNegatedExpression(N0, DAG, LegalOperations); 6120 6121 // Transform fneg(bitconvert(x)) -> bitconvert(x^sign) to avoid loading 6122 // constant pool values. 6123 if (!TLI.isFNegFree(VT) && N0.getOpcode() == ISD::BITCAST && 6124 !VT.isVector() && 6125 N0.getNode()->hasOneUse() && 6126 N0.getOperand(0).getValueType().isInteger()) { 6127 SDValue Int = N0.getOperand(0); 6128 EVT IntVT = Int.getValueType(); 6129 if (IntVT.isInteger() && !IntVT.isVector()) { 6130 Int = DAG.getNode(ISD::XOR, N0.getDebugLoc(), IntVT, Int, 6131 DAG.getConstant(APInt::getSignBit(IntVT.getSizeInBits()), IntVT)); 6132 AddToWorkList(Int.getNode()); 6133 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), 6134 VT, Int); 6135 } 6136 } 6137 6138 return SDValue(); 6139} 6140 6141SDValue DAGCombiner::visitFABS(SDNode *N) { 6142 SDValue N0 = N->getOperand(0); 6143 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6144 EVT VT = N->getValueType(0); 6145 6146 // fold (fabs c1) -> fabs(c1) 6147 if (N0CFP && VT != MVT::ppcf128) 6148 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 6149 // fold (fabs (fabs x)) -> (fabs x) 6150 if (N0.getOpcode() == ISD::FABS) 6151 return N->getOperand(0); 6152 // fold (fabs (fneg x)) -> (fabs x) 6153 // fold (fabs (fcopysign x, y)) -> (fabs x) 6154 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN) 6155 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0.getOperand(0)); 6156 6157 // Transform fabs(bitconvert(x)) -> bitconvert(x&~sign) to avoid loading 6158 // constant pool values. 6159 if (!TLI.isFAbsFree(VT) && 6160 N0.getOpcode() == ISD::BITCAST && N0.getNode()->hasOneUse() && 6161 N0.getOperand(0).getValueType().isInteger() && 6162 !N0.getOperand(0).getValueType().isVector()) { 6163 SDValue Int = N0.getOperand(0); 6164 EVT IntVT = Int.getValueType(); 6165 if (IntVT.isInteger() && !IntVT.isVector()) { 6166 Int = DAG.getNode(ISD::AND, N0.getDebugLoc(), IntVT, Int, 6167 DAG.getConstant(~APInt::getSignBit(IntVT.getSizeInBits()), IntVT)); 6168 AddToWorkList(Int.getNode()); 6169 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), 6170 N->getValueType(0), Int); 6171 } 6172 } 6173 6174 return SDValue(); 6175} 6176 6177SDValue DAGCombiner::visitBRCOND(SDNode *N) { 6178 SDValue Chain = N->getOperand(0); 6179 SDValue N1 = N->getOperand(1); 6180 SDValue N2 = N->getOperand(2); 6181 6182 // If N is a constant we could fold this into a fallthrough or unconditional 6183 // branch. However that doesn't happen very often in normal code, because 6184 // Instcombine/SimplifyCFG should have handled the available opportunities. 6185 // If we did this folding here, it would be necessary to update the 6186 // MachineBasicBlock CFG, which is awkward. 6187 6188 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal 6189 // on the target. 6190 if (N1.getOpcode() == ISD::SETCC && 6191 TLI.isOperationLegalOrCustom(ISD::BR_CC, MVT::Other)) { 6192 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other, 6193 Chain, N1.getOperand(2), 6194 N1.getOperand(0), N1.getOperand(1), N2); 6195 } 6196 6197 if ((N1.hasOneUse() && N1.getOpcode() == ISD::SRL) || 6198 ((N1.getOpcode() == ISD::TRUNCATE && N1.hasOneUse()) && 6199 (N1.getOperand(0).hasOneUse() && 6200 N1.getOperand(0).getOpcode() == ISD::SRL))) { 6201 SDNode *Trunc = 0; 6202 if (N1.getOpcode() == ISD::TRUNCATE) { 6203 // Look pass the truncate. 6204 Trunc = N1.getNode(); 6205 N1 = N1.getOperand(0); 6206 } 6207 6208 // Match this pattern so that we can generate simpler code: 6209 // 6210 // %a = ... 6211 // %b = and i32 %a, 2 6212 // %c = srl i32 %b, 1 6213 // brcond i32 %c ... 6214 // 6215 // into 6216 // 6217 // %a = ... 6218 // %b = and i32 %a, 2 6219 // %c = setcc eq %b, 0 6220 // brcond %c ... 6221 // 6222 // This applies only when the AND constant value has one bit set and the 6223 // SRL constant is equal to the log2 of the AND constant. The back-end is 6224 // smart enough to convert the result into a TEST/JMP sequence. 6225 SDValue Op0 = N1.getOperand(0); 6226 SDValue Op1 = N1.getOperand(1); 6227 6228 if (Op0.getOpcode() == ISD::AND && 6229 Op1.getOpcode() == ISD::Constant) { 6230 SDValue AndOp1 = Op0.getOperand(1); 6231 6232 if (AndOp1.getOpcode() == ISD::Constant) { 6233 const APInt &AndConst = cast<ConstantSDNode>(AndOp1)->getAPIntValue(); 6234 6235 if (AndConst.isPowerOf2() && 6236 cast<ConstantSDNode>(Op1)->getAPIntValue()==AndConst.logBase2()) { 6237 SDValue SetCC = 6238 DAG.getSetCC(N->getDebugLoc(), 6239 TLI.getSetCCResultType(Op0.getValueType()), 6240 Op0, DAG.getConstant(0, Op0.getValueType()), 6241 ISD::SETNE); 6242 6243 SDValue NewBRCond = DAG.getNode(ISD::BRCOND, N->getDebugLoc(), 6244 MVT::Other, Chain, SetCC, N2); 6245 // Don't add the new BRCond into the worklist or else SimplifySelectCC 6246 // will convert it back to (X & C1) >> C2. 6247 CombineTo(N, NewBRCond, false); 6248 // Truncate is dead. 6249 if (Trunc) { 6250 removeFromWorkList(Trunc); 6251 DAG.DeleteNode(Trunc); 6252 } 6253 // Replace the uses of SRL with SETCC 6254 WorkListRemover DeadNodes(*this); 6255 DAG.ReplaceAllUsesOfValueWith(N1, SetCC); 6256 removeFromWorkList(N1.getNode()); 6257 DAG.DeleteNode(N1.getNode()); 6258 return SDValue(N, 0); // Return N so it doesn't get rechecked! 6259 } 6260 } 6261 } 6262 6263 if (Trunc) 6264 // Restore N1 if the above transformation doesn't match. 6265 N1 = N->getOperand(1); 6266 } 6267 6268 // Transform br(xor(x, y)) -> br(x != y) 6269 // Transform br(xor(xor(x,y), 1)) -> br (x == y) 6270 if (N1.hasOneUse() && N1.getOpcode() == ISD::XOR) { 6271 SDNode *TheXor = N1.getNode(); 6272 SDValue Op0 = TheXor->getOperand(0); 6273 SDValue Op1 = TheXor->getOperand(1); 6274 if (Op0.getOpcode() == Op1.getOpcode()) { 6275 // Avoid missing important xor optimizations. 6276 SDValue Tmp = visitXOR(TheXor); 6277 if (Tmp.getNode() && Tmp.getNode() != TheXor) { 6278 DEBUG(dbgs() << "\nReplacing.8 "; 6279 TheXor->dump(&DAG); 6280 dbgs() << "\nWith: "; 6281 Tmp.getNode()->dump(&DAG); 6282 dbgs() << '\n'); 6283 WorkListRemover DeadNodes(*this); 6284 DAG.ReplaceAllUsesOfValueWith(N1, Tmp); 6285 removeFromWorkList(TheXor); 6286 DAG.DeleteNode(TheXor); 6287 return DAG.getNode(ISD::BRCOND, N->getDebugLoc(), 6288 MVT::Other, Chain, Tmp, N2); 6289 } 6290 } 6291 6292 if (Op0.getOpcode() != ISD::SETCC && Op1.getOpcode() != ISD::SETCC) { 6293 bool Equal = false; 6294 if (ConstantSDNode *RHSCI = dyn_cast<ConstantSDNode>(Op0)) 6295 if (RHSCI->getAPIntValue() == 1 && Op0.hasOneUse() && 6296 Op0.getOpcode() == ISD::XOR) { 6297 TheXor = Op0.getNode(); 6298 Equal = true; 6299 } 6300 6301 EVT SetCCVT = N1.getValueType(); 6302 if (LegalTypes) 6303 SetCCVT = TLI.getSetCCResultType(SetCCVT); 6304 SDValue SetCC = DAG.getSetCC(TheXor->getDebugLoc(), 6305 SetCCVT, 6306 Op0, Op1, 6307 Equal ? ISD::SETEQ : ISD::SETNE); 6308 // Replace the uses of XOR with SETCC 6309 WorkListRemover DeadNodes(*this); 6310 DAG.ReplaceAllUsesOfValueWith(N1, SetCC); 6311 removeFromWorkList(N1.getNode()); 6312 DAG.DeleteNode(N1.getNode()); 6313 return DAG.getNode(ISD::BRCOND, N->getDebugLoc(), 6314 MVT::Other, Chain, SetCC, N2); 6315 } 6316 } 6317 6318 return SDValue(); 6319} 6320 6321// Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB. 6322// 6323SDValue DAGCombiner::visitBR_CC(SDNode *N) { 6324 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1)); 6325 SDValue CondLHS = N->getOperand(2), CondRHS = N->getOperand(3); 6326 6327 // If N is a constant we could fold this into a fallthrough or unconditional 6328 // branch. However that doesn't happen very often in normal code, because 6329 // Instcombine/SimplifyCFG should have handled the available opportunities. 6330 // If we did this folding here, it would be necessary to update the 6331 // MachineBasicBlock CFG, which is awkward. 6332 6333 // Use SimplifySetCC to simplify SETCC's. 6334 SDValue Simp = SimplifySetCC(TLI.getSetCCResultType(CondLHS.getValueType()), 6335 CondLHS, CondRHS, CC->get(), N->getDebugLoc(), 6336 false); 6337 if (Simp.getNode()) AddToWorkList(Simp.getNode()); 6338 6339 // fold to a simpler setcc 6340 if (Simp.getNode() && Simp.getOpcode() == ISD::SETCC) 6341 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other, 6342 N->getOperand(0), Simp.getOperand(2), 6343 Simp.getOperand(0), Simp.getOperand(1), 6344 N->getOperand(4)); 6345 6346 return SDValue(); 6347} 6348 6349/// canFoldInAddressingMode - Return true if 'Use' is a load or a store that 6350/// uses N as its base pointer and that N may be folded in the load / store 6351/// addressing mode. 6352static bool canFoldInAddressingMode(SDNode *N, SDNode *Use, 6353 SelectionDAG &DAG, 6354 const TargetLowering &TLI) { 6355 EVT VT; 6356 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Use)) { 6357 if (LD->isIndexed() || LD->getBasePtr().getNode() != N) 6358 return false; 6359 VT = Use->getValueType(0); 6360 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(Use)) { 6361 if (ST->isIndexed() || ST->getBasePtr().getNode() != N) 6362 return false; 6363 VT = ST->getValue().getValueType(); 6364 } else 6365 return false; 6366 6367 TargetLowering::AddrMode AM; 6368 if (N->getOpcode() == ISD::ADD) { 6369 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1)); 6370 if (Offset) 6371 // [reg +/- imm] 6372 AM.BaseOffs = Offset->getSExtValue(); 6373 else 6374 // [reg +/- reg] 6375 AM.Scale = 1; 6376 } else if (N->getOpcode() == ISD::SUB) { 6377 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1)); 6378 if (Offset) 6379 // [reg +/- imm] 6380 AM.BaseOffs = -Offset->getSExtValue(); 6381 else 6382 // [reg +/- reg] 6383 AM.Scale = 1; 6384 } else 6385 return false; 6386 6387 return TLI.isLegalAddressingMode(AM, VT.getTypeForEVT(*DAG.getContext())); 6388} 6389 6390/// CombineToPreIndexedLoadStore - Try turning a load / store into a 6391/// pre-indexed load / store when the base pointer is an add or subtract 6392/// and it has other uses besides the load / store. After the 6393/// transformation, the new indexed load / store has effectively folded 6394/// the add / subtract in and all of its other uses are redirected to the 6395/// new load / store. 6396bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) { 6397 if (Level < AfterLegalizeDAG) 6398 return false; 6399 6400 bool isLoad = true; 6401 SDValue Ptr; 6402 EVT VT; 6403 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 6404 if (LD->isIndexed()) 6405 return false; 6406 VT = LD->getMemoryVT(); 6407 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) && 6408 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT)) 6409 return false; 6410 Ptr = LD->getBasePtr(); 6411 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 6412 if (ST->isIndexed()) 6413 return false; 6414 VT = ST->getMemoryVT(); 6415 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) && 6416 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT)) 6417 return false; 6418 Ptr = ST->getBasePtr(); 6419 isLoad = false; 6420 } else { 6421 return false; 6422 } 6423 6424 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail 6425 // out. There is no reason to make this a preinc/predec. 6426 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) || 6427 Ptr.getNode()->hasOneUse()) 6428 return false; 6429 6430 // Ask the target to do addressing mode selection. 6431 SDValue BasePtr; 6432 SDValue Offset; 6433 ISD::MemIndexedMode AM = ISD::UNINDEXED; 6434 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG)) 6435 return false; 6436 // Don't create a indexed load / store with zero offset. 6437 if (isa<ConstantSDNode>(Offset) && 6438 cast<ConstantSDNode>(Offset)->isNullValue()) 6439 return false; 6440 6441 // Try turning it into a pre-indexed load / store except when: 6442 // 1) The new base ptr is a frame index. 6443 // 2) If N is a store and the new base ptr is either the same as or is a 6444 // predecessor of the value being stored. 6445 // 3) Another use of old base ptr is a predecessor of N. If ptr is folded 6446 // that would create a cycle. 6447 // 4) All uses are load / store ops that use it as old base ptr. 6448 6449 // Check #1. Preinc'ing a frame index would require copying the stack pointer 6450 // (plus the implicit offset) to a register to preinc anyway. 6451 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr)) 6452 return false; 6453 6454 // Check #2. 6455 if (!isLoad) { 6456 SDValue Val = cast<StoreSDNode>(N)->getValue(); 6457 if (Val == BasePtr || BasePtr.getNode()->isPredecessorOf(Val.getNode())) 6458 return false; 6459 } 6460 6461 // Now check for #3 and #4. 6462 bool RealUse = false; 6463 6464 // Caches for hasPredecessorHelper 6465 SmallPtrSet<const SDNode *, 32> Visited; 6466 SmallVector<const SDNode *, 16> Worklist; 6467 6468 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(), 6469 E = Ptr.getNode()->use_end(); I != E; ++I) { 6470 SDNode *Use = *I; 6471 if (Use == N) 6472 continue; 6473 if (N->hasPredecessorHelper(Use, Visited, Worklist)) 6474 return false; 6475 6476 // If Ptr may be folded in addressing mode of other use, then it's 6477 // not profitable to do this transformation. 6478 if (!canFoldInAddressingMode(Ptr.getNode(), Use, DAG, TLI)) 6479 RealUse = true; 6480 } 6481 6482 if (!RealUse) 6483 return false; 6484 6485 SDValue Result; 6486 if (isLoad) 6487 Result = DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(), 6488 BasePtr, Offset, AM); 6489 else 6490 Result = DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(), 6491 BasePtr, Offset, AM); 6492 ++PreIndexedNodes; 6493 ++NodesCombined; 6494 DEBUG(dbgs() << "\nReplacing.4 "; 6495 N->dump(&DAG); 6496 dbgs() << "\nWith: "; 6497 Result.getNode()->dump(&DAG); 6498 dbgs() << '\n'); 6499 WorkListRemover DeadNodes(*this); 6500 if (isLoad) { 6501 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0)); 6502 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2)); 6503 } else { 6504 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1)); 6505 } 6506 6507 // Finally, since the node is now dead, remove it from the graph. 6508 DAG.DeleteNode(N); 6509 6510 // Replace the uses of Ptr with uses of the updated base value. 6511 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0)); 6512 removeFromWorkList(Ptr.getNode()); 6513 DAG.DeleteNode(Ptr.getNode()); 6514 6515 return true; 6516} 6517 6518/// CombineToPostIndexedLoadStore - Try to combine a load / store with a 6519/// add / sub of the base pointer node into a post-indexed load / store. 6520/// The transformation folded the add / subtract into the new indexed 6521/// load / store effectively and all of its uses are redirected to the 6522/// new load / store. 6523bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) { 6524 if (Level < AfterLegalizeDAG) 6525 return false; 6526 6527 bool isLoad = true; 6528 SDValue Ptr; 6529 EVT VT; 6530 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 6531 if (LD->isIndexed()) 6532 return false; 6533 VT = LD->getMemoryVT(); 6534 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) && 6535 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT)) 6536 return false; 6537 Ptr = LD->getBasePtr(); 6538 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 6539 if (ST->isIndexed()) 6540 return false; 6541 VT = ST->getMemoryVT(); 6542 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) && 6543 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT)) 6544 return false; 6545 Ptr = ST->getBasePtr(); 6546 isLoad = false; 6547 } else { 6548 return false; 6549 } 6550 6551 if (Ptr.getNode()->hasOneUse()) 6552 return false; 6553 6554 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(), 6555 E = Ptr.getNode()->use_end(); I != E; ++I) { 6556 SDNode *Op = *I; 6557 if (Op == N || 6558 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB)) 6559 continue; 6560 6561 SDValue BasePtr; 6562 SDValue Offset; 6563 ISD::MemIndexedMode AM = ISD::UNINDEXED; 6564 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) { 6565 // Don't create a indexed load / store with zero offset. 6566 if (isa<ConstantSDNode>(Offset) && 6567 cast<ConstantSDNode>(Offset)->isNullValue()) 6568 continue; 6569 6570 // Try turning it into a post-indexed load / store except when 6571 // 1) All uses are load / store ops that use it as base ptr (and 6572 // it may be folded as addressing mmode). 6573 // 2) Op must be independent of N, i.e. Op is neither a predecessor 6574 // nor a successor of N. Otherwise, if Op is folded that would 6575 // create a cycle. 6576 6577 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr)) 6578 continue; 6579 6580 // Check for #1. 6581 bool TryNext = false; 6582 for (SDNode::use_iterator II = BasePtr.getNode()->use_begin(), 6583 EE = BasePtr.getNode()->use_end(); II != EE; ++II) { 6584 SDNode *Use = *II; 6585 if (Use == Ptr.getNode()) 6586 continue; 6587 6588 // If all the uses are load / store addresses, then don't do the 6589 // transformation. 6590 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){ 6591 bool RealUse = false; 6592 for (SDNode::use_iterator III = Use->use_begin(), 6593 EEE = Use->use_end(); III != EEE; ++III) { 6594 SDNode *UseUse = *III; 6595 if (!canFoldInAddressingMode(Use, UseUse, DAG, TLI)) 6596 RealUse = true; 6597 } 6598 6599 if (!RealUse) { 6600 TryNext = true; 6601 break; 6602 } 6603 } 6604 } 6605 6606 if (TryNext) 6607 continue; 6608 6609 // Check for #2 6610 if (!Op->isPredecessorOf(N) && !N->isPredecessorOf(Op)) { 6611 SDValue Result = isLoad 6612 ? DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(), 6613 BasePtr, Offset, AM) 6614 : DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(), 6615 BasePtr, Offset, AM); 6616 ++PostIndexedNodes; 6617 ++NodesCombined; 6618 DEBUG(dbgs() << "\nReplacing.5 "; 6619 N->dump(&DAG); 6620 dbgs() << "\nWith: "; 6621 Result.getNode()->dump(&DAG); 6622 dbgs() << '\n'); 6623 WorkListRemover DeadNodes(*this); 6624 if (isLoad) { 6625 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0)); 6626 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2)); 6627 } else { 6628 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1)); 6629 } 6630 6631 // Finally, since the node is now dead, remove it from the graph. 6632 DAG.DeleteNode(N); 6633 6634 // Replace the uses of Use with uses of the updated base value. 6635 DAG.ReplaceAllUsesOfValueWith(SDValue(Op, 0), 6636 Result.getValue(isLoad ? 1 : 0)); 6637 removeFromWorkList(Op); 6638 DAG.DeleteNode(Op); 6639 return true; 6640 } 6641 } 6642 } 6643 6644 return false; 6645} 6646 6647SDValue DAGCombiner::visitLOAD(SDNode *N) { 6648 LoadSDNode *LD = cast<LoadSDNode>(N); 6649 SDValue Chain = LD->getChain(); 6650 SDValue Ptr = LD->getBasePtr(); 6651 6652 // If load is not volatile and there are no uses of the loaded value (and 6653 // the updated indexed value in case of indexed loads), change uses of the 6654 // chain value into uses of the chain input (i.e. delete the dead load). 6655 if (!LD->isVolatile()) { 6656 if (N->getValueType(1) == MVT::Other) { 6657 // Unindexed loads. 6658 if (!N->hasAnyUseOfValue(0)) { 6659 // It's not safe to use the two value CombineTo variant here. e.g. 6660 // v1, chain2 = load chain1, loc 6661 // v2, chain3 = load chain2, loc 6662 // v3 = add v2, c 6663 // Now we replace use of chain2 with chain1. This makes the second load 6664 // isomorphic to the one we are deleting, and thus makes this load live. 6665 DEBUG(dbgs() << "\nReplacing.6 "; 6666 N->dump(&DAG); 6667 dbgs() << "\nWith chain: "; 6668 Chain.getNode()->dump(&DAG); 6669 dbgs() << "\n"); 6670 WorkListRemover DeadNodes(*this); 6671 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Chain); 6672 6673 if (N->use_empty()) { 6674 removeFromWorkList(N); 6675 DAG.DeleteNode(N); 6676 } 6677 6678 return SDValue(N, 0); // Return N so it doesn't get rechecked! 6679 } 6680 } else { 6681 // Indexed loads. 6682 assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?"); 6683 if (!N->hasAnyUseOfValue(0) && !N->hasAnyUseOfValue(1)) { 6684 SDValue Undef = DAG.getUNDEF(N->getValueType(0)); 6685 DEBUG(dbgs() << "\nReplacing.7 "; 6686 N->dump(&DAG); 6687 dbgs() << "\nWith: "; 6688 Undef.getNode()->dump(&DAG); 6689 dbgs() << " and 2 other values\n"); 6690 WorkListRemover DeadNodes(*this); 6691 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Undef); 6692 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), 6693 DAG.getUNDEF(N->getValueType(1))); 6694 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 2), Chain); 6695 removeFromWorkList(N); 6696 DAG.DeleteNode(N); 6697 return SDValue(N, 0); // Return N so it doesn't get rechecked! 6698 } 6699 } 6700 } 6701 6702 // If this load is directly stored, replace the load value with the stored 6703 // value. 6704 // TODO: Handle store large -> read small portion. 6705 // TODO: Handle TRUNCSTORE/LOADEXT 6706 if (ISD::isNormalLoad(N) && !LD->isVolatile()) { 6707 if (ISD::isNON_TRUNCStore(Chain.getNode())) { 6708 StoreSDNode *PrevST = cast<StoreSDNode>(Chain); 6709 if (PrevST->getBasePtr() == Ptr && 6710 PrevST->getValue().getValueType() == N->getValueType(0)) 6711 return CombineTo(N, Chain.getOperand(1), Chain); 6712 } 6713 } 6714 6715 // Try to infer better alignment information than the load already has. 6716 if (OptLevel != CodeGenOpt::None && LD->isUnindexed()) { 6717 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) { 6718 if (Align > LD->getAlignment()) 6719 return DAG.getExtLoad(LD->getExtensionType(), N->getDebugLoc(), 6720 LD->getValueType(0), 6721 Chain, Ptr, LD->getPointerInfo(), 6722 LD->getMemoryVT(), 6723 LD->isVolatile(), LD->isNonTemporal(), Align); 6724 } 6725 } 6726 6727 if (CombinerAA) { 6728 // Walk up chain skipping non-aliasing memory nodes. 6729 SDValue BetterChain = FindBetterChain(N, Chain); 6730 6731 // If there is a better chain. 6732 if (Chain != BetterChain) { 6733 SDValue ReplLoad; 6734 6735 // Replace the chain to void dependency. 6736 if (LD->getExtensionType() == ISD::NON_EXTLOAD) { 6737 ReplLoad = DAG.getLoad(N->getValueType(0), LD->getDebugLoc(), 6738 BetterChain, Ptr, LD->getPointerInfo(), 6739 LD->isVolatile(), LD->isNonTemporal(), 6740 LD->isInvariant(), LD->getAlignment()); 6741 } else { 6742 ReplLoad = DAG.getExtLoad(LD->getExtensionType(), LD->getDebugLoc(), 6743 LD->getValueType(0), 6744 BetterChain, Ptr, LD->getPointerInfo(), 6745 LD->getMemoryVT(), 6746 LD->isVolatile(), 6747 LD->isNonTemporal(), 6748 LD->getAlignment()); 6749 } 6750 6751 // Create token factor to keep old chain connected. 6752 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 6753 MVT::Other, Chain, ReplLoad.getValue(1)); 6754 6755 // Make sure the new and old chains are cleaned up. 6756 AddToWorkList(Token.getNode()); 6757 6758 // Replace uses with load result and token factor. Don't add users 6759 // to work list. 6760 return CombineTo(N, ReplLoad.getValue(0), Token, false); 6761 } 6762 } 6763 6764 // Try transforming N to an indexed load. 6765 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 6766 return SDValue(N, 0); 6767 6768 return SDValue(); 6769} 6770 6771/// CheckForMaskedLoad - Check to see if V is (and load (ptr), imm), where the 6772/// load is having specific bytes cleared out. If so, return the byte size 6773/// being masked out and the shift amount. 6774static std::pair<unsigned, unsigned> 6775CheckForMaskedLoad(SDValue V, SDValue Ptr, SDValue Chain) { 6776 std::pair<unsigned, unsigned> Result(0, 0); 6777 6778 // Check for the structure we're looking for. 6779 if (V->getOpcode() != ISD::AND || 6780 !isa<ConstantSDNode>(V->getOperand(1)) || 6781 !ISD::isNormalLoad(V->getOperand(0).getNode())) 6782 return Result; 6783 6784 // Check the chain and pointer. 6785 LoadSDNode *LD = cast<LoadSDNode>(V->getOperand(0)); 6786 if (LD->getBasePtr() != Ptr) return Result; // Not from same pointer. 6787 6788 // The store should be chained directly to the load or be an operand of a 6789 // tokenfactor. 6790 if (LD == Chain.getNode()) 6791 ; // ok. 6792 else if (Chain->getOpcode() != ISD::TokenFactor) 6793 return Result; // Fail. 6794 else { 6795 bool isOk = false; 6796 for (unsigned i = 0, e = Chain->getNumOperands(); i != e; ++i) 6797 if (Chain->getOperand(i).getNode() == LD) { 6798 isOk = true; 6799 break; 6800 } 6801 if (!isOk) return Result; 6802 } 6803 6804 // This only handles simple types. 6805 if (V.getValueType() != MVT::i16 && 6806 V.getValueType() != MVT::i32 && 6807 V.getValueType() != MVT::i64) 6808 return Result; 6809 6810 // Check the constant mask. Invert it so that the bits being masked out are 6811 // 0 and the bits being kept are 1. Use getSExtValue so that leading bits 6812 // follow the sign bit for uniformity. 6813 uint64_t NotMask = ~cast<ConstantSDNode>(V->getOperand(1))->getSExtValue(); 6814 unsigned NotMaskLZ = CountLeadingZeros_64(NotMask); 6815 if (NotMaskLZ & 7) return Result; // Must be multiple of a byte. 6816 unsigned NotMaskTZ = CountTrailingZeros_64(NotMask); 6817 if (NotMaskTZ & 7) return Result; // Must be multiple of a byte. 6818 if (NotMaskLZ == 64) return Result; // All zero mask. 6819 6820 // See if we have a continuous run of bits. If so, we have 0*1+0* 6821 if (CountTrailingOnes_64(NotMask >> NotMaskTZ)+NotMaskTZ+NotMaskLZ != 64) 6822 return Result; 6823 6824 // Adjust NotMaskLZ down to be from the actual size of the int instead of i64. 6825 if (V.getValueType() != MVT::i64 && NotMaskLZ) 6826 NotMaskLZ -= 64-V.getValueSizeInBits(); 6827 6828 unsigned MaskedBytes = (V.getValueSizeInBits()-NotMaskLZ-NotMaskTZ)/8; 6829 switch (MaskedBytes) { 6830 case 1: 6831 case 2: 6832 case 4: break; 6833 default: return Result; // All one mask, or 5-byte mask. 6834 } 6835 6836 // Verify that the first bit starts at a multiple of mask so that the access 6837 // is aligned the same as the access width. 6838 if (NotMaskTZ && NotMaskTZ/8 % MaskedBytes) return Result; 6839 6840 Result.first = MaskedBytes; 6841 Result.second = NotMaskTZ/8; 6842 return Result; 6843} 6844 6845 6846/// ShrinkLoadReplaceStoreWithStore - Check to see if IVal is something that 6847/// provides a value as specified by MaskInfo. If so, replace the specified 6848/// store with a narrower store of truncated IVal. 6849static SDNode * 6850ShrinkLoadReplaceStoreWithStore(const std::pair<unsigned, unsigned> &MaskInfo, 6851 SDValue IVal, StoreSDNode *St, 6852 DAGCombiner *DC) { 6853 unsigned NumBytes = MaskInfo.first; 6854 unsigned ByteShift = MaskInfo.second; 6855 SelectionDAG &DAG = DC->getDAG(); 6856 6857 // Check to see if IVal is all zeros in the part being masked in by the 'or' 6858 // that uses this. If not, this is not a replacement. 6859 APInt Mask = ~APInt::getBitsSet(IVal.getValueSizeInBits(), 6860 ByteShift*8, (ByteShift+NumBytes)*8); 6861 if (!DAG.MaskedValueIsZero(IVal, Mask)) return 0; 6862 6863 // Check that it is legal on the target to do this. It is legal if the new 6864 // VT we're shrinking to (i8/i16/i32) is legal or we're still before type 6865 // legalization. 6866 MVT VT = MVT::getIntegerVT(NumBytes*8); 6867 if (!DC->isTypeLegal(VT)) 6868 return 0; 6869 6870 // Okay, we can do this! Replace the 'St' store with a store of IVal that is 6871 // shifted by ByteShift and truncated down to NumBytes. 6872 if (ByteShift) 6873 IVal = DAG.getNode(ISD::SRL, IVal->getDebugLoc(), IVal.getValueType(), IVal, 6874 DAG.getConstant(ByteShift*8, 6875 DC->getShiftAmountTy(IVal.getValueType()))); 6876 6877 // Figure out the offset for the store and the alignment of the access. 6878 unsigned StOffset; 6879 unsigned NewAlign = St->getAlignment(); 6880 6881 if (DAG.getTargetLoweringInfo().isLittleEndian()) 6882 StOffset = ByteShift; 6883 else 6884 StOffset = IVal.getValueType().getStoreSize() - ByteShift - NumBytes; 6885 6886 SDValue Ptr = St->getBasePtr(); 6887 if (StOffset) { 6888 Ptr = DAG.getNode(ISD::ADD, IVal->getDebugLoc(), Ptr.getValueType(), 6889 Ptr, DAG.getConstant(StOffset, Ptr.getValueType())); 6890 NewAlign = MinAlign(NewAlign, StOffset); 6891 } 6892 6893 // Truncate down to the new size. 6894 IVal = DAG.getNode(ISD::TRUNCATE, IVal->getDebugLoc(), VT, IVal); 6895 6896 ++OpsNarrowed; 6897 return DAG.getStore(St->getChain(), St->getDebugLoc(), IVal, Ptr, 6898 St->getPointerInfo().getWithOffset(StOffset), 6899 false, false, NewAlign).getNode(); 6900} 6901 6902 6903/// ReduceLoadOpStoreWidth - Look for sequence of load / op / store where op is 6904/// one of 'or', 'xor', and 'and' of immediates. If 'op' is only touching some 6905/// of the loaded bits, try narrowing the load and store if it would end up 6906/// being a win for performance or code size. 6907SDValue DAGCombiner::ReduceLoadOpStoreWidth(SDNode *N) { 6908 StoreSDNode *ST = cast<StoreSDNode>(N); 6909 if (ST->isVolatile()) 6910 return SDValue(); 6911 6912 SDValue Chain = ST->getChain(); 6913 SDValue Value = ST->getValue(); 6914 SDValue Ptr = ST->getBasePtr(); 6915 EVT VT = Value.getValueType(); 6916 6917 if (ST->isTruncatingStore() || VT.isVector() || !Value.hasOneUse()) 6918 return SDValue(); 6919 6920 unsigned Opc = Value.getOpcode(); 6921 6922 // If this is "store (or X, Y), P" and X is "(and (load P), cst)", where cst 6923 // is a byte mask indicating a consecutive number of bytes, check to see if 6924 // Y is known to provide just those bytes. If so, we try to replace the 6925 // load + replace + store sequence with a single (narrower) store, which makes 6926 // the load dead. 6927 if (Opc == ISD::OR) { 6928 std::pair<unsigned, unsigned> MaskedLoad; 6929 MaskedLoad = CheckForMaskedLoad(Value.getOperand(0), Ptr, Chain); 6930 if (MaskedLoad.first) 6931 if (SDNode *NewST = ShrinkLoadReplaceStoreWithStore(MaskedLoad, 6932 Value.getOperand(1), ST,this)) 6933 return SDValue(NewST, 0); 6934 6935 // Or is commutative, so try swapping X and Y. 6936 MaskedLoad = CheckForMaskedLoad(Value.getOperand(1), Ptr, Chain); 6937 if (MaskedLoad.first) 6938 if (SDNode *NewST = ShrinkLoadReplaceStoreWithStore(MaskedLoad, 6939 Value.getOperand(0), ST,this)) 6940 return SDValue(NewST, 0); 6941 } 6942 6943 if ((Opc != ISD::OR && Opc != ISD::XOR && Opc != ISD::AND) || 6944 Value.getOperand(1).getOpcode() != ISD::Constant) 6945 return SDValue(); 6946 6947 SDValue N0 = Value.getOperand(0); 6948 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() && 6949 Chain == SDValue(N0.getNode(), 1)) { 6950 LoadSDNode *LD = cast<LoadSDNode>(N0); 6951 if (LD->getBasePtr() != Ptr || 6952 LD->getPointerInfo().getAddrSpace() != 6953 ST->getPointerInfo().getAddrSpace()) 6954 return SDValue(); 6955 6956 // Find the type to narrow it the load / op / store to. 6957 SDValue N1 = Value.getOperand(1); 6958 unsigned BitWidth = N1.getValueSizeInBits(); 6959 APInt Imm = cast<ConstantSDNode>(N1)->getAPIntValue(); 6960 if (Opc == ISD::AND) 6961 Imm ^= APInt::getAllOnesValue(BitWidth); 6962 if (Imm == 0 || Imm.isAllOnesValue()) 6963 return SDValue(); 6964 unsigned ShAmt = Imm.countTrailingZeros(); 6965 unsigned MSB = BitWidth - Imm.countLeadingZeros() - 1; 6966 unsigned NewBW = NextPowerOf2(MSB - ShAmt); 6967 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW); 6968 while (NewBW < BitWidth && 6969 !(TLI.isOperationLegalOrCustom(Opc, NewVT) && 6970 TLI.isNarrowingProfitable(VT, NewVT))) { 6971 NewBW = NextPowerOf2(NewBW); 6972 NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW); 6973 } 6974 if (NewBW >= BitWidth) 6975 return SDValue(); 6976 6977 // If the lsb changed does not start at the type bitwidth boundary, 6978 // start at the previous one. 6979 if (ShAmt % NewBW) 6980 ShAmt = (((ShAmt + NewBW - 1) / NewBW) * NewBW) - NewBW; 6981 APInt Mask = APInt::getBitsSet(BitWidth, ShAmt, ShAmt + NewBW); 6982 if ((Imm & Mask) == Imm) { 6983 APInt NewImm = (Imm & Mask).lshr(ShAmt).trunc(NewBW); 6984 if (Opc == ISD::AND) 6985 NewImm ^= APInt::getAllOnesValue(NewBW); 6986 uint64_t PtrOff = ShAmt / 8; 6987 // For big endian targets, we need to adjust the offset to the pointer to 6988 // load the correct bytes. 6989 if (TLI.isBigEndian()) 6990 PtrOff = (BitWidth + 7 - NewBW) / 8 - PtrOff; 6991 6992 unsigned NewAlign = MinAlign(LD->getAlignment(), PtrOff); 6993 Type *NewVTTy = NewVT.getTypeForEVT(*DAG.getContext()); 6994 if (NewAlign < TLI.getTargetData()->getABITypeAlignment(NewVTTy)) 6995 return SDValue(); 6996 6997 SDValue NewPtr = DAG.getNode(ISD::ADD, LD->getDebugLoc(), 6998 Ptr.getValueType(), Ptr, 6999 DAG.getConstant(PtrOff, Ptr.getValueType())); 7000 SDValue NewLD = DAG.getLoad(NewVT, N0.getDebugLoc(), 7001 LD->getChain(), NewPtr, 7002 LD->getPointerInfo().getWithOffset(PtrOff), 7003 LD->isVolatile(), LD->isNonTemporal(), 7004 LD->isInvariant(), NewAlign); 7005 SDValue NewVal = DAG.getNode(Opc, Value.getDebugLoc(), NewVT, NewLD, 7006 DAG.getConstant(NewImm, NewVT)); 7007 SDValue NewST = DAG.getStore(Chain, N->getDebugLoc(), 7008 NewVal, NewPtr, 7009 ST->getPointerInfo().getWithOffset(PtrOff), 7010 false, false, NewAlign); 7011 7012 AddToWorkList(NewPtr.getNode()); 7013 AddToWorkList(NewLD.getNode()); 7014 AddToWorkList(NewVal.getNode()); 7015 WorkListRemover DeadNodes(*this); 7016 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), NewLD.getValue(1)); 7017 ++OpsNarrowed; 7018 return NewST; 7019 } 7020 } 7021 7022 return SDValue(); 7023} 7024 7025/// TransformFPLoadStorePair - For a given floating point load / store pair, 7026/// if the load value isn't used by any other operations, then consider 7027/// transforming the pair to integer load / store operations if the target 7028/// deems the transformation profitable. 7029SDValue DAGCombiner::TransformFPLoadStorePair(SDNode *N) { 7030 StoreSDNode *ST = cast<StoreSDNode>(N); 7031 SDValue Chain = ST->getChain(); 7032 SDValue Value = ST->getValue(); 7033 if (ISD::isNormalStore(ST) && ISD::isNormalLoad(Value.getNode()) && 7034 Value.hasOneUse() && 7035 Chain == SDValue(Value.getNode(), 1)) { 7036 LoadSDNode *LD = cast<LoadSDNode>(Value); 7037 EVT VT = LD->getMemoryVT(); 7038 if (!VT.isFloatingPoint() || 7039 VT != ST->getMemoryVT() || 7040 LD->isNonTemporal() || 7041 ST->isNonTemporal() || 7042 LD->getPointerInfo().getAddrSpace() != 0 || 7043 ST->getPointerInfo().getAddrSpace() != 0) 7044 return SDValue(); 7045 7046 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits()); 7047 if (!TLI.isOperationLegal(ISD::LOAD, IntVT) || 7048 !TLI.isOperationLegal(ISD::STORE, IntVT) || 7049 !TLI.isDesirableToTransformToIntegerOp(ISD::LOAD, VT) || 7050 !TLI.isDesirableToTransformToIntegerOp(ISD::STORE, VT)) 7051 return SDValue(); 7052 7053 unsigned LDAlign = LD->getAlignment(); 7054 unsigned STAlign = ST->getAlignment(); 7055 Type *IntVTTy = IntVT.getTypeForEVT(*DAG.getContext()); 7056 unsigned ABIAlign = TLI.getTargetData()->getABITypeAlignment(IntVTTy); 7057 if (LDAlign < ABIAlign || STAlign < ABIAlign) 7058 return SDValue(); 7059 7060 SDValue NewLD = DAG.getLoad(IntVT, Value.getDebugLoc(), 7061 LD->getChain(), LD->getBasePtr(), 7062 LD->getPointerInfo(), 7063 false, false, false, LDAlign); 7064 7065 SDValue NewST = DAG.getStore(NewLD.getValue(1), N->getDebugLoc(), 7066 NewLD, ST->getBasePtr(), 7067 ST->getPointerInfo(), 7068 false, false, STAlign); 7069 7070 AddToWorkList(NewLD.getNode()); 7071 AddToWorkList(NewST.getNode()); 7072 WorkListRemover DeadNodes(*this); 7073 DAG.ReplaceAllUsesOfValueWith(Value.getValue(1), NewLD.getValue(1)); 7074 ++LdStFP2Int; 7075 return NewST; 7076 } 7077 7078 return SDValue(); 7079} 7080 7081SDValue DAGCombiner::visitSTORE(SDNode *N) { 7082 StoreSDNode *ST = cast<StoreSDNode>(N); 7083 SDValue Chain = ST->getChain(); 7084 SDValue Value = ST->getValue(); 7085 SDValue Ptr = ST->getBasePtr(); 7086 7087 // If this is a store of a bit convert, store the input value if the 7088 // resultant store does not need a higher alignment than the original. 7089 if (Value.getOpcode() == ISD::BITCAST && !ST->isTruncatingStore() && 7090 ST->isUnindexed()) { 7091 unsigned OrigAlign = ST->getAlignment(); 7092 EVT SVT = Value.getOperand(0).getValueType(); 7093 unsigned Align = TLI.getTargetData()-> 7094 getABITypeAlignment(SVT.getTypeForEVT(*DAG.getContext())); 7095 if (Align <= OrigAlign && 7096 ((!LegalOperations && !ST->isVolatile()) || 7097 TLI.isOperationLegalOrCustom(ISD::STORE, SVT))) 7098 return DAG.getStore(Chain, N->getDebugLoc(), Value.getOperand(0), 7099 Ptr, ST->getPointerInfo(), ST->isVolatile(), 7100 ST->isNonTemporal(), OrigAlign); 7101 } 7102 7103 // Turn 'store undef, Ptr' -> nothing. 7104 if (Value.getOpcode() == ISD::UNDEF && ST->isUnindexed()) 7105 return Chain; 7106 7107 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 7108 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) { 7109 // NOTE: If the original store is volatile, this transform must not increase 7110 // the number of stores. For example, on x86-32 an f64 can be stored in one 7111 // processor operation but an i64 (which is not legal) requires two. So the 7112 // transform should not be done in this case. 7113 if (Value.getOpcode() != ISD::TargetConstantFP) { 7114 SDValue Tmp; 7115 switch (CFP->getValueType(0).getSimpleVT().SimpleTy) { 7116 default: llvm_unreachable("Unknown FP type"); 7117 case MVT::f80: // We don't do this for these yet. 7118 case MVT::f128: 7119 case MVT::ppcf128: 7120 break; 7121 case MVT::f32: 7122 if ((isTypeLegal(MVT::i32) && !LegalOperations && !ST->isVolatile()) || 7123 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) { 7124 Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF(). 7125 bitcastToAPInt().getZExtValue(), MVT::i32); 7126 return DAG.getStore(Chain, N->getDebugLoc(), Tmp, 7127 Ptr, ST->getPointerInfo(), ST->isVolatile(), 7128 ST->isNonTemporal(), ST->getAlignment()); 7129 } 7130 break; 7131 case MVT::f64: 7132 if ((TLI.isTypeLegal(MVT::i64) && !LegalOperations && 7133 !ST->isVolatile()) || 7134 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i64)) { 7135 Tmp = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt(). 7136 getZExtValue(), MVT::i64); 7137 return DAG.getStore(Chain, N->getDebugLoc(), Tmp, 7138 Ptr, ST->getPointerInfo(), ST->isVolatile(), 7139 ST->isNonTemporal(), ST->getAlignment()); 7140 } 7141 7142 if (!ST->isVolatile() && 7143 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) { 7144 // Many FP stores are not made apparent until after legalize, e.g. for 7145 // argument passing. Since this is so common, custom legalize the 7146 // 64-bit integer store into two 32-bit stores. 7147 uint64_t Val = CFP->getValueAPF().bitcastToAPInt().getZExtValue(); 7148 SDValue Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32); 7149 SDValue Hi = DAG.getConstant(Val >> 32, MVT::i32); 7150 if (TLI.isBigEndian()) std::swap(Lo, Hi); 7151 7152 unsigned Alignment = ST->getAlignment(); 7153 bool isVolatile = ST->isVolatile(); 7154 bool isNonTemporal = ST->isNonTemporal(); 7155 7156 SDValue St0 = DAG.getStore(Chain, ST->getDebugLoc(), Lo, 7157 Ptr, ST->getPointerInfo(), 7158 isVolatile, isNonTemporal, 7159 ST->getAlignment()); 7160 Ptr = DAG.getNode(ISD::ADD, N->getDebugLoc(), Ptr.getValueType(), Ptr, 7161 DAG.getConstant(4, Ptr.getValueType())); 7162 Alignment = MinAlign(Alignment, 4U); 7163 SDValue St1 = DAG.getStore(Chain, ST->getDebugLoc(), Hi, 7164 Ptr, ST->getPointerInfo().getWithOffset(4), 7165 isVolatile, isNonTemporal, 7166 Alignment); 7167 return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, 7168 St0, St1); 7169 } 7170 7171 break; 7172 } 7173 } 7174 } 7175 7176 // Try to infer better alignment information than the store already has. 7177 if (OptLevel != CodeGenOpt::None && ST->isUnindexed()) { 7178 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) { 7179 if (Align > ST->getAlignment()) 7180 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value, 7181 Ptr, ST->getPointerInfo(), ST->getMemoryVT(), 7182 ST->isVolatile(), ST->isNonTemporal(), Align); 7183 } 7184 } 7185 7186 // Try transforming a pair floating point load / store ops to integer 7187 // load / store ops. 7188 SDValue NewST = TransformFPLoadStorePair(N); 7189 if (NewST.getNode()) 7190 return NewST; 7191 7192 if (CombinerAA) { 7193 // Walk up chain skipping non-aliasing memory nodes. 7194 SDValue BetterChain = FindBetterChain(N, Chain); 7195 7196 // If there is a better chain. 7197 if (Chain != BetterChain) { 7198 SDValue ReplStore; 7199 7200 // Replace the chain to avoid dependency. 7201 if (ST->isTruncatingStore()) { 7202 ReplStore = DAG.getTruncStore(BetterChain, N->getDebugLoc(), Value, Ptr, 7203 ST->getPointerInfo(), 7204 ST->getMemoryVT(), ST->isVolatile(), 7205 ST->isNonTemporal(), ST->getAlignment()); 7206 } else { 7207 ReplStore = DAG.getStore(BetterChain, N->getDebugLoc(), Value, Ptr, 7208 ST->getPointerInfo(), 7209 ST->isVolatile(), ST->isNonTemporal(), 7210 ST->getAlignment()); 7211 } 7212 7213 // Create token to keep both nodes around. 7214 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 7215 MVT::Other, Chain, ReplStore); 7216 7217 // Make sure the new and old chains are cleaned up. 7218 AddToWorkList(Token.getNode()); 7219 7220 // Don't add users to work list. 7221 return CombineTo(N, Token, false); 7222 } 7223 } 7224 7225 // Try transforming N to an indexed store. 7226 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 7227 return SDValue(N, 0); 7228 7229 // FIXME: is there such a thing as a truncating indexed store? 7230 if (ST->isTruncatingStore() && ST->isUnindexed() && 7231 Value.getValueType().isInteger()) { 7232 // See if we can simplify the input to this truncstore with knowledge that 7233 // only the low bits are being used. For example: 7234 // "truncstore (or (shl x, 8), y), i8" -> "truncstore y, i8" 7235 SDValue Shorter = 7236 GetDemandedBits(Value, 7237 APInt::getLowBitsSet( 7238 Value.getValueType().getScalarType().getSizeInBits(), 7239 ST->getMemoryVT().getScalarType().getSizeInBits())); 7240 AddToWorkList(Value.getNode()); 7241 if (Shorter.getNode()) 7242 return DAG.getTruncStore(Chain, N->getDebugLoc(), Shorter, 7243 Ptr, ST->getPointerInfo(), ST->getMemoryVT(), 7244 ST->isVolatile(), ST->isNonTemporal(), 7245 ST->getAlignment()); 7246 7247 // Otherwise, see if we can simplify the operation with 7248 // SimplifyDemandedBits, which only works if the value has a single use. 7249 if (SimplifyDemandedBits(Value, 7250 APInt::getLowBitsSet( 7251 Value.getValueType().getScalarType().getSizeInBits(), 7252 ST->getMemoryVT().getScalarType().getSizeInBits()))) 7253 return SDValue(N, 0); 7254 } 7255 7256 // If this is a load followed by a store to the same location, then the store 7257 // is dead/noop. 7258 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Value)) { 7259 if (Ld->getBasePtr() == Ptr && ST->getMemoryVT() == Ld->getMemoryVT() && 7260 ST->isUnindexed() && !ST->isVolatile() && 7261 // There can't be any side effects between the load and store, such as 7262 // a call or store. 7263 Chain.reachesChainWithoutSideEffects(SDValue(Ld, 1))) { 7264 // The store is dead, remove it. 7265 return Chain; 7266 } 7267 } 7268 7269 // If this is an FP_ROUND or TRUNC followed by a store, fold this into a 7270 // truncating store. We can do this even if this is already a truncstore. 7271 if ((Value.getOpcode() == ISD::FP_ROUND || Value.getOpcode() == ISD::TRUNCATE) 7272 && Value.getNode()->hasOneUse() && ST->isUnindexed() && 7273 TLI.isTruncStoreLegal(Value.getOperand(0).getValueType(), 7274 ST->getMemoryVT())) { 7275 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value.getOperand(0), 7276 Ptr, ST->getPointerInfo(), ST->getMemoryVT(), 7277 ST->isVolatile(), ST->isNonTemporal(), 7278 ST->getAlignment()); 7279 } 7280 7281 return ReduceLoadOpStoreWidth(N); 7282} 7283 7284SDValue DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) { 7285 SDValue InVec = N->getOperand(0); 7286 SDValue InVal = N->getOperand(1); 7287 SDValue EltNo = N->getOperand(2); 7288 DebugLoc dl = N->getDebugLoc(); 7289 7290 // If the inserted element is an UNDEF, just use the input vector. 7291 if (InVal.getOpcode() == ISD::UNDEF) 7292 return InVec; 7293 7294 EVT VT = InVec.getValueType(); 7295 7296 // If we can't generate a legal BUILD_VECTOR, exit 7297 if (LegalOperations && !TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) 7298 return SDValue(); 7299 7300 // Check that we know which element is being inserted 7301 if (!isa<ConstantSDNode>(EltNo)) 7302 return SDValue(); 7303 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 7304 7305 // Check that the operand is a BUILD_VECTOR (or UNDEF, which can essentially 7306 // be converted to a BUILD_VECTOR). Fill in the Ops vector with the 7307 // vector elements. 7308 SmallVector<SDValue, 8> Ops; 7309 if (InVec.getOpcode() == ISD::BUILD_VECTOR) { 7310 Ops.append(InVec.getNode()->op_begin(), 7311 InVec.getNode()->op_end()); 7312 } else if (InVec.getOpcode() == ISD::UNDEF) { 7313 unsigned NElts = VT.getVectorNumElements(); 7314 Ops.append(NElts, DAG.getUNDEF(InVal.getValueType())); 7315 } else { 7316 return SDValue(); 7317 } 7318 7319 // Insert the element 7320 if (Elt < Ops.size()) { 7321 // All the operands of BUILD_VECTOR must have the same type; 7322 // we enforce that here. 7323 EVT OpVT = Ops[0].getValueType(); 7324 if (InVal.getValueType() != OpVT) 7325 InVal = OpVT.bitsGT(InVal.getValueType()) ? 7326 DAG.getNode(ISD::ANY_EXTEND, dl, OpVT, InVal) : 7327 DAG.getNode(ISD::TRUNCATE, dl, OpVT, InVal); 7328 Ops[Elt] = InVal; 7329 } 7330 7331 // Return the new vector 7332 return DAG.getNode(ISD::BUILD_VECTOR, dl, 7333 VT, &Ops[0], Ops.size()); 7334} 7335 7336SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) { 7337 // (vextract (scalar_to_vector val, 0) -> val 7338 SDValue InVec = N->getOperand(0); 7339 EVT VT = InVec.getValueType(); 7340 EVT NVT = N->getValueType(0); 7341 7342 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) { 7343 // Check if the result type doesn't match the inserted element type. A 7344 // SCALAR_TO_VECTOR may truncate the inserted element and the 7345 // EXTRACT_VECTOR_ELT may widen the extracted vector. 7346 SDValue InOp = InVec.getOperand(0); 7347 if (InOp.getValueType() != NVT) { 7348 assert(InOp.getValueType().isInteger() && NVT.isInteger()); 7349 return DAG.getSExtOrTrunc(InOp, InVec.getDebugLoc(), NVT); 7350 } 7351 return InOp; 7352 } 7353 7354 SDValue EltNo = N->getOperand(1); 7355 bool ConstEltNo = isa<ConstantSDNode>(EltNo); 7356 7357 // Transform: (EXTRACT_VECTOR_ELT( VECTOR_SHUFFLE )) -> EXTRACT_VECTOR_ELT. 7358 // We only perform this optimization before the op legalization phase because 7359 // we may introduce new vector instructions which are not backed by TD patterns. 7360 // For example on AVX, extracting elements from a wide vector without using 7361 // extract_subvector. 7362 if (InVec.getOpcode() == ISD::VECTOR_SHUFFLE 7363 && ConstEltNo && !LegalOperations) { 7364 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 7365 int NumElem = VT.getVectorNumElements(); 7366 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(InVec); 7367 // Find the new index to extract from. 7368 int OrigElt = SVOp->getMaskElt(Elt); 7369 7370 // Extracting an undef index is undef. 7371 if (OrigElt == -1) 7372 return DAG.getUNDEF(NVT); 7373 7374 // Select the right vector half to extract from. 7375 if (OrigElt < NumElem) { 7376 InVec = InVec->getOperand(0); 7377 } else { 7378 InVec = InVec->getOperand(1); 7379 OrigElt -= NumElem; 7380 } 7381 7382 EVT IndexTy = N->getOperand(1).getValueType(); 7383 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, N->getDebugLoc(), NVT, 7384 InVec, DAG.getConstant(OrigElt, IndexTy)); 7385 } 7386 7387 // Perform only after legalization to ensure build_vector / vector_shuffle 7388 // optimizations have already been done. 7389 if (!LegalOperations) return SDValue(); 7390 7391 // (vextract (v4f32 load $addr), c) -> (f32 load $addr+c*size) 7392 // (vextract (v4f32 s2v (f32 load $addr)), c) -> (f32 load $addr+c*size) 7393 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), 0) -> (f32 load $addr) 7394 7395 if (ConstEltNo) { 7396 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 7397 bool NewLoad = false; 7398 bool BCNumEltsChanged = false; 7399 EVT ExtVT = VT.getVectorElementType(); 7400 EVT LVT = ExtVT; 7401 7402 // If the result of load has to be truncated, then it's not necessarily 7403 // profitable. 7404 if (NVT.bitsLT(LVT) && !TLI.isTruncateFree(LVT, NVT)) 7405 return SDValue(); 7406 7407 if (InVec.getOpcode() == ISD::BITCAST) { 7408 // Don't duplicate a load with other uses. 7409 if (!InVec.hasOneUse()) 7410 return SDValue(); 7411 7412 EVT BCVT = InVec.getOperand(0).getValueType(); 7413 if (!BCVT.isVector() || ExtVT.bitsGT(BCVT.getVectorElementType())) 7414 return SDValue(); 7415 if (VT.getVectorNumElements() != BCVT.getVectorNumElements()) 7416 BCNumEltsChanged = true; 7417 InVec = InVec.getOperand(0); 7418 ExtVT = BCVT.getVectorElementType(); 7419 NewLoad = true; 7420 } 7421 7422 LoadSDNode *LN0 = NULL; 7423 const ShuffleVectorSDNode *SVN = NULL; 7424 if (ISD::isNormalLoad(InVec.getNode())) { 7425 LN0 = cast<LoadSDNode>(InVec); 7426 } else if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR && 7427 InVec.getOperand(0).getValueType() == ExtVT && 7428 ISD::isNormalLoad(InVec.getOperand(0).getNode())) { 7429 // Don't duplicate a load with other uses. 7430 if (!InVec.hasOneUse()) 7431 return SDValue(); 7432 7433 LN0 = cast<LoadSDNode>(InVec.getOperand(0)); 7434 } else if ((SVN = dyn_cast<ShuffleVectorSDNode>(InVec))) { 7435 // (vextract (vector_shuffle (load $addr), v2, <1, u, u, u>), 1) 7436 // => 7437 // (load $addr+1*size) 7438 7439 // Don't duplicate a load with other uses. 7440 if (!InVec.hasOneUse()) 7441 return SDValue(); 7442 7443 // If the bit convert changed the number of elements, it is unsafe 7444 // to examine the mask. 7445 if (BCNumEltsChanged) 7446 return SDValue(); 7447 7448 // Select the input vector, guarding against out of range extract vector. 7449 unsigned NumElems = VT.getVectorNumElements(); 7450 int Idx = (Elt > (int)NumElems) ? -1 : SVN->getMaskElt(Elt); 7451 InVec = (Idx < (int)NumElems) ? InVec.getOperand(0) : InVec.getOperand(1); 7452 7453 if (InVec.getOpcode() == ISD::BITCAST) { 7454 // Don't duplicate a load with other uses. 7455 if (!InVec.hasOneUse()) 7456 return SDValue(); 7457 7458 InVec = InVec.getOperand(0); 7459 } 7460 if (ISD::isNormalLoad(InVec.getNode())) { 7461 LN0 = cast<LoadSDNode>(InVec); 7462 Elt = (Idx < (int)NumElems) ? Idx : Idx - (int)NumElems; 7463 } 7464 } 7465 7466 // Make sure we found a non-volatile load and the extractelement is 7467 // the only use. 7468 if (!LN0 || !LN0->hasNUsesOfValue(1,0) || LN0->isVolatile()) 7469 return SDValue(); 7470 7471 // If Idx was -1 above, Elt is going to be -1, so just return undef. 7472 if (Elt == -1) 7473 return DAG.getUNDEF(LVT); 7474 7475 unsigned Align = LN0->getAlignment(); 7476 if (NewLoad) { 7477 // Check the resultant load doesn't need a higher alignment than the 7478 // original load. 7479 unsigned NewAlign = 7480 TLI.getTargetData() 7481 ->getABITypeAlignment(LVT.getTypeForEVT(*DAG.getContext())); 7482 7483 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, LVT)) 7484 return SDValue(); 7485 7486 Align = NewAlign; 7487 } 7488 7489 SDValue NewPtr = LN0->getBasePtr(); 7490 unsigned PtrOff = 0; 7491 7492 if (Elt) { 7493 PtrOff = LVT.getSizeInBits() * Elt / 8; 7494 EVT PtrType = NewPtr.getValueType(); 7495 if (TLI.isBigEndian()) 7496 PtrOff = VT.getSizeInBits() / 8 - PtrOff; 7497 NewPtr = DAG.getNode(ISD::ADD, N->getDebugLoc(), PtrType, NewPtr, 7498 DAG.getConstant(PtrOff, PtrType)); 7499 } 7500 7501 // The replacement we need to do here is a little tricky: we need to 7502 // replace an extractelement of a load with a load. 7503 // Use ReplaceAllUsesOfValuesWith to do the replacement. 7504 // Note that this replacement assumes that the extractvalue is the only 7505 // use of the load; that's okay because we don't want to perform this 7506 // transformation in other cases anyway. 7507 SDValue Load; 7508 SDValue Chain; 7509 if (NVT.bitsGT(LVT)) { 7510 // If the result type of vextract is wider than the load, then issue an 7511 // extending load instead. 7512 ISD::LoadExtType ExtType = TLI.isLoadExtLegal(ISD::ZEXTLOAD, LVT) 7513 ? ISD::ZEXTLOAD : ISD::EXTLOAD; 7514 Load = DAG.getExtLoad(ExtType, N->getDebugLoc(), NVT, LN0->getChain(), 7515 NewPtr, LN0->getPointerInfo().getWithOffset(PtrOff), 7516 LVT, LN0->isVolatile(), LN0->isNonTemporal(),Align); 7517 Chain = Load.getValue(1); 7518 } else { 7519 Load = DAG.getLoad(LVT, N->getDebugLoc(), LN0->getChain(), NewPtr, 7520 LN0->getPointerInfo().getWithOffset(PtrOff), 7521 LN0->isVolatile(), LN0->isNonTemporal(), 7522 LN0->isInvariant(), Align); 7523 Chain = Load.getValue(1); 7524 if (NVT.bitsLT(LVT)) 7525 Load = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), NVT, Load); 7526 else 7527 Load = DAG.getNode(ISD::BITCAST, N->getDebugLoc(), NVT, Load); 7528 } 7529 WorkListRemover DeadNodes(*this); 7530 SDValue From[] = { SDValue(N, 0), SDValue(LN0,1) }; 7531 SDValue To[] = { Load, Chain }; 7532 DAG.ReplaceAllUsesOfValuesWith(From, To, 2); 7533 // Since we're explcitly calling ReplaceAllUses, add the new node to the 7534 // worklist explicitly as well. 7535 AddToWorkList(Load.getNode()); 7536 AddUsersToWorkList(Load.getNode()); // Add users too 7537 // Make sure to revisit this node to clean it up; it will usually be dead. 7538 AddToWorkList(N); 7539 return SDValue(N, 0); 7540 } 7541 7542 return SDValue(); 7543} 7544 7545SDValue DAGCombiner::visitBUILD_VECTOR(SDNode *N) { 7546 unsigned NumInScalars = N->getNumOperands(); 7547 DebugLoc dl = N->getDebugLoc(); 7548 EVT VT = N->getValueType(0); 7549 // Check to see if this is a BUILD_VECTOR of a bunch of values 7550 // which come from any_extend or zero_extend nodes. If so, we can create 7551 // a new BUILD_VECTOR using bit-casts which may enable other BUILD_VECTOR 7552 // optimizations. We do not handle sign-extend because we can't fill the sign 7553 // using shuffles. 7554 EVT SourceType = MVT::Other; 7555 bool AllAnyExt = true; 7556 bool AllUndef = true; 7557 for (unsigned i = 0; i != NumInScalars; ++i) { 7558 SDValue In = N->getOperand(i); 7559 // Ignore undef inputs. 7560 if (In.getOpcode() == ISD::UNDEF) continue; 7561 AllUndef = false; 7562 7563 bool AnyExt = In.getOpcode() == ISD::ANY_EXTEND; 7564 bool ZeroExt = In.getOpcode() == ISD::ZERO_EXTEND; 7565 7566 // Abort if the element is not an extension. 7567 if (!ZeroExt && !AnyExt) { 7568 SourceType = MVT::Other; 7569 break; 7570 } 7571 7572 // The input is a ZeroExt or AnyExt. Check the original type. 7573 EVT InTy = In.getOperand(0).getValueType(); 7574 7575 // Check that all of the widened source types are the same. 7576 if (SourceType == MVT::Other) 7577 // First time. 7578 SourceType = InTy; 7579 else if (InTy != SourceType) { 7580 // Multiple income types. Abort. 7581 SourceType = MVT::Other; 7582 break; 7583 } 7584 7585 // Check if all of the extends are ANY_EXTENDs. 7586 AllAnyExt &= AnyExt; 7587 } 7588 7589 if (AllUndef) 7590 return DAG.getUNDEF(VT); 7591 7592 // In order to have valid types, all of the inputs must be extended from the 7593 // same source type and all of the inputs must be any or zero extend. 7594 // Scalar sizes must be a power of two. 7595 EVT OutScalarTy = N->getValueType(0).getScalarType(); 7596 bool ValidTypes = SourceType != MVT::Other && 7597 isPowerOf2_32(OutScalarTy.getSizeInBits()) && 7598 isPowerOf2_32(SourceType.getSizeInBits()); 7599 7600 // We perform this optimization post type-legalization because 7601 // the type-legalizer often scalarizes integer-promoted vectors. 7602 // Performing this optimization before may create bit-casts which 7603 // will be type-legalized to complex code sequences. 7604 // We perform this optimization only before the operation legalizer because we 7605 // may introduce illegal operations. 7606 // Create a new simpler BUILD_VECTOR sequence which other optimizations can 7607 // turn into a single shuffle instruction. 7608 if ((Level == AfterLegalizeVectorOps || Level == AfterLegalizeTypes) && 7609 ValidTypes) { 7610 bool isLE = TLI.isLittleEndian(); 7611 unsigned ElemRatio = OutScalarTy.getSizeInBits()/SourceType.getSizeInBits(); 7612 assert(ElemRatio > 1 && "Invalid element size ratio"); 7613 SDValue Filler = AllAnyExt ? DAG.getUNDEF(SourceType): 7614 DAG.getConstant(0, SourceType); 7615 7616 unsigned NewBVElems = ElemRatio * N->getValueType(0).getVectorNumElements(); 7617 SmallVector<SDValue, 8> Ops(NewBVElems, Filler); 7618 7619 // Populate the new build_vector 7620 for (unsigned i=0; i < N->getNumOperands(); ++i) { 7621 SDValue Cast = N->getOperand(i); 7622 assert((Cast.getOpcode() == ISD::ANY_EXTEND || 7623 Cast.getOpcode() == ISD::ZERO_EXTEND || 7624 Cast.getOpcode() == ISD::UNDEF) && "Invalid cast opcode"); 7625 SDValue In; 7626 if (Cast.getOpcode() == ISD::UNDEF) 7627 In = DAG.getUNDEF(SourceType); 7628 else 7629 In = Cast->getOperand(0); 7630 unsigned Index = isLE ? (i * ElemRatio) : 7631 (i * ElemRatio + (ElemRatio - 1)); 7632 7633 assert(Index < Ops.size() && "Invalid index"); 7634 Ops[Index] = In; 7635 } 7636 7637 // The type of the new BUILD_VECTOR node. 7638 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), SourceType, NewBVElems); 7639 assert(VecVT.getSizeInBits() == N->getValueType(0).getSizeInBits() && 7640 "Invalid vector size"); 7641 // Check if the new vector type is legal. 7642 if (!isTypeLegal(VecVT)) return SDValue(); 7643 7644 // Make the new BUILD_VECTOR. 7645 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 7646 VecVT, &Ops[0], Ops.size()); 7647 7648 // The new BUILD_VECTOR node has the potential to be further optimized. 7649 AddToWorkList(BV.getNode()); 7650 // Bitcast to the desired type. 7651 return DAG.getNode(ISD::BITCAST, dl, N->getValueType(0), BV); 7652 } 7653 7654 // Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT 7655 // operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from 7656 // at most two distinct vectors, turn this into a shuffle node. 7657 7658 // May only combine to shuffle after legalize if shuffle is legal. 7659 if (LegalOperations && 7660 !TLI.isOperationLegalOrCustom(ISD::VECTOR_SHUFFLE, VT)) 7661 return SDValue(); 7662 7663 SDValue VecIn1, VecIn2; 7664 for (unsigned i = 0; i != NumInScalars; ++i) { 7665 // Ignore undef inputs. 7666 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 7667 7668 // If this input is something other than a EXTRACT_VECTOR_ELT with a 7669 // constant index, bail out. 7670 if (N->getOperand(i).getOpcode() != ISD::EXTRACT_VECTOR_ELT || 7671 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) { 7672 VecIn1 = VecIn2 = SDValue(0, 0); 7673 break; 7674 } 7675 7676 // We allow up to two distinct input vectors. 7677 SDValue ExtractedFromVec = N->getOperand(i).getOperand(0); 7678 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2) 7679 continue; 7680 7681 if (VecIn1.getNode() == 0) { 7682 VecIn1 = ExtractedFromVec; 7683 } else if (VecIn2.getNode() == 0) { 7684 VecIn2 = ExtractedFromVec; 7685 } else { 7686 // Too many inputs. 7687 VecIn1 = VecIn2 = SDValue(0, 0); 7688 break; 7689 } 7690 } 7691 7692 // If everything is good, we can make a shuffle operation. 7693 if (VecIn1.getNode()) { 7694 SmallVector<int, 8> Mask; 7695 for (unsigned i = 0; i != NumInScalars; ++i) { 7696 if (N->getOperand(i).getOpcode() == ISD::UNDEF) { 7697 Mask.push_back(-1); 7698 continue; 7699 } 7700 7701 // If extracting from the first vector, just use the index directly. 7702 SDValue Extract = N->getOperand(i); 7703 SDValue ExtVal = Extract.getOperand(1); 7704 if (Extract.getOperand(0) == VecIn1) { 7705 unsigned ExtIndex = cast<ConstantSDNode>(ExtVal)->getZExtValue(); 7706 if (ExtIndex > VT.getVectorNumElements()) 7707 return SDValue(); 7708 7709 Mask.push_back(ExtIndex); 7710 continue; 7711 } 7712 7713 // Otherwise, use InIdx + VecSize 7714 unsigned Idx = cast<ConstantSDNode>(ExtVal)->getZExtValue(); 7715 Mask.push_back(Idx+NumInScalars); 7716 } 7717 7718 // We can't generate a shuffle node with mismatched input and output types. 7719 // Attempt to transform a single input vector to the correct type. 7720 if ((VT != VecIn1.getValueType())) { 7721 // We don't support shuffeling between TWO values of different types. 7722 if (VecIn2.getNode() != 0) 7723 return SDValue(); 7724 7725 // We only support widening of vectors which are half the size of the 7726 // output registers. For example XMM->YMM widening on X86 with AVX. 7727 if (VecIn1.getValueType().getSizeInBits()*2 != VT.getSizeInBits()) 7728 return SDValue(); 7729 7730 // Widen the input vector by adding undef values. 7731 VecIn1 = DAG.getNode(ISD::CONCAT_VECTORS, N->getDebugLoc(), VT, 7732 VecIn1, DAG.getUNDEF(VecIn1.getValueType())); 7733 } 7734 7735 // If VecIn2 is unused then change it to undef. 7736 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT); 7737 7738 // Check that we were able to transform all incoming values to the same type. 7739 if (VecIn2.getValueType() != VecIn1.getValueType() || 7740 VecIn1.getValueType() != VT) 7741 return SDValue(); 7742 7743 // Only type-legal BUILD_VECTOR nodes are converted to shuffle nodes. 7744 if (!isTypeLegal(VT)) 7745 return SDValue(); 7746 7747 // Return the new VECTOR_SHUFFLE node. 7748 SDValue Ops[2]; 7749 Ops[0] = VecIn1; 7750 Ops[1] = VecIn2; 7751 return DAG.getVectorShuffle(VT, N->getDebugLoc(), Ops[0], Ops[1], &Mask[0]); 7752 } 7753 7754 return SDValue(); 7755} 7756 7757SDValue DAGCombiner::visitCONCAT_VECTORS(SDNode *N) { 7758 // TODO: Check to see if this is a CONCAT_VECTORS of a bunch of 7759 // EXTRACT_SUBVECTOR operations. If so, and if the EXTRACT_SUBVECTOR vector 7760 // inputs come from at most two distinct vectors, turn this into a shuffle 7761 // node. 7762 7763 // If we only have one input vector, we don't need to do any concatenation. 7764 if (N->getNumOperands() == 1) 7765 return N->getOperand(0); 7766 7767 return SDValue(); 7768} 7769 7770SDValue DAGCombiner::visitEXTRACT_SUBVECTOR(SDNode* N) { 7771 EVT NVT = N->getValueType(0); 7772 SDValue V = N->getOperand(0); 7773 7774 if (V->getOpcode() == ISD::INSERT_SUBVECTOR) { 7775 // Handle only simple case where vector being inserted and vector 7776 // being extracted are of same type, and are half size of larger vectors. 7777 EVT BigVT = V->getOperand(0).getValueType(); 7778 EVT SmallVT = V->getOperand(1).getValueType(); 7779 if (NVT != SmallVT || NVT.getSizeInBits()*2 != BigVT.getSizeInBits()) 7780 return SDValue(); 7781 7782 // Only handle cases where both indexes are constants with the same type. 7783 ConstantSDNode *InsIdx = dyn_cast<ConstantSDNode>(N->getOperand(1)); 7784 ConstantSDNode *ExtIdx = dyn_cast<ConstantSDNode>(V->getOperand(2)); 7785 7786 if (InsIdx && ExtIdx && 7787 InsIdx->getValueType(0).getSizeInBits() <= 64 && 7788 ExtIdx->getValueType(0).getSizeInBits() <= 64) { 7789 // Combine: 7790 // (extract_subvec (insert_subvec V1, V2, InsIdx), ExtIdx) 7791 // Into: 7792 // indices are equal => V1 7793 // otherwise => (extract_subvec V1, ExtIdx) 7794 if (InsIdx->getZExtValue() == ExtIdx->getZExtValue()) 7795 return V->getOperand(1); 7796 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, N->getDebugLoc(), NVT, 7797 V->getOperand(0), N->getOperand(1)); 7798 } 7799 } 7800 7801 return SDValue(); 7802} 7803 7804SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) { 7805 EVT VT = N->getValueType(0); 7806 unsigned NumElts = VT.getVectorNumElements(); 7807 7808 SDValue N0 = N->getOperand(0); 7809 SDValue N1 = N->getOperand(1); 7810 7811 assert(N0.getValueType() == VT && "Vector shuffle must be normalized in DAG"); 7812 7813 // Canonicalize shuffle undef, undef -> undef 7814 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF) 7815 return DAG.getUNDEF(VT); 7816 7817 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N); 7818 7819 // Canonicalize shuffle v, v -> v, undef 7820 if (N0 == N1) { 7821 SmallVector<int, 8> NewMask; 7822 for (unsigned i = 0; i != NumElts; ++i) { 7823 int Idx = SVN->getMaskElt(i); 7824 if (Idx >= (int)NumElts) Idx -= NumElts; 7825 NewMask.push_back(Idx); 7826 } 7827 return DAG.getVectorShuffle(VT, N->getDebugLoc(), N0, DAG.getUNDEF(VT), 7828 &NewMask[0]); 7829 } 7830 7831 // Canonicalize shuffle undef, v -> v, undef. Commute the shuffle mask. 7832 if (N0.getOpcode() == ISD::UNDEF) { 7833 SmallVector<int, 8> NewMask; 7834 for (unsigned i = 0; i != NumElts; ++i) { 7835 int Idx = SVN->getMaskElt(i); 7836 if (Idx >= 0) { 7837 if (Idx < (int)NumElts) 7838 Idx += NumElts; 7839 else 7840 Idx -= NumElts; 7841 } 7842 NewMask.push_back(Idx); 7843 } 7844 return DAG.getVectorShuffle(VT, N->getDebugLoc(), N1, DAG.getUNDEF(VT), 7845 &NewMask[0]); 7846 } 7847 7848 // Remove references to rhs if it is undef 7849 if (N1.getOpcode() == ISD::UNDEF) { 7850 bool Changed = false; 7851 SmallVector<int, 8> NewMask; 7852 for (unsigned i = 0; i != NumElts; ++i) { 7853 int Idx = SVN->getMaskElt(i); 7854 if (Idx >= (int)NumElts) { 7855 Idx = -1; 7856 Changed = true; 7857 } 7858 NewMask.push_back(Idx); 7859 } 7860 if (Changed) 7861 return DAG.getVectorShuffle(VT, N->getDebugLoc(), N0, N1, &NewMask[0]); 7862 } 7863 7864 // If it is a splat, check if the argument vector is another splat or a 7865 // build_vector with all scalar elements the same. 7866 if (SVN->isSplat() && SVN->getSplatIndex() < (int)NumElts) { 7867 SDNode *V = N0.getNode(); 7868 7869 // If this is a bit convert that changes the element type of the vector but 7870 // not the number of vector elements, look through it. Be careful not to 7871 // look though conversions that change things like v4f32 to v2f64. 7872 if (V->getOpcode() == ISD::BITCAST) { 7873 SDValue ConvInput = V->getOperand(0); 7874 if (ConvInput.getValueType().isVector() && 7875 ConvInput.getValueType().getVectorNumElements() == NumElts) 7876 V = ConvInput.getNode(); 7877 } 7878 7879 if (V->getOpcode() == ISD::BUILD_VECTOR) { 7880 assert(V->getNumOperands() == NumElts && 7881 "BUILD_VECTOR has wrong number of operands"); 7882 SDValue Base; 7883 bool AllSame = true; 7884 for (unsigned i = 0; i != NumElts; ++i) { 7885 if (V->getOperand(i).getOpcode() != ISD::UNDEF) { 7886 Base = V->getOperand(i); 7887 break; 7888 } 7889 } 7890 // Splat of <u, u, u, u>, return <u, u, u, u> 7891 if (!Base.getNode()) 7892 return N0; 7893 for (unsigned i = 0; i != NumElts; ++i) { 7894 if (V->getOperand(i) != Base) { 7895 AllSame = false; 7896 break; 7897 } 7898 } 7899 // Splat of <x, x, x, x>, return <x, x, x, x> 7900 if (AllSame) 7901 return N0; 7902 } 7903 } 7904 7905 // If this shuffle node is simply a swizzle of another shuffle node, 7906 // and it reverses the swizzle of the previous shuffle then we can 7907 // optimize shuffle(shuffle(x, undef), undef) -> x. 7908 if (N0.getOpcode() == ISD::VECTOR_SHUFFLE && Level < AfterLegalizeDAG && 7909 N1.getOpcode() == ISD::UNDEF) { 7910 7911 ShuffleVectorSDNode *OtherSV = cast<ShuffleVectorSDNode>(N0); 7912 7913 // Shuffle nodes can only reverse shuffles with a single non-undef value. 7914 if (N0.getOperand(1).getOpcode() != ISD::UNDEF) 7915 return SDValue(); 7916 7917 // The incoming shuffle must be of the same type as the result of the 7918 // current shuffle. 7919 assert(OtherSV->getOperand(0).getValueType() == VT && 7920 "Shuffle types don't match"); 7921 7922 for (unsigned i = 0; i != NumElts; ++i) { 7923 int Idx = SVN->getMaskElt(i); 7924 assert(Idx < (int)NumElts && "Index references undef operand"); 7925 // Next, this index comes from the first value, which is the incoming 7926 // shuffle. Adopt the incoming index. 7927 if (Idx >= 0) 7928 Idx = OtherSV->getMaskElt(Idx); 7929 7930 // The combined shuffle must map each index to itself. 7931 if (Idx >= 0 && (unsigned)Idx != i) 7932 return SDValue(); 7933 } 7934 7935 return OtherSV->getOperand(0); 7936 } 7937 7938 return SDValue(); 7939} 7940 7941SDValue DAGCombiner::visitMEMBARRIER(SDNode* N) { 7942 if (!TLI.getShouldFoldAtomicFences()) 7943 return SDValue(); 7944 7945 SDValue atomic = N->getOperand(0); 7946 switch (atomic.getOpcode()) { 7947 case ISD::ATOMIC_CMP_SWAP: 7948 case ISD::ATOMIC_SWAP: 7949 case ISD::ATOMIC_LOAD_ADD: 7950 case ISD::ATOMIC_LOAD_SUB: 7951 case ISD::ATOMIC_LOAD_AND: 7952 case ISD::ATOMIC_LOAD_OR: 7953 case ISD::ATOMIC_LOAD_XOR: 7954 case ISD::ATOMIC_LOAD_NAND: 7955 case ISD::ATOMIC_LOAD_MIN: 7956 case ISD::ATOMIC_LOAD_MAX: 7957 case ISD::ATOMIC_LOAD_UMIN: 7958 case ISD::ATOMIC_LOAD_UMAX: 7959 break; 7960 default: 7961 return SDValue(); 7962 } 7963 7964 SDValue fence = atomic.getOperand(0); 7965 if (fence.getOpcode() != ISD::MEMBARRIER) 7966 return SDValue(); 7967 7968 switch (atomic.getOpcode()) { 7969 case ISD::ATOMIC_CMP_SWAP: 7970 return SDValue(DAG.UpdateNodeOperands(atomic.getNode(), 7971 fence.getOperand(0), 7972 atomic.getOperand(1), atomic.getOperand(2), 7973 atomic.getOperand(3)), atomic.getResNo()); 7974 case ISD::ATOMIC_SWAP: 7975 case ISD::ATOMIC_LOAD_ADD: 7976 case ISD::ATOMIC_LOAD_SUB: 7977 case ISD::ATOMIC_LOAD_AND: 7978 case ISD::ATOMIC_LOAD_OR: 7979 case ISD::ATOMIC_LOAD_XOR: 7980 case ISD::ATOMIC_LOAD_NAND: 7981 case ISD::ATOMIC_LOAD_MIN: 7982 case ISD::ATOMIC_LOAD_MAX: 7983 case ISD::ATOMIC_LOAD_UMIN: 7984 case ISD::ATOMIC_LOAD_UMAX: 7985 return SDValue(DAG.UpdateNodeOperands(atomic.getNode(), 7986 fence.getOperand(0), 7987 atomic.getOperand(1), atomic.getOperand(2)), 7988 atomic.getResNo()); 7989 default: 7990 return SDValue(); 7991 } 7992} 7993 7994/// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform 7995/// an AND to a vector_shuffle with the destination vector and a zero vector. 7996/// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==> 7997/// vector_shuffle V, Zero, <0, 4, 2, 4> 7998SDValue DAGCombiner::XformToShuffleWithZero(SDNode *N) { 7999 EVT VT = N->getValueType(0); 8000 DebugLoc dl = N->getDebugLoc(); 8001 SDValue LHS = N->getOperand(0); 8002 SDValue RHS = N->getOperand(1); 8003 if (N->getOpcode() == ISD::AND) { 8004 if (RHS.getOpcode() == ISD::BITCAST) 8005 RHS = RHS.getOperand(0); 8006 if (RHS.getOpcode() == ISD::BUILD_VECTOR) { 8007 SmallVector<int, 8> Indices; 8008 unsigned NumElts = RHS.getNumOperands(); 8009 for (unsigned i = 0; i != NumElts; ++i) { 8010 SDValue Elt = RHS.getOperand(i); 8011 if (!isa<ConstantSDNode>(Elt)) 8012 return SDValue(); 8013 8014 if (cast<ConstantSDNode>(Elt)->isAllOnesValue()) 8015 Indices.push_back(i); 8016 else if (cast<ConstantSDNode>(Elt)->isNullValue()) 8017 Indices.push_back(NumElts); 8018 else 8019 return SDValue(); 8020 } 8021 8022 // Let's see if the target supports this vector_shuffle. 8023 EVT RVT = RHS.getValueType(); 8024 if (!TLI.isVectorClearMaskLegal(Indices, RVT)) 8025 return SDValue(); 8026 8027 // Return the new VECTOR_SHUFFLE node. 8028 EVT EltVT = RVT.getVectorElementType(); 8029 SmallVector<SDValue,8> ZeroOps(RVT.getVectorNumElements(), 8030 DAG.getConstant(0, EltVT)); 8031 SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 8032 RVT, &ZeroOps[0], ZeroOps.size()); 8033 LHS = DAG.getNode(ISD::BITCAST, dl, RVT, LHS); 8034 SDValue Shuf = DAG.getVectorShuffle(RVT, dl, LHS, Zero, &Indices[0]); 8035 return DAG.getNode(ISD::BITCAST, dl, VT, Shuf); 8036 } 8037 } 8038 8039 return SDValue(); 8040} 8041 8042/// SimplifyVBinOp - Visit a binary vector operation, like ADD. 8043SDValue DAGCombiner::SimplifyVBinOp(SDNode *N) { 8044 // After legalize, the target may be depending on adds and other 8045 // binary ops to provide legal ways to construct constants or other 8046 // things. Simplifying them may result in a loss of legality. 8047 if (LegalOperations) return SDValue(); 8048 8049 assert(N->getValueType(0).isVector() && 8050 "SimplifyVBinOp only works on vectors!"); 8051 8052 SDValue LHS = N->getOperand(0); 8053 SDValue RHS = N->getOperand(1); 8054 SDValue Shuffle = XformToShuffleWithZero(N); 8055 if (Shuffle.getNode()) return Shuffle; 8056 8057 // If the LHS and RHS are BUILD_VECTOR nodes, see if we can constant fold 8058 // this operation. 8059 if (LHS.getOpcode() == ISD::BUILD_VECTOR && 8060 RHS.getOpcode() == ISD::BUILD_VECTOR) { 8061 SmallVector<SDValue, 8> Ops; 8062 for (unsigned i = 0, e = LHS.getNumOperands(); i != e; ++i) { 8063 SDValue LHSOp = LHS.getOperand(i); 8064 SDValue RHSOp = RHS.getOperand(i); 8065 // If these two elements can't be folded, bail out. 8066 if ((LHSOp.getOpcode() != ISD::UNDEF && 8067 LHSOp.getOpcode() != ISD::Constant && 8068 LHSOp.getOpcode() != ISD::ConstantFP) || 8069 (RHSOp.getOpcode() != ISD::UNDEF && 8070 RHSOp.getOpcode() != ISD::Constant && 8071 RHSOp.getOpcode() != ISD::ConstantFP)) 8072 break; 8073 8074 // Can't fold divide by zero. 8075 if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV || 8076 N->getOpcode() == ISD::FDIV) { 8077 if ((RHSOp.getOpcode() == ISD::Constant && 8078 cast<ConstantSDNode>(RHSOp.getNode())->isNullValue()) || 8079 (RHSOp.getOpcode() == ISD::ConstantFP && 8080 cast<ConstantFPSDNode>(RHSOp.getNode())->getValueAPF().isZero())) 8081 break; 8082 } 8083 8084 EVT VT = LHSOp.getValueType(); 8085 EVT RVT = RHSOp.getValueType(); 8086 if (RVT != VT) { 8087 // Integer BUILD_VECTOR operands may have types larger than the element 8088 // size (e.g., when the element type is not legal). Prior to type 8089 // legalization, the types may not match between the two BUILD_VECTORS. 8090 // Truncate one of the operands to make them match. 8091 if (RVT.getSizeInBits() > VT.getSizeInBits()) { 8092 RHSOp = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, RHSOp); 8093 } else { 8094 LHSOp = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), RVT, LHSOp); 8095 VT = RVT; 8096 } 8097 } 8098 SDValue FoldOp = DAG.getNode(N->getOpcode(), LHS.getDebugLoc(), VT, 8099 LHSOp, RHSOp); 8100 if (FoldOp.getOpcode() != ISD::UNDEF && 8101 FoldOp.getOpcode() != ISD::Constant && 8102 FoldOp.getOpcode() != ISD::ConstantFP) 8103 break; 8104 Ops.push_back(FoldOp); 8105 AddToWorkList(FoldOp.getNode()); 8106 } 8107 8108 if (Ops.size() == LHS.getNumOperands()) 8109 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 8110 LHS.getValueType(), &Ops[0], Ops.size()); 8111 } 8112 8113 return SDValue(); 8114} 8115 8116SDValue DAGCombiner::SimplifySelect(DebugLoc DL, SDValue N0, 8117 SDValue N1, SDValue N2){ 8118 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!"); 8119 8120 SDValue SCC = SimplifySelectCC(DL, N0.getOperand(0), N0.getOperand(1), N1, N2, 8121 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 8122 8123 // If we got a simplified select_cc node back from SimplifySelectCC, then 8124 // break it down into a new SETCC node, and a new SELECT node, and then return 8125 // the SELECT node, since we were called with a SELECT node. 8126 if (SCC.getNode()) { 8127 // Check to see if we got a select_cc back (to turn into setcc/select). 8128 // Otherwise, just return whatever node we got back, like fabs. 8129 if (SCC.getOpcode() == ISD::SELECT_CC) { 8130 SDValue SETCC = DAG.getNode(ISD::SETCC, N0.getDebugLoc(), 8131 N0.getValueType(), 8132 SCC.getOperand(0), SCC.getOperand(1), 8133 SCC.getOperand(4)); 8134 AddToWorkList(SETCC.getNode()); 8135 return DAG.getNode(ISD::SELECT, SCC.getDebugLoc(), SCC.getValueType(), 8136 SCC.getOperand(2), SCC.getOperand(3), SETCC); 8137 } 8138 8139 return SCC; 8140 } 8141 return SDValue(); 8142} 8143 8144/// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS 8145/// are the two values being selected between, see if we can simplify the 8146/// select. Callers of this should assume that TheSelect is deleted if this 8147/// returns true. As such, they should return the appropriate thing (e.g. the 8148/// node) back to the top-level of the DAG combiner loop to avoid it being 8149/// looked at. 8150bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDValue LHS, 8151 SDValue RHS) { 8152 8153 // Cannot simplify select with vector condition 8154 if (TheSelect->getOperand(0).getValueType().isVector()) return false; 8155 8156 // If this is a select from two identical things, try to pull the operation 8157 // through the select. 8158 if (LHS.getOpcode() != RHS.getOpcode() || 8159 !LHS.hasOneUse() || !RHS.hasOneUse()) 8160 return false; 8161 8162 // If this is a load and the token chain is identical, replace the select 8163 // of two loads with a load through a select of the address to load from. 8164 // This triggers in things like "select bool X, 10.0, 123.0" after the FP 8165 // constants have been dropped into the constant pool. 8166 if (LHS.getOpcode() == ISD::LOAD) { 8167 LoadSDNode *LLD = cast<LoadSDNode>(LHS); 8168 LoadSDNode *RLD = cast<LoadSDNode>(RHS); 8169 8170 // Token chains must be identical. 8171 if (LHS.getOperand(0) != RHS.getOperand(0) || 8172 // Do not let this transformation reduce the number of volatile loads. 8173 LLD->isVolatile() || RLD->isVolatile() || 8174 // If this is an EXTLOAD, the VT's must match. 8175 LLD->getMemoryVT() != RLD->getMemoryVT() || 8176 // If this is an EXTLOAD, the kind of extension must match. 8177 (LLD->getExtensionType() != RLD->getExtensionType() && 8178 // The only exception is if one of the extensions is anyext. 8179 LLD->getExtensionType() != ISD::EXTLOAD && 8180 RLD->getExtensionType() != ISD::EXTLOAD) || 8181 // FIXME: this discards src value information. This is 8182 // over-conservative. It would be beneficial to be able to remember 8183 // both potential memory locations. Since we are discarding 8184 // src value info, don't do the transformation if the memory 8185 // locations are not in the default address space. 8186 LLD->getPointerInfo().getAddrSpace() != 0 || 8187 RLD->getPointerInfo().getAddrSpace() != 0) 8188 return false; 8189 8190 // Check that the select condition doesn't reach either load. If so, 8191 // folding this will induce a cycle into the DAG. If not, this is safe to 8192 // xform, so create a select of the addresses. 8193 SDValue Addr; 8194 if (TheSelect->getOpcode() == ISD::SELECT) { 8195 SDNode *CondNode = TheSelect->getOperand(0).getNode(); 8196 if ((LLD->hasAnyUseOfValue(1) && LLD->isPredecessorOf(CondNode)) || 8197 (RLD->hasAnyUseOfValue(1) && RLD->isPredecessorOf(CondNode))) 8198 return false; 8199 Addr = DAG.getNode(ISD::SELECT, TheSelect->getDebugLoc(), 8200 LLD->getBasePtr().getValueType(), 8201 TheSelect->getOperand(0), LLD->getBasePtr(), 8202 RLD->getBasePtr()); 8203 } else { // Otherwise SELECT_CC 8204 SDNode *CondLHS = TheSelect->getOperand(0).getNode(); 8205 SDNode *CondRHS = TheSelect->getOperand(1).getNode(); 8206 8207 if ((LLD->hasAnyUseOfValue(1) && 8208 (LLD->isPredecessorOf(CondLHS) || LLD->isPredecessorOf(CondRHS))) || 8209 (RLD->hasAnyUseOfValue(1) && 8210 (RLD->isPredecessorOf(CondLHS) || RLD->isPredecessorOf(CondRHS)))) 8211 return false; 8212 8213 Addr = DAG.getNode(ISD::SELECT_CC, TheSelect->getDebugLoc(), 8214 LLD->getBasePtr().getValueType(), 8215 TheSelect->getOperand(0), 8216 TheSelect->getOperand(1), 8217 LLD->getBasePtr(), RLD->getBasePtr(), 8218 TheSelect->getOperand(4)); 8219 } 8220 8221 SDValue Load; 8222 if (LLD->getExtensionType() == ISD::NON_EXTLOAD) { 8223 Load = DAG.getLoad(TheSelect->getValueType(0), 8224 TheSelect->getDebugLoc(), 8225 // FIXME: Discards pointer info. 8226 LLD->getChain(), Addr, MachinePointerInfo(), 8227 LLD->isVolatile(), LLD->isNonTemporal(), 8228 LLD->isInvariant(), LLD->getAlignment()); 8229 } else { 8230 Load = DAG.getExtLoad(LLD->getExtensionType() == ISD::EXTLOAD ? 8231 RLD->getExtensionType() : LLD->getExtensionType(), 8232 TheSelect->getDebugLoc(), 8233 TheSelect->getValueType(0), 8234 // FIXME: Discards pointer info. 8235 LLD->getChain(), Addr, MachinePointerInfo(), 8236 LLD->getMemoryVT(), LLD->isVolatile(), 8237 LLD->isNonTemporal(), LLD->getAlignment()); 8238 } 8239 8240 // Users of the select now use the result of the load. 8241 CombineTo(TheSelect, Load); 8242 8243 // Users of the old loads now use the new load's chain. We know the 8244 // old-load value is dead now. 8245 CombineTo(LHS.getNode(), Load.getValue(0), Load.getValue(1)); 8246 CombineTo(RHS.getNode(), Load.getValue(0), Load.getValue(1)); 8247 return true; 8248 } 8249 8250 return false; 8251} 8252 8253/// SimplifySelectCC - Simplify an expression of the form (N0 cond N1) ? N2 : N3 8254/// where 'cond' is the comparison specified by CC. 8255SDValue DAGCombiner::SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, 8256 SDValue N2, SDValue N3, 8257 ISD::CondCode CC, bool NotExtCompare) { 8258 // (x ? y : y) -> y. 8259 if (N2 == N3) return N2; 8260 8261 EVT VT = N2.getValueType(); 8262 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 8263 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode()); 8264 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.getNode()); 8265 8266 // Determine if the condition we're dealing with is constant 8267 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()), 8268 N0, N1, CC, DL, false); 8269 if (SCC.getNode()) AddToWorkList(SCC.getNode()); 8270 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode()); 8271 8272 // fold select_cc true, x, y -> x 8273 if (SCCC && !SCCC->isNullValue()) 8274 return N2; 8275 // fold select_cc false, x, y -> y 8276 if (SCCC && SCCC->isNullValue()) 8277 return N3; 8278 8279 // Check to see if we can simplify the select into an fabs node 8280 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) { 8281 // Allow either -0.0 or 0.0 8282 if (CFP->getValueAPF().isZero()) { 8283 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs 8284 if ((CC == ISD::SETGE || CC == ISD::SETGT) && 8285 N0 == N2 && N3.getOpcode() == ISD::FNEG && 8286 N2 == N3.getOperand(0)) 8287 return DAG.getNode(ISD::FABS, DL, VT, N0); 8288 8289 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs 8290 if ((CC == ISD::SETLT || CC == ISD::SETLE) && 8291 N0 == N3 && N2.getOpcode() == ISD::FNEG && 8292 N2.getOperand(0) == N3) 8293 return DAG.getNode(ISD::FABS, DL, VT, N3); 8294 } 8295 } 8296 8297 // Turn "(a cond b) ? 1.0f : 2.0f" into "load (tmp + ((a cond b) ? 0 : 4)" 8298 // where "tmp" is a constant pool entry containing an array with 1.0 and 2.0 8299 // in it. This is a win when the constant is not otherwise available because 8300 // it replaces two constant pool loads with one. We only do this if the FP 8301 // type is known to be legal, because if it isn't, then we are before legalize 8302 // types an we want the other legalization to happen first (e.g. to avoid 8303 // messing with soft float) and if the ConstantFP is not legal, because if 8304 // it is legal, we may not need to store the FP constant in a constant pool. 8305 if (ConstantFPSDNode *TV = dyn_cast<ConstantFPSDNode>(N2)) 8306 if (ConstantFPSDNode *FV = dyn_cast<ConstantFPSDNode>(N3)) { 8307 if (TLI.isTypeLegal(N2.getValueType()) && 8308 (TLI.getOperationAction(ISD::ConstantFP, N2.getValueType()) != 8309 TargetLowering::Legal) && 8310 // If both constants have multiple uses, then we won't need to do an 8311 // extra load, they are likely around in registers for other users. 8312 (TV->hasOneUse() || FV->hasOneUse())) { 8313 Constant *Elts[] = { 8314 const_cast<ConstantFP*>(FV->getConstantFPValue()), 8315 const_cast<ConstantFP*>(TV->getConstantFPValue()) 8316 }; 8317 Type *FPTy = Elts[0]->getType(); 8318 const TargetData &TD = *TLI.getTargetData(); 8319 8320 // Create a ConstantArray of the two constants. 8321 Constant *CA = ConstantArray::get(ArrayType::get(FPTy, 2), Elts); 8322 SDValue CPIdx = DAG.getConstantPool(CA, TLI.getPointerTy(), 8323 TD.getPrefTypeAlignment(FPTy)); 8324 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 8325 8326 // Get the offsets to the 0 and 1 element of the array so that we can 8327 // select between them. 8328 SDValue Zero = DAG.getIntPtrConstant(0); 8329 unsigned EltSize = (unsigned)TD.getTypeAllocSize(Elts[0]->getType()); 8330 SDValue One = DAG.getIntPtrConstant(EltSize); 8331 8332 SDValue Cond = DAG.getSetCC(DL, 8333 TLI.getSetCCResultType(N0.getValueType()), 8334 N0, N1, CC); 8335 AddToWorkList(Cond.getNode()); 8336 SDValue CstOffset = DAG.getNode(ISD::SELECT, DL, Zero.getValueType(), 8337 Cond, One, Zero); 8338 AddToWorkList(CstOffset.getNode()); 8339 CPIdx = DAG.getNode(ISD::ADD, DL, TLI.getPointerTy(), CPIdx, 8340 CstOffset); 8341 AddToWorkList(CPIdx.getNode()); 8342 return DAG.getLoad(TV->getValueType(0), DL, DAG.getEntryNode(), CPIdx, 8343 MachinePointerInfo::getConstantPool(), false, 8344 false, false, Alignment); 8345 8346 } 8347 } 8348 8349 // Check to see if we can perform the "gzip trick", transforming 8350 // (select_cc setlt X, 0, A, 0) -> (and (sra X, (sub size(X), 1), A) 8351 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT && 8352 (N1C->isNullValue() || // (a < 0) ? b : 0 8353 (N1C->getAPIntValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0 8354 EVT XType = N0.getValueType(); 8355 EVT AType = N2.getValueType(); 8356 if (XType.bitsGE(AType)) { 8357 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a 8358 // single-bit constant. 8359 if (N2C && ((N2C->getAPIntValue() & (N2C->getAPIntValue()-1)) == 0)) { 8360 unsigned ShCtV = N2C->getAPIntValue().logBase2(); 8361 ShCtV = XType.getSizeInBits()-ShCtV-1; 8362 SDValue ShCt = DAG.getConstant(ShCtV, 8363 getShiftAmountTy(N0.getValueType())); 8364 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), 8365 XType, N0, ShCt); 8366 AddToWorkList(Shift.getNode()); 8367 8368 if (XType.bitsGT(AType)) { 8369 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift); 8370 AddToWorkList(Shift.getNode()); 8371 } 8372 8373 return DAG.getNode(ISD::AND, DL, AType, Shift, N2); 8374 } 8375 8376 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), 8377 XType, N0, 8378 DAG.getConstant(XType.getSizeInBits()-1, 8379 getShiftAmountTy(N0.getValueType()))); 8380 AddToWorkList(Shift.getNode()); 8381 8382 if (XType.bitsGT(AType)) { 8383 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift); 8384 AddToWorkList(Shift.getNode()); 8385 } 8386 8387 return DAG.getNode(ISD::AND, DL, AType, Shift, N2); 8388 } 8389 } 8390 8391 // fold (select_cc seteq (and x, y), 0, 0, A) -> (and (shr (shl x)) A) 8392 // where y is has a single bit set. 8393 // A plaintext description would be, we can turn the SELECT_CC into an AND 8394 // when the condition can be materialized as an all-ones register. Any 8395 // single bit-test can be materialized as an all-ones register with 8396 // shift-left and shift-right-arith. 8397 if (CC == ISD::SETEQ && N0->getOpcode() == ISD::AND && 8398 N0->getValueType(0) == VT && 8399 N1C && N1C->isNullValue() && 8400 N2C && N2C->isNullValue()) { 8401 SDValue AndLHS = N0->getOperand(0); 8402 ConstantSDNode *ConstAndRHS = dyn_cast<ConstantSDNode>(N0->getOperand(1)); 8403 if (ConstAndRHS && ConstAndRHS->getAPIntValue().countPopulation() == 1) { 8404 // Shift the tested bit over the sign bit. 8405 APInt AndMask = ConstAndRHS->getAPIntValue(); 8406 SDValue ShlAmt = 8407 DAG.getConstant(AndMask.countLeadingZeros(), 8408 getShiftAmountTy(AndLHS.getValueType())); 8409 SDValue Shl = DAG.getNode(ISD::SHL, N0.getDebugLoc(), VT, AndLHS, ShlAmt); 8410 8411 // Now arithmetic right shift it all the way over, so the result is either 8412 // all-ones, or zero. 8413 SDValue ShrAmt = 8414 DAG.getConstant(AndMask.getBitWidth()-1, 8415 getShiftAmountTy(Shl.getValueType())); 8416 SDValue Shr = DAG.getNode(ISD::SRA, N0.getDebugLoc(), VT, Shl, ShrAmt); 8417 8418 return DAG.getNode(ISD::AND, DL, VT, Shr, N3); 8419 } 8420 } 8421 8422 // fold select C, 16, 0 -> shl C, 4 8423 if (N2C && N3C && N3C->isNullValue() && N2C->getAPIntValue().isPowerOf2() && 8424 TLI.getBooleanContents(N0.getValueType().isVector()) == 8425 TargetLowering::ZeroOrOneBooleanContent) { 8426 8427 // If the caller doesn't want us to simplify this into a zext of a compare, 8428 // don't do it. 8429 if (NotExtCompare && N2C->getAPIntValue() == 1) 8430 return SDValue(); 8431 8432 // Get a SetCC of the condition 8433 // FIXME: Should probably make sure that setcc is legal if we ever have a 8434 // target where it isn't. 8435 SDValue Temp, SCC; 8436 // cast from setcc result type to select result type 8437 if (LegalTypes) { 8438 SCC = DAG.getSetCC(DL, TLI.getSetCCResultType(N0.getValueType()), 8439 N0, N1, CC); 8440 if (N2.getValueType().bitsLT(SCC.getValueType())) 8441 Temp = DAG.getZeroExtendInReg(SCC, N2.getDebugLoc(), N2.getValueType()); 8442 else 8443 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(), 8444 N2.getValueType(), SCC); 8445 } else { 8446 SCC = DAG.getSetCC(N0.getDebugLoc(), MVT::i1, N0, N1, CC); 8447 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(), 8448 N2.getValueType(), SCC); 8449 } 8450 8451 AddToWorkList(SCC.getNode()); 8452 AddToWorkList(Temp.getNode()); 8453 8454 if (N2C->getAPIntValue() == 1) 8455 return Temp; 8456 8457 // shl setcc result by log2 n2c 8458 return DAG.getNode(ISD::SHL, DL, N2.getValueType(), Temp, 8459 DAG.getConstant(N2C->getAPIntValue().logBase2(), 8460 getShiftAmountTy(Temp.getValueType()))); 8461 } 8462 8463 // Check to see if this is the equivalent of setcc 8464 // FIXME: Turn all of these into setcc if setcc if setcc is legal 8465 // otherwise, go ahead with the folds. 8466 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getAPIntValue() == 1ULL)) { 8467 EVT XType = N0.getValueType(); 8468 if (!LegalOperations || 8469 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(XType))) { 8470 SDValue Res = DAG.getSetCC(DL, TLI.getSetCCResultType(XType), N0, N1, CC); 8471 if (Res.getValueType() != VT) 8472 Res = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, Res); 8473 return Res; 8474 } 8475 8476 // fold (seteq X, 0) -> (srl (ctlz X, log2(size(X)))) 8477 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ && 8478 (!LegalOperations || 8479 TLI.isOperationLegal(ISD::CTLZ, XType))) { 8480 SDValue Ctlz = DAG.getNode(ISD::CTLZ, N0.getDebugLoc(), XType, N0); 8481 return DAG.getNode(ISD::SRL, DL, XType, Ctlz, 8482 DAG.getConstant(Log2_32(XType.getSizeInBits()), 8483 getShiftAmountTy(Ctlz.getValueType()))); 8484 } 8485 // fold (setgt X, 0) -> (srl (and (-X, ~X), size(X)-1)) 8486 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) { 8487 SDValue NegN0 = DAG.getNode(ISD::SUB, N0.getDebugLoc(), 8488 XType, DAG.getConstant(0, XType), N0); 8489 SDValue NotN0 = DAG.getNOT(N0.getDebugLoc(), N0, XType); 8490 return DAG.getNode(ISD::SRL, DL, XType, 8491 DAG.getNode(ISD::AND, DL, XType, NegN0, NotN0), 8492 DAG.getConstant(XType.getSizeInBits()-1, 8493 getShiftAmountTy(XType))); 8494 } 8495 // fold (setgt X, -1) -> (xor (srl (X, size(X)-1), 1)) 8496 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) { 8497 SDValue Sign = DAG.getNode(ISD::SRL, N0.getDebugLoc(), XType, N0, 8498 DAG.getConstant(XType.getSizeInBits()-1, 8499 getShiftAmountTy(N0.getValueType()))); 8500 return DAG.getNode(ISD::XOR, DL, XType, Sign, DAG.getConstant(1, XType)); 8501 } 8502 } 8503 8504 // Check to see if this is an integer abs. 8505 // select_cc setg[te] X, 0, X, -X -> 8506 // select_cc setgt X, -1, X, -X -> 8507 // select_cc setl[te] X, 0, -X, X -> 8508 // select_cc setlt X, 1, -X, X -> 8509 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 8510 if (N1C) { 8511 ConstantSDNode *SubC = NULL; 8512 if (((N1C->isNullValue() && (CC == ISD::SETGT || CC == ISD::SETGE)) || 8513 (N1C->isAllOnesValue() && CC == ISD::SETGT)) && 8514 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1)) 8515 SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0)); 8516 else if (((N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE)) || 8517 (N1C->isOne() && CC == ISD::SETLT)) && 8518 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1)) 8519 SubC = dyn_cast<ConstantSDNode>(N2.getOperand(0)); 8520 8521 EVT XType = N0.getValueType(); 8522 if (SubC && SubC->isNullValue() && XType.isInteger()) { 8523 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), XType, 8524 N0, 8525 DAG.getConstant(XType.getSizeInBits()-1, 8526 getShiftAmountTy(N0.getValueType()))); 8527 SDValue Add = DAG.getNode(ISD::ADD, N0.getDebugLoc(), 8528 XType, N0, Shift); 8529 AddToWorkList(Shift.getNode()); 8530 AddToWorkList(Add.getNode()); 8531 return DAG.getNode(ISD::XOR, DL, XType, Add, Shift); 8532 } 8533 } 8534 8535 return SDValue(); 8536} 8537 8538/// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC. 8539SDValue DAGCombiner::SimplifySetCC(EVT VT, SDValue N0, 8540 SDValue N1, ISD::CondCode Cond, 8541 DebugLoc DL, bool foldBooleans) { 8542 TargetLowering::DAGCombinerInfo 8543 DagCombineInfo(DAG, !LegalTypes, !LegalOperations, false, this); 8544 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo, DL); 8545} 8546 8547/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 8548/// return a DAG expression to select that will generate the same value by 8549/// multiplying by a magic number. See: 8550/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 8551SDValue DAGCombiner::BuildSDIV(SDNode *N) { 8552 std::vector<SDNode*> Built; 8553 SDValue S = TLI.BuildSDIV(N, DAG, LegalOperations, &Built); 8554 8555 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 8556 ii != ee; ++ii) 8557 AddToWorkList(*ii); 8558 return S; 8559} 8560 8561/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 8562/// return a DAG expression to select that will generate the same value by 8563/// multiplying by a magic number. See: 8564/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 8565SDValue DAGCombiner::BuildUDIV(SDNode *N) { 8566 std::vector<SDNode*> Built; 8567 SDValue S = TLI.BuildUDIV(N, DAG, LegalOperations, &Built); 8568 8569 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 8570 ii != ee; ++ii) 8571 AddToWorkList(*ii); 8572 return S; 8573} 8574 8575/// FindBaseOffset - Return true if base is a frame index, which is known not 8576// to alias with anything but itself. Provides base object and offset as 8577// results. 8578static bool FindBaseOffset(SDValue Ptr, SDValue &Base, int64_t &Offset, 8579 const GlobalValue *&GV, void *&CV) { 8580 // Assume it is a primitive operation. 8581 Base = Ptr; Offset = 0; GV = 0; CV = 0; 8582 8583 // If it's an adding a simple constant then integrate the offset. 8584 if (Base.getOpcode() == ISD::ADD) { 8585 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) { 8586 Base = Base.getOperand(0); 8587 Offset += C->getZExtValue(); 8588 } 8589 } 8590 8591 // Return the underlying GlobalValue, and update the Offset. Return false 8592 // for GlobalAddressSDNode since the same GlobalAddress may be represented 8593 // by multiple nodes with different offsets. 8594 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Base)) { 8595 GV = G->getGlobal(); 8596 Offset += G->getOffset(); 8597 return false; 8598 } 8599 8600 // Return the underlying Constant value, and update the Offset. Return false 8601 // for ConstantSDNodes since the same constant pool entry may be represented 8602 // by multiple nodes with different offsets. 8603 if (ConstantPoolSDNode *C = dyn_cast<ConstantPoolSDNode>(Base)) { 8604 CV = C->isMachineConstantPoolEntry() ? (void *)C->getMachineCPVal() 8605 : (void *)C->getConstVal(); 8606 Offset += C->getOffset(); 8607 return false; 8608 } 8609 // If it's any of the following then it can't alias with anything but itself. 8610 return isa<FrameIndexSDNode>(Base); 8611} 8612 8613/// isAlias - Return true if there is any possibility that the two addresses 8614/// overlap. 8615bool DAGCombiner::isAlias(SDValue Ptr1, int64_t Size1, 8616 const Value *SrcValue1, int SrcValueOffset1, 8617 unsigned SrcValueAlign1, 8618 const MDNode *TBAAInfo1, 8619 SDValue Ptr2, int64_t Size2, 8620 const Value *SrcValue2, int SrcValueOffset2, 8621 unsigned SrcValueAlign2, 8622 const MDNode *TBAAInfo2) const { 8623 // If they are the same then they must be aliases. 8624 if (Ptr1 == Ptr2) return true; 8625 8626 // Gather base node and offset information. 8627 SDValue Base1, Base2; 8628 int64_t Offset1, Offset2; 8629 const GlobalValue *GV1, *GV2; 8630 void *CV1, *CV2; 8631 bool isFrameIndex1 = FindBaseOffset(Ptr1, Base1, Offset1, GV1, CV1); 8632 bool isFrameIndex2 = FindBaseOffset(Ptr2, Base2, Offset2, GV2, CV2); 8633 8634 // If they have a same base address then check to see if they overlap. 8635 if (Base1 == Base2 || (GV1 && (GV1 == GV2)) || (CV1 && (CV1 == CV2))) 8636 return !((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1); 8637 8638 // It is possible for different frame indices to alias each other, mostly 8639 // when tail call optimization reuses return address slots for arguments. 8640 // To catch this case, look up the actual index of frame indices to compute 8641 // the real alias relationship. 8642 if (isFrameIndex1 && isFrameIndex2) { 8643 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 8644 Offset1 += MFI->getObjectOffset(cast<FrameIndexSDNode>(Base1)->getIndex()); 8645 Offset2 += MFI->getObjectOffset(cast<FrameIndexSDNode>(Base2)->getIndex()); 8646 return !((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1); 8647 } 8648 8649 // Otherwise, if we know what the bases are, and they aren't identical, then 8650 // we know they cannot alias. 8651 if ((isFrameIndex1 || CV1 || GV1) && (isFrameIndex2 || CV2 || GV2)) 8652 return false; 8653 8654 // If we know required SrcValue1 and SrcValue2 have relatively large alignment 8655 // compared to the size and offset of the access, we may be able to prove they 8656 // do not alias. This check is conservative for now to catch cases created by 8657 // splitting vector types. 8658 if ((SrcValueAlign1 == SrcValueAlign2) && 8659 (SrcValueOffset1 != SrcValueOffset2) && 8660 (Size1 == Size2) && (SrcValueAlign1 > Size1)) { 8661 int64_t OffAlign1 = SrcValueOffset1 % SrcValueAlign1; 8662 int64_t OffAlign2 = SrcValueOffset2 % SrcValueAlign1; 8663 8664 // There is no overlap between these relatively aligned accesses of similar 8665 // size, return no alias. 8666 if ((OffAlign1 + Size1) <= OffAlign2 || (OffAlign2 + Size2) <= OffAlign1) 8667 return false; 8668 } 8669 8670 if (CombinerGlobalAA) { 8671 // Use alias analysis information. 8672 int64_t MinOffset = std::min(SrcValueOffset1, SrcValueOffset2); 8673 int64_t Overlap1 = Size1 + SrcValueOffset1 - MinOffset; 8674 int64_t Overlap2 = Size2 + SrcValueOffset2 - MinOffset; 8675 AliasAnalysis::AliasResult AAResult = 8676 AA.alias(AliasAnalysis::Location(SrcValue1, Overlap1, TBAAInfo1), 8677 AliasAnalysis::Location(SrcValue2, Overlap2, TBAAInfo2)); 8678 if (AAResult == AliasAnalysis::NoAlias) 8679 return false; 8680 } 8681 8682 // Otherwise we have to assume they alias. 8683 return true; 8684} 8685 8686/// FindAliasInfo - Extracts the relevant alias information from the memory 8687/// node. Returns true if the operand was a load. 8688bool DAGCombiner::FindAliasInfo(SDNode *N, 8689 SDValue &Ptr, int64_t &Size, 8690 const Value *&SrcValue, 8691 int &SrcValueOffset, 8692 unsigned &SrcValueAlign, 8693 const MDNode *&TBAAInfo) const { 8694 LSBaseSDNode *LS = cast<LSBaseSDNode>(N); 8695 8696 Ptr = LS->getBasePtr(); 8697 Size = LS->getMemoryVT().getSizeInBits() >> 3; 8698 SrcValue = LS->getSrcValue(); 8699 SrcValueOffset = LS->getSrcValueOffset(); 8700 SrcValueAlign = LS->getOriginalAlignment(); 8701 TBAAInfo = LS->getTBAAInfo(); 8702 return isa<LoadSDNode>(LS); 8703} 8704 8705/// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 8706/// looking for aliasing nodes and adding them to the Aliases vector. 8707void DAGCombiner::GatherAllAliases(SDNode *N, SDValue OriginalChain, 8708 SmallVector<SDValue, 8> &Aliases) { 8709 SmallVector<SDValue, 8> Chains; // List of chains to visit. 8710 SmallPtrSet<SDNode *, 16> Visited; // Visited node set. 8711 8712 // Get alias information for node. 8713 SDValue Ptr; 8714 int64_t Size; 8715 const Value *SrcValue; 8716 int SrcValueOffset; 8717 unsigned SrcValueAlign; 8718 const MDNode *SrcTBAAInfo; 8719 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset, 8720 SrcValueAlign, SrcTBAAInfo); 8721 8722 // Starting off. 8723 Chains.push_back(OriginalChain); 8724 unsigned Depth = 0; 8725 8726 // Look at each chain and determine if it is an alias. If so, add it to the 8727 // aliases list. If not, then continue up the chain looking for the next 8728 // candidate. 8729 while (!Chains.empty()) { 8730 SDValue Chain = Chains.back(); 8731 Chains.pop_back(); 8732 8733 // For TokenFactor nodes, look at each operand and only continue up the 8734 // chain until we find two aliases. If we've seen two aliases, assume we'll 8735 // find more and revert to original chain since the xform is unlikely to be 8736 // profitable. 8737 // 8738 // FIXME: The depth check could be made to return the last non-aliasing 8739 // chain we found before we hit a tokenfactor rather than the original 8740 // chain. 8741 if (Depth > 6 || Aliases.size() == 2) { 8742 Aliases.clear(); 8743 Aliases.push_back(OriginalChain); 8744 break; 8745 } 8746 8747 // Don't bother if we've been before. 8748 if (!Visited.insert(Chain.getNode())) 8749 continue; 8750 8751 switch (Chain.getOpcode()) { 8752 case ISD::EntryToken: 8753 // Entry token is ideal chain operand, but handled in FindBetterChain. 8754 break; 8755 8756 case ISD::LOAD: 8757 case ISD::STORE: { 8758 // Get alias information for Chain. 8759 SDValue OpPtr; 8760 int64_t OpSize; 8761 const Value *OpSrcValue; 8762 int OpSrcValueOffset; 8763 unsigned OpSrcValueAlign; 8764 const MDNode *OpSrcTBAAInfo; 8765 bool IsOpLoad = FindAliasInfo(Chain.getNode(), OpPtr, OpSize, 8766 OpSrcValue, OpSrcValueOffset, 8767 OpSrcValueAlign, 8768 OpSrcTBAAInfo); 8769 8770 // If chain is alias then stop here. 8771 if (!(IsLoad && IsOpLoad) && 8772 isAlias(Ptr, Size, SrcValue, SrcValueOffset, SrcValueAlign, 8773 SrcTBAAInfo, 8774 OpPtr, OpSize, OpSrcValue, OpSrcValueOffset, 8775 OpSrcValueAlign, OpSrcTBAAInfo)) { 8776 Aliases.push_back(Chain); 8777 } else { 8778 // Look further up the chain. 8779 Chains.push_back(Chain.getOperand(0)); 8780 ++Depth; 8781 } 8782 break; 8783 } 8784 8785 case ISD::TokenFactor: 8786 // We have to check each of the operands of the token factor for "small" 8787 // token factors, so we queue them up. Adding the operands to the queue 8788 // (stack) in reverse order maintains the original order and increases the 8789 // likelihood that getNode will find a matching token factor (CSE.) 8790 if (Chain.getNumOperands() > 16) { 8791 Aliases.push_back(Chain); 8792 break; 8793 } 8794 for (unsigned n = Chain.getNumOperands(); n;) 8795 Chains.push_back(Chain.getOperand(--n)); 8796 ++Depth; 8797 break; 8798 8799 default: 8800 // For all other instructions we will just have to take what we can get. 8801 Aliases.push_back(Chain); 8802 break; 8803 } 8804 } 8805} 8806 8807/// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking 8808/// for a better chain (aliasing node.) 8809SDValue DAGCombiner::FindBetterChain(SDNode *N, SDValue OldChain) { 8810 SmallVector<SDValue, 8> Aliases; // Ops for replacing token factor. 8811 8812 // Accumulate all the aliases to this node. 8813 GatherAllAliases(N, OldChain, Aliases); 8814 8815 // If no operands then chain to entry token. 8816 if (Aliases.size() == 0) 8817 return DAG.getEntryNode(); 8818 8819 // If a single operand then chain to it. We don't need to revisit it. 8820 if (Aliases.size() == 1) 8821 return Aliases[0]; 8822 8823 // Construct a custom tailored token factor. 8824 return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, 8825 &Aliases[0], Aliases.size()); 8826} 8827 8828// SelectionDAG::Combine - This is the entry point for the file. 8829// 8830void SelectionDAG::Combine(CombineLevel Level, AliasAnalysis &AA, 8831 CodeGenOpt::Level OptLevel) { 8832 /// run - This is the main entry point to this class. 8833 /// 8834 DAGCombiner(*this, AA, OptLevel).Run(Level); 8835} 8836