DAGCombiner.cpp revision dd201ff1dcbc138cde07fb86896d491134987a2e
1//===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run 11// both before and after the DAG is legalized. 12// 13// This pass is not a substitute for the LLVM IR instcombine pass. This pass is 14// primarily intended to handle simplification opportunities that are implicit 15// in the LLVM IR and exposed by the various codegen lowering phases. 16// 17//===----------------------------------------------------------------------===// 18 19#define DEBUG_TYPE "dagcombine" 20#include "llvm/CodeGen/SelectionDAG.h" 21#include "llvm/DerivedTypes.h" 22#include "llvm/LLVMContext.h" 23#include "llvm/CodeGen/MachineFunction.h" 24#include "llvm/CodeGen/MachineFrameInfo.h" 25#include "llvm/Analysis/AliasAnalysis.h" 26#include "llvm/Target/TargetData.h" 27#include "llvm/Target/TargetLowering.h" 28#include "llvm/Target/TargetMachine.h" 29#include "llvm/Target/TargetOptions.h" 30#include "llvm/ADT/SmallPtrSet.h" 31#include "llvm/ADT/Statistic.h" 32#include "llvm/Support/CommandLine.h" 33#include "llvm/Support/Debug.h" 34#include "llvm/Support/ErrorHandling.h" 35#include "llvm/Support/MathExtras.h" 36#include "llvm/Support/raw_ostream.h" 37#include <algorithm> 38using namespace llvm; 39 40STATISTIC(NodesCombined , "Number of dag nodes combined"); 41STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created"); 42STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created"); 43STATISTIC(OpsNarrowed , "Number of load/op/store narrowed"); 44STATISTIC(LdStFP2Int , "Number of fp load/store pairs transformed to int"); 45 46namespace { 47 static cl::opt<bool> 48 CombinerAA("combiner-alias-analysis", cl::Hidden, 49 cl::desc("Turn on alias analysis during testing")); 50 51 static cl::opt<bool> 52 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden, 53 cl::desc("Include global information in alias analysis")); 54 55//------------------------------ DAGCombiner ---------------------------------// 56 57 class DAGCombiner { 58 SelectionDAG &DAG; 59 const TargetLowering &TLI; 60 CombineLevel Level; 61 CodeGenOpt::Level OptLevel; 62 bool LegalOperations; 63 bool LegalTypes; 64 65 // Worklist of all of the nodes that need to be simplified. 66 // 67 // This has the semantics that when adding to the worklist, 68 // the item added must be next to be processed. It should 69 // also only appear once. The naive approach to this takes 70 // linear time. 71 // 72 // To reduce the insert/remove time to logarithmic, we use 73 // a set and a vector to maintain our worklist. 74 // 75 // The set contains the items on the worklist, but does not 76 // maintain the order they should be visited. 77 // 78 // The vector maintains the order nodes should be visited, but may 79 // contain duplicate or removed nodes. When choosing a node to 80 // visit, we pop off the order stack until we find an item that is 81 // also in the contents set. All operations are O(log N). 82 SmallPtrSet<SDNode*, 64> WorkListContents; 83 SmallVector<SDNode*, 64> WorkListOrder; 84 85 // AA - Used for DAG load/store alias analysis. 86 AliasAnalysis &AA; 87 88 /// AddUsersToWorkList - When an instruction is simplified, add all users of 89 /// the instruction to the work lists because they might get more simplified 90 /// now. 91 /// 92 void AddUsersToWorkList(SDNode *N) { 93 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 94 UI != UE; ++UI) 95 AddToWorkList(*UI); 96 } 97 98 /// visit - call the node-specific routine that knows how to fold each 99 /// particular type of node. 100 SDValue visit(SDNode *N); 101 102 public: 103 /// AddToWorkList - Add to the work list making sure its instance is at the 104 /// back (next to be processed.) 105 void AddToWorkList(SDNode *N) { 106 WorkListContents.insert(N); 107 WorkListOrder.push_back(N); 108 } 109 110 /// removeFromWorkList - remove all instances of N from the worklist. 111 /// 112 void removeFromWorkList(SDNode *N) { 113 WorkListContents.erase(N); 114 } 115 116 SDValue CombineTo(SDNode *N, const SDValue *To, unsigned NumTo, 117 bool AddTo = true); 118 119 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true) { 120 return CombineTo(N, &Res, 1, AddTo); 121 } 122 123 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, 124 bool AddTo = true) { 125 SDValue To[] = { Res0, Res1 }; 126 return CombineTo(N, To, 2, AddTo); 127 } 128 129 void CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO); 130 131 private: 132 133 /// SimplifyDemandedBits - Check the specified integer node value to see if 134 /// it can be simplified or if things it uses can be simplified by bit 135 /// propagation. If so, return true. 136 bool SimplifyDemandedBits(SDValue Op) { 137 unsigned BitWidth = Op.getValueType().getScalarType().getSizeInBits(); 138 APInt Demanded = APInt::getAllOnesValue(BitWidth); 139 return SimplifyDemandedBits(Op, Demanded); 140 } 141 142 bool SimplifyDemandedBits(SDValue Op, const APInt &Demanded); 143 144 bool CombineToPreIndexedLoadStore(SDNode *N); 145 bool CombineToPostIndexedLoadStore(SDNode *N); 146 147 void ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad); 148 SDValue PromoteOperand(SDValue Op, EVT PVT, bool &Replace); 149 SDValue SExtPromoteOperand(SDValue Op, EVT PVT); 150 SDValue ZExtPromoteOperand(SDValue Op, EVT PVT); 151 SDValue PromoteIntBinOp(SDValue Op); 152 SDValue PromoteIntShiftOp(SDValue Op); 153 SDValue PromoteExtend(SDValue Op); 154 bool PromoteLoad(SDValue Op); 155 156 void ExtendSetCCUses(SmallVector<SDNode*, 4> SetCCs, 157 SDValue Trunc, SDValue ExtLoad, DebugLoc DL, 158 ISD::NodeType ExtType); 159 160 /// combine - call the node-specific routine that knows how to fold each 161 /// particular type of node. If that doesn't do anything, try the 162 /// target-specific DAG combines. 163 SDValue combine(SDNode *N); 164 165 // Visitation implementation - Implement dag node combining for different 166 // node types. The semantics are as follows: 167 // Return Value: 168 // SDValue.getNode() == 0 - No change was made 169 // SDValue.getNode() == N - N was replaced, is dead and has been handled. 170 // otherwise - N should be replaced by the returned Operand. 171 // 172 SDValue visitTokenFactor(SDNode *N); 173 SDValue visitMERGE_VALUES(SDNode *N); 174 SDValue visitADD(SDNode *N); 175 SDValue visitSUB(SDNode *N); 176 SDValue visitADDC(SDNode *N); 177 SDValue visitSUBC(SDNode *N); 178 SDValue visitADDE(SDNode *N); 179 SDValue visitSUBE(SDNode *N); 180 SDValue visitMUL(SDNode *N); 181 SDValue visitSDIV(SDNode *N); 182 SDValue visitUDIV(SDNode *N); 183 SDValue visitSREM(SDNode *N); 184 SDValue visitUREM(SDNode *N); 185 SDValue visitMULHU(SDNode *N); 186 SDValue visitMULHS(SDNode *N); 187 SDValue visitSMUL_LOHI(SDNode *N); 188 SDValue visitUMUL_LOHI(SDNode *N); 189 SDValue visitSMULO(SDNode *N); 190 SDValue visitUMULO(SDNode *N); 191 SDValue visitSDIVREM(SDNode *N); 192 SDValue visitUDIVREM(SDNode *N); 193 SDValue visitAND(SDNode *N); 194 SDValue visitOR(SDNode *N); 195 SDValue visitXOR(SDNode *N); 196 SDValue SimplifyVBinOp(SDNode *N); 197 SDValue SimplifyVUnaryOp(SDNode *N); 198 SDValue visitSHL(SDNode *N); 199 SDValue visitSRA(SDNode *N); 200 SDValue visitSRL(SDNode *N); 201 SDValue visitCTLZ(SDNode *N); 202 SDValue visitCTLZ_ZERO_UNDEF(SDNode *N); 203 SDValue visitCTTZ(SDNode *N); 204 SDValue visitCTTZ_ZERO_UNDEF(SDNode *N); 205 SDValue visitCTPOP(SDNode *N); 206 SDValue visitSELECT(SDNode *N); 207 SDValue visitSELECT_CC(SDNode *N); 208 SDValue visitSETCC(SDNode *N); 209 SDValue visitSIGN_EXTEND(SDNode *N); 210 SDValue visitZERO_EXTEND(SDNode *N); 211 SDValue visitANY_EXTEND(SDNode *N); 212 SDValue visitSIGN_EXTEND_INREG(SDNode *N); 213 SDValue visitTRUNCATE(SDNode *N); 214 SDValue visitBITCAST(SDNode *N); 215 SDValue visitBUILD_PAIR(SDNode *N); 216 SDValue visitFADD(SDNode *N); 217 SDValue visitFSUB(SDNode *N); 218 SDValue visitFMUL(SDNode *N); 219 SDValue visitFMA(SDNode *N); 220 SDValue visitFDIV(SDNode *N); 221 SDValue visitFREM(SDNode *N); 222 SDValue visitFCOPYSIGN(SDNode *N); 223 SDValue visitSINT_TO_FP(SDNode *N); 224 SDValue visitUINT_TO_FP(SDNode *N); 225 SDValue visitFP_TO_SINT(SDNode *N); 226 SDValue visitFP_TO_UINT(SDNode *N); 227 SDValue visitFP_ROUND(SDNode *N); 228 SDValue visitFP_ROUND_INREG(SDNode *N); 229 SDValue visitFP_EXTEND(SDNode *N); 230 SDValue visitFNEG(SDNode *N); 231 SDValue visitFABS(SDNode *N); 232 SDValue visitFCEIL(SDNode *N); 233 SDValue visitFTRUNC(SDNode *N); 234 SDValue visitFFLOOR(SDNode *N); 235 SDValue visitBRCOND(SDNode *N); 236 SDValue visitBR_CC(SDNode *N); 237 SDValue visitLOAD(SDNode *N); 238 SDValue visitSTORE(SDNode *N); 239 SDValue visitINSERT_VECTOR_ELT(SDNode *N); 240 SDValue visitEXTRACT_VECTOR_ELT(SDNode *N); 241 SDValue visitBUILD_VECTOR(SDNode *N); 242 SDValue visitCONCAT_VECTORS(SDNode *N); 243 SDValue visitEXTRACT_SUBVECTOR(SDNode *N); 244 SDValue visitVECTOR_SHUFFLE(SDNode *N); 245 SDValue visitMEMBARRIER(SDNode *N); 246 247 SDValue XformToShuffleWithZero(SDNode *N); 248 SDValue ReassociateOps(unsigned Opc, DebugLoc DL, SDValue LHS, SDValue RHS); 249 250 SDValue visitShiftByConstant(SDNode *N, unsigned Amt); 251 252 bool SimplifySelectOps(SDNode *SELECT, SDValue LHS, SDValue RHS); 253 SDValue SimplifyBinOpWithSameOpcodeHands(SDNode *N); 254 SDValue SimplifySelect(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2); 255 SDValue SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2, 256 SDValue N3, ISD::CondCode CC, 257 bool NotExtCompare = false); 258 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond, 259 DebugLoc DL, bool foldBooleans = true); 260 SDValue SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 261 unsigned HiOp); 262 SDValue CombineConsecutiveLoads(SDNode *N, EVT VT); 263 SDValue ConstantFoldBITCASTofBUILD_VECTOR(SDNode *, EVT); 264 SDValue BuildSDIV(SDNode *N); 265 SDValue BuildUDIV(SDNode *N); 266 SDValue MatchBSwapHWordLow(SDNode *N, SDValue N0, SDValue N1, 267 bool DemandHighBits = true); 268 SDValue MatchBSwapHWord(SDNode *N, SDValue N0, SDValue N1); 269 SDNode *MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL); 270 SDValue ReduceLoadWidth(SDNode *N); 271 SDValue ReduceLoadOpStoreWidth(SDNode *N); 272 SDValue TransformFPLoadStorePair(SDNode *N); 273 274 SDValue GetDemandedBits(SDValue V, const APInt &Mask); 275 276 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 277 /// looking for aliasing nodes and adding them to the Aliases vector. 278 void GatherAllAliases(SDNode *N, SDValue OriginalChain, 279 SmallVector<SDValue, 8> &Aliases); 280 281 /// isAlias - Return true if there is any possibility that the two addresses 282 /// overlap. 283 bool isAlias(SDValue Ptr1, int64_t Size1, 284 const Value *SrcValue1, int SrcValueOffset1, 285 unsigned SrcValueAlign1, 286 const MDNode *TBAAInfo1, 287 SDValue Ptr2, int64_t Size2, 288 const Value *SrcValue2, int SrcValueOffset2, 289 unsigned SrcValueAlign2, 290 const MDNode *TBAAInfo2) const; 291 292 /// FindAliasInfo - Extracts the relevant alias information from the memory 293 /// node. Returns true if the operand was a load. 294 bool FindAliasInfo(SDNode *N, 295 SDValue &Ptr, int64_t &Size, 296 const Value *&SrcValue, int &SrcValueOffset, 297 unsigned &SrcValueAlignment, 298 const MDNode *&TBAAInfo) const; 299 300 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, 301 /// looking for a better chain (aliasing node.) 302 SDValue FindBetterChain(SDNode *N, SDValue Chain); 303 304 public: 305 DAGCombiner(SelectionDAG &D, AliasAnalysis &A, CodeGenOpt::Level OL) 306 : DAG(D), TLI(D.getTargetLoweringInfo()), Level(BeforeLegalizeTypes), 307 OptLevel(OL), LegalOperations(false), LegalTypes(false), AA(A) {} 308 309 /// Run - runs the dag combiner on all nodes in the work list 310 void Run(CombineLevel AtLevel); 311 312 SelectionDAG &getDAG() const { return DAG; } 313 314 /// getShiftAmountTy - Returns a type large enough to hold any valid 315 /// shift amount - before type legalization these can be huge. 316 EVT getShiftAmountTy(EVT LHSTy) { 317 return LegalTypes ? TLI.getShiftAmountTy(LHSTy) : TLI.getPointerTy(); 318 } 319 320 /// isTypeLegal - This method returns true if we are running before type 321 /// legalization or if the specified VT is legal. 322 bool isTypeLegal(const EVT &VT) { 323 if (!LegalTypes) return true; 324 return TLI.isTypeLegal(VT); 325 } 326 }; 327} 328 329 330namespace { 331/// WorkListRemover - This class is a DAGUpdateListener that removes any deleted 332/// nodes from the worklist. 333class WorkListRemover : public SelectionDAG::DAGUpdateListener { 334 DAGCombiner &DC; 335public: 336 explicit WorkListRemover(DAGCombiner &dc) 337 : SelectionDAG::DAGUpdateListener(dc.getDAG()), DC(dc) {} 338 339 virtual void NodeDeleted(SDNode *N, SDNode *E) { 340 DC.removeFromWorkList(N); 341 } 342}; 343} 344 345//===----------------------------------------------------------------------===// 346// TargetLowering::DAGCombinerInfo implementation 347//===----------------------------------------------------------------------===// 348 349void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) { 350 ((DAGCombiner*)DC)->AddToWorkList(N); 351} 352 353void TargetLowering::DAGCombinerInfo::RemoveFromWorklist(SDNode *N) { 354 ((DAGCombiner*)DC)->removeFromWorkList(N); 355} 356 357SDValue TargetLowering::DAGCombinerInfo:: 358CombineTo(SDNode *N, const std::vector<SDValue> &To, bool AddTo) { 359 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size(), AddTo); 360} 361 362SDValue TargetLowering::DAGCombinerInfo:: 363CombineTo(SDNode *N, SDValue Res, bool AddTo) { 364 return ((DAGCombiner*)DC)->CombineTo(N, Res, AddTo); 365} 366 367 368SDValue TargetLowering::DAGCombinerInfo:: 369CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo) { 370 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1, AddTo); 371} 372 373void TargetLowering::DAGCombinerInfo:: 374CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) { 375 return ((DAGCombiner*)DC)->CommitTargetLoweringOpt(TLO); 376} 377 378//===----------------------------------------------------------------------===// 379// Helper Functions 380//===----------------------------------------------------------------------===// 381 382/// isNegatibleForFree - Return 1 if we can compute the negated form of the 383/// specified expression for the same cost as the expression itself, or 2 if we 384/// can compute the negated form more cheaply than the expression itself. 385static char isNegatibleForFree(SDValue Op, bool LegalOperations, 386 const TargetLowering &TLI, 387 const TargetOptions *Options, 388 unsigned Depth = 0) { 389 // No compile time optimizations on this type. 390 if (Op.getValueType() == MVT::ppcf128) 391 return 0; 392 393 // fneg is removable even if it has multiple uses. 394 if (Op.getOpcode() == ISD::FNEG) return 2; 395 396 // Don't allow anything with multiple uses. 397 if (!Op.hasOneUse()) return 0; 398 399 // Don't recurse exponentially. 400 if (Depth > 6) return 0; 401 402 switch (Op.getOpcode()) { 403 default: return false; 404 case ISD::ConstantFP: 405 // Don't invert constant FP values after legalize. The negated constant 406 // isn't necessarily legal. 407 return LegalOperations ? 0 : 1; 408 case ISD::FADD: 409 // FIXME: determine better conditions for this xform. 410 if (!Options->UnsafeFPMath) return 0; 411 412 // After operation legalization, it might not be legal to create new FSUBs. 413 if (LegalOperations && 414 !TLI.isOperationLegalOrCustom(ISD::FSUB, Op.getValueType())) 415 return 0; 416 417 // fold (fneg (fadd A, B)) -> (fsub (fneg A), B) 418 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI, 419 Options, Depth + 1)) 420 return V; 421 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A) 422 return isNegatibleForFree(Op.getOperand(1), LegalOperations, TLI, Options, 423 Depth + 1); 424 case ISD::FSUB: 425 // We can't turn -(A-B) into B-A when we honor signed zeros. 426 if (!Options->UnsafeFPMath) return 0; 427 428 // fold (fneg (fsub A, B)) -> (fsub B, A) 429 return 1; 430 431 case ISD::FMUL: 432 case ISD::FDIV: 433 if (Options->HonorSignDependentRoundingFPMath()) return 0; 434 435 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) or (fmul X, (fneg Y)) 436 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI, 437 Options, Depth + 1)) 438 return V; 439 440 return isNegatibleForFree(Op.getOperand(1), LegalOperations, TLI, Options, 441 Depth + 1); 442 443 case ISD::FP_EXTEND: 444 case ISD::FP_ROUND: 445 case ISD::FSIN: 446 return isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI, Options, 447 Depth + 1); 448 } 449} 450 451/// GetNegatedExpression - If isNegatibleForFree returns true, this function 452/// returns the newly negated expression. 453static SDValue GetNegatedExpression(SDValue Op, SelectionDAG &DAG, 454 bool LegalOperations, unsigned Depth = 0) { 455 // fneg is removable even if it has multiple uses. 456 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0); 457 458 // Don't allow anything with multiple uses. 459 assert(Op.hasOneUse() && "Unknown reuse!"); 460 461 assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree"); 462 switch (Op.getOpcode()) { 463 default: llvm_unreachable("Unknown code"); 464 case ISD::ConstantFP: { 465 APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF(); 466 V.changeSign(); 467 return DAG.getConstantFP(V, Op.getValueType()); 468 } 469 case ISD::FADD: 470 // FIXME: determine better conditions for this xform. 471 assert(DAG.getTarget().Options.UnsafeFPMath); 472 473 // fold (fneg (fadd A, B)) -> (fsub (fneg A), B) 474 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, 475 DAG.getTargetLoweringInfo(), 476 &DAG.getTarget().Options, Depth+1)) 477 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 478 GetNegatedExpression(Op.getOperand(0), DAG, 479 LegalOperations, Depth+1), 480 Op.getOperand(1)); 481 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A) 482 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 483 GetNegatedExpression(Op.getOperand(1), DAG, 484 LegalOperations, Depth+1), 485 Op.getOperand(0)); 486 case ISD::FSUB: 487 // We can't turn -(A-B) into B-A when we honor signed zeros. 488 assert(DAG.getTarget().Options.UnsafeFPMath); 489 490 // fold (fneg (fsub 0, B)) -> B 491 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(Op.getOperand(0))) 492 if (N0CFP->getValueAPF().isZero()) 493 return Op.getOperand(1); 494 495 // fold (fneg (fsub A, B)) -> (fsub B, A) 496 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 497 Op.getOperand(1), Op.getOperand(0)); 498 499 case ISD::FMUL: 500 case ISD::FDIV: 501 assert(!DAG.getTarget().Options.HonorSignDependentRoundingFPMath()); 502 503 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) 504 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, 505 DAG.getTargetLoweringInfo(), 506 &DAG.getTarget().Options, Depth+1)) 507 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 508 GetNegatedExpression(Op.getOperand(0), DAG, 509 LegalOperations, Depth+1), 510 Op.getOperand(1)); 511 512 // fold (fneg (fmul X, Y)) -> (fmul X, (fneg Y)) 513 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 514 Op.getOperand(0), 515 GetNegatedExpression(Op.getOperand(1), DAG, 516 LegalOperations, Depth+1)); 517 518 case ISD::FP_EXTEND: 519 case ISD::FSIN: 520 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 521 GetNegatedExpression(Op.getOperand(0), DAG, 522 LegalOperations, Depth+1)); 523 case ISD::FP_ROUND: 524 return DAG.getNode(ISD::FP_ROUND, Op.getDebugLoc(), Op.getValueType(), 525 GetNegatedExpression(Op.getOperand(0), DAG, 526 LegalOperations, Depth+1), 527 Op.getOperand(1)); 528 } 529} 530 531 532// isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc 533// that selects between the values 1 and 0, making it equivalent to a setcc. 534// Also, set the incoming LHS, RHS, and CC references to the appropriate 535// nodes based on the type of node we are checking. This simplifies life a 536// bit for the callers. 537static bool isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS, 538 SDValue &CC) { 539 if (N.getOpcode() == ISD::SETCC) { 540 LHS = N.getOperand(0); 541 RHS = N.getOperand(1); 542 CC = N.getOperand(2); 543 return true; 544 } 545 if (N.getOpcode() == ISD::SELECT_CC && 546 N.getOperand(2).getOpcode() == ISD::Constant && 547 N.getOperand(3).getOpcode() == ISD::Constant && 548 cast<ConstantSDNode>(N.getOperand(2))->getAPIntValue() == 1 && 549 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) { 550 LHS = N.getOperand(0); 551 RHS = N.getOperand(1); 552 CC = N.getOperand(4); 553 return true; 554 } 555 return false; 556} 557 558// isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only 559// one use. If this is true, it allows the users to invert the operation for 560// free when it is profitable to do so. 561static bool isOneUseSetCC(SDValue N) { 562 SDValue N0, N1, N2; 563 if (isSetCCEquivalent(N, N0, N1, N2) && N.getNode()->hasOneUse()) 564 return true; 565 return false; 566} 567 568SDValue DAGCombiner::ReassociateOps(unsigned Opc, DebugLoc DL, 569 SDValue N0, SDValue N1) { 570 EVT VT = N0.getValueType(); 571 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) { 572 if (isa<ConstantSDNode>(N1)) { 573 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2)) 574 SDValue OpNode = 575 DAG.FoldConstantArithmetic(Opc, VT, 576 cast<ConstantSDNode>(N0.getOperand(1)), 577 cast<ConstantSDNode>(N1)); 578 return DAG.getNode(Opc, DL, VT, N0.getOperand(0), OpNode); 579 } 580 if (N0.hasOneUse()) { 581 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use 582 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT, 583 N0.getOperand(0), N1); 584 AddToWorkList(OpNode.getNode()); 585 return DAG.getNode(Opc, DL, VT, OpNode, N0.getOperand(1)); 586 } 587 } 588 589 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) { 590 if (isa<ConstantSDNode>(N0)) { 591 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2)) 592 SDValue OpNode = 593 DAG.FoldConstantArithmetic(Opc, VT, 594 cast<ConstantSDNode>(N1.getOperand(1)), 595 cast<ConstantSDNode>(N0)); 596 return DAG.getNode(Opc, DL, VT, N1.getOperand(0), OpNode); 597 } 598 if (N1.hasOneUse()) { 599 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use 600 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT, 601 N1.getOperand(0), N0); 602 AddToWorkList(OpNode.getNode()); 603 return DAG.getNode(Opc, DL, VT, OpNode, N1.getOperand(1)); 604 } 605 } 606 607 return SDValue(); 608} 609 610SDValue DAGCombiner::CombineTo(SDNode *N, const SDValue *To, unsigned NumTo, 611 bool AddTo) { 612 assert(N->getNumValues() == NumTo && "Broken CombineTo call!"); 613 ++NodesCombined; 614 DEBUG(dbgs() << "\nReplacing.1 "; 615 N->dump(&DAG); 616 dbgs() << "\nWith: "; 617 To[0].getNode()->dump(&DAG); 618 dbgs() << " and " << NumTo-1 << " other values\n"; 619 for (unsigned i = 0, e = NumTo; i != e; ++i) 620 assert((!To[i].getNode() || 621 N->getValueType(i) == To[i].getValueType()) && 622 "Cannot combine value to value of different type!")); 623 WorkListRemover DeadNodes(*this); 624 DAG.ReplaceAllUsesWith(N, To); 625 if (AddTo) { 626 // Push the new nodes and any users onto the worklist 627 for (unsigned i = 0, e = NumTo; i != e; ++i) { 628 if (To[i].getNode()) { 629 AddToWorkList(To[i].getNode()); 630 AddUsersToWorkList(To[i].getNode()); 631 } 632 } 633 } 634 635 // Finally, if the node is now dead, remove it from the graph. The node 636 // may not be dead if the replacement process recursively simplified to 637 // something else needing this node. 638 if (N->use_empty()) { 639 // Nodes can be reintroduced into the worklist. Make sure we do not 640 // process a node that has been replaced. 641 removeFromWorkList(N); 642 643 // Finally, since the node is now dead, remove it from the graph. 644 DAG.DeleteNode(N); 645 } 646 return SDValue(N, 0); 647} 648 649void DAGCombiner:: 650CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) { 651 // Replace all uses. If any nodes become isomorphic to other nodes and 652 // are deleted, make sure to remove them from our worklist. 653 WorkListRemover DeadNodes(*this); 654 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New); 655 656 // Push the new node and any (possibly new) users onto the worklist. 657 AddToWorkList(TLO.New.getNode()); 658 AddUsersToWorkList(TLO.New.getNode()); 659 660 // Finally, if the node is now dead, remove it from the graph. The node 661 // may not be dead if the replacement process recursively simplified to 662 // something else needing this node. 663 if (TLO.Old.getNode()->use_empty()) { 664 removeFromWorkList(TLO.Old.getNode()); 665 666 // If the operands of this node are only used by the node, they will now 667 // be dead. Make sure to visit them first to delete dead nodes early. 668 for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands(); i != e; ++i) 669 if (TLO.Old.getNode()->getOperand(i).getNode()->hasOneUse()) 670 AddToWorkList(TLO.Old.getNode()->getOperand(i).getNode()); 671 672 DAG.DeleteNode(TLO.Old.getNode()); 673 } 674} 675 676/// SimplifyDemandedBits - Check the specified integer node value to see if 677/// it can be simplified or if things it uses can be simplified by bit 678/// propagation. If so, return true. 679bool DAGCombiner::SimplifyDemandedBits(SDValue Op, const APInt &Demanded) { 680 TargetLowering::TargetLoweringOpt TLO(DAG, LegalTypes, LegalOperations); 681 APInt KnownZero, KnownOne; 682 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO)) 683 return false; 684 685 // Revisit the node. 686 AddToWorkList(Op.getNode()); 687 688 // Replace the old value with the new one. 689 ++NodesCombined; 690 DEBUG(dbgs() << "\nReplacing.2 "; 691 TLO.Old.getNode()->dump(&DAG); 692 dbgs() << "\nWith: "; 693 TLO.New.getNode()->dump(&DAG); 694 dbgs() << '\n'); 695 696 CommitTargetLoweringOpt(TLO); 697 return true; 698} 699 700void DAGCombiner::ReplaceLoadWithPromotedLoad(SDNode *Load, SDNode *ExtLoad) { 701 DebugLoc dl = Load->getDebugLoc(); 702 EVT VT = Load->getValueType(0); 703 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, VT, SDValue(ExtLoad, 0)); 704 705 DEBUG(dbgs() << "\nReplacing.9 "; 706 Load->dump(&DAG); 707 dbgs() << "\nWith: "; 708 Trunc.getNode()->dump(&DAG); 709 dbgs() << '\n'); 710 WorkListRemover DeadNodes(*this); 711 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 0), Trunc); 712 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 1), SDValue(ExtLoad, 1)); 713 removeFromWorkList(Load); 714 DAG.DeleteNode(Load); 715 AddToWorkList(Trunc.getNode()); 716} 717 718SDValue DAGCombiner::PromoteOperand(SDValue Op, EVT PVT, bool &Replace) { 719 Replace = false; 720 DebugLoc dl = Op.getDebugLoc(); 721 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Op)) { 722 EVT MemVT = LD->getMemoryVT(); 723 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD) 724 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT) ? ISD::ZEXTLOAD 725 : ISD::EXTLOAD) 726 : LD->getExtensionType(); 727 Replace = true; 728 return DAG.getExtLoad(ExtType, dl, PVT, 729 LD->getChain(), LD->getBasePtr(), 730 LD->getPointerInfo(), 731 MemVT, LD->isVolatile(), 732 LD->isNonTemporal(), LD->getAlignment()); 733 } 734 735 unsigned Opc = Op.getOpcode(); 736 switch (Opc) { 737 default: break; 738 case ISD::AssertSext: 739 return DAG.getNode(ISD::AssertSext, dl, PVT, 740 SExtPromoteOperand(Op.getOperand(0), PVT), 741 Op.getOperand(1)); 742 case ISD::AssertZext: 743 return DAG.getNode(ISD::AssertZext, dl, PVT, 744 ZExtPromoteOperand(Op.getOperand(0), PVT), 745 Op.getOperand(1)); 746 case ISD::Constant: { 747 unsigned ExtOpc = 748 Op.getValueType().isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; 749 return DAG.getNode(ExtOpc, dl, PVT, Op); 750 } 751 } 752 753 if (!TLI.isOperationLegal(ISD::ANY_EXTEND, PVT)) 754 return SDValue(); 755 return DAG.getNode(ISD::ANY_EXTEND, dl, PVT, Op); 756} 757 758SDValue DAGCombiner::SExtPromoteOperand(SDValue Op, EVT PVT) { 759 if (!TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, PVT)) 760 return SDValue(); 761 EVT OldVT = Op.getValueType(); 762 DebugLoc dl = Op.getDebugLoc(); 763 bool Replace = false; 764 SDValue NewOp = PromoteOperand(Op, PVT, Replace); 765 if (NewOp.getNode() == 0) 766 return SDValue(); 767 AddToWorkList(NewOp.getNode()); 768 769 if (Replace) 770 ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode()); 771 return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, NewOp.getValueType(), NewOp, 772 DAG.getValueType(OldVT)); 773} 774 775SDValue DAGCombiner::ZExtPromoteOperand(SDValue Op, EVT PVT) { 776 EVT OldVT = Op.getValueType(); 777 DebugLoc dl = Op.getDebugLoc(); 778 bool Replace = false; 779 SDValue NewOp = PromoteOperand(Op, PVT, Replace); 780 if (NewOp.getNode() == 0) 781 return SDValue(); 782 AddToWorkList(NewOp.getNode()); 783 784 if (Replace) 785 ReplaceLoadWithPromotedLoad(Op.getNode(), NewOp.getNode()); 786 return DAG.getZeroExtendInReg(NewOp, dl, OldVT); 787} 788 789/// PromoteIntBinOp - Promote the specified integer binary operation if the 790/// target indicates it is beneficial. e.g. On x86, it's usually better to 791/// promote i16 operations to i32 since i16 instructions are longer. 792SDValue DAGCombiner::PromoteIntBinOp(SDValue Op) { 793 if (!LegalOperations) 794 return SDValue(); 795 796 EVT VT = Op.getValueType(); 797 if (VT.isVector() || !VT.isInteger()) 798 return SDValue(); 799 800 // If operation type is 'undesirable', e.g. i16 on x86, consider 801 // promoting it. 802 unsigned Opc = Op.getOpcode(); 803 if (TLI.isTypeDesirableForOp(Opc, VT)) 804 return SDValue(); 805 806 EVT PVT = VT; 807 // Consult target whether it is a good idea to promote this operation and 808 // what's the right type to promote it to. 809 if (TLI.IsDesirableToPromoteOp(Op, PVT)) { 810 assert(PVT != VT && "Don't know what type to promote to!"); 811 812 bool Replace0 = false; 813 SDValue N0 = Op.getOperand(0); 814 SDValue NN0 = PromoteOperand(N0, PVT, Replace0); 815 if (NN0.getNode() == 0) 816 return SDValue(); 817 818 bool Replace1 = false; 819 SDValue N1 = Op.getOperand(1); 820 SDValue NN1; 821 if (N0 == N1) 822 NN1 = NN0; 823 else { 824 NN1 = PromoteOperand(N1, PVT, Replace1); 825 if (NN1.getNode() == 0) 826 return SDValue(); 827 } 828 829 AddToWorkList(NN0.getNode()); 830 if (NN1.getNode()) 831 AddToWorkList(NN1.getNode()); 832 833 if (Replace0) 834 ReplaceLoadWithPromotedLoad(N0.getNode(), NN0.getNode()); 835 if (Replace1) 836 ReplaceLoadWithPromotedLoad(N1.getNode(), NN1.getNode()); 837 838 DEBUG(dbgs() << "\nPromoting "; 839 Op.getNode()->dump(&DAG)); 840 DebugLoc dl = Op.getDebugLoc(); 841 return DAG.getNode(ISD::TRUNCATE, dl, VT, 842 DAG.getNode(Opc, dl, PVT, NN0, NN1)); 843 } 844 return SDValue(); 845} 846 847/// PromoteIntShiftOp - Promote the specified integer shift operation if the 848/// target indicates it is beneficial. e.g. On x86, it's usually better to 849/// promote i16 operations to i32 since i16 instructions are longer. 850SDValue DAGCombiner::PromoteIntShiftOp(SDValue Op) { 851 if (!LegalOperations) 852 return SDValue(); 853 854 EVT VT = Op.getValueType(); 855 if (VT.isVector() || !VT.isInteger()) 856 return SDValue(); 857 858 // If operation type is 'undesirable', e.g. i16 on x86, consider 859 // promoting it. 860 unsigned Opc = Op.getOpcode(); 861 if (TLI.isTypeDesirableForOp(Opc, VT)) 862 return SDValue(); 863 864 EVT PVT = VT; 865 // Consult target whether it is a good idea to promote this operation and 866 // what's the right type to promote it to. 867 if (TLI.IsDesirableToPromoteOp(Op, PVT)) { 868 assert(PVT != VT && "Don't know what type to promote to!"); 869 870 bool Replace = false; 871 SDValue N0 = Op.getOperand(0); 872 if (Opc == ISD::SRA) 873 N0 = SExtPromoteOperand(Op.getOperand(0), PVT); 874 else if (Opc == ISD::SRL) 875 N0 = ZExtPromoteOperand(Op.getOperand(0), PVT); 876 else 877 N0 = PromoteOperand(N0, PVT, Replace); 878 if (N0.getNode() == 0) 879 return SDValue(); 880 881 AddToWorkList(N0.getNode()); 882 if (Replace) 883 ReplaceLoadWithPromotedLoad(Op.getOperand(0).getNode(), N0.getNode()); 884 885 DEBUG(dbgs() << "\nPromoting "; 886 Op.getNode()->dump(&DAG)); 887 DebugLoc dl = Op.getDebugLoc(); 888 return DAG.getNode(ISD::TRUNCATE, dl, VT, 889 DAG.getNode(Opc, dl, PVT, N0, Op.getOperand(1))); 890 } 891 return SDValue(); 892} 893 894SDValue DAGCombiner::PromoteExtend(SDValue Op) { 895 if (!LegalOperations) 896 return SDValue(); 897 898 EVT VT = Op.getValueType(); 899 if (VT.isVector() || !VT.isInteger()) 900 return SDValue(); 901 902 // If operation type is 'undesirable', e.g. i16 on x86, consider 903 // promoting it. 904 unsigned Opc = Op.getOpcode(); 905 if (TLI.isTypeDesirableForOp(Opc, VT)) 906 return SDValue(); 907 908 EVT PVT = VT; 909 // Consult target whether it is a good idea to promote this operation and 910 // what's the right type to promote it to. 911 if (TLI.IsDesirableToPromoteOp(Op, PVT)) { 912 assert(PVT != VT && "Don't know what type to promote to!"); 913 // fold (aext (aext x)) -> (aext x) 914 // fold (aext (zext x)) -> (zext x) 915 // fold (aext (sext x)) -> (sext x) 916 DEBUG(dbgs() << "\nPromoting "; 917 Op.getNode()->dump(&DAG)); 918 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), VT, Op.getOperand(0)); 919 } 920 return SDValue(); 921} 922 923bool DAGCombiner::PromoteLoad(SDValue Op) { 924 if (!LegalOperations) 925 return false; 926 927 EVT VT = Op.getValueType(); 928 if (VT.isVector() || !VT.isInteger()) 929 return false; 930 931 // If operation type is 'undesirable', e.g. i16 on x86, consider 932 // promoting it. 933 unsigned Opc = Op.getOpcode(); 934 if (TLI.isTypeDesirableForOp(Opc, VT)) 935 return false; 936 937 EVT PVT = VT; 938 // Consult target whether it is a good idea to promote this operation and 939 // what's the right type to promote it to. 940 if (TLI.IsDesirableToPromoteOp(Op, PVT)) { 941 assert(PVT != VT && "Don't know what type to promote to!"); 942 943 DebugLoc dl = Op.getDebugLoc(); 944 SDNode *N = Op.getNode(); 945 LoadSDNode *LD = cast<LoadSDNode>(N); 946 EVT MemVT = LD->getMemoryVT(); 947 ISD::LoadExtType ExtType = ISD::isNON_EXTLoad(LD) 948 ? (TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT) ? ISD::ZEXTLOAD 949 : ISD::EXTLOAD) 950 : LD->getExtensionType(); 951 SDValue NewLD = DAG.getExtLoad(ExtType, dl, PVT, 952 LD->getChain(), LD->getBasePtr(), 953 LD->getPointerInfo(), 954 MemVT, LD->isVolatile(), 955 LD->isNonTemporal(), LD->getAlignment()); 956 SDValue Result = DAG.getNode(ISD::TRUNCATE, dl, VT, NewLD); 957 958 DEBUG(dbgs() << "\nPromoting "; 959 N->dump(&DAG); 960 dbgs() << "\nTo: "; 961 Result.getNode()->dump(&DAG); 962 dbgs() << '\n'); 963 WorkListRemover DeadNodes(*this); 964 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result); 965 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), NewLD.getValue(1)); 966 removeFromWorkList(N); 967 DAG.DeleteNode(N); 968 AddToWorkList(Result.getNode()); 969 return true; 970 } 971 return false; 972} 973 974 975//===----------------------------------------------------------------------===// 976// Main DAG Combiner implementation 977//===----------------------------------------------------------------------===// 978 979void DAGCombiner::Run(CombineLevel AtLevel) { 980 // set the instance variables, so that the various visit routines may use it. 981 Level = AtLevel; 982 LegalOperations = Level >= AfterLegalizeVectorOps; 983 LegalTypes = Level >= AfterLegalizeTypes; 984 985 // Add all the dag nodes to the worklist. 986 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 987 E = DAG.allnodes_end(); I != E; ++I) 988 AddToWorkList(I); 989 990 // Create a dummy node (which is not added to allnodes), that adds a reference 991 // to the root node, preventing it from being deleted, and tracking any 992 // changes of the root. 993 HandleSDNode Dummy(DAG.getRoot()); 994 995 // The root of the dag may dangle to deleted nodes until the dag combiner is 996 // done. Set it to null to avoid confusion. 997 DAG.setRoot(SDValue()); 998 999 // while the worklist isn't empty, find a node and 1000 // try and combine it. 1001 while (!WorkListContents.empty()) { 1002 SDNode *N; 1003 // The WorkListOrder holds the SDNodes in order, but it may contain duplicates. 1004 // In order to avoid a linear scan, we use a set (O(log N)) to hold what the 1005 // worklist *should* contain, and check the node we want to visit is should 1006 // actually be visited. 1007 do { 1008 N = WorkListOrder.pop_back_val(); 1009 } while (!WorkListContents.erase(N)); 1010 1011 // If N has no uses, it is dead. Make sure to revisit all N's operands once 1012 // N is deleted from the DAG, since they too may now be dead or may have a 1013 // reduced number of uses, allowing other xforms. 1014 if (N->use_empty() && N != &Dummy) { 1015 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 1016 AddToWorkList(N->getOperand(i).getNode()); 1017 1018 DAG.DeleteNode(N); 1019 continue; 1020 } 1021 1022 SDValue RV = combine(N); 1023 1024 if (RV.getNode() == 0) 1025 continue; 1026 1027 ++NodesCombined; 1028 1029 // If we get back the same node we passed in, rather than a new node or 1030 // zero, we know that the node must have defined multiple values and 1031 // CombineTo was used. Since CombineTo takes care of the worklist 1032 // mechanics for us, we have no work to do in this case. 1033 if (RV.getNode() == N) 1034 continue; 1035 1036 assert(N->getOpcode() != ISD::DELETED_NODE && 1037 RV.getNode()->getOpcode() != ISD::DELETED_NODE && 1038 "Node was deleted but visit returned new node!"); 1039 1040 DEBUG(dbgs() << "\nReplacing.3 "; 1041 N->dump(&DAG); 1042 dbgs() << "\nWith: "; 1043 RV.getNode()->dump(&DAG); 1044 dbgs() << '\n'); 1045 1046 // Transfer debug value. 1047 DAG.TransferDbgValues(SDValue(N, 0), RV); 1048 WorkListRemover DeadNodes(*this); 1049 if (N->getNumValues() == RV.getNode()->getNumValues()) 1050 DAG.ReplaceAllUsesWith(N, RV.getNode()); 1051 else { 1052 assert(N->getValueType(0) == RV.getValueType() && 1053 N->getNumValues() == 1 && "Type mismatch"); 1054 SDValue OpV = RV; 1055 DAG.ReplaceAllUsesWith(N, &OpV); 1056 } 1057 1058 // Push the new node and any users onto the worklist 1059 AddToWorkList(RV.getNode()); 1060 AddUsersToWorkList(RV.getNode()); 1061 1062 // Add any uses of the old node to the worklist in case this node is the 1063 // last one that uses them. They may become dead after this node is 1064 // deleted. 1065 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 1066 AddToWorkList(N->getOperand(i).getNode()); 1067 1068 // Finally, if the node is now dead, remove it from the graph. The node 1069 // may not be dead if the replacement process recursively simplified to 1070 // something else needing this node. 1071 if (N->use_empty()) { 1072 // Nodes can be reintroduced into the worklist. Make sure we do not 1073 // process a node that has been replaced. 1074 removeFromWorkList(N); 1075 1076 // Finally, since the node is now dead, remove it from the graph. 1077 DAG.DeleteNode(N); 1078 } 1079 } 1080 1081 // If the root changed (e.g. it was a dead load, update the root). 1082 DAG.setRoot(Dummy.getValue()); 1083 DAG.RemoveDeadNodes(); 1084} 1085 1086SDValue DAGCombiner::visit(SDNode *N) { 1087 switch (N->getOpcode()) { 1088 default: break; 1089 case ISD::TokenFactor: return visitTokenFactor(N); 1090 case ISD::MERGE_VALUES: return visitMERGE_VALUES(N); 1091 case ISD::ADD: return visitADD(N); 1092 case ISD::SUB: return visitSUB(N); 1093 case ISD::ADDC: return visitADDC(N); 1094 case ISD::SUBC: return visitSUBC(N); 1095 case ISD::ADDE: return visitADDE(N); 1096 case ISD::SUBE: return visitSUBE(N); 1097 case ISD::MUL: return visitMUL(N); 1098 case ISD::SDIV: return visitSDIV(N); 1099 case ISD::UDIV: return visitUDIV(N); 1100 case ISD::SREM: return visitSREM(N); 1101 case ISD::UREM: return visitUREM(N); 1102 case ISD::MULHU: return visitMULHU(N); 1103 case ISD::MULHS: return visitMULHS(N); 1104 case ISD::SMUL_LOHI: return visitSMUL_LOHI(N); 1105 case ISD::UMUL_LOHI: return visitUMUL_LOHI(N); 1106 case ISD::SMULO: return visitSMULO(N); 1107 case ISD::UMULO: return visitUMULO(N); 1108 case ISD::SDIVREM: return visitSDIVREM(N); 1109 case ISD::UDIVREM: return visitUDIVREM(N); 1110 case ISD::AND: return visitAND(N); 1111 case ISD::OR: return visitOR(N); 1112 case ISD::XOR: return visitXOR(N); 1113 case ISD::SHL: return visitSHL(N); 1114 case ISD::SRA: return visitSRA(N); 1115 case ISD::SRL: return visitSRL(N); 1116 case ISD::CTLZ: return visitCTLZ(N); 1117 case ISD::CTLZ_ZERO_UNDEF: return visitCTLZ_ZERO_UNDEF(N); 1118 case ISD::CTTZ: return visitCTTZ(N); 1119 case ISD::CTTZ_ZERO_UNDEF: return visitCTTZ_ZERO_UNDEF(N); 1120 case ISD::CTPOP: return visitCTPOP(N); 1121 case ISD::SELECT: return visitSELECT(N); 1122 case ISD::SELECT_CC: return visitSELECT_CC(N); 1123 case ISD::SETCC: return visitSETCC(N); 1124 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N); 1125 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N); 1126 case ISD::ANY_EXTEND: return visitANY_EXTEND(N); 1127 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N); 1128 case ISD::TRUNCATE: return visitTRUNCATE(N); 1129 case ISD::BITCAST: return visitBITCAST(N); 1130 case ISD::BUILD_PAIR: return visitBUILD_PAIR(N); 1131 case ISD::FADD: return visitFADD(N); 1132 case ISD::FSUB: return visitFSUB(N); 1133 case ISD::FMUL: return visitFMUL(N); 1134 case ISD::FMA: return visitFMA(N); 1135 case ISD::FDIV: return visitFDIV(N); 1136 case ISD::FREM: return visitFREM(N); 1137 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N); 1138 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N); 1139 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N); 1140 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N); 1141 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N); 1142 case ISD::FP_ROUND: return visitFP_ROUND(N); 1143 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N); 1144 case ISD::FP_EXTEND: return visitFP_EXTEND(N); 1145 case ISD::FNEG: return visitFNEG(N); 1146 case ISD::FABS: return visitFABS(N); 1147 case ISD::FFLOOR: return visitFFLOOR(N); 1148 case ISD::FCEIL: return visitFCEIL(N); 1149 case ISD::FTRUNC: return visitFTRUNC(N); 1150 case ISD::BRCOND: return visitBRCOND(N); 1151 case ISD::BR_CC: return visitBR_CC(N); 1152 case ISD::LOAD: return visitLOAD(N); 1153 case ISD::STORE: return visitSTORE(N); 1154 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N); 1155 case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N); 1156 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N); 1157 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N); 1158 case ISD::EXTRACT_SUBVECTOR: return visitEXTRACT_SUBVECTOR(N); 1159 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N); 1160 case ISD::MEMBARRIER: return visitMEMBARRIER(N); 1161 } 1162 return SDValue(); 1163} 1164 1165SDValue DAGCombiner::combine(SDNode *N) { 1166 SDValue RV = visit(N); 1167 1168 // If nothing happened, try a target-specific DAG combine. 1169 if (RV.getNode() == 0) { 1170 assert(N->getOpcode() != ISD::DELETED_NODE && 1171 "Node was deleted but visit returned NULL!"); 1172 1173 if (N->getOpcode() >= ISD::BUILTIN_OP_END || 1174 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) { 1175 1176 // Expose the DAG combiner to the target combiner impls. 1177 TargetLowering::DAGCombinerInfo 1178 DagCombineInfo(DAG, !LegalTypes, !LegalOperations, false, this); 1179 1180 RV = TLI.PerformDAGCombine(N, DagCombineInfo); 1181 } 1182 } 1183 1184 // If nothing happened still, try promoting the operation. 1185 if (RV.getNode() == 0) { 1186 switch (N->getOpcode()) { 1187 default: break; 1188 case ISD::ADD: 1189 case ISD::SUB: 1190 case ISD::MUL: 1191 case ISD::AND: 1192 case ISD::OR: 1193 case ISD::XOR: 1194 RV = PromoteIntBinOp(SDValue(N, 0)); 1195 break; 1196 case ISD::SHL: 1197 case ISD::SRA: 1198 case ISD::SRL: 1199 RV = PromoteIntShiftOp(SDValue(N, 0)); 1200 break; 1201 case ISD::SIGN_EXTEND: 1202 case ISD::ZERO_EXTEND: 1203 case ISD::ANY_EXTEND: 1204 RV = PromoteExtend(SDValue(N, 0)); 1205 break; 1206 case ISD::LOAD: 1207 if (PromoteLoad(SDValue(N, 0))) 1208 RV = SDValue(N, 0); 1209 break; 1210 } 1211 } 1212 1213 // If N is a commutative binary node, try commuting it to enable more 1214 // sdisel CSE. 1215 if (RV.getNode() == 0 && 1216 SelectionDAG::isCommutativeBinOp(N->getOpcode()) && 1217 N->getNumValues() == 1) { 1218 SDValue N0 = N->getOperand(0); 1219 SDValue N1 = N->getOperand(1); 1220 1221 // Constant operands are canonicalized to RHS. 1222 if (isa<ConstantSDNode>(N0) || !isa<ConstantSDNode>(N1)) { 1223 SDValue Ops[] = { N1, N0 }; 1224 SDNode *CSENode = DAG.getNodeIfExists(N->getOpcode(), N->getVTList(), 1225 Ops, 2); 1226 if (CSENode) 1227 return SDValue(CSENode, 0); 1228 } 1229 } 1230 1231 return RV; 1232} 1233 1234/// getInputChainForNode - Given a node, return its input chain if it has one, 1235/// otherwise return a null sd operand. 1236static SDValue getInputChainForNode(SDNode *N) { 1237 if (unsigned NumOps = N->getNumOperands()) { 1238 if (N->getOperand(0).getValueType() == MVT::Other) 1239 return N->getOperand(0); 1240 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other) 1241 return N->getOperand(NumOps-1); 1242 for (unsigned i = 1; i < NumOps-1; ++i) 1243 if (N->getOperand(i).getValueType() == MVT::Other) 1244 return N->getOperand(i); 1245 } 1246 return SDValue(); 1247} 1248 1249SDValue DAGCombiner::visitTokenFactor(SDNode *N) { 1250 // If N has two operands, where one has an input chain equal to the other, 1251 // the 'other' chain is redundant. 1252 if (N->getNumOperands() == 2) { 1253 if (getInputChainForNode(N->getOperand(0).getNode()) == N->getOperand(1)) 1254 return N->getOperand(0); 1255 if (getInputChainForNode(N->getOperand(1).getNode()) == N->getOperand(0)) 1256 return N->getOperand(1); 1257 } 1258 1259 SmallVector<SDNode *, 8> TFs; // List of token factors to visit. 1260 SmallVector<SDValue, 8> Ops; // Ops for replacing token factor. 1261 SmallPtrSet<SDNode*, 16> SeenOps; 1262 bool Changed = false; // If we should replace this token factor. 1263 1264 // Start out with this token factor. 1265 TFs.push_back(N); 1266 1267 // Iterate through token factors. The TFs grows when new token factors are 1268 // encountered. 1269 for (unsigned i = 0; i < TFs.size(); ++i) { 1270 SDNode *TF = TFs[i]; 1271 1272 // Check each of the operands. 1273 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) { 1274 SDValue Op = TF->getOperand(i); 1275 1276 switch (Op.getOpcode()) { 1277 case ISD::EntryToken: 1278 // Entry tokens don't need to be added to the list. They are 1279 // rededundant. 1280 Changed = true; 1281 break; 1282 1283 case ISD::TokenFactor: 1284 if (Op.hasOneUse() && 1285 std::find(TFs.begin(), TFs.end(), Op.getNode()) == TFs.end()) { 1286 // Queue up for processing. 1287 TFs.push_back(Op.getNode()); 1288 // Clean up in case the token factor is removed. 1289 AddToWorkList(Op.getNode()); 1290 Changed = true; 1291 break; 1292 } 1293 // Fall thru 1294 1295 default: 1296 // Only add if it isn't already in the list. 1297 if (SeenOps.insert(Op.getNode())) 1298 Ops.push_back(Op); 1299 else 1300 Changed = true; 1301 break; 1302 } 1303 } 1304 } 1305 1306 SDValue Result; 1307 1308 // If we've change things around then replace token factor. 1309 if (Changed) { 1310 if (Ops.empty()) { 1311 // The entry token is the only possible outcome. 1312 Result = DAG.getEntryNode(); 1313 } else { 1314 // New and improved token factor. 1315 Result = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 1316 MVT::Other, &Ops[0], Ops.size()); 1317 } 1318 1319 // Don't add users to work list. 1320 return CombineTo(N, Result, false); 1321 } 1322 1323 return Result; 1324} 1325 1326/// MERGE_VALUES can always be eliminated. 1327SDValue DAGCombiner::visitMERGE_VALUES(SDNode *N) { 1328 WorkListRemover DeadNodes(*this); 1329 // Replacing results may cause a different MERGE_VALUES to suddenly 1330 // be CSE'd with N, and carry its uses with it. Iterate until no 1331 // uses remain, to ensure that the node can be safely deleted. 1332 // First add the users of this node to the work list so that they 1333 // can be tried again once they have new operands. 1334 AddUsersToWorkList(N); 1335 do { 1336 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 1337 DAG.ReplaceAllUsesOfValueWith(SDValue(N, i), N->getOperand(i)); 1338 } while (!N->use_empty()); 1339 removeFromWorkList(N); 1340 DAG.DeleteNode(N); 1341 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1342} 1343 1344static 1345SDValue combineShlAddConstant(DebugLoc DL, SDValue N0, SDValue N1, 1346 SelectionDAG &DAG) { 1347 EVT VT = N0.getValueType(); 1348 SDValue N00 = N0.getOperand(0); 1349 SDValue N01 = N0.getOperand(1); 1350 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01); 1351 1352 if (N01C && N00.getOpcode() == ISD::ADD && N00.getNode()->hasOneUse() && 1353 isa<ConstantSDNode>(N00.getOperand(1))) { 1354 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 1355 N0 = DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, 1356 DAG.getNode(ISD::SHL, N00.getDebugLoc(), VT, 1357 N00.getOperand(0), N01), 1358 DAG.getNode(ISD::SHL, N01.getDebugLoc(), VT, 1359 N00.getOperand(1), N01)); 1360 return DAG.getNode(ISD::ADD, DL, VT, N0, N1); 1361 } 1362 1363 return SDValue(); 1364} 1365 1366SDValue DAGCombiner::visitADD(SDNode *N) { 1367 SDValue N0 = N->getOperand(0); 1368 SDValue N1 = N->getOperand(1); 1369 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1370 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1371 EVT VT = N0.getValueType(); 1372 1373 // fold vector ops 1374 if (VT.isVector()) { 1375 SDValue FoldedVOp = SimplifyVBinOp(N); 1376 if (FoldedVOp.getNode()) return FoldedVOp; 1377 } 1378 1379 // fold (add x, undef) -> undef 1380 if (N0.getOpcode() == ISD::UNDEF) 1381 return N0; 1382 if (N1.getOpcode() == ISD::UNDEF) 1383 return N1; 1384 // fold (add c1, c2) -> c1+c2 1385 if (N0C && N1C) 1386 return DAG.FoldConstantArithmetic(ISD::ADD, VT, N0C, N1C); 1387 // canonicalize constant to RHS 1388 if (N0C && !N1C) 1389 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0); 1390 // fold (add x, 0) -> x 1391 if (N1C && N1C->isNullValue()) 1392 return N0; 1393 // fold (add Sym, c) -> Sym+c 1394 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0)) 1395 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA) && N1C && 1396 GA->getOpcode() == ISD::GlobalAddress) 1397 return DAG.getGlobalAddress(GA->getGlobal(), N1C->getDebugLoc(), VT, 1398 GA->getOffset() + 1399 (uint64_t)N1C->getSExtValue()); 1400 // fold ((c1-A)+c2) -> (c1+c2)-A 1401 if (N1C && N0.getOpcode() == ISD::SUB) 1402 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0))) 1403 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1404 DAG.getConstant(N1C->getAPIntValue()+ 1405 N0C->getAPIntValue(), VT), 1406 N0.getOperand(1)); 1407 // reassociate add 1408 SDValue RADD = ReassociateOps(ISD::ADD, N->getDebugLoc(), N0, N1); 1409 if (RADD.getNode() != 0) 1410 return RADD; 1411 // fold ((0-A) + B) -> B-A 1412 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) && 1413 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue()) 1414 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1, N0.getOperand(1)); 1415 // fold (A + (0-B)) -> A-B 1416 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) && 1417 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue()) 1418 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, N1.getOperand(1)); 1419 // fold (A+(B-A)) -> B 1420 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1)) 1421 return N1.getOperand(0); 1422 // fold ((B-A)+A) -> B 1423 if (N0.getOpcode() == ISD::SUB && N1 == N0.getOperand(1)) 1424 return N0.getOperand(0); 1425 // fold (A+(B-(A+C))) to (B-C) 1426 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD && 1427 N0 == N1.getOperand(1).getOperand(0)) 1428 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0), 1429 N1.getOperand(1).getOperand(1)); 1430 // fold (A+(B-(C+A))) to (B-C) 1431 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD && 1432 N0 == N1.getOperand(1).getOperand(1)) 1433 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0), 1434 N1.getOperand(1).getOperand(0)); 1435 // fold (A+((B-A)+or-C)) to (B+or-C) 1436 if ((N1.getOpcode() == ISD::SUB || N1.getOpcode() == ISD::ADD) && 1437 N1.getOperand(0).getOpcode() == ISD::SUB && 1438 N0 == N1.getOperand(0).getOperand(1)) 1439 return DAG.getNode(N1.getOpcode(), N->getDebugLoc(), VT, 1440 N1.getOperand(0).getOperand(0), N1.getOperand(1)); 1441 1442 // fold (A-B)+(C-D) to (A+C)-(B+D) when A or C is constant 1443 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB) { 1444 SDValue N00 = N0.getOperand(0); 1445 SDValue N01 = N0.getOperand(1); 1446 SDValue N10 = N1.getOperand(0); 1447 SDValue N11 = N1.getOperand(1); 1448 1449 if (isa<ConstantSDNode>(N00) || isa<ConstantSDNode>(N10)) 1450 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1451 DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, N00, N10), 1452 DAG.getNode(ISD::ADD, N1.getDebugLoc(), VT, N01, N11)); 1453 } 1454 1455 if (!VT.isVector() && SimplifyDemandedBits(SDValue(N, 0))) 1456 return SDValue(N, 0); 1457 1458 // fold (a+b) -> (a|b) iff a and b share no bits. 1459 if (VT.isInteger() && !VT.isVector()) { 1460 APInt LHSZero, LHSOne; 1461 APInt RHSZero, RHSOne; 1462 DAG.ComputeMaskedBits(N0, LHSZero, LHSOne); 1463 1464 if (LHSZero.getBoolValue()) { 1465 DAG.ComputeMaskedBits(N1, RHSZero, RHSOne); 1466 1467 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1468 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1469 if ((RHSZero & ~LHSZero) == ~LHSZero || (LHSZero & ~RHSZero) == ~RHSZero) 1470 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1); 1471 } 1472 } 1473 1474 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 1475 if (N0.getOpcode() == ISD::SHL && N0.getNode()->hasOneUse()) { 1476 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N0, N1, DAG); 1477 if (Result.getNode()) return Result; 1478 } 1479 if (N1.getOpcode() == ISD::SHL && N1.getNode()->hasOneUse()) { 1480 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N1, N0, DAG); 1481 if (Result.getNode()) return Result; 1482 } 1483 1484 // fold (add x, shl(0 - y, n)) -> sub(x, shl(y, n)) 1485 if (N1.getOpcode() == ISD::SHL && 1486 N1.getOperand(0).getOpcode() == ISD::SUB) 1487 if (ConstantSDNode *C = 1488 dyn_cast<ConstantSDNode>(N1.getOperand(0).getOperand(0))) 1489 if (C->getAPIntValue() == 0) 1490 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, 1491 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1492 N1.getOperand(0).getOperand(1), 1493 N1.getOperand(1))); 1494 if (N0.getOpcode() == ISD::SHL && 1495 N0.getOperand(0).getOpcode() == ISD::SUB) 1496 if (ConstantSDNode *C = 1497 dyn_cast<ConstantSDNode>(N0.getOperand(0).getOperand(0))) 1498 if (C->getAPIntValue() == 0) 1499 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1, 1500 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1501 N0.getOperand(0).getOperand(1), 1502 N0.getOperand(1))); 1503 1504 if (N1.getOpcode() == ISD::AND) { 1505 SDValue AndOp0 = N1.getOperand(0); 1506 ConstantSDNode *AndOp1 = dyn_cast<ConstantSDNode>(N1->getOperand(1)); 1507 unsigned NumSignBits = DAG.ComputeNumSignBits(AndOp0); 1508 unsigned DestBits = VT.getScalarType().getSizeInBits(); 1509 1510 // (add z, (and (sbbl x, x), 1)) -> (sub z, (sbbl x, x)) 1511 // and similar xforms where the inner op is either ~0 or 0. 1512 if (NumSignBits == DestBits && AndOp1 && AndOp1->isOne()) { 1513 DebugLoc DL = N->getDebugLoc(); 1514 return DAG.getNode(ISD::SUB, DL, VT, N->getOperand(0), AndOp0); 1515 } 1516 } 1517 1518 // add (sext i1), X -> sub X, (zext i1) 1519 if (N0.getOpcode() == ISD::SIGN_EXTEND && 1520 N0.getOperand(0).getValueType() == MVT::i1 && 1521 !TLI.isOperationLegal(ISD::SIGN_EXTEND, MVT::i1)) { 1522 DebugLoc DL = N->getDebugLoc(); 1523 SDValue ZExt = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0)); 1524 return DAG.getNode(ISD::SUB, DL, VT, N1, ZExt); 1525 } 1526 1527 return SDValue(); 1528} 1529 1530SDValue DAGCombiner::visitADDC(SDNode *N) { 1531 SDValue N0 = N->getOperand(0); 1532 SDValue N1 = N->getOperand(1); 1533 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1534 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1535 EVT VT = N0.getValueType(); 1536 1537 // If the flag result is dead, turn this into an ADD. 1538 if (!N->hasAnyUseOfValue(1)) 1539 return CombineTo(N, DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, N1), 1540 DAG.getNode(ISD::CARRY_FALSE, 1541 N->getDebugLoc(), MVT::Glue)); 1542 1543 // canonicalize constant to RHS. 1544 if (N0C && !N1C) 1545 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0); 1546 1547 // fold (addc x, 0) -> x + no carry out 1548 if (N1C && N1C->isNullValue()) 1549 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, 1550 N->getDebugLoc(), MVT::Glue)); 1551 1552 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits. 1553 APInt LHSZero, LHSOne; 1554 APInt RHSZero, RHSOne; 1555 DAG.ComputeMaskedBits(N0, LHSZero, LHSOne); 1556 1557 if (LHSZero.getBoolValue()) { 1558 DAG.ComputeMaskedBits(N1, RHSZero, RHSOne); 1559 1560 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1561 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1562 if ((RHSZero & ~LHSZero) == ~LHSZero || (LHSZero & ~RHSZero) == ~RHSZero) 1563 return CombineTo(N, DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1), 1564 DAG.getNode(ISD::CARRY_FALSE, 1565 N->getDebugLoc(), MVT::Glue)); 1566 } 1567 1568 return SDValue(); 1569} 1570 1571SDValue DAGCombiner::visitADDE(SDNode *N) { 1572 SDValue N0 = N->getOperand(0); 1573 SDValue N1 = N->getOperand(1); 1574 SDValue CarryIn = N->getOperand(2); 1575 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1576 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1577 1578 // canonicalize constant to RHS 1579 if (N0C && !N1C) 1580 return DAG.getNode(ISD::ADDE, N->getDebugLoc(), N->getVTList(), 1581 N1, N0, CarryIn); 1582 1583 // fold (adde x, y, false) -> (addc x, y) 1584 if (CarryIn.getOpcode() == ISD::CARRY_FALSE) 1585 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N0, N1); 1586 1587 return SDValue(); 1588} 1589 1590// Since it may not be valid to emit a fold to zero for vector initializers 1591// check if we can before folding. 1592static SDValue tryFoldToZero(DebugLoc DL, const TargetLowering &TLI, EVT VT, 1593 SelectionDAG &DAG, bool LegalOperations) { 1594 if (!VT.isVector()) { 1595 return DAG.getConstant(0, VT); 1596 } 1597 if (!LegalOperations || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) { 1598 // Produce a vector of zeros. 1599 SDValue El = DAG.getConstant(0, VT.getVectorElementType()); 1600 std::vector<SDValue> Ops(VT.getVectorNumElements(), El); 1601 return DAG.getNode(ISD::BUILD_VECTOR, DL, VT, 1602 &Ops[0], Ops.size()); 1603 } 1604 return SDValue(); 1605} 1606 1607SDValue DAGCombiner::visitSUB(SDNode *N) { 1608 SDValue N0 = N->getOperand(0); 1609 SDValue N1 = N->getOperand(1); 1610 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1611 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1612 ConstantSDNode *N1C1 = N1.getOpcode() != ISD::ADD ? 0 : 1613 dyn_cast<ConstantSDNode>(N1.getOperand(1).getNode()); 1614 EVT VT = N0.getValueType(); 1615 1616 // fold vector ops 1617 if (VT.isVector()) { 1618 SDValue FoldedVOp = SimplifyVBinOp(N); 1619 if (FoldedVOp.getNode()) return FoldedVOp; 1620 } 1621 1622 // fold (sub x, x) -> 0 1623 // FIXME: Refactor this and xor and other similar operations together. 1624 if (N0 == N1) 1625 return tryFoldToZero(N->getDebugLoc(), TLI, VT, DAG, LegalOperations); 1626 // fold (sub c1, c2) -> c1-c2 1627 if (N0C && N1C) 1628 return DAG.FoldConstantArithmetic(ISD::SUB, VT, N0C, N1C); 1629 // fold (sub x, c) -> (add x, -c) 1630 if (N1C) 1631 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, 1632 DAG.getConstant(-N1C->getAPIntValue(), VT)); 1633 // Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1) 1634 if (N0C && N0C->isAllOnesValue()) 1635 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0); 1636 // fold A-(A-B) -> B 1637 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(0)) 1638 return N1.getOperand(1); 1639 // fold (A+B)-A -> B 1640 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1) 1641 return N0.getOperand(1); 1642 // fold (A+B)-B -> A 1643 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1) 1644 return N0.getOperand(0); 1645 // fold C2-(A+C1) -> (C2-C1)-A 1646 if (N1.getOpcode() == ISD::ADD && N0C && N1C1) { 1647 SDValue NewC = DAG.getConstant((N0C->getAPIntValue() - N1C1->getAPIntValue()), VT); 1648 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, NewC, 1649 N1.getOperand(0)); 1650 } 1651 // fold ((A+(B+or-C))-B) -> A+or-C 1652 if (N0.getOpcode() == ISD::ADD && 1653 (N0.getOperand(1).getOpcode() == ISD::SUB || 1654 N0.getOperand(1).getOpcode() == ISD::ADD) && 1655 N0.getOperand(1).getOperand(0) == N1) 1656 return DAG.getNode(N0.getOperand(1).getOpcode(), N->getDebugLoc(), VT, 1657 N0.getOperand(0), N0.getOperand(1).getOperand(1)); 1658 // fold ((A+(C+B))-B) -> A+C 1659 if (N0.getOpcode() == ISD::ADD && 1660 N0.getOperand(1).getOpcode() == ISD::ADD && 1661 N0.getOperand(1).getOperand(1) == N1) 1662 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, 1663 N0.getOperand(0), N0.getOperand(1).getOperand(0)); 1664 // fold ((A-(B-C))-C) -> A-B 1665 if (N0.getOpcode() == ISD::SUB && 1666 N0.getOperand(1).getOpcode() == ISD::SUB && 1667 N0.getOperand(1).getOperand(1) == N1) 1668 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1669 N0.getOperand(0), N0.getOperand(1).getOperand(0)); 1670 1671 // If either operand of a sub is undef, the result is undef 1672 if (N0.getOpcode() == ISD::UNDEF) 1673 return N0; 1674 if (N1.getOpcode() == ISD::UNDEF) 1675 return N1; 1676 1677 // If the relocation model supports it, consider symbol offsets. 1678 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0)) 1679 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA)) { 1680 // fold (sub Sym, c) -> Sym-c 1681 if (N1C && GA->getOpcode() == ISD::GlobalAddress) 1682 return DAG.getGlobalAddress(GA->getGlobal(), N1C->getDebugLoc(), VT, 1683 GA->getOffset() - 1684 (uint64_t)N1C->getSExtValue()); 1685 // fold (sub Sym+c1, Sym+c2) -> c1-c2 1686 if (GlobalAddressSDNode *GB = dyn_cast<GlobalAddressSDNode>(N1)) 1687 if (GA->getGlobal() == GB->getGlobal()) 1688 return DAG.getConstant((uint64_t)GA->getOffset() - GB->getOffset(), 1689 VT); 1690 } 1691 1692 return SDValue(); 1693} 1694 1695SDValue DAGCombiner::visitSUBC(SDNode *N) { 1696 SDValue N0 = N->getOperand(0); 1697 SDValue N1 = N->getOperand(1); 1698 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1699 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1700 EVT VT = N0.getValueType(); 1701 1702 // If the flag result is dead, turn this into an SUB. 1703 if (!N->hasAnyUseOfValue(1)) 1704 return CombineTo(N, DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, N1), 1705 DAG.getNode(ISD::CARRY_FALSE, N->getDebugLoc(), 1706 MVT::Glue)); 1707 1708 // fold (subc x, x) -> 0 + no borrow 1709 if (N0 == N1) 1710 return CombineTo(N, DAG.getConstant(0, VT), 1711 DAG.getNode(ISD::CARRY_FALSE, N->getDebugLoc(), 1712 MVT::Glue)); 1713 1714 // fold (subc x, 0) -> x + no borrow 1715 if (N1C && N1C->isNullValue()) 1716 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, N->getDebugLoc(), 1717 MVT::Glue)); 1718 1719 // Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1) + no borrow 1720 if (N0C && N0C->isAllOnesValue()) 1721 return CombineTo(N, DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0), 1722 DAG.getNode(ISD::CARRY_FALSE, N->getDebugLoc(), 1723 MVT::Glue)); 1724 1725 return SDValue(); 1726} 1727 1728SDValue DAGCombiner::visitSUBE(SDNode *N) { 1729 SDValue N0 = N->getOperand(0); 1730 SDValue N1 = N->getOperand(1); 1731 SDValue CarryIn = N->getOperand(2); 1732 1733 // fold (sube x, y, false) -> (subc x, y) 1734 if (CarryIn.getOpcode() == ISD::CARRY_FALSE) 1735 return DAG.getNode(ISD::SUBC, N->getDebugLoc(), N->getVTList(), N0, N1); 1736 1737 return SDValue(); 1738} 1739 1740SDValue DAGCombiner::visitMUL(SDNode *N) { 1741 SDValue N0 = N->getOperand(0); 1742 SDValue N1 = N->getOperand(1); 1743 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1744 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1745 EVT VT = N0.getValueType(); 1746 1747 // fold vector ops 1748 if (VT.isVector()) { 1749 SDValue FoldedVOp = SimplifyVBinOp(N); 1750 if (FoldedVOp.getNode()) return FoldedVOp; 1751 } 1752 1753 // fold (mul x, undef) -> 0 1754 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1755 return DAG.getConstant(0, VT); 1756 // fold (mul c1, c2) -> c1*c2 1757 if (N0C && N1C) 1758 return DAG.FoldConstantArithmetic(ISD::MUL, VT, N0C, N1C); 1759 // canonicalize constant to RHS 1760 if (N0C && !N1C) 1761 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, N1, N0); 1762 // fold (mul x, 0) -> 0 1763 if (N1C && N1C->isNullValue()) 1764 return N1; 1765 // fold (mul x, -1) -> 0-x 1766 if (N1C && N1C->isAllOnesValue()) 1767 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1768 DAG.getConstant(0, VT), N0); 1769 // fold (mul x, (1 << c)) -> x << c 1770 if (N1C && N1C->getAPIntValue().isPowerOf2()) 1771 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 1772 DAG.getConstant(N1C->getAPIntValue().logBase2(), 1773 getShiftAmountTy(N0.getValueType()))); 1774 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c 1775 if (N1C && (-N1C->getAPIntValue()).isPowerOf2()) { 1776 unsigned Log2Val = (-N1C->getAPIntValue()).logBase2(); 1777 // FIXME: If the input is something that is easily negated (e.g. a 1778 // single-use add), we should put the negate there. 1779 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1780 DAG.getConstant(0, VT), 1781 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 1782 DAG.getConstant(Log2Val, 1783 getShiftAmountTy(N0.getValueType())))); 1784 } 1785 // (mul (shl X, c1), c2) -> (mul X, c2 << c1) 1786 if (N1C && N0.getOpcode() == ISD::SHL && 1787 isa<ConstantSDNode>(N0.getOperand(1))) { 1788 SDValue C3 = DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1789 N1, N0.getOperand(1)); 1790 AddToWorkList(C3.getNode()); 1791 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1792 N0.getOperand(0), C3); 1793 } 1794 1795 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one 1796 // use. 1797 { 1798 SDValue Sh(0,0), Y(0,0); 1799 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)). 1800 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) && 1801 N0.getNode()->hasOneUse()) { 1802 Sh = N0; Y = N1; 1803 } else if (N1.getOpcode() == ISD::SHL && 1804 isa<ConstantSDNode>(N1.getOperand(1)) && 1805 N1.getNode()->hasOneUse()) { 1806 Sh = N1; Y = N0; 1807 } 1808 1809 if (Sh.getNode()) { 1810 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1811 Sh.getOperand(0), Y); 1812 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1813 Mul, Sh.getOperand(1)); 1814 } 1815 } 1816 1817 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2) 1818 if (N1C && N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse() && 1819 isa<ConstantSDNode>(N0.getOperand(1))) 1820 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, 1821 DAG.getNode(ISD::MUL, N0.getDebugLoc(), VT, 1822 N0.getOperand(0), N1), 1823 DAG.getNode(ISD::MUL, N1.getDebugLoc(), VT, 1824 N0.getOperand(1), N1)); 1825 1826 // reassociate mul 1827 SDValue RMUL = ReassociateOps(ISD::MUL, N->getDebugLoc(), N0, N1); 1828 if (RMUL.getNode() != 0) 1829 return RMUL; 1830 1831 return SDValue(); 1832} 1833 1834SDValue DAGCombiner::visitSDIV(SDNode *N) { 1835 SDValue N0 = N->getOperand(0); 1836 SDValue N1 = N->getOperand(1); 1837 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1838 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1839 EVT VT = N->getValueType(0); 1840 1841 // fold vector ops 1842 if (VT.isVector()) { 1843 SDValue FoldedVOp = SimplifyVBinOp(N); 1844 if (FoldedVOp.getNode()) return FoldedVOp; 1845 } 1846 1847 // fold (sdiv c1, c2) -> c1/c2 1848 if (N0C && N1C && !N1C->isNullValue()) 1849 return DAG.FoldConstantArithmetic(ISD::SDIV, VT, N0C, N1C); 1850 // fold (sdiv X, 1) -> X 1851 if (N1C && N1C->getAPIntValue() == 1LL) 1852 return N0; 1853 // fold (sdiv X, -1) -> 0-X 1854 if (N1C && N1C->isAllOnesValue()) 1855 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1856 DAG.getConstant(0, VT), N0); 1857 // If we know the sign bits of both operands are zero, strength reduce to a 1858 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2 1859 if (!VT.isVector()) { 1860 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 1861 return DAG.getNode(ISD::UDIV, N->getDebugLoc(), N1.getValueType(), 1862 N0, N1); 1863 } 1864 // fold (sdiv X, pow2) -> simple ops after legalize 1865 if (N1C && !N1C->isNullValue() && 1866 (N1C->getAPIntValue().isPowerOf2() || 1867 (-N1C->getAPIntValue()).isPowerOf2())) { 1868 // If dividing by powers of two is cheap, then don't perform the following 1869 // fold. 1870 if (TLI.isPow2DivCheap()) 1871 return SDValue(); 1872 1873 unsigned lg2 = N1C->getAPIntValue().countTrailingZeros(); 1874 1875 // Splat the sign bit into the register 1876 SDValue SGN = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0, 1877 DAG.getConstant(VT.getSizeInBits()-1, 1878 getShiftAmountTy(N0.getValueType()))); 1879 AddToWorkList(SGN.getNode()); 1880 1881 // Add (N0 < 0) ? abs2 - 1 : 0; 1882 SDValue SRL = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, SGN, 1883 DAG.getConstant(VT.getSizeInBits() - lg2, 1884 getShiftAmountTy(SGN.getValueType()))); 1885 SDValue ADD = DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, SRL); 1886 AddToWorkList(SRL.getNode()); 1887 AddToWorkList(ADD.getNode()); // Divide by pow2 1888 SDValue SRA = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, ADD, 1889 DAG.getConstant(lg2, getShiftAmountTy(ADD.getValueType()))); 1890 1891 // If we're dividing by a positive value, we're done. Otherwise, we must 1892 // negate the result. 1893 if (N1C->getAPIntValue().isNonNegative()) 1894 return SRA; 1895 1896 AddToWorkList(SRA.getNode()); 1897 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1898 DAG.getConstant(0, VT), SRA); 1899 } 1900 1901 // if integer divide is expensive and we satisfy the requirements, emit an 1902 // alternate sequence. 1903 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) { 1904 SDValue Op = BuildSDIV(N); 1905 if (Op.getNode()) return Op; 1906 } 1907 1908 // undef / X -> 0 1909 if (N0.getOpcode() == ISD::UNDEF) 1910 return DAG.getConstant(0, VT); 1911 // X / undef -> undef 1912 if (N1.getOpcode() == ISD::UNDEF) 1913 return N1; 1914 1915 return SDValue(); 1916} 1917 1918SDValue DAGCombiner::visitUDIV(SDNode *N) { 1919 SDValue N0 = N->getOperand(0); 1920 SDValue N1 = N->getOperand(1); 1921 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1922 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1923 EVT VT = N->getValueType(0); 1924 1925 // fold vector ops 1926 if (VT.isVector()) { 1927 SDValue FoldedVOp = SimplifyVBinOp(N); 1928 if (FoldedVOp.getNode()) return FoldedVOp; 1929 } 1930 1931 // fold (udiv c1, c2) -> c1/c2 1932 if (N0C && N1C && !N1C->isNullValue()) 1933 return DAG.FoldConstantArithmetic(ISD::UDIV, VT, N0C, N1C); 1934 // fold (udiv x, (1 << c)) -> x >>u c 1935 if (N1C && N1C->getAPIntValue().isPowerOf2()) 1936 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, 1937 DAG.getConstant(N1C->getAPIntValue().logBase2(), 1938 getShiftAmountTy(N0.getValueType()))); 1939 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2 1940 if (N1.getOpcode() == ISD::SHL) { 1941 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1942 if (SHC->getAPIntValue().isPowerOf2()) { 1943 EVT ADDVT = N1.getOperand(1).getValueType(); 1944 SDValue Add = DAG.getNode(ISD::ADD, N->getDebugLoc(), ADDVT, 1945 N1.getOperand(1), 1946 DAG.getConstant(SHC->getAPIntValue() 1947 .logBase2(), 1948 ADDVT)); 1949 AddToWorkList(Add.getNode()); 1950 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, Add); 1951 } 1952 } 1953 } 1954 // fold (udiv x, c) -> alternate 1955 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) { 1956 SDValue Op = BuildUDIV(N); 1957 if (Op.getNode()) return Op; 1958 } 1959 1960 // undef / X -> 0 1961 if (N0.getOpcode() == ISD::UNDEF) 1962 return DAG.getConstant(0, VT); 1963 // X / undef -> undef 1964 if (N1.getOpcode() == ISD::UNDEF) 1965 return N1; 1966 1967 return SDValue(); 1968} 1969 1970SDValue DAGCombiner::visitSREM(SDNode *N) { 1971 SDValue N0 = N->getOperand(0); 1972 SDValue N1 = N->getOperand(1); 1973 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1974 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1975 EVT VT = N->getValueType(0); 1976 1977 // fold (srem c1, c2) -> c1%c2 1978 if (N0C && N1C && !N1C->isNullValue()) 1979 return DAG.FoldConstantArithmetic(ISD::SREM, VT, N0C, N1C); 1980 // If we know the sign bits of both operands are zero, strength reduce to a 1981 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15 1982 if (!VT.isVector()) { 1983 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 1984 return DAG.getNode(ISD::UREM, N->getDebugLoc(), VT, N0, N1); 1985 } 1986 1987 // If X/C can be simplified by the division-by-constant logic, lower 1988 // X%C to the equivalent of X-X/C*C. 1989 if (N1C && !N1C->isNullValue()) { 1990 SDValue Div = DAG.getNode(ISD::SDIV, N->getDebugLoc(), VT, N0, N1); 1991 AddToWorkList(Div.getNode()); 1992 SDValue OptimizedDiv = combine(Div.getNode()); 1993 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) { 1994 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1995 OptimizedDiv, N1); 1996 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul); 1997 AddToWorkList(Mul.getNode()); 1998 return Sub; 1999 } 2000 } 2001 2002 // undef % X -> 0 2003 if (N0.getOpcode() == ISD::UNDEF) 2004 return DAG.getConstant(0, VT); 2005 // X % undef -> undef 2006 if (N1.getOpcode() == ISD::UNDEF) 2007 return N1; 2008 2009 return SDValue(); 2010} 2011 2012SDValue DAGCombiner::visitUREM(SDNode *N) { 2013 SDValue N0 = N->getOperand(0); 2014 SDValue N1 = N->getOperand(1); 2015 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2016 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2017 EVT VT = N->getValueType(0); 2018 2019 // fold (urem c1, c2) -> c1%c2 2020 if (N0C && N1C && !N1C->isNullValue()) 2021 return DAG.FoldConstantArithmetic(ISD::UREM, VT, N0C, N1C); 2022 // fold (urem x, pow2) -> (and x, pow2-1) 2023 if (N1C && !N1C->isNullValue() && N1C->getAPIntValue().isPowerOf2()) 2024 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, 2025 DAG.getConstant(N1C->getAPIntValue()-1,VT)); 2026 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1)) 2027 if (N1.getOpcode() == ISD::SHL) { 2028 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 2029 if (SHC->getAPIntValue().isPowerOf2()) { 2030 SDValue Add = 2031 DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, 2032 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), 2033 VT)); 2034 AddToWorkList(Add.getNode()); 2035 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, Add); 2036 } 2037 } 2038 } 2039 2040 // If X/C can be simplified by the division-by-constant logic, lower 2041 // X%C to the equivalent of X-X/C*C. 2042 if (N1C && !N1C->isNullValue()) { 2043 SDValue Div = DAG.getNode(ISD::UDIV, N->getDebugLoc(), VT, N0, N1); 2044 AddToWorkList(Div.getNode()); 2045 SDValue OptimizedDiv = combine(Div.getNode()); 2046 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) { 2047 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 2048 OptimizedDiv, N1); 2049 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul); 2050 AddToWorkList(Mul.getNode()); 2051 return Sub; 2052 } 2053 } 2054 2055 // undef % X -> 0 2056 if (N0.getOpcode() == ISD::UNDEF) 2057 return DAG.getConstant(0, VT); 2058 // X % undef -> undef 2059 if (N1.getOpcode() == ISD::UNDEF) 2060 return N1; 2061 2062 return SDValue(); 2063} 2064 2065SDValue DAGCombiner::visitMULHS(SDNode *N) { 2066 SDValue N0 = N->getOperand(0); 2067 SDValue N1 = N->getOperand(1); 2068 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2069 EVT VT = N->getValueType(0); 2070 DebugLoc DL = N->getDebugLoc(); 2071 2072 // fold (mulhs x, 0) -> 0 2073 if (N1C && N1C->isNullValue()) 2074 return N1; 2075 // fold (mulhs x, 1) -> (sra x, size(x)-1) 2076 if (N1C && N1C->getAPIntValue() == 1) 2077 return DAG.getNode(ISD::SRA, N->getDebugLoc(), N0.getValueType(), N0, 2078 DAG.getConstant(N0.getValueType().getSizeInBits() - 1, 2079 getShiftAmountTy(N0.getValueType()))); 2080 // fold (mulhs x, undef) -> 0 2081 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 2082 return DAG.getConstant(0, VT); 2083 2084 // If the type twice as wide is legal, transform the mulhs to a wider multiply 2085 // plus a shift. 2086 if (VT.isSimple() && !VT.isVector()) { 2087 MVT Simple = VT.getSimpleVT(); 2088 unsigned SimpleSize = Simple.getSizeInBits(); 2089 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2); 2090 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { 2091 N0 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N0); 2092 N1 = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N1); 2093 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1); 2094 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1, 2095 DAG.getConstant(SimpleSize, getShiftAmountTy(N1.getValueType()))); 2096 return DAG.getNode(ISD::TRUNCATE, DL, VT, N1); 2097 } 2098 } 2099 2100 return SDValue(); 2101} 2102 2103SDValue DAGCombiner::visitMULHU(SDNode *N) { 2104 SDValue N0 = N->getOperand(0); 2105 SDValue N1 = N->getOperand(1); 2106 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2107 EVT VT = N->getValueType(0); 2108 DebugLoc DL = N->getDebugLoc(); 2109 2110 // fold (mulhu x, 0) -> 0 2111 if (N1C && N1C->isNullValue()) 2112 return N1; 2113 // fold (mulhu x, 1) -> 0 2114 if (N1C && N1C->getAPIntValue() == 1) 2115 return DAG.getConstant(0, N0.getValueType()); 2116 // fold (mulhu x, undef) -> 0 2117 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 2118 return DAG.getConstant(0, VT); 2119 2120 // If the type twice as wide is legal, transform the mulhu to a wider multiply 2121 // plus a shift. 2122 if (VT.isSimple() && !VT.isVector()) { 2123 MVT Simple = VT.getSimpleVT(); 2124 unsigned SimpleSize = Simple.getSizeInBits(); 2125 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2); 2126 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { 2127 N0 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N0); 2128 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N1); 2129 N1 = DAG.getNode(ISD::MUL, DL, NewVT, N0, N1); 2130 N1 = DAG.getNode(ISD::SRL, DL, NewVT, N1, 2131 DAG.getConstant(SimpleSize, getShiftAmountTy(N1.getValueType()))); 2132 return DAG.getNode(ISD::TRUNCATE, DL, VT, N1); 2133 } 2134 } 2135 2136 return SDValue(); 2137} 2138 2139/// SimplifyNodeWithTwoResults - Perform optimizations common to nodes that 2140/// compute two values. LoOp and HiOp give the opcodes for the two computations 2141/// that are being performed. Return true if a simplification was made. 2142/// 2143SDValue DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 2144 unsigned HiOp) { 2145 // If the high half is not needed, just compute the low half. 2146 bool HiExists = N->hasAnyUseOfValue(1); 2147 if (!HiExists && 2148 (!LegalOperations || 2149 TLI.isOperationLegal(LoOp, N->getValueType(0)))) { 2150 SDValue Res = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0), 2151 N->op_begin(), N->getNumOperands()); 2152 return CombineTo(N, Res, Res); 2153 } 2154 2155 // If the low half is not needed, just compute the high half. 2156 bool LoExists = N->hasAnyUseOfValue(0); 2157 if (!LoExists && 2158 (!LegalOperations || 2159 TLI.isOperationLegal(HiOp, N->getValueType(1)))) { 2160 SDValue Res = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1), 2161 N->op_begin(), N->getNumOperands()); 2162 return CombineTo(N, Res, Res); 2163 } 2164 2165 // If both halves are used, return as it is. 2166 if (LoExists && HiExists) 2167 return SDValue(); 2168 2169 // If the two computed results can be simplified separately, separate them. 2170 if (LoExists) { 2171 SDValue Lo = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0), 2172 N->op_begin(), N->getNumOperands()); 2173 AddToWorkList(Lo.getNode()); 2174 SDValue LoOpt = combine(Lo.getNode()); 2175 if (LoOpt.getNode() && LoOpt.getNode() != Lo.getNode() && 2176 (!LegalOperations || 2177 TLI.isOperationLegal(LoOpt.getOpcode(), LoOpt.getValueType()))) 2178 return CombineTo(N, LoOpt, LoOpt); 2179 } 2180 2181 if (HiExists) { 2182 SDValue Hi = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1), 2183 N->op_begin(), N->getNumOperands()); 2184 AddToWorkList(Hi.getNode()); 2185 SDValue HiOpt = combine(Hi.getNode()); 2186 if (HiOpt.getNode() && HiOpt != Hi && 2187 (!LegalOperations || 2188 TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType()))) 2189 return CombineTo(N, HiOpt, HiOpt); 2190 } 2191 2192 return SDValue(); 2193} 2194 2195SDValue DAGCombiner::visitSMUL_LOHI(SDNode *N) { 2196 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS); 2197 if (Res.getNode()) return Res; 2198 2199 EVT VT = N->getValueType(0); 2200 DebugLoc DL = N->getDebugLoc(); 2201 2202 // If the type twice as wide is legal, transform the mulhu to a wider multiply 2203 // plus a shift. 2204 if (VT.isSimple() && !VT.isVector()) { 2205 MVT Simple = VT.getSimpleVT(); 2206 unsigned SimpleSize = Simple.getSizeInBits(); 2207 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2); 2208 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { 2209 SDValue Lo = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(0)); 2210 SDValue Hi = DAG.getNode(ISD::SIGN_EXTEND, DL, NewVT, N->getOperand(1)); 2211 Lo = DAG.getNode(ISD::MUL, DL, NewVT, Lo, Hi); 2212 // Compute the high part as N1. 2213 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo, 2214 DAG.getConstant(SimpleSize, getShiftAmountTy(Lo.getValueType()))); 2215 Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi); 2216 // Compute the low part as N0. 2217 Lo = DAG.getNode(ISD::TRUNCATE, DL, VT, Lo); 2218 return CombineTo(N, Lo, Hi); 2219 } 2220 } 2221 2222 return SDValue(); 2223} 2224 2225SDValue DAGCombiner::visitUMUL_LOHI(SDNode *N) { 2226 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU); 2227 if (Res.getNode()) return Res; 2228 2229 EVT VT = N->getValueType(0); 2230 DebugLoc DL = N->getDebugLoc(); 2231 2232 // If the type twice as wide is legal, transform the mulhu to a wider multiply 2233 // plus a shift. 2234 if (VT.isSimple() && !VT.isVector()) { 2235 MVT Simple = VT.getSimpleVT(); 2236 unsigned SimpleSize = Simple.getSizeInBits(); 2237 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), SimpleSize*2); 2238 if (TLI.isOperationLegal(ISD::MUL, NewVT)) { 2239 SDValue Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(0)); 2240 SDValue Hi = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(1)); 2241 Lo = DAG.getNode(ISD::MUL, DL, NewVT, Lo, Hi); 2242 // Compute the high part as N1. 2243 Hi = DAG.getNode(ISD::SRL, DL, NewVT, Lo, 2244 DAG.getConstant(SimpleSize, getShiftAmountTy(Lo.getValueType()))); 2245 Hi = DAG.getNode(ISD::TRUNCATE, DL, VT, Hi); 2246 // Compute the low part as N0. 2247 Lo = DAG.getNode(ISD::TRUNCATE, DL, VT, Lo); 2248 return CombineTo(N, Lo, Hi); 2249 } 2250 } 2251 2252 return SDValue(); 2253} 2254 2255SDValue DAGCombiner::visitSMULO(SDNode *N) { 2256 // (smulo x, 2) -> (saddo x, x) 2257 if (ConstantSDNode *C2 = dyn_cast<ConstantSDNode>(N->getOperand(1))) 2258 if (C2->getAPIntValue() == 2) 2259 return DAG.getNode(ISD::SADDO, N->getDebugLoc(), N->getVTList(), 2260 N->getOperand(0), N->getOperand(0)); 2261 2262 return SDValue(); 2263} 2264 2265SDValue DAGCombiner::visitUMULO(SDNode *N) { 2266 // (umulo x, 2) -> (uaddo x, x) 2267 if (ConstantSDNode *C2 = dyn_cast<ConstantSDNode>(N->getOperand(1))) 2268 if (C2->getAPIntValue() == 2) 2269 return DAG.getNode(ISD::UADDO, N->getDebugLoc(), N->getVTList(), 2270 N->getOperand(0), N->getOperand(0)); 2271 2272 return SDValue(); 2273} 2274 2275SDValue DAGCombiner::visitSDIVREM(SDNode *N) { 2276 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM); 2277 if (Res.getNode()) return Res; 2278 2279 return SDValue(); 2280} 2281 2282SDValue DAGCombiner::visitUDIVREM(SDNode *N) { 2283 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM); 2284 if (Res.getNode()) return Res; 2285 2286 return SDValue(); 2287} 2288 2289/// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with 2290/// two operands of the same opcode, try to simplify it. 2291SDValue DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) { 2292 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1); 2293 EVT VT = N0.getValueType(); 2294 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!"); 2295 2296 // Bail early if none of these transforms apply. 2297 if (N0.getNode()->getNumOperands() == 0) return SDValue(); 2298 2299 // For each of OP in AND/OR/XOR: 2300 // fold (OP (zext x), (zext y)) -> (zext (OP x, y)) 2301 // fold (OP (sext x), (sext y)) -> (sext (OP x, y)) 2302 // fold (OP (aext x), (aext y)) -> (aext (OP x, y)) 2303 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y)) (if trunc isn't free) 2304 // 2305 // do not sink logical op inside of a vector extend, since it may combine 2306 // into a vsetcc. 2307 EVT Op0VT = N0.getOperand(0).getValueType(); 2308 if ((N0.getOpcode() == ISD::ZERO_EXTEND || 2309 N0.getOpcode() == ISD::SIGN_EXTEND || 2310 // Avoid infinite looping with PromoteIntBinOp. 2311 (N0.getOpcode() == ISD::ANY_EXTEND && 2312 (!LegalTypes || TLI.isTypeDesirableForOp(N->getOpcode(), Op0VT))) || 2313 (N0.getOpcode() == ISD::TRUNCATE && 2314 (!TLI.isZExtFree(VT, Op0VT) || 2315 !TLI.isTruncateFree(Op0VT, VT)) && 2316 TLI.isTypeLegal(Op0VT))) && 2317 !VT.isVector() && 2318 Op0VT == N1.getOperand(0).getValueType() && 2319 (!LegalOperations || TLI.isOperationLegal(N->getOpcode(), Op0VT))) { 2320 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(), 2321 N0.getOperand(0).getValueType(), 2322 N0.getOperand(0), N1.getOperand(0)); 2323 AddToWorkList(ORNode.getNode()); 2324 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, ORNode); 2325 } 2326 2327 // For each of OP in SHL/SRL/SRA/AND... 2328 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z) 2329 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z) 2330 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z) 2331 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL || 2332 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) && 2333 N0.getOperand(1) == N1.getOperand(1)) { 2334 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(), 2335 N0.getOperand(0).getValueType(), 2336 N0.getOperand(0), N1.getOperand(0)); 2337 AddToWorkList(ORNode.getNode()); 2338 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, 2339 ORNode, N0.getOperand(1)); 2340 } 2341 2342 // Simplify xor/and/or (bitcast(A), bitcast(B)) -> bitcast(op (A,B)) 2343 // Only perform this optimization after type legalization and before 2344 // LegalizeVectorOprs. LegalizeVectorOprs promotes vector operations by 2345 // adding bitcasts. For example (xor v4i32) is promoted to (v2i64), and 2346 // we don't want to undo this promotion. 2347 // We also handle SCALAR_TO_VECTOR because xor/or/and operations are cheaper 2348 // on scalars. 2349 if ((N0.getOpcode() == ISD::BITCAST || N0.getOpcode() == ISD::SCALAR_TO_VECTOR) 2350 && Level == AfterLegalizeTypes) { 2351 SDValue In0 = N0.getOperand(0); 2352 SDValue In1 = N1.getOperand(0); 2353 EVT In0Ty = In0.getValueType(); 2354 EVT In1Ty = In1.getValueType(); 2355 // If both incoming values are integers, and the original types are the same. 2356 if (In0Ty.isInteger() && In1Ty.isInteger() && In0Ty == In1Ty) { 2357 SDValue Op = DAG.getNode(N->getOpcode(), N->getDebugLoc(), In0Ty, In0, In1); 2358 SDValue BC = DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, Op); 2359 AddToWorkList(Op.getNode()); 2360 return BC; 2361 } 2362 } 2363 2364 // Xor/and/or are indifferent to the swizzle operation (shuffle of one value). 2365 // Simplify xor/and/or (shuff(A), shuff(B)) -> shuff(op (A,B)) 2366 // If both shuffles use the same mask, and both shuffle within a single 2367 // vector, then it is worthwhile to move the swizzle after the operation. 2368 // The type-legalizer generates this pattern when loading illegal 2369 // vector types from memory. In many cases this allows additional shuffle 2370 // optimizations. 2371 if (N0.getOpcode() == ISD::VECTOR_SHUFFLE && Level < AfterLegalizeDAG && 2372 N0.getOperand(1).getOpcode() == ISD::UNDEF && 2373 N1.getOperand(1).getOpcode() == ISD::UNDEF) { 2374 ShuffleVectorSDNode *SVN0 = cast<ShuffleVectorSDNode>(N0); 2375 ShuffleVectorSDNode *SVN1 = cast<ShuffleVectorSDNode>(N1); 2376 2377 assert(N0.getOperand(0).getValueType() == N1.getOperand(1).getValueType() && 2378 "Inputs to shuffles are not the same type"); 2379 2380 unsigned NumElts = VT.getVectorNumElements(); 2381 2382 // Check that both shuffles use the same mask. The masks are known to be of 2383 // the same length because the result vector type is the same. 2384 bool SameMask = true; 2385 for (unsigned i = 0; i != NumElts; ++i) { 2386 int Idx0 = SVN0->getMaskElt(i); 2387 int Idx1 = SVN1->getMaskElt(i); 2388 if (Idx0 != Idx1) { 2389 SameMask = false; 2390 break; 2391 } 2392 } 2393 2394 if (SameMask) { 2395 SDValue Op = DAG.getNode(N->getOpcode(), N->getDebugLoc(), VT, 2396 N0.getOperand(0), N1.getOperand(0)); 2397 AddToWorkList(Op.getNode()); 2398 return DAG.getVectorShuffle(VT, N->getDebugLoc(), Op, 2399 DAG.getUNDEF(VT), &SVN0->getMask()[0]); 2400 } 2401 } 2402 2403 return SDValue(); 2404} 2405 2406SDValue DAGCombiner::visitAND(SDNode *N) { 2407 SDValue N0 = N->getOperand(0); 2408 SDValue N1 = N->getOperand(1); 2409 SDValue LL, LR, RL, RR, CC0, CC1; 2410 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2411 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2412 EVT VT = N1.getValueType(); 2413 unsigned BitWidth = VT.getScalarType().getSizeInBits(); 2414 2415 // fold vector ops 2416 if (VT.isVector()) { 2417 SDValue FoldedVOp = SimplifyVBinOp(N); 2418 if (FoldedVOp.getNode()) return FoldedVOp; 2419 } 2420 2421 // fold (and x, undef) -> 0 2422 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 2423 return DAG.getConstant(0, VT); 2424 // fold (and c1, c2) -> c1&c2 2425 if (N0C && N1C) 2426 return DAG.FoldConstantArithmetic(ISD::AND, VT, N0C, N1C); 2427 // canonicalize constant to RHS 2428 if (N0C && !N1C) 2429 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N1, N0); 2430 // fold (and x, -1) -> x 2431 if (N1C && N1C->isAllOnesValue()) 2432 return N0; 2433 // if (and x, c) is known to be zero, return 0 2434 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0), 2435 APInt::getAllOnesValue(BitWidth))) 2436 return DAG.getConstant(0, VT); 2437 // reassociate and 2438 SDValue RAND = ReassociateOps(ISD::AND, N->getDebugLoc(), N0, N1); 2439 if (RAND.getNode() != 0) 2440 return RAND; 2441 // fold (and (or x, C), D) -> D if (C & D) == D 2442 if (N1C && N0.getOpcode() == ISD::OR) 2443 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 2444 if ((ORI->getAPIntValue() & N1C->getAPIntValue()) == N1C->getAPIntValue()) 2445 return N1; 2446 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits. 2447 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 2448 SDValue N0Op0 = N0.getOperand(0); 2449 APInt Mask = ~N1C->getAPIntValue(); 2450 Mask = Mask.trunc(N0Op0.getValueSizeInBits()); 2451 if (DAG.MaskedValueIsZero(N0Op0, Mask)) { 2452 SDValue Zext = DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), 2453 N0.getValueType(), N0Op0); 2454 2455 // Replace uses of the AND with uses of the Zero extend node. 2456 CombineTo(N, Zext); 2457 2458 // We actually want to replace all uses of the any_extend with the 2459 // zero_extend, to avoid duplicating things. This will later cause this 2460 // AND to be folded. 2461 CombineTo(N0.getNode(), Zext); 2462 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2463 } 2464 } 2465 // similarly fold (and (X (load ([non_ext|any_ext|zero_ext] V))), c) -> 2466 // (X (load ([non_ext|zero_ext] V))) if 'and' only clears top bits which must 2467 // already be zero by virtue of the width of the base type of the load. 2468 // 2469 // the 'X' node here can either be nothing or an extract_vector_elt to catch 2470 // more cases. 2471 if ((N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT && 2472 N0.getOperand(0).getOpcode() == ISD::LOAD) || 2473 N0.getOpcode() == ISD::LOAD) { 2474 LoadSDNode *Load = cast<LoadSDNode>( (N0.getOpcode() == ISD::LOAD) ? 2475 N0 : N0.getOperand(0) ); 2476 2477 // Get the constant (if applicable) the zero'th operand is being ANDed with. 2478 // This can be a pure constant or a vector splat, in which case we treat the 2479 // vector as a scalar and use the splat value. 2480 APInt Constant = APInt::getNullValue(1); 2481 if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(N1)) { 2482 Constant = C->getAPIntValue(); 2483 } else if (BuildVectorSDNode *Vector = dyn_cast<BuildVectorSDNode>(N1)) { 2484 APInt SplatValue, SplatUndef; 2485 unsigned SplatBitSize; 2486 bool HasAnyUndefs; 2487 bool IsSplat = Vector->isConstantSplat(SplatValue, SplatUndef, 2488 SplatBitSize, HasAnyUndefs); 2489 if (IsSplat) { 2490 // Undef bits can contribute to a possible optimisation if set, so 2491 // set them. 2492 SplatValue |= SplatUndef; 2493 2494 // The splat value may be something like "0x00FFFFFF", which means 0 for 2495 // the first vector value and FF for the rest, repeating. We need a mask 2496 // that will apply equally to all members of the vector, so AND all the 2497 // lanes of the constant together. 2498 EVT VT = Vector->getValueType(0); 2499 unsigned BitWidth = VT.getVectorElementType().getSizeInBits(); 2500 2501 // If the splat value has been compressed to a bitlength lower 2502 // than the size of the vector lane, we need to re-expand it to 2503 // the lane size. 2504 if (BitWidth > SplatBitSize) 2505 for (SplatValue = SplatValue.zextOrTrunc(BitWidth); 2506 SplatBitSize < BitWidth; 2507 SplatBitSize = SplatBitSize * 2) 2508 SplatValue |= SplatValue.shl(SplatBitSize); 2509 2510 Constant = APInt::getAllOnesValue(BitWidth); 2511 for (unsigned i = 0, n = SplatBitSize/BitWidth; i < n; ++i) 2512 Constant &= SplatValue.lshr(i*BitWidth).zextOrTrunc(BitWidth); 2513 } 2514 } 2515 2516 // If we want to change an EXTLOAD to a ZEXTLOAD, ensure a ZEXTLOAD is 2517 // actually legal and isn't going to get expanded, else this is a false 2518 // optimisation. 2519 bool CanZextLoadProfitably = TLI.isLoadExtLegal(ISD::ZEXTLOAD, 2520 Load->getMemoryVT()); 2521 2522 // Resize the constant to the same size as the original memory access before 2523 // extension. If it is still the AllOnesValue then this AND is completely 2524 // unneeded. 2525 Constant = 2526 Constant.zextOrTrunc(Load->getMemoryVT().getScalarType().getSizeInBits()); 2527 2528 bool B; 2529 switch (Load->getExtensionType()) { 2530 default: B = false; break; 2531 case ISD::EXTLOAD: B = CanZextLoadProfitably; break; 2532 case ISD::ZEXTLOAD: 2533 case ISD::NON_EXTLOAD: B = true; break; 2534 } 2535 2536 if (B && Constant.isAllOnesValue()) { 2537 // If the load type was an EXTLOAD, convert to ZEXTLOAD in order to 2538 // preserve semantics once we get rid of the AND. 2539 SDValue NewLoad(Load, 0); 2540 if (Load->getExtensionType() == ISD::EXTLOAD) { 2541 NewLoad = DAG.getLoad(Load->getAddressingMode(), ISD::ZEXTLOAD, 2542 Load->getValueType(0), Load->getDebugLoc(), 2543 Load->getChain(), Load->getBasePtr(), 2544 Load->getOffset(), Load->getMemoryVT(), 2545 Load->getMemOperand()); 2546 // Replace uses of the EXTLOAD with the new ZEXTLOAD. 2547 if (Load->getNumValues() == 3) { 2548 // PRE/POST_INC loads have 3 values. 2549 SDValue To[] = { NewLoad.getValue(0), NewLoad.getValue(1), 2550 NewLoad.getValue(2) }; 2551 CombineTo(Load, To, 3, true); 2552 } else { 2553 CombineTo(Load, NewLoad.getValue(0), NewLoad.getValue(1)); 2554 } 2555 } 2556 2557 // Fold the AND away, taking care not to fold to the old load node if we 2558 // replaced it. 2559 CombineTo(N, (N0.getNode() == Load) ? NewLoad : N0); 2560 2561 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2562 } 2563 } 2564 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y)) 2565 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 2566 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 2567 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 2568 2569 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 2570 LL.getValueType().isInteger()) { 2571 // fold (and (seteq X, 0), (seteq Y, 0)) -> (seteq (or X, Y), 0) 2572 if (cast<ConstantSDNode>(LR)->isNullValue() && Op1 == ISD::SETEQ) { 2573 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(), 2574 LR.getValueType(), LL, RL); 2575 AddToWorkList(ORNode.getNode()); 2576 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 2577 } 2578 // fold (and (seteq X, -1), (seteq Y, -1)) -> (seteq (and X, Y), -1) 2579 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) { 2580 SDValue ANDNode = DAG.getNode(ISD::AND, N0.getDebugLoc(), 2581 LR.getValueType(), LL, RL); 2582 AddToWorkList(ANDNode.getNode()); 2583 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1); 2584 } 2585 // fold (and (setgt X, -1), (setgt Y, -1)) -> (setgt (or X, Y), -1) 2586 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) { 2587 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(), 2588 LR.getValueType(), LL, RL); 2589 AddToWorkList(ORNode.getNode()); 2590 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 2591 } 2592 } 2593 // canonicalize equivalent to ll == rl 2594 if (LL == RR && LR == RL) { 2595 Op1 = ISD::getSetCCSwappedOperands(Op1); 2596 std::swap(RL, RR); 2597 } 2598 if (LL == RL && LR == RR) { 2599 bool isInteger = LL.getValueType().isInteger(); 2600 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger); 2601 if (Result != ISD::SETCC_INVALID && 2602 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType()))) 2603 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(), 2604 LL, LR, Result); 2605 } 2606 } 2607 2608 // Simplify: (and (op x...), (op y...)) -> (op (and x, y)) 2609 if (N0.getOpcode() == N1.getOpcode()) { 2610 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 2611 if (Tmp.getNode()) return Tmp; 2612 } 2613 2614 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1) 2615 // fold (and (sra)) -> (and (srl)) when possible. 2616 if (!VT.isVector() && 2617 SimplifyDemandedBits(SDValue(N, 0))) 2618 return SDValue(N, 0); 2619 2620 // fold (zext_inreg (extload x)) -> (zextload x) 2621 if (ISD::isEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode())) { 2622 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2623 EVT MemVT = LN0->getMemoryVT(); 2624 // If we zero all the possible extended bits, then we can turn this into 2625 // a zextload if we are running before legalize or the operation is legal. 2626 unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits(); 2627 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 2628 BitWidth - MemVT.getScalarType().getSizeInBits())) && 2629 ((!LegalOperations && !LN0->isVolatile()) || 2630 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) { 2631 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT, 2632 LN0->getChain(), LN0->getBasePtr(), 2633 LN0->getPointerInfo(), MemVT, 2634 LN0->isVolatile(), LN0->isNonTemporal(), 2635 LN0->getAlignment()); 2636 AddToWorkList(N); 2637 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 2638 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2639 } 2640 } 2641 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use 2642 if (ISD::isSEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 2643 N0.hasOneUse()) { 2644 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2645 EVT MemVT = LN0->getMemoryVT(); 2646 // If we zero all the possible extended bits, then we can turn this into 2647 // a zextload if we are running before legalize or the operation is legal. 2648 unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits(); 2649 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 2650 BitWidth - MemVT.getScalarType().getSizeInBits())) && 2651 ((!LegalOperations && !LN0->isVolatile()) || 2652 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) { 2653 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT, 2654 LN0->getChain(), 2655 LN0->getBasePtr(), LN0->getPointerInfo(), 2656 MemVT, 2657 LN0->isVolatile(), LN0->isNonTemporal(), 2658 LN0->getAlignment()); 2659 AddToWorkList(N); 2660 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 2661 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2662 } 2663 } 2664 2665 // fold (and (load x), 255) -> (zextload x, i8) 2666 // fold (and (extload x, i16), 255) -> (zextload x, i8) 2667 // fold (and (any_ext (extload x, i16)), 255) -> (zextload x, i8) 2668 if (N1C && (N0.getOpcode() == ISD::LOAD || 2669 (N0.getOpcode() == ISD::ANY_EXTEND && 2670 N0.getOperand(0).getOpcode() == ISD::LOAD))) { 2671 bool HasAnyExt = N0.getOpcode() == ISD::ANY_EXTEND; 2672 LoadSDNode *LN0 = HasAnyExt 2673 ? cast<LoadSDNode>(N0.getOperand(0)) 2674 : cast<LoadSDNode>(N0); 2675 if (LN0->getExtensionType() != ISD::SEXTLOAD && 2676 LN0->isUnindexed() && N0.hasOneUse() && LN0->hasOneUse()) { 2677 uint32_t ActiveBits = N1C->getAPIntValue().getActiveBits(); 2678 if (ActiveBits > 0 && APIntOps::isMask(ActiveBits, N1C->getAPIntValue())){ 2679 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), ActiveBits); 2680 EVT LoadedVT = LN0->getMemoryVT(); 2681 2682 if (ExtVT == LoadedVT && 2683 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) { 2684 EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT; 2685 2686 SDValue NewLoad = 2687 DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), LoadResultTy, 2688 LN0->getChain(), LN0->getBasePtr(), 2689 LN0->getPointerInfo(), 2690 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(), 2691 LN0->getAlignment()); 2692 AddToWorkList(N); 2693 CombineTo(LN0, NewLoad, NewLoad.getValue(1)); 2694 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2695 } 2696 2697 // Do not change the width of a volatile load. 2698 // Do not generate loads of non-round integer types since these can 2699 // be expensive (and would be wrong if the type is not byte sized). 2700 if (!LN0->isVolatile() && LoadedVT.bitsGT(ExtVT) && ExtVT.isRound() && 2701 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) { 2702 EVT PtrType = LN0->getOperand(1).getValueType(); 2703 2704 unsigned Alignment = LN0->getAlignment(); 2705 SDValue NewPtr = LN0->getBasePtr(); 2706 2707 // For big endian targets, we need to add an offset to the pointer 2708 // to load the correct bytes. For little endian systems, we merely 2709 // need to read fewer bytes from the same pointer. 2710 if (TLI.isBigEndian()) { 2711 unsigned LVTStoreBytes = LoadedVT.getStoreSize(); 2712 unsigned EVTStoreBytes = ExtVT.getStoreSize(); 2713 unsigned PtrOff = LVTStoreBytes - EVTStoreBytes; 2714 NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(), PtrType, 2715 NewPtr, DAG.getConstant(PtrOff, PtrType)); 2716 Alignment = MinAlign(Alignment, PtrOff); 2717 } 2718 2719 AddToWorkList(NewPtr.getNode()); 2720 2721 EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT; 2722 SDValue Load = 2723 DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), LoadResultTy, 2724 LN0->getChain(), NewPtr, 2725 LN0->getPointerInfo(), 2726 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(), 2727 Alignment); 2728 AddToWorkList(N); 2729 CombineTo(LN0, Load, Load.getValue(1)); 2730 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2731 } 2732 } 2733 } 2734 } 2735 2736 if (N0.getOpcode() == ISD::ADD && N1.getOpcode() == ISD::SRL && 2737 VT.getSizeInBits() <= 64) { 2738 if (ConstantSDNode *ADDI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 2739 APInt ADDC = ADDI->getAPIntValue(); 2740 if (!TLI.isLegalAddImmediate(ADDC.getSExtValue())) { 2741 // Look for (and (add x, c1), (lshr y, c2)). If C1 wasn't a legal 2742 // immediate for an add, but it is legal if its top c2 bits are set, 2743 // transform the ADD so the immediate doesn't need to be materialized 2744 // in a register. 2745 if (ConstantSDNode *SRLI = dyn_cast<ConstantSDNode>(N1.getOperand(1))) { 2746 APInt Mask = APInt::getHighBitsSet(VT.getSizeInBits(), 2747 SRLI->getZExtValue()); 2748 if (DAG.MaskedValueIsZero(N0.getOperand(1), Mask)) { 2749 ADDC |= Mask; 2750 if (TLI.isLegalAddImmediate(ADDC.getSExtValue())) { 2751 SDValue NewAdd = 2752 DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, 2753 N0.getOperand(0), DAG.getConstant(ADDC, VT)); 2754 CombineTo(N0.getNode(), NewAdd); 2755 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2756 } 2757 } 2758 } 2759 } 2760 } 2761 } 2762 2763 2764 return SDValue(); 2765} 2766 2767/// MatchBSwapHWord - Match (a >> 8) | (a << 8) as (bswap a) >> 16 2768/// 2769SDValue DAGCombiner::MatchBSwapHWordLow(SDNode *N, SDValue N0, SDValue N1, 2770 bool DemandHighBits) { 2771 if (!LegalOperations) 2772 return SDValue(); 2773 2774 EVT VT = N->getValueType(0); 2775 if (VT != MVT::i64 && VT != MVT::i32 && VT != MVT::i16) 2776 return SDValue(); 2777 if (!TLI.isOperationLegal(ISD::BSWAP, VT)) 2778 return SDValue(); 2779 2780 // Recognize (and (shl a, 8), 0xff), (and (srl a, 8), 0xff00) 2781 bool LookPassAnd0 = false; 2782 bool LookPassAnd1 = false; 2783 if (N0.getOpcode() == ISD::AND && N0.getOperand(0).getOpcode() == ISD::SRL) 2784 std::swap(N0, N1); 2785 if (N1.getOpcode() == ISD::AND && N1.getOperand(0).getOpcode() == ISD::SHL) 2786 std::swap(N0, N1); 2787 if (N0.getOpcode() == ISD::AND) { 2788 if (!N0.getNode()->hasOneUse()) 2789 return SDValue(); 2790 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2791 if (!N01C || N01C->getZExtValue() != 0xFF00) 2792 return SDValue(); 2793 N0 = N0.getOperand(0); 2794 LookPassAnd0 = true; 2795 } 2796 2797 if (N1.getOpcode() == ISD::AND) { 2798 if (!N1.getNode()->hasOneUse()) 2799 return SDValue(); 2800 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1)); 2801 if (!N11C || N11C->getZExtValue() != 0xFF) 2802 return SDValue(); 2803 N1 = N1.getOperand(0); 2804 LookPassAnd1 = true; 2805 } 2806 2807 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL) 2808 std::swap(N0, N1); 2809 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL) 2810 return SDValue(); 2811 if (!N0.getNode()->hasOneUse() || 2812 !N1.getNode()->hasOneUse()) 2813 return SDValue(); 2814 2815 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2816 ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1)); 2817 if (!N01C || !N11C) 2818 return SDValue(); 2819 if (N01C->getZExtValue() != 8 || N11C->getZExtValue() != 8) 2820 return SDValue(); 2821 2822 // Look for (shl (and a, 0xff), 8), (srl (and a, 0xff00), 8) 2823 SDValue N00 = N0->getOperand(0); 2824 if (!LookPassAnd0 && N00.getOpcode() == ISD::AND) { 2825 if (!N00.getNode()->hasOneUse()) 2826 return SDValue(); 2827 ConstantSDNode *N001C = dyn_cast<ConstantSDNode>(N00.getOperand(1)); 2828 if (!N001C || N001C->getZExtValue() != 0xFF) 2829 return SDValue(); 2830 N00 = N00.getOperand(0); 2831 LookPassAnd0 = true; 2832 } 2833 2834 SDValue N10 = N1->getOperand(0); 2835 if (!LookPassAnd1 && N10.getOpcode() == ISD::AND) { 2836 if (!N10.getNode()->hasOneUse()) 2837 return SDValue(); 2838 ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N10.getOperand(1)); 2839 if (!N101C || N101C->getZExtValue() != 0xFF00) 2840 return SDValue(); 2841 N10 = N10.getOperand(0); 2842 LookPassAnd1 = true; 2843 } 2844 2845 if (N00 != N10) 2846 return SDValue(); 2847 2848 // Make sure everything beyond the low halfword is zero since the SRL 16 2849 // will clear the top bits. 2850 unsigned OpSizeInBits = VT.getSizeInBits(); 2851 if (DemandHighBits && OpSizeInBits > 16 && 2852 (!LookPassAnd0 || !LookPassAnd1) && 2853 !DAG.MaskedValueIsZero(N10, APInt::getHighBitsSet(OpSizeInBits, 16))) 2854 return SDValue(); 2855 2856 SDValue Res = DAG.getNode(ISD::BSWAP, N->getDebugLoc(), VT, N00); 2857 if (OpSizeInBits > 16) 2858 Res = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, Res, 2859 DAG.getConstant(OpSizeInBits-16, getShiftAmountTy(VT))); 2860 return Res; 2861} 2862 2863/// isBSwapHWordElement - Return true if the specified node is an element 2864/// that makes up a 32-bit packed halfword byteswap. i.e. 2865/// ((x&0xff)<<8)|((x&0xff00)>>8)|((x&0x00ff0000)<<8)|((x&0xff000000)>>8) 2866static bool isBSwapHWordElement(SDValue N, SmallVector<SDNode*,4> &Parts) { 2867 if (!N.getNode()->hasOneUse()) 2868 return false; 2869 2870 unsigned Opc = N.getOpcode(); 2871 if (Opc != ISD::AND && Opc != ISD::SHL && Opc != ISD::SRL) 2872 return false; 2873 2874 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N.getOperand(1)); 2875 if (!N1C) 2876 return false; 2877 2878 unsigned Num; 2879 switch (N1C->getZExtValue()) { 2880 default: 2881 return false; 2882 case 0xFF: Num = 0; break; 2883 case 0xFF00: Num = 1; break; 2884 case 0xFF0000: Num = 2; break; 2885 case 0xFF000000: Num = 3; break; 2886 } 2887 2888 // Look for (x & 0xff) << 8 as well as ((x << 8) & 0xff00). 2889 SDValue N0 = N.getOperand(0); 2890 if (Opc == ISD::AND) { 2891 if (Num == 0 || Num == 2) { 2892 // (x >> 8) & 0xff 2893 // (x >> 8) & 0xff0000 2894 if (N0.getOpcode() != ISD::SRL) 2895 return false; 2896 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2897 if (!C || C->getZExtValue() != 8) 2898 return false; 2899 } else { 2900 // (x << 8) & 0xff00 2901 // (x << 8) & 0xff000000 2902 if (N0.getOpcode() != ISD::SHL) 2903 return false; 2904 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2905 if (!C || C->getZExtValue() != 8) 2906 return false; 2907 } 2908 } else if (Opc == ISD::SHL) { 2909 // (x & 0xff) << 8 2910 // (x & 0xff0000) << 8 2911 if (Num != 0 && Num != 2) 2912 return false; 2913 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N.getOperand(1)); 2914 if (!C || C->getZExtValue() != 8) 2915 return false; 2916 } else { // Opc == ISD::SRL 2917 // (x & 0xff00) >> 8 2918 // (x & 0xff000000) >> 8 2919 if (Num != 1 && Num != 3) 2920 return false; 2921 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N.getOperand(1)); 2922 if (!C || C->getZExtValue() != 8) 2923 return false; 2924 } 2925 2926 if (Parts[Num]) 2927 return false; 2928 2929 Parts[Num] = N0.getOperand(0).getNode(); 2930 return true; 2931} 2932 2933/// MatchBSwapHWord - Match a 32-bit packed halfword bswap. That is 2934/// ((x&0xff)<<8)|((x&0xff00)>>8)|((x&0x00ff0000)<<8)|((x&0xff000000)>>8) 2935/// => (rotl (bswap x), 16) 2936SDValue DAGCombiner::MatchBSwapHWord(SDNode *N, SDValue N0, SDValue N1) { 2937 if (!LegalOperations) 2938 return SDValue(); 2939 2940 EVT VT = N->getValueType(0); 2941 if (VT != MVT::i32) 2942 return SDValue(); 2943 if (!TLI.isOperationLegal(ISD::BSWAP, VT)) 2944 return SDValue(); 2945 2946 SmallVector<SDNode*,4> Parts(4, (SDNode*)0); 2947 // Look for either 2948 // (or (or (and), (and)), (or (and), (and))) 2949 // (or (or (or (and), (and)), (and)), (and)) 2950 if (N0.getOpcode() != ISD::OR) 2951 return SDValue(); 2952 SDValue N00 = N0.getOperand(0); 2953 SDValue N01 = N0.getOperand(1); 2954 2955 if (N1.getOpcode() == ISD::OR) { 2956 // (or (or (and), (and)), (or (and), (and))) 2957 SDValue N000 = N00.getOperand(0); 2958 if (!isBSwapHWordElement(N000, Parts)) 2959 return SDValue(); 2960 2961 SDValue N001 = N00.getOperand(1); 2962 if (!isBSwapHWordElement(N001, Parts)) 2963 return SDValue(); 2964 SDValue N010 = N01.getOperand(0); 2965 if (!isBSwapHWordElement(N010, Parts)) 2966 return SDValue(); 2967 SDValue N011 = N01.getOperand(1); 2968 if (!isBSwapHWordElement(N011, Parts)) 2969 return SDValue(); 2970 } else { 2971 // (or (or (or (and), (and)), (and)), (and)) 2972 if (!isBSwapHWordElement(N1, Parts)) 2973 return SDValue(); 2974 if (!isBSwapHWordElement(N01, Parts)) 2975 return SDValue(); 2976 if (N00.getOpcode() != ISD::OR) 2977 return SDValue(); 2978 SDValue N000 = N00.getOperand(0); 2979 if (!isBSwapHWordElement(N000, Parts)) 2980 return SDValue(); 2981 SDValue N001 = N00.getOperand(1); 2982 if (!isBSwapHWordElement(N001, Parts)) 2983 return SDValue(); 2984 } 2985 2986 // Make sure the parts are all coming from the same node. 2987 if (Parts[0] != Parts[1] || Parts[0] != Parts[2] || Parts[0] != Parts[3]) 2988 return SDValue(); 2989 2990 SDValue BSwap = DAG.getNode(ISD::BSWAP, N->getDebugLoc(), VT, 2991 SDValue(Parts[0],0)); 2992 2993 // Result of the bswap should be rotated by 16. If it's not legal, than 2994 // do (x << 16) | (x >> 16). 2995 SDValue ShAmt = DAG.getConstant(16, getShiftAmountTy(VT)); 2996 if (TLI.isOperationLegalOrCustom(ISD::ROTL, VT)) 2997 return DAG.getNode(ISD::ROTL, N->getDebugLoc(), VT, BSwap, ShAmt); 2998 else if (TLI.isOperationLegalOrCustom(ISD::ROTR, VT)) 2999 return DAG.getNode(ISD::ROTR, N->getDebugLoc(), VT, BSwap, ShAmt); 3000 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, 3001 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, BSwap, ShAmt), 3002 DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, BSwap, ShAmt)); 3003} 3004 3005SDValue DAGCombiner::visitOR(SDNode *N) { 3006 SDValue N0 = N->getOperand(0); 3007 SDValue N1 = N->getOperand(1); 3008 SDValue LL, LR, RL, RR, CC0, CC1; 3009 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3010 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3011 EVT VT = N1.getValueType(); 3012 3013 // fold vector ops 3014 if (VT.isVector()) { 3015 SDValue FoldedVOp = SimplifyVBinOp(N); 3016 if (FoldedVOp.getNode()) return FoldedVOp; 3017 } 3018 3019 // fold (or x, undef) -> -1 3020 if (!LegalOperations && 3021 (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF)) { 3022 EVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT; 3023 return DAG.getConstant(APInt::getAllOnesValue(EltVT.getSizeInBits()), VT); 3024 } 3025 // fold (or c1, c2) -> c1|c2 3026 if (N0C && N1C) 3027 return DAG.FoldConstantArithmetic(ISD::OR, VT, N0C, N1C); 3028 // canonicalize constant to RHS 3029 if (N0C && !N1C) 3030 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N1, N0); 3031 // fold (or x, 0) -> x 3032 if (N1C && N1C->isNullValue()) 3033 return N0; 3034 // fold (or x, -1) -> -1 3035 if (N1C && N1C->isAllOnesValue()) 3036 return N1; 3037 // fold (or x, c) -> c iff (x & ~c) == 0 3038 if (N1C && DAG.MaskedValueIsZero(N0, ~N1C->getAPIntValue())) 3039 return N1; 3040 3041 // Recognize halfword bswaps as (bswap + rotl 16) or (bswap + shl 16) 3042 SDValue BSwap = MatchBSwapHWord(N, N0, N1); 3043 if (BSwap.getNode() != 0) 3044 return BSwap; 3045 BSwap = MatchBSwapHWordLow(N, N0, N1); 3046 if (BSwap.getNode() != 0) 3047 return BSwap; 3048 3049 // reassociate or 3050 SDValue ROR = ReassociateOps(ISD::OR, N->getDebugLoc(), N0, N1); 3051 if (ROR.getNode() != 0) 3052 return ROR; 3053 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2) 3054 // iff (c1 & c2) == 0. 3055 if (N1C && N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() && 3056 isa<ConstantSDNode>(N0.getOperand(1))) { 3057 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1)); 3058 if ((C1->getAPIntValue() & N1C->getAPIntValue()) != 0) 3059 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 3060 DAG.getNode(ISD::OR, N0.getDebugLoc(), VT, 3061 N0.getOperand(0), N1), 3062 DAG.FoldConstantArithmetic(ISD::OR, VT, N1C, C1)); 3063 } 3064 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y)) 3065 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 3066 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 3067 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 3068 3069 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 3070 LL.getValueType().isInteger()) { 3071 // fold (or (setne X, 0), (setne Y, 0)) -> (setne (or X, Y), 0) 3072 // fold (or (setlt X, 0), (setlt Y, 0)) -> (setne (or X, Y), 0) 3073 if (cast<ConstantSDNode>(LR)->isNullValue() && 3074 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) { 3075 SDValue ORNode = DAG.getNode(ISD::OR, LR.getDebugLoc(), 3076 LR.getValueType(), LL, RL); 3077 AddToWorkList(ORNode.getNode()); 3078 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 3079 } 3080 // fold (or (setne X, -1), (setne Y, -1)) -> (setne (and X, Y), -1) 3081 // fold (or (setgt X, -1), (setgt Y -1)) -> (setgt (and X, Y), -1) 3082 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && 3083 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) { 3084 SDValue ANDNode = DAG.getNode(ISD::AND, LR.getDebugLoc(), 3085 LR.getValueType(), LL, RL); 3086 AddToWorkList(ANDNode.getNode()); 3087 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1); 3088 } 3089 } 3090 // canonicalize equivalent to ll == rl 3091 if (LL == RR && LR == RL) { 3092 Op1 = ISD::getSetCCSwappedOperands(Op1); 3093 std::swap(RL, RR); 3094 } 3095 if (LL == RL && LR == RR) { 3096 bool isInteger = LL.getValueType().isInteger(); 3097 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger); 3098 if (Result != ISD::SETCC_INVALID && 3099 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType()))) 3100 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(), 3101 LL, LR, Result); 3102 } 3103 } 3104 3105 // Simplify: (or (op x...), (op y...)) -> (op (or x, y)) 3106 if (N0.getOpcode() == N1.getOpcode()) { 3107 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 3108 if (Tmp.getNode()) return Tmp; 3109 } 3110 3111 // (or (and X, C1), (and Y, C2)) -> (and (or X, Y), C3) if possible. 3112 if (N0.getOpcode() == ISD::AND && 3113 N1.getOpcode() == ISD::AND && 3114 N0.getOperand(1).getOpcode() == ISD::Constant && 3115 N1.getOperand(1).getOpcode() == ISD::Constant && 3116 // Don't increase # computations. 3117 (N0.getNode()->hasOneUse() || N1.getNode()->hasOneUse())) { 3118 // We can only do this xform if we know that bits from X that are set in C2 3119 // but not in C1 are already zero. Likewise for Y. 3120 const APInt &LHSMask = 3121 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 3122 const APInt &RHSMask = 3123 cast<ConstantSDNode>(N1.getOperand(1))->getAPIntValue(); 3124 3125 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) && 3126 DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) { 3127 SDValue X = DAG.getNode(ISD::OR, N0.getDebugLoc(), VT, 3128 N0.getOperand(0), N1.getOperand(0)); 3129 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, X, 3130 DAG.getConstant(LHSMask | RHSMask, VT)); 3131 } 3132 } 3133 3134 // See if this is some rotate idiom. 3135 if (SDNode *Rot = MatchRotate(N0, N1, N->getDebugLoc())) 3136 return SDValue(Rot, 0); 3137 3138 // Simplify the operands using demanded-bits information. 3139 if (!VT.isVector() && 3140 SimplifyDemandedBits(SDValue(N, 0))) 3141 return SDValue(N, 0); 3142 3143 return SDValue(); 3144} 3145 3146/// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present. 3147static bool MatchRotateHalf(SDValue Op, SDValue &Shift, SDValue &Mask) { 3148 if (Op.getOpcode() == ISD::AND) { 3149 if (isa<ConstantSDNode>(Op.getOperand(1))) { 3150 Mask = Op.getOperand(1); 3151 Op = Op.getOperand(0); 3152 } else { 3153 return false; 3154 } 3155 } 3156 3157 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) { 3158 Shift = Op; 3159 return true; 3160 } 3161 3162 return false; 3163} 3164 3165// MatchRotate - Handle an 'or' of two operands. If this is one of the many 3166// idioms for rotate, and if the target supports rotation instructions, generate 3167// a rot[lr]. 3168SDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL) { 3169 // Must be a legal type. Expanded 'n promoted things won't work with rotates. 3170 EVT VT = LHS.getValueType(); 3171 if (!TLI.isTypeLegal(VT)) return 0; 3172 3173 // The target must have at least one rotate flavor. 3174 bool HasROTL = TLI.isOperationLegalOrCustom(ISD::ROTL, VT); 3175 bool HasROTR = TLI.isOperationLegalOrCustom(ISD::ROTR, VT); 3176 if (!HasROTL && !HasROTR) return 0; 3177 3178 // Match "(X shl/srl V1) & V2" where V2 may not be present. 3179 SDValue LHSShift; // The shift. 3180 SDValue LHSMask; // AND value if any. 3181 if (!MatchRotateHalf(LHS, LHSShift, LHSMask)) 3182 return 0; // Not part of a rotate. 3183 3184 SDValue RHSShift; // The shift. 3185 SDValue RHSMask; // AND value if any. 3186 if (!MatchRotateHalf(RHS, RHSShift, RHSMask)) 3187 return 0; // Not part of a rotate. 3188 3189 if (LHSShift.getOperand(0) != RHSShift.getOperand(0)) 3190 return 0; // Not shifting the same value. 3191 3192 if (LHSShift.getOpcode() == RHSShift.getOpcode()) 3193 return 0; // Shifts must disagree. 3194 3195 // Canonicalize shl to left side in a shl/srl pair. 3196 if (RHSShift.getOpcode() == ISD::SHL) { 3197 std::swap(LHS, RHS); 3198 std::swap(LHSShift, RHSShift); 3199 std::swap(LHSMask , RHSMask ); 3200 } 3201 3202 unsigned OpSizeInBits = VT.getSizeInBits(); 3203 SDValue LHSShiftArg = LHSShift.getOperand(0); 3204 SDValue LHSShiftAmt = LHSShift.getOperand(1); 3205 SDValue RHSShiftAmt = RHSShift.getOperand(1); 3206 3207 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1) 3208 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2) 3209 if (LHSShiftAmt.getOpcode() == ISD::Constant && 3210 RHSShiftAmt.getOpcode() == ISD::Constant) { 3211 uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getZExtValue(); 3212 uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getZExtValue(); 3213 if ((LShVal + RShVal) != OpSizeInBits) 3214 return 0; 3215 3216 SDValue Rot; 3217 if (HasROTL) 3218 Rot = DAG.getNode(ISD::ROTL, DL, VT, LHSShiftArg, LHSShiftAmt); 3219 else 3220 Rot = DAG.getNode(ISD::ROTR, DL, VT, LHSShiftArg, RHSShiftAmt); 3221 3222 // If there is an AND of either shifted operand, apply it to the result. 3223 if (LHSMask.getNode() || RHSMask.getNode()) { 3224 APInt Mask = APInt::getAllOnesValue(OpSizeInBits); 3225 3226 if (LHSMask.getNode()) { 3227 APInt RHSBits = APInt::getLowBitsSet(OpSizeInBits, LShVal); 3228 Mask &= cast<ConstantSDNode>(LHSMask)->getAPIntValue() | RHSBits; 3229 } 3230 if (RHSMask.getNode()) { 3231 APInt LHSBits = APInt::getHighBitsSet(OpSizeInBits, RShVal); 3232 Mask &= cast<ConstantSDNode>(RHSMask)->getAPIntValue() | LHSBits; 3233 } 3234 3235 Rot = DAG.getNode(ISD::AND, DL, VT, Rot, DAG.getConstant(Mask, VT)); 3236 } 3237 3238 return Rot.getNode(); 3239 } 3240 3241 // If there is a mask here, and we have a variable shift, we can't be sure 3242 // that we're masking out the right stuff. 3243 if (LHSMask.getNode() || RHSMask.getNode()) 3244 return 0; 3245 3246 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y) 3247 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y)) 3248 if (RHSShiftAmt.getOpcode() == ISD::SUB && 3249 LHSShiftAmt == RHSShiftAmt.getOperand(1)) { 3250 if (ConstantSDNode *SUBC = 3251 dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) { 3252 if (SUBC->getAPIntValue() == OpSizeInBits) { 3253 if (HasROTL) 3254 return DAG.getNode(ISD::ROTL, DL, VT, 3255 LHSShiftArg, LHSShiftAmt).getNode(); 3256 else 3257 return DAG.getNode(ISD::ROTR, DL, VT, 3258 LHSShiftArg, RHSShiftAmt).getNode(); 3259 } 3260 } 3261 } 3262 3263 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y) 3264 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y)) 3265 if (LHSShiftAmt.getOpcode() == ISD::SUB && 3266 RHSShiftAmt == LHSShiftAmt.getOperand(1)) { 3267 if (ConstantSDNode *SUBC = 3268 dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) { 3269 if (SUBC->getAPIntValue() == OpSizeInBits) { 3270 if (HasROTR) 3271 return DAG.getNode(ISD::ROTR, DL, VT, 3272 LHSShiftArg, RHSShiftAmt).getNode(); 3273 else 3274 return DAG.getNode(ISD::ROTL, DL, VT, 3275 LHSShiftArg, LHSShiftAmt).getNode(); 3276 } 3277 } 3278 } 3279 3280 // Look for sign/zext/any-extended or truncate cases: 3281 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 3282 || LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 3283 || LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND 3284 || LHSShiftAmt.getOpcode() == ISD::TRUNCATE) && 3285 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 3286 || RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 3287 || RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND 3288 || RHSShiftAmt.getOpcode() == ISD::TRUNCATE)) { 3289 SDValue LExtOp0 = LHSShiftAmt.getOperand(0); 3290 SDValue RExtOp0 = RHSShiftAmt.getOperand(0); 3291 if (RExtOp0.getOpcode() == ISD::SUB && 3292 RExtOp0.getOperand(1) == LExtOp0) { 3293 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 3294 // (rotl x, y) 3295 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 3296 // (rotr x, (sub 32, y)) 3297 if (ConstantSDNode *SUBC = 3298 dyn_cast<ConstantSDNode>(RExtOp0.getOperand(0))) { 3299 if (SUBC->getAPIntValue() == OpSizeInBits) { 3300 return DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT, 3301 LHSShiftArg, 3302 HasROTL ? LHSShiftAmt : RHSShiftAmt).getNode(); 3303 } 3304 } 3305 } else if (LExtOp0.getOpcode() == ISD::SUB && 3306 RExtOp0 == LExtOp0.getOperand(1)) { 3307 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) -> 3308 // (rotr x, y) 3309 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) -> 3310 // (rotl x, (sub 32, y)) 3311 if (ConstantSDNode *SUBC = 3312 dyn_cast<ConstantSDNode>(LExtOp0.getOperand(0))) { 3313 if (SUBC->getAPIntValue() == OpSizeInBits) { 3314 return DAG.getNode(HasROTR ? ISD::ROTR : ISD::ROTL, DL, VT, 3315 LHSShiftArg, 3316 HasROTR ? RHSShiftAmt : LHSShiftAmt).getNode(); 3317 } 3318 } 3319 } 3320 } 3321 3322 return 0; 3323} 3324 3325SDValue DAGCombiner::visitXOR(SDNode *N) { 3326 SDValue N0 = N->getOperand(0); 3327 SDValue N1 = N->getOperand(1); 3328 SDValue LHS, RHS, CC; 3329 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3330 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3331 EVT VT = N0.getValueType(); 3332 3333 // fold vector ops 3334 if (VT.isVector()) { 3335 SDValue FoldedVOp = SimplifyVBinOp(N); 3336 if (FoldedVOp.getNode()) return FoldedVOp; 3337 } 3338 3339 // fold (xor undef, undef) -> 0. This is a common idiom (misuse). 3340 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF) 3341 return DAG.getConstant(0, VT); 3342 // fold (xor x, undef) -> undef 3343 if (N0.getOpcode() == ISD::UNDEF) 3344 return N0; 3345 if (N1.getOpcode() == ISD::UNDEF) 3346 return N1; 3347 // fold (xor c1, c2) -> c1^c2 3348 if (N0C && N1C) 3349 return DAG.FoldConstantArithmetic(ISD::XOR, VT, N0C, N1C); 3350 // canonicalize constant to RHS 3351 if (N0C && !N1C) 3352 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0); 3353 // fold (xor x, 0) -> x 3354 if (N1C && N1C->isNullValue()) 3355 return N0; 3356 // reassociate xor 3357 SDValue RXOR = ReassociateOps(ISD::XOR, N->getDebugLoc(), N0, N1); 3358 if (RXOR.getNode() != 0) 3359 return RXOR; 3360 3361 // fold !(x cc y) -> (x !cc y) 3362 if (N1C && N1C->getAPIntValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) { 3363 bool isInt = LHS.getValueType().isInteger(); 3364 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(), 3365 isInt); 3366 3367 if (!LegalOperations || TLI.isCondCodeLegal(NotCC, LHS.getValueType())) { 3368 switch (N0.getOpcode()) { 3369 default: 3370 llvm_unreachable("Unhandled SetCC Equivalent!"); 3371 case ISD::SETCC: 3372 return DAG.getSetCC(N->getDebugLoc(), VT, LHS, RHS, NotCC); 3373 case ISD::SELECT_CC: 3374 return DAG.getSelectCC(N->getDebugLoc(), LHS, RHS, N0.getOperand(2), 3375 N0.getOperand(3), NotCC); 3376 } 3377 } 3378 } 3379 3380 // fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y))) 3381 if (N1C && N1C->getAPIntValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND && 3382 N0.getNode()->hasOneUse() && 3383 isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){ 3384 SDValue V = N0.getOperand(0); 3385 V = DAG.getNode(ISD::XOR, N0.getDebugLoc(), V.getValueType(), V, 3386 DAG.getConstant(1, V.getValueType())); 3387 AddToWorkList(V.getNode()); 3388 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, V); 3389 } 3390 3391 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are setcc 3392 if (N1C && N1C->getAPIntValue() == 1 && VT == MVT::i1 && 3393 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 3394 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1); 3395 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) { 3396 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 3397 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS 3398 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS 3399 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode()); 3400 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS); 3401 } 3402 } 3403 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are constants 3404 if (N1C && N1C->isAllOnesValue() && 3405 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 3406 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1); 3407 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) { 3408 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 3409 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS 3410 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS 3411 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode()); 3412 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS); 3413 } 3414 } 3415 // fold (xor (xor x, c1), c2) -> (xor x, (xor c1, c2)) 3416 if (N1C && N0.getOpcode() == ISD::XOR) { 3417 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0)); 3418 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 3419 if (N00C) 3420 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(1), 3421 DAG.getConstant(N1C->getAPIntValue() ^ 3422 N00C->getAPIntValue(), VT)); 3423 if (N01C) 3424 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(0), 3425 DAG.getConstant(N1C->getAPIntValue() ^ 3426 N01C->getAPIntValue(), VT)); 3427 } 3428 // fold (xor x, x) -> 0 3429 if (N0 == N1) 3430 return tryFoldToZero(N->getDebugLoc(), TLI, VT, DAG, LegalOperations); 3431 3432 // Simplify: xor (op x...), (op y...) -> (op (xor x, y)) 3433 if (N0.getOpcode() == N1.getOpcode()) { 3434 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 3435 if (Tmp.getNode()) return Tmp; 3436 } 3437 3438 // Simplify the expression using non-local knowledge. 3439 if (!VT.isVector() && 3440 SimplifyDemandedBits(SDValue(N, 0))) 3441 return SDValue(N, 0); 3442 3443 return SDValue(); 3444} 3445 3446/// visitShiftByConstant - Handle transforms common to the three shifts, when 3447/// the shift amount is a constant. 3448SDValue DAGCombiner::visitShiftByConstant(SDNode *N, unsigned Amt) { 3449 SDNode *LHS = N->getOperand(0).getNode(); 3450 if (!LHS->hasOneUse()) return SDValue(); 3451 3452 // We want to pull some binops through shifts, so that we have (and (shift)) 3453 // instead of (shift (and)), likewise for add, or, xor, etc. This sort of 3454 // thing happens with address calculations, so it's important to canonicalize 3455 // it. 3456 bool HighBitSet = false; // Can we transform this if the high bit is set? 3457 3458 switch (LHS->getOpcode()) { 3459 default: return SDValue(); 3460 case ISD::OR: 3461 case ISD::XOR: 3462 HighBitSet = false; // We can only transform sra if the high bit is clear. 3463 break; 3464 case ISD::AND: 3465 HighBitSet = true; // We can only transform sra if the high bit is set. 3466 break; 3467 case ISD::ADD: 3468 if (N->getOpcode() != ISD::SHL) 3469 return SDValue(); // only shl(add) not sr[al](add). 3470 HighBitSet = false; // We can only transform sra if the high bit is clear. 3471 break; 3472 } 3473 3474 // We require the RHS of the binop to be a constant as well. 3475 ConstantSDNode *BinOpCst = dyn_cast<ConstantSDNode>(LHS->getOperand(1)); 3476 if (!BinOpCst) return SDValue(); 3477 3478 // FIXME: disable this unless the input to the binop is a shift by a constant. 3479 // If it is not a shift, it pessimizes some common cases like: 3480 // 3481 // void foo(int *X, int i) { X[i & 1235] = 1; } 3482 // int bar(int *X, int i) { return X[i & 255]; } 3483 SDNode *BinOpLHSVal = LHS->getOperand(0).getNode(); 3484 if ((BinOpLHSVal->getOpcode() != ISD::SHL && 3485 BinOpLHSVal->getOpcode() != ISD::SRA && 3486 BinOpLHSVal->getOpcode() != ISD::SRL) || 3487 !isa<ConstantSDNode>(BinOpLHSVal->getOperand(1))) 3488 return SDValue(); 3489 3490 EVT VT = N->getValueType(0); 3491 3492 // If this is a signed shift right, and the high bit is modified by the 3493 // logical operation, do not perform the transformation. The highBitSet 3494 // boolean indicates the value of the high bit of the constant which would 3495 // cause it to be modified for this operation. 3496 if (N->getOpcode() == ISD::SRA) { 3497 bool BinOpRHSSignSet = BinOpCst->getAPIntValue().isNegative(); 3498 if (BinOpRHSSignSet != HighBitSet) 3499 return SDValue(); 3500 } 3501 3502 // Fold the constants, shifting the binop RHS by the shift amount. 3503 SDValue NewRHS = DAG.getNode(N->getOpcode(), LHS->getOperand(1).getDebugLoc(), 3504 N->getValueType(0), 3505 LHS->getOperand(1), N->getOperand(1)); 3506 3507 // Create the new shift. 3508 SDValue NewShift = DAG.getNode(N->getOpcode(), 3509 LHS->getOperand(0).getDebugLoc(), 3510 VT, LHS->getOperand(0), N->getOperand(1)); 3511 3512 // Create the new binop. 3513 return DAG.getNode(LHS->getOpcode(), N->getDebugLoc(), VT, NewShift, NewRHS); 3514} 3515 3516SDValue DAGCombiner::visitSHL(SDNode *N) { 3517 SDValue N0 = N->getOperand(0); 3518 SDValue N1 = N->getOperand(1); 3519 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3520 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3521 EVT VT = N0.getValueType(); 3522 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits(); 3523 3524 // fold (shl c1, c2) -> c1<<c2 3525 if (N0C && N1C) 3526 return DAG.FoldConstantArithmetic(ISD::SHL, VT, N0C, N1C); 3527 // fold (shl 0, x) -> 0 3528 if (N0C && N0C->isNullValue()) 3529 return N0; 3530 // fold (shl x, c >= size(x)) -> undef 3531 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 3532 return DAG.getUNDEF(VT); 3533 // fold (shl x, 0) -> x 3534 if (N1C && N1C->isNullValue()) 3535 return N0; 3536 // fold (shl undef, x) -> 0 3537 if (N0.getOpcode() == ISD::UNDEF) 3538 return DAG.getConstant(0, VT); 3539 // if (shl x, c) is known to be zero, return 0 3540 if (DAG.MaskedValueIsZero(SDValue(N, 0), 3541 APInt::getAllOnesValue(OpSizeInBits))) 3542 return DAG.getConstant(0, VT); 3543 // fold (shl x, (trunc (and y, c))) -> (shl x, (and (trunc y), (trunc c))). 3544 if (N1.getOpcode() == ISD::TRUNCATE && 3545 N1.getOperand(0).getOpcode() == ISD::AND && 3546 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 3547 SDValue N101 = N1.getOperand(0).getOperand(1); 3548 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 3549 EVT TruncVT = N1.getValueType(); 3550 SDValue N100 = N1.getOperand(0).getOperand(0); 3551 APInt TruncC = N101C->getAPIntValue(); 3552 TruncC = TruncC.trunc(TruncVT.getSizeInBits()); 3553 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 3554 DAG.getNode(ISD::AND, N->getDebugLoc(), TruncVT, 3555 DAG.getNode(ISD::TRUNCATE, 3556 N->getDebugLoc(), 3557 TruncVT, N100), 3558 DAG.getConstant(TruncC, TruncVT))); 3559 } 3560 } 3561 3562 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 3563 return SDValue(N, 0); 3564 3565 // fold (shl (shl x, c1), c2) -> 0 or (shl x, (add c1, c2)) 3566 if (N1C && N0.getOpcode() == ISD::SHL && 3567 N0.getOperand(1).getOpcode() == ISD::Constant) { 3568 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 3569 uint64_t c2 = N1C->getZExtValue(); 3570 if (c1 + c2 >= OpSizeInBits) 3571 return DAG.getConstant(0, VT); 3572 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0.getOperand(0), 3573 DAG.getConstant(c1 + c2, N1.getValueType())); 3574 } 3575 3576 // fold (shl (ext (shl x, c1)), c2) -> (ext (shl x, (add c1, c2))) 3577 // For this to be valid, the second form must not preserve any of the bits 3578 // that are shifted out by the inner shift in the first form. This means 3579 // the outer shift size must be >= the number of bits added by the ext. 3580 // As a corollary, we don't care what kind of ext it is. 3581 if (N1C && (N0.getOpcode() == ISD::ZERO_EXTEND || 3582 N0.getOpcode() == ISD::ANY_EXTEND || 3583 N0.getOpcode() == ISD::SIGN_EXTEND) && 3584 N0.getOperand(0).getOpcode() == ISD::SHL && 3585 isa<ConstantSDNode>(N0.getOperand(0)->getOperand(1))) { 3586 uint64_t c1 = 3587 cast<ConstantSDNode>(N0.getOperand(0)->getOperand(1))->getZExtValue(); 3588 uint64_t c2 = N1C->getZExtValue(); 3589 EVT InnerShiftVT = N0.getOperand(0).getValueType(); 3590 uint64_t InnerShiftSize = InnerShiftVT.getScalarType().getSizeInBits(); 3591 if (c2 >= OpSizeInBits - InnerShiftSize) { 3592 if (c1 + c2 >= OpSizeInBits) 3593 return DAG.getConstant(0, VT); 3594 return DAG.getNode(ISD::SHL, N0->getDebugLoc(), VT, 3595 DAG.getNode(N0.getOpcode(), N0->getDebugLoc(), VT, 3596 N0.getOperand(0)->getOperand(0)), 3597 DAG.getConstant(c1 + c2, N1.getValueType())); 3598 } 3599 } 3600 3601 // fold (shl (srl x, c1), c2) -> (and (shl x, (sub c2, c1), MASK) or 3602 // (and (srl x, (sub c1, c2), MASK) 3603 // Only fold this if the inner shift has no other uses -- if it does, folding 3604 // this will increase the total number of instructions. 3605 if (N1C && N0.getOpcode() == ISD::SRL && N0.hasOneUse() && 3606 N0.getOperand(1).getOpcode() == ISD::Constant) { 3607 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 3608 if (c1 < VT.getSizeInBits()) { 3609 uint64_t c2 = N1C->getZExtValue(); 3610 APInt Mask = APInt::getHighBitsSet(VT.getSizeInBits(), 3611 VT.getSizeInBits() - c1); 3612 SDValue Shift; 3613 if (c2 > c1) { 3614 Mask = Mask.shl(c2-c1); 3615 Shift = DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0.getOperand(0), 3616 DAG.getConstant(c2-c1, N1.getValueType())); 3617 } else { 3618 Mask = Mask.lshr(c1-c2); 3619 Shift = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), 3620 DAG.getConstant(c1-c2, N1.getValueType())); 3621 } 3622 return DAG.getNode(ISD::AND, N0.getDebugLoc(), VT, Shift, 3623 DAG.getConstant(Mask, VT)); 3624 } 3625 } 3626 // fold (shl (sra x, c1), c1) -> (and x, (shl -1, c1)) 3627 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) { 3628 SDValue HiBitsMask = 3629 DAG.getConstant(APInt::getHighBitsSet(VT.getSizeInBits(), 3630 VT.getSizeInBits() - 3631 N1C->getZExtValue()), 3632 VT); 3633 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0), 3634 HiBitsMask); 3635 } 3636 3637 if (N1C) { 3638 SDValue NewSHL = visitShiftByConstant(N, N1C->getZExtValue()); 3639 if (NewSHL.getNode()) 3640 return NewSHL; 3641 } 3642 3643 return SDValue(); 3644} 3645 3646SDValue DAGCombiner::visitSRA(SDNode *N) { 3647 SDValue N0 = N->getOperand(0); 3648 SDValue N1 = N->getOperand(1); 3649 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3650 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3651 EVT VT = N0.getValueType(); 3652 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits(); 3653 3654 // fold (sra c1, c2) -> (sra c1, c2) 3655 if (N0C && N1C) 3656 return DAG.FoldConstantArithmetic(ISD::SRA, VT, N0C, N1C); 3657 // fold (sra 0, x) -> 0 3658 if (N0C && N0C->isNullValue()) 3659 return N0; 3660 // fold (sra -1, x) -> -1 3661 if (N0C && N0C->isAllOnesValue()) 3662 return N0; 3663 // fold (sra x, (setge c, size(x))) -> undef 3664 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 3665 return DAG.getUNDEF(VT); 3666 // fold (sra x, 0) -> x 3667 if (N1C && N1C->isNullValue()) 3668 return N0; 3669 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports 3670 // sext_inreg. 3671 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) { 3672 unsigned LowBits = OpSizeInBits - (unsigned)N1C->getZExtValue(); 3673 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), LowBits); 3674 if (VT.isVector()) 3675 ExtVT = EVT::getVectorVT(*DAG.getContext(), 3676 ExtVT, VT.getVectorNumElements()); 3677 if ((!LegalOperations || 3678 TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, ExtVT))) 3679 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, 3680 N0.getOperand(0), DAG.getValueType(ExtVT)); 3681 } 3682 3683 // fold (sra (sra x, c1), c2) -> (sra x, (add c1, c2)) 3684 if (N1C && N0.getOpcode() == ISD::SRA) { 3685 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 3686 unsigned Sum = N1C->getZExtValue() + C1->getZExtValue(); 3687 if (Sum >= OpSizeInBits) Sum = OpSizeInBits-1; 3688 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0.getOperand(0), 3689 DAG.getConstant(Sum, N1C->getValueType(0))); 3690 } 3691 } 3692 3693 // fold (sra (shl X, m), (sub result_size, n)) 3694 // -> (sign_extend (trunc (shl X, (sub (sub result_size, n), m)))) for 3695 // result_size - n != m. 3696 // If truncate is free for the target sext(shl) is likely to result in better 3697 // code. 3698 if (N0.getOpcode() == ISD::SHL) { 3699 // Get the two constanst of the shifts, CN0 = m, CN = n. 3700 const ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 3701 if (N01C && N1C) { 3702 // Determine what the truncate's result bitsize and type would be. 3703 EVT TruncVT = 3704 EVT::getIntegerVT(*DAG.getContext(), 3705 OpSizeInBits - N1C->getZExtValue()); 3706 // Determine the residual right-shift amount. 3707 signed ShiftAmt = N1C->getZExtValue() - N01C->getZExtValue(); 3708 3709 // If the shift is not a no-op (in which case this should be just a sign 3710 // extend already), the truncated to type is legal, sign_extend is legal 3711 // on that type, and the truncate to that type is both legal and free, 3712 // perform the transform. 3713 if ((ShiftAmt > 0) && 3714 TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND, TruncVT) && 3715 TLI.isOperationLegalOrCustom(ISD::TRUNCATE, VT) && 3716 TLI.isTruncateFree(VT, TruncVT)) { 3717 3718 SDValue Amt = DAG.getConstant(ShiftAmt, 3719 getShiftAmountTy(N0.getOperand(0).getValueType())); 3720 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, 3721 N0.getOperand(0), Amt); 3722 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), TruncVT, 3723 Shift); 3724 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), 3725 N->getValueType(0), Trunc); 3726 } 3727 } 3728 } 3729 3730 // fold (sra x, (trunc (and y, c))) -> (sra x, (and (trunc y), (trunc c))). 3731 if (N1.getOpcode() == ISD::TRUNCATE && 3732 N1.getOperand(0).getOpcode() == ISD::AND && 3733 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 3734 SDValue N101 = N1.getOperand(0).getOperand(1); 3735 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 3736 EVT TruncVT = N1.getValueType(); 3737 SDValue N100 = N1.getOperand(0).getOperand(0); 3738 APInt TruncC = N101C->getAPIntValue(); 3739 TruncC = TruncC.trunc(TruncVT.getScalarType().getSizeInBits()); 3740 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0, 3741 DAG.getNode(ISD::AND, N->getDebugLoc(), 3742 TruncVT, 3743 DAG.getNode(ISD::TRUNCATE, 3744 N->getDebugLoc(), 3745 TruncVT, N100), 3746 DAG.getConstant(TruncC, TruncVT))); 3747 } 3748 } 3749 3750 // fold (sra (trunc (sr x, c1)), c2) -> (trunc (sra x, c1+c2)) 3751 // if c1 is equal to the number of bits the trunc removes 3752 if (N0.getOpcode() == ISD::TRUNCATE && 3753 (N0.getOperand(0).getOpcode() == ISD::SRL || 3754 N0.getOperand(0).getOpcode() == ISD::SRA) && 3755 N0.getOperand(0).hasOneUse() && 3756 N0.getOperand(0).getOperand(1).hasOneUse() && 3757 N1C && isa<ConstantSDNode>(N0.getOperand(0).getOperand(1))) { 3758 EVT LargeVT = N0.getOperand(0).getValueType(); 3759 ConstantSDNode *LargeShiftAmt = 3760 cast<ConstantSDNode>(N0.getOperand(0).getOperand(1)); 3761 3762 if (LargeVT.getScalarType().getSizeInBits() - OpSizeInBits == 3763 LargeShiftAmt->getZExtValue()) { 3764 SDValue Amt = 3765 DAG.getConstant(LargeShiftAmt->getZExtValue() + N1C->getZExtValue(), 3766 getShiftAmountTy(N0.getOperand(0).getOperand(0).getValueType())); 3767 SDValue SRA = DAG.getNode(ISD::SRA, N->getDebugLoc(), LargeVT, 3768 N0.getOperand(0).getOperand(0), Amt); 3769 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, SRA); 3770 } 3771 } 3772 3773 // Simplify, based on bits shifted out of the LHS. 3774 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 3775 return SDValue(N, 0); 3776 3777 3778 // If the sign bit is known to be zero, switch this to a SRL. 3779 if (DAG.SignBitIsZero(N0)) 3780 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, N1); 3781 3782 if (N1C) { 3783 SDValue NewSRA = visitShiftByConstant(N, N1C->getZExtValue()); 3784 if (NewSRA.getNode()) 3785 return NewSRA; 3786 } 3787 3788 return SDValue(); 3789} 3790 3791SDValue DAGCombiner::visitSRL(SDNode *N) { 3792 SDValue N0 = N->getOperand(0); 3793 SDValue N1 = N->getOperand(1); 3794 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3795 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3796 EVT VT = N0.getValueType(); 3797 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits(); 3798 3799 // fold (srl c1, c2) -> c1 >>u c2 3800 if (N0C && N1C) 3801 return DAG.FoldConstantArithmetic(ISD::SRL, VT, N0C, N1C); 3802 // fold (srl 0, x) -> 0 3803 if (N0C && N0C->isNullValue()) 3804 return N0; 3805 // fold (srl x, c >= size(x)) -> undef 3806 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 3807 return DAG.getUNDEF(VT); 3808 // fold (srl x, 0) -> x 3809 if (N1C && N1C->isNullValue()) 3810 return N0; 3811 // if (srl x, c) is known to be zero, return 0 3812 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0), 3813 APInt::getAllOnesValue(OpSizeInBits))) 3814 return DAG.getConstant(0, VT); 3815 3816 // fold (srl (srl x, c1), c2) -> 0 or (srl x, (add c1, c2)) 3817 if (N1C && N0.getOpcode() == ISD::SRL && 3818 N0.getOperand(1).getOpcode() == ISD::Constant) { 3819 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 3820 uint64_t c2 = N1C->getZExtValue(); 3821 if (c1 + c2 >= OpSizeInBits) 3822 return DAG.getConstant(0, VT); 3823 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), 3824 DAG.getConstant(c1 + c2, N1.getValueType())); 3825 } 3826 3827 // fold (srl (trunc (srl x, c1)), c2) -> 0 or (trunc (srl x, (add c1, c2))) 3828 if (N1C && N0.getOpcode() == ISD::TRUNCATE && 3829 N0.getOperand(0).getOpcode() == ISD::SRL && 3830 isa<ConstantSDNode>(N0.getOperand(0)->getOperand(1))) { 3831 uint64_t c1 = 3832 cast<ConstantSDNode>(N0.getOperand(0)->getOperand(1))->getZExtValue(); 3833 uint64_t c2 = N1C->getZExtValue(); 3834 EVT InnerShiftVT = N0.getOperand(0).getValueType(); 3835 EVT ShiftCountVT = N0.getOperand(0)->getOperand(1).getValueType(); 3836 uint64_t InnerShiftSize = InnerShiftVT.getScalarType().getSizeInBits(); 3837 // This is only valid if the OpSizeInBits + c1 = size of inner shift. 3838 if (c1 + OpSizeInBits == InnerShiftSize) { 3839 if (c1 + c2 >= InnerShiftSize) 3840 return DAG.getConstant(0, VT); 3841 return DAG.getNode(ISD::TRUNCATE, N0->getDebugLoc(), VT, 3842 DAG.getNode(ISD::SRL, N0->getDebugLoc(), InnerShiftVT, 3843 N0.getOperand(0)->getOperand(0), 3844 DAG.getConstant(c1 + c2, ShiftCountVT))); 3845 } 3846 } 3847 3848 // fold (srl (shl x, c), c) -> (and x, cst2) 3849 if (N1C && N0.getOpcode() == ISD::SHL && N0.getOperand(1) == N1 && 3850 N0.getValueSizeInBits() <= 64) { 3851 uint64_t ShAmt = N1C->getZExtValue()+64-N0.getValueSizeInBits(); 3852 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0), 3853 DAG.getConstant(~0ULL >> ShAmt, VT)); 3854 } 3855 3856 3857 // fold (srl (anyextend x), c) -> (anyextend (srl x, c)) 3858 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 3859 // Shifting in all undef bits? 3860 EVT SmallVT = N0.getOperand(0).getValueType(); 3861 if (N1C->getZExtValue() >= SmallVT.getSizeInBits()) 3862 return DAG.getUNDEF(VT); 3863 3864 if (!LegalTypes || TLI.isTypeDesirableForOp(ISD::SRL, SmallVT)) { 3865 uint64_t ShiftAmt = N1C->getZExtValue(); 3866 SDValue SmallShift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), SmallVT, 3867 N0.getOperand(0), 3868 DAG.getConstant(ShiftAmt, getShiftAmountTy(SmallVT))); 3869 AddToWorkList(SmallShift.getNode()); 3870 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, SmallShift); 3871 } 3872 } 3873 3874 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign 3875 // bit, which is unmodified by sra. 3876 if (N1C && N1C->getZExtValue() + 1 == VT.getSizeInBits()) { 3877 if (N0.getOpcode() == ISD::SRA) 3878 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), N1); 3879 } 3880 3881 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit). 3882 if (N1C && N0.getOpcode() == ISD::CTLZ && 3883 N1C->getAPIntValue() == Log2_32(VT.getSizeInBits())) { 3884 APInt KnownZero, KnownOne; 3885 DAG.ComputeMaskedBits(N0.getOperand(0), KnownZero, KnownOne); 3886 3887 // If any of the input bits are KnownOne, then the input couldn't be all 3888 // zeros, thus the result of the srl will always be zero. 3889 if (KnownOne.getBoolValue()) return DAG.getConstant(0, VT); 3890 3891 // If all of the bits input the to ctlz node are known to be zero, then 3892 // the result of the ctlz is "32" and the result of the shift is one. 3893 APInt UnknownBits = ~KnownZero; 3894 if (UnknownBits == 0) return DAG.getConstant(1, VT); 3895 3896 // Otherwise, check to see if there is exactly one bit input to the ctlz. 3897 if ((UnknownBits & (UnknownBits - 1)) == 0) { 3898 // Okay, we know that only that the single bit specified by UnknownBits 3899 // could be set on input to the CTLZ node. If this bit is set, the SRL 3900 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair 3901 // to an SRL/XOR pair, which is likely to simplify more. 3902 unsigned ShAmt = UnknownBits.countTrailingZeros(); 3903 SDValue Op = N0.getOperand(0); 3904 3905 if (ShAmt) { 3906 Op = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, Op, 3907 DAG.getConstant(ShAmt, getShiftAmountTy(Op.getValueType()))); 3908 AddToWorkList(Op.getNode()); 3909 } 3910 3911 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, 3912 Op, DAG.getConstant(1, VT)); 3913 } 3914 } 3915 3916 // fold (srl x, (trunc (and y, c))) -> (srl x, (and (trunc y), (trunc c))). 3917 if (N1.getOpcode() == ISD::TRUNCATE && 3918 N1.getOperand(0).getOpcode() == ISD::AND && 3919 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 3920 SDValue N101 = N1.getOperand(0).getOperand(1); 3921 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 3922 EVT TruncVT = N1.getValueType(); 3923 SDValue N100 = N1.getOperand(0).getOperand(0); 3924 APInt TruncC = N101C->getAPIntValue(); 3925 TruncC = TruncC.trunc(TruncVT.getSizeInBits()); 3926 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, 3927 DAG.getNode(ISD::AND, N->getDebugLoc(), 3928 TruncVT, 3929 DAG.getNode(ISD::TRUNCATE, 3930 N->getDebugLoc(), 3931 TruncVT, N100), 3932 DAG.getConstant(TruncC, TruncVT))); 3933 } 3934 } 3935 3936 // fold operands of srl based on knowledge that the low bits are not 3937 // demanded. 3938 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 3939 return SDValue(N, 0); 3940 3941 if (N1C) { 3942 SDValue NewSRL = visitShiftByConstant(N, N1C->getZExtValue()); 3943 if (NewSRL.getNode()) 3944 return NewSRL; 3945 } 3946 3947 // Attempt to convert a srl of a load into a narrower zero-extending load. 3948 SDValue NarrowLoad = ReduceLoadWidth(N); 3949 if (NarrowLoad.getNode()) 3950 return NarrowLoad; 3951 3952 // Here is a common situation. We want to optimize: 3953 // 3954 // %a = ... 3955 // %b = and i32 %a, 2 3956 // %c = srl i32 %b, 1 3957 // brcond i32 %c ... 3958 // 3959 // into 3960 // 3961 // %a = ... 3962 // %b = and %a, 2 3963 // %c = setcc eq %b, 0 3964 // brcond %c ... 3965 // 3966 // However when after the source operand of SRL is optimized into AND, the SRL 3967 // itself may not be optimized further. Look for it and add the BRCOND into 3968 // the worklist. 3969 if (N->hasOneUse()) { 3970 SDNode *Use = *N->use_begin(); 3971 if (Use->getOpcode() == ISD::BRCOND) 3972 AddToWorkList(Use); 3973 else if (Use->getOpcode() == ISD::TRUNCATE && Use->hasOneUse()) { 3974 // Also look pass the truncate. 3975 Use = *Use->use_begin(); 3976 if (Use->getOpcode() == ISD::BRCOND) 3977 AddToWorkList(Use); 3978 } 3979 } 3980 3981 return SDValue(); 3982} 3983 3984SDValue DAGCombiner::visitCTLZ(SDNode *N) { 3985 SDValue N0 = N->getOperand(0); 3986 EVT VT = N->getValueType(0); 3987 3988 // fold (ctlz c1) -> c2 3989 if (isa<ConstantSDNode>(N0)) 3990 return DAG.getNode(ISD::CTLZ, N->getDebugLoc(), VT, N0); 3991 return SDValue(); 3992} 3993 3994SDValue DAGCombiner::visitCTLZ_ZERO_UNDEF(SDNode *N) { 3995 SDValue N0 = N->getOperand(0); 3996 EVT VT = N->getValueType(0); 3997 3998 // fold (ctlz_zero_undef c1) -> c2 3999 if (isa<ConstantSDNode>(N0)) 4000 return DAG.getNode(ISD::CTLZ_ZERO_UNDEF, N->getDebugLoc(), VT, N0); 4001 return SDValue(); 4002} 4003 4004SDValue DAGCombiner::visitCTTZ(SDNode *N) { 4005 SDValue N0 = N->getOperand(0); 4006 EVT VT = N->getValueType(0); 4007 4008 // fold (cttz c1) -> c2 4009 if (isa<ConstantSDNode>(N0)) 4010 return DAG.getNode(ISD::CTTZ, N->getDebugLoc(), VT, N0); 4011 return SDValue(); 4012} 4013 4014SDValue DAGCombiner::visitCTTZ_ZERO_UNDEF(SDNode *N) { 4015 SDValue N0 = N->getOperand(0); 4016 EVT VT = N->getValueType(0); 4017 4018 // fold (cttz_zero_undef c1) -> c2 4019 if (isa<ConstantSDNode>(N0)) 4020 return DAG.getNode(ISD::CTTZ_ZERO_UNDEF, N->getDebugLoc(), VT, N0); 4021 return SDValue(); 4022} 4023 4024SDValue DAGCombiner::visitCTPOP(SDNode *N) { 4025 SDValue N0 = N->getOperand(0); 4026 EVT VT = N->getValueType(0); 4027 4028 // fold (ctpop c1) -> c2 4029 if (isa<ConstantSDNode>(N0)) 4030 return DAG.getNode(ISD::CTPOP, N->getDebugLoc(), VT, N0); 4031 return SDValue(); 4032} 4033 4034SDValue DAGCombiner::visitSELECT(SDNode *N) { 4035 SDValue N0 = N->getOperand(0); 4036 SDValue N1 = N->getOperand(1); 4037 SDValue N2 = N->getOperand(2); 4038 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 4039 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 4040 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2); 4041 EVT VT = N->getValueType(0); 4042 EVT VT0 = N0.getValueType(); 4043 4044 // fold (select C, X, X) -> X 4045 if (N1 == N2) 4046 return N1; 4047 // fold (select true, X, Y) -> X 4048 if (N0C && !N0C->isNullValue()) 4049 return N1; 4050 // fold (select false, X, Y) -> Y 4051 if (N0C && N0C->isNullValue()) 4052 return N2; 4053 // fold (select C, 1, X) -> (or C, X) 4054 if (VT == MVT::i1 && N1C && N1C->getAPIntValue() == 1) 4055 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2); 4056 // fold (select C, 0, 1) -> (xor C, 1) 4057 if (VT.isInteger() && 4058 (VT0 == MVT::i1 || 4059 (VT0.isInteger() && 4060 TLI.getBooleanContents(false) == TargetLowering::ZeroOrOneBooleanContent)) && 4061 N1C && N2C && N1C->isNullValue() && N2C->getAPIntValue() == 1) { 4062 SDValue XORNode; 4063 if (VT == VT0) 4064 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT0, 4065 N0, DAG.getConstant(1, VT0)); 4066 XORNode = DAG.getNode(ISD::XOR, N0.getDebugLoc(), VT0, 4067 N0, DAG.getConstant(1, VT0)); 4068 AddToWorkList(XORNode.getNode()); 4069 if (VT.bitsGT(VT0)) 4070 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, XORNode); 4071 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, XORNode); 4072 } 4073 // fold (select C, 0, X) -> (and (not C), X) 4074 if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) { 4075 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT); 4076 AddToWorkList(NOTNode.getNode()); 4077 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, NOTNode, N2); 4078 } 4079 // fold (select C, X, 1) -> (or (not C), X) 4080 if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getAPIntValue() == 1) { 4081 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT); 4082 AddToWorkList(NOTNode.getNode()); 4083 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, NOTNode, N1); 4084 } 4085 // fold (select C, X, 0) -> (and C, X) 4086 if (VT == MVT::i1 && N2C && N2C->isNullValue()) 4087 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1); 4088 // fold (select X, X, Y) -> (or X, Y) 4089 // fold (select X, 1, Y) -> (or X, Y) 4090 if (VT == MVT::i1 && (N0 == N1 || (N1C && N1C->getAPIntValue() == 1))) 4091 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2); 4092 // fold (select X, Y, X) -> (and X, Y) 4093 // fold (select X, Y, 0) -> (and X, Y) 4094 if (VT == MVT::i1 && (N0 == N2 || (N2C && N2C->getAPIntValue() == 0))) 4095 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1); 4096 4097 // If we can fold this based on the true/false value, do so. 4098 if (SimplifySelectOps(N, N1, N2)) 4099 return SDValue(N, 0); // Don't revisit N. 4100 4101 // fold selects based on a setcc into other things, such as min/max/abs 4102 if (N0.getOpcode() == ISD::SETCC) { 4103 // FIXME: 4104 // Check against MVT::Other for SELECT_CC, which is a workaround for targets 4105 // having to say they don't support SELECT_CC on every type the DAG knows 4106 // about, since there is no way to mark an opcode illegal at all value types 4107 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other) && 4108 TLI.isOperationLegalOrCustom(ISD::SELECT_CC, VT)) 4109 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT, 4110 N0.getOperand(0), N0.getOperand(1), 4111 N1, N2, N0.getOperand(2)); 4112 return SimplifySelect(N->getDebugLoc(), N0, N1, N2); 4113 } 4114 4115 return SDValue(); 4116} 4117 4118SDValue DAGCombiner::visitSELECT_CC(SDNode *N) { 4119 SDValue N0 = N->getOperand(0); 4120 SDValue N1 = N->getOperand(1); 4121 SDValue N2 = N->getOperand(2); 4122 SDValue N3 = N->getOperand(3); 4123 SDValue N4 = N->getOperand(4); 4124 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get(); 4125 4126 // fold select_cc lhs, rhs, x, x, cc -> x 4127 if (N2 == N3) 4128 return N2; 4129 4130 // Determine if the condition we're dealing with is constant 4131 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()), 4132 N0, N1, CC, N->getDebugLoc(), false); 4133 if (SCC.getNode()) AddToWorkList(SCC.getNode()); 4134 4135 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode())) { 4136 if (!SCCC->isNullValue()) 4137 return N2; // cond always true -> true val 4138 else 4139 return N3; // cond always false -> false val 4140 } 4141 4142 // Fold to a simpler select_cc 4143 if (SCC.getNode() && SCC.getOpcode() == ISD::SETCC) 4144 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), N2.getValueType(), 4145 SCC.getOperand(0), SCC.getOperand(1), N2, N3, 4146 SCC.getOperand(2)); 4147 4148 // If we can fold this based on the true/false value, do so. 4149 if (SimplifySelectOps(N, N2, N3)) 4150 return SDValue(N, 0); // Don't revisit N. 4151 4152 // fold select_cc into other things, such as min/max/abs 4153 return SimplifySelectCC(N->getDebugLoc(), N0, N1, N2, N3, CC); 4154} 4155 4156SDValue DAGCombiner::visitSETCC(SDNode *N) { 4157 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1), 4158 cast<CondCodeSDNode>(N->getOperand(2))->get(), 4159 N->getDebugLoc()); 4160} 4161 4162// ExtendUsesToFormExtLoad - Trying to extend uses of a load to enable this: 4163// "fold ({s|z|a}ext (load x)) -> ({s|z|a}ext (truncate ({s|z|a}extload x)))" 4164// transformation. Returns true if extension are possible and the above 4165// mentioned transformation is profitable. 4166static bool ExtendUsesToFormExtLoad(SDNode *N, SDValue N0, 4167 unsigned ExtOpc, 4168 SmallVector<SDNode*, 4> &ExtendNodes, 4169 const TargetLowering &TLI) { 4170 bool HasCopyToRegUses = false; 4171 bool isTruncFree = TLI.isTruncateFree(N->getValueType(0), N0.getValueType()); 4172 for (SDNode::use_iterator UI = N0.getNode()->use_begin(), 4173 UE = N0.getNode()->use_end(); 4174 UI != UE; ++UI) { 4175 SDNode *User = *UI; 4176 if (User == N) 4177 continue; 4178 if (UI.getUse().getResNo() != N0.getResNo()) 4179 continue; 4180 // FIXME: Only extend SETCC N, N and SETCC N, c for now. 4181 if (ExtOpc != ISD::ANY_EXTEND && User->getOpcode() == ISD::SETCC) { 4182 ISD::CondCode CC = cast<CondCodeSDNode>(User->getOperand(2))->get(); 4183 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC)) 4184 // Sign bits will be lost after a zext. 4185 return false; 4186 bool Add = false; 4187 for (unsigned i = 0; i != 2; ++i) { 4188 SDValue UseOp = User->getOperand(i); 4189 if (UseOp == N0) 4190 continue; 4191 if (!isa<ConstantSDNode>(UseOp)) 4192 return false; 4193 Add = true; 4194 } 4195 if (Add) 4196 ExtendNodes.push_back(User); 4197 continue; 4198 } 4199 // If truncates aren't free and there are users we can't 4200 // extend, it isn't worthwhile. 4201 if (!isTruncFree) 4202 return false; 4203 // Remember if this value is live-out. 4204 if (User->getOpcode() == ISD::CopyToReg) 4205 HasCopyToRegUses = true; 4206 } 4207 4208 if (HasCopyToRegUses) { 4209 bool BothLiveOut = false; 4210 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 4211 UI != UE; ++UI) { 4212 SDUse &Use = UI.getUse(); 4213 if (Use.getResNo() == 0 && Use.getUser()->getOpcode() == ISD::CopyToReg) { 4214 BothLiveOut = true; 4215 break; 4216 } 4217 } 4218 if (BothLiveOut) 4219 // Both unextended and extended values are live out. There had better be 4220 // a good reason for the transformation. 4221 return ExtendNodes.size(); 4222 } 4223 return true; 4224} 4225 4226void DAGCombiner::ExtendSetCCUses(SmallVector<SDNode*, 4> SetCCs, 4227 SDValue Trunc, SDValue ExtLoad, DebugLoc DL, 4228 ISD::NodeType ExtType) { 4229 // Extend SetCC uses if necessary. 4230 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 4231 SDNode *SetCC = SetCCs[i]; 4232 SmallVector<SDValue, 4> Ops; 4233 4234 for (unsigned j = 0; j != 2; ++j) { 4235 SDValue SOp = SetCC->getOperand(j); 4236 if (SOp == Trunc) 4237 Ops.push_back(ExtLoad); 4238 else 4239 Ops.push_back(DAG.getNode(ExtType, DL, ExtLoad->getValueType(0), SOp)); 4240 } 4241 4242 Ops.push_back(SetCC->getOperand(2)); 4243 CombineTo(SetCC, DAG.getNode(ISD::SETCC, DL, SetCC->getValueType(0), 4244 &Ops[0], Ops.size())); 4245 } 4246} 4247 4248SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) { 4249 SDValue N0 = N->getOperand(0); 4250 EVT VT = N->getValueType(0); 4251 4252 // fold (sext c1) -> c1 4253 if (isa<ConstantSDNode>(N0)) 4254 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N0); 4255 4256 // fold (sext (sext x)) -> (sext x) 4257 // fold (sext (aext x)) -> (sext x) 4258 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 4259 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, 4260 N0.getOperand(0)); 4261 4262 if (N0.getOpcode() == ISD::TRUNCATE) { 4263 // fold (sext (truncate (load x))) -> (sext (smaller load x)) 4264 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n))) 4265 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 4266 if (NarrowLoad.getNode()) { 4267 SDNode* oye = N0.getNode()->getOperand(0).getNode(); 4268 if (NarrowLoad.getNode() != N0.getNode()) { 4269 CombineTo(N0.getNode(), NarrowLoad); 4270 // CombineTo deleted the truncate, if needed, but not what's under it. 4271 AddToWorkList(oye); 4272 } 4273 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4274 } 4275 4276 // See if the value being truncated is already sign extended. If so, just 4277 // eliminate the trunc/sext pair. 4278 SDValue Op = N0.getOperand(0); 4279 unsigned OpBits = Op.getValueType().getScalarType().getSizeInBits(); 4280 unsigned MidBits = N0.getValueType().getScalarType().getSizeInBits(); 4281 unsigned DestBits = VT.getScalarType().getSizeInBits(); 4282 unsigned NumSignBits = DAG.ComputeNumSignBits(Op); 4283 4284 if (OpBits == DestBits) { 4285 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign 4286 // bits, it is already ready. 4287 if (NumSignBits > DestBits-MidBits) 4288 return Op; 4289 } else if (OpBits < DestBits) { 4290 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign 4291 // bits, just sext from i32. 4292 if (NumSignBits > OpBits-MidBits) 4293 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, Op); 4294 } else { 4295 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign 4296 // bits, just truncate to i32. 4297 if (NumSignBits > OpBits-MidBits) 4298 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op); 4299 } 4300 4301 // fold (sext (truncate x)) -> (sextinreg x). 4302 if (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, 4303 N0.getValueType())) { 4304 if (OpBits < DestBits) 4305 Op = DAG.getNode(ISD::ANY_EXTEND, N0.getDebugLoc(), VT, Op); 4306 else if (OpBits > DestBits) 4307 Op = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), VT, Op); 4308 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, Op, 4309 DAG.getValueType(N0.getValueType())); 4310 } 4311 } 4312 4313 // fold (sext (load x)) -> (sext (truncate (sextload x))) 4314 // None of the supported targets knows how to perform load and sign extend 4315 // on vectors in one instruction. We only perform this transformation on 4316 // scalars. 4317 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() && 4318 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 4319 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()))) { 4320 bool DoXform = true; 4321 SmallVector<SDNode*, 4> SetCCs; 4322 if (!N0.hasOneUse()) 4323 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::SIGN_EXTEND, SetCCs, TLI); 4324 if (DoXform) { 4325 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4326 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 4327 LN0->getChain(), 4328 LN0->getBasePtr(), LN0->getPointerInfo(), 4329 N0.getValueType(), 4330 LN0->isVolatile(), LN0->isNonTemporal(), 4331 LN0->getAlignment()); 4332 CombineTo(N, ExtLoad); 4333 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 4334 N0.getValueType(), ExtLoad); 4335 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 4336 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(), 4337 ISD::SIGN_EXTEND); 4338 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4339 } 4340 } 4341 4342 // fold (sext (sextload x)) -> (sext (truncate (sextload x))) 4343 // fold (sext ( extload x)) -> (sext (truncate (sextload x))) 4344 if ((ISD::isSEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) && 4345 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) { 4346 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4347 EVT MemVT = LN0->getMemoryVT(); 4348 if ((!LegalOperations && !LN0->isVolatile()) || 4349 TLI.isLoadExtLegal(ISD::SEXTLOAD, MemVT)) { 4350 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 4351 LN0->getChain(), 4352 LN0->getBasePtr(), LN0->getPointerInfo(), 4353 MemVT, 4354 LN0->isVolatile(), LN0->isNonTemporal(), 4355 LN0->getAlignment()); 4356 CombineTo(N, ExtLoad); 4357 CombineTo(N0.getNode(), 4358 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 4359 N0.getValueType(), ExtLoad), 4360 ExtLoad.getValue(1)); 4361 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4362 } 4363 } 4364 4365 // fold (sext (and/or/xor (load x), cst)) -> 4366 // (and/or/xor (sextload x), (sext cst)) 4367 if ((N0.getOpcode() == ISD::AND || N0.getOpcode() == ISD::OR || 4368 N0.getOpcode() == ISD::XOR) && 4369 isa<LoadSDNode>(N0.getOperand(0)) && 4370 N0.getOperand(1).getOpcode() == ISD::Constant && 4371 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()) && 4372 (!LegalOperations && TLI.isOperationLegal(N0.getOpcode(), VT))) { 4373 LoadSDNode *LN0 = cast<LoadSDNode>(N0.getOperand(0)); 4374 if (LN0->getExtensionType() != ISD::ZEXTLOAD) { 4375 bool DoXform = true; 4376 SmallVector<SDNode*, 4> SetCCs; 4377 if (!N0.hasOneUse()) 4378 DoXform = ExtendUsesToFormExtLoad(N, N0.getOperand(0), ISD::SIGN_EXTEND, 4379 SetCCs, TLI); 4380 if (DoXform) { 4381 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, LN0->getDebugLoc(), VT, 4382 LN0->getChain(), LN0->getBasePtr(), 4383 LN0->getPointerInfo(), 4384 LN0->getMemoryVT(), 4385 LN0->isVolatile(), 4386 LN0->isNonTemporal(), 4387 LN0->getAlignment()); 4388 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 4389 Mask = Mask.sext(VT.getSizeInBits()); 4390 SDValue And = DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, 4391 ExtLoad, DAG.getConstant(Mask, VT)); 4392 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, 4393 N0.getOperand(0).getDebugLoc(), 4394 N0.getOperand(0).getValueType(), ExtLoad); 4395 CombineTo(N, And); 4396 CombineTo(N0.getOperand(0).getNode(), Trunc, ExtLoad.getValue(1)); 4397 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(), 4398 ISD::SIGN_EXTEND); 4399 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4400 } 4401 } 4402 } 4403 4404 if (N0.getOpcode() == ISD::SETCC) { 4405 // sext(setcc) -> sext_in_reg(vsetcc) for vectors. 4406 // Only do this before legalize for now. 4407 if (VT.isVector() && !LegalOperations) { 4408 EVT N0VT = N0.getOperand(0).getValueType(); 4409 // On some architectures (such as SSE/NEON/etc) the SETCC result type is 4410 // of the same size as the compared operands. Only optimize sext(setcc()) 4411 // if this is the case. 4412 EVT SVT = TLI.getSetCCResultType(N0VT); 4413 4414 // We know that the # elements of the results is the same as the 4415 // # elements of the compare (and the # elements of the compare result 4416 // for that matter). Check to see that they are the same size. If so, 4417 // we know that the element size of the sext'd result matches the 4418 // element size of the compare operands. 4419 if (VT.getSizeInBits() == SVT.getSizeInBits()) 4420 return DAG.getSetCC(N->getDebugLoc(), VT, N0.getOperand(0), 4421 N0.getOperand(1), 4422 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 4423 // If the desired elements are smaller or larger than the source 4424 // elements we can use a matching integer vector type and then 4425 // truncate/sign extend 4426 else { 4427 EVT MatchingElementType = 4428 EVT::getIntegerVT(*DAG.getContext(), 4429 N0VT.getScalarType().getSizeInBits()); 4430 EVT MatchingVectorType = 4431 EVT::getVectorVT(*DAG.getContext(), MatchingElementType, 4432 N0VT.getVectorNumElements()); 4433 4434 if (SVT == MatchingVectorType) { 4435 SDValue VsetCC = DAG.getSetCC(N->getDebugLoc(), MatchingVectorType, 4436 N0.getOperand(0), N0.getOperand(1), 4437 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 4438 return DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT); 4439 } 4440 } 4441 } 4442 4443 // sext(setcc x, y, cc) -> (select_cc x, y, -1, 0, cc) 4444 unsigned ElementWidth = VT.getScalarType().getSizeInBits(); 4445 SDValue NegOne = 4446 DAG.getConstant(APInt::getAllOnesValue(ElementWidth), VT); 4447 SDValue SCC = 4448 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 4449 NegOne, DAG.getConstant(0, VT), 4450 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 4451 if (SCC.getNode()) return SCC; 4452 if (!LegalOperations || 4453 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(VT))) 4454 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT, 4455 DAG.getSetCC(N->getDebugLoc(), 4456 TLI.getSetCCResultType(VT), 4457 N0.getOperand(0), N0.getOperand(1), 4458 cast<CondCodeSDNode>(N0.getOperand(2))->get()), 4459 NegOne, DAG.getConstant(0, VT)); 4460 } 4461 4462 // fold (sext x) -> (zext x) if the sign bit is known zero. 4463 if ((!LegalOperations || TLI.isOperationLegal(ISD::ZERO_EXTEND, VT)) && 4464 DAG.SignBitIsZero(N0)) 4465 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0); 4466 4467 return SDValue(); 4468} 4469 4470// isTruncateOf - If N is a truncate of some other value, return true, record 4471// the value being truncated in Op and which of Op's bits are zero in KnownZero. 4472// This function computes KnownZero to avoid a duplicated call to 4473// ComputeMaskedBits in the caller. 4474static bool isTruncateOf(SelectionDAG &DAG, SDValue N, SDValue &Op, 4475 APInt &KnownZero) { 4476 APInt KnownOne; 4477 if (N->getOpcode() == ISD::TRUNCATE) { 4478 Op = N->getOperand(0); 4479 DAG.ComputeMaskedBits(Op, KnownZero, KnownOne); 4480 return true; 4481 } 4482 4483 if (N->getOpcode() != ISD::SETCC || N->getValueType(0) != MVT::i1 || 4484 cast<CondCodeSDNode>(N->getOperand(2))->get() != ISD::SETNE) 4485 return false; 4486 4487 SDValue Op0 = N->getOperand(0); 4488 SDValue Op1 = N->getOperand(1); 4489 assert(Op0.getValueType() == Op1.getValueType()); 4490 4491 ConstantSDNode *COp0 = dyn_cast<ConstantSDNode>(Op0); 4492 ConstantSDNode *COp1 = dyn_cast<ConstantSDNode>(Op1); 4493 if (COp0 && COp0->isNullValue()) 4494 Op = Op1; 4495 else if (COp1 && COp1->isNullValue()) 4496 Op = Op0; 4497 else 4498 return false; 4499 4500 DAG.ComputeMaskedBits(Op, KnownZero, KnownOne); 4501 4502 if (!(KnownZero | APInt(Op.getValueSizeInBits(), 1)).isAllOnesValue()) 4503 return false; 4504 4505 return true; 4506} 4507 4508SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) { 4509 SDValue N0 = N->getOperand(0); 4510 EVT VT = N->getValueType(0); 4511 4512 // fold (zext c1) -> c1 4513 if (isa<ConstantSDNode>(N0)) 4514 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0); 4515 // fold (zext (zext x)) -> (zext x) 4516 // fold (zext (aext x)) -> (zext x) 4517 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 4518 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, 4519 N0.getOperand(0)); 4520 4521 // fold (zext (truncate x)) -> (zext x) or 4522 // (zext (truncate x)) -> (truncate x) 4523 // This is valid when the truncated bits of x are already zero. 4524 // FIXME: We should extend this to work for vectors too. 4525 SDValue Op; 4526 APInt KnownZero; 4527 if (!VT.isVector() && isTruncateOf(DAG, N0, Op, KnownZero)) { 4528 APInt TruncatedBits = 4529 (Op.getValueSizeInBits() == N0.getValueSizeInBits()) ? 4530 APInt(Op.getValueSizeInBits(), 0) : 4531 APInt::getBitsSet(Op.getValueSizeInBits(), 4532 N0.getValueSizeInBits(), 4533 std::min(Op.getValueSizeInBits(), 4534 VT.getSizeInBits())); 4535 if (TruncatedBits == (KnownZero & TruncatedBits)) { 4536 if (VT.bitsGT(Op.getValueType())) 4537 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, Op); 4538 if (VT.bitsLT(Op.getValueType())) 4539 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op); 4540 4541 return Op; 4542 } 4543 } 4544 4545 // fold (zext (truncate (load x))) -> (zext (smaller load x)) 4546 // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n))) 4547 if (N0.getOpcode() == ISD::TRUNCATE) { 4548 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 4549 if (NarrowLoad.getNode()) { 4550 SDNode* oye = N0.getNode()->getOperand(0).getNode(); 4551 if (NarrowLoad.getNode() != N0.getNode()) { 4552 CombineTo(N0.getNode(), NarrowLoad); 4553 // CombineTo deleted the truncate, if needed, but not what's under it. 4554 AddToWorkList(oye); 4555 } 4556 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4557 } 4558 } 4559 4560 // fold (zext (truncate x)) -> (and x, mask) 4561 if (N0.getOpcode() == ISD::TRUNCATE && 4562 (!LegalOperations || TLI.isOperationLegal(ISD::AND, VT))) { 4563 4564 // fold (zext (truncate (load x))) -> (zext (smaller load x)) 4565 // fold (zext (truncate (srl (load x), c))) -> (zext (smaller load (x+c/n))) 4566 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 4567 if (NarrowLoad.getNode()) { 4568 SDNode* oye = N0.getNode()->getOperand(0).getNode(); 4569 if (NarrowLoad.getNode() != N0.getNode()) { 4570 CombineTo(N0.getNode(), NarrowLoad); 4571 // CombineTo deleted the truncate, if needed, but not what's under it. 4572 AddToWorkList(oye); 4573 } 4574 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4575 } 4576 4577 SDValue Op = N0.getOperand(0); 4578 if (Op.getValueType().bitsLT(VT)) { 4579 Op = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, Op); 4580 AddToWorkList(Op.getNode()); 4581 } else if (Op.getValueType().bitsGT(VT)) { 4582 Op = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op); 4583 AddToWorkList(Op.getNode()); 4584 } 4585 return DAG.getZeroExtendInReg(Op, N->getDebugLoc(), 4586 N0.getValueType().getScalarType()); 4587 } 4588 4589 // Fold (zext (and (trunc x), cst)) -> (and x, cst), 4590 // if either of the casts is not free. 4591 if (N0.getOpcode() == ISD::AND && 4592 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 4593 N0.getOperand(1).getOpcode() == ISD::Constant && 4594 (!TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(), 4595 N0.getValueType()) || 4596 !TLI.isZExtFree(N0.getValueType(), VT))) { 4597 SDValue X = N0.getOperand(0).getOperand(0); 4598 if (X.getValueType().bitsLT(VT)) { 4599 X = DAG.getNode(ISD::ANY_EXTEND, X.getDebugLoc(), VT, X); 4600 } else if (X.getValueType().bitsGT(VT)) { 4601 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X); 4602 } 4603 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 4604 Mask = Mask.zext(VT.getSizeInBits()); 4605 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 4606 X, DAG.getConstant(Mask, VT)); 4607 } 4608 4609 // fold (zext (load x)) -> (zext (truncate (zextload x))) 4610 // None of the supported targets knows how to perform load and vector_zext 4611 // on vectors in one instruction. We only perform this transformation on 4612 // scalars. 4613 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() && 4614 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 4615 TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()))) { 4616 bool DoXform = true; 4617 SmallVector<SDNode*, 4> SetCCs; 4618 if (!N0.hasOneUse()) 4619 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ZERO_EXTEND, SetCCs, TLI); 4620 if (DoXform) { 4621 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4622 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT, 4623 LN0->getChain(), 4624 LN0->getBasePtr(), LN0->getPointerInfo(), 4625 N0.getValueType(), 4626 LN0->isVolatile(), LN0->isNonTemporal(), 4627 LN0->getAlignment()); 4628 CombineTo(N, ExtLoad); 4629 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 4630 N0.getValueType(), ExtLoad); 4631 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 4632 4633 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(), 4634 ISD::ZERO_EXTEND); 4635 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4636 } 4637 } 4638 4639 // fold (zext (and/or/xor (load x), cst)) -> 4640 // (and/or/xor (zextload x), (zext cst)) 4641 if ((N0.getOpcode() == ISD::AND || N0.getOpcode() == ISD::OR || 4642 N0.getOpcode() == ISD::XOR) && 4643 isa<LoadSDNode>(N0.getOperand(0)) && 4644 N0.getOperand(1).getOpcode() == ISD::Constant && 4645 TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()) && 4646 (!LegalOperations && TLI.isOperationLegal(N0.getOpcode(), VT))) { 4647 LoadSDNode *LN0 = cast<LoadSDNode>(N0.getOperand(0)); 4648 if (LN0->getExtensionType() != ISD::SEXTLOAD) { 4649 bool DoXform = true; 4650 SmallVector<SDNode*, 4> SetCCs; 4651 if (!N0.hasOneUse()) 4652 DoXform = ExtendUsesToFormExtLoad(N, N0.getOperand(0), ISD::ZERO_EXTEND, 4653 SetCCs, TLI); 4654 if (DoXform) { 4655 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), VT, 4656 LN0->getChain(), LN0->getBasePtr(), 4657 LN0->getPointerInfo(), 4658 LN0->getMemoryVT(), 4659 LN0->isVolatile(), 4660 LN0->isNonTemporal(), 4661 LN0->getAlignment()); 4662 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 4663 Mask = Mask.zext(VT.getSizeInBits()); 4664 SDValue And = DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, 4665 ExtLoad, DAG.getConstant(Mask, VT)); 4666 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, 4667 N0.getOperand(0).getDebugLoc(), 4668 N0.getOperand(0).getValueType(), ExtLoad); 4669 CombineTo(N, And); 4670 CombineTo(N0.getOperand(0).getNode(), Trunc, ExtLoad.getValue(1)); 4671 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(), 4672 ISD::ZERO_EXTEND); 4673 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4674 } 4675 } 4676 } 4677 4678 // fold (zext (zextload x)) -> (zext (truncate (zextload x))) 4679 // fold (zext ( extload x)) -> (zext (truncate (zextload x))) 4680 if ((ISD::isZEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) && 4681 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) { 4682 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4683 EVT MemVT = LN0->getMemoryVT(); 4684 if ((!LegalOperations && !LN0->isVolatile()) || 4685 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT)) { 4686 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT, 4687 LN0->getChain(), 4688 LN0->getBasePtr(), LN0->getPointerInfo(), 4689 MemVT, 4690 LN0->isVolatile(), LN0->isNonTemporal(), 4691 LN0->getAlignment()); 4692 CombineTo(N, ExtLoad); 4693 CombineTo(N0.getNode(), 4694 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), N0.getValueType(), 4695 ExtLoad), 4696 ExtLoad.getValue(1)); 4697 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4698 } 4699 } 4700 4701 if (N0.getOpcode() == ISD::SETCC) { 4702 if (!LegalOperations && VT.isVector()) { 4703 // zext(setcc) -> (and (vsetcc), (1, 1, ...) for vectors. 4704 // Only do this before legalize for now. 4705 EVT N0VT = N0.getOperand(0).getValueType(); 4706 EVT EltVT = VT.getVectorElementType(); 4707 SmallVector<SDValue,8> OneOps(VT.getVectorNumElements(), 4708 DAG.getConstant(1, EltVT)); 4709 if (VT.getSizeInBits() == N0VT.getSizeInBits()) 4710 // We know that the # elements of the results is the same as the 4711 // # elements of the compare (and the # elements of the compare result 4712 // for that matter). Check to see that they are the same size. If so, 4713 // we know that the element size of the sext'd result matches the 4714 // element size of the compare operands. 4715 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 4716 DAG.getSetCC(N->getDebugLoc(), VT, N0.getOperand(0), 4717 N0.getOperand(1), 4718 cast<CondCodeSDNode>(N0.getOperand(2))->get()), 4719 DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT, 4720 &OneOps[0], OneOps.size())); 4721 4722 // If the desired elements are smaller or larger than the source 4723 // elements we can use a matching integer vector type and then 4724 // truncate/sign extend 4725 EVT MatchingElementType = 4726 EVT::getIntegerVT(*DAG.getContext(), 4727 N0VT.getScalarType().getSizeInBits()); 4728 EVT MatchingVectorType = 4729 EVT::getVectorVT(*DAG.getContext(), MatchingElementType, 4730 N0VT.getVectorNumElements()); 4731 SDValue VsetCC = 4732 DAG.getSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0), 4733 N0.getOperand(1), 4734 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 4735 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 4736 DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT), 4737 DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT, 4738 &OneOps[0], OneOps.size())); 4739 } 4740 4741 // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 4742 SDValue SCC = 4743 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 4744 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 4745 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 4746 if (SCC.getNode()) return SCC; 4747 } 4748 4749 // (zext (shl (zext x), cst)) -> (shl (zext x), cst) 4750 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL) && 4751 isa<ConstantSDNode>(N0.getOperand(1)) && 4752 N0.getOperand(0).getOpcode() == ISD::ZERO_EXTEND && 4753 N0.hasOneUse()) { 4754 SDValue ShAmt = N0.getOperand(1); 4755 unsigned ShAmtVal = cast<ConstantSDNode>(ShAmt)->getZExtValue(); 4756 if (N0.getOpcode() == ISD::SHL) { 4757 SDValue InnerZExt = N0.getOperand(0); 4758 // If the original shl may be shifting out bits, do not perform this 4759 // transformation. 4760 unsigned KnownZeroBits = InnerZExt.getValueType().getSizeInBits() - 4761 InnerZExt.getOperand(0).getValueType().getSizeInBits(); 4762 if (ShAmtVal > KnownZeroBits) 4763 return SDValue(); 4764 } 4765 4766 DebugLoc DL = N->getDebugLoc(); 4767 4768 // Ensure that the shift amount is wide enough for the shifted value. 4769 if (VT.getSizeInBits() >= 256) 4770 ShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, ShAmt); 4771 4772 return DAG.getNode(N0.getOpcode(), DL, VT, 4773 DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0)), 4774 ShAmt); 4775 } 4776 4777 return SDValue(); 4778} 4779 4780SDValue DAGCombiner::visitANY_EXTEND(SDNode *N) { 4781 SDValue N0 = N->getOperand(0); 4782 EVT VT = N->getValueType(0); 4783 4784 // fold (aext c1) -> c1 4785 if (isa<ConstantSDNode>(N0)) 4786 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, N0); 4787 // fold (aext (aext x)) -> (aext x) 4788 // fold (aext (zext x)) -> (zext x) 4789 // fold (aext (sext x)) -> (sext x) 4790 if (N0.getOpcode() == ISD::ANY_EXTEND || 4791 N0.getOpcode() == ISD::ZERO_EXTEND || 4792 N0.getOpcode() == ISD::SIGN_EXTEND) 4793 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, N0.getOperand(0)); 4794 4795 // fold (aext (truncate (load x))) -> (aext (smaller load x)) 4796 // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n))) 4797 if (N0.getOpcode() == ISD::TRUNCATE) { 4798 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 4799 if (NarrowLoad.getNode()) { 4800 SDNode* oye = N0.getNode()->getOperand(0).getNode(); 4801 if (NarrowLoad.getNode() != N0.getNode()) { 4802 CombineTo(N0.getNode(), NarrowLoad); 4803 // CombineTo deleted the truncate, if needed, but not what's under it. 4804 AddToWorkList(oye); 4805 } 4806 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4807 } 4808 } 4809 4810 // fold (aext (truncate x)) 4811 if (N0.getOpcode() == ISD::TRUNCATE) { 4812 SDValue TruncOp = N0.getOperand(0); 4813 if (TruncOp.getValueType() == VT) 4814 return TruncOp; // x iff x size == zext size. 4815 if (TruncOp.getValueType().bitsGT(VT)) 4816 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, TruncOp); 4817 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, TruncOp); 4818 } 4819 4820 // Fold (aext (and (trunc x), cst)) -> (and x, cst) 4821 // if the trunc is not free. 4822 if (N0.getOpcode() == ISD::AND && 4823 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 4824 N0.getOperand(1).getOpcode() == ISD::Constant && 4825 !TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(), 4826 N0.getValueType())) { 4827 SDValue X = N0.getOperand(0).getOperand(0); 4828 if (X.getValueType().bitsLT(VT)) { 4829 X = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, X); 4830 } else if (X.getValueType().bitsGT(VT)) { 4831 X = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, X); 4832 } 4833 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 4834 Mask = Mask.zext(VT.getSizeInBits()); 4835 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 4836 X, DAG.getConstant(Mask, VT)); 4837 } 4838 4839 // fold (aext (load x)) -> (aext (truncate (extload x))) 4840 // None of the supported targets knows how to perform load and any_ext 4841 // on vectors in one instruction. We only perform this transformation on 4842 // scalars. 4843 if (ISD::isNON_EXTLoad(N0.getNode()) && !VT.isVector() && 4844 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 4845 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) { 4846 bool DoXform = true; 4847 SmallVector<SDNode*, 4> SetCCs; 4848 if (!N0.hasOneUse()) 4849 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ANY_EXTEND, SetCCs, TLI); 4850 if (DoXform) { 4851 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4852 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT, 4853 LN0->getChain(), 4854 LN0->getBasePtr(), LN0->getPointerInfo(), 4855 N0.getValueType(), 4856 LN0->isVolatile(), LN0->isNonTemporal(), 4857 LN0->getAlignment()); 4858 CombineTo(N, ExtLoad); 4859 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 4860 N0.getValueType(), ExtLoad); 4861 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 4862 ExtendSetCCUses(SetCCs, Trunc, ExtLoad, N->getDebugLoc(), 4863 ISD::ANY_EXTEND); 4864 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4865 } 4866 } 4867 4868 // fold (aext (zextload x)) -> (aext (truncate (zextload x))) 4869 // fold (aext (sextload x)) -> (aext (truncate (sextload x))) 4870 // fold (aext ( extload x)) -> (aext (truncate (extload x))) 4871 if (N0.getOpcode() == ISD::LOAD && 4872 !ISD::isNON_EXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 4873 N0.hasOneUse()) { 4874 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4875 EVT MemVT = LN0->getMemoryVT(); 4876 SDValue ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), N->getDebugLoc(), 4877 VT, LN0->getChain(), LN0->getBasePtr(), 4878 LN0->getPointerInfo(), MemVT, 4879 LN0->isVolatile(), LN0->isNonTemporal(), 4880 LN0->getAlignment()); 4881 CombineTo(N, ExtLoad); 4882 CombineTo(N0.getNode(), 4883 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 4884 N0.getValueType(), ExtLoad), 4885 ExtLoad.getValue(1)); 4886 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4887 } 4888 4889 if (N0.getOpcode() == ISD::SETCC) { 4890 // aext(setcc) -> sext_in_reg(vsetcc) for vectors. 4891 // Only do this before legalize for now. 4892 if (VT.isVector() && !LegalOperations) { 4893 EVT N0VT = N0.getOperand(0).getValueType(); 4894 // We know that the # elements of the results is the same as the 4895 // # elements of the compare (and the # elements of the compare result 4896 // for that matter). Check to see that they are the same size. If so, 4897 // we know that the element size of the sext'd result matches the 4898 // element size of the compare operands. 4899 if (VT.getSizeInBits() == N0VT.getSizeInBits()) 4900 return DAG.getSetCC(N->getDebugLoc(), VT, N0.getOperand(0), 4901 N0.getOperand(1), 4902 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 4903 // If the desired elements are smaller or larger than the source 4904 // elements we can use a matching integer vector type and then 4905 // truncate/sign extend 4906 else { 4907 EVT MatchingElementType = 4908 EVT::getIntegerVT(*DAG.getContext(), 4909 N0VT.getScalarType().getSizeInBits()); 4910 EVT MatchingVectorType = 4911 EVT::getVectorVT(*DAG.getContext(), MatchingElementType, 4912 N0VT.getVectorNumElements()); 4913 SDValue VsetCC = 4914 DAG.getSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0), 4915 N0.getOperand(1), 4916 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 4917 return DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT); 4918 } 4919 } 4920 4921 // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 4922 SDValue SCC = 4923 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 4924 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 4925 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 4926 if (SCC.getNode()) 4927 return SCC; 4928 } 4929 4930 return SDValue(); 4931} 4932 4933/// GetDemandedBits - See if the specified operand can be simplified with the 4934/// knowledge that only the bits specified by Mask are used. If so, return the 4935/// simpler operand, otherwise return a null SDValue. 4936SDValue DAGCombiner::GetDemandedBits(SDValue V, const APInt &Mask) { 4937 switch (V.getOpcode()) { 4938 default: break; 4939 case ISD::Constant: { 4940 const ConstantSDNode *CV = cast<ConstantSDNode>(V.getNode()); 4941 assert(CV != 0 && "Const value should be ConstSDNode."); 4942 const APInt &CVal = CV->getAPIntValue(); 4943 APInt NewVal = CVal & Mask; 4944 if (NewVal != CVal) { 4945 return DAG.getConstant(NewVal, V.getValueType()); 4946 } 4947 break; 4948 } 4949 case ISD::OR: 4950 case ISD::XOR: 4951 // If the LHS or RHS don't contribute bits to the or, drop them. 4952 if (DAG.MaskedValueIsZero(V.getOperand(0), Mask)) 4953 return V.getOperand(1); 4954 if (DAG.MaskedValueIsZero(V.getOperand(1), Mask)) 4955 return V.getOperand(0); 4956 break; 4957 case ISD::SRL: 4958 // Only look at single-use SRLs. 4959 if (!V.getNode()->hasOneUse()) 4960 break; 4961 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(V.getOperand(1))) { 4962 // See if we can recursively simplify the LHS. 4963 unsigned Amt = RHSC->getZExtValue(); 4964 4965 // Watch out for shift count overflow though. 4966 if (Amt >= Mask.getBitWidth()) break; 4967 APInt NewMask = Mask << Amt; 4968 SDValue SimplifyLHS = GetDemandedBits(V.getOperand(0), NewMask); 4969 if (SimplifyLHS.getNode()) 4970 return DAG.getNode(ISD::SRL, V.getDebugLoc(), V.getValueType(), 4971 SimplifyLHS, V.getOperand(1)); 4972 } 4973 } 4974 return SDValue(); 4975} 4976 4977/// ReduceLoadWidth - If the result of a wider load is shifted to right of N 4978/// bits and then truncated to a narrower type and where N is a multiple 4979/// of number of bits of the narrower type, transform it to a narrower load 4980/// from address + N / num of bits of new type. If the result is to be 4981/// extended, also fold the extension to form a extending load. 4982SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) { 4983 unsigned Opc = N->getOpcode(); 4984 4985 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD; 4986 SDValue N0 = N->getOperand(0); 4987 EVT VT = N->getValueType(0); 4988 EVT ExtVT = VT; 4989 4990 // This transformation isn't valid for vector loads. 4991 if (VT.isVector()) 4992 return SDValue(); 4993 4994 // Special case: SIGN_EXTEND_INREG is basically truncating to ExtVT then 4995 // extended to VT. 4996 if (Opc == ISD::SIGN_EXTEND_INREG) { 4997 ExtType = ISD::SEXTLOAD; 4998 ExtVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 4999 } else if (Opc == ISD::SRL) { 5000 // Another special-case: SRL is basically zero-extending a narrower value. 5001 ExtType = ISD::ZEXTLOAD; 5002 N0 = SDValue(N, 0); 5003 ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 5004 if (!N01) return SDValue(); 5005 ExtVT = EVT::getIntegerVT(*DAG.getContext(), 5006 VT.getSizeInBits() - N01->getZExtValue()); 5007 } 5008 if (LegalOperations && !TLI.isLoadExtLegal(ExtType, ExtVT)) 5009 return SDValue(); 5010 5011 unsigned EVTBits = ExtVT.getSizeInBits(); 5012 5013 // Do not generate loads of non-round integer types since these can 5014 // be expensive (and would be wrong if the type is not byte sized). 5015 if (!ExtVT.isRound()) 5016 return SDValue(); 5017 5018 unsigned ShAmt = 0; 5019 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) { 5020 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 5021 ShAmt = N01->getZExtValue(); 5022 // Is the shift amount a multiple of size of VT? 5023 if ((ShAmt & (EVTBits-1)) == 0) { 5024 N0 = N0.getOperand(0); 5025 // Is the load width a multiple of size of VT? 5026 if ((N0.getValueType().getSizeInBits() & (EVTBits-1)) != 0) 5027 return SDValue(); 5028 } 5029 5030 // At this point, we must have a load or else we can't do the transform. 5031 if (!isa<LoadSDNode>(N0)) return SDValue(); 5032 5033 // If the shift amount is larger than the input type then we're not 5034 // accessing any of the loaded bytes. If the load was a zextload/extload 5035 // then the result of the shift+trunc is zero/undef (handled elsewhere). 5036 // If the load was a sextload then the result is a splat of the sign bit 5037 // of the extended byte. This is not worth optimizing for. 5038 if (ShAmt >= cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits()) 5039 return SDValue(); 5040 } 5041 } 5042 5043 // If the load is shifted left (and the result isn't shifted back right), 5044 // we can fold the truncate through the shift. 5045 unsigned ShLeftAmt = 0; 5046 if (ShAmt == 0 && N0.getOpcode() == ISD::SHL && N0.hasOneUse() && 5047 ExtVT == VT && TLI.isNarrowingProfitable(N0.getValueType(), VT)) { 5048 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 5049 ShLeftAmt = N01->getZExtValue(); 5050 N0 = N0.getOperand(0); 5051 } 5052 } 5053 5054 // If we haven't found a load, we can't narrow it. Don't transform one with 5055 // multiple uses, this would require adding a new load. 5056 if (!isa<LoadSDNode>(N0) || !N0.hasOneUse() || 5057 // Don't change the width of a volatile load. 5058 cast<LoadSDNode>(N0)->isVolatile()) 5059 return SDValue(); 5060 5061 // Verify that we are actually reducing a load width here. 5062 if (cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits() < EVTBits) 5063 return SDValue(); 5064 5065 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 5066 EVT PtrType = N0.getOperand(1).getValueType(); 5067 5068 if (PtrType == MVT::Untyped || PtrType.isExtended()) 5069 // It's not possible to generate a constant of extended or untyped type. 5070 return SDValue(); 5071 5072 // For big endian targets, we need to adjust the offset to the pointer to 5073 // load the correct bytes. 5074 if (TLI.isBigEndian()) { 5075 unsigned LVTStoreBits = LN0->getMemoryVT().getStoreSizeInBits(); 5076 unsigned EVTStoreBits = ExtVT.getStoreSizeInBits(); 5077 ShAmt = LVTStoreBits - EVTStoreBits - ShAmt; 5078 } 5079 5080 uint64_t PtrOff = ShAmt / 8; 5081 unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff); 5082 SDValue NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(), 5083 PtrType, LN0->getBasePtr(), 5084 DAG.getConstant(PtrOff, PtrType)); 5085 AddToWorkList(NewPtr.getNode()); 5086 5087 SDValue Load; 5088 if (ExtType == ISD::NON_EXTLOAD) 5089 Load = DAG.getLoad(VT, N0.getDebugLoc(), LN0->getChain(), NewPtr, 5090 LN0->getPointerInfo().getWithOffset(PtrOff), 5091 LN0->isVolatile(), LN0->isNonTemporal(), 5092 LN0->isInvariant(), NewAlign); 5093 else 5094 Load = DAG.getExtLoad(ExtType, N0.getDebugLoc(), VT, LN0->getChain(),NewPtr, 5095 LN0->getPointerInfo().getWithOffset(PtrOff), 5096 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(), 5097 NewAlign); 5098 5099 // Replace the old load's chain with the new load's chain. 5100 WorkListRemover DeadNodes(*this); 5101 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1)); 5102 5103 // Shift the result left, if we've swallowed a left shift. 5104 SDValue Result = Load; 5105 if (ShLeftAmt != 0) { 5106 EVT ShImmTy = getShiftAmountTy(Result.getValueType()); 5107 if (!isUIntN(ShImmTy.getSizeInBits(), ShLeftAmt)) 5108 ShImmTy = VT; 5109 Result = DAG.getNode(ISD::SHL, N0.getDebugLoc(), VT, 5110 Result, DAG.getConstant(ShLeftAmt, ShImmTy)); 5111 } 5112 5113 // Return the new loaded value. 5114 return Result; 5115} 5116 5117SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) { 5118 SDValue N0 = N->getOperand(0); 5119 SDValue N1 = N->getOperand(1); 5120 EVT VT = N->getValueType(0); 5121 EVT EVT = cast<VTSDNode>(N1)->getVT(); 5122 unsigned VTBits = VT.getScalarType().getSizeInBits(); 5123 unsigned EVTBits = EVT.getScalarType().getSizeInBits(); 5124 5125 // fold (sext_in_reg c1) -> c1 5126 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF) 5127 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, N0, N1); 5128 5129 // If the input is already sign extended, just drop the extension. 5130 if (DAG.ComputeNumSignBits(N0) >= VTBits-EVTBits+1) 5131 return N0; 5132 5133 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2 5134 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 5135 EVT.bitsLT(cast<VTSDNode>(N0.getOperand(1))->getVT())) { 5136 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, 5137 N0.getOperand(0), N1); 5138 } 5139 5140 // fold (sext_in_reg (sext x)) -> (sext x) 5141 // fold (sext_in_reg (aext x)) -> (sext x) 5142 // if x is small enough. 5143 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) { 5144 SDValue N00 = N0.getOperand(0); 5145 if (N00.getValueType().getScalarType().getSizeInBits() <= EVTBits && 5146 (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND, VT))) 5147 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N00, N1); 5148 } 5149 5150 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero. 5151 if (DAG.MaskedValueIsZero(N0, APInt::getBitsSet(VTBits, EVTBits-1, EVTBits))) 5152 return DAG.getZeroExtendInReg(N0, N->getDebugLoc(), EVT); 5153 5154 // fold operands of sext_in_reg based on knowledge that the top bits are not 5155 // demanded. 5156 if (SimplifyDemandedBits(SDValue(N, 0))) 5157 return SDValue(N, 0); 5158 5159 // fold (sext_in_reg (load x)) -> (smaller sextload x) 5160 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits)) 5161 SDValue NarrowLoad = ReduceLoadWidth(N); 5162 if (NarrowLoad.getNode()) 5163 return NarrowLoad; 5164 5165 // fold (sext_in_reg (srl X, 24), i8) -> (sra X, 24) 5166 // fold (sext_in_reg (srl X, 23), i8) -> (sra X, 23) iff possible. 5167 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above. 5168 if (N0.getOpcode() == ISD::SRL) { 5169 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 5170 if (ShAmt->getZExtValue()+EVTBits <= VTBits) { 5171 // We can turn this into an SRA iff the input to the SRL is already sign 5172 // extended enough. 5173 unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0)); 5174 if (VTBits-(ShAmt->getZExtValue()+EVTBits) < InSignBits) 5175 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, 5176 N0.getOperand(0), N0.getOperand(1)); 5177 } 5178 } 5179 5180 // fold (sext_inreg (extload x)) -> (sextload x) 5181 if (ISD::isEXTLoad(N0.getNode()) && 5182 ISD::isUNINDEXEDLoad(N0.getNode()) && 5183 EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 5184 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 5185 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) { 5186 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 5187 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 5188 LN0->getChain(), 5189 LN0->getBasePtr(), LN0->getPointerInfo(), 5190 EVT, 5191 LN0->isVolatile(), LN0->isNonTemporal(), 5192 LN0->getAlignment()); 5193 CombineTo(N, ExtLoad); 5194 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 5195 return SDValue(N, 0); // Return N so it doesn't get rechecked! 5196 } 5197 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use 5198 if (ISD::isZEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 5199 N0.hasOneUse() && 5200 EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 5201 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 5202 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) { 5203 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 5204 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 5205 LN0->getChain(), 5206 LN0->getBasePtr(), LN0->getPointerInfo(), 5207 EVT, 5208 LN0->isVolatile(), LN0->isNonTemporal(), 5209 LN0->getAlignment()); 5210 CombineTo(N, ExtLoad); 5211 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 5212 return SDValue(N, 0); // Return N so it doesn't get rechecked! 5213 } 5214 5215 // Form (sext_inreg (bswap >> 16)) or (sext_inreg (rotl (bswap) 16)) 5216 if (EVTBits <= 16 && N0.getOpcode() == ISD::OR) { 5217 SDValue BSwap = MatchBSwapHWordLow(N0.getNode(), N0.getOperand(0), 5218 N0.getOperand(1), false); 5219 if (BSwap.getNode() != 0) 5220 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, 5221 BSwap, N1); 5222 } 5223 5224 return SDValue(); 5225} 5226 5227SDValue DAGCombiner::visitTRUNCATE(SDNode *N) { 5228 SDValue N0 = N->getOperand(0); 5229 EVT VT = N->getValueType(0); 5230 bool isLE = TLI.isLittleEndian(); 5231 5232 // noop truncate 5233 if (N0.getValueType() == N->getValueType(0)) 5234 return N0; 5235 // fold (truncate c1) -> c1 5236 if (isa<ConstantSDNode>(N0)) 5237 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0); 5238 // fold (truncate (truncate x)) -> (truncate x) 5239 if (N0.getOpcode() == ISD::TRUNCATE) 5240 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0)); 5241 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x 5242 if (N0.getOpcode() == ISD::ZERO_EXTEND || 5243 N0.getOpcode() == ISD::SIGN_EXTEND || 5244 N0.getOpcode() == ISD::ANY_EXTEND) { 5245 if (N0.getOperand(0).getValueType().bitsLT(VT)) 5246 // if the source is smaller than the dest, we still need an extend 5247 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, 5248 N0.getOperand(0)); 5249 else if (N0.getOperand(0).getValueType().bitsGT(VT)) 5250 // if the source is larger than the dest, than we just need the truncate 5251 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0)); 5252 else 5253 // if the source and dest are the same type, we can drop both the extend 5254 // and the truncate. 5255 return N0.getOperand(0); 5256 } 5257 5258 // Fold extract-and-trunc into a narrow extract. For example: 5259 // i64 x = EXTRACT_VECTOR_ELT(v2i64 val, i32 1) 5260 // i32 y = TRUNCATE(i64 x) 5261 // -- becomes -- 5262 // v16i8 b = BITCAST (v2i64 val) 5263 // i8 x = EXTRACT_VECTOR_ELT(v16i8 b, i32 8) 5264 // 5265 // Note: We only run this optimization after type legalization (which often 5266 // creates this pattern) and before operation legalization after which 5267 // we need to be more careful about the vector instructions that we generate. 5268 if (N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT && 5269 LegalTypes && !LegalOperations && N0->hasOneUse()) { 5270 5271 EVT VecTy = N0.getOperand(0).getValueType(); 5272 EVT ExTy = N0.getValueType(); 5273 EVT TrTy = N->getValueType(0); 5274 5275 unsigned NumElem = VecTy.getVectorNumElements(); 5276 unsigned SizeRatio = ExTy.getSizeInBits()/TrTy.getSizeInBits(); 5277 5278 EVT NVT = EVT::getVectorVT(*DAG.getContext(), TrTy, SizeRatio * NumElem); 5279 assert(NVT.getSizeInBits() == VecTy.getSizeInBits() && "Invalid Size"); 5280 5281 SDValue EltNo = N0->getOperand(1); 5282 if (isa<ConstantSDNode>(EltNo) && isTypeLegal(NVT)) { 5283 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 5284 EVT IndexTy = N0->getOperand(1).getValueType(); 5285 int Index = isLE ? (Elt*SizeRatio) : (Elt*SizeRatio + (SizeRatio-1)); 5286 5287 SDValue V = DAG.getNode(ISD::BITCAST, N->getDebugLoc(), 5288 NVT, N0.getOperand(0)); 5289 5290 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, 5291 N->getDebugLoc(), TrTy, V, 5292 DAG.getConstant(Index, IndexTy)); 5293 } 5294 } 5295 5296 // See if we can simplify the input to this truncate through knowledge that 5297 // only the low bits are being used. 5298 // For example "trunc (or (shl x, 8), y)" // -> trunc y 5299 // Currently we only perform this optimization on scalars because vectors 5300 // may have different active low bits. 5301 if (!VT.isVector()) { 5302 SDValue Shorter = 5303 GetDemandedBits(N0, APInt::getLowBitsSet(N0.getValueSizeInBits(), 5304 VT.getSizeInBits())); 5305 if (Shorter.getNode()) 5306 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Shorter); 5307 } 5308 // fold (truncate (load x)) -> (smaller load x) 5309 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits)) 5310 if (!LegalTypes || TLI.isTypeDesirableForOp(N0.getOpcode(), VT)) { 5311 SDValue Reduced = ReduceLoadWidth(N); 5312 if (Reduced.getNode()) 5313 return Reduced; 5314 } 5315 5316 // Simplify the operands using demanded-bits information. 5317 if (!VT.isVector() && 5318 SimplifyDemandedBits(SDValue(N, 0))) 5319 return SDValue(N, 0); 5320 5321 return SDValue(); 5322} 5323 5324static SDNode *getBuildPairElt(SDNode *N, unsigned i) { 5325 SDValue Elt = N->getOperand(i); 5326 if (Elt.getOpcode() != ISD::MERGE_VALUES) 5327 return Elt.getNode(); 5328 return Elt.getOperand(Elt.getResNo()).getNode(); 5329} 5330 5331/// CombineConsecutiveLoads - build_pair (load, load) -> load 5332/// if load locations are consecutive. 5333SDValue DAGCombiner::CombineConsecutiveLoads(SDNode *N, EVT VT) { 5334 assert(N->getOpcode() == ISD::BUILD_PAIR); 5335 5336 LoadSDNode *LD1 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 0)); 5337 LoadSDNode *LD2 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 1)); 5338 if (!LD1 || !LD2 || !ISD::isNON_EXTLoad(LD1) || !LD1->hasOneUse() || 5339 LD1->getPointerInfo().getAddrSpace() != 5340 LD2->getPointerInfo().getAddrSpace()) 5341 return SDValue(); 5342 EVT LD1VT = LD1->getValueType(0); 5343 5344 if (ISD::isNON_EXTLoad(LD2) && 5345 LD2->hasOneUse() && 5346 // If both are volatile this would reduce the number of volatile loads. 5347 // If one is volatile it might be ok, but play conservative and bail out. 5348 !LD1->isVolatile() && 5349 !LD2->isVolatile() && 5350 DAG.isConsecutiveLoad(LD2, LD1, LD1VT.getSizeInBits()/8, 1)) { 5351 unsigned Align = LD1->getAlignment(); 5352 unsigned NewAlign = TLI.getTargetData()-> 5353 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext())); 5354 5355 if (NewAlign <= Align && 5356 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) 5357 return DAG.getLoad(VT, N->getDebugLoc(), LD1->getChain(), 5358 LD1->getBasePtr(), LD1->getPointerInfo(), 5359 false, false, false, Align); 5360 } 5361 5362 return SDValue(); 5363} 5364 5365SDValue DAGCombiner::visitBITCAST(SDNode *N) { 5366 SDValue N0 = N->getOperand(0); 5367 EVT VT = N->getValueType(0); 5368 5369 // If the input is a BUILD_VECTOR with all constant elements, fold this now. 5370 // Only do this before legalize, since afterward the target may be depending 5371 // on the bitconvert. 5372 // First check to see if this is all constant. 5373 if (!LegalTypes && 5374 N0.getOpcode() == ISD::BUILD_VECTOR && N0.getNode()->hasOneUse() && 5375 VT.isVector()) { 5376 bool isSimple = true; 5377 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i) 5378 if (N0.getOperand(i).getOpcode() != ISD::UNDEF && 5379 N0.getOperand(i).getOpcode() != ISD::Constant && 5380 N0.getOperand(i).getOpcode() != ISD::ConstantFP) { 5381 isSimple = false; 5382 break; 5383 } 5384 5385 EVT DestEltVT = N->getValueType(0).getVectorElementType(); 5386 assert(!DestEltVT.isVector() && 5387 "Element type of vector ValueType must not be vector!"); 5388 if (isSimple) 5389 return ConstantFoldBITCASTofBUILD_VECTOR(N0.getNode(), DestEltVT); 5390 } 5391 5392 // If the input is a constant, let getNode fold it. 5393 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) { 5394 SDValue Res = DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, N0); 5395 if (Res.getNode() != N) { 5396 if (!LegalOperations || 5397 TLI.isOperationLegal(Res.getNode()->getOpcode(), VT)) 5398 return Res; 5399 5400 // Folding it resulted in an illegal node, and it's too late to 5401 // do that. Clean up the old node and forego the transformation. 5402 // Ideally this won't happen very often, because instcombine 5403 // and the earlier dagcombine runs (where illegal nodes are 5404 // permitted) should have folded most of them already. 5405 DAG.DeleteNode(Res.getNode()); 5406 } 5407 } 5408 5409 // (conv (conv x, t1), t2) -> (conv x, t2) 5410 if (N0.getOpcode() == ISD::BITCAST) 5411 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, 5412 N0.getOperand(0)); 5413 5414 // fold (conv (load x)) -> (load (conv*)x) 5415 // If the resultant load doesn't need a higher alignment than the original! 5416 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() && 5417 // Do not change the width of a volatile load. 5418 !cast<LoadSDNode>(N0)->isVolatile() && 5419 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) { 5420 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 5421 unsigned Align = TLI.getTargetData()-> 5422 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext())); 5423 unsigned OrigAlign = LN0->getAlignment(); 5424 5425 if (Align <= OrigAlign) { 5426 SDValue Load = DAG.getLoad(VT, N->getDebugLoc(), LN0->getChain(), 5427 LN0->getBasePtr(), LN0->getPointerInfo(), 5428 LN0->isVolatile(), LN0->isNonTemporal(), 5429 LN0->isInvariant(), OrigAlign); 5430 AddToWorkList(N); 5431 CombineTo(N0.getNode(), 5432 DAG.getNode(ISD::BITCAST, N0.getDebugLoc(), 5433 N0.getValueType(), Load), 5434 Load.getValue(1)); 5435 return Load; 5436 } 5437 } 5438 5439 // fold (bitconvert (fneg x)) -> (xor (bitconvert x), signbit) 5440 // fold (bitconvert (fabs x)) -> (and (bitconvert x), (not signbit)) 5441 // This often reduces constant pool loads. 5442 if (((N0.getOpcode() == ISD::FNEG && !TLI.isFNegFree(VT)) || 5443 (N0.getOpcode() == ISD::FABS && !TLI.isFAbsFree(VT))) && 5444 N0.getNode()->hasOneUse() && VT.isInteger() && !VT.isVector()) { 5445 SDValue NewConv = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(), VT, 5446 N0.getOperand(0)); 5447 AddToWorkList(NewConv.getNode()); 5448 5449 APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); 5450 if (N0.getOpcode() == ISD::FNEG) 5451 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, 5452 NewConv, DAG.getConstant(SignBit, VT)); 5453 assert(N0.getOpcode() == ISD::FABS); 5454 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 5455 NewConv, DAG.getConstant(~SignBit, VT)); 5456 } 5457 5458 // fold (bitconvert (fcopysign cst, x)) -> 5459 // (or (and (bitconvert x), sign), (and cst, (not sign))) 5460 // Note that we don't handle (copysign x, cst) because this can always be 5461 // folded to an fneg or fabs. 5462 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse() && 5463 isa<ConstantFPSDNode>(N0.getOperand(0)) && 5464 VT.isInteger() && !VT.isVector()) { 5465 unsigned OrigXWidth = N0.getOperand(1).getValueType().getSizeInBits(); 5466 EVT IntXVT = EVT::getIntegerVT(*DAG.getContext(), OrigXWidth); 5467 if (isTypeLegal(IntXVT)) { 5468 SDValue X = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(), 5469 IntXVT, N0.getOperand(1)); 5470 AddToWorkList(X.getNode()); 5471 5472 // If X has a different width than the result/lhs, sext it or truncate it. 5473 unsigned VTWidth = VT.getSizeInBits(); 5474 if (OrigXWidth < VTWidth) { 5475 X = DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, X); 5476 AddToWorkList(X.getNode()); 5477 } else if (OrigXWidth > VTWidth) { 5478 // To get the sign bit in the right place, we have to shift it right 5479 // before truncating. 5480 X = DAG.getNode(ISD::SRL, X.getDebugLoc(), 5481 X.getValueType(), X, 5482 DAG.getConstant(OrigXWidth-VTWidth, X.getValueType())); 5483 AddToWorkList(X.getNode()); 5484 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X); 5485 AddToWorkList(X.getNode()); 5486 } 5487 5488 APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); 5489 X = DAG.getNode(ISD::AND, X.getDebugLoc(), VT, 5490 X, DAG.getConstant(SignBit, VT)); 5491 AddToWorkList(X.getNode()); 5492 5493 SDValue Cst = DAG.getNode(ISD::BITCAST, N0.getDebugLoc(), 5494 VT, N0.getOperand(0)); 5495 Cst = DAG.getNode(ISD::AND, Cst.getDebugLoc(), VT, 5496 Cst, DAG.getConstant(~SignBit, VT)); 5497 AddToWorkList(Cst.getNode()); 5498 5499 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, X, Cst); 5500 } 5501 } 5502 5503 // bitconvert(build_pair(ld, ld)) -> ld iff load locations are consecutive. 5504 if (N0.getOpcode() == ISD::BUILD_PAIR) { 5505 SDValue CombineLD = CombineConsecutiveLoads(N0.getNode(), VT); 5506 if (CombineLD.getNode()) 5507 return CombineLD; 5508 } 5509 5510 return SDValue(); 5511} 5512 5513SDValue DAGCombiner::visitBUILD_PAIR(SDNode *N) { 5514 EVT VT = N->getValueType(0); 5515 return CombineConsecutiveLoads(N, VT); 5516} 5517 5518/// ConstantFoldBITCASTofBUILD_VECTOR - We know that BV is a build_vector 5519/// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the 5520/// destination element value type. 5521SDValue DAGCombiner:: 5522ConstantFoldBITCASTofBUILD_VECTOR(SDNode *BV, EVT DstEltVT) { 5523 EVT SrcEltVT = BV->getValueType(0).getVectorElementType(); 5524 5525 // If this is already the right type, we're done. 5526 if (SrcEltVT == DstEltVT) return SDValue(BV, 0); 5527 5528 unsigned SrcBitSize = SrcEltVT.getSizeInBits(); 5529 unsigned DstBitSize = DstEltVT.getSizeInBits(); 5530 5531 // If this is a conversion of N elements of one type to N elements of another 5532 // type, convert each element. This handles FP<->INT cases. 5533 if (SrcBitSize == DstBitSize) { 5534 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, 5535 BV->getValueType(0).getVectorNumElements()); 5536 5537 // Due to the FP element handling below calling this routine recursively, 5538 // we can end up with a scalar-to-vector node here. 5539 if (BV->getOpcode() == ISD::SCALAR_TO_VECTOR) 5540 return DAG.getNode(ISD::SCALAR_TO_VECTOR, BV->getDebugLoc(), VT, 5541 DAG.getNode(ISD::BITCAST, BV->getDebugLoc(), 5542 DstEltVT, BV->getOperand(0))); 5543 5544 SmallVector<SDValue, 8> Ops; 5545 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 5546 SDValue Op = BV->getOperand(i); 5547 // If the vector element type is not legal, the BUILD_VECTOR operands 5548 // are promoted and implicitly truncated. Make that explicit here. 5549 if (Op.getValueType() != SrcEltVT) 5550 Op = DAG.getNode(ISD::TRUNCATE, BV->getDebugLoc(), SrcEltVT, Op); 5551 Ops.push_back(DAG.getNode(ISD::BITCAST, BV->getDebugLoc(), 5552 DstEltVT, Op)); 5553 AddToWorkList(Ops.back().getNode()); 5554 } 5555 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 5556 &Ops[0], Ops.size()); 5557 } 5558 5559 // Otherwise, we're growing or shrinking the elements. To avoid having to 5560 // handle annoying details of growing/shrinking FP values, we convert them to 5561 // int first. 5562 if (SrcEltVT.isFloatingPoint()) { 5563 // Convert the input float vector to a int vector where the elements are the 5564 // same sizes. 5565 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!"); 5566 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), SrcEltVT.getSizeInBits()); 5567 BV = ConstantFoldBITCASTofBUILD_VECTOR(BV, IntVT).getNode(); 5568 SrcEltVT = IntVT; 5569 } 5570 5571 // Now we know the input is an integer vector. If the output is a FP type, 5572 // convert to integer first, then to FP of the right size. 5573 if (DstEltVT.isFloatingPoint()) { 5574 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!"); 5575 EVT TmpVT = EVT::getIntegerVT(*DAG.getContext(), DstEltVT.getSizeInBits()); 5576 SDNode *Tmp = ConstantFoldBITCASTofBUILD_VECTOR(BV, TmpVT).getNode(); 5577 5578 // Next, convert to FP elements of the same size. 5579 return ConstantFoldBITCASTofBUILD_VECTOR(Tmp, DstEltVT); 5580 } 5581 5582 // Okay, we know the src/dst types are both integers of differing types. 5583 // Handling growing first. 5584 assert(SrcEltVT.isInteger() && DstEltVT.isInteger()); 5585 if (SrcBitSize < DstBitSize) { 5586 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize; 5587 5588 SmallVector<SDValue, 8> Ops; 5589 for (unsigned i = 0, e = BV->getNumOperands(); i != e; 5590 i += NumInputsPerOutput) { 5591 bool isLE = TLI.isLittleEndian(); 5592 APInt NewBits = APInt(DstBitSize, 0); 5593 bool EltIsUndef = true; 5594 for (unsigned j = 0; j != NumInputsPerOutput; ++j) { 5595 // Shift the previously computed bits over. 5596 NewBits <<= SrcBitSize; 5597 SDValue Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j)); 5598 if (Op.getOpcode() == ISD::UNDEF) continue; 5599 EltIsUndef = false; 5600 5601 NewBits |= cast<ConstantSDNode>(Op)->getAPIntValue(). 5602 zextOrTrunc(SrcBitSize).zext(DstBitSize); 5603 } 5604 5605 if (EltIsUndef) 5606 Ops.push_back(DAG.getUNDEF(DstEltVT)); 5607 else 5608 Ops.push_back(DAG.getConstant(NewBits, DstEltVT)); 5609 } 5610 5611 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, Ops.size()); 5612 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 5613 &Ops[0], Ops.size()); 5614 } 5615 5616 // Finally, this must be the case where we are shrinking elements: each input 5617 // turns into multiple outputs. 5618 bool isS2V = ISD::isScalarToVector(BV); 5619 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize; 5620 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, 5621 NumOutputsPerInput*BV->getNumOperands()); 5622 SmallVector<SDValue, 8> Ops; 5623 5624 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 5625 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) { 5626 for (unsigned j = 0; j != NumOutputsPerInput; ++j) 5627 Ops.push_back(DAG.getUNDEF(DstEltVT)); 5628 continue; 5629 } 5630 5631 APInt OpVal = cast<ConstantSDNode>(BV->getOperand(i))-> 5632 getAPIntValue().zextOrTrunc(SrcBitSize); 5633 5634 for (unsigned j = 0; j != NumOutputsPerInput; ++j) { 5635 APInt ThisVal = OpVal.trunc(DstBitSize); 5636 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT)); 5637 if (isS2V && i == 0 && j == 0 && ThisVal.zext(SrcBitSize) == OpVal) 5638 // Simply turn this into a SCALAR_TO_VECTOR of the new type. 5639 return DAG.getNode(ISD::SCALAR_TO_VECTOR, BV->getDebugLoc(), VT, 5640 Ops[0]); 5641 OpVal = OpVal.lshr(DstBitSize); 5642 } 5643 5644 // For big endian targets, swap the order of the pieces of each element. 5645 if (TLI.isBigEndian()) 5646 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end()); 5647 } 5648 5649 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 5650 &Ops[0], Ops.size()); 5651} 5652 5653SDValue DAGCombiner::visitFADD(SDNode *N) { 5654 SDValue N0 = N->getOperand(0); 5655 SDValue N1 = N->getOperand(1); 5656 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5657 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 5658 EVT VT = N->getValueType(0); 5659 5660 // fold vector ops 5661 if (VT.isVector()) { 5662 SDValue FoldedVOp = SimplifyVBinOp(N); 5663 if (FoldedVOp.getNode()) return FoldedVOp; 5664 } 5665 5666 // fold (fadd c1, c2) -> c1 + c2 5667 if (N0CFP && N1CFP && VT != MVT::ppcf128) 5668 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N1); 5669 // canonicalize constant to RHS 5670 if (N0CFP && !N1CFP) 5671 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N1, N0); 5672 // fold (fadd A, 0) -> A 5673 if (DAG.getTarget().Options.UnsafeFPMath && N1CFP && 5674 N1CFP->getValueAPF().isZero()) 5675 return N0; 5676 // fold (fadd A, (fneg B)) -> (fsub A, B) 5677 if ((!LegalOperations || TLI.isOperationLegalOrCustom(ISD::FSUB, VT)) && 5678 isNegatibleForFree(N1, LegalOperations, TLI, &DAG.getTarget().Options) == 2) 5679 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, 5680 GetNegatedExpression(N1, DAG, LegalOperations)); 5681 // fold (fadd (fneg A), B) -> (fsub B, A) 5682 if ((!LegalOperations || TLI.isOperationLegalOrCustom(ISD::FSUB, VT)) && 5683 isNegatibleForFree(N0, LegalOperations, TLI, &DAG.getTarget().Options) == 2) 5684 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N1, 5685 GetNegatedExpression(N0, DAG, LegalOperations)); 5686 5687 // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2)) 5688 if (DAG.getTarget().Options.UnsafeFPMath && N1CFP && 5689 N0.getOpcode() == ISD::FADD && N0.getNode()->hasOneUse() && 5690 isa<ConstantFPSDNode>(N0.getOperand(1))) 5691 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0.getOperand(0), 5692 DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, 5693 N0.getOperand(1), N1)); 5694 5695 // In unsafe math mode, we can fold chains of FADD's of the same value 5696 // into multiplications. This transform is not safe in general because 5697 // we are reducing the number of rounding steps. 5698 if (DAG.getTarget().Options.UnsafeFPMath && 5699 TLI.isOperationLegalOrCustom(ISD::FMUL, VT) && 5700 !N0CFP && !N1CFP) { 5701 if (N0.getOpcode() == ISD::FMUL) { 5702 ConstantFPSDNode *CFP00 = dyn_cast<ConstantFPSDNode>(N0.getOperand(0)); 5703 ConstantFPSDNode *CFP01 = dyn_cast<ConstantFPSDNode>(N0.getOperand(1)); 5704 5705 // (fadd (fmul c, x), x) -> (fmul c+1, x) 5706 if (CFP00 && !CFP01 && N0.getOperand(1) == N1) { 5707 SDValue NewCFP = DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, 5708 SDValue(CFP00, 0), 5709 DAG.getConstantFP(1.0, VT)); 5710 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 5711 N1, NewCFP); 5712 } 5713 5714 // (fadd (fmul x, c), x) -> (fmul c+1, x) 5715 if (CFP01 && !CFP00 && N0.getOperand(0) == N1) { 5716 SDValue NewCFP = DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, 5717 SDValue(CFP01, 0), 5718 DAG.getConstantFP(1.0, VT)); 5719 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 5720 N1, NewCFP); 5721 } 5722 5723 // (fadd (fadd x, x), x) -> (fmul 3.0, x) 5724 if (!CFP00 && !CFP01 && N0.getOperand(0) == N0.getOperand(1) && 5725 N0.getOperand(0) == N1) { 5726 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 5727 N1, DAG.getConstantFP(3.0, VT)); 5728 } 5729 5730 // (fadd (fmul c, x), (fadd x, x)) -> (fmul c+2, x) 5731 if (CFP00 && !CFP01 && N1.getOpcode() == ISD::FADD && 5732 N1.getOperand(0) == N1.getOperand(1) && 5733 N0.getOperand(1) == N1.getOperand(0)) { 5734 SDValue NewCFP = DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, 5735 SDValue(CFP00, 0), 5736 DAG.getConstantFP(2.0, VT)); 5737 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 5738 N0.getOperand(1), NewCFP); 5739 } 5740 5741 // (fadd (fmul x, c), (fadd x, x)) -> (fmul c+2, x) 5742 if (CFP01 && !CFP00 && N1.getOpcode() == ISD::FADD && 5743 N1.getOperand(0) == N1.getOperand(1) && 5744 N0.getOperand(0) == N1.getOperand(0)) { 5745 SDValue NewCFP = DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, 5746 SDValue(CFP01, 0), 5747 DAG.getConstantFP(2.0, VT)); 5748 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 5749 N0.getOperand(0), NewCFP); 5750 } 5751 } 5752 5753 if (N1.getOpcode() == ISD::FMUL) { 5754 ConstantFPSDNode *CFP10 = dyn_cast<ConstantFPSDNode>(N1.getOperand(0)); 5755 ConstantFPSDNode *CFP11 = dyn_cast<ConstantFPSDNode>(N1.getOperand(1)); 5756 5757 // (fadd x, (fmul c, x)) -> (fmul c+1, x) 5758 if (CFP10 && !CFP11 && N1.getOperand(1) == N0) { 5759 SDValue NewCFP = DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, 5760 SDValue(CFP10, 0), 5761 DAG.getConstantFP(1.0, VT)); 5762 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 5763 N0, NewCFP); 5764 } 5765 5766 // (fadd x, (fmul x, c)) -> (fmul c+1, x) 5767 if (CFP11 && !CFP10 && N1.getOperand(0) == N0) { 5768 SDValue NewCFP = DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, 5769 SDValue(CFP11, 0), 5770 DAG.getConstantFP(1.0, VT)); 5771 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 5772 N0, NewCFP); 5773 } 5774 5775 // (fadd x, (fadd x, x)) -> (fmul 3.0, x) 5776 if (!CFP10 && !CFP11 && N1.getOperand(0) == N1.getOperand(1) && 5777 N1.getOperand(0) == N0) { 5778 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 5779 N0, DAG.getConstantFP(3.0, VT)); 5780 } 5781 5782 // (fadd (fadd x, x), (fmul c, x)) -> (fmul c+2, x) 5783 if (CFP10 && !CFP11 && N1.getOpcode() == ISD::FADD && 5784 N1.getOperand(0) == N1.getOperand(1) && 5785 N0.getOperand(1) == N1.getOperand(0)) { 5786 SDValue NewCFP = DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, 5787 SDValue(CFP10, 0), 5788 DAG.getConstantFP(2.0, VT)); 5789 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 5790 N0.getOperand(1), NewCFP); 5791 } 5792 5793 // (fadd (fadd x, x), (fmul x, c)) -> (fmul c+2, x) 5794 if (CFP11 && !CFP10 && N1.getOpcode() == ISD::FADD && 5795 N1.getOperand(0) == N1.getOperand(1) && 5796 N0.getOperand(0) == N1.getOperand(0)) { 5797 SDValue NewCFP = DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, 5798 SDValue(CFP11, 0), 5799 DAG.getConstantFP(2.0, VT)); 5800 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 5801 N0.getOperand(0), NewCFP); 5802 } 5803 } 5804 5805 // (fadd (fadd x, x), (fadd x, x)) -> (fmul 4.0, x) 5806 if (N0.getOpcode() == ISD::FADD && N1.getOpcode() == ISD::FADD && 5807 N0.getOperand(0) == N0.getOperand(1) && 5808 N1.getOperand(0) == N1.getOperand(1) && 5809 N0.getOperand(0) == N1.getOperand(0)) { 5810 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 5811 N0.getOperand(0), 5812 DAG.getConstantFP(4.0, VT)); 5813 } 5814 } 5815 5816 // FADD -> FMA combines: 5817 if ((DAG.getTarget().Options.AllowFPOpFusion == FPOpFusion::Fast || 5818 DAG.getTarget().Options.UnsafeFPMath) && 5819 DAG.getTarget().getTargetLowering()->isFMAFasterThanMulAndAdd(VT) && 5820 TLI.isOperationLegalOrCustom(ISD::FMA, VT)) { 5821 5822 // fold (fadd (fmul x, y), z) -> (fma x, y, z) 5823 if (N0.getOpcode() == ISD::FMUL && N0->hasOneUse()) { 5824 return DAG.getNode(ISD::FMA, N->getDebugLoc(), VT, 5825 N0.getOperand(0), N0.getOperand(1), N1); 5826 } 5827 5828 // fold (fadd x, (fmul y, z)) -> (fma y, z, x) 5829 // Note: Commutes FADD operands. 5830 if (N1.getOpcode() == ISD::FMUL && N1->hasOneUse()) { 5831 return DAG.getNode(ISD::FMA, N->getDebugLoc(), VT, 5832 N1.getOperand(0), N1.getOperand(1), N0); 5833 } 5834 } 5835 5836 return SDValue(); 5837} 5838 5839SDValue DAGCombiner::visitFSUB(SDNode *N) { 5840 SDValue N0 = N->getOperand(0); 5841 SDValue N1 = N->getOperand(1); 5842 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5843 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 5844 EVT VT = N->getValueType(0); 5845 DebugLoc dl = N->getDebugLoc(); 5846 5847 // fold vector ops 5848 if (VT.isVector()) { 5849 SDValue FoldedVOp = SimplifyVBinOp(N); 5850 if (FoldedVOp.getNode()) return FoldedVOp; 5851 } 5852 5853 // fold (fsub c1, c2) -> c1-c2 5854 if (N0CFP && N1CFP && VT != MVT::ppcf128) 5855 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, N1); 5856 // fold (fsub A, 0) -> A 5857 if (DAG.getTarget().Options.UnsafeFPMath && 5858 N1CFP && N1CFP->getValueAPF().isZero()) 5859 return N0; 5860 // fold (fsub 0, B) -> -B 5861 if (DAG.getTarget().Options.UnsafeFPMath && 5862 N0CFP && N0CFP->getValueAPF().isZero()) { 5863 if (isNegatibleForFree(N1, LegalOperations, TLI, &DAG.getTarget().Options)) 5864 return GetNegatedExpression(N1, DAG, LegalOperations); 5865 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 5866 return DAG.getNode(ISD::FNEG, dl, VT, N1); 5867 } 5868 // fold (fsub A, (fneg B)) -> (fadd A, B) 5869 if (isNegatibleForFree(N1, LegalOperations, TLI, &DAG.getTarget().Options)) 5870 return DAG.getNode(ISD::FADD, dl, VT, N0, 5871 GetNegatedExpression(N1, DAG, LegalOperations)); 5872 5873 // If 'unsafe math' is enabled, fold 5874 // (fsub x, x) -> 0.0 & 5875 // (fsub x, (fadd x, y)) -> (fneg y) & 5876 // (fsub x, (fadd y, x)) -> (fneg y) 5877 if (DAG.getTarget().Options.UnsafeFPMath) { 5878 if (N0 == N1) 5879 return DAG.getConstantFP(0.0f, VT); 5880 5881 if (N1.getOpcode() == ISD::FADD) { 5882 SDValue N10 = N1->getOperand(0); 5883 SDValue N11 = N1->getOperand(1); 5884 5885 if (N10 == N0 && isNegatibleForFree(N11, LegalOperations, TLI, 5886 &DAG.getTarget().Options)) 5887 return GetNegatedExpression(N11, DAG, LegalOperations); 5888 else if (N11 == N0 && isNegatibleForFree(N10, LegalOperations, TLI, 5889 &DAG.getTarget().Options)) 5890 return GetNegatedExpression(N10, DAG, LegalOperations); 5891 } 5892 } 5893 5894 // FSUB -> FMA combines: 5895 if ((DAG.getTarget().Options.AllowFPOpFusion == FPOpFusion::Fast || 5896 DAG.getTarget().Options.UnsafeFPMath) && 5897 DAG.getTarget().getTargetLowering()->isFMAFasterThanMulAndAdd(VT) && 5898 TLI.isOperationLegalOrCustom(ISD::FMA, VT)) { 5899 5900 // fold (fsub (fmul x, y), z) -> (fma x, y, (fneg z)) 5901 if (N0.getOpcode() == ISD::FMUL && N0->hasOneUse()) { 5902 return DAG.getNode(ISD::FMA, dl, VT, 5903 N0.getOperand(0), N0.getOperand(1), 5904 DAG.getNode(ISD::FNEG, dl, VT, N1)); 5905 } 5906 5907 // fold (fsub x, (fmul y, z)) -> (fma (fneg y), z, x) 5908 // Note: Commutes FSUB operands. 5909 if (N1.getOpcode() == ISD::FMUL && N1->hasOneUse()) { 5910 return DAG.getNode(ISD::FMA, dl, VT, 5911 DAG.getNode(ISD::FNEG, dl, VT, 5912 N1.getOperand(0)), 5913 N1.getOperand(1), N0); 5914 } 5915 5916 // fold (fsub (-(fmul, x, y)), z) -> (fma (fneg x), y, (fneg z)) 5917 if (N0.getOpcode() == ISD::FNEG && 5918 N0.getOperand(0).getOpcode() == ISD::FMUL && 5919 N0->hasOneUse() && N0.getOperand(0).hasOneUse()) { 5920 SDValue N00 = N0.getOperand(0).getOperand(0); 5921 SDValue N01 = N0.getOperand(0).getOperand(1); 5922 return DAG.getNode(ISD::FMA, dl, VT, 5923 DAG.getNode(ISD::FNEG, dl, VT, N00), N01, 5924 DAG.getNode(ISD::FNEG, dl, VT, N1)); 5925 } 5926 } 5927 5928 return SDValue(); 5929} 5930 5931SDValue DAGCombiner::visitFMUL(SDNode *N) { 5932 SDValue N0 = N->getOperand(0); 5933 SDValue N1 = N->getOperand(1); 5934 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 5935 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 5936 EVT VT = N->getValueType(0); 5937 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 5938 5939 // fold vector ops 5940 if (VT.isVector()) { 5941 SDValue FoldedVOp = SimplifyVBinOp(N); 5942 if (FoldedVOp.getNode()) return FoldedVOp; 5943 } 5944 5945 // fold (fmul c1, c2) -> c1*c2 5946 if (N0CFP && N1CFP && VT != MVT::ppcf128) 5947 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0, N1); 5948 // canonicalize constant to RHS 5949 if (N0CFP && !N1CFP) 5950 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N1, N0); 5951 // fold (fmul A, 0) -> 0 5952 if (DAG.getTarget().Options.UnsafeFPMath && 5953 N1CFP && N1CFP->getValueAPF().isZero()) 5954 return N1; 5955 // fold (fmul A, 0) -> 0, vector edition. 5956 if (DAG.getTarget().Options.UnsafeFPMath && 5957 ISD::isBuildVectorAllZeros(N1.getNode())) 5958 return N1; 5959 // fold (fmul A, 1.0) -> A 5960 if (N1CFP && N1CFP->isExactlyValue(1.0)) 5961 return N0; 5962 // fold (fmul X, 2.0) -> (fadd X, X) 5963 if (N1CFP && N1CFP->isExactlyValue(+2.0)) 5964 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N0); 5965 // fold (fmul X, -1.0) -> (fneg X) 5966 if (N1CFP && N1CFP->isExactlyValue(-1.0)) 5967 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 5968 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N0); 5969 5970 // fold (fmul (fneg X), (fneg Y)) -> (fmul X, Y) 5971 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations, TLI, 5972 &DAG.getTarget().Options)) { 5973 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations, TLI, 5974 &DAG.getTarget().Options)) { 5975 // Both can be negated for free, check to see if at least one is cheaper 5976 // negated. 5977 if (LHSNeg == 2 || RHSNeg == 2) 5978 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 5979 GetNegatedExpression(N0, DAG, LegalOperations), 5980 GetNegatedExpression(N1, DAG, LegalOperations)); 5981 } 5982 } 5983 5984 // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2)) 5985 if (DAG.getTarget().Options.UnsafeFPMath && 5986 N1CFP && N0.getOpcode() == ISD::FMUL && 5987 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 5988 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0.getOperand(0), 5989 DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 5990 N0.getOperand(1), N1)); 5991 5992 return SDValue(); 5993} 5994 5995SDValue DAGCombiner::visitFMA(SDNode *N) { 5996 SDValue N0 = N->getOperand(0); 5997 SDValue N1 = N->getOperand(1); 5998 SDValue N2 = N->getOperand(2); 5999 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6000 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 6001 EVT VT = N->getValueType(0); 6002 DebugLoc dl = N->getDebugLoc(); 6003 6004 if (N0CFP && N0CFP->isExactlyValue(1.0)) 6005 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N1, N2); 6006 if (N1CFP && N1CFP->isExactlyValue(1.0)) 6007 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N2); 6008 6009 // Canonicalize (fma c, x, y) -> (fma x, c, y) 6010 if (N0CFP && !N1CFP) 6011 return DAG.getNode(ISD::FMA, N->getDebugLoc(), VT, N1, N0, N2); 6012 6013 // (fma x, c1, (fmul x, c2)) -> (fmul x, c1+c2) 6014 if (DAG.getTarget().Options.UnsafeFPMath && N1CFP && 6015 N2.getOpcode() == ISD::FMUL && 6016 N0 == N2.getOperand(0) && 6017 N2.getOperand(1).getOpcode() == ISD::ConstantFP) { 6018 return DAG.getNode(ISD::FMUL, dl, VT, N0, 6019 DAG.getNode(ISD::FADD, dl, VT, N1, N2.getOperand(1))); 6020 } 6021 6022 6023 // (fma (fmul x, c1), c2, y) -> (fma x, c1*c2, y) 6024 if (DAG.getTarget().Options.UnsafeFPMath && 6025 N0.getOpcode() == ISD::FMUL && N1CFP && 6026 N0.getOperand(1).getOpcode() == ISD::ConstantFP) { 6027 return DAG.getNode(ISD::FMA, dl, VT, 6028 N0.getOperand(0), 6029 DAG.getNode(ISD::FMUL, dl, VT, N1, N0.getOperand(1)), 6030 N2); 6031 } 6032 6033 // (fma x, 1, y) -> (fadd x, y) 6034 // (fma x, -1, y) -> (fadd (fneg x), y) 6035 if (N1CFP) { 6036 if (N1CFP->isExactlyValue(1.0)) 6037 return DAG.getNode(ISD::FADD, dl, VT, N0, N2); 6038 6039 if (N1CFP->isExactlyValue(-1.0) && 6040 (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT))) { 6041 SDValue RHSNeg = DAG.getNode(ISD::FNEG, dl, VT, N0); 6042 AddToWorkList(RHSNeg.getNode()); 6043 return DAG.getNode(ISD::FADD, dl, VT, N2, RHSNeg); 6044 } 6045 } 6046 6047 // (fma x, c, x) -> (fmul x, (c+1)) 6048 if (DAG.getTarget().Options.UnsafeFPMath && N1CFP && N0 == N2) { 6049 return DAG.getNode(ISD::FMUL, dl, VT, 6050 N0, 6051 DAG.getNode(ISD::FADD, dl, VT, 6052 N1, DAG.getConstantFP(1.0, VT))); 6053 } 6054 6055 // (fma x, c, (fneg x)) -> (fmul x, (c-1)) 6056 if (DAG.getTarget().Options.UnsafeFPMath && N1CFP && 6057 N2.getOpcode() == ISD::FNEG && N2.getOperand(0) == N0) { 6058 return DAG.getNode(ISD::FMUL, dl, VT, 6059 N0, 6060 DAG.getNode(ISD::FADD, dl, VT, 6061 N1, DAG.getConstantFP(-1.0, VT))); 6062 } 6063 6064 6065 return SDValue(); 6066} 6067 6068SDValue DAGCombiner::visitFDIV(SDNode *N) { 6069 SDValue N0 = N->getOperand(0); 6070 SDValue N1 = N->getOperand(1); 6071 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6072 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 6073 EVT VT = N->getValueType(0); 6074 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 6075 6076 // fold vector ops 6077 if (VT.isVector()) { 6078 SDValue FoldedVOp = SimplifyVBinOp(N); 6079 if (FoldedVOp.getNode()) return FoldedVOp; 6080 } 6081 6082 // fold (fdiv c1, c2) -> c1/c2 6083 if (N0CFP && N1CFP && VT != MVT::ppcf128) 6084 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, N0, N1); 6085 6086 // fold (fdiv X, c2) -> fmul X, 1/c2 if losing precision is acceptable. 6087 if (N1CFP && VT != MVT::ppcf128 && DAG.getTarget().Options.UnsafeFPMath) { 6088 // Compute the reciprocal 1.0 / c2. 6089 APFloat N1APF = N1CFP->getValueAPF(); 6090 APFloat Recip(N1APF.getSemantics(), 1); // 1.0 6091 APFloat::opStatus st = Recip.divide(N1APF, APFloat::rmNearestTiesToEven); 6092 // Only do the transform if the reciprocal is a legal fp immediate that 6093 // isn't too nasty (eg NaN, denormal, ...). 6094 if ((st == APFloat::opOK || st == APFloat::opInexact) && // Not too nasty 6095 (!LegalOperations || 6096 // FIXME: custom lowering of ConstantFP might fail (see e.g. ARM 6097 // backend)... we should handle this gracefully after Legalize. 6098 // TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT) || 6099 TLI.isOperationLegal(llvm::ISD::ConstantFP, VT) || 6100 TLI.isFPImmLegal(Recip, VT))) 6101 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0, 6102 DAG.getConstantFP(Recip, VT)); 6103 } 6104 6105 // (fdiv (fneg X), (fneg Y)) -> (fdiv X, Y) 6106 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations, TLI, 6107 &DAG.getTarget().Options)) { 6108 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations, TLI, 6109 &DAG.getTarget().Options)) { 6110 // Both can be negated for free, check to see if at least one is cheaper 6111 // negated. 6112 if (LHSNeg == 2 || RHSNeg == 2) 6113 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, 6114 GetNegatedExpression(N0, DAG, LegalOperations), 6115 GetNegatedExpression(N1, DAG, LegalOperations)); 6116 } 6117 } 6118 6119 return SDValue(); 6120} 6121 6122SDValue DAGCombiner::visitFREM(SDNode *N) { 6123 SDValue N0 = N->getOperand(0); 6124 SDValue N1 = N->getOperand(1); 6125 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6126 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 6127 EVT VT = N->getValueType(0); 6128 6129 // fold (frem c1, c2) -> fmod(c1,c2) 6130 if (N0CFP && N1CFP && VT != MVT::ppcf128) 6131 return DAG.getNode(ISD::FREM, N->getDebugLoc(), VT, N0, N1); 6132 6133 return SDValue(); 6134} 6135 6136SDValue DAGCombiner::visitFCOPYSIGN(SDNode *N) { 6137 SDValue N0 = N->getOperand(0); 6138 SDValue N1 = N->getOperand(1); 6139 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6140 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 6141 EVT VT = N->getValueType(0); 6142 6143 if (N0CFP && N1CFP && VT != MVT::ppcf128) // Constant fold 6144 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, N0, N1); 6145 6146 if (N1CFP) { 6147 const APFloat& V = N1CFP->getValueAPF(); 6148 // copysign(x, c1) -> fabs(x) iff ispos(c1) 6149 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1) 6150 if (!V.isNegative()) { 6151 if (!LegalOperations || TLI.isOperationLegal(ISD::FABS, VT)) 6152 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 6153 } else { 6154 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 6155 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, 6156 DAG.getNode(ISD::FABS, N0.getDebugLoc(), VT, N0)); 6157 } 6158 } 6159 6160 // copysign(fabs(x), y) -> copysign(x, y) 6161 // copysign(fneg(x), y) -> copysign(x, y) 6162 // copysign(copysign(x,z), y) -> copysign(x, y) 6163 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG || 6164 N0.getOpcode() == ISD::FCOPYSIGN) 6165 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 6166 N0.getOperand(0), N1); 6167 6168 // copysign(x, abs(y)) -> abs(x) 6169 if (N1.getOpcode() == ISD::FABS) 6170 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 6171 6172 // copysign(x, copysign(y,z)) -> copysign(x, z) 6173 if (N1.getOpcode() == ISD::FCOPYSIGN) 6174 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 6175 N0, N1.getOperand(1)); 6176 6177 // copysign(x, fp_extend(y)) -> copysign(x, y) 6178 // copysign(x, fp_round(y)) -> copysign(x, y) 6179 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND) 6180 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 6181 N0, N1.getOperand(0)); 6182 6183 return SDValue(); 6184} 6185 6186SDValue DAGCombiner::visitSINT_TO_FP(SDNode *N) { 6187 SDValue N0 = N->getOperand(0); 6188 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 6189 EVT VT = N->getValueType(0); 6190 EVT OpVT = N0.getValueType(); 6191 6192 // fold (sint_to_fp c1) -> c1fp 6193 if (N0C && OpVT != MVT::ppcf128 && 6194 // ...but only if the target supports immediate floating-point values 6195 (!LegalOperations || 6196 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT))) 6197 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0); 6198 6199 // If the input is a legal type, and SINT_TO_FP is not legal on this target, 6200 // but UINT_TO_FP is legal on this target, try to convert. 6201 if (!TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT) && 6202 TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT)) { 6203 // If the sign bit is known to be zero, we can change this to UINT_TO_FP. 6204 if (DAG.SignBitIsZero(N0)) 6205 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0); 6206 } 6207 6208 // The next optimizations are desireable only if SELECT_CC can be lowered. 6209 // Check against MVT::Other for SELECT_CC, which is a workaround for targets 6210 // having to say they don't support SELECT_CC on every type the DAG knows 6211 // about, since there is no way to mark an opcode illegal at all value types 6212 // (See also visitSELECT) 6213 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other)) { 6214 // fold (sint_to_fp (setcc x, y, cc)) -> (select_cc x, y, -1.0, 0.0,, cc) 6215 if (N0.getOpcode() == ISD::SETCC && N0.getValueType() == MVT::i1 && 6216 !VT.isVector() && 6217 (!LegalOperations || 6218 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT))) { 6219 SDValue Ops[] = 6220 { N0.getOperand(0), N0.getOperand(1), 6221 DAG.getConstantFP(-1.0, VT) , DAG.getConstantFP(0.0, VT), 6222 N0.getOperand(2) }; 6223 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT, Ops, 5); 6224 } 6225 6226 // fold (sint_to_fp (zext (setcc x, y, cc))) -> 6227 // (select_cc x, y, 1.0, 0.0,, cc) 6228 if (N0.getOpcode() == ISD::ZERO_EXTEND && 6229 N0.getOperand(0).getOpcode() == ISD::SETCC &&!VT.isVector() && 6230 (!LegalOperations || 6231 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT))) { 6232 SDValue Ops[] = 6233 { N0.getOperand(0).getOperand(0), N0.getOperand(0).getOperand(1), 6234 DAG.getConstantFP(1.0, VT) , DAG.getConstantFP(0.0, VT), 6235 N0.getOperand(0).getOperand(2) }; 6236 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT, Ops, 5); 6237 } 6238 } 6239 6240 return SDValue(); 6241} 6242 6243SDValue DAGCombiner::visitUINT_TO_FP(SDNode *N) { 6244 SDValue N0 = N->getOperand(0); 6245 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 6246 EVT VT = N->getValueType(0); 6247 EVT OpVT = N0.getValueType(); 6248 6249 // fold (uint_to_fp c1) -> c1fp 6250 if (N0C && OpVT != MVT::ppcf128 && 6251 // ...but only if the target supports immediate floating-point values 6252 (!LegalOperations || 6253 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT))) 6254 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0); 6255 6256 // If the input is a legal type, and UINT_TO_FP is not legal on this target, 6257 // but SINT_TO_FP is legal on this target, try to convert. 6258 if (!TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT) && 6259 TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT)) { 6260 // If the sign bit is known to be zero, we can change this to SINT_TO_FP. 6261 if (DAG.SignBitIsZero(N0)) 6262 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0); 6263 } 6264 6265 // The next optimizations are desireable only if SELECT_CC can be lowered. 6266 // Check against MVT::Other for SELECT_CC, which is a workaround for targets 6267 // having to say they don't support SELECT_CC on every type the DAG knows 6268 // about, since there is no way to mark an opcode illegal at all value types 6269 // (See also visitSELECT) 6270 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other)) { 6271 // fold (uint_to_fp (setcc x, y, cc)) -> (select_cc x, y, -1.0, 0.0,, cc) 6272 6273 if (N0.getOpcode() == ISD::SETCC && !VT.isVector() && 6274 (!LegalOperations || 6275 TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT))) { 6276 SDValue Ops[] = 6277 { N0.getOperand(0), N0.getOperand(1), 6278 DAG.getConstantFP(1.0, VT), DAG.getConstantFP(0.0, VT), 6279 N0.getOperand(2) }; 6280 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT, Ops, 5); 6281 } 6282 } 6283 6284 return SDValue(); 6285} 6286 6287SDValue DAGCombiner::visitFP_TO_SINT(SDNode *N) { 6288 SDValue N0 = N->getOperand(0); 6289 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6290 EVT VT = N->getValueType(0); 6291 6292 // fold (fp_to_sint c1fp) -> c1 6293 if (N0CFP) 6294 return DAG.getNode(ISD::FP_TO_SINT, N->getDebugLoc(), VT, N0); 6295 6296 return SDValue(); 6297} 6298 6299SDValue DAGCombiner::visitFP_TO_UINT(SDNode *N) { 6300 SDValue N0 = N->getOperand(0); 6301 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6302 EVT VT = N->getValueType(0); 6303 6304 // fold (fp_to_uint c1fp) -> c1 6305 if (N0CFP && VT != MVT::ppcf128) 6306 return DAG.getNode(ISD::FP_TO_UINT, N->getDebugLoc(), VT, N0); 6307 6308 return SDValue(); 6309} 6310 6311SDValue DAGCombiner::visitFP_ROUND(SDNode *N) { 6312 SDValue N0 = N->getOperand(0); 6313 SDValue N1 = N->getOperand(1); 6314 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6315 EVT VT = N->getValueType(0); 6316 6317 // fold (fp_round c1fp) -> c1fp 6318 if (N0CFP && N0.getValueType() != MVT::ppcf128) 6319 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0, N1); 6320 6321 // fold (fp_round (fp_extend x)) -> x 6322 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType()) 6323 return N0.getOperand(0); 6324 6325 // fold (fp_round (fp_round x)) -> (fp_round x) 6326 if (N0.getOpcode() == ISD::FP_ROUND) { 6327 // This is a value preserving truncation if both round's are. 6328 bool IsTrunc = N->getConstantOperandVal(1) == 1 && 6329 N0.getNode()->getConstantOperandVal(1) == 1; 6330 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0.getOperand(0), 6331 DAG.getIntPtrConstant(IsTrunc)); 6332 } 6333 6334 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y) 6335 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse()) { 6336 SDValue Tmp = DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(), VT, 6337 N0.getOperand(0), N1); 6338 AddToWorkList(Tmp.getNode()); 6339 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 6340 Tmp, N0.getOperand(1)); 6341 } 6342 6343 return SDValue(); 6344} 6345 6346SDValue DAGCombiner::visitFP_ROUND_INREG(SDNode *N) { 6347 SDValue N0 = N->getOperand(0); 6348 EVT VT = N->getValueType(0); 6349 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 6350 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6351 6352 // fold (fp_round_inreg c1fp) -> c1fp 6353 if (N0CFP && isTypeLegal(EVT)) { 6354 SDValue Round = DAG.getConstantFP(*N0CFP->getConstantFPValue(), EVT); 6355 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, Round); 6356 } 6357 6358 return SDValue(); 6359} 6360 6361SDValue DAGCombiner::visitFP_EXTEND(SDNode *N) { 6362 SDValue N0 = N->getOperand(0); 6363 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6364 EVT VT = N->getValueType(0); 6365 6366 // If this is fp_round(fpextend), don't fold it, allow ourselves to be folded. 6367 if (N->hasOneUse() && 6368 N->use_begin()->getOpcode() == ISD::FP_ROUND) 6369 return SDValue(); 6370 6371 // fold (fp_extend c1fp) -> c1fp 6372 if (N0CFP && VT != MVT::ppcf128) 6373 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, N0); 6374 6375 // Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't affect the 6376 // value of X. 6377 if (N0.getOpcode() == ISD::FP_ROUND 6378 && N0.getNode()->getConstantOperandVal(1) == 1) { 6379 SDValue In = N0.getOperand(0); 6380 if (In.getValueType() == VT) return In; 6381 if (VT.bitsLT(In.getValueType())) 6382 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, 6383 In, N0.getOperand(1)); 6384 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, In); 6385 } 6386 6387 // fold (fpext (load x)) -> (fpext (fptrunc (extload x))) 6388 if (ISD::isNON_EXTLoad(N0.getNode()) && N0.hasOneUse() && 6389 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 6390 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) { 6391 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 6392 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT, 6393 LN0->getChain(), 6394 LN0->getBasePtr(), LN0->getPointerInfo(), 6395 N0.getValueType(), 6396 LN0->isVolatile(), LN0->isNonTemporal(), 6397 LN0->getAlignment()); 6398 CombineTo(N, ExtLoad); 6399 CombineTo(N0.getNode(), 6400 DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(), 6401 N0.getValueType(), ExtLoad, DAG.getIntPtrConstant(1)), 6402 ExtLoad.getValue(1)); 6403 return SDValue(N, 0); // Return N so it doesn't get rechecked! 6404 } 6405 6406 return SDValue(); 6407} 6408 6409SDValue DAGCombiner::visitFNEG(SDNode *N) { 6410 SDValue N0 = N->getOperand(0); 6411 EVT VT = N->getValueType(0); 6412 6413 if (VT.isVector()) { 6414 SDValue FoldedVOp = SimplifyVUnaryOp(N); 6415 if (FoldedVOp.getNode()) return FoldedVOp; 6416 } 6417 6418 if (isNegatibleForFree(N0, LegalOperations, DAG.getTargetLoweringInfo(), 6419 &DAG.getTarget().Options)) 6420 return GetNegatedExpression(N0, DAG, LegalOperations); 6421 6422 // Transform fneg(bitconvert(x)) -> bitconvert(x^sign) to avoid loading 6423 // constant pool values. 6424 if (!TLI.isFNegFree(VT) && N0.getOpcode() == ISD::BITCAST && 6425 !VT.isVector() && 6426 N0.getNode()->hasOneUse() && 6427 N0.getOperand(0).getValueType().isInteger()) { 6428 SDValue Int = N0.getOperand(0); 6429 EVT IntVT = Int.getValueType(); 6430 if (IntVT.isInteger() && !IntVT.isVector()) { 6431 Int = DAG.getNode(ISD::XOR, N0.getDebugLoc(), IntVT, Int, 6432 DAG.getConstant(APInt::getSignBit(IntVT.getSizeInBits()), IntVT)); 6433 AddToWorkList(Int.getNode()); 6434 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), 6435 VT, Int); 6436 } 6437 } 6438 6439 // (fneg (fmul c, x)) -> (fmul -c, x) 6440 if (N0.getOpcode() == ISD::FMUL) { 6441 ConstantFPSDNode *CFP1 = dyn_cast<ConstantFPSDNode>(N0.getOperand(1)); 6442 if (CFP1) { 6443 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 6444 N0.getOperand(0), 6445 DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, 6446 N0.getOperand(1))); 6447 } 6448 } 6449 6450 return SDValue(); 6451} 6452 6453SDValue DAGCombiner::visitFCEIL(SDNode *N) { 6454 SDValue N0 = N->getOperand(0); 6455 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6456 EVT VT = N->getValueType(0); 6457 6458 // fold (fceil c1) -> fceil(c1) 6459 if (N0CFP && VT != MVT::ppcf128) 6460 return DAG.getNode(ISD::FCEIL, N->getDebugLoc(), VT, N0); 6461 6462 return SDValue(); 6463} 6464 6465SDValue DAGCombiner::visitFTRUNC(SDNode *N) { 6466 SDValue N0 = N->getOperand(0); 6467 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6468 EVT VT = N->getValueType(0); 6469 6470 // fold (ftrunc c1) -> ftrunc(c1) 6471 if (N0CFP && VT != MVT::ppcf128) 6472 return DAG.getNode(ISD::FTRUNC, N->getDebugLoc(), VT, N0); 6473 6474 return SDValue(); 6475} 6476 6477SDValue DAGCombiner::visitFFLOOR(SDNode *N) { 6478 SDValue N0 = N->getOperand(0); 6479 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6480 EVT VT = N->getValueType(0); 6481 6482 // fold (ffloor c1) -> ffloor(c1) 6483 if (N0CFP && VT != MVT::ppcf128) 6484 return DAG.getNode(ISD::FFLOOR, N->getDebugLoc(), VT, N0); 6485 6486 return SDValue(); 6487} 6488 6489SDValue DAGCombiner::visitFABS(SDNode *N) { 6490 SDValue N0 = N->getOperand(0); 6491 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 6492 EVT VT = N->getValueType(0); 6493 6494 if (VT.isVector()) { 6495 SDValue FoldedVOp = SimplifyVUnaryOp(N); 6496 if (FoldedVOp.getNode()) return FoldedVOp; 6497 } 6498 6499 // fold (fabs c1) -> fabs(c1) 6500 if (N0CFP && VT != MVT::ppcf128) 6501 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 6502 // fold (fabs (fabs x)) -> (fabs x) 6503 if (N0.getOpcode() == ISD::FABS) 6504 return N->getOperand(0); 6505 // fold (fabs (fneg x)) -> (fabs x) 6506 // fold (fabs (fcopysign x, y)) -> (fabs x) 6507 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN) 6508 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0.getOperand(0)); 6509 6510 // Transform fabs(bitconvert(x)) -> bitconvert(x&~sign) to avoid loading 6511 // constant pool values. 6512 if (!TLI.isFAbsFree(VT) && 6513 N0.getOpcode() == ISD::BITCAST && N0.getNode()->hasOneUse() && 6514 N0.getOperand(0).getValueType().isInteger() && 6515 !N0.getOperand(0).getValueType().isVector()) { 6516 SDValue Int = N0.getOperand(0); 6517 EVT IntVT = Int.getValueType(); 6518 if (IntVT.isInteger() && !IntVT.isVector()) { 6519 Int = DAG.getNode(ISD::AND, N0.getDebugLoc(), IntVT, Int, 6520 DAG.getConstant(~APInt::getSignBit(IntVT.getSizeInBits()), IntVT)); 6521 AddToWorkList(Int.getNode()); 6522 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), 6523 N->getValueType(0), Int); 6524 } 6525 } 6526 6527 return SDValue(); 6528} 6529 6530SDValue DAGCombiner::visitBRCOND(SDNode *N) { 6531 SDValue Chain = N->getOperand(0); 6532 SDValue N1 = N->getOperand(1); 6533 SDValue N2 = N->getOperand(2); 6534 6535 // If N is a constant we could fold this into a fallthrough or unconditional 6536 // branch. However that doesn't happen very often in normal code, because 6537 // Instcombine/SimplifyCFG should have handled the available opportunities. 6538 // If we did this folding here, it would be necessary to update the 6539 // MachineBasicBlock CFG, which is awkward. 6540 6541 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal 6542 // on the target. 6543 if (N1.getOpcode() == ISD::SETCC && 6544 TLI.isOperationLegalOrCustom(ISD::BR_CC, MVT::Other)) { 6545 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other, 6546 Chain, N1.getOperand(2), 6547 N1.getOperand(0), N1.getOperand(1), N2); 6548 } 6549 6550 if ((N1.hasOneUse() && N1.getOpcode() == ISD::SRL) || 6551 ((N1.getOpcode() == ISD::TRUNCATE && N1.hasOneUse()) && 6552 (N1.getOperand(0).hasOneUse() && 6553 N1.getOperand(0).getOpcode() == ISD::SRL))) { 6554 SDNode *Trunc = 0; 6555 if (N1.getOpcode() == ISD::TRUNCATE) { 6556 // Look pass the truncate. 6557 Trunc = N1.getNode(); 6558 N1 = N1.getOperand(0); 6559 } 6560 6561 // Match this pattern so that we can generate simpler code: 6562 // 6563 // %a = ... 6564 // %b = and i32 %a, 2 6565 // %c = srl i32 %b, 1 6566 // brcond i32 %c ... 6567 // 6568 // into 6569 // 6570 // %a = ... 6571 // %b = and i32 %a, 2 6572 // %c = setcc eq %b, 0 6573 // brcond %c ... 6574 // 6575 // This applies only when the AND constant value has one bit set and the 6576 // SRL constant is equal to the log2 of the AND constant. The back-end is 6577 // smart enough to convert the result into a TEST/JMP sequence. 6578 SDValue Op0 = N1.getOperand(0); 6579 SDValue Op1 = N1.getOperand(1); 6580 6581 if (Op0.getOpcode() == ISD::AND && 6582 Op1.getOpcode() == ISD::Constant) { 6583 SDValue AndOp1 = Op0.getOperand(1); 6584 6585 if (AndOp1.getOpcode() == ISD::Constant) { 6586 const APInt &AndConst = cast<ConstantSDNode>(AndOp1)->getAPIntValue(); 6587 6588 if (AndConst.isPowerOf2() && 6589 cast<ConstantSDNode>(Op1)->getAPIntValue()==AndConst.logBase2()) { 6590 SDValue SetCC = 6591 DAG.getSetCC(N->getDebugLoc(), 6592 TLI.getSetCCResultType(Op0.getValueType()), 6593 Op0, DAG.getConstant(0, Op0.getValueType()), 6594 ISD::SETNE); 6595 6596 SDValue NewBRCond = DAG.getNode(ISD::BRCOND, N->getDebugLoc(), 6597 MVT::Other, Chain, SetCC, N2); 6598 // Don't add the new BRCond into the worklist or else SimplifySelectCC 6599 // will convert it back to (X & C1) >> C2. 6600 CombineTo(N, NewBRCond, false); 6601 // Truncate is dead. 6602 if (Trunc) { 6603 removeFromWorkList(Trunc); 6604 DAG.DeleteNode(Trunc); 6605 } 6606 // Replace the uses of SRL with SETCC 6607 WorkListRemover DeadNodes(*this); 6608 DAG.ReplaceAllUsesOfValueWith(N1, SetCC); 6609 removeFromWorkList(N1.getNode()); 6610 DAG.DeleteNode(N1.getNode()); 6611 return SDValue(N, 0); // Return N so it doesn't get rechecked! 6612 } 6613 } 6614 } 6615 6616 if (Trunc) 6617 // Restore N1 if the above transformation doesn't match. 6618 N1 = N->getOperand(1); 6619 } 6620 6621 // Transform br(xor(x, y)) -> br(x != y) 6622 // Transform br(xor(xor(x,y), 1)) -> br (x == y) 6623 if (N1.hasOneUse() && N1.getOpcode() == ISD::XOR) { 6624 SDNode *TheXor = N1.getNode(); 6625 SDValue Op0 = TheXor->getOperand(0); 6626 SDValue Op1 = TheXor->getOperand(1); 6627 if (Op0.getOpcode() == Op1.getOpcode()) { 6628 // Avoid missing important xor optimizations. 6629 SDValue Tmp = visitXOR(TheXor); 6630 if (Tmp.getNode() && Tmp.getNode() != TheXor) { 6631 DEBUG(dbgs() << "\nReplacing.8 "; 6632 TheXor->dump(&DAG); 6633 dbgs() << "\nWith: "; 6634 Tmp.getNode()->dump(&DAG); 6635 dbgs() << '\n'); 6636 WorkListRemover DeadNodes(*this); 6637 DAG.ReplaceAllUsesOfValueWith(N1, Tmp); 6638 removeFromWorkList(TheXor); 6639 DAG.DeleteNode(TheXor); 6640 return DAG.getNode(ISD::BRCOND, N->getDebugLoc(), 6641 MVT::Other, Chain, Tmp, N2); 6642 } 6643 } 6644 6645 if (Op0.getOpcode() != ISD::SETCC && Op1.getOpcode() != ISD::SETCC) { 6646 bool Equal = false; 6647 if (ConstantSDNode *RHSCI = dyn_cast<ConstantSDNode>(Op0)) 6648 if (RHSCI->getAPIntValue() == 1 && Op0.hasOneUse() && 6649 Op0.getOpcode() == ISD::XOR) { 6650 TheXor = Op0.getNode(); 6651 Equal = true; 6652 } 6653 6654 EVT SetCCVT = N1.getValueType(); 6655 if (LegalTypes) 6656 SetCCVT = TLI.getSetCCResultType(SetCCVT); 6657 SDValue SetCC = DAG.getSetCC(TheXor->getDebugLoc(), 6658 SetCCVT, 6659 Op0, Op1, 6660 Equal ? ISD::SETEQ : ISD::SETNE); 6661 // Replace the uses of XOR with SETCC 6662 WorkListRemover DeadNodes(*this); 6663 DAG.ReplaceAllUsesOfValueWith(N1, SetCC); 6664 removeFromWorkList(N1.getNode()); 6665 DAG.DeleteNode(N1.getNode()); 6666 return DAG.getNode(ISD::BRCOND, N->getDebugLoc(), 6667 MVT::Other, Chain, SetCC, N2); 6668 } 6669 } 6670 6671 return SDValue(); 6672} 6673 6674// Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB. 6675// 6676SDValue DAGCombiner::visitBR_CC(SDNode *N) { 6677 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1)); 6678 SDValue CondLHS = N->getOperand(2), CondRHS = N->getOperand(3); 6679 6680 // If N is a constant we could fold this into a fallthrough or unconditional 6681 // branch. However that doesn't happen very often in normal code, because 6682 // Instcombine/SimplifyCFG should have handled the available opportunities. 6683 // If we did this folding here, it would be necessary to update the 6684 // MachineBasicBlock CFG, which is awkward. 6685 6686 // Use SimplifySetCC to simplify SETCC's. 6687 SDValue Simp = SimplifySetCC(TLI.getSetCCResultType(CondLHS.getValueType()), 6688 CondLHS, CondRHS, CC->get(), N->getDebugLoc(), 6689 false); 6690 if (Simp.getNode()) AddToWorkList(Simp.getNode()); 6691 6692 // fold to a simpler setcc 6693 if (Simp.getNode() && Simp.getOpcode() == ISD::SETCC) 6694 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other, 6695 N->getOperand(0), Simp.getOperand(2), 6696 Simp.getOperand(0), Simp.getOperand(1), 6697 N->getOperand(4)); 6698 6699 return SDValue(); 6700} 6701 6702/// canFoldInAddressingMode - Return true if 'Use' is a load or a store that 6703/// uses N as its base pointer and that N may be folded in the load / store 6704/// addressing mode. 6705static bool canFoldInAddressingMode(SDNode *N, SDNode *Use, 6706 SelectionDAG &DAG, 6707 const TargetLowering &TLI) { 6708 EVT VT; 6709 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Use)) { 6710 if (LD->isIndexed() || LD->getBasePtr().getNode() != N) 6711 return false; 6712 VT = Use->getValueType(0); 6713 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(Use)) { 6714 if (ST->isIndexed() || ST->getBasePtr().getNode() != N) 6715 return false; 6716 VT = ST->getValue().getValueType(); 6717 } else 6718 return false; 6719 6720 TargetLowering::AddrMode AM; 6721 if (N->getOpcode() == ISD::ADD) { 6722 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1)); 6723 if (Offset) 6724 // [reg +/- imm] 6725 AM.BaseOffs = Offset->getSExtValue(); 6726 else 6727 // [reg +/- reg] 6728 AM.Scale = 1; 6729 } else if (N->getOpcode() == ISD::SUB) { 6730 ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1)); 6731 if (Offset) 6732 // [reg +/- imm] 6733 AM.BaseOffs = -Offset->getSExtValue(); 6734 else 6735 // [reg +/- reg] 6736 AM.Scale = 1; 6737 } else 6738 return false; 6739 6740 return TLI.isLegalAddressingMode(AM, VT.getTypeForEVT(*DAG.getContext())); 6741} 6742 6743/// CombineToPreIndexedLoadStore - Try turning a load / store into a 6744/// pre-indexed load / store when the base pointer is an add or subtract 6745/// and it has other uses besides the load / store. After the 6746/// transformation, the new indexed load / store has effectively folded 6747/// the add / subtract in and all of its other uses are redirected to the 6748/// new load / store. 6749bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) { 6750 if (Level < AfterLegalizeDAG) 6751 return false; 6752 6753 bool isLoad = true; 6754 SDValue Ptr; 6755 EVT VT; 6756 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 6757 if (LD->isIndexed()) 6758 return false; 6759 VT = LD->getMemoryVT(); 6760 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) && 6761 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT)) 6762 return false; 6763 Ptr = LD->getBasePtr(); 6764 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 6765 if (ST->isIndexed()) 6766 return false; 6767 VT = ST->getMemoryVT(); 6768 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) && 6769 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT)) 6770 return false; 6771 Ptr = ST->getBasePtr(); 6772 isLoad = false; 6773 } else { 6774 return false; 6775 } 6776 6777 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail 6778 // out. There is no reason to make this a preinc/predec. 6779 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) || 6780 Ptr.getNode()->hasOneUse()) 6781 return false; 6782 6783 // Ask the target to do addressing mode selection. 6784 SDValue BasePtr; 6785 SDValue Offset; 6786 ISD::MemIndexedMode AM = ISD::UNINDEXED; 6787 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG)) 6788 return false; 6789 // Don't create a indexed load / store with zero offset. 6790 if (isa<ConstantSDNode>(Offset) && 6791 cast<ConstantSDNode>(Offset)->isNullValue()) 6792 return false; 6793 6794 // Try turning it into a pre-indexed load / store except when: 6795 // 1) The new base ptr is a frame index. 6796 // 2) If N is a store and the new base ptr is either the same as or is a 6797 // predecessor of the value being stored. 6798 // 3) Another use of old base ptr is a predecessor of N. If ptr is folded 6799 // that would create a cycle. 6800 // 4) All uses are load / store ops that use it as old base ptr. 6801 6802 // Check #1. Preinc'ing a frame index would require copying the stack pointer 6803 // (plus the implicit offset) to a register to preinc anyway. 6804 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr)) 6805 return false; 6806 6807 // Check #2. 6808 if (!isLoad) { 6809 SDValue Val = cast<StoreSDNode>(N)->getValue(); 6810 if (Val == BasePtr || BasePtr.getNode()->isPredecessorOf(Val.getNode())) 6811 return false; 6812 } 6813 6814 // Now check for #3 and #4. 6815 bool RealUse = false; 6816 6817 // Caches for hasPredecessorHelper 6818 SmallPtrSet<const SDNode *, 32> Visited; 6819 SmallVector<const SDNode *, 16> Worklist; 6820 6821 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(), 6822 E = Ptr.getNode()->use_end(); I != E; ++I) { 6823 SDNode *Use = *I; 6824 if (Use == N) 6825 continue; 6826 if (N->hasPredecessorHelper(Use, Visited, Worklist)) 6827 return false; 6828 6829 // If Ptr may be folded in addressing mode of other use, then it's 6830 // not profitable to do this transformation. 6831 if (!canFoldInAddressingMode(Ptr.getNode(), Use, DAG, TLI)) 6832 RealUse = true; 6833 } 6834 6835 if (!RealUse) 6836 return false; 6837 6838 SDValue Result; 6839 if (isLoad) 6840 Result = DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(), 6841 BasePtr, Offset, AM); 6842 else 6843 Result = DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(), 6844 BasePtr, Offset, AM); 6845 ++PreIndexedNodes; 6846 ++NodesCombined; 6847 DEBUG(dbgs() << "\nReplacing.4 "; 6848 N->dump(&DAG); 6849 dbgs() << "\nWith: "; 6850 Result.getNode()->dump(&DAG); 6851 dbgs() << '\n'); 6852 WorkListRemover DeadNodes(*this); 6853 if (isLoad) { 6854 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0)); 6855 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2)); 6856 } else { 6857 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1)); 6858 } 6859 6860 // Finally, since the node is now dead, remove it from the graph. 6861 DAG.DeleteNode(N); 6862 6863 // Replace the uses of Ptr with uses of the updated base value. 6864 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0)); 6865 removeFromWorkList(Ptr.getNode()); 6866 DAG.DeleteNode(Ptr.getNode()); 6867 6868 return true; 6869} 6870 6871/// CombineToPostIndexedLoadStore - Try to combine a load / store with a 6872/// add / sub of the base pointer node into a post-indexed load / store. 6873/// The transformation folded the add / subtract into the new indexed 6874/// load / store effectively and all of its uses are redirected to the 6875/// new load / store. 6876bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) { 6877 if (Level < AfterLegalizeDAG) 6878 return false; 6879 6880 bool isLoad = true; 6881 SDValue Ptr; 6882 EVT VT; 6883 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 6884 if (LD->isIndexed()) 6885 return false; 6886 VT = LD->getMemoryVT(); 6887 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) && 6888 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT)) 6889 return false; 6890 Ptr = LD->getBasePtr(); 6891 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 6892 if (ST->isIndexed()) 6893 return false; 6894 VT = ST->getMemoryVT(); 6895 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) && 6896 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT)) 6897 return false; 6898 Ptr = ST->getBasePtr(); 6899 isLoad = false; 6900 } else { 6901 return false; 6902 } 6903 6904 if (Ptr.getNode()->hasOneUse()) 6905 return false; 6906 6907 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(), 6908 E = Ptr.getNode()->use_end(); I != E; ++I) { 6909 SDNode *Op = *I; 6910 if (Op == N || 6911 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB)) 6912 continue; 6913 6914 SDValue BasePtr; 6915 SDValue Offset; 6916 ISD::MemIndexedMode AM = ISD::UNINDEXED; 6917 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) { 6918 // Don't create a indexed load / store with zero offset. 6919 if (isa<ConstantSDNode>(Offset) && 6920 cast<ConstantSDNode>(Offset)->isNullValue()) 6921 continue; 6922 6923 // Try turning it into a post-indexed load / store except when 6924 // 1) All uses are load / store ops that use it as base ptr (and 6925 // it may be folded as addressing mmode). 6926 // 2) Op must be independent of N, i.e. Op is neither a predecessor 6927 // nor a successor of N. Otherwise, if Op is folded that would 6928 // create a cycle. 6929 6930 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr)) 6931 continue; 6932 6933 // Check for #1. 6934 bool TryNext = false; 6935 for (SDNode::use_iterator II = BasePtr.getNode()->use_begin(), 6936 EE = BasePtr.getNode()->use_end(); II != EE; ++II) { 6937 SDNode *Use = *II; 6938 if (Use == Ptr.getNode()) 6939 continue; 6940 6941 // If all the uses are load / store addresses, then don't do the 6942 // transformation. 6943 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){ 6944 bool RealUse = false; 6945 for (SDNode::use_iterator III = Use->use_begin(), 6946 EEE = Use->use_end(); III != EEE; ++III) { 6947 SDNode *UseUse = *III; 6948 if (!canFoldInAddressingMode(Use, UseUse, DAG, TLI)) 6949 RealUse = true; 6950 } 6951 6952 if (!RealUse) { 6953 TryNext = true; 6954 break; 6955 } 6956 } 6957 } 6958 6959 if (TryNext) 6960 continue; 6961 6962 // Check for #2 6963 if (!Op->isPredecessorOf(N) && !N->isPredecessorOf(Op)) { 6964 SDValue Result = isLoad 6965 ? DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(), 6966 BasePtr, Offset, AM) 6967 : DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(), 6968 BasePtr, Offset, AM); 6969 ++PostIndexedNodes; 6970 ++NodesCombined; 6971 DEBUG(dbgs() << "\nReplacing.5 "; 6972 N->dump(&DAG); 6973 dbgs() << "\nWith: "; 6974 Result.getNode()->dump(&DAG); 6975 dbgs() << '\n'); 6976 WorkListRemover DeadNodes(*this); 6977 if (isLoad) { 6978 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0)); 6979 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2)); 6980 } else { 6981 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1)); 6982 } 6983 6984 // Finally, since the node is now dead, remove it from the graph. 6985 DAG.DeleteNode(N); 6986 6987 // Replace the uses of Use with uses of the updated base value. 6988 DAG.ReplaceAllUsesOfValueWith(SDValue(Op, 0), 6989 Result.getValue(isLoad ? 1 : 0)); 6990 removeFromWorkList(Op); 6991 DAG.DeleteNode(Op); 6992 return true; 6993 } 6994 } 6995 } 6996 6997 return false; 6998} 6999 7000SDValue DAGCombiner::visitLOAD(SDNode *N) { 7001 LoadSDNode *LD = cast<LoadSDNode>(N); 7002 SDValue Chain = LD->getChain(); 7003 SDValue Ptr = LD->getBasePtr(); 7004 7005 // If load is not volatile and there are no uses of the loaded value (and 7006 // the updated indexed value in case of indexed loads), change uses of the 7007 // chain value into uses of the chain input (i.e. delete the dead load). 7008 if (!LD->isVolatile()) { 7009 if (N->getValueType(1) == MVT::Other) { 7010 // Unindexed loads. 7011 if (!N->hasAnyUseOfValue(0)) { 7012 // It's not safe to use the two value CombineTo variant here. e.g. 7013 // v1, chain2 = load chain1, loc 7014 // v2, chain3 = load chain2, loc 7015 // v3 = add v2, c 7016 // Now we replace use of chain2 with chain1. This makes the second load 7017 // isomorphic to the one we are deleting, and thus makes this load live. 7018 DEBUG(dbgs() << "\nReplacing.6 "; 7019 N->dump(&DAG); 7020 dbgs() << "\nWith chain: "; 7021 Chain.getNode()->dump(&DAG); 7022 dbgs() << "\n"); 7023 WorkListRemover DeadNodes(*this); 7024 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Chain); 7025 7026 if (N->use_empty()) { 7027 removeFromWorkList(N); 7028 DAG.DeleteNode(N); 7029 } 7030 7031 return SDValue(N, 0); // Return N so it doesn't get rechecked! 7032 } 7033 } else { 7034 // Indexed loads. 7035 assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?"); 7036 if (!N->hasAnyUseOfValue(0) && !N->hasAnyUseOfValue(1)) { 7037 SDValue Undef = DAG.getUNDEF(N->getValueType(0)); 7038 DEBUG(dbgs() << "\nReplacing.7 "; 7039 N->dump(&DAG); 7040 dbgs() << "\nWith: "; 7041 Undef.getNode()->dump(&DAG); 7042 dbgs() << " and 2 other values\n"); 7043 WorkListRemover DeadNodes(*this); 7044 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Undef); 7045 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), 7046 DAG.getUNDEF(N->getValueType(1))); 7047 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 2), Chain); 7048 removeFromWorkList(N); 7049 DAG.DeleteNode(N); 7050 return SDValue(N, 0); // Return N so it doesn't get rechecked! 7051 } 7052 } 7053 } 7054 7055 // If this load is directly stored, replace the load value with the stored 7056 // value. 7057 // TODO: Handle store large -> read small portion. 7058 // TODO: Handle TRUNCSTORE/LOADEXT 7059 if (ISD::isNormalLoad(N) && !LD->isVolatile()) { 7060 if (ISD::isNON_TRUNCStore(Chain.getNode())) { 7061 StoreSDNode *PrevST = cast<StoreSDNode>(Chain); 7062 if (PrevST->getBasePtr() == Ptr && 7063 PrevST->getValue().getValueType() == N->getValueType(0)) 7064 return CombineTo(N, Chain.getOperand(1), Chain); 7065 } 7066 } 7067 7068 // Try to infer better alignment information than the load already has. 7069 if (OptLevel != CodeGenOpt::None && LD->isUnindexed()) { 7070 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) { 7071 if (Align > LD->getAlignment()) 7072 return DAG.getExtLoad(LD->getExtensionType(), N->getDebugLoc(), 7073 LD->getValueType(0), 7074 Chain, Ptr, LD->getPointerInfo(), 7075 LD->getMemoryVT(), 7076 LD->isVolatile(), LD->isNonTemporal(), Align); 7077 } 7078 } 7079 7080 if (CombinerAA) { 7081 // Walk up chain skipping non-aliasing memory nodes. 7082 SDValue BetterChain = FindBetterChain(N, Chain); 7083 7084 // If there is a better chain. 7085 if (Chain != BetterChain) { 7086 SDValue ReplLoad; 7087 7088 // Replace the chain to void dependency. 7089 if (LD->getExtensionType() == ISD::NON_EXTLOAD) { 7090 ReplLoad = DAG.getLoad(N->getValueType(0), LD->getDebugLoc(), 7091 BetterChain, Ptr, LD->getPointerInfo(), 7092 LD->isVolatile(), LD->isNonTemporal(), 7093 LD->isInvariant(), LD->getAlignment()); 7094 } else { 7095 ReplLoad = DAG.getExtLoad(LD->getExtensionType(), LD->getDebugLoc(), 7096 LD->getValueType(0), 7097 BetterChain, Ptr, LD->getPointerInfo(), 7098 LD->getMemoryVT(), 7099 LD->isVolatile(), 7100 LD->isNonTemporal(), 7101 LD->getAlignment()); 7102 } 7103 7104 // Create token factor to keep old chain connected. 7105 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 7106 MVT::Other, Chain, ReplLoad.getValue(1)); 7107 7108 // Make sure the new and old chains are cleaned up. 7109 AddToWorkList(Token.getNode()); 7110 7111 // Replace uses with load result and token factor. Don't add users 7112 // to work list. 7113 return CombineTo(N, ReplLoad.getValue(0), Token, false); 7114 } 7115 } 7116 7117 // Try transforming N to an indexed load. 7118 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 7119 return SDValue(N, 0); 7120 7121 return SDValue(); 7122} 7123 7124/// CheckForMaskedLoad - Check to see if V is (and load (ptr), imm), where the 7125/// load is having specific bytes cleared out. If so, return the byte size 7126/// being masked out and the shift amount. 7127static std::pair<unsigned, unsigned> 7128CheckForMaskedLoad(SDValue V, SDValue Ptr, SDValue Chain) { 7129 std::pair<unsigned, unsigned> Result(0, 0); 7130 7131 // Check for the structure we're looking for. 7132 if (V->getOpcode() != ISD::AND || 7133 !isa<ConstantSDNode>(V->getOperand(1)) || 7134 !ISD::isNormalLoad(V->getOperand(0).getNode())) 7135 return Result; 7136 7137 // Check the chain and pointer. 7138 LoadSDNode *LD = cast<LoadSDNode>(V->getOperand(0)); 7139 if (LD->getBasePtr() != Ptr) return Result; // Not from same pointer. 7140 7141 // The store should be chained directly to the load or be an operand of a 7142 // tokenfactor. 7143 if (LD == Chain.getNode()) 7144 ; // ok. 7145 else if (Chain->getOpcode() != ISD::TokenFactor) 7146 return Result; // Fail. 7147 else { 7148 bool isOk = false; 7149 for (unsigned i = 0, e = Chain->getNumOperands(); i != e; ++i) 7150 if (Chain->getOperand(i).getNode() == LD) { 7151 isOk = true; 7152 break; 7153 } 7154 if (!isOk) return Result; 7155 } 7156 7157 // This only handles simple types. 7158 if (V.getValueType() != MVT::i16 && 7159 V.getValueType() != MVT::i32 && 7160 V.getValueType() != MVT::i64) 7161 return Result; 7162 7163 // Check the constant mask. Invert it so that the bits being masked out are 7164 // 0 and the bits being kept are 1. Use getSExtValue so that leading bits 7165 // follow the sign bit for uniformity. 7166 uint64_t NotMask = ~cast<ConstantSDNode>(V->getOperand(1))->getSExtValue(); 7167 unsigned NotMaskLZ = CountLeadingZeros_64(NotMask); 7168 if (NotMaskLZ & 7) return Result; // Must be multiple of a byte. 7169 unsigned NotMaskTZ = CountTrailingZeros_64(NotMask); 7170 if (NotMaskTZ & 7) return Result; // Must be multiple of a byte. 7171 if (NotMaskLZ == 64) return Result; // All zero mask. 7172 7173 // See if we have a continuous run of bits. If so, we have 0*1+0* 7174 if (CountTrailingOnes_64(NotMask >> NotMaskTZ)+NotMaskTZ+NotMaskLZ != 64) 7175 return Result; 7176 7177 // Adjust NotMaskLZ down to be from the actual size of the int instead of i64. 7178 if (V.getValueType() != MVT::i64 && NotMaskLZ) 7179 NotMaskLZ -= 64-V.getValueSizeInBits(); 7180 7181 unsigned MaskedBytes = (V.getValueSizeInBits()-NotMaskLZ-NotMaskTZ)/8; 7182 switch (MaskedBytes) { 7183 case 1: 7184 case 2: 7185 case 4: break; 7186 default: return Result; // All one mask, or 5-byte mask. 7187 } 7188 7189 // Verify that the first bit starts at a multiple of mask so that the access 7190 // is aligned the same as the access width. 7191 if (NotMaskTZ && NotMaskTZ/8 % MaskedBytes) return Result; 7192 7193 Result.first = MaskedBytes; 7194 Result.second = NotMaskTZ/8; 7195 return Result; 7196} 7197 7198 7199/// ShrinkLoadReplaceStoreWithStore - Check to see if IVal is something that 7200/// provides a value as specified by MaskInfo. If so, replace the specified 7201/// store with a narrower store of truncated IVal. 7202static SDNode * 7203ShrinkLoadReplaceStoreWithStore(const std::pair<unsigned, unsigned> &MaskInfo, 7204 SDValue IVal, StoreSDNode *St, 7205 DAGCombiner *DC) { 7206 unsigned NumBytes = MaskInfo.first; 7207 unsigned ByteShift = MaskInfo.second; 7208 SelectionDAG &DAG = DC->getDAG(); 7209 7210 // Check to see if IVal is all zeros in the part being masked in by the 'or' 7211 // that uses this. If not, this is not a replacement. 7212 APInt Mask = ~APInt::getBitsSet(IVal.getValueSizeInBits(), 7213 ByteShift*8, (ByteShift+NumBytes)*8); 7214 if (!DAG.MaskedValueIsZero(IVal, Mask)) return 0; 7215 7216 // Check that it is legal on the target to do this. It is legal if the new 7217 // VT we're shrinking to (i8/i16/i32) is legal or we're still before type 7218 // legalization. 7219 MVT VT = MVT::getIntegerVT(NumBytes*8); 7220 if (!DC->isTypeLegal(VT)) 7221 return 0; 7222 7223 // Okay, we can do this! Replace the 'St' store with a store of IVal that is 7224 // shifted by ByteShift and truncated down to NumBytes. 7225 if (ByteShift) 7226 IVal = DAG.getNode(ISD::SRL, IVal->getDebugLoc(), IVal.getValueType(), IVal, 7227 DAG.getConstant(ByteShift*8, 7228 DC->getShiftAmountTy(IVal.getValueType()))); 7229 7230 // Figure out the offset for the store and the alignment of the access. 7231 unsigned StOffset; 7232 unsigned NewAlign = St->getAlignment(); 7233 7234 if (DAG.getTargetLoweringInfo().isLittleEndian()) 7235 StOffset = ByteShift; 7236 else 7237 StOffset = IVal.getValueType().getStoreSize() - ByteShift - NumBytes; 7238 7239 SDValue Ptr = St->getBasePtr(); 7240 if (StOffset) { 7241 Ptr = DAG.getNode(ISD::ADD, IVal->getDebugLoc(), Ptr.getValueType(), 7242 Ptr, DAG.getConstant(StOffset, Ptr.getValueType())); 7243 NewAlign = MinAlign(NewAlign, StOffset); 7244 } 7245 7246 // Truncate down to the new size. 7247 IVal = DAG.getNode(ISD::TRUNCATE, IVal->getDebugLoc(), VT, IVal); 7248 7249 ++OpsNarrowed; 7250 return DAG.getStore(St->getChain(), St->getDebugLoc(), IVal, Ptr, 7251 St->getPointerInfo().getWithOffset(StOffset), 7252 false, false, NewAlign).getNode(); 7253} 7254 7255 7256/// ReduceLoadOpStoreWidth - Look for sequence of load / op / store where op is 7257/// one of 'or', 'xor', and 'and' of immediates. If 'op' is only touching some 7258/// of the loaded bits, try narrowing the load and store if it would end up 7259/// being a win for performance or code size. 7260SDValue DAGCombiner::ReduceLoadOpStoreWidth(SDNode *N) { 7261 StoreSDNode *ST = cast<StoreSDNode>(N); 7262 if (ST->isVolatile()) 7263 return SDValue(); 7264 7265 SDValue Chain = ST->getChain(); 7266 SDValue Value = ST->getValue(); 7267 SDValue Ptr = ST->getBasePtr(); 7268 EVT VT = Value.getValueType(); 7269 7270 if (ST->isTruncatingStore() || VT.isVector() || !Value.hasOneUse()) 7271 return SDValue(); 7272 7273 unsigned Opc = Value.getOpcode(); 7274 7275 // If this is "store (or X, Y), P" and X is "(and (load P), cst)", where cst 7276 // is a byte mask indicating a consecutive number of bytes, check to see if 7277 // Y is known to provide just those bytes. If so, we try to replace the 7278 // load + replace + store sequence with a single (narrower) store, which makes 7279 // the load dead. 7280 if (Opc == ISD::OR) { 7281 std::pair<unsigned, unsigned> MaskedLoad; 7282 MaskedLoad = CheckForMaskedLoad(Value.getOperand(0), Ptr, Chain); 7283 if (MaskedLoad.first) 7284 if (SDNode *NewST = ShrinkLoadReplaceStoreWithStore(MaskedLoad, 7285 Value.getOperand(1), ST,this)) 7286 return SDValue(NewST, 0); 7287 7288 // Or is commutative, so try swapping X and Y. 7289 MaskedLoad = CheckForMaskedLoad(Value.getOperand(1), Ptr, Chain); 7290 if (MaskedLoad.first) 7291 if (SDNode *NewST = ShrinkLoadReplaceStoreWithStore(MaskedLoad, 7292 Value.getOperand(0), ST,this)) 7293 return SDValue(NewST, 0); 7294 } 7295 7296 if ((Opc != ISD::OR && Opc != ISD::XOR && Opc != ISD::AND) || 7297 Value.getOperand(1).getOpcode() != ISD::Constant) 7298 return SDValue(); 7299 7300 SDValue N0 = Value.getOperand(0); 7301 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() && 7302 Chain == SDValue(N0.getNode(), 1)) { 7303 LoadSDNode *LD = cast<LoadSDNode>(N0); 7304 if (LD->getBasePtr() != Ptr || 7305 LD->getPointerInfo().getAddrSpace() != 7306 ST->getPointerInfo().getAddrSpace()) 7307 return SDValue(); 7308 7309 // Find the type to narrow it the load / op / store to. 7310 SDValue N1 = Value.getOperand(1); 7311 unsigned BitWidth = N1.getValueSizeInBits(); 7312 APInt Imm = cast<ConstantSDNode>(N1)->getAPIntValue(); 7313 if (Opc == ISD::AND) 7314 Imm ^= APInt::getAllOnesValue(BitWidth); 7315 if (Imm == 0 || Imm.isAllOnesValue()) 7316 return SDValue(); 7317 unsigned ShAmt = Imm.countTrailingZeros(); 7318 unsigned MSB = BitWidth - Imm.countLeadingZeros() - 1; 7319 unsigned NewBW = NextPowerOf2(MSB - ShAmt); 7320 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW); 7321 while (NewBW < BitWidth && 7322 !(TLI.isOperationLegalOrCustom(Opc, NewVT) && 7323 TLI.isNarrowingProfitable(VT, NewVT))) { 7324 NewBW = NextPowerOf2(NewBW); 7325 NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW); 7326 } 7327 if (NewBW >= BitWidth) 7328 return SDValue(); 7329 7330 // If the lsb changed does not start at the type bitwidth boundary, 7331 // start at the previous one. 7332 if (ShAmt % NewBW) 7333 ShAmt = (((ShAmt + NewBW - 1) / NewBW) * NewBW) - NewBW; 7334 APInt Mask = APInt::getBitsSet(BitWidth, ShAmt, ShAmt + NewBW); 7335 if ((Imm & Mask) == Imm) { 7336 APInt NewImm = (Imm & Mask).lshr(ShAmt).trunc(NewBW); 7337 if (Opc == ISD::AND) 7338 NewImm ^= APInt::getAllOnesValue(NewBW); 7339 uint64_t PtrOff = ShAmt / 8; 7340 // For big endian targets, we need to adjust the offset to the pointer to 7341 // load the correct bytes. 7342 if (TLI.isBigEndian()) 7343 PtrOff = (BitWidth + 7 - NewBW) / 8 - PtrOff; 7344 7345 unsigned NewAlign = MinAlign(LD->getAlignment(), PtrOff); 7346 Type *NewVTTy = NewVT.getTypeForEVT(*DAG.getContext()); 7347 if (NewAlign < TLI.getTargetData()->getABITypeAlignment(NewVTTy)) 7348 return SDValue(); 7349 7350 SDValue NewPtr = DAG.getNode(ISD::ADD, LD->getDebugLoc(), 7351 Ptr.getValueType(), Ptr, 7352 DAG.getConstant(PtrOff, Ptr.getValueType())); 7353 SDValue NewLD = DAG.getLoad(NewVT, N0.getDebugLoc(), 7354 LD->getChain(), NewPtr, 7355 LD->getPointerInfo().getWithOffset(PtrOff), 7356 LD->isVolatile(), LD->isNonTemporal(), 7357 LD->isInvariant(), NewAlign); 7358 SDValue NewVal = DAG.getNode(Opc, Value.getDebugLoc(), NewVT, NewLD, 7359 DAG.getConstant(NewImm, NewVT)); 7360 SDValue NewST = DAG.getStore(Chain, N->getDebugLoc(), 7361 NewVal, NewPtr, 7362 ST->getPointerInfo().getWithOffset(PtrOff), 7363 false, false, NewAlign); 7364 7365 AddToWorkList(NewPtr.getNode()); 7366 AddToWorkList(NewLD.getNode()); 7367 AddToWorkList(NewVal.getNode()); 7368 WorkListRemover DeadNodes(*this); 7369 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), NewLD.getValue(1)); 7370 ++OpsNarrowed; 7371 return NewST; 7372 } 7373 } 7374 7375 return SDValue(); 7376} 7377 7378/// TransformFPLoadStorePair - For a given floating point load / store pair, 7379/// if the load value isn't used by any other operations, then consider 7380/// transforming the pair to integer load / store operations if the target 7381/// deems the transformation profitable. 7382SDValue DAGCombiner::TransformFPLoadStorePair(SDNode *N) { 7383 StoreSDNode *ST = cast<StoreSDNode>(N); 7384 SDValue Chain = ST->getChain(); 7385 SDValue Value = ST->getValue(); 7386 if (ISD::isNormalStore(ST) && ISD::isNormalLoad(Value.getNode()) && 7387 Value.hasOneUse() && 7388 Chain == SDValue(Value.getNode(), 1)) { 7389 LoadSDNode *LD = cast<LoadSDNode>(Value); 7390 EVT VT = LD->getMemoryVT(); 7391 if (!VT.isFloatingPoint() || 7392 VT != ST->getMemoryVT() || 7393 LD->isNonTemporal() || 7394 ST->isNonTemporal() || 7395 LD->getPointerInfo().getAddrSpace() != 0 || 7396 ST->getPointerInfo().getAddrSpace() != 0) 7397 return SDValue(); 7398 7399 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits()); 7400 if (!TLI.isOperationLegal(ISD::LOAD, IntVT) || 7401 !TLI.isOperationLegal(ISD::STORE, IntVT) || 7402 !TLI.isDesirableToTransformToIntegerOp(ISD::LOAD, VT) || 7403 !TLI.isDesirableToTransformToIntegerOp(ISD::STORE, VT)) 7404 return SDValue(); 7405 7406 unsigned LDAlign = LD->getAlignment(); 7407 unsigned STAlign = ST->getAlignment(); 7408 Type *IntVTTy = IntVT.getTypeForEVT(*DAG.getContext()); 7409 unsigned ABIAlign = TLI.getTargetData()->getABITypeAlignment(IntVTTy); 7410 if (LDAlign < ABIAlign || STAlign < ABIAlign) 7411 return SDValue(); 7412 7413 SDValue NewLD = DAG.getLoad(IntVT, Value.getDebugLoc(), 7414 LD->getChain(), LD->getBasePtr(), 7415 LD->getPointerInfo(), 7416 false, false, false, LDAlign); 7417 7418 SDValue NewST = DAG.getStore(NewLD.getValue(1), N->getDebugLoc(), 7419 NewLD, ST->getBasePtr(), 7420 ST->getPointerInfo(), 7421 false, false, STAlign); 7422 7423 AddToWorkList(NewLD.getNode()); 7424 AddToWorkList(NewST.getNode()); 7425 WorkListRemover DeadNodes(*this); 7426 DAG.ReplaceAllUsesOfValueWith(Value.getValue(1), NewLD.getValue(1)); 7427 ++LdStFP2Int; 7428 return NewST; 7429 } 7430 7431 return SDValue(); 7432} 7433 7434SDValue DAGCombiner::visitSTORE(SDNode *N) { 7435 StoreSDNode *ST = cast<StoreSDNode>(N); 7436 SDValue Chain = ST->getChain(); 7437 SDValue Value = ST->getValue(); 7438 SDValue Ptr = ST->getBasePtr(); 7439 7440 // If this is a store of a bit convert, store the input value if the 7441 // resultant store does not need a higher alignment than the original. 7442 if (Value.getOpcode() == ISD::BITCAST && !ST->isTruncatingStore() && 7443 ST->isUnindexed()) { 7444 unsigned OrigAlign = ST->getAlignment(); 7445 EVT SVT = Value.getOperand(0).getValueType(); 7446 unsigned Align = TLI.getTargetData()-> 7447 getABITypeAlignment(SVT.getTypeForEVT(*DAG.getContext())); 7448 if (Align <= OrigAlign && 7449 ((!LegalOperations && !ST->isVolatile()) || 7450 TLI.isOperationLegalOrCustom(ISD::STORE, SVT))) 7451 return DAG.getStore(Chain, N->getDebugLoc(), Value.getOperand(0), 7452 Ptr, ST->getPointerInfo(), ST->isVolatile(), 7453 ST->isNonTemporal(), OrigAlign); 7454 } 7455 7456 // Turn 'store undef, Ptr' -> nothing. 7457 if (Value.getOpcode() == ISD::UNDEF && ST->isUnindexed()) 7458 return Chain; 7459 7460 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 7461 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) { 7462 // NOTE: If the original store is volatile, this transform must not increase 7463 // the number of stores. For example, on x86-32 an f64 can be stored in one 7464 // processor operation but an i64 (which is not legal) requires two. So the 7465 // transform should not be done in this case. 7466 if (Value.getOpcode() != ISD::TargetConstantFP) { 7467 SDValue Tmp; 7468 switch (CFP->getValueType(0).getSimpleVT().SimpleTy) { 7469 default: llvm_unreachable("Unknown FP type"); 7470 case MVT::f16: // We don't do this for these yet. 7471 case MVT::f80: 7472 case MVT::f128: 7473 case MVT::ppcf128: 7474 break; 7475 case MVT::f32: 7476 if ((isTypeLegal(MVT::i32) && !LegalOperations && !ST->isVolatile()) || 7477 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) { 7478 Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF(). 7479 bitcastToAPInt().getZExtValue(), MVT::i32); 7480 return DAG.getStore(Chain, N->getDebugLoc(), Tmp, 7481 Ptr, ST->getPointerInfo(), ST->isVolatile(), 7482 ST->isNonTemporal(), ST->getAlignment()); 7483 } 7484 break; 7485 case MVT::f64: 7486 if ((TLI.isTypeLegal(MVT::i64) && !LegalOperations && 7487 !ST->isVolatile()) || 7488 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i64)) { 7489 Tmp = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt(). 7490 getZExtValue(), MVT::i64); 7491 return DAG.getStore(Chain, N->getDebugLoc(), Tmp, 7492 Ptr, ST->getPointerInfo(), ST->isVolatile(), 7493 ST->isNonTemporal(), ST->getAlignment()); 7494 } 7495 7496 if (!ST->isVolatile() && 7497 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) { 7498 // Many FP stores are not made apparent until after legalize, e.g. for 7499 // argument passing. Since this is so common, custom legalize the 7500 // 64-bit integer store into two 32-bit stores. 7501 uint64_t Val = CFP->getValueAPF().bitcastToAPInt().getZExtValue(); 7502 SDValue Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32); 7503 SDValue Hi = DAG.getConstant(Val >> 32, MVT::i32); 7504 if (TLI.isBigEndian()) std::swap(Lo, Hi); 7505 7506 unsigned Alignment = ST->getAlignment(); 7507 bool isVolatile = ST->isVolatile(); 7508 bool isNonTemporal = ST->isNonTemporal(); 7509 7510 SDValue St0 = DAG.getStore(Chain, ST->getDebugLoc(), Lo, 7511 Ptr, ST->getPointerInfo(), 7512 isVolatile, isNonTemporal, 7513 ST->getAlignment()); 7514 Ptr = DAG.getNode(ISD::ADD, N->getDebugLoc(), Ptr.getValueType(), Ptr, 7515 DAG.getConstant(4, Ptr.getValueType())); 7516 Alignment = MinAlign(Alignment, 4U); 7517 SDValue St1 = DAG.getStore(Chain, ST->getDebugLoc(), Hi, 7518 Ptr, ST->getPointerInfo().getWithOffset(4), 7519 isVolatile, isNonTemporal, 7520 Alignment); 7521 return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, 7522 St0, St1); 7523 } 7524 7525 break; 7526 } 7527 } 7528 } 7529 7530 // Try to infer better alignment information than the store already has. 7531 if (OptLevel != CodeGenOpt::None && ST->isUnindexed()) { 7532 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) { 7533 if (Align > ST->getAlignment()) 7534 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value, 7535 Ptr, ST->getPointerInfo(), ST->getMemoryVT(), 7536 ST->isVolatile(), ST->isNonTemporal(), Align); 7537 } 7538 } 7539 7540 // Try transforming a pair floating point load / store ops to integer 7541 // load / store ops. 7542 SDValue NewST = TransformFPLoadStorePair(N); 7543 if (NewST.getNode()) 7544 return NewST; 7545 7546 if (CombinerAA) { 7547 // Walk up chain skipping non-aliasing memory nodes. 7548 SDValue BetterChain = FindBetterChain(N, Chain); 7549 7550 // If there is a better chain. 7551 if (Chain != BetterChain) { 7552 SDValue ReplStore; 7553 7554 // Replace the chain to avoid dependency. 7555 if (ST->isTruncatingStore()) { 7556 ReplStore = DAG.getTruncStore(BetterChain, N->getDebugLoc(), Value, Ptr, 7557 ST->getPointerInfo(), 7558 ST->getMemoryVT(), ST->isVolatile(), 7559 ST->isNonTemporal(), ST->getAlignment()); 7560 } else { 7561 ReplStore = DAG.getStore(BetterChain, N->getDebugLoc(), Value, Ptr, 7562 ST->getPointerInfo(), 7563 ST->isVolatile(), ST->isNonTemporal(), 7564 ST->getAlignment()); 7565 } 7566 7567 // Create token to keep both nodes around. 7568 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 7569 MVT::Other, Chain, ReplStore); 7570 7571 // Make sure the new and old chains are cleaned up. 7572 AddToWorkList(Token.getNode()); 7573 7574 // Don't add users to work list. 7575 return CombineTo(N, Token, false); 7576 } 7577 } 7578 7579 // Try transforming N to an indexed store. 7580 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 7581 return SDValue(N, 0); 7582 7583 // FIXME: is there such a thing as a truncating indexed store? 7584 if (ST->isTruncatingStore() && ST->isUnindexed() && 7585 Value.getValueType().isInteger()) { 7586 // See if we can simplify the input to this truncstore with knowledge that 7587 // only the low bits are being used. For example: 7588 // "truncstore (or (shl x, 8), y), i8" -> "truncstore y, i8" 7589 SDValue Shorter = 7590 GetDemandedBits(Value, 7591 APInt::getLowBitsSet( 7592 Value.getValueType().getScalarType().getSizeInBits(), 7593 ST->getMemoryVT().getScalarType().getSizeInBits())); 7594 AddToWorkList(Value.getNode()); 7595 if (Shorter.getNode()) 7596 return DAG.getTruncStore(Chain, N->getDebugLoc(), Shorter, 7597 Ptr, ST->getPointerInfo(), ST->getMemoryVT(), 7598 ST->isVolatile(), ST->isNonTemporal(), 7599 ST->getAlignment()); 7600 7601 // Otherwise, see if we can simplify the operation with 7602 // SimplifyDemandedBits, which only works if the value has a single use. 7603 if (SimplifyDemandedBits(Value, 7604 APInt::getLowBitsSet( 7605 Value.getValueType().getScalarType().getSizeInBits(), 7606 ST->getMemoryVT().getScalarType().getSizeInBits()))) 7607 return SDValue(N, 0); 7608 } 7609 7610 // If this is a load followed by a store to the same location, then the store 7611 // is dead/noop. 7612 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Value)) { 7613 if (Ld->getBasePtr() == Ptr && ST->getMemoryVT() == Ld->getMemoryVT() && 7614 ST->isUnindexed() && !ST->isVolatile() && 7615 // There can't be any side effects between the load and store, such as 7616 // a call or store. 7617 Chain.reachesChainWithoutSideEffects(SDValue(Ld, 1))) { 7618 // The store is dead, remove it. 7619 return Chain; 7620 } 7621 } 7622 7623 // If this is an FP_ROUND or TRUNC followed by a store, fold this into a 7624 // truncating store. We can do this even if this is already a truncstore. 7625 if ((Value.getOpcode() == ISD::FP_ROUND || Value.getOpcode() == ISD::TRUNCATE) 7626 && Value.getNode()->hasOneUse() && ST->isUnindexed() && 7627 TLI.isTruncStoreLegal(Value.getOperand(0).getValueType(), 7628 ST->getMemoryVT())) { 7629 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value.getOperand(0), 7630 Ptr, ST->getPointerInfo(), ST->getMemoryVT(), 7631 ST->isVolatile(), ST->isNonTemporal(), 7632 ST->getAlignment()); 7633 } 7634 7635 return ReduceLoadOpStoreWidth(N); 7636} 7637 7638SDValue DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) { 7639 SDValue InVec = N->getOperand(0); 7640 SDValue InVal = N->getOperand(1); 7641 SDValue EltNo = N->getOperand(2); 7642 DebugLoc dl = N->getDebugLoc(); 7643 7644 // If the inserted element is an UNDEF, just use the input vector. 7645 if (InVal.getOpcode() == ISD::UNDEF) 7646 return InVec; 7647 7648 EVT VT = InVec.getValueType(); 7649 7650 // If we can't generate a legal BUILD_VECTOR, exit 7651 if (LegalOperations && !TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) 7652 return SDValue(); 7653 7654 // Check that we know which element is being inserted 7655 if (!isa<ConstantSDNode>(EltNo)) 7656 return SDValue(); 7657 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 7658 7659 // Check that the operand is a BUILD_VECTOR (or UNDEF, which can essentially 7660 // be converted to a BUILD_VECTOR). Fill in the Ops vector with the 7661 // vector elements. 7662 SmallVector<SDValue, 8> Ops; 7663 if (InVec.getOpcode() == ISD::BUILD_VECTOR) { 7664 Ops.append(InVec.getNode()->op_begin(), 7665 InVec.getNode()->op_end()); 7666 } else if (InVec.getOpcode() == ISD::UNDEF) { 7667 unsigned NElts = VT.getVectorNumElements(); 7668 Ops.append(NElts, DAG.getUNDEF(InVal.getValueType())); 7669 } else { 7670 return SDValue(); 7671 } 7672 7673 // Insert the element 7674 if (Elt < Ops.size()) { 7675 // All the operands of BUILD_VECTOR must have the same type; 7676 // we enforce that here. 7677 EVT OpVT = Ops[0].getValueType(); 7678 if (InVal.getValueType() != OpVT) 7679 InVal = OpVT.bitsGT(InVal.getValueType()) ? 7680 DAG.getNode(ISD::ANY_EXTEND, dl, OpVT, InVal) : 7681 DAG.getNode(ISD::TRUNCATE, dl, OpVT, InVal); 7682 Ops[Elt] = InVal; 7683 } 7684 7685 // Return the new vector 7686 return DAG.getNode(ISD::BUILD_VECTOR, dl, 7687 VT, &Ops[0], Ops.size()); 7688} 7689 7690SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) { 7691 // (vextract (scalar_to_vector val, 0) -> val 7692 SDValue InVec = N->getOperand(0); 7693 EVT VT = InVec.getValueType(); 7694 EVT NVT = N->getValueType(0); 7695 7696 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) { 7697 // Check if the result type doesn't match the inserted element type. A 7698 // SCALAR_TO_VECTOR may truncate the inserted element and the 7699 // EXTRACT_VECTOR_ELT may widen the extracted vector. 7700 SDValue InOp = InVec.getOperand(0); 7701 if (InOp.getValueType() != NVT) { 7702 assert(InOp.getValueType().isInteger() && NVT.isInteger()); 7703 return DAG.getSExtOrTrunc(InOp, InVec.getDebugLoc(), NVT); 7704 } 7705 return InOp; 7706 } 7707 7708 SDValue EltNo = N->getOperand(1); 7709 bool ConstEltNo = isa<ConstantSDNode>(EltNo); 7710 7711 // Transform: (EXTRACT_VECTOR_ELT( VECTOR_SHUFFLE )) -> EXTRACT_VECTOR_ELT. 7712 // We only perform this optimization before the op legalization phase because 7713 // we may introduce new vector instructions which are not backed by TD patterns. 7714 // For example on AVX, extracting elements from a wide vector without using 7715 // extract_subvector. 7716 if (InVec.getOpcode() == ISD::VECTOR_SHUFFLE 7717 && ConstEltNo && !LegalOperations) { 7718 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 7719 int NumElem = VT.getVectorNumElements(); 7720 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(InVec); 7721 // Find the new index to extract from. 7722 int OrigElt = SVOp->getMaskElt(Elt); 7723 7724 // Extracting an undef index is undef. 7725 if (OrigElt == -1) 7726 return DAG.getUNDEF(NVT); 7727 7728 // Select the right vector half to extract from. 7729 if (OrigElt < NumElem) { 7730 InVec = InVec->getOperand(0); 7731 } else { 7732 InVec = InVec->getOperand(1); 7733 OrigElt -= NumElem; 7734 } 7735 7736 EVT IndexTy = N->getOperand(1).getValueType(); 7737 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, N->getDebugLoc(), NVT, 7738 InVec, DAG.getConstant(OrigElt, IndexTy)); 7739 } 7740 7741 // Perform only after legalization to ensure build_vector / vector_shuffle 7742 // optimizations have already been done. 7743 if (!LegalOperations) return SDValue(); 7744 7745 // (vextract (v4f32 load $addr), c) -> (f32 load $addr+c*size) 7746 // (vextract (v4f32 s2v (f32 load $addr)), c) -> (f32 load $addr+c*size) 7747 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), 0) -> (f32 load $addr) 7748 7749 if (ConstEltNo) { 7750 int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 7751 bool NewLoad = false; 7752 bool BCNumEltsChanged = false; 7753 EVT ExtVT = VT.getVectorElementType(); 7754 EVT LVT = ExtVT; 7755 7756 // If the result of load has to be truncated, then it's not necessarily 7757 // profitable. 7758 if (NVT.bitsLT(LVT) && !TLI.isTruncateFree(LVT, NVT)) 7759 return SDValue(); 7760 7761 if (InVec.getOpcode() == ISD::BITCAST) { 7762 // Don't duplicate a load with other uses. 7763 if (!InVec.hasOneUse()) 7764 return SDValue(); 7765 7766 EVT BCVT = InVec.getOperand(0).getValueType(); 7767 if (!BCVT.isVector() || ExtVT.bitsGT(BCVT.getVectorElementType())) 7768 return SDValue(); 7769 if (VT.getVectorNumElements() != BCVT.getVectorNumElements()) 7770 BCNumEltsChanged = true; 7771 InVec = InVec.getOperand(0); 7772 ExtVT = BCVT.getVectorElementType(); 7773 NewLoad = true; 7774 } 7775 7776 LoadSDNode *LN0 = NULL; 7777 const ShuffleVectorSDNode *SVN = NULL; 7778 if (ISD::isNormalLoad(InVec.getNode())) { 7779 LN0 = cast<LoadSDNode>(InVec); 7780 } else if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR && 7781 InVec.getOperand(0).getValueType() == ExtVT && 7782 ISD::isNormalLoad(InVec.getOperand(0).getNode())) { 7783 // Don't duplicate a load with other uses. 7784 if (!InVec.hasOneUse()) 7785 return SDValue(); 7786 7787 LN0 = cast<LoadSDNode>(InVec.getOperand(0)); 7788 } else if ((SVN = dyn_cast<ShuffleVectorSDNode>(InVec))) { 7789 // (vextract (vector_shuffle (load $addr), v2, <1, u, u, u>), 1) 7790 // => 7791 // (load $addr+1*size) 7792 7793 // Don't duplicate a load with other uses. 7794 if (!InVec.hasOneUse()) 7795 return SDValue(); 7796 7797 // If the bit convert changed the number of elements, it is unsafe 7798 // to examine the mask. 7799 if (BCNumEltsChanged) 7800 return SDValue(); 7801 7802 // Select the input vector, guarding against out of range extract vector. 7803 unsigned NumElems = VT.getVectorNumElements(); 7804 int Idx = (Elt > (int)NumElems) ? -1 : SVN->getMaskElt(Elt); 7805 InVec = (Idx < (int)NumElems) ? InVec.getOperand(0) : InVec.getOperand(1); 7806 7807 if (InVec.getOpcode() == ISD::BITCAST) { 7808 // Don't duplicate a load with other uses. 7809 if (!InVec.hasOneUse()) 7810 return SDValue(); 7811 7812 InVec = InVec.getOperand(0); 7813 } 7814 if (ISD::isNormalLoad(InVec.getNode())) { 7815 LN0 = cast<LoadSDNode>(InVec); 7816 Elt = (Idx < (int)NumElems) ? Idx : Idx - (int)NumElems; 7817 } 7818 } 7819 7820 // Make sure we found a non-volatile load and the extractelement is 7821 // the only use. 7822 if (!LN0 || !LN0->hasNUsesOfValue(1,0) || LN0->isVolatile()) 7823 return SDValue(); 7824 7825 // If Idx was -1 above, Elt is going to be -1, so just return undef. 7826 if (Elt == -1) 7827 return DAG.getUNDEF(LVT); 7828 7829 unsigned Align = LN0->getAlignment(); 7830 if (NewLoad) { 7831 // Check the resultant load doesn't need a higher alignment than the 7832 // original load. 7833 unsigned NewAlign = 7834 TLI.getTargetData() 7835 ->getABITypeAlignment(LVT.getTypeForEVT(*DAG.getContext())); 7836 7837 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, LVT)) 7838 return SDValue(); 7839 7840 Align = NewAlign; 7841 } 7842 7843 SDValue NewPtr = LN0->getBasePtr(); 7844 unsigned PtrOff = 0; 7845 7846 if (Elt) { 7847 PtrOff = LVT.getSizeInBits() * Elt / 8; 7848 EVT PtrType = NewPtr.getValueType(); 7849 if (TLI.isBigEndian()) 7850 PtrOff = VT.getSizeInBits() / 8 - PtrOff; 7851 NewPtr = DAG.getNode(ISD::ADD, N->getDebugLoc(), PtrType, NewPtr, 7852 DAG.getConstant(PtrOff, PtrType)); 7853 } 7854 7855 // The replacement we need to do here is a little tricky: we need to 7856 // replace an extractelement of a load with a load. 7857 // Use ReplaceAllUsesOfValuesWith to do the replacement. 7858 // Note that this replacement assumes that the extractvalue is the only 7859 // use of the load; that's okay because we don't want to perform this 7860 // transformation in other cases anyway. 7861 SDValue Load; 7862 SDValue Chain; 7863 if (NVT.bitsGT(LVT)) { 7864 // If the result type of vextract is wider than the load, then issue an 7865 // extending load instead. 7866 ISD::LoadExtType ExtType = TLI.isLoadExtLegal(ISD::ZEXTLOAD, LVT) 7867 ? ISD::ZEXTLOAD : ISD::EXTLOAD; 7868 Load = DAG.getExtLoad(ExtType, N->getDebugLoc(), NVT, LN0->getChain(), 7869 NewPtr, LN0->getPointerInfo().getWithOffset(PtrOff), 7870 LVT, LN0->isVolatile(), LN0->isNonTemporal(),Align); 7871 Chain = Load.getValue(1); 7872 } else { 7873 Load = DAG.getLoad(LVT, N->getDebugLoc(), LN0->getChain(), NewPtr, 7874 LN0->getPointerInfo().getWithOffset(PtrOff), 7875 LN0->isVolatile(), LN0->isNonTemporal(), 7876 LN0->isInvariant(), Align); 7877 Chain = Load.getValue(1); 7878 if (NVT.bitsLT(LVT)) 7879 Load = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), NVT, Load); 7880 else 7881 Load = DAG.getNode(ISD::BITCAST, N->getDebugLoc(), NVT, Load); 7882 } 7883 WorkListRemover DeadNodes(*this); 7884 SDValue From[] = { SDValue(N, 0), SDValue(LN0,1) }; 7885 SDValue To[] = { Load, Chain }; 7886 DAG.ReplaceAllUsesOfValuesWith(From, To, 2); 7887 // Since we're explcitly calling ReplaceAllUses, add the new node to the 7888 // worklist explicitly as well. 7889 AddToWorkList(Load.getNode()); 7890 AddUsersToWorkList(Load.getNode()); // Add users too 7891 // Make sure to revisit this node to clean it up; it will usually be dead. 7892 AddToWorkList(N); 7893 return SDValue(N, 0); 7894 } 7895 7896 return SDValue(); 7897} 7898 7899SDValue DAGCombiner::visitBUILD_VECTOR(SDNode *N) { 7900 unsigned NumInScalars = N->getNumOperands(); 7901 DebugLoc dl = N->getDebugLoc(); 7902 EVT VT = N->getValueType(0); 7903 7904 // A vector built entirely of undefs is undef. 7905 if (ISD::allOperandsUndef(N)) 7906 return DAG.getUNDEF(VT); 7907 7908 // Check to see if this is a BUILD_VECTOR of a bunch of values 7909 // which come from any_extend or zero_extend nodes. If so, we can create 7910 // a new BUILD_VECTOR using bit-casts which may enable other BUILD_VECTOR 7911 // optimizations. We do not handle sign-extend because we can't fill the sign 7912 // using shuffles. 7913 EVT SourceType = MVT::Other; 7914 bool AllAnyExt = true; 7915 7916 for (unsigned i = 0; i != NumInScalars; ++i) { 7917 SDValue In = N->getOperand(i); 7918 // Ignore undef inputs. 7919 if (In.getOpcode() == ISD::UNDEF) continue; 7920 7921 bool AnyExt = In.getOpcode() == ISD::ANY_EXTEND; 7922 bool ZeroExt = In.getOpcode() == ISD::ZERO_EXTEND; 7923 7924 // Abort if the element is not an extension. 7925 if (!ZeroExt && !AnyExt) { 7926 SourceType = MVT::Other; 7927 break; 7928 } 7929 7930 // The input is a ZeroExt or AnyExt. Check the original type. 7931 EVT InTy = In.getOperand(0).getValueType(); 7932 7933 // Check that all of the widened source types are the same. 7934 if (SourceType == MVT::Other) 7935 // First time. 7936 SourceType = InTy; 7937 else if (InTy != SourceType) { 7938 // Multiple income types. Abort. 7939 SourceType = MVT::Other; 7940 break; 7941 } 7942 7943 // Check if all of the extends are ANY_EXTENDs. 7944 AllAnyExt &= AnyExt; 7945 } 7946 7947 // In order to have valid types, all of the inputs must be extended from the 7948 // same source type and all of the inputs must be any or zero extend. 7949 // Scalar sizes must be a power of two. 7950 EVT OutScalarTy = N->getValueType(0).getScalarType(); 7951 bool ValidTypes = SourceType != MVT::Other && 7952 isPowerOf2_32(OutScalarTy.getSizeInBits()) && 7953 isPowerOf2_32(SourceType.getSizeInBits()); 7954 7955 // We perform this optimization post type-legalization because 7956 // the type-legalizer often scalarizes integer-promoted vectors. 7957 // Performing this optimization before may create bit-casts which 7958 // will be type-legalized to complex code sequences. 7959 // We perform this optimization only before the operation legalizer because we 7960 // may introduce illegal operations. 7961 // Create a new simpler BUILD_VECTOR sequence which other optimizations can 7962 // turn into a single shuffle instruction. 7963 if ((Level == AfterLegalizeVectorOps || Level == AfterLegalizeTypes) && 7964 ValidTypes) { 7965 bool isLE = TLI.isLittleEndian(); 7966 unsigned ElemRatio = OutScalarTy.getSizeInBits()/SourceType.getSizeInBits(); 7967 assert(ElemRatio > 1 && "Invalid element size ratio"); 7968 SDValue Filler = AllAnyExt ? DAG.getUNDEF(SourceType): 7969 DAG.getConstant(0, SourceType); 7970 7971 unsigned NewBVElems = ElemRatio * N->getValueType(0).getVectorNumElements(); 7972 SmallVector<SDValue, 8> Ops(NewBVElems, Filler); 7973 7974 // Populate the new build_vector 7975 for (unsigned i=0; i < N->getNumOperands(); ++i) { 7976 SDValue Cast = N->getOperand(i); 7977 assert((Cast.getOpcode() == ISD::ANY_EXTEND || 7978 Cast.getOpcode() == ISD::ZERO_EXTEND || 7979 Cast.getOpcode() == ISD::UNDEF) && "Invalid cast opcode"); 7980 SDValue In; 7981 if (Cast.getOpcode() == ISD::UNDEF) 7982 In = DAG.getUNDEF(SourceType); 7983 else 7984 In = Cast->getOperand(0); 7985 unsigned Index = isLE ? (i * ElemRatio) : 7986 (i * ElemRatio + (ElemRatio - 1)); 7987 7988 assert(Index < Ops.size() && "Invalid index"); 7989 Ops[Index] = In; 7990 } 7991 7992 // The type of the new BUILD_VECTOR node. 7993 EVT VecVT = EVT::getVectorVT(*DAG.getContext(), SourceType, NewBVElems); 7994 assert(VecVT.getSizeInBits() == N->getValueType(0).getSizeInBits() && 7995 "Invalid vector size"); 7996 // Check if the new vector type is legal. 7997 if (!isTypeLegal(VecVT)) return SDValue(); 7998 7999 // Make the new BUILD_VECTOR. 8000 SDValue BV = DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 8001 VecVT, &Ops[0], Ops.size()); 8002 8003 // The new BUILD_VECTOR node has the potential to be further optimized. 8004 AddToWorkList(BV.getNode()); 8005 // Bitcast to the desired type. 8006 return DAG.getNode(ISD::BITCAST, dl, N->getValueType(0), BV); 8007 } 8008 8009 // Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT 8010 // operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from 8011 // at most two distinct vectors, turn this into a shuffle node. 8012 8013 // May only combine to shuffle after legalize if shuffle is legal. 8014 if (LegalOperations && 8015 !TLI.isOperationLegalOrCustom(ISD::VECTOR_SHUFFLE, VT)) 8016 return SDValue(); 8017 8018 SDValue VecIn1, VecIn2; 8019 for (unsigned i = 0; i != NumInScalars; ++i) { 8020 // Ignore undef inputs. 8021 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 8022 8023 // If this input is something other than a EXTRACT_VECTOR_ELT with a 8024 // constant index, bail out. 8025 if (N->getOperand(i).getOpcode() != ISD::EXTRACT_VECTOR_ELT || 8026 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) { 8027 VecIn1 = VecIn2 = SDValue(0, 0); 8028 break; 8029 } 8030 8031 // We allow up to two distinct input vectors. 8032 SDValue ExtractedFromVec = N->getOperand(i).getOperand(0); 8033 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2) 8034 continue; 8035 8036 if (VecIn1.getNode() == 0) { 8037 VecIn1 = ExtractedFromVec; 8038 } else if (VecIn2.getNode() == 0) { 8039 VecIn2 = ExtractedFromVec; 8040 } else { 8041 // Too many inputs. 8042 VecIn1 = VecIn2 = SDValue(0, 0); 8043 break; 8044 } 8045 } 8046 8047 // If everything is good, we can make a shuffle operation. 8048 if (VecIn1.getNode()) { 8049 SmallVector<int, 8> Mask; 8050 for (unsigned i = 0; i != NumInScalars; ++i) { 8051 if (N->getOperand(i).getOpcode() == ISD::UNDEF) { 8052 Mask.push_back(-1); 8053 continue; 8054 } 8055 8056 // If extracting from the first vector, just use the index directly. 8057 SDValue Extract = N->getOperand(i); 8058 SDValue ExtVal = Extract.getOperand(1); 8059 if (Extract.getOperand(0) == VecIn1) { 8060 unsigned ExtIndex = cast<ConstantSDNode>(ExtVal)->getZExtValue(); 8061 if (ExtIndex > VT.getVectorNumElements()) 8062 return SDValue(); 8063 8064 Mask.push_back(ExtIndex); 8065 continue; 8066 } 8067 8068 // Otherwise, use InIdx + VecSize 8069 unsigned Idx = cast<ConstantSDNode>(ExtVal)->getZExtValue(); 8070 Mask.push_back(Idx+NumInScalars); 8071 } 8072 8073 // We can't generate a shuffle node with mismatched input and output types. 8074 // Attempt to transform a single input vector to the correct type. 8075 if ((VT != VecIn1.getValueType())) { 8076 // We don't support shuffeling between TWO values of different types. 8077 if (VecIn2.getNode() != 0) 8078 return SDValue(); 8079 8080 // We only support widening of vectors which are half the size of the 8081 // output registers. For example XMM->YMM widening on X86 with AVX. 8082 if (VecIn1.getValueType().getSizeInBits()*2 != VT.getSizeInBits()) 8083 return SDValue(); 8084 8085 // If the input vector type has a different base type to the output 8086 // vector type, bail out. 8087 if (VecIn1.getValueType().getVectorElementType() != 8088 VT.getVectorElementType()) 8089 return SDValue(); 8090 8091 // Widen the input vector by adding undef values. 8092 VecIn1 = DAG.getNode(ISD::CONCAT_VECTORS, N->getDebugLoc(), VT, 8093 VecIn1, DAG.getUNDEF(VecIn1.getValueType())); 8094 } 8095 8096 // If VecIn2 is unused then change it to undef. 8097 VecIn2 = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT); 8098 8099 // Check that we were able to transform all incoming values to the same type. 8100 if (VecIn2.getValueType() != VecIn1.getValueType() || 8101 VecIn1.getValueType() != VT) 8102 return SDValue(); 8103 8104 // Only type-legal BUILD_VECTOR nodes are converted to shuffle nodes. 8105 if (!isTypeLegal(VT)) 8106 return SDValue(); 8107 8108 // Return the new VECTOR_SHUFFLE node. 8109 SDValue Ops[2]; 8110 Ops[0] = VecIn1; 8111 Ops[1] = VecIn2; 8112 return DAG.getVectorShuffle(VT, N->getDebugLoc(), Ops[0], Ops[1], &Mask[0]); 8113 } 8114 8115 return SDValue(); 8116} 8117 8118SDValue DAGCombiner::visitCONCAT_VECTORS(SDNode *N) { 8119 // TODO: Check to see if this is a CONCAT_VECTORS of a bunch of 8120 // EXTRACT_SUBVECTOR operations. If so, and if the EXTRACT_SUBVECTOR vector 8121 // inputs come from at most two distinct vectors, turn this into a shuffle 8122 // node. 8123 8124 // If we only have one input vector, we don't need to do any concatenation. 8125 if (N->getNumOperands() == 1) 8126 return N->getOperand(0); 8127 8128 // Check if all of the operands are undefs. 8129 if (ISD::allOperandsUndef(N)) 8130 return DAG.getUNDEF(N->getValueType(0)); 8131 8132 return SDValue(); 8133} 8134 8135SDValue DAGCombiner::visitEXTRACT_SUBVECTOR(SDNode* N) { 8136 EVT NVT = N->getValueType(0); 8137 SDValue V = N->getOperand(0); 8138 8139 if (V->getOpcode() == ISD::INSERT_SUBVECTOR) { 8140 // Handle only simple case where vector being inserted and vector 8141 // being extracted are of same type, and are half size of larger vectors. 8142 EVT BigVT = V->getOperand(0).getValueType(); 8143 EVT SmallVT = V->getOperand(1).getValueType(); 8144 if (NVT != SmallVT || NVT.getSizeInBits()*2 != BigVT.getSizeInBits()) 8145 return SDValue(); 8146 8147 // Only handle cases where both indexes are constants with the same type. 8148 ConstantSDNode *InsIdx = dyn_cast<ConstantSDNode>(N->getOperand(1)); 8149 ConstantSDNode *ExtIdx = dyn_cast<ConstantSDNode>(V->getOperand(2)); 8150 8151 if (InsIdx && ExtIdx && 8152 InsIdx->getValueType(0).getSizeInBits() <= 64 && 8153 ExtIdx->getValueType(0).getSizeInBits() <= 64) { 8154 // Combine: 8155 // (extract_subvec (insert_subvec V1, V2, InsIdx), ExtIdx) 8156 // Into: 8157 // indices are equal => V1 8158 // otherwise => (extract_subvec V1, ExtIdx) 8159 if (InsIdx->getZExtValue() == ExtIdx->getZExtValue()) 8160 return V->getOperand(1); 8161 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, N->getDebugLoc(), NVT, 8162 V->getOperand(0), N->getOperand(1)); 8163 } 8164 } 8165 8166 return SDValue(); 8167} 8168 8169SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) { 8170 EVT VT = N->getValueType(0); 8171 unsigned NumElts = VT.getVectorNumElements(); 8172 8173 SDValue N0 = N->getOperand(0); 8174 SDValue N1 = N->getOperand(1); 8175 8176 assert(N0.getValueType() == VT && "Vector shuffle must be normalized in DAG"); 8177 8178 // Canonicalize shuffle undef, undef -> undef 8179 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF) 8180 return DAG.getUNDEF(VT); 8181 8182 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N); 8183 8184 // Canonicalize shuffle v, v -> v, undef 8185 if (N0 == N1) { 8186 SmallVector<int, 8> NewMask; 8187 for (unsigned i = 0; i != NumElts; ++i) { 8188 int Idx = SVN->getMaskElt(i); 8189 if (Idx >= (int)NumElts) Idx -= NumElts; 8190 NewMask.push_back(Idx); 8191 } 8192 return DAG.getVectorShuffle(VT, N->getDebugLoc(), N0, DAG.getUNDEF(VT), 8193 &NewMask[0]); 8194 } 8195 8196 // Canonicalize shuffle undef, v -> v, undef. Commute the shuffle mask. 8197 if (N0.getOpcode() == ISD::UNDEF) { 8198 SmallVector<int, 8> NewMask; 8199 for (unsigned i = 0; i != NumElts; ++i) { 8200 int Idx = SVN->getMaskElt(i); 8201 if (Idx >= 0) { 8202 if (Idx < (int)NumElts) 8203 Idx += NumElts; 8204 else 8205 Idx -= NumElts; 8206 } 8207 NewMask.push_back(Idx); 8208 } 8209 return DAG.getVectorShuffle(VT, N->getDebugLoc(), N1, DAG.getUNDEF(VT), 8210 &NewMask[0]); 8211 } 8212 8213 // Remove references to rhs if it is undef 8214 if (N1.getOpcode() == ISD::UNDEF) { 8215 bool Changed = false; 8216 SmallVector<int, 8> NewMask; 8217 for (unsigned i = 0; i != NumElts; ++i) { 8218 int Idx = SVN->getMaskElt(i); 8219 if (Idx >= (int)NumElts) { 8220 Idx = -1; 8221 Changed = true; 8222 } 8223 NewMask.push_back(Idx); 8224 } 8225 if (Changed) 8226 return DAG.getVectorShuffle(VT, N->getDebugLoc(), N0, N1, &NewMask[0]); 8227 } 8228 8229 // If it is a splat, check if the argument vector is another splat or a 8230 // build_vector with all scalar elements the same. 8231 if (SVN->isSplat() && SVN->getSplatIndex() < (int)NumElts) { 8232 SDNode *V = N0.getNode(); 8233 8234 // If this is a bit convert that changes the element type of the vector but 8235 // not the number of vector elements, look through it. Be careful not to 8236 // look though conversions that change things like v4f32 to v2f64. 8237 if (V->getOpcode() == ISD::BITCAST) { 8238 SDValue ConvInput = V->getOperand(0); 8239 if (ConvInput.getValueType().isVector() && 8240 ConvInput.getValueType().getVectorNumElements() == NumElts) 8241 V = ConvInput.getNode(); 8242 } 8243 8244 if (V->getOpcode() == ISD::BUILD_VECTOR) { 8245 assert(V->getNumOperands() == NumElts && 8246 "BUILD_VECTOR has wrong number of operands"); 8247 SDValue Base; 8248 bool AllSame = true; 8249 for (unsigned i = 0; i != NumElts; ++i) { 8250 if (V->getOperand(i).getOpcode() != ISD::UNDEF) { 8251 Base = V->getOperand(i); 8252 break; 8253 } 8254 } 8255 // Splat of <u, u, u, u>, return <u, u, u, u> 8256 if (!Base.getNode()) 8257 return N0; 8258 for (unsigned i = 0; i != NumElts; ++i) { 8259 if (V->getOperand(i) != Base) { 8260 AllSame = false; 8261 break; 8262 } 8263 } 8264 // Splat of <x, x, x, x>, return <x, x, x, x> 8265 if (AllSame) 8266 return N0; 8267 } 8268 } 8269 8270 // If this shuffle node is simply a swizzle of another shuffle node, 8271 // and it reverses the swizzle of the previous shuffle then we can 8272 // optimize shuffle(shuffle(x, undef), undef) -> x. 8273 if (N0.getOpcode() == ISD::VECTOR_SHUFFLE && Level < AfterLegalizeDAG && 8274 N1.getOpcode() == ISD::UNDEF) { 8275 8276 ShuffleVectorSDNode *OtherSV = cast<ShuffleVectorSDNode>(N0); 8277 8278 // Shuffle nodes can only reverse shuffles with a single non-undef value. 8279 if (N0.getOperand(1).getOpcode() != ISD::UNDEF) 8280 return SDValue(); 8281 8282 // The incoming shuffle must be of the same type as the result of the 8283 // current shuffle. 8284 assert(OtherSV->getOperand(0).getValueType() == VT && 8285 "Shuffle types don't match"); 8286 8287 for (unsigned i = 0; i != NumElts; ++i) { 8288 int Idx = SVN->getMaskElt(i); 8289 assert(Idx < (int)NumElts && "Index references undef operand"); 8290 // Next, this index comes from the first value, which is the incoming 8291 // shuffle. Adopt the incoming index. 8292 if (Idx >= 0) 8293 Idx = OtherSV->getMaskElt(Idx); 8294 8295 // The combined shuffle must map each index to itself. 8296 if (Idx >= 0 && (unsigned)Idx != i) 8297 return SDValue(); 8298 } 8299 8300 return OtherSV->getOperand(0); 8301 } 8302 8303 return SDValue(); 8304} 8305 8306SDValue DAGCombiner::visitMEMBARRIER(SDNode* N) { 8307 if (!TLI.getShouldFoldAtomicFences()) 8308 return SDValue(); 8309 8310 SDValue atomic = N->getOperand(0); 8311 switch (atomic.getOpcode()) { 8312 case ISD::ATOMIC_CMP_SWAP: 8313 case ISD::ATOMIC_SWAP: 8314 case ISD::ATOMIC_LOAD_ADD: 8315 case ISD::ATOMIC_LOAD_SUB: 8316 case ISD::ATOMIC_LOAD_AND: 8317 case ISD::ATOMIC_LOAD_OR: 8318 case ISD::ATOMIC_LOAD_XOR: 8319 case ISD::ATOMIC_LOAD_NAND: 8320 case ISD::ATOMIC_LOAD_MIN: 8321 case ISD::ATOMIC_LOAD_MAX: 8322 case ISD::ATOMIC_LOAD_UMIN: 8323 case ISD::ATOMIC_LOAD_UMAX: 8324 break; 8325 default: 8326 return SDValue(); 8327 } 8328 8329 SDValue fence = atomic.getOperand(0); 8330 if (fence.getOpcode() != ISD::MEMBARRIER) 8331 return SDValue(); 8332 8333 switch (atomic.getOpcode()) { 8334 case ISD::ATOMIC_CMP_SWAP: 8335 return SDValue(DAG.UpdateNodeOperands(atomic.getNode(), 8336 fence.getOperand(0), 8337 atomic.getOperand(1), atomic.getOperand(2), 8338 atomic.getOperand(3)), atomic.getResNo()); 8339 case ISD::ATOMIC_SWAP: 8340 case ISD::ATOMIC_LOAD_ADD: 8341 case ISD::ATOMIC_LOAD_SUB: 8342 case ISD::ATOMIC_LOAD_AND: 8343 case ISD::ATOMIC_LOAD_OR: 8344 case ISD::ATOMIC_LOAD_XOR: 8345 case ISD::ATOMIC_LOAD_NAND: 8346 case ISD::ATOMIC_LOAD_MIN: 8347 case ISD::ATOMIC_LOAD_MAX: 8348 case ISD::ATOMIC_LOAD_UMIN: 8349 case ISD::ATOMIC_LOAD_UMAX: 8350 return SDValue(DAG.UpdateNodeOperands(atomic.getNode(), 8351 fence.getOperand(0), 8352 atomic.getOperand(1), atomic.getOperand(2)), 8353 atomic.getResNo()); 8354 default: 8355 return SDValue(); 8356 } 8357} 8358 8359/// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform 8360/// an AND to a vector_shuffle with the destination vector and a zero vector. 8361/// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==> 8362/// vector_shuffle V, Zero, <0, 4, 2, 4> 8363SDValue DAGCombiner::XformToShuffleWithZero(SDNode *N) { 8364 EVT VT = N->getValueType(0); 8365 DebugLoc dl = N->getDebugLoc(); 8366 SDValue LHS = N->getOperand(0); 8367 SDValue RHS = N->getOperand(1); 8368 if (N->getOpcode() == ISD::AND) { 8369 if (RHS.getOpcode() == ISD::BITCAST) 8370 RHS = RHS.getOperand(0); 8371 if (RHS.getOpcode() == ISD::BUILD_VECTOR) { 8372 SmallVector<int, 8> Indices; 8373 unsigned NumElts = RHS.getNumOperands(); 8374 for (unsigned i = 0; i != NumElts; ++i) { 8375 SDValue Elt = RHS.getOperand(i); 8376 if (!isa<ConstantSDNode>(Elt)) 8377 return SDValue(); 8378 8379 if (cast<ConstantSDNode>(Elt)->isAllOnesValue()) 8380 Indices.push_back(i); 8381 else if (cast<ConstantSDNode>(Elt)->isNullValue()) 8382 Indices.push_back(NumElts); 8383 else 8384 return SDValue(); 8385 } 8386 8387 // Let's see if the target supports this vector_shuffle. 8388 EVT RVT = RHS.getValueType(); 8389 if (!TLI.isVectorClearMaskLegal(Indices, RVT)) 8390 return SDValue(); 8391 8392 // Return the new VECTOR_SHUFFLE node. 8393 EVT EltVT = RVT.getVectorElementType(); 8394 SmallVector<SDValue,8> ZeroOps(RVT.getVectorNumElements(), 8395 DAG.getConstant(0, EltVT)); 8396 SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 8397 RVT, &ZeroOps[0], ZeroOps.size()); 8398 LHS = DAG.getNode(ISD::BITCAST, dl, RVT, LHS); 8399 SDValue Shuf = DAG.getVectorShuffle(RVT, dl, LHS, Zero, &Indices[0]); 8400 return DAG.getNode(ISD::BITCAST, dl, VT, Shuf); 8401 } 8402 } 8403 8404 return SDValue(); 8405} 8406 8407/// SimplifyVBinOp - Visit a binary vector operation, like ADD. 8408SDValue DAGCombiner::SimplifyVBinOp(SDNode *N) { 8409 // After legalize, the target may be depending on adds and other 8410 // binary ops to provide legal ways to construct constants or other 8411 // things. Simplifying them may result in a loss of legality. 8412 if (LegalOperations) return SDValue(); 8413 8414 assert(N->getValueType(0).isVector() && 8415 "SimplifyVBinOp only works on vectors!"); 8416 8417 SDValue LHS = N->getOperand(0); 8418 SDValue RHS = N->getOperand(1); 8419 SDValue Shuffle = XformToShuffleWithZero(N); 8420 if (Shuffle.getNode()) return Shuffle; 8421 8422 // If the LHS and RHS are BUILD_VECTOR nodes, see if we can constant fold 8423 // this operation. 8424 if (LHS.getOpcode() == ISD::BUILD_VECTOR && 8425 RHS.getOpcode() == ISD::BUILD_VECTOR) { 8426 SmallVector<SDValue, 8> Ops; 8427 for (unsigned i = 0, e = LHS.getNumOperands(); i != e; ++i) { 8428 SDValue LHSOp = LHS.getOperand(i); 8429 SDValue RHSOp = RHS.getOperand(i); 8430 // If these two elements can't be folded, bail out. 8431 if ((LHSOp.getOpcode() != ISD::UNDEF && 8432 LHSOp.getOpcode() != ISD::Constant && 8433 LHSOp.getOpcode() != ISD::ConstantFP) || 8434 (RHSOp.getOpcode() != ISD::UNDEF && 8435 RHSOp.getOpcode() != ISD::Constant && 8436 RHSOp.getOpcode() != ISD::ConstantFP)) 8437 break; 8438 8439 // Can't fold divide by zero. 8440 if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV || 8441 N->getOpcode() == ISD::FDIV) { 8442 if ((RHSOp.getOpcode() == ISD::Constant && 8443 cast<ConstantSDNode>(RHSOp.getNode())->isNullValue()) || 8444 (RHSOp.getOpcode() == ISD::ConstantFP && 8445 cast<ConstantFPSDNode>(RHSOp.getNode())->getValueAPF().isZero())) 8446 break; 8447 } 8448 8449 EVT VT = LHSOp.getValueType(); 8450 EVT RVT = RHSOp.getValueType(); 8451 if (RVT != VT) { 8452 // Integer BUILD_VECTOR operands may have types larger than the element 8453 // size (e.g., when the element type is not legal). Prior to type 8454 // legalization, the types may not match between the two BUILD_VECTORS. 8455 // Truncate one of the operands to make them match. 8456 if (RVT.getSizeInBits() > VT.getSizeInBits()) { 8457 RHSOp = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, RHSOp); 8458 } else { 8459 LHSOp = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), RVT, LHSOp); 8460 VT = RVT; 8461 } 8462 } 8463 SDValue FoldOp = DAG.getNode(N->getOpcode(), LHS.getDebugLoc(), VT, 8464 LHSOp, RHSOp); 8465 if (FoldOp.getOpcode() != ISD::UNDEF && 8466 FoldOp.getOpcode() != ISD::Constant && 8467 FoldOp.getOpcode() != ISD::ConstantFP) 8468 break; 8469 Ops.push_back(FoldOp); 8470 AddToWorkList(FoldOp.getNode()); 8471 } 8472 8473 if (Ops.size() == LHS.getNumOperands()) 8474 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 8475 LHS.getValueType(), &Ops[0], Ops.size()); 8476 } 8477 8478 return SDValue(); 8479} 8480 8481/// SimplifyVUnaryOp - Visit a binary vector operation, like FABS/FNEG. 8482SDValue DAGCombiner::SimplifyVUnaryOp(SDNode *N) { 8483 // After legalize, the target may be depending on adds and other 8484 // binary ops to provide legal ways to construct constants or other 8485 // things. Simplifying them may result in a loss of legality. 8486 if (LegalOperations) return SDValue(); 8487 8488 assert(N->getValueType(0).isVector() && 8489 "SimplifyVUnaryOp only works on vectors!"); 8490 8491 SDValue N0 = N->getOperand(0); 8492 8493 if (N0.getOpcode() != ISD::BUILD_VECTOR) 8494 return SDValue(); 8495 8496 // Operand is a BUILD_VECTOR node, see if we can constant fold it. 8497 SmallVector<SDValue, 8> Ops; 8498 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i) { 8499 SDValue Op = N0.getOperand(i); 8500 if (Op.getOpcode() != ISD::UNDEF && 8501 Op.getOpcode() != ISD::ConstantFP) 8502 break; 8503 EVT EltVT = Op.getValueType(); 8504 SDValue FoldOp = DAG.getNode(N->getOpcode(), N0.getDebugLoc(), EltVT, Op); 8505 if (FoldOp.getOpcode() != ISD::UNDEF && 8506 FoldOp.getOpcode() != ISD::ConstantFP) 8507 break; 8508 Ops.push_back(FoldOp); 8509 AddToWorkList(FoldOp.getNode()); 8510 } 8511 8512 if (Ops.size() != N0.getNumOperands()) 8513 return SDValue(); 8514 8515 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 8516 N0.getValueType(), &Ops[0], Ops.size()); 8517} 8518 8519SDValue DAGCombiner::SimplifySelect(DebugLoc DL, SDValue N0, 8520 SDValue N1, SDValue N2){ 8521 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!"); 8522 8523 SDValue SCC = SimplifySelectCC(DL, N0.getOperand(0), N0.getOperand(1), N1, N2, 8524 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 8525 8526 // If we got a simplified select_cc node back from SimplifySelectCC, then 8527 // break it down into a new SETCC node, and a new SELECT node, and then return 8528 // the SELECT node, since we were called with a SELECT node. 8529 if (SCC.getNode()) { 8530 // Check to see if we got a select_cc back (to turn into setcc/select). 8531 // Otherwise, just return whatever node we got back, like fabs. 8532 if (SCC.getOpcode() == ISD::SELECT_CC) { 8533 SDValue SETCC = DAG.getNode(ISD::SETCC, N0.getDebugLoc(), 8534 N0.getValueType(), 8535 SCC.getOperand(0), SCC.getOperand(1), 8536 SCC.getOperand(4)); 8537 AddToWorkList(SETCC.getNode()); 8538 return DAG.getNode(ISD::SELECT, SCC.getDebugLoc(), SCC.getValueType(), 8539 SCC.getOperand(2), SCC.getOperand(3), SETCC); 8540 } 8541 8542 return SCC; 8543 } 8544 return SDValue(); 8545} 8546 8547/// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS 8548/// are the two values being selected between, see if we can simplify the 8549/// select. Callers of this should assume that TheSelect is deleted if this 8550/// returns true. As such, they should return the appropriate thing (e.g. the 8551/// node) back to the top-level of the DAG combiner loop to avoid it being 8552/// looked at. 8553bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDValue LHS, 8554 SDValue RHS) { 8555 8556 // Cannot simplify select with vector condition 8557 if (TheSelect->getOperand(0).getValueType().isVector()) return false; 8558 8559 // If this is a select from two identical things, try to pull the operation 8560 // through the select. 8561 if (LHS.getOpcode() != RHS.getOpcode() || 8562 !LHS.hasOneUse() || !RHS.hasOneUse()) 8563 return false; 8564 8565 // If this is a load and the token chain is identical, replace the select 8566 // of two loads with a load through a select of the address to load from. 8567 // This triggers in things like "select bool X, 10.0, 123.0" after the FP 8568 // constants have been dropped into the constant pool. 8569 if (LHS.getOpcode() == ISD::LOAD) { 8570 LoadSDNode *LLD = cast<LoadSDNode>(LHS); 8571 LoadSDNode *RLD = cast<LoadSDNode>(RHS); 8572 8573 // Token chains must be identical. 8574 if (LHS.getOperand(0) != RHS.getOperand(0) || 8575 // Do not let this transformation reduce the number of volatile loads. 8576 LLD->isVolatile() || RLD->isVolatile() || 8577 // If this is an EXTLOAD, the VT's must match. 8578 LLD->getMemoryVT() != RLD->getMemoryVT() || 8579 // If this is an EXTLOAD, the kind of extension must match. 8580 (LLD->getExtensionType() != RLD->getExtensionType() && 8581 // The only exception is if one of the extensions is anyext. 8582 LLD->getExtensionType() != ISD::EXTLOAD && 8583 RLD->getExtensionType() != ISD::EXTLOAD) || 8584 // FIXME: this discards src value information. This is 8585 // over-conservative. It would be beneficial to be able to remember 8586 // both potential memory locations. Since we are discarding 8587 // src value info, don't do the transformation if the memory 8588 // locations are not in the default address space. 8589 LLD->getPointerInfo().getAddrSpace() != 0 || 8590 RLD->getPointerInfo().getAddrSpace() != 0) 8591 return false; 8592 8593 // Check that the select condition doesn't reach either load. If so, 8594 // folding this will induce a cycle into the DAG. If not, this is safe to 8595 // xform, so create a select of the addresses. 8596 SDValue Addr; 8597 if (TheSelect->getOpcode() == ISD::SELECT) { 8598 SDNode *CondNode = TheSelect->getOperand(0).getNode(); 8599 if ((LLD->hasAnyUseOfValue(1) && LLD->isPredecessorOf(CondNode)) || 8600 (RLD->hasAnyUseOfValue(1) && RLD->isPredecessorOf(CondNode))) 8601 return false; 8602 Addr = DAG.getNode(ISD::SELECT, TheSelect->getDebugLoc(), 8603 LLD->getBasePtr().getValueType(), 8604 TheSelect->getOperand(0), LLD->getBasePtr(), 8605 RLD->getBasePtr()); 8606 } else { // Otherwise SELECT_CC 8607 SDNode *CondLHS = TheSelect->getOperand(0).getNode(); 8608 SDNode *CondRHS = TheSelect->getOperand(1).getNode(); 8609 8610 if ((LLD->hasAnyUseOfValue(1) && 8611 (LLD->isPredecessorOf(CondLHS) || LLD->isPredecessorOf(CondRHS))) || 8612 (RLD->hasAnyUseOfValue(1) && 8613 (RLD->isPredecessorOf(CondLHS) || RLD->isPredecessorOf(CondRHS)))) 8614 return false; 8615 8616 Addr = DAG.getNode(ISD::SELECT_CC, TheSelect->getDebugLoc(), 8617 LLD->getBasePtr().getValueType(), 8618 TheSelect->getOperand(0), 8619 TheSelect->getOperand(1), 8620 LLD->getBasePtr(), RLD->getBasePtr(), 8621 TheSelect->getOperand(4)); 8622 } 8623 8624 SDValue Load; 8625 if (LLD->getExtensionType() == ISD::NON_EXTLOAD) { 8626 Load = DAG.getLoad(TheSelect->getValueType(0), 8627 TheSelect->getDebugLoc(), 8628 // FIXME: Discards pointer info. 8629 LLD->getChain(), Addr, MachinePointerInfo(), 8630 LLD->isVolatile(), LLD->isNonTemporal(), 8631 LLD->isInvariant(), LLD->getAlignment()); 8632 } else { 8633 Load = DAG.getExtLoad(LLD->getExtensionType() == ISD::EXTLOAD ? 8634 RLD->getExtensionType() : LLD->getExtensionType(), 8635 TheSelect->getDebugLoc(), 8636 TheSelect->getValueType(0), 8637 // FIXME: Discards pointer info. 8638 LLD->getChain(), Addr, MachinePointerInfo(), 8639 LLD->getMemoryVT(), LLD->isVolatile(), 8640 LLD->isNonTemporal(), LLD->getAlignment()); 8641 } 8642 8643 // Users of the select now use the result of the load. 8644 CombineTo(TheSelect, Load); 8645 8646 // Users of the old loads now use the new load's chain. We know the 8647 // old-load value is dead now. 8648 CombineTo(LHS.getNode(), Load.getValue(0), Load.getValue(1)); 8649 CombineTo(RHS.getNode(), Load.getValue(0), Load.getValue(1)); 8650 return true; 8651 } 8652 8653 return false; 8654} 8655 8656/// SimplifySelectCC - Simplify an expression of the form (N0 cond N1) ? N2 : N3 8657/// where 'cond' is the comparison specified by CC. 8658SDValue DAGCombiner::SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, 8659 SDValue N2, SDValue N3, 8660 ISD::CondCode CC, bool NotExtCompare) { 8661 // (x ? y : y) -> y. 8662 if (N2 == N3) return N2; 8663 8664 EVT VT = N2.getValueType(); 8665 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 8666 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode()); 8667 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.getNode()); 8668 8669 // Determine if the condition we're dealing with is constant 8670 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()), 8671 N0, N1, CC, DL, false); 8672 if (SCC.getNode()) AddToWorkList(SCC.getNode()); 8673 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode()); 8674 8675 // fold select_cc true, x, y -> x 8676 if (SCCC && !SCCC->isNullValue()) 8677 return N2; 8678 // fold select_cc false, x, y -> y 8679 if (SCCC && SCCC->isNullValue()) 8680 return N3; 8681 8682 // Check to see if we can simplify the select into an fabs node 8683 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) { 8684 // Allow either -0.0 or 0.0 8685 if (CFP->getValueAPF().isZero()) { 8686 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs 8687 if ((CC == ISD::SETGE || CC == ISD::SETGT) && 8688 N0 == N2 && N3.getOpcode() == ISD::FNEG && 8689 N2 == N3.getOperand(0)) 8690 return DAG.getNode(ISD::FABS, DL, VT, N0); 8691 8692 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs 8693 if ((CC == ISD::SETLT || CC == ISD::SETLE) && 8694 N0 == N3 && N2.getOpcode() == ISD::FNEG && 8695 N2.getOperand(0) == N3) 8696 return DAG.getNode(ISD::FABS, DL, VT, N3); 8697 } 8698 } 8699 8700 // Turn "(a cond b) ? 1.0f : 2.0f" into "load (tmp + ((a cond b) ? 0 : 4)" 8701 // where "tmp" is a constant pool entry containing an array with 1.0 and 2.0 8702 // in it. This is a win when the constant is not otherwise available because 8703 // it replaces two constant pool loads with one. We only do this if the FP 8704 // type is known to be legal, because if it isn't, then we are before legalize 8705 // types an we want the other legalization to happen first (e.g. to avoid 8706 // messing with soft float) and if the ConstantFP is not legal, because if 8707 // it is legal, we may not need to store the FP constant in a constant pool. 8708 if (ConstantFPSDNode *TV = dyn_cast<ConstantFPSDNode>(N2)) 8709 if (ConstantFPSDNode *FV = dyn_cast<ConstantFPSDNode>(N3)) { 8710 if (TLI.isTypeLegal(N2.getValueType()) && 8711 (TLI.getOperationAction(ISD::ConstantFP, N2.getValueType()) != 8712 TargetLowering::Legal) && 8713 // If both constants have multiple uses, then we won't need to do an 8714 // extra load, they are likely around in registers for other users. 8715 (TV->hasOneUse() || FV->hasOneUse())) { 8716 Constant *Elts[] = { 8717 const_cast<ConstantFP*>(FV->getConstantFPValue()), 8718 const_cast<ConstantFP*>(TV->getConstantFPValue()) 8719 }; 8720 Type *FPTy = Elts[0]->getType(); 8721 const TargetData &TD = *TLI.getTargetData(); 8722 8723 // Create a ConstantArray of the two constants. 8724 Constant *CA = ConstantArray::get(ArrayType::get(FPTy, 2), Elts); 8725 SDValue CPIdx = DAG.getConstantPool(CA, TLI.getPointerTy(), 8726 TD.getPrefTypeAlignment(FPTy)); 8727 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 8728 8729 // Get the offsets to the 0 and 1 element of the array so that we can 8730 // select between them. 8731 SDValue Zero = DAG.getIntPtrConstant(0); 8732 unsigned EltSize = (unsigned)TD.getTypeAllocSize(Elts[0]->getType()); 8733 SDValue One = DAG.getIntPtrConstant(EltSize); 8734 8735 SDValue Cond = DAG.getSetCC(DL, 8736 TLI.getSetCCResultType(N0.getValueType()), 8737 N0, N1, CC); 8738 AddToWorkList(Cond.getNode()); 8739 SDValue CstOffset = DAG.getNode(ISD::SELECT, DL, Zero.getValueType(), 8740 Cond, One, Zero); 8741 AddToWorkList(CstOffset.getNode()); 8742 CPIdx = DAG.getNode(ISD::ADD, DL, TLI.getPointerTy(), CPIdx, 8743 CstOffset); 8744 AddToWorkList(CPIdx.getNode()); 8745 return DAG.getLoad(TV->getValueType(0), DL, DAG.getEntryNode(), CPIdx, 8746 MachinePointerInfo::getConstantPool(), false, 8747 false, false, Alignment); 8748 8749 } 8750 } 8751 8752 // Check to see if we can perform the "gzip trick", transforming 8753 // (select_cc setlt X, 0, A, 0) -> (and (sra X, (sub size(X), 1), A) 8754 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT && 8755 (N1C->isNullValue() || // (a < 0) ? b : 0 8756 (N1C->getAPIntValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0 8757 EVT XType = N0.getValueType(); 8758 EVT AType = N2.getValueType(); 8759 if (XType.bitsGE(AType)) { 8760 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a 8761 // single-bit constant. 8762 if (N2C && ((N2C->getAPIntValue() & (N2C->getAPIntValue()-1)) == 0)) { 8763 unsigned ShCtV = N2C->getAPIntValue().logBase2(); 8764 ShCtV = XType.getSizeInBits()-ShCtV-1; 8765 SDValue ShCt = DAG.getConstant(ShCtV, 8766 getShiftAmountTy(N0.getValueType())); 8767 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), 8768 XType, N0, ShCt); 8769 AddToWorkList(Shift.getNode()); 8770 8771 if (XType.bitsGT(AType)) { 8772 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift); 8773 AddToWorkList(Shift.getNode()); 8774 } 8775 8776 return DAG.getNode(ISD::AND, DL, AType, Shift, N2); 8777 } 8778 8779 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), 8780 XType, N0, 8781 DAG.getConstant(XType.getSizeInBits()-1, 8782 getShiftAmountTy(N0.getValueType()))); 8783 AddToWorkList(Shift.getNode()); 8784 8785 if (XType.bitsGT(AType)) { 8786 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift); 8787 AddToWorkList(Shift.getNode()); 8788 } 8789 8790 return DAG.getNode(ISD::AND, DL, AType, Shift, N2); 8791 } 8792 } 8793 8794 // fold (select_cc seteq (and x, y), 0, 0, A) -> (and (shr (shl x)) A) 8795 // where y is has a single bit set. 8796 // A plaintext description would be, we can turn the SELECT_CC into an AND 8797 // when the condition can be materialized as an all-ones register. Any 8798 // single bit-test can be materialized as an all-ones register with 8799 // shift-left and shift-right-arith. 8800 if (CC == ISD::SETEQ && N0->getOpcode() == ISD::AND && 8801 N0->getValueType(0) == VT && 8802 N1C && N1C->isNullValue() && 8803 N2C && N2C->isNullValue()) { 8804 SDValue AndLHS = N0->getOperand(0); 8805 ConstantSDNode *ConstAndRHS = dyn_cast<ConstantSDNode>(N0->getOperand(1)); 8806 if (ConstAndRHS && ConstAndRHS->getAPIntValue().countPopulation() == 1) { 8807 // Shift the tested bit over the sign bit. 8808 APInt AndMask = ConstAndRHS->getAPIntValue(); 8809 SDValue ShlAmt = 8810 DAG.getConstant(AndMask.countLeadingZeros(), 8811 getShiftAmountTy(AndLHS.getValueType())); 8812 SDValue Shl = DAG.getNode(ISD::SHL, N0.getDebugLoc(), VT, AndLHS, ShlAmt); 8813 8814 // Now arithmetic right shift it all the way over, so the result is either 8815 // all-ones, or zero. 8816 SDValue ShrAmt = 8817 DAG.getConstant(AndMask.getBitWidth()-1, 8818 getShiftAmountTy(Shl.getValueType())); 8819 SDValue Shr = DAG.getNode(ISD::SRA, N0.getDebugLoc(), VT, Shl, ShrAmt); 8820 8821 return DAG.getNode(ISD::AND, DL, VT, Shr, N3); 8822 } 8823 } 8824 8825 // fold select C, 16, 0 -> shl C, 4 8826 if (N2C && N3C && N3C->isNullValue() && N2C->getAPIntValue().isPowerOf2() && 8827 TLI.getBooleanContents(N0.getValueType().isVector()) == 8828 TargetLowering::ZeroOrOneBooleanContent) { 8829 8830 // If the caller doesn't want us to simplify this into a zext of a compare, 8831 // don't do it. 8832 if (NotExtCompare && N2C->getAPIntValue() == 1) 8833 return SDValue(); 8834 8835 // Get a SetCC of the condition 8836 // FIXME: Should probably make sure that setcc is legal if we ever have a 8837 // target where it isn't. 8838 SDValue Temp, SCC; 8839 // cast from setcc result type to select result type 8840 if (LegalTypes) { 8841 SCC = DAG.getSetCC(DL, TLI.getSetCCResultType(N0.getValueType()), 8842 N0, N1, CC); 8843 if (N2.getValueType().bitsLT(SCC.getValueType())) 8844 Temp = DAG.getZeroExtendInReg(SCC, N2.getDebugLoc(), N2.getValueType()); 8845 else 8846 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(), 8847 N2.getValueType(), SCC); 8848 } else { 8849 SCC = DAG.getSetCC(N0.getDebugLoc(), MVT::i1, N0, N1, CC); 8850 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(), 8851 N2.getValueType(), SCC); 8852 } 8853 8854 AddToWorkList(SCC.getNode()); 8855 AddToWorkList(Temp.getNode()); 8856 8857 if (N2C->getAPIntValue() == 1) 8858 return Temp; 8859 8860 // shl setcc result by log2 n2c 8861 return DAG.getNode(ISD::SHL, DL, N2.getValueType(), Temp, 8862 DAG.getConstant(N2C->getAPIntValue().logBase2(), 8863 getShiftAmountTy(Temp.getValueType()))); 8864 } 8865 8866 // Check to see if this is the equivalent of setcc 8867 // FIXME: Turn all of these into setcc if setcc if setcc is legal 8868 // otherwise, go ahead with the folds. 8869 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getAPIntValue() == 1ULL)) { 8870 EVT XType = N0.getValueType(); 8871 if (!LegalOperations || 8872 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(XType))) { 8873 SDValue Res = DAG.getSetCC(DL, TLI.getSetCCResultType(XType), N0, N1, CC); 8874 if (Res.getValueType() != VT) 8875 Res = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, Res); 8876 return Res; 8877 } 8878 8879 // fold (seteq X, 0) -> (srl (ctlz X, log2(size(X)))) 8880 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ && 8881 (!LegalOperations || 8882 TLI.isOperationLegal(ISD::CTLZ, XType))) { 8883 SDValue Ctlz = DAG.getNode(ISD::CTLZ, N0.getDebugLoc(), XType, N0); 8884 return DAG.getNode(ISD::SRL, DL, XType, Ctlz, 8885 DAG.getConstant(Log2_32(XType.getSizeInBits()), 8886 getShiftAmountTy(Ctlz.getValueType()))); 8887 } 8888 // fold (setgt X, 0) -> (srl (and (-X, ~X), size(X)-1)) 8889 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) { 8890 SDValue NegN0 = DAG.getNode(ISD::SUB, N0.getDebugLoc(), 8891 XType, DAG.getConstant(0, XType), N0); 8892 SDValue NotN0 = DAG.getNOT(N0.getDebugLoc(), N0, XType); 8893 return DAG.getNode(ISD::SRL, DL, XType, 8894 DAG.getNode(ISD::AND, DL, XType, NegN0, NotN0), 8895 DAG.getConstant(XType.getSizeInBits()-1, 8896 getShiftAmountTy(XType))); 8897 } 8898 // fold (setgt X, -1) -> (xor (srl (X, size(X)-1), 1)) 8899 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) { 8900 SDValue Sign = DAG.getNode(ISD::SRL, N0.getDebugLoc(), XType, N0, 8901 DAG.getConstant(XType.getSizeInBits()-1, 8902 getShiftAmountTy(N0.getValueType()))); 8903 return DAG.getNode(ISD::XOR, DL, XType, Sign, DAG.getConstant(1, XType)); 8904 } 8905 } 8906 8907 // Check to see if this is an integer abs. 8908 // select_cc setg[te] X, 0, X, -X -> 8909 // select_cc setgt X, -1, X, -X -> 8910 // select_cc setl[te] X, 0, -X, X -> 8911 // select_cc setlt X, 1, -X, X -> 8912 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 8913 if (N1C) { 8914 ConstantSDNode *SubC = NULL; 8915 if (((N1C->isNullValue() && (CC == ISD::SETGT || CC == ISD::SETGE)) || 8916 (N1C->isAllOnesValue() && CC == ISD::SETGT)) && 8917 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1)) 8918 SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0)); 8919 else if (((N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE)) || 8920 (N1C->isOne() && CC == ISD::SETLT)) && 8921 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1)) 8922 SubC = dyn_cast<ConstantSDNode>(N2.getOperand(0)); 8923 8924 EVT XType = N0.getValueType(); 8925 if (SubC && SubC->isNullValue() && XType.isInteger()) { 8926 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), XType, 8927 N0, 8928 DAG.getConstant(XType.getSizeInBits()-1, 8929 getShiftAmountTy(N0.getValueType()))); 8930 SDValue Add = DAG.getNode(ISD::ADD, N0.getDebugLoc(), 8931 XType, N0, Shift); 8932 AddToWorkList(Shift.getNode()); 8933 AddToWorkList(Add.getNode()); 8934 return DAG.getNode(ISD::XOR, DL, XType, Add, Shift); 8935 } 8936 } 8937 8938 return SDValue(); 8939} 8940 8941/// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC. 8942SDValue DAGCombiner::SimplifySetCC(EVT VT, SDValue N0, 8943 SDValue N1, ISD::CondCode Cond, 8944 DebugLoc DL, bool foldBooleans) { 8945 TargetLowering::DAGCombinerInfo 8946 DagCombineInfo(DAG, !LegalTypes, !LegalOperations, false, this); 8947 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo, DL); 8948} 8949 8950/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 8951/// return a DAG expression to select that will generate the same value by 8952/// multiplying by a magic number. See: 8953/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 8954SDValue DAGCombiner::BuildSDIV(SDNode *N) { 8955 std::vector<SDNode*> Built; 8956 SDValue S = TLI.BuildSDIV(N, DAG, LegalOperations, &Built); 8957 8958 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 8959 ii != ee; ++ii) 8960 AddToWorkList(*ii); 8961 return S; 8962} 8963 8964/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 8965/// return a DAG expression to select that will generate the same value by 8966/// multiplying by a magic number. See: 8967/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 8968SDValue DAGCombiner::BuildUDIV(SDNode *N) { 8969 std::vector<SDNode*> Built; 8970 SDValue S = TLI.BuildUDIV(N, DAG, LegalOperations, &Built); 8971 8972 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 8973 ii != ee; ++ii) 8974 AddToWorkList(*ii); 8975 return S; 8976} 8977 8978/// FindBaseOffset - Return true if base is a frame index, which is known not 8979// to alias with anything but itself. Provides base object and offset as 8980// results. 8981static bool FindBaseOffset(SDValue Ptr, SDValue &Base, int64_t &Offset, 8982 const GlobalValue *&GV, const void *&CV) { 8983 // Assume it is a primitive operation. 8984 Base = Ptr; Offset = 0; GV = 0; CV = 0; 8985 8986 // If it's an adding a simple constant then integrate the offset. 8987 if (Base.getOpcode() == ISD::ADD) { 8988 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) { 8989 Base = Base.getOperand(0); 8990 Offset += C->getZExtValue(); 8991 } 8992 } 8993 8994 // Return the underlying GlobalValue, and update the Offset. Return false 8995 // for GlobalAddressSDNode since the same GlobalAddress may be represented 8996 // by multiple nodes with different offsets. 8997 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Base)) { 8998 GV = G->getGlobal(); 8999 Offset += G->getOffset(); 9000 return false; 9001 } 9002 9003 // Return the underlying Constant value, and update the Offset. Return false 9004 // for ConstantSDNodes since the same constant pool entry may be represented 9005 // by multiple nodes with different offsets. 9006 if (ConstantPoolSDNode *C = dyn_cast<ConstantPoolSDNode>(Base)) { 9007 CV = C->isMachineConstantPoolEntry() ? (const void *)C->getMachineCPVal() 9008 : (const void *)C->getConstVal(); 9009 Offset += C->getOffset(); 9010 return false; 9011 } 9012 // If it's any of the following then it can't alias with anything but itself. 9013 return isa<FrameIndexSDNode>(Base); 9014} 9015 9016/// isAlias - Return true if there is any possibility that the two addresses 9017/// overlap. 9018bool DAGCombiner::isAlias(SDValue Ptr1, int64_t Size1, 9019 const Value *SrcValue1, int SrcValueOffset1, 9020 unsigned SrcValueAlign1, 9021 const MDNode *TBAAInfo1, 9022 SDValue Ptr2, int64_t Size2, 9023 const Value *SrcValue2, int SrcValueOffset2, 9024 unsigned SrcValueAlign2, 9025 const MDNode *TBAAInfo2) const { 9026 // If they are the same then they must be aliases. 9027 if (Ptr1 == Ptr2) return true; 9028 9029 // Gather base node and offset information. 9030 SDValue Base1, Base2; 9031 int64_t Offset1, Offset2; 9032 const GlobalValue *GV1, *GV2; 9033 const void *CV1, *CV2; 9034 bool isFrameIndex1 = FindBaseOffset(Ptr1, Base1, Offset1, GV1, CV1); 9035 bool isFrameIndex2 = FindBaseOffset(Ptr2, Base2, Offset2, GV2, CV2); 9036 9037 // If they have a same base address then check to see if they overlap. 9038 if (Base1 == Base2 || (GV1 && (GV1 == GV2)) || (CV1 && (CV1 == CV2))) 9039 return !((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1); 9040 9041 // It is possible for different frame indices to alias each other, mostly 9042 // when tail call optimization reuses return address slots for arguments. 9043 // To catch this case, look up the actual index of frame indices to compute 9044 // the real alias relationship. 9045 if (isFrameIndex1 && isFrameIndex2) { 9046 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 9047 Offset1 += MFI->getObjectOffset(cast<FrameIndexSDNode>(Base1)->getIndex()); 9048 Offset2 += MFI->getObjectOffset(cast<FrameIndexSDNode>(Base2)->getIndex()); 9049 return !((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1); 9050 } 9051 9052 // Otherwise, if we know what the bases are, and they aren't identical, then 9053 // we know they cannot alias. 9054 if ((isFrameIndex1 || CV1 || GV1) && (isFrameIndex2 || CV2 || GV2)) 9055 return false; 9056 9057 // If we know required SrcValue1 and SrcValue2 have relatively large alignment 9058 // compared to the size and offset of the access, we may be able to prove they 9059 // do not alias. This check is conservative for now to catch cases created by 9060 // splitting vector types. 9061 if ((SrcValueAlign1 == SrcValueAlign2) && 9062 (SrcValueOffset1 != SrcValueOffset2) && 9063 (Size1 == Size2) && (SrcValueAlign1 > Size1)) { 9064 int64_t OffAlign1 = SrcValueOffset1 % SrcValueAlign1; 9065 int64_t OffAlign2 = SrcValueOffset2 % SrcValueAlign1; 9066 9067 // There is no overlap between these relatively aligned accesses of similar 9068 // size, return no alias. 9069 if ((OffAlign1 + Size1) <= OffAlign2 || (OffAlign2 + Size2) <= OffAlign1) 9070 return false; 9071 } 9072 9073 if (CombinerGlobalAA) { 9074 // Use alias analysis information. 9075 int64_t MinOffset = std::min(SrcValueOffset1, SrcValueOffset2); 9076 int64_t Overlap1 = Size1 + SrcValueOffset1 - MinOffset; 9077 int64_t Overlap2 = Size2 + SrcValueOffset2 - MinOffset; 9078 AliasAnalysis::AliasResult AAResult = 9079 AA.alias(AliasAnalysis::Location(SrcValue1, Overlap1, TBAAInfo1), 9080 AliasAnalysis::Location(SrcValue2, Overlap2, TBAAInfo2)); 9081 if (AAResult == AliasAnalysis::NoAlias) 9082 return false; 9083 } 9084 9085 // Otherwise we have to assume they alias. 9086 return true; 9087} 9088 9089/// FindAliasInfo - Extracts the relevant alias information from the memory 9090/// node. Returns true if the operand was a load. 9091bool DAGCombiner::FindAliasInfo(SDNode *N, 9092 SDValue &Ptr, int64_t &Size, 9093 const Value *&SrcValue, 9094 int &SrcValueOffset, 9095 unsigned &SrcValueAlign, 9096 const MDNode *&TBAAInfo) const { 9097 LSBaseSDNode *LS = cast<LSBaseSDNode>(N); 9098 9099 Ptr = LS->getBasePtr(); 9100 Size = LS->getMemoryVT().getSizeInBits() >> 3; 9101 SrcValue = LS->getSrcValue(); 9102 SrcValueOffset = LS->getSrcValueOffset(); 9103 SrcValueAlign = LS->getOriginalAlignment(); 9104 TBAAInfo = LS->getTBAAInfo(); 9105 return isa<LoadSDNode>(LS); 9106} 9107 9108/// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 9109/// looking for aliasing nodes and adding them to the Aliases vector. 9110void DAGCombiner::GatherAllAliases(SDNode *N, SDValue OriginalChain, 9111 SmallVector<SDValue, 8> &Aliases) { 9112 SmallVector<SDValue, 8> Chains; // List of chains to visit. 9113 SmallPtrSet<SDNode *, 16> Visited; // Visited node set. 9114 9115 // Get alias information for node. 9116 SDValue Ptr; 9117 int64_t Size; 9118 const Value *SrcValue; 9119 int SrcValueOffset; 9120 unsigned SrcValueAlign; 9121 const MDNode *SrcTBAAInfo; 9122 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset, 9123 SrcValueAlign, SrcTBAAInfo); 9124 9125 // Starting off. 9126 Chains.push_back(OriginalChain); 9127 unsigned Depth = 0; 9128 9129 // Look at each chain and determine if it is an alias. If so, add it to the 9130 // aliases list. If not, then continue up the chain looking for the next 9131 // candidate. 9132 while (!Chains.empty()) { 9133 SDValue Chain = Chains.back(); 9134 Chains.pop_back(); 9135 9136 // For TokenFactor nodes, look at each operand and only continue up the 9137 // chain until we find two aliases. If we've seen two aliases, assume we'll 9138 // find more and revert to original chain since the xform is unlikely to be 9139 // profitable. 9140 // 9141 // FIXME: The depth check could be made to return the last non-aliasing 9142 // chain we found before we hit a tokenfactor rather than the original 9143 // chain. 9144 if (Depth > 6 || Aliases.size() == 2) { 9145 Aliases.clear(); 9146 Aliases.push_back(OriginalChain); 9147 break; 9148 } 9149 9150 // Don't bother if we've been before. 9151 if (!Visited.insert(Chain.getNode())) 9152 continue; 9153 9154 switch (Chain.getOpcode()) { 9155 case ISD::EntryToken: 9156 // Entry token is ideal chain operand, but handled in FindBetterChain. 9157 break; 9158 9159 case ISD::LOAD: 9160 case ISD::STORE: { 9161 // Get alias information for Chain. 9162 SDValue OpPtr; 9163 int64_t OpSize; 9164 const Value *OpSrcValue; 9165 int OpSrcValueOffset; 9166 unsigned OpSrcValueAlign; 9167 const MDNode *OpSrcTBAAInfo; 9168 bool IsOpLoad = FindAliasInfo(Chain.getNode(), OpPtr, OpSize, 9169 OpSrcValue, OpSrcValueOffset, 9170 OpSrcValueAlign, 9171 OpSrcTBAAInfo); 9172 9173 // If chain is alias then stop here. 9174 if (!(IsLoad && IsOpLoad) && 9175 isAlias(Ptr, Size, SrcValue, SrcValueOffset, SrcValueAlign, 9176 SrcTBAAInfo, 9177 OpPtr, OpSize, OpSrcValue, OpSrcValueOffset, 9178 OpSrcValueAlign, OpSrcTBAAInfo)) { 9179 Aliases.push_back(Chain); 9180 } else { 9181 // Look further up the chain. 9182 Chains.push_back(Chain.getOperand(0)); 9183 ++Depth; 9184 } 9185 break; 9186 } 9187 9188 case ISD::TokenFactor: 9189 // We have to check each of the operands of the token factor for "small" 9190 // token factors, so we queue them up. Adding the operands to the queue 9191 // (stack) in reverse order maintains the original order and increases the 9192 // likelihood that getNode will find a matching token factor (CSE.) 9193 if (Chain.getNumOperands() > 16) { 9194 Aliases.push_back(Chain); 9195 break; 9196 } 9197 for (unsigned n = Chain.getNumOperands(); n;) 9198 Chains.push_back(Chain.getOperand(--n)); 9199 ++Depth; 9200 break; 9201 9202 default: 9203 // For all other instructions we will just have to take what we can get. 9204 Aliases.push_back(Chain); 9205 break; 9206 } 9207 } 9208} 9209 9210/// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking 9211/// for a better chain (aliasing node.) 9212SDValue DAGCombiner::FindBetterChain(SDNode *N, SDValue OldChain) { 9213 SmallVector<SDValue, 8> Aliases; // Ops for replacing token factor. 9214 9215 // Accumulate all the aliases to this node. 9216 GatherAllAliases(N, OldChain, Aliases); 9217 9218 // If no operands then chain to entry token. 9219 if (Aliases.size() == 0) 9220 return DAG.getEntryNode(); 9221 9222 // If a single operand then chain to it. We don't need to revisit it. 9223 if (Aliases.size() == 1) 9224 return Aliases[0]; 9225 9226 // Construct a custom tailored token factor. 9227 return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, 9228 &Aliases[0], Aliases.size()); 9229} 9230 9231// SelectionDAG::Combine - This is the entry point for the file. 9232// 9233void SelectionDAG::Combine(CombineLevel Level, AliasAnalysis &AA, 9234 CodeGenOpt::Level OptLevel) { 9235 /// run - This is the main entry point to this class. 9236 /// 9237 DAGCombiner(*this, AA, OptLevel).Run(Level); 9238} 9239