DAGCombiner.cpp revision efcddc33256512a08d7182783e2262da27f27cdd
1//===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run 11// both before and after the DAG is legalized. 12// 13// This pass is not a substitute for the LLVM IR instcombine pass. This pass is 14// primarily intended to handle simplification opportunities that are implicit 15// in the LLVM IR and exposed by the various codegen lowering phases. 16// 17//===----------------------------------------------------------------------===// 18 19#define DEBUG_TYPE "dagcombine" 20#include "llvm/CodeGen/SelectionDAG.h" 21#include "llvm/DerivedTypes.h" 22#include "llvm/LLVMContext.h" 23#include "llvm/CodeGen/MachineFunction.h" 24#include "llvm/CodeGen/MachineFrameInfo.h" 25#include "llvm/CodeGen/PseudoSourceValue.h" 26#include "llvm/Analysis/AliasAnalysis.h" 27#include "llvm/Target/TargetData.h" 28#include "llvm/Target/TargetFrameInfo.h" 29#include "llvm/Target/TargetLowering.h" 30#include "llvm/Target/TargetMachine.h" 31#include "llvm/Target/TargetOptions.h" 32#include "llvm/ADT/SmallPtrSet.h" 33#include "llvm/ADT/Statistic.h" 34#include "llvm/Support/CommandLine.h" 35#include "llvm/Support/Debug.h" 36#include "llvm/Support/ErrorHandling.h" 37#include "llvm/Support/MathExtras.h" 38#include "llvm/Support/raw_ostream.h" 39#include <algorithm> 40using namespace llvm; 41 42STATISTIC(NodesCombined , "Number of dag nodes combined"); 43STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created"); 44STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created"); 45STATISTIC(OpsNarrowed , "Number of load/op/store narrowed"); 46 47namespace { 48 static cl::opt<bool> 49 CombinerAA("combiner-alias-analysis", cl::Hidden, 50 cl::desc("Turn on alias analysis during testing")); 51 52 static cl::opt<bool> 53 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden, 54 cl::desc("Include global information in alias analysis")); 55 56//------------------------------ DAGCombiner ---------------------------------// 57 58 class DAGCombiner { 59 SelectionDAG &DAG; 60 const TargetLowering &TLI; 61 CombineLevel Level; 62 CodeGenOpt::Level OptLevel; 63 bool LegalOperations; 64 bool LegalTypes; 65 66 // Worklist of all of the nodes that need to be simplified. 67 std::vector<SDNode*> WorkList; 68 69 // AA - Used for DAG load/store alias analysis. 70 AliasAnalysis &AA; 71 72 /// AddUsersToWorkList - When an instruction is simplified, add all users of 73 /// the instruction to the work lists because they might get more simplified 74 /// now. 75 /// 76 void AddUsersToWorkList(SDNode *N) { 77 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 78 UI != UE; ++UI) 79 AddToWorkList(*UI); 80 } 81 82 /// visit - call the node-specific routine that knows how to fold each 83 /// particular type of node. 84 SDValue visit(SDNode *N); 85 86 public: 87 /// AddToWorkList - Add to the work list making sure it's instance is at the 88 /// the back (next to be processed.) 89 void AddToWorkList(SDNode *N) { 90 removeFromWorkList(N); 91 WorkList.push_back(N); 92 } 93 94 /// removeFromWorkList - remove all instances of N from the worklist. 95 /// 96 void removeFromWorkList(SDNode *N) { 97 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N), 98 WorkList.end()); 99 } 100 101 SDValue CombineTo(SDNode *N, const SDValue *To, unsigned NumTo, 102 bool AddTo = true); 103 104 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true) { 105 return CombineTo(N, &Res, 1, AddTo); 106 } 107 108 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, 109 bool AddTo = true) { 110 SDValue To[] = { Res0, Res1 }; 111 return CombineTo(N, To, 2, AddTo); 112 } 113 114 void CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO); 115 116 private: 117 118 /// SimplifyDemandedBits - Check the specified integer node value to see if 119 /// it can be simplified or if things it uses can be simplified by bit 120 /// propagation. If so, return true. 121 bool SimplifyDemandedBits(SDValue Op) { 122 unsigned BitWidth = Op.getValueType().getScalarType().getSizeInBits(); 123 APInt Demanded = APInt::getAllOnesValue(BitWidth); 124 return SimplifyDemandedBits(Op, Demanded); 125 } 126 127 bool SimplifyDemandedBits(SDValue Op, const APInt &Demanded); 128 129 bool CombineToPreIndexedLoadStore(SDNode *N); 130 bool CombineToPostIndexedLoadStore(SDNode *N); 131 132 133 /// combine - call the node-specific routine that knows how to fold each 134 /// particular type of node. If that doesn't do anything, try the 135 /// target-specific DAG combines. 136 SDValue combine(SDNode *N); 137 138 // Visitation implementation - Implement dag node combining for different 139 // node types. The semantics are as follows: 140 // Return Value: 141 // SDValue.getNode() == 0 - No change was made 142 // SDValue.getNode() == N - N was replaced, is dead and has been handled. 143 // otherwise - N should be replaced by the returned Operand. 144 // 145 SDValue visitTokenFactor(SDNode *N); 146 SDValue visitMERGE_VALUES(SDNode *N); 147 SDValue visitADD(SDNode *N); 148 SDValue visitSUB(SDNode *N); 149 SDValue visitADDC(SDNode *N); 150 SDValue visitADDE(SDNode *N); 151 SDValue visitMUL(SDNode *N); 152 SDValue visitSDIV(SDNode *N); 153 SDValue visitUDIV(SDNode *N); 154 SDValue visitSREM(SDNode *N); 155 SDValue visitUREM(SDNode *N); 156 SDValue visitMULHU(SDNode *N); 157 SDValue visitMULHS(SDNode *N); 158 SDValue visitSMUL_LOHI(SDNode *N); 159 SDValue visitUMUL_LOHI(SDNode *N); 160 SDValue visitSDIVREM(SDNode *N); 161 SDValue visitUDIVREM(SDNode *N); 162 SDValue visitAND(SDNode *N); 163 SDValue visitOR(SDNode *N); 164 SDValue visitXOR(SDNode *N); 165 SDValue SimplifyVBinOp(SDNode *N); 166 SDValue visitSHL(SDNode *N); 167 SDValue visitSRA(SDNode *N); 168 SDValue visitSRL(SDNode *N); 169 SDValue visitCTLZ(SDNode *N); 170 SDValue visitCTTZ(SDNode *N); 171 SDValue visitCTPOP(SDNode *N); 172 SDValue visitSELECT(SDNode *N); 173 SDValue visitSELECT_CC(SDNode *N); 174 SDValue visitSETCC(SDNode *N); 175 SDValue visitSIGN_EXTEND(SDNode *N); 176 SDValue visitZERO_EXTEND(SDNode *N); 177 SDValue visitANY_EXTEND(SDNode *N); 178 SDValue visitSIGN_EXTEND_INREG(SDNode *N); 179 SDValue visitTRUNCATE(SDNode *N); 180 SDValue visitBIT_CONVERT(SDNode *N); 181 SDValue visitBUILD_PAIR(SDNode *N); 182 SDValue visitFADD(SDNode *N); 183 SDValue visitFSUB(SDNode *N); 184 SDValue visitFMUL(SDNode *N); 185 SDValue visitFDIV(SDNode *N); 186 SDValue visitFREM(SDNode *N); 187 SDValue visitFCOPYSIGN(SDNode *N); 188 SDValue visitSINT_TO_FP(SDNode *N); 189 SDValue visitUINT_TO_FP(SDNode *N); 190 SDValue visitFP_TO_SINT(SDNode *N); 191 SDValue visitFP_TO_UINT(SDNode *N); 192 SDValue visitFP_ROUND(SDNode *N); 193 SDValue visitFP_ROUND_INREG(SDNode *N); 194 SDValue visitFP_EXTEND(SDNode *N); 195 SDValue visitFNEG(SDNode *N); 196 SDValue visitFABS(SDNode *N); 197 SDValue visitBRCOND(SDNode *N); 198 SDValue visitBR_CC(SDNode *N); 199 SDValue visitLOAD(SDNode *N); 200 SDValue visitSTORE(SDNode *N); 201 SDValue visitINSERT_VECTOR_ELT(SDNode *N); 202 SDValue visitEXTRACT_VECTOR_ELT(SDNode *N); 203 SDValue visitBUILD_VECTOR(SDNode *N); 204 SDValue visitCONCAT_VECTORS(SDNode *N); 205 SDValue visitVECTOR_SHUFFLE(SDNode *N); 206 207 SDValue XformToShuffleWithZero(SDNode *N); 208 SDValue ReassociateOps(unsigned Opc, DebugLoc DL, SDValue LHS, SDValue RHS); 209 210 SDValue visitShiftByConstant(SDNode *N, unsigned Amt); 211 212 bool SimplifySelectOps(SDNode *SELECT, SDValue LHS, SDValue RHS); 213 SDValue SimplifyBinOpWithSameOpcodeHands(SDNode *N); 214 SDValue SimplifySelect(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2); 215 SDValue SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2, 216 SDValue N3, ISD::CondCode CC, 217 bool NotExtCompare = false); 218 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond, 219 DebugLoc DL, bool foldBooleans = true); 220 SDValue SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 221 unsigned HiOp); 222 SDValue CombineConsecutiveLoads(SDNode *N, EVT VT); 223 SDValue ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *, EVT); 224 SDValue BuildSDIV(SDNode *N); 225 SDValue BuildUDIV(SDNode *N); 226 SDNode *MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL); 227 SDValue ReduceLoadWidth(SDNode *N); 228 SDValue ReduceLoadOpStoreWidth(SDNode *N); 229 230 SDValue GetDemandedBits(SDValue V, const APInt &Mask); 231 232 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 233 /// looking for aliasing nodes and adding them to the Aliases vector. 234 void GatherAllAliases(SDNode *N, SDValue OriginalChain, 235 SmallVector<SDValue, 8> &Aliases); 236 237 /// isAlias - Return true if there is any possibility that the two addresses 238 /// overlap. 239 bool isAlias(SDValue Ptr1, int64_t Size1, 240 const Value *SrcValue1, int SrcValueOffset1, 241 unsigned SrcValueAlign1, 242 SDValue Ptr2, int64_t Size2, 243 const Value *SrcValue2, int SrcValueOffset2, 244 unsigned SrcValueAlign2) const; 245 246 /// FindAliasInfo - Extracts the relevant alias information from the memory 247 /// node. Returns true if the operand was a load. 248 bool FindAliasInfo(SDNode *N, 249 SDValue &Ptr, int64_t &Size, 250 const Value *&SrcValue, int &SrcValueOffset, 251 unsigned &SrcValueAlignment) const; 252 253 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, 254 /// looking for a better chain (aliasing node.) 255 SDValue FindBetterChain(SDNode *N, SDValue Chain); 256 257 public: 258 DAGCombiner(SelectionDAG &D, AliasAnalysis &A, CodeGenOpt::Level OL) 259 : DAG(D), TLI(D.getTargetLoweringInfo()), Level(Unrestricted), 260 OptLevel(OL), LegalOperations(false), LegalTypes(false), AA(A) {} 261 262 /// Run - runs the dag combiner on all nodes in the work list 263 void Run(CombineLevel AtLevel); 264 265 SelectionDAG &getDAG() const { return DAG; } 266 267 /// getShiftAmountTy - Returns a type large enough to hold any valid 268 /// shift amount - before type legalization these can be huge. 269 EVT getShiftAmountTy() { 270 return LegalTypes ? TLI.getShiftAmountTy() : TLI.getPointerTy(); 271 } 272 273 /// isTypeLegal - This method returns true if we are running before type 274 /// legalization or if the specified VT is legal. 275 bool isTypeLegal(const EVT &VT) { 276 if (!LegalTypes) return true; 277 return TLI.isTypeLegal(VT); 278 } 279 }; 280} 281 282 283namespace { 284/// WorkListRemover - This class is a DAGUpdateListener that removes any deleted 285/// nodes from the worklist. 286class WorkListRemover : public SelectionDAG::DAGUpdateListener { 287 DAGCombiner &DC; 288public: 289 explicit WorkListRemover(DAGCombiner &dc) : DC(dc) {} 290 291 virtual void NodeDeleted(SDNode *N, SDNode *E) { 292 DC.removeFromWorkList(N); 293 } 294 295 virtual void NodeUpdated(SDNode *N) { 296 // Ignore updates. 297 } 298}; 299} 300 301//===----------------------------------------------------------------------===// 302// TargetLowering::DAGCombinerInfo implementation 303//===----------------------------------------------------------------------===// 304 305void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) { 306 ((DAGCombiner*)DC)->AddToWorkList(N); 307} 308 309SDValue TargetLowering::DAGCombinerInfo:: 310CombineTo(SDNode *N, const std::vector<SDValue> &To, bool AddTo) { 311 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size(), AddTo); 312} 313 314SDValue TargetLowering::DAGCombinerInfo:: 315CombineTo(SDNode *N, SDValue Res, bool AddTo) { 316 return ((DAGCombiner*)DC)->CombineTo(N, Res, AddTo); 317} 318 319 320SDValue TargetLowering::DAGCombinerInfo:: 321CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo) { 322 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1, AddTo); 323} 324 325void TargetLowering::DAGCombinerInfo:: 326CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt &TLO) { 327 return ((DAGCombiner*)DC)->CommitTargetLoweringOpt(TLO); 328} 329 330//===----------------------------------------------------------------------===// 331// Helper Functions 332//===----------------------------------------------------------------------===// 333 334/// isNegatibleForFree - Return 1 if we can compute the negated form of the 335/// specified expression for the same cost as the expression itself, or 2 if we 336/// can compute the negated form more cheaply than the expression itself. 337static char isNegatibleForFree(SDValue Op, bool LegalOperations, 338 unsigned Depth = 0) { 339 // No compile time optimizations on this type. 340 if (Op.getValueType() == MVT::ppcf128) 341 return 0; 342 343 // fneg is removable even if it has multiple uses. 344 if (Op.getOpcode() == ISD::FNEG) return 2; 345 346 // Don't allow anything with multiple uses. 347 if (!Op.hasOneUse()) return 0; 348 349 // Don't recurse exponentially. 350 if (Depth > 6) return 0; 351 352 switch (Op.getOpcode()) { 353 default: return false; 354 case ISD::ConstantFP: 355 // Don't invert constant FP values after legalize. The negated constant 356 // isn't necessarily legal. 357 return LegalOperations ? 0 : 1; 358 case ISD::FADD: 359 // FIXME: determine better conditions for this xform. 360 if (!UnsafeFPMath) return 0; 361 362 // fold (fsub (fadd A, B)) -> (fsub (fneg A), B) 363 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 364 return V; 365 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A) 366 return isNegatibleForFree(Op.getOperand(1), LegalOperations, Depth+1); 367 case ISD::FSUB: 368 // We can't turn -(A-B) into B-A when we honor signed zeros. 369 if (!UnsafeFPMath) return 0; 370 371 // fold (fneg (fsub A, B)) -> (fsub B, A) 372 return 1; 373 374 case ISD::FMUL: 375 case ISD::FDIV: 376 if (HonorSignDependentRoundingFPMath()) return 0; 377 378 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) or (fmul X, (fneg Y)) 379 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 380 return V; 381 382 return isNegatibleForFree(Op.getOperand(1), LegalOperations, Depth+1); 383 384 case ISD::FP_EXTEND: 385 case ISD::FP_ROUND: 386 case ISD::FSIN: 387 return isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1); 388 } 389} 390 391/// GetNegatedExpression - If isNegatibleForFree returns true, this function 392/// returns the newly negated expression. 393static SDValue GetNegatedExpression(SDValue Op, SelectionDAG &DAG, 394 bool LegalOperations, unsigned Depth = 0) { 395 // fneg is removable even if it has multiple uses. 396 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0); 397 398 // Don't allow anything with multiple uses. 399 assert(Op.hasOneUse() && "Unknown reuse!"); 400 401 assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree"); 402 switch (Op.getOpcode()) { 403 default: llvm_unreachable("Unknown code"); 404 case ISD::ConstantFP: { 405 APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF(); 406 V.changeSign(); 407 return DAG.getConstantFP(V, Op.getValueType()); 408 } 409 case ISD::FADD: 410 // FIXME: determine better conditions for this xform. 411 assert(UnsafeFPMath); 412 413 // fold (fneg (fadd A, B)) -> (fsub (fneg A), B) 414 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 415 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 416 GetNegatedExpression(Op.getOperand(0), DAG, 417 LegalOperations, Depth+1), 418 Op.getOperand(1)); 419 // fold (fneg (fadd A, B)) -> (fsub (fneg B), A) 420 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 421 GetNegatedExpression(Op.getOperand(1), DAG, 422 LegalOperations, Depth+1), 423 Op.getOperand(0)); 424 case ISD::FSUB: 425 // We can't turn -(A-B) into B-A when we honor signed zeros. 426 assert(UnsafeFPMath); 427 428 // fold (fneg (fsub 0, B)) -> B 429 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(Op.getOperand(0))) 430 if (N0CFP->getValueAPF().isZero()) 431 return Op.getOperand(1); 432 433 // fold (fneg (fsub A, B)) -> (fsub B, A) 434 return DAG.getNode(ISD::FSUB, Op.getDebugLoc(), Op.getValueType(), 435 Op.getOperand(1), Op.getOperand(0)); 436 437 case ISD::FMUL: 438 case ISD::FDIV: 439 assert(!HonorSignDependentRoundingFPMath()); 440 441 // fold (fneg (fmul X, Y)) -> (fmul (fneg X), Y) 442 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 443 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 444 GetNegatedExpression(Op.getOperand(0), DAG, 445 LegalOperations, Depth+1), 446 Op.getOperand(1)); 447 448 // fold (fneg (fmul X, Y)) -> (fmul X, (fneg Y)) 449 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 450 Op.getOperand(0), 451 GetNegatedExpression(Op.getOperand(1), DAG, 452 LegalOperations, Depth+1)); 453 454 case ISD::FP_EXTEND: 455 case ISD::FSIN: 456 return DAG.getNode(Op.getOpcode(), Op.getDebugLoc(), Op.getValueType(), 457 GetNegatedExpression(Op.getOperand(0), DAG, 458 LegalOperations, Depth+1)); 459 case ISD::FP_ROUND: 460 return DAG.getNode(ISD::FP_ROUND, Op.getDebugLoc(), Op.getValueType(), 461 GetNegatedExpression(Op.getOperand(0), DAG, 462 LegalOperations, Depth+1), 463 Op.getOperand(1)); 464 } 465} 466 467 468// isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc 469// that selects between the values 1 and 0, making it equivalent to a setcc. 470// Also, set the incoming LHS, RHS, and CC references to the appropriate 471// nodes based on the type of node we are checking. This simplifies life a 472// bit for the callers. 473static bool isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS, 474 SDValue &CC) { 475 if (N.getOpcode() == ISD::SETCC) { 476 LHS = N.getOperand(0); 477 RHS = N.getOperand(1); 478 CC = N.getOperand(2); 479 return true; 480 } 481 if (N.getOpcode() == ISD::SELECT_CC && 482 N.getOperand(2).getOpcode() == ISD::Constant && 483 N.getOperand(3).getOpcode() == ISD::Constant && 484 cast<ConstantSDNode>(N.getOperand(2))->getAPIntValue() == 1 && 485 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) { 486 LHS = N.getOperand(0); 487 RHS = N.getOperand(1); 488 CC = N.getOperand(4); 489 return true; 490 } 491 return false; 492} 493 494// isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only 495// one use. If this is true, it allows the users to invert the operation for 496// free when it is profitable to do so. 497static bool isOneUseSetCC(SDValue N) { 498 SDValue N0, N1, N2; 499 if (isSetCCEquivalent(N, N0, N1, N2) && N.getNode()->hasOneUse()) 500 return true; 501 return false; 502} 503 504SDValue DAGCombiner::ReassociateOps(unsigned Opc, DebugLoc DL, 505 SDValue N0, SDValue N1) { 506 EVT VT = N0.getValueType(); 507 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) { 508 if (isa<ConstantSDNode>(N1)) { 509 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2)) 510 SDValue OpNode = 511 DAG.FoldConstantArithmetic(Opc, VT, 512 cast<ConstantSDNode>(N0.getOperand(1)), 513 cast<ConstantSDNode>(N1)); 514 return DAG.getNode(Opc, DL, VT, N0.getOperand(0), OpNode); 515 } else if (N0.hasOneUse()) { 516 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use 517 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT, 518 N0.getOperand(0), N1); 519 AddToWorkList(OpNode.getNode()); 520 return DAG.getNode(Opc, DL, VT, OpNode, N0.getOperand(1)); 521 } 522 } 523 524 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) { 525 if (isa<ConstantSDNode>(N0)) { 526 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2)) 527 SDValue OpNode = 528 DAG.FoldConstantArithmetic(Opc, VT, 529 cast<ConstantSDNode>(N1.getOperand(1)), 530 cast<ConstantSDNode>(N0)); 531 return DAG.getNode(Opc, DL, VT, N1.getOperand(0), OpNode); 532 } else if (N1.hasOneUse()) { 533 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use 534 SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT, 535 N1.getOperand(0), N0); 536 AddToWorkList(OpNode.getNode()); 537 return DAG.getNode(Opc, DL, VT, OpNode, N1.getOperand(1)); 538 } 539 } 540 541 return SDValue(); 542} 543 544SDValue DAGCombiner::CombineTo(SDNode *N, const SDValue *To, unsigned NumTo, 545 bool AddTo) { 546 assert(N->getNumValues() == NumTo && "Broken CombineTo call!"); 547 ++NodesCombined; 548 DEBUG(dbgs() << "\nReplacing.1 "; 549 N->dump(&DAG); 550 dbgs() << "\nWith: "; 551 To[0].getNode()->dump(&DAG); 552 dbgs() << " and " << NumTo-1 << " other values\n"; 553 for (unsigned i = 0, e = NumTo; i != e; ++i) 554 assert((!To[i].getNode() || 555 N->getValueType(i) == To[i].getValueType()) && 556 "Cannot combine value to value of different type!")); 557 WorkListRemover DeadNodes(*this); 558 DAG.ReplaceAllUsesWith(N, To, &DeadNodes); 559 560 if (AddTo) { 561 // Push the new nodes and any users onto the worklist 562 for (unsigned i = 0, e = NumTo; i != e; ++i) { 563 if (To[i].getNode()) { 564 AddToWorkList(To[i].getNode()); 565 AddUsersToWorkList(To[i].getNode()); 566 } 567 } 568 } 569 570 // Finally, if the node is now dead, remove it from the graph. The node 571 // may not be dead if the replacement process recursively simplified to 572 // something else needing this node. 573 if (N->use_empty()) { 574 // Nodes can be reintroduced into the worklist. Make sure we do not 575 // process a node that has been replaced. 576 removeFromWorkList(N); 577 578 // Finally, since the node is now dead, remove it from the graph. 579 DAG.DeleteNode(N); 580 } 581 return SDValue(N, 0); 582} 583 584void 585DAGCombiner::CommitTargetLoweringOpt(const TargetLowering::TargetLoweringOpt & 586 TLO) { 587 // Replace all uses. If any nodes become isomorphic to other nodes and 588 // are deleted, make sure to remove them from our worklist. 589 WorkListRemover DeadNodes(*this); 590 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &DeadNodes); 591 592 // Push the new node and any (possibly new) users onto the worklist. 593 AddToWorkList(TLO.New.getNode()); 594 AddUsersToWorkList(TLO.New.getNode()); 595 596 // Finally, if the node is now dead, remove it from the graph. The node 597 // may not be dead if the replacement process recursively simplified to 598 // something else needing this node. 599 if (TLO.Old.getNode()->use_empty()) { 600 removeFromWorkList(TLO.Old.getNode()); 601 602 // If the operands of this node are only used by the node, they will now 603 // be dead. Make sure to visit them first to delete dead nodes early. 604 for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands(); i != e; ++i) 605 if (TLO.Old.getNode()->getOperand(i).getNode()->hasOneUse()) 606 AddToWorkList(TLO.Old.getNode()->getOperand(i).getNode()); 607 608 DAG.DeleteNode(TLO.Old.getNode()); 609 } 610} 611 612/// SimplifyDemandedBits - Check the specified integer node value to see if 613/// it can be simplified or if things it uses can be simplified by bit 614/// propagation. If so, return true. 615bool DAGCombiner::SimplifyDemandedBits(SDValue Op, const APInt &Demanded) { 616 TargetLowering::TargetLoweringOpt TLO(DAG); 617 APInt KnownZero, KnownOne; 618 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO)) 619 return false; 620 621 // Revisit the node. 622 AddToWorkList(Op.getNode()); 623 624 // Replace the old value with the new one. 625 ++NodesCombined; 626 DEBUG(dbgs() << "\nReplacing.2 "; 627 TLO.Old.getNode()->dump(&DAG); 628 dbgs() << "\nWith: "; 629 TLO.New.getNode()->dump(&DAG); 630 dbgs() << '\n'); 631 632 CommitTargetLoweringOpt(TLO); 633 return true; 634} 635 636//===----------------------------------------------------------------------===// 637// Main DAG Combiner implementation 638//===----------------------------------------------------------------------===// 639 640void DAGCombiner::Run(CombineLevel AtLevel) { 641 // set the instance variables, so that the various visit routines may use it. 642 Level = AtLevel; 643 LegalOperations = Level >= NoIllegalOperations; 644 LegalTypes = Level >= NoIllegalTypes; 645 646 // Add all the dag nodes to the worklist. 647 WorkList.reserve(DAG.allnodes_size()); 648 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 649 E = DAG.allnodes_end(); I != E; ++I) 650 WorkList.push_back(I); 651 652 // Create a dummy node (which is not added to allnodes), that adds a reference 653 // to the root node, preventing it from being deleted, and tracking any 654 // changes of the root. 655 HandleSDNode Dummy(DAG.getRoot()); 656 657 // The root of the dag may dangle to deleted nodes until the dag combiner is 658 // done. Set it to null to avoid confusion. 659 DAG.setRoot(SDValue()); 660 661 // while the worklist isn't empty, inspect the node on the end of it and 662 // try and combine it. 663 while (!WorkList.empty()) { 664 SDNode *N = WorkList.back(); 665 WorkList.pop_back(); 666 667 // If N has no uses, it is dead. Make sure to revisit all N's operands once 668 // N is deleted from the DAG, since they too may now be dead or may have a 669 // reduced number of uses, allowing other xforms. 670 if (N->use_empty() && N != &Dummy) { 671 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 672 AddToWorkList(N->getOperand(i).getNode()); 673 674 DAG.DeleteNode(N); 675 continue; 676 } 677 678 SDValue RV = combine(N); 679 680 if (RV.getNode() == 0) 681 continue; 682 683 ++NodesCombined; 684 685 // If we get back the same node we passed in, rather than a new node or 686 // zero, we know that the node must have defined multiple values and 687 // CombineTo was used. Since CombineTo takes care of the worklist 688 // mechanics for us, we have no work to do in this case. 689 if (RV.getNode() == N) 690 continue; 691 692 assert(N->getOpcode() != ISD::DELETED_NODE && 693 RV.getNode()->getOpcode() != ISD::DELETED_NODE && 694 "Node was deleted but visit returned new node!"); 695 696 DEBUG(dbgs() << "\nReplacing.3 "; 697 N->dump(&DAG); 698 dbgs() << "\nWith: "; 699 RV.getNode()->dump(&DAG); 700 dbgs() << '\n'); 701 WorkListRemover DeadNodes(*this); 702 if (N->getNumValues() == RV.getNode()->getNumValues()) 703 DAG.ReplaceAllUsesWith(N, RV.getNode(), &DeadNodes); 704 else { 705 assert(N->getValueType(0) == RV.getValueType() && 706 N->getNumValues() == 1 && "Type mismatch"); 707 SDValue OpV = RV; 708 DAG.ReplaceAllUsesWith(N, &OpV, &DeadNodes); 709 } 710 711 // Push the new node and any users onto the worklist 712 AddToWorkList(RV.getNode()); 713 AddUsersToWorkList(RV.getNode()); 714 715 // Add any uses of the old node to the worklist in case this node is the 716 // last one that uses them. They may become dead after this node is 717 // deleted. 718 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 719 AddToWorkList(N->getOperand(i).getNode()); 720 721 // Finally, if the node is now dead, remove it from the graph. The node 722 // may not be dead if the replacement process recursively simplified to 723 // something else needing this node. 724 if (N->use_empty()) { 725 // Nodes can be reintroduced into the worklist. Make sure we do not 726 // process a node that has been replaced. 727 removeFromWorkList(N); 728 729 // Finally, since the node is now dead, remove it from the graph. 730 DAG.DeleteNode(N); 731 } 732 } 733 734 // If the root changed (e.g. it was a dead load, update the root). 735 DAG.setRoot(Dummy.getValue()); 736} 737 738SDValue DAGCombiner::visit(SDNode *N) { 739 switch(N->getOpcode()) { 740 default: break; 741 case ISD::TokenFactor: return visitTokenFactor(N); 742 case ISD::MERGE_VALUES: return visitMERGE_VALUES(N); 743 case ISD::ADD: return visitADD(N); 744 case ISD::SUB: return visitSUB(N); 745 case ISD::ADDC: return visitADDC(N); 746 case ISD::ADDE: return visitADDE(N); 747 case ISD::MUL: return visitMUL(N); 748 case ISD::SDIV: return visitSDIV(N); 749 case ISD::UDIV: return visitUDIV(N); 750 case ISD::SREM: return visitSREM(N); 751 case ISD::UREM: return visitUREM(N); 752 case ISD::MULHU: return visitMULHU(N); 753 case ISD::MULHS: return visitMULHS(N); 754 case ISD::SMUL_LOHI: return visitSMUL_LOHI(N); 755 case ISD::UMUL_LOHI: return visitUMUL_LOHI(N); 756 case ISD::SDIVREM: return visitSDIVREM(N); 757 case ISD::UDIVREM: return visitUDIVREM(N); 758 case ISD::AND: return visitAND(N); 759 case ISD::OR: return visitOR(N); 760 case ISD::XOR: return visitXOR(N); 761 case ISD::SHL: return visitSHL(N); 762 case ISD::SRA: return visitSRA(N); 763 case ISD::SRL: return visitSRL(N); 764 case ISD::CTLZ: return visitCTLZ(N); 765 case ISD::CTTZ: return visitCTTZ(N); 766 case ISD::CTPOP: return visitCTPOP(N); 767 case ISD::SELECT: return visitSELECT(N); 768 case ISD::SELECT_CC: return visitSELECT_CC(N); 769 case ISD::SETCC: return visitSETCC(N); 770 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N); 771 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N); 772 case ISD::ANY_EXTEND: return visitANY_EXTEND(N); 773 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N); 774 case ISD::TRUNCATE: return visitTRUNCATE(N); 775 case ISD::BIT_CONVERT: return visitBIT_CONVERT(N); 776 case ISD::BUILD_PAIR: return visitBUILD_PAIR(N); 777 case ISD::FADD: return visitFADD(N); 778 case ISD::FSUB: return visitFSUB(N); 779 case ISD::FMUL: return visitFMUL(N); 780 case ISD::FDIV: return visitFDIV(N); 781 case ISD::FREM: return visitFREM(N); 782 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N); 783 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N); 784 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N); 785 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N); 786 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N); 787 case ISD::FP_ROUND: return visitFP_ROUND(N); 788 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N); 789 case ISD::FP_EXTEND: return visitFP_EXTEND(N); 790 case ISD::FNEG: return visitFNEG(N); 791 case ISD::FABS: return visitFABS(N); 792 case ISD::BRCOND: return visitBRCOND(N); 793 case ISD::BR_CC: return visitBR_CC(N); 794 case ISD::LOAD: return visitLOAD(N); 795 case ISD::STORE: return visitSTORE(N); 796 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N); 797 case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N); 798 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N); 799 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N); 800 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N); 801 } 802 return SDValue(); 803} 804 805SDValue DAGCombiner::combine(SDNode *N) { 806 SDValue RV = visit(N); 807 808 // If nothing happened, try a target-specific DAG combine. 809 if (RV.getNode() == 0) { 810 assert(N->getOpcode() != ISD::DELETED_NODE && 811 "Node was deleted but visit returned NULL!"); 812 813 if (N->getOpcode() >= ISD::BUILTIN_OP_END || 814 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) { 815 816 // Expose the DAG combiner to the target combiner impls. 817 TargetLowering::DAGCombinerInfo 818 DagCombineInfo(DAG, !LegalTypes, !LegalOperations, false, this); 819 820 RV = TLI.PerformDAGCombine(N, DagCombineInfo); 821 } 822 } 823 824 // If N is a commutative binary node, try commuting it to enable more 825 // sdisel CSE. 826 if (RV.getNode() == 0 && 827 SelectionDAG::isCommutativeBinOp(N->getOpcode()) && 828 N->getNumValues() == 1) { 829 SDValue N0 = N->getOperand(0); 830 SDValue N1 = N->getOperand(1); 831 832 // Constant operands are canonicalized to RHS. 833 if (isa<ConstantSDNode>(N0) || !isa<ConstantSDNode>(N1)) { 834 SDValue Ops[] = { N1, N0 }; 835 SDNode *CSENode = DAG.getNodeIfExists(N->getOpcode(), N->getVTList(), 836 Ops, 2); 837 if (CSENode) 838 return SDValue(CSENode, 0); 839 } 840 } 841 842 return RV; 843} 844 845/// getInputChainForNode - Given a node, return its input chain if it has one, 846/// otherwise return a null sd operand. 847static SDValue getInputChainForNode(SDNode *N) { 848 if (unsigned NumOps = N->getNumOperands()) { 849 if (N->getOperand(0).getValueType() == MVT::Other) 850 return N->getOperand(0); 851 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other) 852 return N->getOperand(NumOps-1); 853 for (unsigned i = 1; i < NumOps-1; ++i) 854 if (N->getOperand(i).getValueType() == MVT::Other) 855 return N->getOperand(i); 856 } 857 return SDValue(); 858} 859 860SDValue DAGCombiner::visitTokenFactor(SDNode *N) { 861 // If N has two operands, where one has an input chain equal to the other, 862 // the 'other' chain is redundant. 863 if (N->getNumOperands() == 2) { 864 if (getInputChainForNode(N->getOperand(0).getNode()) == N->getOperand(1)) 865 return N->getOperand(0); 866 if (getInputChainForNode(N->getOperand(1).getNode()) == N->getOperand(0)) 867 return N->getOperand(1); 868 } 869 870 SmallVector<SDNode *, 8> TFs; // List of token factors to visit. 871 SmallVector<SDValue, 8> Ops; // Ops for replacing token factor. 872 SmallPtrSet<SDNode*, 16> SeenOps; 873 bool Changed = false; // If we should replace this token factor. 874 875 // Start out with this token factor. 876 TFs.push_back(N); 877 878 // Iterate through token factors. The TFs grows when new token factors are 879 // encountered. 880 for (unsigned i = 0; i < TFs.size(); ++i) { 881 SDNode *TF = TFs[i]; 882 883 // Check each of the operands. 884 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) { 885 SDValue Op = TF->getOperand(i); 886 887 switch (Op.getOpcode()) { 888 case ISD::EntryToken: 889 // Entry tokens don't need to be added to the list. They are 890 // rededundant. 891 Changed = true; 892 break; 893 894 case ISD::TokenFactor: 895 if (Op.hasOneUse() && 896 std::find(TFs.begin(), TFs.end(), Op.getNode()) == TFs.end()) { 897 // Queue up for processing. 898 TFs.push_back(Op.getNode()); 899 // Clean up in case the token factor is removed. 900 AddToWorkList(Op.getNode()); 901 Changed = true; 902 break; 903 } 904 // Fall thru 905 906 default: 907 // Only add if it isn't already in the list. 908 if (SeenOps.insert(Op.getNode())) 909 Ops.push_back(Op); 910 else 911 Changed = true; 912 break; 913 } 914 } 915 } 916 917 SDValue Result; 918 919 // If we've change things around then replace token factor. 920 if (Changed) { 921 if (Ops.empty()) { 922 // The entry token is the only possible outcome. 923 Result = DAG.getEntryNode(); 924 } else { 925 // New and improved token factor. 926 Result = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 927 MVT::Other, &Ops[0], Ops.size()); 928 } 929 930 // Don't add users to work list. 931 return CombineTo(N, Result, false); 932 } 933 934 return Result; 935} 936 937/// MERGE_VALUES can always be eliminated. 938SDValue DAGCombiner::visitMERGE_VALUES(SDNode *N) { 939 WorkListRemover DeadNodes(*this); 940 // Replacing results may cause a different MERGE_VALUES to suddenly 941 // be CSE'd with N, and carry its uses with it. Iterate until no 942 // uses remain, to ensure that the node can be safely deleted. 943 do { 944 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 945 DAG.ReplaceAllUsesOfValueWith(SDValue(N, i), N->getOperand(i), 946 &DeadNodes); 947 } while (!N->use_empty()); 948 removeFromWorkList(N); 949 DAG.DeleteNode(N); 950 return SDValue(N, 0); // Return N so it doesn't get rechecked! 951} 952 953static 954SDValue combineShlAddConstant(DebugLoc DL, SDValue N0, SDValue N1, 955 SelectionDAG &DAG) { 956 EVT VT = N0.getValueType(); 957 SDValue N00 = N0.getOperand(0); 958 SDValue N01 = N0.getOperand(1); 959 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01); 960 961 if (N01C && N00.getOpcode() == ISD::ADD && N00.getNode()->hasOneUse() && 962 isa<ConstantSDNode>(N00.getOperand(1))) { 963 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 964 N0 = DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, 965 DAG.getNode(ISD::SHL, N00.getDebugLoc(), VT, 966 N00.getOperand(0), N01), 967 DAG.getNode(ISD::SHL, N01.getDebugLoc(), VT, 968 N00.getOperand(1), N01)); 969 return DAG.getNode(ISD::ADD, DL, VT, N0, N1); 970 } 971 972 return SDValue(); 973} 974 975SDValue DAGCombiner::visitADD(SDNode *N) { 976 SDValue N0 = N->getOperand(0); 977 SDValue N1 = N->getOperand(1); 978 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 979 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 980 EVT VT = N0.getValueType(); 981 982 // fold vector ops 983 if (VT.isVector()) { 984 SDValue FoldedVOp = SimplifyVBinOp(N); 985 if (FoldedVOp.getNode()) return FoldedVOp; 986 } 987 988 // fold (add x, undef) -> undef 989 if (N0.getOpcode() == ISD::UNDEF) 990 return N0; 991 if (N1.getOpcode() == ISD::UNDEF) 992 return N1; 993 // fold (add c1, c2) -> c1+c2 994 if (N0C && N1C) 995 return DAG.FoldConstantArithmetic(ISD::ADD, VT, N0C, N1C); 996 // canonicalize constant to RHS 997 if (N0C && !N1C) 998 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0); 999 // fold (add x, 0) -> x 1000 if (N1C && N1C->isNullValue()) 1001 return N0; 1002 // fold (add Sym, c) -> Sym+c 1003 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0)) 1004 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA) && N1C && 1005 GA->getOpcode() == ISD::GlobalAddress) 1006 return DAG.getGlobalAddress(GA->getGlobal(), VT, 1007 GA->getOffset() + 1008 (uint64_t)N1C->getSExtValue()); 1009 // fold ((c1-A)+c2) -> (c1+c2)-A 1010 if (N1C && N0.getOpcode() == ISD::SUB) 1011 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0))) 1012 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1013 DAG.getConstant(N1C->getAPIntValue()+ 1014 N0C->getAPIntValue(), VT), 1015 N0.getOperand(1)); 1016 // reassociate add 1017 SDValue RADD = ReassociateOps(ISD::ADD, N->getDebugLoc(), N0, N1); 1018 if (RADD.getNode() != 0) 1019 return RADD; 1020 // fold ((0-A) + B) -> B-A 1021 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) && 1022 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue()) 1023 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1, N0.getOperand(1)); 1024 // fold (A + (0-B)) -> A-B 1025 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) && 1026 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue()) 1027 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, N1.getOperand(1)); 1028 // fold (A+(B-A)) -> B 1029 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1)) 1030 return N1.getOperand(0); 1031 // fold ((B-A)+A) -> B 1032 if (N0.getOpcode() == ISD::SUB && N1 == N0.getOperand(1)) 1033 return N0.getOperand(0); 1034 // fold (A+(B-(A+C))) to (B-C) 1035 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD && 1036 N0 == N1.getOperand(1).getOperand(0)) 1037 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0), 1038 N1.getOperand(1).getOperand(1)); 1039 // fold (A+(B-(C+A))) to (B-C) 1040 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD && 1041 N0 == N1.getOperand(1).getOperand(1)) 1042 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1.getOperand(0), 1043 N1.getOperand(1).getOperand(0)); 1044 // fold (A+((B-A)+or-C)) to (B+or-C) 1045 if ((N1.getOpcode() == ISD::SUB || N1.getOpcode() == ISD::ADD) && 1046 N1.getOperand(0).getOpcode() == ISD::SUB && 1047 N0 == N1.getOperand(0).getOperand(1)) 1048 return DAG.getNode(N1.getOpcode(), N->getDebugLoc(), VT, 1049 N1.getOperand(0).getOperand(0), N1.getOperand(1)); 1050 1051 // fold (A-B)+(C-D) to (A+C)-(B+D) when A or C is constant 1052 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB) { 1053 SDValue N00 = N0.getOperand(0); 1054 SDValue N01 = N0.getOperand(1); 1055 SDValue N10 = N1.getOperand(0); 1056 SDValue N11 = N1.getOperand(1); 1057 1058 if (isa<ConstantSDNode>(N00) || isa<ConstantSDNode>(N10)) 1059 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1060 DAG.getNode(ISD::ADD, N0.getDebugLoc(), VT, N00, N10), 1061 DAG.getNode(ISD::ADD, N1.getDebugLoc(), VT, N01, N11)); 1062 } 1063 1064 if (!VT.isVector() && SimplifyDemandedBits(SDValue(N, 0))) 1065 return SDValue(N, 0); 1066 1067 // fold (a+b) -> (a|b) iff a and b share no bits. 1068 if (VT.isInteger() && !VT.isVector()) { 1069 APInt LHSZero, LHSOne; 1070 APInt RHSZero, RHSOne; 1071 APInt Mask = APInt::getAllOnesValue(VT.getScalarType().getSizeInBits()); 1072 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 1073 1074 if (LHSZero.getBoolValue()) { 1075 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 1076 1077 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1078 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1079 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 1080 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 1081 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1); 1082 } 1083 } 1084 1085 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 1086 if (N0.getOpcode() == ISD::SHL && N0.getNode()->hasOneUse()) { 1087 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N0, N1, DAG); 1088 if (Result.getNode()) return Result; 1089 } 1090 if (N1.getOpcode() == ISD::SHL && N1.getNode()->hasOneUse()) { 1091 SDValue Result = combineShlAddConstant(N->getDebugLoc(), N1, N0, DAG); 1092 if (Result.getNode()) return Result; 1093 } 1094 1095 // fold (add x, shl(0 - y, n)) -> sub(x, shl(y, n)) 1096 if (N1.getOpcode() == ISD::SHL && 1097 N1.getOperand(0).getOpcode() == ISD::SUB) 1098 if (ConstantSDNode *C = 1099 dyn_cast<ConstantSDNode>(N1.getOperand(0).getOperand(0))) 1100 if (C->getAPIntValue() == 0) 1101 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, 1102 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1103 N1.getOperand(0).getOperand(1), 1104 N1.getOperand(1))); 1105 if (N0.getOpcode() == ISD::SHL && 1106 N0.getOperand(0).getOpcode() == ISD::SUB) 1107 if (ConstantSDNode *C = 1108 dyn_cast<ConstantSDNode>(N0.getOperand(0).getOperand(0))) 1109 if (C->getAPIntValue() == 0) 1110 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N1, 1111 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1112 N0.getOperand(0).getOperand(1), 1113 N0.getOperand(1))); 1114 1115 return SDValue(); 1116} 1117 1118SDValue DAGCombiner::visitADDC(SDNode *N) { 1119 SDValue N0 = N->getOperand(0); 1120 SDValue N1 = N->getOperand(1); 1121 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1122 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1123 EVT VT = N0.getValueType(); 1124 1125 // If the flag result is dead, turn this into an ADD. 1126 if (N->hasNUsesOfValue(0, 1)) 1127 return CombineTo(N, DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0), 1128 DAG.getNode(ISD::CARRY_FALSE, 1129 N->getDebugLoc(), MVT::Flag)); 1130 1131 // canonicalize constant to RHS. 1132 if (N0C && !N1C) 1133 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0); 1134 1135 // fold (addc x, 0) -> x + no carry out 1136 if (N1C && N1C->isNullValue()) 1137 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, 1138 N->getDebugLoc(), MVT::Flag)); 1139 1140 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits. 1141 APInt LHSZero, LHSOne; 1142 APInt RHSZero, RHSOne; 1143 APInt Mask = APInt::getAllOnesValue(VT.getScalarType().getSizeInBits()); 1144 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 1145 1146 if (LHSZero.getBoolValue()) { 1147 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 1148 1149 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1150 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1151 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 1152 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 1153 return CombineTo(N, DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1), 1154 DAG.getNode(ISD::CARRY_FALSE, 1155 N->getDebugLoc(), MVT::Flag)); 1156 } 1157 1158 return SDValue(); 1159} 1160 1161SDValue DAGCombiner::visitADDE(SDNode *N) { 1162 SDValue N0 = N->getOperand(0); 1163 SDValue N1 = N->getOperand(1); 1164 SDValue CarryIn = N->getOperand(2); 1165 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1166 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1167 1168 // canonicalize constant to RHS 1169 if (N0C && !N1C) 1170 return DAG.getNode(ISD::ADDE, N->getDebugLoc(), N->getVTList(), 1171 N1, N0, CarryIn); 1172 1173 // fold (adde x, y, false) -> (addc x, y) 1174 if (CarryIn.getOpcode() == ISD::CARRY_FALSE) 1175 return DAG.getNode(ISD::ADDC, N->getDebugLoc(), N->getVTList(), N1, N0); 1176 1177 return SDValue(); 1178} 1179 1180SDValue DAGCombiner::visitSUB(SDNode *N) { 1181 SDValue N0 = N->getOperand(0); 1182 SDValue N1 = N->getOperand(1); 1183 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1184 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1185 EVT VT = N0.getValueType(); 1186 1187 // fold vector ops 1188 if (VT.isVector()) { 1189 SDValue FoldedVOp = SimplifyVBinOp(N); 1190 if (FoldedVOp.getNode()) return FoldedVOp; 1191 } 1192 1193 // fold (sub x, x) -> 0 1194 if (N0 == N1) 1195 return DAG.getConstant(0, N->getValueType(0)); 1196 // fold (sub c1, c2) -> c1-c2 1197 if (N0C && N1C) 1198 return DAG.FoldConstantArithmetic(ISD::SUB, VT, N0C, N1C); 1199 // fold (sub x, c) -> (add x, -c) 1200 if (N1C) 1201 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, 1202 DAG.getConstant(-N1C->getAPIntValue(), VT)); 1203 // Canonicalize (sub -1, x) -> ~x, i.e. (xor x, -1) 1204 if (N0C && N0C->isAllOnesValue()) 1205 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0); 1206 // fold (A+B)-A -> B 1207 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1) 1208 return N0.getOperand(1); 1209 // fold (A+B)-B -> A 1210 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1) 1211 return N0.getOperand(0); 1212 // fold ((A+(B+or-C))-B) -> A+or-C 1213 if (N0.getOpcode() == ISD::ADD && 1214 (N0.getOperand(1).getOpcode() == ISD::SUB || 1215 N0.getOperand(1).getOpcode() == ISD::ADD) && 1216 N0.getOperand(1).getOperand(0) == N1) 1217 return DAG.getNode(N0.getOperand(1).getOpcode(), N->getDebugLoc(), VT, 1218 N0.getOperand(0), N0.getOperand(1).getOperand(1)); 1219 // fold ((A+(C+B))-B) -> A+C 1220 if (N0.getOpcode() == ISD::ADD && 1221 N0.getOperand(1).getOpcode() == ISD::ADD && 1222 N0.getOperand(1).getOperand(1) == N1) 1223 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, 1224 N0.getOperand(0), N0.getOperand(1).getOperand(0)); 1225 // fold ((A-(B-C))-C) -> A-B 1226 if (N0.getOpcode() == ISD::SUB && 1227 N0.getOperand(1).getOpcode() == ISD::SUB && 1228 N0.getOperand(1).getOperand(1) == N1) 1229 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1230 N0.getOperand(0), N0.getOperand(1).getOperand(0)); 1231 1232 // If either operand of a sub is undef, the result is undef 1233 if (N0.getOpcode() == ISD::UNDEF) 1234 return N0; 1235 if (N1.getOpcode() == ISD::UNDEF) 1236 return N1; 1237 1238 // If the relocation model supports it, consider symbol offsets. 1239 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0)) 1240 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA)) { 1241 // fold (sub Sym, c) -> Sym-c 1242 if (N1C && GA->getOpcode() == ISD::GlobalAddress) 1243 return DAG.getGlobalAddress(GA->getGlobal(), VT, 1244 GA->getOffset() - 1245 (uint64_t)N1C->getSExtValue()); 1246 // fold (sub Sym+c1, Sym+c2) -> c1-c2 1247 if (GlobalAddressSDNode *GB = dyn_cast<GlobalAddressSDNode>(N1)) 1248 if (GA->getGlobal() == GB->getGlobal()) 1249 return DAG.getConstant((uint64_t)GA->getOffset() - GB->getOffset(), 1250 VT); 1251 } 1252 1253 return SDValue(); 1254} 1255 1256SDValue DAGCombiner::visitMUL(SDNode *N) { 1257 SDValue N0 = N->getOperand(0); 1258 SDValue N1 = N->getOperand(1); 1259 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1260 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1261 EVT VT = N0.getValueType(); 1262 1263 // fold vector ops 1264 if (VT.isVector()) { 1265 SDValue FoldedVOp = SimplifyVBinOp(N); 1266 if (FoldedVOp.getNode()) return FoldedVOp; 1267 } 1268 1269 // fold (mul x, undef) -> 0 1270 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1271 return DAG.getConstant(0, VT); 1272 // fold (mul c1, c2) -> c1*c2 1273 if (N0C && N1C) 1274 return DAG.FoldConstantArithmetic(ISD::MUL, VT, N0C, N1C); 1275 // canonicalize constant to RHS 1276 if (N0C && !N1C) 1277 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, N1, N0); 1278 // fold (mul x, 0) -> 0 1279 if (N1C && N1C->isNullValue()) 1280 return N1; 1281 // fold (mul x, -1) -> 0-x 1282 if (N1C && N1C->isAllOnesValue()) 1283 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1284 DAG.getConstant(0, VT), N0); 1285 // fold (mul x, (1 << c)) -> x << c 1286 if (N1C && N1C->getAPIntValue().isPowerOf2()) 1287 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 1288 DAG.getConstant(N1C->getAPIntValue().logBase2(), 1289 getShiftAmountTy())); 1290 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c 1291 if (N1C && (-N1C->getAPIntValue()).isPowerOf2()) { 1292 unsigned Log2Val = (-N1C->getAPIntValue()).logBase2(); 1293 // FIXME: If the input is something that is easily negated (e.g. a 1294 // single-use add), we should put the negate there. 1295 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1296 DAG.getConstant(0, VT), 1297 DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 1298 DAG.getConstant(Log2Val, getShiftAmountTy()))); 1299 } 1300 // (mul (shl X, c1), c2) -> (mul X, c2 << c1) 1301 if (N1C && N0.getOpcode() == ISD::SHL && 1302 isa<ConstantSDNode>(N0.getOperand(1))) { 1303 SDValue C3 = DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1304 N1, N0.getOperand(1)); 1305 AddToWorkList(C3.getNode()); 1306 return DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1307 N0.getOperand(0), C3); 1308 } 1309 1310 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one 1311 // use. 1312 { 1313 SDValue Sh(0,0), Y(0,0); 1314 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)). 1315 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) && 1316 N0.getNode()->hasOneUse()) { 1317 Sh = N0; Y = N1; 1318 } else if (N1.getOpcode() == ISD::SHL && 1319 isa<ConstantSDNode>(N1.getOperand(1)) && 1320 N1.getNode()->hasOneUse()) { 1321 Sh = N1; Y = N0; 1322 } 1323 1324 if (Sh.getNode()) { 1325 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1326 Sh.getOperand(0), Y); 1327 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, 1328 Mul, Sh.getOperand(1)); 1329 } 1330 } 1331 1332 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2) 1333 if (N1C && N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse() && 1334 isa<ConstantSDNode>(N0.getOperand(1))) 1335 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, 1336 DAG.getNode(ISD::MUL, N0.getDebugLoc(), VT, 1337 N0.getOperand(0), N1), 1338 DAG.getNode(ISD::MUL, N1.getDebugLoc(), VT, 1339 N0.getOperand(1), N1)); 1340 1341 // reassociate mul 1342 SDValue RMUL = ReassociateOps(ISD::MUL, N->getDebugLoc(), N0, N1); 1343 if (RMUL.getNode() != 0) 1344 return RMUL; 1345 1346 return SDValue(); 1347} 1348 1349SDValue DAGCombiner::visitSDIV(SDNode *N) { 1350 SDValue N0 = N->getOperand(0); 1351 SDValue N1 = N->getOperand(1); 1352 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1353 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1354 EVT VT = N->getValueType(0); 1355 1356 // fold vector ops 1357 if (VT.isVector()) { 1358 SDValue FoldedVOp = SimplifyVBinOp(N); 1359 if (FoldedVOp.getNode()) return FoldedVOp; 1360 } 1361 1362 // fold (sdiv c1, c2) -> c1/c2 1363 if (N0C && N1C && !N1C->isNullValue()) 1364 return DAG.FoldConstantArithmetic(ISD::SDIV, VT, N0C, N1C); 1365 // fold (sdiv X, 1) -> X 1366 if (N1C && N1C->getSExtValue() == 1LL) 1367 return N0; 1368 // fold (sdiv X, -1) -> 0-X 1369 if (N1C && N1C->isAllOnesValue()) 1370 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1371 DAG.getConstant(0, VT), N0); 1372 // If we know the sign bits of both operands are zero, strength reduce to a 1373 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2 1374 if (!VT.isVector()) { 1375 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 1376 return DAG.getNode(ISD::UDIV, N->getDebugLoc(), N1.getValueType(), 1377 N0, N1); 1378 } 1379 // fold (sdiv X, pow2) -> simple ops after legalize 1380 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap() && 1381 (isPowerOf2_64(N1C->getSExtValue()) || 1382 isPowerOf2_64(-N1C->getSExtValue()))) { 1383 // If dividing by powers of two is cheap, then don't perform the following 1384 // fold. 1385 if (TLI.isPow2DivCheap()) 1386 return SDValue(); 1387 1388 int64_t pow2 = N1C->getSExtValue(); 1389 int64_t abs2 = pow2 > 0 ? pow2 : -pow2; 1390 unsigned lg2 = Log2_64(abs2); 1391 1392 // Splat the sign bit into the register 1393 SDValue SGN = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0, 1394 DAG.getConstant(VT.getSizeInBits()-1, 1395 getShiftAmountTy())); 1396 AddToWorkList(SGN.getNode()); 1397 1398 // Add (N0 < 0) ? abs2 - 1 : 0; 1399 SDValue SRL = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, SGN, 1400 DAG.getConstant(VT.getSizeInBits() - lg2, 1401 getShiftAmountTy())); 1402 SDValue ADD = DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N0, SRL); 1403 AddToWorkList(SRL.getNode()); 1404 AddToWorkList(ADD.getNode()); // Divide by pow2 1405 SDValue SRA = DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, ADD, 1406 DAG.getConstant(lg2, getShiftAmountTy())); 1407 1408 // If we're dividing by a positive value, we're done. Otherwise, we must 1409 // negate the result. 1410 if (pow2 > 0) 1411 return SRA; 1412 1413 AddToWorkList(SRA.getNode()); 1414 return DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, 1415 DAG.getConstant(0, VT), SRA); 1416 } 1417 1418 // if integer divide is expensive and we satisfy the requirements, emit an 1419 // alternate sequence. 1420 if (N1C && (N1C->getSExtValue() < -1 || N1C->getSExtValue() > 1) && 1421 !TLI.isIntDivCheap()) { 1422 SDValue Op = BuildSDIV(N); 1423 if (Op.getNode()) return Op; 1424 } 1425 1426 // undef / X -> 0 1427 if (N0.getOpcode() == ISD::UNDEF) 1428 return DAG.getConstant(0, VT); 1429 // X / undef -> undef 1430 if (N1.getOpcode() == ISD::UNDEF) 1431 return N1; 1432 1433 return SDValue(); 1434} 1435 1436SDValue DAGCombiner::visitUDIV(SDNode *N) { 1437 SDValue N0 = N->getOperand(0); 1438 SDValue N1 = N->getOperand(1); 1439 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1440 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1441 EVT VT = N->getValueType(0); 1442 1443 // fold vector ops 1444 if (VT.isVector()) { 1445 SDValue FoldedVOp = SimplifyVBinOp(N); 1446 if (FoldedVOp.getNode()) return FoldedVOp; 1447 } 1448 1449 // fold (udiv c1, c2) -> c1/c2 1450 if (N0C && N1C && !N1C->isNullValue()) 1451 return DAG.FoldConstantArithmetic(ISD::UDIV, VT, N0C, N1C); 1452 // fold (udiv x, (1 << c)) -> x >>u c 1453 if (N1C && N1C->getAPIntValue().isPowerOf2()) 1454 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, 1455 DAG.getConstant(N1C->getAPIntValue().logBase2(), 1456 getShiftAmountTy())); 1457 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2 1458 if (N1.getOpcode() == ISD::SHL) { 1459 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1460 if (SHC->getAPIntValue().isPowerOf2()) { 1461 EVT ADDVT = N1.getOperand(1).getValueType(); 1462 SDValue Add = DAG.getNode(ISD::ADD, N->getDebugLoc(), ADDVT, 1463 N1.getOperand(1), 1464 DAG.getConstant(SHC->getAPIntValue() 1465 .logBase2(), 1466 ADDVT)); 1467 AddToWorkList(Add.getNode()); 1468 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, Add); 1469 } 1470 } 1471 } 1472 // fold (udiv x, c) -> alternate 1473 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) { 1474 SDValue Op = BuildUDIV(N); 1475 if (Op.getNode()) return Op; 1476 } 1477 1478 // undef / X -> 0 1479 if (N0.getOpcode() == ISD::UNDEF) 1480 return DAG.getConstant(0, VT); 1481 // X / undef -> undef 1482 if (N1.getOpcode() == ISD::UNDEF) 1483 return N1; 1484 1485 return SDValue(); 1486} 1487 1488SDValue DAGCombiner::visitSREM(SDNode *N) { 1489 SDValue N0 = N->getOperand(0); 1490 SDValue N1 = N->getOperand(1); 1491 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1492 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1493 EVT VT = N->getValueType(0); 1494 1495 // fold (srem c1, c2) -> c1%c2 1496 if (N0C && N1C && !N1C->isNullValue()) 1497 return DAG.FoldConstantArithmetic(ISD::SREM, VT, N0C, N1C); 1498 // If we know the sign bits of both operands are zero, strength reduce to a 1499 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15 1500 if (!VT.isVector()) { 1501 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 1502 return DAG.getNode(ISD::UREM, N->getDebugLoc(), VT, N0, N1); 1503 } 1504 1505 // If X/C can be simplified by the division-by-constant logic, lower 1506 // X%C to the equivalent of X-X/C*C. 1507 if (N1C && !N1C->isNullValue()) { 1508 SDValue Div = DAG.getNode(ISD::SDIV, N->getDebugLoc(), VT, N0, N1); 1509 AddToWorkList(Div.getNode()); 1510 SDValue OptimizedDiv = combine(Div.getNode()); 1511 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) { 1512 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1513 OptimizedDiv, N1); 1514 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul); 1515 AddToWorkList(Mul.getNode()); 1516 return Sub; 1517 } 1518 } 1519 1520 // undef % X -> 0 1521 if (N0.getOpcode() == ISD::UNDEF) 1522 return DAG.getConstant(0, VT); 1523 // X % undef -> undef 1524 if (N1.getOpcode() == ISD::UNDEF) 1525 return N1; 1526 1527 return SDValue(); 1528} 1529 1530SDValue DAGCombiner::visitUREM(SDNode *N) { 1531 SDValue N0 = N->getOperand(0); 1532 SDValue N1 = N->getOperand(1); 1533 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1534 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1535 EVT VT = N->getValueType(0); 1536 1537 // fold (urem c1, c2) -> c1%c2 1538 if (N0C && N1C && !N1C->isNullValue()) 1539 return DAG.FoldConstantArithmetic(ISD::UREM, VT, N0C, N1C); 1540 // fold (urem x, pow2) -> (and x, pow2-1) 1541 if (N1C && !N1C->isNullValue() && N1C->getAPIntValue().isPowerOf2()) 1542 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, 1543 DAG.getConstant(N1C->getAPIntValue()-1,VT)); 1544 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1)) 1545 if (N1.getOpcode() == ISD::SHL) { 1546 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1547 if (SHC->getAPIntValue().isPowerOf2()) { 1548 SDValue Add = 1549 DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, 1550 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), 1551 VT)); 1552 AddToWorkList(Add.getNode()); 1553 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, Add); 1554 } 1555 } 1556 } 1557 1558 // If X/C can be simplified by the division-by-constant logic, lower 1559 // X%C to the equivalent of X-X/C*C. 1560 if (N1C && !N1C->isNullValue()) { 1561 SDValue Div = DAG.getNode(ISD::UDIV, N->getDebugLoc(), VT, N0, N1); 1562 AddToWorkList(Div.getNode()); 1563 SDValue OptimizedDiv = combine(Div.getNode()); 1564 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) { 1565 SDValue Mul = DAG.getNode(ISD::MUL, N->getDebugLoc(), VT, 1566 OptimizedDiv, N1); 1567 SDValue Sub = DAG.getNode(ISD::SUB, N->getDebugLoc(), VT, N0, Mul); 1568 AddToWorkList(Mul.getNode()); 1569 return Sub; 1570 } 1571 } 1572 1573 // undef % X -> 0 1574 if (N0.getOpcode() == ISD::UNDEF) 1575 return DAG.getConstant(0, VT); 1576 // X % undef -> undef 1577 if (N1.getOpcode() == ISD::UNDEF) 1578 return N1; 1579 1580 return SDValue(); 1581} 1582 1583SDValue DAGCombiner::visitMULHS(SDNode *N) { 1584 SDValue N0 = N->getOperand(0); 1585 SDValue N1 = N->getOperand(1); 1586 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1587 EVT VT = N->getValueType(0); 1588 1589 // fold (mulhs x, 0) -> 0 1590 if (N1C && N1C->isNullValue()) 1591 return N1; 1592 // fold (mulhs x, 1) -> (sra x, size(x)-1) 1593 if (N1C && N1C->getAPIntValue() == 1) 1594 return DAG.getNode(ISD::SRA, N->getDebugLoc(), N0.getValueType(), N0, 1595 DAG.getConstant(N0.getValueType().getSizeInBits() - 1, 1596 getShiftAmountTy())); 1597 // fold (mulhs x, undef) -> 0 1598 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1599 return DAG.getConstant(0, VT); 1600 1601 return SDValue(); 1602} 1603 1604SDValue DAGCombiner::visitMULHU(SDNode *N) { 1605 SDValue N0 = N->getOperand(0); 1606 SDValue N1 = N->getOperand(1); 1607 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1608 EVT VT = N->getValueType(0); 1609 1610 // fold (mulhu x, 0) -> 0 1611 if (N1C && N1C->isNullValue()) 1612 return N1; 1613 // fold (mulhu x, 1) -> 0 1614 if (N1C && N1C->getAPIntValue() == 1) 1615 return DAG.getConstant(0, N0.getValueType()); 1616 // fold (mulhu x, undef) -> 0 1617 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1618 return DAG.getConstant(0, VT); 1619 1620 return SDValue(); 1621} 1622 1623/// SimplifyNodeWithTwoResults - Perform optimizations common to nodes that 1624/// compute two values. LoOp and HiOp give the opcodes for the two computations 1625/// that are being performed. Return true if a simplification was made. 1626/// 1627SDValue DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 1628 unsigned HiOp) { 1629 // If the high half is not needed, just compute the low half. 1630 bool HiExists = N->hasAnyUseOfValue(1); 1631 if (!HiExists && 1632 (!LegalOperations || 1633 TLI.isOperationLegal(LoOp, N->getValueType(0)))) { 1634 SDValue Res = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0), 1635 N->op_begin(), N->getNumOperands()); 1636 return CombineTo(N, Res, Res); 1637 } 1638 1639 // If the low half is not needed, just compute the high half. 1640 bool LoExists = N->hasAnyUseOfValue(0); 1641 if (!LoExists && 1642 (!LegalOperations || 1643 TLI.isOperationLegal(HiOp, N->getValueType(1)))) { 1644 SDValue Res = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1), 1645 N->op_begin(), N->getNumOperands()); 1646 return CombineTo(N, Res, Res); 1647 } 1648 1649 // If both halves are used, return as it is. 1650 if (LoExists && HiExists) 1651 return SDValue(); 1652 1653 // If the two computed results can be simplified separately, separate them. 1654 if (LoExists) { 1655 SDValue Lo = DAG.getNode(LoOp, N->getDebugLoc(), N->getValueType(0), 1656 N->op_begin(), N->getNumOperands()); 1657 AddToWorkList(Lo.getNode()); 1658 SDValue LoOpt = combine(Lo.getNode()); 1659 if (LoOpt.getNode() && LoOpt.getNode() != Lo.getNode() && 1660 (!LegalOperations || 1661 TLI.isOperationLegal(LoOpt.getOpcode(), LoOpt.getValueType()))) 1662 return CombineTo(N, LoOpt, LoOpt); 1663 } 1664 1665 if (HiExists) { 1666 SDValue Hi = DAG.getNode(HiOp, N->getDebugLoc(), N->getValueType(1), 1667 N->op_begin(), N->getNumOperands()); 1668 AddToWorkList(Hi.getNode()); 1669 SDValue HiOpt = combine(Hi.getNode()); 1670 if (HiOpt.getNode() && HiOpt != Hi && 1671 (!LegalOperations || 1672 TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType()))) 1673 return CombineTo(N, HiOpt, HiOpt); 1674 } 1675 1676 return SDValue(); 1677} 1678 1679SDValue DAGCombiner::visitSMUL_LOHI(SDNode *N) { 1680 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS); 1681 if (Res.getNode()) return Res; 1682 1683 return SDValue(); 1684} 1685 1686SDValue DAGCombiner::visitUMUL_LOHI(SDNode *N) { 1687 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU); 1688 if (Res.getNode()) return Res; 1689 1690 return SDValue(); 1691} 1692 1693SDValue DAGCombiner::visitSDIVREM(SDNode *N) { 1694 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM); 1695 if (Res.getNode()) return Res; 1696 1697 return SDValue(); 1698} 1699 1700SDValue DAGCombiner::visitUDIVREM(SDNode *N) { 1701 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM); 1702 if (Res.getNode()) return Res; 1703 1704 return SDValue(); 1705} 1706 1707/// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with 1708/// two operands of the same opcode, try to simplify it. 1709SDValue DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) { 1710 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1); 1711 EVT VT = N0.getValueType(); 1712 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!"); 1713 1714 // Bail early if none of these transforms apply. 1715 if (N0.getNode()->getNumOperands() == 0) return SDValue(); 1716 1717 // For each of OP in AND/OR/XOR: 1718 // fold (OP (zext x), (zext y)) -> (zext (OP x, y)) 1719 // fold (OP (sext x), (sext y)) -> (sext (OP x, y)) 1720 // fold (OP (aext x), (aext y)) -> (aext (OP x, y)) 1721 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y)) 1722 // 1723 // do not sink logical op inside of a vector extend, since it may combine 1724 // into a vsetcc. 1725 EVT Op0VT = N0.getOperand(0).getValueType(); 1726 if ((N0.getOpcode() == ISD::ZERO_EXTEND || 1727 N0.getOpcode() == ISD::ANY_EXTEND || 1728 N0.getOpcode() == ISD::SIGN_EXTEND || 1729 (N0.getOpcode() == ISD::TRUNCATE && TLI.isTypeLegal(Op0VT))) && 1730 !VT.isVector() && 1731 Op0VT == N1.getOperand(0).getValueType() && 1732 (!LegalOperations || TLI.isOperationLegal(N->getOpcode(), Op0VT))) { 1733 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(), 1734 N0.getOperand(0).getValueType(), 1735 N0.getOperand(0), N1.getOperand(0)); 1736 AddToWorkList(ORNode.getNode()); 1737 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, ORNode); 1738 } 1739 1740 // For each of OP in SHL/SRL/SRA/AND... 1741 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z) 1742 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z) 1743 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z) 1744 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL || 1745 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) && 1746 N0.getOperand(1) == N1.getOperand(1)) { 1747 SDValue ORNode = DAG.getNode(N->getOpcode(), N0.getDebugLoc(), 1748 N0.getOperand(0).getValueType(), 1749 N0.getOperand(0), N1.getOperand(0)); 1750 AddToWorkList(ORNode.getNode()); 1751 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, 1752 ORNode, N0.getOperand(1)); 1753 } 1754 1755 return SDValue(); 1756} 1757 1758SDValue DAGCombiner::visitAND(SDNode *N) { 1759 SDValue N0 = N->getOperand(0); 1760 SDValue N1 = N->getOperand(1); 1761 SDValue LL, LR, RL, RR, CC0, CC1; 1762 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1763 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1764 EVT VT = N1.getValueType(); 1765 unsigned BitWidth = VT.getScalarType().getSizeInBits(); 1766 1767 // fold vector ops 1768 if (VT.isVector()) { 1769 SDValue FoldedVOp = SimplifyVBinOp(N); 1770 if (FoldedVOp.getNode()) return FoldedVOp; 1771 } 1772 1773 // fold (and x, undef) -> 0 1774 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1775 return DAG.getConstant(0, VT); 1776 // fold (and c1, c2) -> c1&c2 1777 if (N0C && N1C) 1778 return DAG.FoldConstantArithmetic(ISD::AND, VT, N0C, N1C); 1779 // canonicalize constant to RHS 1780 if (N0C && !N1C) 1781 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N1, N0); 1782 // fold (and x, -1) -> x 1783 if (N1C && N1C->isAllOnesValue()) 1784 return N0; 1785 // if (and x, c) is known to be zero, return 0 1786 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0), 1787 APInt::getAllOnesValue(BitWidth))) 1788 return DAG.getConstant(0, VT); 1789 // reassociate and 1790 SDValue RAND = ReassociateOps(ISD::AND, N->getDebugLoc(), N0, N1); 1791 if (RAND.getNode() != 0) 1792 return RAND; 1793 // fold (and (or x, C), D) -> D if (C & D) == D 1794 if (N1C && N0.getOpcode() == ISD::OR) 1795 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 1796 if ((ORI->getAPIntValue() & N1C->getAPIntValue()) == N1C->getAPIntValue()) 1797 return N1; 1798 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits. 1799 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 1800 SDValue N0Op0 = N0.getOperand(0); 1801 APInt Mask = ~N1C->getAPIntValue(); 1802 Mask.trunc(N0Op0.getValueSizeInBits()); 1803 if (DAG.MaskedValueIsZero(N0Op0, Mask)) { 1804 SDValue Zext = DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), 1805 N0.getValueType(), N0Op0); 1806 1807 // Replace uses of the AND with uses of the Zero extend node. 1808 CombineTo(N, Zext); 1809 1810 // We actually want to replace all uses of the any_extend with the 1811 // zero_extend, to avoid duplicating things. This will later cause this 1812 // AND to be folded. 1813 CombineTo(N0.getNode(), Zext); 1814 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1815 } 1816 } 1817 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y)) 1818 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 1819 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 1820 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 1821 1822 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 1823 LL.getValueType().isInteger()) { 1824 // fold (and (seteq X, 0), (seteq Y, 0)) -> (seteq (or X, Y), 0) 1825 if (cast<ConstantSDNode>(LR)->isNullValue() && Op1 == ISD::SETEQ) { 1826 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(), 1827 LR.getValueType(), LL, RL); 1828 AddToWorkList(ORNode.getNode()); 1829 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 1830 } 1831 // fold (and (seteq X, -1), (seteq Y, -1)) -> (seteq (and X, Y), -1) 1832 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) { 1833 SDValue ANDNode = DAG.getNode(ISD::AND, N0.getDebugLoc(), 1834 LR.getValueType(), LL, RL); 1835 AddToWorkList(ANDNode.getNode()); 1836 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1); 1837 } 1838 // fold (and (setgt X, -1), (setgt Y, -1)) -> (setgt (or X, Y), -1) 1839 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) { 1840 SDValue ORNode = DAG.getNode(ISD::OR, N0.getDebugLoc(), 1841 LR.getValueType(), LL, RL); 1842 AddToWorkList(ORNode.getNode()); 1843 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 1844 } 1845 } 1846 // canonicalize equivalent to ll == rl 1847 if (LL == RR && LR == RL) { 1848 Op1 = ISD::getSetCCSwappedOperands(Op1); 1849 std::swap(RL, RR); 1850 } 1851 if (LL == RL && LR == RR) { 1852 bool isInteger = LL.getValueType().isInteger(); 1853 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger); 1854 if (Result != ISD::SETCC_INVALID && 1855 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType()))) 1856 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(), 1857 LL, LR, Result); 1858 } 1859 } 1860 1861 // Simplify: (and (op x...), (op y...)) -> (op (and x, y)) 1862 if (N0.getOpcode() == N1.getOpcode()) { 1863 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 1864 if (Tmp.getNode()) return Tmp; 1865 } 1866 1867 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1) 1868 // fold (and (sra)) -> (and (srl)) when possible. 1869 if (!VT.isVector() && 1870 SimplifyDemandedBits(SDValue(N, 0))) 1871 return SDValue(N, 0); 1872 1873 // fold (zext_inreg (extload x)) -> (zextload x) 1874 if (ISD::isEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode())) { 1875 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1876 EVT MemVT = LN0->getMemoryVT(); 1877 // If we zero all the possible extended bits, then we can turn this into 1878 // a zextload if we are running before legalize or the operation is legal. 1879 unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits(); 1880 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 1881 BitWidth - MemVT.getScalarType().getSizeInBits())) && 1882 ((!LegalOperations && !LN0->isVolatile()) || 1883 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) { 1884 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT, 1885 LN0->getChain(), LN0->getBasePtr(), 1886 LN0->getSrcValue(), 1887 LN0->getSrcValueOffset(), MemVT, 1888 LN0->isVolatile(), LN0->isNonTemporal(), 1889 LN0->getAlignment()); 1890 AddToWorkList(N); 1891 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 1892 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1893 } 1894 } 1895 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use 1896 if (ISD::isSEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 1897 N0.hasOneUse()) { 1898 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1899 EVT MemVT = LN0->getMemoryVT(); 1900 // If we zero all the possible extended bits, then we can turn this into 1901 // a zextload if we are running before legalize or the operation is legal. 1902 unsigned BitWidth = N1.getValueType().getScalarType().getSizeInBits(); 1903 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 1904 BitWidth - MemVT.getScalarType().getSizeInBits())) && 1905 ((!LegalOperations && !LN0->isVolatile()) || 1906 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT))) { 1907 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N0.getDebugLoc(), VT, 1908 LN0->getChain(), 1909 LN0->getBasePtr(), LN0->getSrcValue(), 1910 LN0->getSrcValueOffset(), MemVT, 1911 LN0->isVolatile(), LN0->isNonTemporal(), 1912 LN0->getAlignment()); 1913 AddToWorkList(N); 1914 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 1915 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1916 } 1917 } 1918 1919 // fold (and (load x), 255) -> (zextload x, i8) 1920 // fold (and (extload x, i16), 255) -> (zextload x, i8) 1921 // fold (and (any_ext (extload x, i16)), 255) -> (zextload x, i8) 1922 if (N1C && (N0.getOpcode() == ISD::LOAD || 1923 (N0.getOpcode() == ISD::ANY_EXTEND && 1924 N0.getOperand(0).getOpcode() == ISD::LOAD))) { 1925 bool HasAnyExt = N0.getOpcode() == ISD::ANY_EXTEND; 1926 LoadSDNode *LN0 = HasAnyExt 1927 ? cast<LoadSDNode>(N0.getOperand(0)) 1928 : cast<LoadSDNode>(N0); 1929 if (LN0->getExtensionType() != ISD::SEXTLOAD && 1930 LN0->isUnindexed() && N0.hasOneUse() && LN0->hasOneUse()) { 1931 uint32_t ActiveBits = N1C->getAPIntValue().getActiveBits(); 1932 if (ActiveBits > 0 && APIntOps::isMask(ActiveBits, N1C->getAPIntValue())){ 1933 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), ActiveBits); 1934 EVT LoadedVT = LN0->getMemoryVT(); 1935 1936 if (ExtVT == LoadedVT && 1937 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) { 1938 EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT; 1939 1940 SDValue NewLoad = 1941 DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), LoadResultTy, 1942 LN0->getChain(), LN0->getBasePtr(), 1943 LN0->getSrcValue(), LN0->getSrcValueOffset(), 1944 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(), 1945 LN0->getAlignment()); 1946 AddToWorkList(N); 1947 CombineTo(LN0, NewLoad, NewLoad.getValue(1)); 1948 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1949 } 1950 1951 // Do not change the width of a volatile load. 1952 // Do not generate loads of non-round integer types since these can 1953 // be expensive (and would be wrong if the type is not byte sized). 1954 if (!LN0->isVolatile() && LoadedVT.bitsGT(ExtVT) && ExtVT.isRound() && 1955 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) { 1956 EVT PtrType = LN0->getOperand(1).getValueType(); 1957 1958 unsigned Alignment = LN0->getAlignment(); 1959 SDValue NewPtr = LN0->getBasePtr(); 1960 1961 // For big endian targets, we need to add an offset to the pointer 1962 // to load the correct bytes. For little endian systems, we merely 1963 // need to read fewer bytes from the same pointer. 1964 if (TLI.isBigEndian()) { 1965 unsigned LVTStoreBytes = LoadedVT.getStoreSize(); 1966 unsigned EVTStoreBytes = ExtVT.getStoreSize(); 1967 unsigned PtrOff = LVTStoreBytes - EVTStoreBytes; 1968 NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(), PtrType, 1969 NewPtr, DAG.getConstant(PtrOff, PtrType)); 1970 Alignment = MinAlign(Alignment, PtrOff); 1971 } 1972 1973 AddToWorkList(NewPtr.getNode()); 1974 1975 EVT LoadResultTy = HasAnyExt ? LN0->getValueType(0) : VT; 1976 SDValue Load = 1977 DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), LoadResultTy, 1978 LN0->getChain(), NewPtr, 1979 LN0->getSrcValue(), LN0->getSrcValueOffset(), 1980 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(), 1981 Alignment); 1982 AddToWorkList(N); 1983 CombineTo(LN0, Load, Load.getValue(1)); 1984 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1985 } 1986 } 1987 } 1988 } 1989 1990 return SDValue(); 1991} 1992 1993SDValue DAGCombiner::visitOR(SDNode *N) { 1994 SDValue N0 = N->getOperand(0); 1995 SDValue N1 = N->getOperand(1); 1996 SDValue LL, LR, RL, RR, CC0, CC1; 1997 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1998 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1999 EVT VT = N1.getValueType(); 2000 2001 // fold vector ops 2002 if (VT.isVector()) { 2003 SDValue FoldedVOp = SimplifyVBinOp(N); 2004 if (FoldedVOp.getNode()) return FoldedVOp; 2005 } 2006 2007 // fold (or x, undef) -> -1 2008 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) { 2009 EVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT; 2010 return DAG.getConstant(APInt::getAllOnesValue(EltVT.getSizeInBits()), VT); 2011 } 2012 // fold (or c1, c2) -> c1|c2 2013 if (N0C && N1C) 2014 return DAG.FoldConstantArithmetic(ISD::OR, VT, N0C, N1C); 2015 // canonicalize constant to RHS 2016 if (N0C && !N1C) 2017 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N1, N0); 2018 // fold (or x, 0) -> x 2019 if (N1C && N1C->isNullValue()) 2020 return N0; 2021 // fold (or x, -1) -> -1 2022 if (N1C && N1C->isAllOnesValue()) 2023 return N1; 2024 // fold (or x, c) -> c iff (x & ~c) == 0 2025 if (N1C && DAG.MaskedValueIsZero(N0, ~N1C->getAPIntValue())) 2026 return N1; 2027 // reassociate or 2028 SDValue ROR = ReassociateOps(ISD::OR, N->getDebugLoc(), N0, N1); 2029 if (ROR.getNode() != 0) 2030 return ROR; 2031 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2) 2032 // iff (c1 & c2) == 0. 2033 if (N1C && N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() && 2034 isa<ConstantSDNode>(N0.getOperand(1))) { 2035 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1)); 2036 if ((C1->getAPIntValue() & N1C->getAPIntValue()) != 0) 2037 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 2038 DAG.getNode(ISD::OR, N0.getDebugLoc(), VT, 2039 N0.getOperand(0), N1), 2040 DAG.FoldConstantArithmetic(ISD::OR, VT, N1C, C1)); 2041 } 2042 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y)) 2043 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 2044 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 2045 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 2046 2047 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 2048 LL.getValueType().isInteger()) { 2049 // fold (or (setne X, 0), (setne Y, 0)) -> (setne (or X, Y), 0) 2050 // fold (or (setlt X, 0), (setlt Y, 0)) -> (setne (or X, Y), 0) 2051 if (cast<ConstantSDNode>(LR)->isNullValue() && 2052 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) { 2053 SDValue ORNode = DAG.getNode(ISD::OR, LR.getDebugLoc(), 2054 LR.getValueType(), LL, RL); 2055 AddToWorkList(ORNode.getNode()); 2056 return DAG.getSetCC(N->getDebugLoc(), VT, ORNode, LR, Op1); 2057 } 2058 // fold (or (setne X, -1), (setne Y, -1)) -> (setne (and X, Y), -1) 2059 // fold (or (setgt X, -1), (setgt Y -1)) -> (setgt (and X, Y), -1) 2060 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && 2061 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) { 2062 SDValue ANDNode = DAG.getNode(ISD::AND, LR.getDebugLoc(), 2063 LR.getValueType(), LL, RL); 2064 AddToWorkList(ANDNode.getNode()); 2065 return DAG.getSetCC(N->getDebugLoc(), VT, ANDNode, LR, Op1); 2066 } 2067 } 2068 // canonicalize equivalent to ll == rl 2069 if (LL == RR && LR == RL) { 2070 Op1 = ISD::getSetCCSwappedOperands(Op1); 2071 std::swap(RL, RR); 2072 } 2073 if (LL == RL && LR == RR) { 2074 bool isInteger = LL.getValueType().isInteger(); 2075 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger); 2076 if (Result != ISD::SETCC_INVALID && 2077 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType()))) 2078 return DAG.getSetCC(N->getDebugLoc(), N0.getValueType(), 2079 LL, LR, Result); 2080 } 2081 } 2082 2083 // Simplify: (or (op x...), (op y...)) -> (op (or x, y)) 2084 if (N0.getOpcode() == N1.getOpcode()) { 2085 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 2086 if (Tmp.getNode()) return Tmp; 2087 } 2088 2089 // (or (and X, C1), (and Y, C2)) -> (and (or X, Y), C3) if possible. 2090 if (N0.getOpcode() == ISD::AND && 2091 N1.getOpcode() == ISD::AND && 2092 N0.getOperand(1).getOpcode() == ISD::Constant && 2093 N1.getOperand(1).getOpcode() == ISD::Constant && 2094 // Don't increase # computations. 2095 (N0.getNode()->hasOneUse() || N1.getNode()->hasOneUse())) { 2096 // We can only do this xform if we know that bits from X that are set in C2 2097 // but not in C1 are already zero. Likewise for Y. 2098 const APInt &LHSMask = 2099 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 2100 const APInt &RHSMask = 2101 cast<ConstantSDNode>(N1.getOperand(1))->getAPIntValue(); 2102 2103 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) && 2104 DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) { 2105 SDValue X = DAG.getNode(ISD::OR, N0.getDebugLoc(), VT, 2106 N0.getOperand(0), N1.getOperand(0)); 2107 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, X, 2108 DAG.getConstant(LHSMask | RHSMask, VT)); 2109 } 2110 } 2111 2112 // See if this is some rotate idiom. 2113 if (SDNode *Rot = MatchRotate(N0, N1, N->getDebugLoc())) 2114 return SDValue(Rot, 0); 2115 2116 return SDValue(); 2117} 2118 2119/// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present. 2120static bool MatchRotateHalf(SDValue Op, SDValue &Shift, SDValue &Mask) { 2121 if (Op.getOpcode() == ISD::AND) { 2122 if (isa<ConstantSDNode>(Op.getOperand(1))) { 2123 Mask = Op.getOperand(1); 2124 Op = Op.getOperand(0); 2125 } else { 2126 return false; 2127 } 2128 } 2129 2130 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) { 2131 Shift = Op; 2132 return true; 2133 } 2134 2135 return false; 2136} 2137 2138// MatchRotate - Handle an 'or' of two operands. If this is one of the many 2139// idioms for rotate, and if the target supports rotation instructions, generate 2140// a rot[lr]. 2141SDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL) { 2142 // Must be a legal type. Expanded 'n promoted things won't work with rotates. 2143 EVT VT = LHS.getValueType(); 2144 if (!TLI.isTypeLegal(VT)) return 0; 2145 2146 // The target must have at least one rotate flavor. 2147 bool HasROTL = TLI.isOperationLegalOrCustom(ISD::ROTL, VT); 2148 bool HasROTR = TLI.isOperationLegalOrCustom(ISD::ROTR, VT); 2149 if (!HasROTL && !HasROTR) return 0; 2150 2151 // Match "(X shl/srl V1) & V2" where V2 may not be present. 2152 SDValue LHSShift; // The shift. 2153 SDValue LHSMask; // AND value if any. 2154 if (!MatchRotateHalf(LHS, LHSShift, LHSMask)) 2155 return 0; // Not part of a rotate. 2156 2157 SDValue RHSShift; // The shift. 2158 SDValue RHSMask; // AND value if any. 2159 if (!MatchRotateHalf(RHS, RHSShift, RHSMask)) 2160 return 0; // Not part of a rotate. 2161 2162 if (LHSShift.getOperand(0) != RHSShift.getOperand(0)) 2163 return 0; // Not shifting the same value. 2164 2165 if (LHSShift.getOpcode() == RHSShift.getOpcode()) 2166 return 0; // Shifts must disagree. 2167 2168 // Canonicalize shl to left side in a shl/srl pair. 2169 if (RHSShift.getOpcode() == ISD::SHL) { 2170 std::swap(LHS, RHS); 2171 std::swap(LHSShift, RHSShift); 2172 std::swap(LHSMask , RHSMask ); 2173 } 2174 2175 unsigned OpSizeInBits = VT.getSizeInBits(); 2176 SDValue LHSShiftArg = LHSShift.getOperand(0); 2177 SDValue LHSShiftAmt = LHSShift.getOperand(1); 2178 SDValue RHSShiftAmt = RHSShift.getOperand(1); 2179 2180 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1) 2181 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2) 2182 if (LHSShiftAmt.getOpcode() == ISD::Constant && 2183 RHSShiftAmt.getOpcode() == ISD::Constant) { 2184 uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getZExtValue(); 2185 uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getZExtValue(); 2186 if ((LShVal + RShVal) != OpSizeInBits) 2187 return 0; 2188 2189 SDValue Rot; 2190 if (HasROTL) 2191 Rot = DAG.getNode(ISD::ROTL, DL, VT, LHSShiftArg, LHSShiftAmt); 2192 else 2193 Rot = DAG.getNode(ISD::ROTR, DL, VT, LHSShiftArg, RHSShiftAmt); 2194 2195 // If there is an AND of either shifted operand, apply it to the result. 2196 if (LHSMask.getNode() || RHSMask.getNode()) { 2197 APInt Mask = APInt::getAllOnesValue(OpSizeInBits); 2198 2199 if (LHSMask.getNode()) { 2200 APInt RHSBits = APInt::getLowBitsSet(OpSizeInBits, LShVal); 2201 Mask &= cast<ConstantSDNode>(LHSMask)->getAPIntValue() | RHSBits; 2202 } 2203 if (RHSMask.getNode()) { 2204 APInt LHSBits = APInt::getHighBitsSet(OpSizeInBits, RShVal); 2205 Mask &= cast<ConstantSDNode>(RHSMask)->getAPIntValue() | LHSBits; 2206 } 2207 2208 Rot = DAG.getNode(ISD::AND, DL, VT, Rot, DAG.getConstant(Mask, VT)); 2209 } 2210 2211 return Rot.getNode(); 2212 } 2213 2214 // If there is a mask here, and we have a variable shift, we can't be sure 2215 // that we're masking out the right stuff. 2216 if (LHSMask.getNode() || RHSMask.getNode()) 2217 return 0; 2218 2219 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y) 2220 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y)) 2221 if (RHSShiftAmt.getOpcode() == ISD::SUB && 2222 LHSShiftAmt == RHSShiftAmt.getOperand(1)) { 2223 if (ConstantSDNode *SUBC = 2224 dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) { 2225 if (SUBC->getAPIntValue() == OpSizeInBits) { 2226 if (HasROTL) 2227 return DAG.getNode(ISD::ROTL, DL, VT, 2228 LHSShiftArg, LHSShiftAmt).getNode(); 2229 else 2230 return DAG.getNode(ISD::ROTR, DL, VT, 2231 LHSShiftArg, RHSShiftAmt).getNode(); 2232 } 2233 } 2234 } 2235 2236 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y) 2237 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y)) 2238 if (LHSShiftAmt.getOpcode() == ISD::SUB && 2239 RHSShiftAmt == LHSShiftAmt.getOperand(1)) { 2240 if (ConstantSDNode *SUBC = 2241 dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) { 2242 if (SUBC->getAPIntValue() == OpSizeInBits) { 2243 if (HasROTR) 2244 return DAG.getNode(ISD::ROTR, DL, VT, 2245 LHSShiftArg, RHSShiftAmt).getNode(); 2246 else 2247 return DAG.getNode(ISD::ROTL, DL, VT, 2248 LHSShiftArg, LHSShiftAmt).getNode(); 2249 } 2250 } 2251 } 2252 2253 // Look for sign/zext/any-extended or truncate cases: 2254 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 2255 || LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 2256 || LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND 2257 || LHSShiftAmt.getOpcode() == ISD::TRUNCATE) && 2258 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 2259 || RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 2260 || RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND 2261 || RHSShiftAmt.getOpcode() == ISD::TRUNCATE)) { 2262 SDValue LExtOp0 = LHSShiftAmt.getOperand(0); 2263 SDValue RExtOp0 = RHSShiftAmt.getOperand(0); 2264 if (RExtOp0.getOpcode() == ISD::SUB && 2265 RExtOp0.getOperand(1) == LExtOp0) { 2266 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 2267 // (rotl x, y) 2268 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 2269 // (rotr x, (sub 32, y)) 2270 if (ConstantSDNode *SUBC = 2271 dyn_cast<ConstantSDNode>(RExtOp0.getOperand(0))) { 2272 if (SUBC->getAPIntValue() == OpSizeInBits) { 2273 return DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT, 2274 LHSShiftArg, 2275 HasROTL ? LHSShiftAmt : RHSShiftAmt).getNode(); 2276 } 2277 } 2278 } else if (LExtOp0.getOpcode() == ISD::SUB && 2279 RExtOp0 == LExtOp0.getOperand(1)) { 2280 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) -> 2281 // (rotr x, y) 2282 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) -> 2283 // (rotl x, (sub 32, y)) 2284 if (ConstantSDNode *SUBC = 2285 dyn_cast<ConstantSDNode>(LExtOp0.getOperand(0))) { 2286 if (SUBC->getAPIntValue() == OpSizeInBits) { 2287 return DAG.getNode(HasROTR ? ISD::ROTR : ISD::ROTL, DL, VT, 2288 LHSShiftArg, 2289 HasROTR ? RHSShiftAmt : LHSShiftAmt).getNode(); 2290 } 2291 } 2292 } 2293 } 2294 2295 return 0; 2296} 2297 2298SDValue DAGCombiner::visitXOR(SDNode *N) { 2299 SDValue N0 = N->getOperand(0); 2300 SDValue N1 = N->getOperand(1); 2301 SDValue LHS, RHS, CC; 2302 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2303 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2304 EVT VT = N0.getValueType(); 2305 2306 // fold vector ops 2307 if (VT.isVector()) { 2308 SDValue FoldedVOp = SimplifyVBinOp(N); 2309 if (FoldedVOp.getNode()) return FoldedVOp; 2310 } 2311 2312 // fold (xor undef, undef) -> 0. This is a common idiom (misuse). 2313 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF) 2314 return DAG.getConstant(0, VT); 2315 // fold (xor x, undef) -> undef 2316 if (N0.getOpcode() == ISD::UNDEF) 2317 return N0; 2318 if (N1.getOpcode() == ISD::UNDEF) 2319 return N1; 2320 // fold (xor c1, c2) -> c1^c2 2321 if (N0C && N1C) 2322 return DAG.FoldConstantArithmetic(ISD::XOR, VT, N0C, N1C); 2323 // canonicalize constant to RHS 2324 if (N0C && !N1C) 2325 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N1, N0); 2326 // fold (xor x, 0) -> x 2327 if (N1C && N1C->isNullValue()) 2328 return N0; 2329 // reassociate xor 2330 SDValue RXOR = ReassociateOps(ISD::XOR, N->getDebugLoc(), N0, N1); 2331 if (RXOR.getNode() != 0) 2332 return RXOR; 2333 2334 // fold !(x cc y) -> (x !cc y) 2335 if (N1C && N1C->getAPIntValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) { 2336 bool isInt = LHS.getValueType().isInteger(); 2337 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(), 2338 isInt); 2339 2340 if (!LegalOperations || TLI.isCondCodeLegal(NotCC, LHS.getValueType())) { 2341 switch (N0.getOpcode()) { 2342 default: 2343 llvm_unreachable("Unhandled SetCC Equivalent!"); 2344 case ISD::SETCC: 2345 return DAG.getSetCC(N->getDebugLoc(), VT, LHS, RHS, NotCC); 2346 case ISD::SELECT_CC: 2347 return DAG.getSelectCC(N->getDebugLoc(), LHS, RHS, N0.getOperand(2), 2348 N0.getOperand(3), NotCC); 2349 } 2350 } 2351 } 2352 2353 // fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y))) 2354 if (N1C && N1C->getAPIntValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND && 2355 N0.getNode()->hasOneUse() && 2356 isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){ 2357 SDValue V = N0.getOperand(0); 2358 V = DAG.getNode(ISD::XOR, N0.getDebugLoc(), V.getValueType(), V, 2359 DAG.getConstant(1, V.getValueType())); 2360 AddToWorkList(V.getNode()); 2361 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, V); 2362 } 2363 2364 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are setcc 2365 if (N1C && N1C->getAPIntValue() == 1 && VT == MVT::i1 && 2366 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 2367 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1); 2368 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) { 2369 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 2370 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS 2371 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS 2372 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode()); 2373 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS); 2374 } 2375 } 2376 // fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are constants 2377 if (N1C && N1C->isAllOnesValue() && 2378 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 2379 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1); 2380 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) { 2381 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 2382 LHS = DAG.getNode(ISD::XOR, LHS.getDebugLoc(), VT, LHS, N1); // LHS = ~LHS 2383 RHS = DAG.getNode(ISD::XOR, RHS.getDebugLoc(), VT, RHS, N1); // RHS = ~RHS 2384 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode()); 2385 return DAG.getNode(NewOpcode, N->getDebugLoc(), VT, LHS, RHS); 2386 } 2387 } 2388 // fold (xor (xor x, c1), c2) -> (xor x, (xor c1, c2)) 2389 if (N1C && N0.getOpcode() == ISD::XOR) { 2390 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0)); 2391 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2392 if (N00C) 2393 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(1), 2394 DAG.getConstant(N1C->getAPIntValue() ^ 2395 N00C->getAPIntValue(), VT)); 2396 if (N01C) 2397 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, N0.getOperand(0), 2398 DAG.getConstant(N1C->getAPIntValue() ^ 2399 N01C->getAPIntValue(), VT)); 2400 } 2401 // fold (xor x, x) -> 0 2402 if (N0 == N1) { 2403 if (!VT.isVector()) { 2404 return DAG.getConstant(0, VT); 2405 } else if (!LegalOperations || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)){ 2406 // Produce a vector of zeros. 2407 SDValue El = DAG.getConstant(0, VT.getVectorElementType()); 2408 std::vector<SDValue> Ops(VT.getVectorNumElements(), El); 2409 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT, 2410 &Ops[0], Ops.size()); 2411 } 2412 } 2413 2414 // Simplify: xor (op x...), (op y...) -> (op (xor x, y)) 2415 if (N0.getOpcode() == N1.getOpcode()) { 2416 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 2417 if (Tmp.getNode()) return Tmp; 2418 } 2419 2420 // Simplify the expression using non-local knowledge. 2421 if (!VT.isVector() && 2422 SimplifyDemandedBits(SDValue(N, 0))) 2423 return SDValue(N, 0); 2424 2425 return SDValue(); 2426} 2427 2428/// visitShiftByConstant - Handle transforms common to the three shifts, when 2429/// the shift amount is a constant. 2430SDValue DAGCombiner::visitShiftByConstant(SDNode *N, unsigned Amt) { 2431 SDNode *LHS = N->getOperand(0).getNode(); 2432 if (!LHS->hasOneUse()) return SDValue(); 2433 2434 // We want to pull some binops through shifts, so that we have (and (shift)) 2435 // instead of (shift (and)), likewise for add, or, xor, etc. This sort of 2436 // thing happens with address calculations, so it's important to canonicalize 2437 // it. 2438 bool HighBitSet = false; // Can we transform this if the high bit is set? 2439 2440 switch (LHS->getOpcode()) { 2441 default: return SDValue(); 2442 case ISD::OR: 2443 case ISD::XOR: 2444 HighBitSet = false; // We can only transform sra if the high bit is clear. 2445 break; 2446 case ISD::AND: 2447 HighBitSet = true; // We can only transform sra if the high bit is set. 2448 break; 2449 case ISD::ADD: 2450 if (N->getOpcode() != ISD::SHL) 2451 return SDValue(); // only shl(add) not sr[al](add). 2452 HighBitSet = false; // We can only transform sra if the high bit is clear. 2453 break; 2454 } 2455 2456 // We require the RHS of the binop to be a constant as well. 2457 ConstantSDNode *BinOpCst = dyn_cast<ConstantSDNode>(LHS->getOperand(1)); 2458 if (!BinOpCst) return SDValue(); 2459 2460 // FIXME: disable this unless the input to the binop is a shift by a constant. 2461 // If it is not a shift, it pessimizes some common cases like: 2462 // 2463 // void foo(int *X, int i) { X[i & 1235] = 1; } 2464 // int bar(int *X, int i) { return X[i & 255]; } 2465 SDNode *BinOpLHSVal = LHS->getOperand(0).getNode(); 2466 if ((BinOpLHSVal->getOpcode() != ISD::SHL && 2467 BinOpLHSVal->getOpcode() != ISD::SRA && 2468 BinOpLHSVal->getOpcode() != ISD::SRL) || 2469 !isa<ConstantSDNode>(BinOpLHSVal->getOperand(1))) 2470 return SDValue(); 2471 2472 EVT VT = N->getValueType(0); 2473 2474 // If this is a signed shift right, and the high bit is modified by the 2475 // logical operation, do not perform the transformation. The highBitSet 2476 // boolean indicates the value of the high bit of the constant which would 2477 // cause it to be modified for this operation. 2478 if (N->getOpcode() == ISD::SRA) { 2479 bool BinOpRHSSignSet = BinOpCst->getAPIntValue().isNegative(); 2480 if (BinOpRHSSignSet != HighBitSet) 2481 return SDValue(); 2482 } 2483 2484 // Fold the constants, shifting the binop RHS by the shift amount. 2485 SDValue NewRHS = DAG.getNode(N->getOpcode(), LHS->getOperand(1).getDebugLoc(), 2486 N->getValueType(0), 2487 LHS->getOperand(1), N->getOperand(1)); 2488 2489 // Create the new shift. 2490 SDValue NewShift = DAG.getNode(N->getOpcode(), LHS->getOperand(0).getDebugLoc(), 2491 VT, LHS->getOperand(0), N->getOperand(1)); 2492 2493 // Create the new binop. 2494 return DAG.getNode(LHS->getOpcode(), N->getDebugLoc(), VT, NewShift, NewRHS); 2495} 2496 2497SDValue DAGCombiner::visitSHL(SDNode *N) { 2498 SDValue N0 = N->getOperand(0); 2499 SDValue N1 = N->getOperand(1); 2500 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2501 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2502 EVT VT = N0.getValueType(); 2503 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits(); 2504 2505 // fold (shl c1, c2) -> c1<<c2 2506 if (N0C && N1C) 2507 return DAG.FoldConstantArithmetic(ISD::SHL, VT, N0C, N1C); 2508 // fold (shl 0, x) -> 0 2509 if (N0C && N0C->isNullValue()) 2510 return N0; 2511 // fold (shl x, c >= size(x)) -> undef 2512 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 2513 return DAG.getUNDEF(VT); 2514 // fold (shl x, 0) -> x 2515 if (N1C && N1C->isNullValue()) 2516 return N0; 2517 // if (shl x, c) is known to be zero, return 0 2518 if (DAG.MaskedValueIsZero(SDValue(N, 0), 2519 APInt::getAllOnesValue(OpSizeInBits))) 2520 return DAG.getConstant(0, VT); 2521 // fold (shl x, (trunc (and y, c))) -> (shl x, (and (trunc y), (trunc c))). 2522 if (N1.getOpcode() == ISD::TRUNCATE && 2523 N1.getOperand(0).getOpcode() == ISD::AND && 2524 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 2525 SDValue N101 = N1.getOperand(0).getOperand(1); 2526 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 2527 EVT TruncVT = N1.getValueType(); 2528 SDValue N100 = N1.getOperand(0).getOperand(0); 2529 APInt TruncC = N101C->getAPIntValue(); 2530 TruncC.trunc(TruncVT.getSizeInBits()); 2531 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0, 2532 DAG.getNode(ISD::AND, N->getDebugLoc(), TruncVT, 2533 DAG.getNode(ISD::TRUNCATE, 2534 N->getDebugLoc(), 2535 TruncVT, N100), 2536 DAG.getConstant(TruncC, TruncVT))); 2537 } 2538 } 2539 2540 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 2541 return SDValue(N, 0); 2542 2543 // fold (shl (shl x, c1), c2) -> 0 or (shl x, (add c1, c2)) 2544 if (N1C && N0.getOpcode() == ISD::SHL && 2545 N0.getOperand(1).getOpcode() == ISD::Constant) { 2546 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 2547 uint64_t c2 = N1C->getZExtValue(); 2548 if (c1 + c2 > OpSizeInBits) 2549 return DAG.getConstant(0, VT); 2550 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, N0.getOperand(0), 2551 DAG.getConstant(c1 + c2, N1.getValueType())); 2552 } 2553 // fold (shl (srl x, c1), c2) -> (shl (and x, (shl -1, c1)), (sub c2, c1)) or 2554 // (srl (and x, (shl -1, c1)), (sub c1, c2)) 2555 if (N1C && N0.getOpcode() == ISD::SRL && 2556 N0.getOperand(1).getOpcode() == ISD::Constant) { 2557 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 2558 if (c1 < VT.getSizeInBits()) { 2559 uint64_t c2 = N1C->getZExtValue(); 2560 SDValue HiBitsMask = 2561 DAG.getConstant(APInt::getHighBitsSet(VT.getSizeInBits(), 2562 VT.getSizeInBits() - c1), 2563 VT); 2564 SDValue Mask = DAG.getNode(ISD::AND, N0.getDebugLoc(), VT, 2565 N0.getOperand(0), 2566 HiBitsMask); 2567 if (c2 > c1) 2568 return DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, Mask, 2569 DAG.getConstant(c2-c1, N1.getValueType())); 2570 else 2571 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, Mask, 2572 DAG.getConstant(c1-c2, N1.getValueType())); 2573 } 2574 } 2575 // fold (shl (sra x, c1), c1) -> (and x, (shl -1, c1)) 2576 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) { 2577 SDValue HiBitsMask = 2578 DAG.getConstant(APInt::getHighBitsSet(VT.getSizeInBits(), 2579 VT.getSizeInBits() - 2580 N1C->getZExtValue()), 2581 VT); 2582 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0), 2583 HiBitsMask); 2584 } 2585 2586 return N1C ? visitShiftByConstant(N, N1C->getZExtValue()) : SDValue(); 2587} 2588 2589SDValue DAGCombiner::visitSRA(SDNode *N) { 2590 SDValue N0 = N->getOperand(0); 2591 SDValue N1 = N->getOperand(1); 2592 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2593 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2594 EVT VT = N0.getValueType(); 2595 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits(); 2596 2597 // fold (sra c1, c2) -> (sra c1, c2) 2598 if (N0C && N1C) 2599 return DAG.FoldConstantArithmetic(ISD::SRA, VT, N0C, N1C); 2600 // fold (sra 0, x) -> 0 2601 if (N0C && N0C->isNullValue()) 2602 return N0; 2603 // fold (sra -1, x) -> -1 2604 if (N0C && N0C->isAllOnesValue()) 2605 return N0; 2606 // fold (sra x, (setge c, size(x))) -> undef 2607 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 2608 return DAG.getUNDEF(VT); 2609 // fold (sra x, 0) -> x 2610 if (N1C && N1C->isNullValue()) 2611 return N0; 2612 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports 2613 // sext_inreg. 2614 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) { 2615 unsigned LowBits = OpSizeInBits - (unsigned)N1C->getZExtValue(); 2616 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), LowBits); 2617 if (VT.isVector()) 2618 ExtVT = EVT::getVectorVT(*DAG.getContext(), 2619 ExtVT, VT.getVectorNumElements()); 2620 if ((!LegalOperations || 2621 TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, ExtVT))) 2622 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, 2623 N0.getOperand(0), DAG.getValueType(ExtVT)); 2624 } 2625 2626 // fold (sra (sra x, c1), c2) -> (sra x, (add c1, c2)) 2627 if (N1C && N0.getOpcode() == ISD::SRA) { 2628 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 2629 unsigned Sum = N1C->getZExtValue() + C1->getZExtValue(); 2630 if (Sum >= OpSizeInBits) Sum = OpSizeInBits-1; 2631 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0.getOperand(0), 2632 DAG.getConstant(Sum, N1C->getValueType(0))); 2633 } 2634 } 2635 2636 // fold (sra (shl X, m), (sub result_size, n)) 2637 // -> (sign_extend (trunc (shl X, (sub (sub result_size, n), m)))) for 2638 // result_size - n != m. 2639 // If truncate is free for the target sext(shl) is likely to result in better 2640 // code. 2641 if (N0.getOpcode() == ISD::SHL) { 2642 // Get the two constanst of the shifts, CN0 = m, CN = n. 2643 const ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2644 if (N01C && N1C) { 2645 // Determine what the truncate's result bitsize and type would be. 2646 EVT TruncVT = 2647 EVT::getIntegerVT(*DAG.getContext(), OpSizeInBits - N1C->getZExtValue()); 2648 // Determine the residual right-shift amount. 2649 signed ShiftAmt = N1C->getZExtValue() - N01C->getZExtValue(); 2650 2651 // If the shift is not a no-op (in which case this should be just a sign 2652 // extend already), the truncated to type is legal, sign_extend is legal 2653 // on that type, and the truncate to that type is both legal and free, 2654 // perform the transform. 2655 if ((ShiftAmt > 0) && 2656 TLI.isOperationLegalOrCustom(ISD::SIGN_EXTEND, TruncVT) && 2657 TLI.isOperationLegalOrCustom(ISD::TRUNCATE, VT) && 2658 TLI.isTruncateFree(VT, TruncVT)) { 2659 2660 SDValue Amt = DAG.getConstant(ShiftAmt, getShiftAmountTy()); 2661 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, 2662 N0.getOperand(0), Amt); 2663 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), TruncVT, 2664 Shift); 2665 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), 2666 N->getValueType(0), Trunc); 2667 } 2668 } 2669 } 2670 2671 // fold (sra x, (trunc (and y, c))) -> (sra x, (and (trunc y), (trunc c))). 2672 if (N1.getOpcode() == ISD::TRUNCATE && 2673 N1.getOperand(0).getOpcode() == ISD::AND && 2674 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 2675 SDValue N101 = N1.getOperand(0).getOperand(1); 2676 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 2677 EVT TruncVT = N1.getValueType(); 2678 SDValue N100 = N1.getOperand(0).getOperand(0); 2679 APInt TruncC = N101C->getAPIntValue(); 2680 TruncC.trunc(TruncVT.getScalarType().getSizeInBits()); 2681 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, N0, 2682 DAG.getNode(ISD::AND, N->getDebugLoc(), 2683 TruncVT, 2684 DAG.getNode(ISD::TRUNCATE, 2685 N->getDebugLoc(), 2686 TruncVT, N100), 2687 DAG.getConstant(TruncC, TruncVT))); 2688 } 2689 } 2690 2691 // Simplify, based on bits shifted out of the LHS. 2692 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 2693 return SDValue(N, 0); 2694 2695 2696 // If the sign bit is known to be zero, switch this to a SRL. 2697 if (DAG.SignBitIsZero(N0)) 2698 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, N1); 2699 2700 return N1C ? visitShiftByConstant(N, N1C->getZExtValue()) : SDValue(); 2701} 2702 2703SDValue DAGCombiner::visitSRL(SDNode *N) { 2704 SDValue N0 = N->getOperand(0); 2705 SDValue N1 = N->getOperand(1); 2706 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2707 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2708 EVT VT = N0.getValueType(); 2709 unsigned OpSizeInBits = VT.getScalarType().getSizeInBits(); 2710 2711 // fold (srl c1, c2) -> c1 >>u c2 2712 if (N0C && N1C) 2713 return DAG.FoldConstantArithmetic(ISD::SRL, VT, N0C, N1C); 2714 // fold (srl 0, x) -> 0 2715 if (N0C && N0C->isNullValue()) 2716 return N0; 2717 // fold (srl x, c >= size(x)) -> undef 2718 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 2719 return DAG.getUNDEF(VT); 2720 // fold (srl x, 0) -> x 2721 if (N1C && N1C->isNullValue()) 2722 return N0; 2723 // if (srl x, c) is known to be zero, return 0 2724 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0), 2725 APInt::getAllOnesValue(OpSizeInBits))) 2726 return DAG.getConstant(0, VT); 2727 2728 // fold (srl (srl x, c1), c2) -> 0 or (srl x, (add c1, c2)) 2729 if (N1C && N0.getOpcode() == ISD::SRL && 2730 N0.getOperand(1).getOpcode() == ISD::Constant) { 2731 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 2732 uint64_t c2 = N1C->getZExtValue(); 2733 if (c1 + c2 > OpSizeInBits) 2734 return DAG.getConstant(0, VT); 2735 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), 2736 DAG.getConstant(c1 + c2, N1.getValueType())); 2737 } 2738 2739 // fold (srl (shl x, c), c) -> (and x, cst2) 2740 if (N1C && N0.getOpcode() == ISD::SHL && N0.getOperand(1) == N1 && 2741 N0.getValueSizeInBits() <= 64) { 2742 uint64_t ShAmt = N1C->getZExtValue()+64-N0.getValueSizeInBits(); 2743 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0.getOperand(0), 2744 DAG.getConstant(~0ULL >> ShAmt, VT)); 2745 } 2746 2747 2748 // fold (srl (anyextend x), c) -> (anyextend (srl x, c)) 2749 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 2750 // Shifting in all undef bits? 2751 EVT SmallVT = N0.getOperand(0).getValueType(); 2752 if (N1C->getZExtValue() >= SmallVT.getSizeInBits()) 2753 return DAG.getUNDEF(VT); 2754 2755 SDValue SmallShift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), SmallVT, 2756 N0.getOperand(0), N1); 2757 AddToWorkList(SmallShift.getNode()); 2758 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, SmallShift); 2759 } 2760 2761 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign 2762 // bit, which is unmodified by sra. 2763 if (N1C && N1C->getZExtValue() + 1 == VT.getSizeInBits()) { 2764 if (N0.getOpcode() == ISD::SRA) 2765 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0.getOperand(0), N1); 2766 } 2767 2768 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit). 2769 if (N1C && N0.getOpcode() == ISD::CTLZ && 2770 N1C->getAPIntValue() == Log2_32(VT.getSizeInBits())) { 2771 APInt KnownZero, KnownOne; 2772 APInt Mask = APInt::getAllOnesValue(VT.getScalarType().getSizeInBits()); 2773 DAG.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne); 2774 2775 // If any of the input bits are KnownOne, then the input couldn't be all 2776 // zeros, thus the result of the srl will always be zero. 2777 if (KnownOne.getBoolValue()) return DAG.getConstant(0, VT); 2778 2779 // If all of the bits input the to ctlz node are known to be zero, then 2780 // the result of the ctlz is "32" and the result of the shift is one. 2781 APInt UnknownBits = ~KnownZero & Mask; 2782 if (UnknownBits == 0) return DAG.getConstant(1, VT); 2783 2784 // Otherwise, check to see if there is exactly one bit input to the ctlz. 2785 if ((UnknownBits & (UnknownBits - 1)) == 0) { 2786 // Okay, we know that only that the single bit specified by UnknownBits 2787 // could be set on input to the CTLZ node. If this bit is set, the SRL 2788 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair 2789 // to an SRL/XOR pair, which is likely to simplify more. 2790 unsigned ShAmt = UnknownBits.countTrailingZeros(); 2791 SDValue Op = N0.getOperand(0); 2792 2793 if (ShAmt) { 2794 Op = DAG.getNode(ISD::SRL, N0.getDebugLoc(), VT, Op, 2795 DAG.getConstant(ShAmt, getShiftAmountTy())); 2796 AddToWorkList(Op.getNode()); 2797 } 2798 2799 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, 2800 Op, DAG.getConstant(1, VT)); 2801 } 2802 } 2803 2804 // fold (srl x, (trunc (and y, c))) -> (srl x, (and (trunc y), (trunc c))). 2805 if (N1.getOpcode() == ISD::TRUNCATE && 2806 N1.getOperand(0).getOpcode() == ISD::AND && 2807 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 2808 SDValue N101 = N1.getOperand(0).getOperand(1); 2809 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 2810 EVT TruncVT = N1.getValueType(); 2811 SDValue N100 = N1.getOperand(0).getOperand(0); 2812 APInt TruncC = N101C->getAPIntValue(); 2813 TruncC.trunc(TruncVT.getSizeInBits()); 2814 return DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, N0, 2815 DAG.getNode(ISD::AND, N->getDebugLoc(), 2816 TruncVT, 2817 DAG.getNode(ISD::TRUNCATE, 2818 N->getDebugLoc(), 2819 TruncVT, N100), 2820 DAG.getConstant(TruncC, TruncVT))); 2821 } 2822 } 2823 2824 // fold operands of srl based on knowledge that the low bits are not 2825 // demanded. 2826 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 2827 return SDValue(N, 0); 2828 2829 if (N1C) { 2830 SDValue NewSRL = visitShiftByConstant(N, N1C->getZExtValue()); 2831 if (NewSRL.getNode()) 2832 return NewSRL; 2833 } 2834 2835 // Here is a common situation. We want to optimize: 2836 // 2837 // %a = ... 2838 // %b = and i32 %a, 2 2839 // %c = srl i32 %b, 1 2840 // brcond i32 %c ... 2841 // 2842 // into 2843 // 2844 // %a = ... 2845 // %b = and %a, 2 2846 // %c = setcc eq %b, 0 2847 // brcond %c ... 2848 // 2849 // However when after the source operand of SRL is optimized into AND, the SRL 2850 // itself may not be optimized further. Look for it and add the BRCOND into 2851 // the worklist. 2852 if (N->hasOneUse()) { 2853 SDNode *Use = *N->use_begin(); 2854 if (Use->getOpcode() == ISD::BRCOND) 2855 AddToWorkList(Use); 2856 else if (Use->getOpcode() == ISD::TRUNCATE && Use->hasOneUse()) { 2857 // Also look pass the truncate. 2858 Use = *Use->use_begin(); 2859 if (Use->getOpcode() == ISD::BRCOND) 2860 AddToWorkList(Use); 2861 } 2862 } 2863 2864 return SDValue(); 2865} 2866 2867SDValue DAGCombiner::visitCTLZ(SDNode *N) { 2868 SDValue N0 = N->getOperand(0); 2869 EVT VT = N->getValueType(0); 2870 2871 // fold (ctlz c1) -> c2 2872 if (isa<ConstantSDNode>(N0)) 2873 return DAG.getNode(ISD::CTLZ, N->getDebugLoc(), VT, N0); 2874 return SDValue(); 2875} 2876 2877SDValue DAGCombiner::visitCTTZ(SDNode *N) { 2878 SDValue N0 = N->getOperand(0); 2879 EVT VT = N->getValueType(0); 2880 2881 // fold (cttz c1) -> c2 2882 if (isa<ConstantSDNode>(N0)) 2883 return DAG.getNode(ISD::CTTZ, N->getDebugLoc(), VT, N0); 2884 return SDValue(); 2885} 2886 2887SDValue DAGCombiner::visitCTPOP(SDNode *N) { 2888 SDValue N0 = N->getOperand(0); 2889 EVT VT = N->getValueType(0); 2890 2891 // fold (ctpop c1) -> c2 2892 if (isa<ConstantSDNode>(N0)) 2893 return DAG.getNode(ISD::CTPOP, N->getDebugLoc(), VT, N0); 2894 return SDValue(); 2895} 2896 2897SDValue DAGCombiner::visitSELECT(SDNode *N) { 2898 SDValue N0 = N->getOperand(0); 2899 SDValue N1 = N->getOperand(1); 2900 SDValue N2 = N->getOperand(2); 2901 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2902 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2903 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2); 2904 EVT VT = N->getValueType(0); 2905 EVT VT0 = N0.getValueType(); 2906 2907 // fold (select C, X, X) -> X 2908 if (N1 == N2) 2909 return N1; 2910 // fold (select true, X, Y) -> X 2911 if (N0C && !N0C->isNullValue()) 2912 return N1; 2913 // fold (select false, X, Y) -> Y 2914 if (N0C && N0C->isNullValue()) 2915 return N2; 2916 // fold (select C, 1, X) -> (or C, X) 2917 if (VT == MVT::i1 && N1C && N1C->getAPIntValue() == 1) 2918 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2); 2919 // fold (select C, 0, 1) -> (xor C, 1) 2920 if (VT.isInteger() && 2921 (VT0 == MVT::i1 || 2922 (VT0.isInteger() && 2923 TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent)) && 2924 N1C && N2C && N1C->isNullValue() && N2C->getAPIntValue() == 1) { 2925 SDValue XORNode; 2926 if (VT == VT0) 2927 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT0, 2928 N0, DAG.getConstant(1, VT0)); 2929 XORNode = DAG.getNode(ISD::XOR, N0.getDebugLoc(), VT0, 2930 N0, DAG.getConstant(1, VT0)); 2931 AddToWorkList(XORNode.getNode()); 2932 if (VT.bitsGT(VT0)) 2933 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, XORNode); 2934 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, XORNode); 2935 } 2936 // fold (select C, 0, X) -> (and (not C), X) 2937 if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) { 2938 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT); 2939 AddToWorkList(NOTNode.getNode()); 2940 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, NOTNode, N2); 2941 } 2942 // fold (select C, X, 1) -> (or (not C), X) 2943 if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getAPIntValue() == 1) { 2944 SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT); 2945 AddToWorkList(NOTNode.getNode()); 2946 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, NOTNode, N1); 2947 } 2948 // fold (select C, X, 0) -> (and C, X) 2949 if (VT == MVT::i1 && N2C && N2C->isNullValue()) 2950 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1); 2951 // fold (select X, X, Y) -> (or X, Y) 2952 // fold (select X, 1, Y) -> (or X, Y) 2953 if (VT == MVT::i1 && (N0 == N1 || (N1C && N1C->getAPIntValue() == 1))) 2954 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2); 2955 // fold (select X, Y, X) -> (and X, Y) 2956 // fold (select X, Y, 0) -> (and X, Y) 2957 if (VT == MVT::i1 && (N0 == N2 || (N2C && N2C->getAPIntValue() == 0))) 2958 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1); 2959 2960 // If we can fold this based on the true/false value, do so. 2961 if (SimplifySelectOps(N, N1, N2)) 2962 return SDValue(N, 0); // Don't revisit N. 2963 2964 // fold selects based on a setcc into other things, such as min/max/abs 2965 if (N0.getOpcode() == ISD::SETCC) { 2966 // FIXME: 2967 // Check against MVT::Other for SELECT_CC, which is a workaround for targets 2968 // having to say they don't support SELECT_CC on every type the DAG knows 2969 // about, since there is no way to mark an opcode illegal at all value types 2970 if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other) && 2971 TLI.isOperationLegalOrCustom(ISD::SELECT_CC, VT)) 2972 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT, 2973 N0.getOperand(0), N0.getOperand(1), 2974 N1, N2, N0.getOperand(2)); 2975 return SimplifySelect(N->getDebugLoc(), N0, N1, N2); 2976 } 2977 2978 return SDValue(); 2979} 2980 2981SDValue DAGCombiner::visitSELECT_CC(SDNode *N) { 2982 SDValue N0 = N->getOperand(0); 2983 SDValue N1 = N->getOperand(1); 2984 SDValue N2 = N->getOperand(2); 2985 SDValue N3 = N->getOperand(3); 2986 SDValue N4 = N->getOperand(4); 2987 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get(); 2988 2989 // fold select_cc lhs, rhs, x, x, cc -> x 2990 if (N2 == N3) 2991 return N2; 2992 2993 // Determine if the condition we're dealing with is constant 2994 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()), 2995 N0, N1, CC, N->getDebugLoc(), false); 2996 if (SCC.getNode()) AddToWorkList(SCC.getNode()); 2997 2998 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode())) { 2999 if (!SCCC->isNullValue()) 3000 return N2; // cond always true -> true val 3001 else 3002 return N3; // cond always false -> false val 3003 } 3004 3005 // Fold to a simpler select_cc 3006 if (SCC.getNode() && SCC.getOpcode() == ISD::SETCC) 3007 return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), N2.getValueType(), 3008 SCC.getOperand(0), SCC.getOperand(1), N2, N3, 3009 SCC.getOperand(2)); 3010 3011 // If we can fold this based on the true/false value, do so. 3012 if (SimplifySelectOps(N, N2, N3)) 3013 return SDValue(N, 0); // Don't revisit N. 3014 3015 // fold select_cc into other things, such as min/max/abs 3016 return SimplifySelectCC(N->getDebugLoc(), N0, N1, N2, N3, CC); 3017} 3018 3019SDValue DAGCombiner::visitSETCC(SDNode *N) { 3020 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1), 3021 cast<CondCodeSDNode>(N->getOperand(2))->get(), 3022 N->getDebugLoc()); 3023} 3024 3025// ExtendUsesToFormExtLoad - Trying to extend uses of a load to enable this: 3026// "fold ({s|z|a}ext (load x)) -> ({s|z|a}ext (truncate ({s|z|a}extload x)))" 3027// transformation. Returns true if extension are possible and the above 3028// mentioned transformation is profitable. 3029static bool ExtendUsesToFormExtLoad(SDNode *N, SDValue N0, 3030 unsigned ExtOpc, 3031 SmallVector<SDNode*, 4> &ExtendNodes, 3032 const TargetLowering &TLI) { 3033 bool HasCopyToRegUses = false; 3034 bool isTruncFree = TLI.isTruncateFree(N->getValueType(0), N0.getValueType()); 3035 for (SDNode::use_iterator UI = N0.getNode()->use_begin(), 3036 UE = N0.getNode()->use_end(); 3037 UI != UE; ++UI) { 3038 SDNode *User = *UI; 3039 if (User == N) 3040 continue; 3041 if (UI.getUse().getResNo() != N0.getResNo()) 3042 continue; 3043 // FIXME: Only extend SETCC N, N and SETCC N, c for now. 3044 if (ExtOpc != ISD::ANY_EXTEND && User->getOpcode() == ISD::SETCC) { 3045 ISD::CondCode CC = cast<CondCodeSDNode>(User->getOperand(2))->get(); 3046 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC)) 3047 // Sign bits will be lost after a zext. 3048 return false; 3049 bool Add = false; 3050 for (unsigned i = 0; i != 2; ++i) { 3051 SDValue UseOp = User->getOperand(i); 3052 if (UseOp == N0) 3053 continue; 3054 if (!isa<ConstantSDNode>(UseOp)) 3055 return false; 3056 Add = true; 3057 } 3058 if (Add) 3059 ExtendNodes.push_back(User); 3060 continue; 3061 } 3062 // If truncates aren't free and there are users we can't 3063 // extend, it isn't worthwhile. 3064 if (!isTruncFree) 3065 return false; 3066 // Remember if this value is live-out. 3067 if (User->getOpcode() == ISD::CopyToReg) 3068 HasCopyToRegUses = true; 3069 } 3070 3071 if (HasCopyToRegUses) { 3072 bool BothLiveOut = false; 3073 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 3074 UI != UE; ++UI) { 3075 SDUse &Use = UI.getUse(); 3076 if (Use.getResNo() == 0 && Use.getUser()->getOpcode() == ISD::CopyToReg) { 3077 BothLiveOut = true; 3078 break; 3079 } 3080 } 3081 if (BothLiveOut) 3082 // Both unextended and extended values are live out. There had better be 3083 // good a reason for the transformation. 3084 return ExtendNodes.size(); 3085 } 3086 return true; 3087} 3088 3089SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) { 3090 SDValue N0 = N->getOperand(0); 3091 EVT VT = N->getValueType(0); 3092 3093 // fold (sext c1) -> c1 3094 if (isa<ConstantSDNode>(N0)) 3095 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N0); 3096 3097 // fold (sext (sext x)) -> (sext x) 3098 // fold (sext (aext x)) -> (sext x) 3099 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 3100 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, 3101 N0.getOperand(0)); 3102 3103 if (N0.getOpcode() == ISD::TRUNCATE) { 3104 // fold (sext (truncate (load x))) -> (sext (smaller load x)) 3105 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n))) 3106 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 3107 if (NarrowLoad.getNode()) { 3108 if (NarrowLoad.getNode() != N0.getNode()) 3109 CombineTo(N0.getNode(), NarrowLoad); 3110 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3111 } 3112 3113 // See if the value being truncated is already sign extended. If so, just 3114 // eliminate the trunc/sext pair. 3115 SDValue Op = N0.getOperand(0); 3116 unsigned OpBits = Op.getValueType().getScalarType().getSizeInBits(); 3117 unsigned MidBits = N0.getValueType().getScalarType().getSizeInBits(); 3118 unsigned DestBits = VT.getScalarType().getSizeInBits(); 3119 unsigned NumSignBits = DAG.ComputeNumSignBits(Op); 3120 3121 if (OpBits == DestBits) { 3122 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign 3123 // bits, it is already ready. 3124 if (NumSignBits > DestBits-MidBits) 3125 return Op; 3126 } else if (OpBits < DestBits) { 3127 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign 3128 // bits, just sext from i32. 3129 if (NumSignBits > OpBits-MidBits) 3130 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, Op); 3131 } else { 3132 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign 3133 // bits, just truncate to i32. 3134 if (NumSignBits > OpBits-MidBits) 3135 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op); 3136 } 3137 3138 // fold (sext (truncate x)) -> (sextinreg x). 3139 if (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, 3140 N0.getValueType())) { 3141 if (OpBits < DestBits) 3142 Op = DAG.getNode(ISD::ANY_EXTEND, N0.getDebugLoc(), VT, Op); 3143 else if (OpBits > DestBits) 3144 Op = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), VT, Op); 3145 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, Op, 3146 DAG.getValueType(N0.getValueType())); 3147 } 3148 } 3149 3150 // fold (sext (load x)) -> (sext (truncate (sextload x))) 3151 if (ISD::isNON_EXTLoad(N0.getNode()) && 3152 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3153 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()))) { 3154 bool DoXform = true; 3155 SmallVector<SDNode*, 4> SetCCs; 3156 if (!N0.hasOneUse()) 3157 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::SIGN_EXTEND, SetCCs, TLI); 3158 if (DoXform) { 3159 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3160 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 3161 LN0->getChain(), 3162 LN0->getBasePtr(), LN0->getSrcValue(), 3163 LN0->getSrcValueOffset(), 3164 N0.getValueType(), 3165 LN0->isVolatile(), LN0->isNonTemporal(), 3166 LN0->getAlignment()); 3167 CombineTo(N, ExtLoad); 3168 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3169 N0.getValueType(), ExtLoad); 3170 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 3171 3172 // Extend SetCC uses if necessary. 3173 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 3174 SDNode *SetCC = SetCCs[i]; 3175 SmallVector<SDValue, 4> Ops; 3176 3177 for (unsigned j = 0; j != 2; ++j) { 3178 SDValue SOp = SetCC->getOperand(j); 3179 if (SOp == Trunc) 3180 Ops.push_back(ExtLoad); 3181 else 3182 Ops.push_back(DAG.getNode(ISD::SIGN_EXTEND, 3183 N->getDebugLoc(), VT, SOp)); 3184 } 3185 3186 Ops.push_back(SetCC->getOperand(2)); 3187 CombineTo(SetCC, DAG.getNode(ISD::SETCC, N->getDebugLoc(), 3188 SetCC->getValueType(0), 3189 &Ops[0], Ops.size())); 3190 } 3191 3192 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3193 } 3194 } 3195 3196 // fold (sext (sextload x)) -> (sext (truncate (sextload x))) 3197 // fold (sext ( extload x)) -> (sext (truncate (sextload x))) 3198 if ((ISD::isSEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) && 3199 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) { 3200 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3201 EVT MemVT = LN0->getMemoryVT(); 3202 if ((!LegalOperations && !LN0->isVolatile()) || 3203 TLI.isLoadExtLegal(ISD::SEXTLOAD, MemVT)) { 3204 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 3205 LN0->getChain(), 3206 LN0->getBasePtr(), LN0->getSrcValue(), 3207 LN0->getSrcValueOffset(), MemVT, 3208 LN0->isVolatile(), LN0->isNonTemporal(), 3209 LN0->getAlignment()); 3210 CombineTo(N, ExtLoad); 3211 CombineTo(N0.getNode(), 3212 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3213 N0.getValueType(), ExtLoad), 3214 ExtLoad.getValue(1)); 3215 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3216 } 3217 } 3218 3219 if (N0.getOpcode() == ISD::SETCC) { 3220 // sext(setcc) -> sext_in_reg(vsetcc) for vectors. 3221 if (VT.isVector() && 3222 // We know that the # elements of the results is the same as the 3223 // # elements of the compare (and the # elements of the compare result 3224 // for that matter). Check to see that they are the same size. If so, 3225 // we know that the element size of the sext'd result matches the 3226 // element size of the compare operands. 3227 VT.getSizeInBits() == N0.getOperand(0).getValueType().getSizeInBits() && 3228 3229 // Only do this before legalize for now. 3230 !LegalOperations) { 3231 return DAG.getVSetCC(N->getDebugLoc(), VT, N0.getOperand(0), 3232 N0.getOperand(1), 3233 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 3234 } 3235 3236 // sext(setcc x, y, cc) -> (select_cc x, y, -1, 0, cc) 3237 SDValue NegOne = 3238 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), VT); 3239 SDValue SCC = 3240 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 3241 NegOne, DAG.getConstant(0, VT), 3242 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 3243 if (SCC.getNode()) return SCC; 3244 if (!LegalOperations || 3245 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(VT))) 3246 return DAG.getNode(ISD::SELECT, N->getDebugLoc(), VT, 3247 DAG.getSetCC(N->getDebugLoc(), 3248 TLI.getSetCCResultType(VT), 3249 N0.getOperand(0), N0.getOperand(1), 3250 cast<CondCodeSDNode>(N0.getOperand(2))->get()), 3251 NegOne, DAG.getConstant(0, VT)); 3252 } 3253 3254 3255 3256 // fold (sext x) -> (zext x) if the sign bit is known zero. 3257 if ((!LegalOperations || TLI.isOperationLegal(ISD::ZERO_EXTEND, VT)) && 3258 DAG.SignBitIsZero(N0)) 3259 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0); 3260 3261 return SDValue(); 3262} 3263 3264SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) { 3265 SDValue N0 = N->getOperand(0); 3266 EVT VT = N->getValueType(0); 3267 3268 // fold (zext c1) -> c1 3269 if (isa<ConstantSDNode>(N0)) 3270 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, N0); 3271 // fold (zext (zext x)) -> (zext x) 3272 // fold (zext (aext x)) -> (zext x) 3273 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 3274 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, 3275 N0.getOperand(0)); 3276 3277 // fold (zext (truncate (load x))) -> (zext (smaller load x)) 3278 // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n))) 3279 if (N0.getOpcode() == ISD::TRUNCATE) { 3280 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 3281 if (NarrowLoad.getNode()) { 3282 if (NarrowLoad.getNode() != N0.getNode()) 3283 CombineTo(N0.getNode(), NarrowLoad); 3284 return DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), VT, NarrowLoad); 3285 } 3286 } 3287 3288 // fold (zext (truncate x)) -> (and x, mask) 3289 if (N0.getOpcode() == ISD::TRUNCATE && 3290 (!LegalOperations || TLI.isOperationLegal(ISD::AND, VT)) && 3291 (!TLI.isTruncateFree(N0.getOperand(0).getValueType(), 3292 N0.getValueType()) || 3293 !TLI.isZExtFree(N0.getValueType(), VT))) { 3294 SDValue Op = N0.getOperand(0); 3295 if (Op.getValueType().bitsLT(VT)) { 3296 Op = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, Op); 3297 } else if (Op.getValueType().bitsGT(VT)) { 3298 Op = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Op); 3299 } 3300 return DAG.getZeroExtendInReg(Op, N->getDebugLoc(), 3301 N0.getValueType().getScalarType()); 3302 } 3303 3304 // Fold (zext (and (trunc x), cst)) -> (and x, cst), 3305 // if either of the casts is not free. 3306 if (N0.getOpcode() == ISD::AND && 3307 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 3308 N0.getOperand(1).getOpcode() == ISD::Constant && 3309 (!TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(), 3310 N0.getValueType()) || 3311 !TLI.isZExtFree(N0.getValueType(), VT))) { 3312 SDValue X = N0.getOperand(0).getOperand(0); 3313 if (X.getValueType().bitsLT(VT)) { 3314 X = DAG.getNode(ISD::ANY_EXTEND, X.getDebugLoc(), VT, X); 3315 } else if (X.getValueType().bitsGT(VT)) { 3316 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X); 3317 } 3318 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 3319 Mask.zext(VT.getSizeInBits()); 3320 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 3321 X, DAG.getConstant(Mask, VT)); 3322 } 3323 3324 // fold (zext (load x)) -> (zext (truncate (zextload x))) 3325 if (ISD::isNON_EXTLoad(N0.getNode()) && 3326 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3327 TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()))) { 3328 bool DoXform = true; 3329 SmallVector<SDNode*, 4> SetCCs; 3330 if (!N0.hasOneUse()) 3331 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ZERO_EXTEND, SetCCs, TLI); 3332 if (DoXform) { 3333 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3334 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT, 3335 LN0->getChain(), 3336 LN0->getBasePtr(), LN0->getSrcValue(), 3337 LN0->getSrcValueOffset(), 3338 N0.getValueType(), 3339 LN0->isVolatile(), LN0->isNonTemporal(), 3340 LN0->getAlignment()); 3341 CombineTo(N, ExtLoad); 3342 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3343 N0.getValueType(), ExtLoad); 3344 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 3345 3346 // Extend SetCC uses if necessary. 3347 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 3348 SDNode *SetCC = SetCCs[i]; 3349 SmallVector<SDValue, 4> Ops; 3350 3351 for (unsigned j = 0; j != 2; ++j) { 3352 SDValue SOp = SetCC->getOperand(j); 3353 if (SOp == Trunc) 3354 Ops.push_back(ExtLoad); 3355 else 3356 Ops.push_back(DAG.getNode(ISD::ZERO_EXTEND, 3357 N->getDebugLoc(), VT, SOp)); 3358 } 3359 3360 Ops.push_back(SetCC->getOperand(2)); 3361 CombineTo(SetCC, DAG.getNode(ISD::SETCC, N->getDebugLoc(), 3362 SetCC->getValueType(0), 3363 &Ops[0], Ops.size())); 3364 } 3365 3366 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3367 } 3368 } 3369 3370 // fold (zext (zextload x)) -> (zext (truncate (zextload x))) 3371 // fold (zext ( extload x)) -> (zext (truncate (zextload x))) 3372 if ((ISD::isZEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) && 3373 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) { 3374 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3375 EVT MemVT = LN0->getMemoryVT(); 3376 if ((!LegalOperations && !LN0->isVolatile()) || 3377 TLI.isLoadExtLegal(ISD::ZEXTLOAD, MemVT)) { 3378 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT, 3379 LN0->getChain(), 3380 LN0->getBasePtr(), LN0->getSrcValue(), 3381 LN0->getSrcValueOffset(), MemVT, 3382 LN0->isVolatile(), LN0->isNonTemporal(), 3383 LN0->getAlignment()); 3384 CombineTo(N, ExtLoad); 3385 CombineTo(N0.getNode(), 3386 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), N0.getValueType(), 3387 ExtLoad), 3388 ExtLoad.getValue(1)); 3389 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3390 } 3391 } 3392 3393 // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 3394 if (N0.getOpcode() == ISD::SETCC) { 3395 SDValue SCC = 3396 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 3397 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 3398 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 3399 if (SCC.getNode()) return SCC; 3400 } 3401 3402 // (zext (shl (zext x), cst)) -> (shl (zext x), cst) 3403 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL) && 3404 isa<ConstantSDNode>(N0.getOperand(1)) && 3405 N0.getOperand(0).getOpcode() == ISD::ZERO_EXTEND && 3406 N0.hasOneUse()) { 3407 if (N0.getOpcode() == ISD::SHL) { 3408 // If the original shl may be shifting out bits, do not perform this 3409 // transformation. 3410 unsigned ShAmt = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 3411 unsigned KnownZeroBits = N0.getOperand(0).getValueType().getSizeInBits() - 3412 N0.getOperand(0).getOperand(0).getValueType().getSizeInBits(); 3413 if (ShAmt > KnownZeroBits) 3414 return SDValue(); 3415 } 3416 DebugLoc dl = N->getDebugLoc(); 3417 return DAG.getNode(N0.getOpcode(), dl, VT, 3418 DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0.getOperand(0)), 3419 DAG.getNode(ISD::ZERO_EXTEND, dl, 3420 N0.getOperand(1).getValueType(), 3421 N0.getOperand(1))); 3422 } 3423 3424 return SDValue(); 3425} 3426 3427SDValue DAGCombiner::visitANY_EXTEND(SDNode *N) { 3428 SDValue N0 = N->getOperand(0); 3429 EVT VT = N->getValueType(0); 3430 3431 // fold (aext c1) -> c1 3432 if (isa<ConstantSDNode>(N0)) 3433 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, N0); 3434 // fold (aext (aext x)) -> (aext x) 3435 // fold (aext (zext x)) -> (zext x) 3436 // fold (aext (sext x)) -> (sext x) 3437 if (N0.getOpcode() == ISD::ANY_EXTEND || 3438 N0.getOpcode() == ISD::ZERO_EXTEND || 3439 N0.getOpcode() == ISD::SIGN_EXTEND) 3440 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, N0.getOperand(0)); 3441 3442 // fold (aext (truncate (load x))) -> (aext (smaller load x)) 3443 // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n))) 3444 if (N0.getOpcode() == ISD::TRUNCATE) { 3445 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 3446 if (NarrowLoad.getNode()) { 3447 if (NarrowLoad.getNode() != N0.getNode()) 3448 CombineTo(N0.getNode(), NarrowLoad); 3449 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, NarrowLoad); 3450 } 3451 } 3452 3453 // fold (aext (truncate x)) 3454 if (N0.getOpcode() == ISD::TRUNCATE) { 3455 SDValue TruncOp = N0.getOperand(0); 3456 if (TruncOp.getValueType() == VT) 3457 return TruncOp; // x iff x size == zext size. 3458 if (TruncOp.getValueType().bitsGT(VT)) 3459 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, TruncOp); 3460 return DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, TruncOp); 3461 } 3462 3463 // Fold (aext (and (trunc x), cst)) -> (and x, cst) 3464 // if the trunc is not free. 3465 if (N0.getOpcode() == ISD::AND && 3466 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 3467 N0.getOperand(1).getOpcode() == ISD::Constant && 3468 !TLI.isTruncateFree(N0.getOperand(0).getOperand(0).getValueType(), 3469 N0.getValueType())) { 3470 SDValue X = N0.getOperand(0).getOperand(0); 3471 if (X.getValueType().bitsLT(VT)) { 3472 X = DAG.getNode(ISD::ANY_EXTEND, N->getDebugLoc(), VT, X); 3473 } else if (X.getValueType().bitsGT(VT)) { 3474 X = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, X); 3475 } 3476 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 3477 Mask.zext(VT.getSizeInBits()); 3478 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 3479 X, DAG.getConstant(Mask, VT)); 3480 } 3481 3482 // fold (aext (load x)) -> (aext (truncate (extload x))) 3483 if (ISD::isNON_EXTLoad(N0.getNode()) && 3484 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3485 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) { 3486 bool DoXform = true; 3487 SmallVector<SDNode*, 4> SetCCs; 3488 if (!N0.hasOneUse()) 3489 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ANY_EXTEND, SetCCs, TLI); 3490 if (DoXform) { 3491 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3492 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT, 3493 LN0->getChain(), 3494 LN0->getBasePtr(), LN0->getSrcValue(), 3495 LN0->getSrcValueOffset(), 3496 N0.getValueType(), 3497 LN0->isVolatile(), LN0->isNonTemporal(), 3498 LN0->getAlignment()); 3499 CombineTo(N, ExtLoad); 3500 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3501 N0.getValueType(), ExtLoad); 3502 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 3503 3504 // Extend SetCC uses if necessary. 3505 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 3506 SDNode *SetCC = SetCCs[i]; 3507 SmallVector<SDValue, 4> Ops; 3508 3509 for (unsigned j = 0; j != 2; ++j) { 3510 SDValue SOp = SetCC->getOperand(j); 3511 if (SOp == Trunc) 3512 Ops.push_back(ExtLoad); 3513 else 3514 Ops.push_back(DAG.getNode(ISD::ANY_EXTEND, 3515 N->getDebugLoc(), VT, SOp)); 3516 } 3517 3518 Ops.push_back(SetCC->getOperand(2)); 3519 CombineTo(SetCC, DAG.getNode(ISD::SETCC, N->getDebugLoc(), 3520 SetCC->getValueType(0), 3521 &Ops[0], Ops.size())); 3522 } 3523 3524 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3525 } 3526 } 3527 3528 // fold (aext (zextload x)) -> (aext (truncate (zextload x))) 3529 // fold (aext (sextload x)) -> (aext (truncate (sextload x))) 3530 // fold (aext ( extload x)) -> (aext (truncate (extload x))) 3531 if (N0.getOpcode() == ISD::LOAD && 3532 !ISD::isNON_EXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 3533 N0.hasOneUse()) { 3534 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3535 EVT MemVT = LN0->getMemoryVT(); 3536 SDValue ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), N->getDebugLoc(), 3537 VT, LN0->getChain(), LN0->getBasePtr(), 3538 LN0->getSrcValue(), 3539 LN0->getSrcValueOffset(), MemVT, 3540 LN0->isVolatile(), LN0->isNonTemporal(), 3541 LN0->getAlignment()); 3542 CombineTo(N, ExtLoad); 3543 CombineTo(N0.getNode(), 3544 DAG.getNode(ISD::TRUNCATE, N0.getDebugLoc(), 3545 N0.getValueType(), ExtLoad), 3546 ExtLoad.getValue(1)); 3547 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3548 } 3549 3550 // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 3551 if (N0.getOpcode() == ISD::SETCC) { 3552 SDValue SCC = 3553 SimplifySelectCC(N->getDebugLoc(), N0.getOperand(0), N0.getOperand(1), 3554 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 3555 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 3556 if (SCC.getNode()) 3557 return SCC; 3558 } 3559 3560 return SDValue(); 3561} 3562 3563/// GetDemandedBits - See if the specified operand can be simplified with the 3564/// knowledge that only the bits specified by Mask are used. If so, return the 3565/// simpler operand, otherwise return a null SDValue. 3566SDValue DAGCombiner::GetDemandedBits(SDValue V, const APInt &Mask) { 3567 switch (V.getOpcode()) { 3568 default: break; 3569 case ISD::OR: 3570 case ISD::XOR: 3571 // If the LHS or RHS don't contribute bits to the or, drop them. 3572 if (DAG.MaskedValueIsZero(V.getOperand(0), Mask)) 3573 return V.getOperand(1); 3574 if (DAG.MaskedValueIsZero(V.getOperand(1), Mask)) 3575 return V.getOperand(0); 3576 break; 3577 case ISD::SRL: 3578 // Only look at single-use SRLs. 3579 if (!V.getNode()->hasOneUse()) 3580 break; 3581 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(V.getOperand(1))) { 3582 // See if we can recursively simplify the LHS. 3583 unsigned Amt = RHSC->getZExtValue(); 3584 3585 // Watch out for shift count overflow though. 3586 if (Amt >= Mask.getBitWidth()) break; 3587 APInt NewMask = Mask << Amt; 3588 SDValue SimplifyLHS = GetDemandedBits(V.getOperand(0), NewMask); 3589 if (SimplifyLHS.getNode()) 3590 return DAG.getNode(ISD::SRL, V.getDebugLoc(), V.getValueType(), 3591 SimplifyLHS, V.getOperand(1)); 3592 } 3593 } 3594 return SDValue(); 3595} 3596 3597/// ReduceLoadWidth - If the result of a wider load is shifted to right of N 3598/// bits and then truncated to a narrower type and where N is a multiple 3599/// of number of bits of the narrower type, transform it to a narrower load 3600/// from address + N / num of bits of new type. If the result is to be 3601/// extended, also fold the extension to form a extending load. 3602SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) { 3603 unsigned Opc = N->getOpcode(); 3604 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD; 3605 SDValue N0 = N->getOperand(0); 3606 EVT VT = N->getValueType(0); 3607 EVT ExtVT = VT; 3608 3609 // This transformation isn't valid for vector loads. 3610 if (VT.isVector()) 3611 return SDValue(); 3612 3613 // Special case: SIGN_EXTEND_INREG is basically truncating to ExtVT then 3614 // extended to VT. 3615 if (Opc == ISD::SIGN_EXTEND_INREG) { 3616 ExtType = ISD::SEXTLOAD; 3617 ExtVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 3618 if (LegalOperations && !TLI.isLoadExtLegal(ISD::SEXTLOAD, ExtVT)) 3619 return SDValue(); 3620 } 3621 3622 unsigned EVTBits = ExtVT.getSizeInBits(); 3623 unsigned ShAmt = 0; 3624 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse() && ExtVT.isRound()) { 3625 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 3626 ShAmt = N01->getZExtValue(); 3627 // Is the shift amount a multiple of size of VT? 3628 if ((ShAmt & (EVTBits-1)) == 0) { 3629 N0 = N0.getOperand(0); 3630 // Is the load width a multiple of size of VT? 3631 if ((N0.getValueType().getSizeInBits() & (EVTBits-1)) != 0) 3632 return SDValue(); 3633 } 3634 } 3635 } 3636 3637 // Do not generate loads of non-round integer types since these can 3638 // be expensive (and would be wrong if the type is not byte sized). 3639 if (isa<LoadSDNode>(N0) && N0.hasOneUse() && ExtVT.isRound() && 3640 cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits() > EVTBits && 3641 // Do not change the width of a volatile load. 3642 !cast<LoadSDNode>(N0)->isVolatile()) { 3643 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3644 EVT PtrType = N0.getOperand(1).getValueType(); 3645 3646 // For big endian targets, we need to adjust the offset to the pointer to 3647 // load the correct bytes. 3648 if (TLI.isBigEndian()) { 3649 unsigned LVTStoreBits = LN0->getMemoryVT().getStoreSizeInBits(); 3650 unsigned EVTStoreBits = ExtVT.getStoreSizeInBits(); 3651 ShAmt = LVTStoreBits - EVTStoreBits - ShAmt; 3652 } 3653 3654 uint64_t PtrOff = ShAmt / 8; 3655 unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff); 3656 SDValue NewPtr = DAG.getNode(ISD::ADD, LN0->getDebugLoc(), 3657 PtrType, LN0->getBasePtr(), 3658 DAG.getConstant(PtrOff, PtrType)); 3659 AddToWorkList(NewPtr.getNode()); 3660 3661 SDValue Load = (ExtType == ISD::NON_EXTLOAD) 3662 ? DAG.getLoad(VT, N0.getDebugLoc(), LN0->getChain(), NewPtr, 3663 LN0->getSrcValue(), LN0->getSrcValueOffset() + PtrOff, 3664 LN0->isVolatile(), LN0->isNonTemporal(), NewAlign) 3665 : DAG.getExtLoad(ExtType, N0.getDebugLoc(), VT, LN0->getChain(), NewPtr, 3666 LN0->getSrcValue(), LN0->getSrcValueOffset() + PtrOff, 3667 ExtVT, LN0->isVolatile(), LN0->isNonTemporal(), 3668 NewAlign); 3669 3670 // Replace the old load's chain with the new load's chain. 3671 WorkListRemover DeadNodes(*this); 3672 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1), 3673 &DeadNodes); 3674 3675 // Return the new loaded value. 3676 return Load; 3677 } 3678 3679 return SDValue(); 3680} 3681 3682SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) { 3683 SDValue N0 = N->getOperand(0); 3684 SDValue N1 = N->getOperand(1); 3685 EVT VT = N->getValueType(0); 3686 EVT EVT = cast<VTSDNode>(N1)->getVT(); 3687 unsigned VTBits = VT.getScalarType().getSizeInBits(); 3688 unsigned EVTBits = EVT.getScalarType().getSizeInBits(); 3689 3690 // fold (sext_in_reg c1) -> c1 3691 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF) 3692 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, N0, N1); 3693 3694 // If the input is already sign extended, just drop the extension. 3695 if (DAG.ComputeNumSignBits(N0) >= VTBits-EVTBits+1) 3696 return N0; 3697 3698 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2 3699 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 3700 EVT.bitsLT(cast<VTSDNode>(N0.getOperand(1))->getVT())) { 3701 return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT, 3702 N0.getOperand(0), N1); 3703 } 3704 3705 // fold (sext_in_reg (sext x)) -> (sext x) 3706 // fold (sext_in_reg (aext x)) -> (sext x) 3707 // if x is small enough. 3708 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) { 3709 SDValue N00 = N0.getOperand(0); 3710 if (N00.getValueType().getScalarType().getSizeInBits() < EVTBits) 3711 return DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, N00, N1); 3712 } 3713 3714 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero. 3715 if (DAG.MaskedValueIsZero(N0, APInt::getBitsSet(VTBits, EVTBits-1, EVTBits))) 3716 return DAG.getZeroExtendInReg(N0, N->getDebugLoc(), EVT); 3717 3718 // fold operands of sext_in_reg based on knowledge that the top bits are not 3719 // demanded. 3720 if (SimplifyDemandedBits(SDValue(N, 0))) 3721 return SDValue(N, 0); 3722 3723 // fold (sext_in_reg (load x)) -> (smaller sextload x) 3724 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits)) 3725 SDValue NarrowLoad = ReduceLoadWidth(N); 3726 if (NarrowLoad.getNode()) 3727 return NarrowLoad; 3728 3729 // fold (sext_in_reg (srl X, 24), i8) -> (sra X, 24) 3730 // fold (sext_in_reg (srl X, 23), i8) -> (sra X, 23) iff possible. 3731 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above. 3732 if (N0.getOpcode() == ISD::SRL) { 3733 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 3734 if (ShAmt->getZExtValue()+EVTBits <= VTBits) { 3735 // We can turn this into an SRA iff the input to the SRL is already sign 3736 // extended enough. 3737 unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0)); 3738 if (VTBits-(ShAmt->getZExtValue()+EVTBits) < InSignBits) 3739 return DAG.getNode(ISD::SRA, N->getDebugLoc(), VT, 3740 N0.getOperand(0), N0.getOperand(1)); 3741 } 3742 } 3743 3744 // fold (sext_inreg (extload x)) -> (sextload x) 3745 if (ISD::isEXTLoad(N0.getNode()) && 3746 ISD::isUNINDEXEDLoad(N0.getNode()) && 3747 EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 3748 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3749 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) { 3750 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3751 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 3752 LN0->getChain(), 3753 LN0->getBasePtr(), LN0->getSrcValue(), 3754 LN0->getSrcValueOffset(), EVT, 3755 LN0->isVolatile(), LN0->isNonTemporal(), 3756 LN0->getAlignment()); 3757 CombineTo(N, ExtLoad); 3758 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 3759 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3760 } 3761 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use 3762 if (ISD::isZEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 3763 N0.hasOneUse() && 3764 EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 3765 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3766 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) { 3767 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3768 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT, 3769 LN0->getChain(), 3770 LN0->getBasePtr(), LN0->getSrcValue(), 3771 LN0->getSrcValueOffset(), EVT, 3772 LN0->isVolatile(), LN0->isNonTemporal(), 3773 LN0->getAlignment()); 3774 CombineTo(N, ExtLoad); 3775 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 3776 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3777 } 3778 return SDValue(); 3779} 3780 3781SDValue DAGCombiner::visitTRUNCATE(SDNode *N) { 3782 SDValue N0 = N->getOperand(0); 3783 EVT VT = N->getValueType(0); 3784 3785 // noop truncate 3786 if (N0.getValueType() == N->getValueType(0)) 3787 return N0; 3788 // fold (truncate c1) -> c1 3789 if (isa<ConstantSDNode>(N0)) 3790 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0); 3791 // fold (truncate (truncate x)) -> (truncate x) 3792 if (N0.getOpcode() == ISD::TRUNCATE) 3793 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0)); 3794 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x 3795 if (N0.getOpcode() == ISD::ZERO_EXTEND || 3796 N0.getOpcode() == ISD::SIGN_EXTEND || 3797 N0.getOpcode() == ISD::ANY_EXTEND) { 3798 if (N0.getOperand(0).getValueType().bitsLT(VT)) 3799 // if the source is smaller than the dest, we still need an extend 3800 return DAG.getNode(N0.getOpcode(), N->getDebugLoc(), VT, 3801 N0.getOperand(0)); 3802 else if (N0.getOperand(0).getValueType().bitsGT(VT)) 3803 // if the source is larger than the dest, than we just need the truncate 3804 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, N0.getOperand(0)); 3805 else 3806 // if the source and dest are the same type, we can drop both the extend 3807 // and the truncate. 3808 return N0.getOperand(0); 3809 } 3810 3811 // See if we can simplify the input to this truncate through knowledge that 3812 // only the low bits are being used. For example "trunc (or (shl x, 8), y)" 3813 // -> trunc y 3814 SDValue Shorter = 3815 GetDemandedBits(N0, APInt::getLowBitsSet(N0.getValueSizeInBits(), 3816 VT.getSizeInBits())); 3817 if (Shorter.getNode()) 3818 return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, Shorter); 3819 3820 // fold (truncate (load x)) -> (smaller load x) 3821 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits)) 3822 return ReduceLoadWidth(N); 3823} 3824 3825static SDNode *getBuildPairElt(SDNode *N, unsigned i) { 3826 SDValue Elt = N->getOperand(i); 3827 if (Elt.getOpcode() != ISD::MERGE_VALUES) 3828 return Elt.getNode(); 3829 return Elt.getOperand(Elt.getResNo()).getNode(); 3830} 3831 3832/// CombineConsecutiveLoads - build_pair (load, load) -> load 3833/// if load locations are consecutive. 3834SDValue DAGCombiner::CombineConsecutiveLoads(SDNode *N, EVT VT) { 3835 assert(N->getOpcode() == ISD::BUILD_PAIR); 3836 3837 LoadSDNode *LD1 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 0)); 3838 LoadSDNode *LD2 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 1)); 3839 if (!LD1 || !LD2 || !ISD::isNON_EXTLoad(LD1) || !LD1->hasOneUse()) 3840 return SDValue(); 3841 EVT LD1VT = LD1->getValueType(0); 3842 3843 if (ISD::isNON_EXTLoad(LD2) && 3844 LD2->hasOneUse() && 3845 // If both are volatile this would reduce the number of volatile loads. 3846 // If one is volatile it might be ok, but play conservative and bail out. 3847 !LD1->isVolatile() && 3848 !LD2->isVolatile() && 3849 DAG.isConsecutiveLoad(LD2, LD1, LD1VT.getSizeInBits()/8, 1)) { 3850 unsigned Align = LD1->getAlignment(); 3851 unsigned NewAlign = TLI.getTargetData()-> 3852 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext())); 3853 3854 if (NewAlign <= Align && 3855 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) 3856 return DAG.getLoad(VT, N->getDebugLoc(), LD1->getChain(), 3857 LD1->getBasePtr(), LD1->getSrcValue(), 3858 LD1->getSrcValueOffset(), false, false, Align); 3859 } 3860 3861 return SDValue(); 3862} 3863 3864SDValue DAGCombiner::visitBIT_CONVERT(SDNode *N) { 3865 SDValue N0 = N->getOperand(0); 3866 EVT VT = N->getValueType(0); 3867 3868 // If the input is a BUILD_VECTOR with all constant elements, fold this now. 3869 // Only do this before legalize, since afterward the target may be depending 3870 // on the bitconvert. 3871 // First check to see if this is all constant. 3872 if (!LegalTypes && 3873 N0.getOpcode() == ISD::BUILD_VECTOR && N0.getNode()->hasOneUse() && 3874 VT.isVector()) { 3875 bool isSimple = true; 3876 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i) 3877 if (N0.getOperand(i).getOpcode() != ISD::UNDEF && 3878 N0.getOperand(i).getOpcode() != ISD::Constant && 3879 N0.getOperand(i).getOpcode() != ISD::ConstantFP) { 3880 isSimple = false; 3881 break; 3882 } 3883 3884 EVT DestEltVT = N->getValueType(0).getVectorElementType(); 3885 assert(!DestEltVT.isVector() && 3886 "Element type of vector ValueType must not be vector!"); 3887 if (isSimple) 3888 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(N0.getNode(), DestEltVT); 3889 } 3890 3891 // If the input is a constant, let getNode fold it. 3892 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) { 3893 SDValue Res = DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT, N0); 3894 if (Res.getNode() != N) { 3895 if (!LegalOperations || 3896 TLI.isOperationLegal(Res.getNode()->getOpcode(), VT)) 3897 return Res; 3898 3899 // Folding it resulted in an illegal node, and it's too late to 3900 // do that. Clean up the old node and forego the transformation. 3901 // Ideally this won't happen very often, because instcombine 3902 // and the earlier dagcombine runs (where illegal nodes are 3903 // permitted) should have folded most of them already. 3904 DAG.DeleteNode(Res.getNode()); 3905 } 3906 } 3907 3908 // (conv (conv x, t1), t2) -> (conv x, t2) 3909 if (N0.getOpcode() == ISD::BIT_CONVERT) 3910 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), VT, 3911 N0.getOperand(0)); 3912 3913 // fold (conv (load x)) -> (load (conv*)x) 3914 // If the resultant load doesn't need a higher alignment than the original! 3915 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() && 3916 // Do not change the width of a volatile load. 3917 !cast<LoadSDNode>(N0)->isVolatile() && 3918 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) { 3919 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3920 unsigned Align = TLI.getTargetData()-> 3921 getABITypeAlignment(VT.getTypeForEVT(*DAG.getContext())); 3922 unsigned OrigAlign = LN0->getAlignment(); 3923 3924 if (Align <= OrigAlign) { 3925 SDValue Load = DAG.getLoad(VT, N->getDebugLoc(), LN0->getChain(), 3926 LN0->getBasePtr(), 3927 LN0->getSrcValue(), LN0->getSrcValueOffset(), 3928 LN0->isVolatile(), LN0->isNonTemporal(), 3929 OrigAlign); 3930 AddToWorkList(N); 3931 CombineTo(N0.getNode(), 3932 DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(), 3933 N0.getValueType(), Load), 3934 Load.getValue(1)); 3935 return Load; 3936 } 3937 } 3938 3939 // fold (bitconvert (fneg x)) -> (xor (bitconvert x), signbit) 3940 // fold (bitconvert (fabs x)) -> (and (bitconvert x), (not signbit)) 3941 // This often reduces constant pool loads. 3942 if ((N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FABS) && 3943 N0.getNode()->hasOneUse() && VT.isInteger() && !VT.isVector()) { 3944 SDValue NewConv = DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(), VT, 3945 N0.getOperand(0)); 3946 AddToWorkList(NewConv.getNode()); 3947 3948 APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); 3949 if (N0.getOpcode() == ISD::FNEG) 3950 return DAG.getNode(ISD::XOR, N->getDebugLoc(), VT, 3951 NewConv, DAG.getConstant(SignBit, VT)); 3952 assert(N0.getOpcode() == ISD::FABS); 3953 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 3954 NewConv, DAG.getConstant(~SignBit, VT)); 3955 } 3956 3957 // fold (bitconvert (fcopysign cst, x)) -> 3958 // (or (and (bitconvert x), sign), (and cst, (not sign))) 3959 // Note that we don't handle (copysign x, cst) because this can always be 3960 // folded to an fneg or fabs. 3961 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse() && 3962 isa<ConstantFPSDNode>(N0.getOperand(0)) && 3963 VT.isInteger() && !VT.isVector()) { 3964 unsigned OrigXWidth = N0.getOperand(1).getValueType().getSizeInBits(); 3965 EVT IntXVT = EVT::getIntegerVT(*DAG.getContext(), OrigXWidth); 3966 if (isTypeLegal(IntXVT)) { 3967 SDValue X = DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(), 3968 IntXVT, N0.getOperand(1)); 3969 AddToWorkList(X.getNode()); 3970 3971 // If X has a different width than the result/lhs, sext it or truncate it. 3972 unsigned VTWidth = VT.getSizeInBits(); 3973 if (OrigXWidth < VTWidth) { 3974 X = DAG.getNode(ISD::SIGN_EXTEND, N->getDebugLoc(), VT, X); 3975 AddToWorkList(X.getNode()); 3976 } else if (OrigXWidth > VTWidth) { 3977 // To get the sign bit in the right place, we have to shift it right 3978 // before truncating. 3979 X = DAG.getNode(ISD::SRL, X.getDebugLoc(), 3980 X.getValueType(), X, 3981 DAG.getConstant(OrigXWidth-VTWidth, X.getValueType())); 3982 AddToWorkList(X.getNode()); 3983 X = DAG.getNode(ISD::TRUNCATE, X.getDebugLoc(), VT, X); 3984 AddToWorkList(X.getNode()); 3985 } 3986 3987 APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); 3988 X = DAG.getNode(ISD::AND, X.getDebugLoc(), VT, 3989 X, DAG.getConstant(SignBit, VT)); 3990 AddToWorkList(X.getNode()); 3991 3992 SDValue Cst = DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(), 3993 VT, N0.getOperand(0)); 3994 Cst = DAG.getNode(ISD::AND, Cst.getDebugLoc(), VT, 3995 Cst, DAG.getConstant(~SignBit, VT)); 3996 AddToWorkList(Cst.getNode()); 3997 3998 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, X, Cst); 3999 } 4000 } 4001 4002 // bitconvert(build_pair(ld, ld)) -> ld iff load locations are consecutive. 4003 if (N0.getOpcode() == ISD::BUILD_PAIR) { 4004 SDValue CombineLD = CombineConsecutiveLoads(N0.getNode(), VT); 4005 if (CombineLD.getNode()) 4006 return CombineLD; 4007 } 4008 4009 return SDValue(); 4010} 4011 4012SDValue DAGCombiner::visitBUILD_PAIR(SDNode *N) { 4013 EVT VT = N->getValueType(0); 4014 return CombineConsecutiveLoads(N, VT); 4015} 4016 4017/// ConstantFoldBIT_CONVERTofBUILD_VECTOR - We know that BV is a build_vector 4018/// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the 4019/// destination element value type. 4020SDValue DAGCombiner:: 4021ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *BV, EVT DstEltVT) { 4022 EVT SrcEltVT = BV->getValueType(0).getVectorElementType(); 4023 4024 // If this is already the right type, we're done. 4025 if (SrcEltVT == DstEltVT) return SDValue(BV, 0); 4026 4027 unsigned SrcBitSize = SrcEltVT.getSizeInBits(); 4028 unsigned DstBitSize = DstEltVT.getSizeInBits(); 4029 4030 // If this is a conversion of N elements of one type to N elements of another 4031 // type, convert each element. This handles FP<->INT cases. 4032 if (SrcBitSize == DstBitSize) { 4033 SmallVector<SDValue, 8> Ops; 4034 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 4035 SDValue Op = BV->getOperand(i); 4036 // If the vector element type is not legal, the BUILD_VECTOR operands 4037 // are promoted and implicitly truncated. Make that explicit here. 4038 if (Op.getValueType() != SrcEltVT) 4039 Op = DAG.getNode(ISD::TRUNCATE, BV->getDebugLoc(), SrcEltVT, Op); 4040 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, BV->getDebugLoc(), 4041 DstEltVT, Op)); 4042 AddToWorkList(Ops.back().getNode()); 4043 } 4044 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, 4045 BV->getValueType(0).getVectorNumElements()); 4046 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 4047 &Ops[0], Ops.size()); 4048 } 4049 4050 // Otherwise, we're growing or shrinking the elements. To avoid having to 4051 // handle annoying details of growing/shrinking FP values, we convert them to 4052 // int first. 4053 if (SrcEltVT.isFloatingPoint()) { 4054 // Convert the input float vector to a int vector where the elements are the 4055 // same sizes. 4056 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!"); 4057 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), SrcEltVT.getSizeInBits()); 4058 BV = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, IntVT).getNode(); 4059 SrcEltVT = IntVT; 4060 } 4061 4062 // Now we know the input is an integer vector. If the output is a FP type, 4063 // convert to integer first, then to FP of the right size. 4064 if (DstEltVT.isFloatingPoint()) { 4065 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!"); 4066 EVT TmpVT = EVT::getIntegerVT(*DAG.getContext(), DstEltVT.getSizeInBits()); 4067 SDNode *Tmp = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, TmpVT).getNode(); 4068 4069 // Next, convert to FP elements of the same size. 4070 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(Tmp, DstEltVT); 4071 } 4072 4073 // Okay, we know the src/dst types are both integers of differing types. 4074 // Handling growing first. 4075 assert(SrcEltVT.isInteger() && DstEltVT.isInteger()); 4076 if (SrcBitSize < DstBitSize) { 4077 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize; 4078 4079 SmallVector<SDValue, 8> Ops; 4080 for (unsigned i = 0, e = BV->getNumOperands(); i != e; 4081 i += NumInputsPerOutput) { 4082 bool isLE = TLI.isLittleEndian(); 4083 APInt NewBits = APInt(DstBitSize, 0); 4084 bool EltIsUndef = true; 4085 for (unsigned j = 0; j != NumInputsPerOutput; ++j) { 4086 // Shift the previously computed bits over. 4087 NewBits <<= SrcBitSize; 4088 SDValue Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j)); 4089 if (Op.getOpcode() == ISD::UNDEF) continue; 4090 EltIsUndef = false; 4091 4092 NewBits |= APInt(cast<ConstantSDNode>(Op)->getAPIntValue()). 4093 zextOrTrunc(SrcBitSize).zext(DstBitSize); 4094 } 4095 4096 if (EltIsUndef) 4097 Ops.push_back(DAG.getUNDEF(DstEltVT)); 4098 else 4099 Ops.push_back(DAG.getConstant(NewBits, DstEltVT)); 4100 } 4101 4102 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, Ops.size()); 4103 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 4104 &Ops[0], Ops.size()); 4105 } 4106 4107 // Finally, this must be the case where we are shrinking elements: each input 4108 // turns into multiple outputs. 4109 bool isS2V = ISD::isScalarToVector(BV); 4110 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize; 4111 EVT VT = EVT::getVectorVT(*DAG.getContext(), DstEltVT, 4112 NumOutputsPerInput*BV->getNumOperands()); 4113 SmallVector<SDValue, 8> Ops; 4114 4115 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 4116 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) { 4117 for (unsigned j = 0; j != NumOutputsPerInput; ++j) 4118 Ops.push_back(DAG.getUNDEF(DstEltVT)); 4119 continue; 4120 } 4121 4122 APInt OpVal = APInt(cast<ConstantSDNode>(BV->getOperand(i))-> 4123 getAPIntValue()).zextOrTrunc(SrcBitSize); 4124 4125 for (unsigned j = 0; j != NumOutputsPerInput; ++j) { 4126 APInt ThisVal = APInt(OpVal).trunc(DstBitSize); 4127 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT)); 4128 if (isS2V && i == 0 && j == 0 && APInt(ThisVal).zext(SrcBitSize) == OpVal) 4129 // Simply turn this into a SCALAR_TO_VECTOR of the new type. 4130 return DAG.getNode(ISD::SCALAR_TO_VECTOR, BV->getDebugLoc(), VT, 4131 Ops[0]); 4132 OpVal = OpVal.lshr(DstBitSize); 4133 } 4134 4135 // For big endian targets, swap the order of the pieces of each element. 4136 if (TLI.isBigEndian()) 4137 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end()); 4138 } 4139 4140 return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT, 4141 &Ops[0], Ops.size()); 4142} 4143 4144SDValue DAGCombiner::visitFADD(SDNode *N) { 4145 SDValue N0 = N->getOperand(0); 4146 SDValue N1 = N->getOperand(1); 4147 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4148 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4149 EVT VT = N->getValueType(0); 4150 4151 // fold vector ops 4152 if (VT.isVector()) { 4153 SDValue FoldedVOp = SimplifyVBinOp(N); 4154 if (FoldedVOp.getNode()) return FoldedVOp; 4155 } 4156 4157 // fold (fadd c1, c2) -> (fadd c1, c2) 4158 if (N0CFP && N1CFP && VT != MVT::ppcf128) 4159 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N1); 4160 // canonicalize constant to RHS 4161 if (N0CFP && !N1CFP) 4162 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N1, N0); 4163 // fold (fadd A, 0) -> A 4164 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero()) 4165 return N0; 4166 // fold (fadd A, (fneg B)) -> (fsub A, B) 4167 if (isNegatibleForFree(N1, LegalOperations) == 2) 4168 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, 4169 GetNegatedExpression(N1, DAG, LegalOperations)); 4170 // fold (fadd (fneg A), B) -> (fsub B, A) 4171 if (isNegatibleForFree(N0, LegalOperations) == 2) 4172 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N1, 4173 GetNegatedExpression(N0, DAG, LegalOperations)); 4174 4175 // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2)) 4176 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FADD && 4177 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 4178 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0.getOperand(0), 4179 DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, 4180 N0.getOperand(1), N1)); 4181 4182 return SDValue(); 4183} 4184 4185SDValue DAGCombiner::visitFSUB(SDNode *N) { 4186 SDValue N0 = N->getOperand(0); 4187 SDValue N1 = N->getOperand(1); 4188 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4189 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4190 EVT VT = N->getValueType(0); 4191 4192 // fold vector ops 4193 if (VT.isVector()) { 4194 SDValue FoldedVOp = SimplifyVBinOp(N); 4195 if (FoldedVOp.getNode()) return FoldedVOp; 4196 } 4197 4198 // fold (fsub c1, c2) -> c1-c2 4199 if (N0CFP && N1CFP && VT != MVT::ppcf128) 4200 return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, N1); 4201 // fold (fsub A, 0) -> A 4202 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero()) 4203 return N0; 4204 // fold (fsub 0, B) -> -B 4205 if (UnsafeFPMath && N0CFP && N0CFP->getValueAPF().isZero()) { 4206 if (isNegatibleForFree(N1, LegalOperations)) 4207 return GetNegatedExpression(N1, DAG, LegalOperations); 4208 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 4209 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N1); 4210 } 4211 // fold (fsub A, (fneg B)) -> (fadd A, B) 4212 if (isNegatibleForFree(N1, LegalOperations)) 4213 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, 4214 GetNegatedExpression(N1, DAG, LegalOperations)); 4215 4216 return SDValue(); 4217} 4218 4219SDValue DAGCombiner::visitFMUL(SDNode *N) { 4220 SDValue N0 = N->getOperand(0); 4221 SDValue N1 = N->getOperand(1); 4222 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4223 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4224 EVT VT = N->getValueType(0); 4225 4226 // fold vector ops 4227 if (VT.isVector()) { 4228 SDValue FoldedVOp = SimplifyVBinOp(N); 4229 if (FoldedVOp.getNode()) return FoldedVOp; 4230 } 4231 4232 // fold (fmul c1, c2) -> c1*c2 4233 if (N0CFP && N1CFP && VT != MVT::ppcf128) 4234 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0, N1); 4235 // canonicalize constant to RHS 4236 if (N0CFP && !N1CFP) 4237 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N1, N0); 4238 // fold (fmul A, 0) -> 0 4239 if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero()) 4240 return N1; 4241 // fold (fmul A, 0) -> 0, vector edition. 4242 if (UnsafeFPMath && ISD::isBuildVectorAllZeros(N1.getNode())) 4243 return N1; 4244 // fold (fmul X, 2.0) -> (fadd X, X) 4245 if (N1CFP && N1CFP->isExactlyValue(+2.0)) 4246 return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N0); 4247 // fold (fmul X, -1.0) -> (fneg X) 4248 if (N1CFP && N1CFP->isExactlyValue(-1.0)) 4249 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 4250 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, N0); 4251 4252 // fold (fmul (fneg X), (fneg Y)) -> (fmul X, Y) 4253 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations)) { 4254 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations)) { 4255 // Both can be negated for free, check to see if at least one is cheaper 4256 // negated. 4257 if (LHSNeg == 2 || RHSNeg == 2) 4258 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 4259 GetNegatedExpression(N0, DAG, LegalOperations), 4260 GetNegatedExpression(N1, DAG, LegalOperations)); 4261 } 4262 } 4263 4264 // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2)) 4265 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FMUL && 4266 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 4267 return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0.getOperand(0), 4268 DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, 4269 N0.getOperand(1), N1)); 4270 4271 return SDValue(); 4272} 4273 4274SDValue DAGCombiner::visitFDIV(SDNode *N) { 4275 SDValue N0 = N->getOperand(0); 4276 SDValue N1 = N->getOperand(1); 4277 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4278 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4279 EVT VT = N->getValueType(0); 4280 4281 // fold vector ops 4282 if (VT.isVector()) { 4283 SDValue FoldedVOp = SimplifyVBinOp(N); 4284 if (FoldedVOp.getNode()) return FoldedVOp; 4285 } 4286 4287 // fold (fdiv c1, c2) -> c1/c2 4288 if (N0CFP && N1CFP && VT != MVT::ppcf128) 4289 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, N0, N1); 4290 4291 4292 // (fdiv (fneg X), (fneg Y)) -> (fdiv X, Y) 4293 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations)) { 4294 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations)) { 4295 // Both can be negated for free, check to see if at least one is cheaper 4296 // negated. 4297 if (LHSNeg == 2 || RHSNeg == 2) 4298 return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, 4299 GetNegatedExpression(N0, DAG, LegalOperations), 4300 GetNegatedExpression(N1, DAG, LegalOperations)); 4301 } 4302 } 4303 4304 return SDValue(); 4305} 4306 4307SDValue DAGCombiner::visitFREM(SDNode *N) { 4308 SDValue N0 = N->getOperand(0); 4309 SDValue N1 = N->getOperand(1); 4310 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4311 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4312 EVT VT = N->getValueType(0); 4313 4314 // fold (frem c1, c2) -> fmod(c1,c2) 4315 if (N0CFP && N1CFP && VT != MVT::ppcf128) 4316 return DAG.getNode(ISD::FREM, N->getDebugLoc(), VT, N0, N1); 4317 4318 return SDValue(); 4319} 4320 4321SDValue DAGCombiner::visitFCOPYSIGN(SDNode *N) { 4322 SDValue N0 = N->getOperand(0); 4323 SDValue N1 = N->getOperand(1); 4324 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4325 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 4326 EVT VT = N->getValueType(0); 4327 4328 if (N0CFP && N1CFP && VT != MVT::ppcf128) // Constant fold 4329 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, N0, N1); 4330 4331 if (N1CFP) { 4332 const APFloat& V = N1CFP->getValueAPF(); 4333 // copysign(x, c1) -> fabs(x) iff ispos(c1) 4334 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1) 4335 if (!V.isNegative()) { 4336 if (!LegalOperations || TLI.isOperationLegal(ISD::FABS, VT)) 4337 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 4338 } else { 4339 if (!LegalOperations || TLI.isOperationLegal(ISD::FNEG, VT)) 4340 return DAG.getNode(ISD::FNEG, N->getDebugLoc(), VT, 4341 DAG.getNode(ISD::FABS, N0.getDebugLoc(), VT, N0)); 4342 } 4343 } 4344 4345 // copysign(fabs(x), y) -> copysign(x, y) 4346 // copysign(fneg(x), y) -> copysign(x, y) 4347 // copysign(copysign(x,z), y) -> copysign(x, y) 4348 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG || 4349 N0.getOpcode() == ISD::FCOPYSIGN) 4350 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 4351 N0.getOperand(0), N1); 4352 4353 // copysign(x, abs(y)) -> abs(x) 4354 if (N1.getOpcode() == ISD::FABS) 4355 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 4356 4357 // copysign(x, copysign(y,z)) -> copysign(x, z) 4358 if (N1.getOpcode() == ISD::FCOPYSIGN) 4359 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 4360 N0, N1.getOperand(1)); 4361 4362 // copysign(x, fp_extend(y)) -> copysign(x, y) 4363 // copysign(x, fp_round(y)) -> copysign(x, y) 4364 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND) 4365 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 4366 N0, N1.getOperand(0)); 4367 4368 return SDValue(); 4369} 4370 4371SDValue DAGCombiner::visitSINT_TO_FP(SDNode *N) { 4372 SDValue N0 = N->getOperand(0); 4373 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 4374 EVT VT = N->getValueType(0); 4375 EVT OpVT = N0.getValueType(); 4376 4377 // fold (sint_to_fp c1) -> c1fp 4378 if (N0C && OpVT != MVT::ppcf128) 4379 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0); 4380 4381 // If the input is a legal type, and SINT_TO_FP is not legal on this target, 4382 // but UINT_TO_FP is legal on this target, try to convert. 4383 if (!TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT) && 4384 TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT)) { 4385 // If the sign bit is known to be zero, we can change this to UINT_TO_FP. 4386 if (DAG.SignBitIsZero(N0)) 4387 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0); 4388 } 4389 4390 return SDValue(); 4391} 4392 4393SDValue DAGCombiner::visitUINT_TO_FP(SDNode *N) { 4394 SDValue N0 = N->getOperand(0); 4395 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 4396 EVT VT = N->getValueType(0); 4397 EVT OpVT = N0.getValueType(); 4398 4399 // fold (uint_to_fp c1) -> c1fp 4400 if (N0C && OpVT != MVT::ppcf128) 4401 return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0); 4402 4403 // If the input is a legal type, and UINT_TO_FP is not legal on this target, 4404 // but SINT_TO_FP is legal on this target, try to convert. 4405 if (!TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, OpVT) && 4406 TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, OpVT)) { 4407 // If the sign bit is known to be zero, we can change this to SINT_TO_FP. 4408 if (DAG.SignBitIsZero(N0)) 4409 return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0); 4410 } 4411 4412 return SDValue(); 4413} 4414 4415SDValue DAGCombiner::visitFP_TO_SINT(SDNode *N) { 4416 SDValue N0 = N->getOperand(0); 4417 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4418 EVT VT = N->getValueType(0); 4419 4420 // fold (fp_to_sint c1fp) -> c1 4421 if (N0CFP) 4422 return DAG.getNode(ISD::FP_TO_SINT, N->getDebugLoc(), VT, N0); 4423 4424 return SDValue(); 4425} 4426 4427SDValue DAGCombiner::visitFP_TO_UINT(SDNode *N) { 4428 SDValue N0 = N->getOperand(0); 4429 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4430 EVT VT = N->getValueType(0); 4431 4432 // fold (fp_to_uint c1fp) -> c1 4433 if (N0CFP && VT != MVT::ppcf128) 4434 return DAG.getNode(ISD::FP_TO_UINT, N->getDebugLoc(), VT, N0); 4435 4436 return SDValue(); 4437} 4438 4439SDValue DAGCombiner::visitFP_ROUND(SDNode *N) { 4440 SDValue N0 = N->getOperand(0); 4441 SDValue N1 = N->getOperand(1); 4442 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4443 EVT VT = N->getValueType(0); 4444 4445 // fold (fp_round c1fp) -> c1fp 4446 if (N0CFP && N0.getValueType() != MVT::ppcf128) 4447 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0, N1); 4448 4449 // fold (fp_round (fp_extend x)) -> x 4450 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType()) 4451 return N0.getOperand(0); 4452 4453 // fold (fp_round (fp_round x)) -> (fp_round x) 4454 if (N0.getOpcode() == ISD::FP_ROUND) { 4455 // This is a value preserving truncation if both round's are. 4456 bool IsTrunc = N->getConstantOperandVal(1) == 1 && 4457 N0.getNode()->getConstantOperandVal(1) == 1; 4458 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0.getOperand(0), 4459 DAG.getIntPtrConstant(IsTrunc)); 4460 } 4461 4462 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y) 4463 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse()) { 4464 SDValue Tmp = DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(), VT, 4465 N0.getOperand(0), N1); 4466 AddToWorkList(Tmp.getNode()); 4467 return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, 4468 Tmp, N0.getOperand(1)); 4469 } 4470 4471 return SDValue(); 4472} 4473 4474SDValue DAGCombiner::visitFP_ROUND_INREG(SDNode *N) { 4475 SDValue N0 = N->getOperand(0); 4476 EVT VT = N->getValueType(0); 4477 EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 4478 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4479 4480 // fold (fp_round_inreg c1fp) -> c1fp 4481 if (N0CFP && isTypeLegal(EVT)) { 4482 SDValue Round = DAG.getConstantFP(*N0CFP->getConstantFPValue(), EVT); 4483 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, Round); 4484 } 4485 4486 return SDValue(); 4487} 4488 4489SDValue DAGCombiner::visitFP_EXTEND(SDNode *N) { 4490 SDValue N0 = N->getOperand(0); 4491 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4492 EVT VT = N->getValueType(0); 4493 4494 // If this is fp_round(fpextend), don't fold it, allow ourselves to be folded. 4495 if (N->hasOneUse() && 4496 N->use_begin()->getOpcode() == ISD::FP_ROUND) 4497 return SDValue(); 4498 4499 // fold (fp_extend c1fp) -> c1fp 4500 if (N0CFP && VT != MVT::ppcf128) 4501 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, N0); 4502 4503 // Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't affect the 4504 // value of X. 4505 if (N0.getOpcode() == ISD::FP_ROUND 4506 && N0.getNode()->getConstantOperandVal(1) == 1) { 4507 SDValue In = N0.getOperand(0); 4508 if (In.getValueType() == VT) return In; 4509 if (VT.bitsLT(In.getValueType())) 4510 return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, 4511 In, N0.getOperand(1)); 4512 return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, In); 4513 } 4514 4515 // fold (fpext (load x)) -> (fpext (fptrunc (extload x))) 4516 if (ISD::isNON_EXTLoad(N0.getNode()) && N0.hasOneUse() && 4517 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 4518 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) { 4519 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4520 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, N->getDebugLoc(), VT, 4521 LN0->getChain(), 4522 LN0->getBasePtr(), LN0->getSrcValue(), 4523 LN0->getSrcValueOffset(), 4524 N0.getValueType(), 4525 LN0->isVolatile(), LN0->isNonTemporal(), 4526 LN0->getAlignment()); 4527 CombineTo(N, ExtLoad); 4528 CombineTo(N0.getNode(), 4529 DAG.getNode(ISD::FP_ROUND, N0.getDebugLoc(), 4530 N0.getValueType(), ExtLoad, DAG.getIntPtrConstant(1)), 4531 ExtLoad.getValue(1)); 4532 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4533 } 4534 4535 return SDValue(); 4536} 4537 4538SDValue DAGCombiner::visitFNEG(SDNode *N) { 4539 SDValue N0 = N->getOperand(0); 4540 EVT VT = N->getValueType(0); 4541 4542 if (isNegatibleForFree(N0, LegalOperations)) 4543 return GetNegatedExpression(N0, DAG, LegalOperations); 4544 4545 // Transform fneg(bitconvert(x)) -> bitconvert(x^sign) to avoid loading 4546 // constant pool values. 4547 if (N0.getOpcode() == ISD::BIT_CONVERT && 4548 !VT.isVector() && 4549 N0.getNode()->hasOneUse() && 4550 N0.getOperand(0).getValueType().isInteger()) { 4551 SDValue Int = N0.getOperand(0); 4552 EVT IntVT = Int.getValueType(); 4553 if (IntVT.isInteger() && !IntVT.isVector()) { 4554 Int = DAG.getNode(ISD::XOR, N0.getDebugLoc(), IntVT, Int, 4555 DAG.getConstant(APInt::getSignBit(IntVT.getSizeInBits()), IntVT)); 4556 AddToWorkList(Int.getNode()); 4557 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), 4558 VT, Int); 4559 } 4560 } 4561 4562 return SDValue(); 4563} 4564 4565SDValue DAGCombiner::visitFABS(SDNode *N) { 4566 SDValue N0 = N->getOperand(0); 4567 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4568 EVT VT = N->getValueType(0); 4569 4570 // fold (fabs c1) -> fabs(c1) 4571 if (N0CFP && VT != MVT::ppcf128) 4572 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0); 4573 // fold (fabs (fabs x)) -> (fabs x) 4574 if (N0.getOpcode() == ISD::FABS) 4575 return N->getOperand(0); 4576 // fold (fabs (fneg x)) -> (fabs x) 4577 // fold (fabs (fcopysign x, y)) -> (fabs x) 4578 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN) 4579 return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0.getOperand(0)); 4580 4581 // Transform fabs(bitconvert(x)) -> bitconvert(x&~sign) to avoid loading 4582 // constant pool values. 4583 if (N0.getOpcode() == ISD::BIT_CONVERT && N0.getNode()->hasOneUse() && 4584 N0.getOperand(0).getValueType().isInteger() && 4585 !N0.getOperand(0).getValueType().isVector()) { 4586 SDValue Int = N0.getOperand(0); 4587 EVT IntVT = Int.getValueType(); 4588 if (IntVT.isInteger() && !IntVT.isVector()) { 4589 Int = DAG.getNode(ISD::AND, N0.getDebugLoc(), IntVT, Int, 4590 DAG.getConstant(~APInt::getSignBit(IntVT.getSizeInBits()), IntVT)); 4591 AddToWorkList(Int.getNode()); 4592 return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(), 4593 N->getValueType(0), Int); 4594 } 4595 } 4596 4597 return SDValue(); 4598} 4599 4600SDValue DAGCombiner::visitBRCOND(SDNode *N) { 4601 SDValue Chain = N->getOperand(0); 4602 SDValue N1 = N->getOperand(1); 4603 SDValue N2 = N->getOperand(2); 4604 4605 // If N is a constant we could fold this into a fallthrough or unconditional 4606 // branch. However that doesn't happen very often in normal code, because 4607 // Instcombine/SimplifyCFG should have handled the available opportunities. 4608 // If we did this folding here, it would be necessary to update the 4609 // MachineBasicBlock CFG, which is awkward. 4610 4611 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal 4612 // on the target. 4613 if (N1.getOpcode() == ISD::SETCC && 4614 TLI.isOperationLegalOrCustom(ISD::BR_CC, MVT::Other)) { 4615 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other, 4616 Chain, N1.getOperand(2), 4617 N1.getOperand(0), N1.getOperand(1), N2); 4618 } 4619 4620 SDNode *Trunc = 0; 4621 if (N1.getOpcode() == ISD::TRUNCATE && N1.hasOneUse()) { 4622 // Look past truncate. 4623 Trunc = N1.getNode(); 4624 N1 = N1.getOperand(0); 4625 } 4626 4627 if (N1.hasOneUse() && N1.getOpcode() == ISD::SRL) { 4628 // Match this pattern so that we can generate simpler code: 4629 // 4630 // %a = ... 4631 // %b = and i32 %a, 2 4632 // %c = srl i32 %b, 1 4633 // brcond i32 %c ... 4634 // 4635 // into 4636 // 4637 // %a = ... 4638 // %b = and i32 %a, 2 4639 // %c = setcc eq %b, 0 4640 // brcond %c ... 4641 // 4642 // This applies only when the AND constant value has one bit set and the 4643 // SRL constant is equal to the log2 of the AND constant. The back-end is 4644 // smart enough to convert the result into a TEST/JMP sequence. 4645 SDValue Op0 = N1.getOperand(0); 4646 SDValue Op1 = N1.getOperand(1); 4647 4648 if (Op0.getOpcode() == ISD::AND && 4649 Op1.getOpcode() == ISD::Constant) { 4650 SDValue AndOp1 = Op0.getOperand(1); 4651 4652 if (AndOp1.getOpcode() == ISD::Constant) { 4653 const APInt &AndConst = cast<ConstantSDNode>(AndOp1)->getAPIntValue(); 4654 4655 if (AndConst.isPowerOf2() && 4656 cast<ConstantSDNode>(Op1)->getAPIntValue()==AndConst.logBase2()) { 4657 SDValue SetCC = 4658 DAG.getSetCC(N->getDebugLoc(), 4659 TLI.getSetCCResultType(Op0.getValueType()), 4660 Op0, DAG.getConstant(0, Op0.getValueType()), 4661 ISD::SETNE); 4662 4663 SDValue NewBRCond = DAG.getNode(ISD::BRCOND, N->getDebugLoc(), 4664 MVT::Other, Chain, SetCC, N2); 4665 // Don't add the new BRCond into the worklist or else SimplifySelectCC 4666 // will convert it back to (X & C1) >> C2. 4667 CombineTo(N, NewBRCond, false); 4668 // Truncate is dead. 4669 if (Trunc) { 4670 removeFromWorkList(Trunc); 4671 DAG.DeleteNode(Trunc); 4672 } 4673 // Replace the uses of SRL with SETCC 4674 WorkListRemover DeadNodes(*this); 4675 DAG.ReplaceAllUsesOfValueWith(N1, SetCC, &DeadNodes); 4676 removeFromWorkList(N1.getNode()); 4677 DAG.DeleteNode(N1.getNode()); 4678 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4679 } 4680 } 4681 } 4682 } 4683 4684 // Transform br(xor(x, y)) -> br(x != y) 4685 // Transform br(xor(xor(x,y), 1)) -> br (x == y) 4686 if (N1.hasOneUse() && N1.getOpcode() == ISD::XOR) { 4687 SDNode *TheXor = N1.getNode(); 4688 SDValue Op0 = TheXor->getOperand(0); 4689 SDValue Op1 = TheXor->getOperand(1); 4690 if (Op0.getOpcode() == Op1.getOpcode()) { 4691 // Avoid missing important xor optimizations. 4692 SDValue Tmp = visitXOR(TheXor); 4693 if (Tmp.getNode()) { 4694 DEBUG(dbgs() << "\nReplacing.8 "; 4695 TheXor->dump(&DAG); 4696 dbgs() << "\nWith: "; 4697 Tmp.getNode()->dump(&DAG); 4698 dbgs() << '\n'); 4699 WorkListRemover DeadNodes(*this); 4700 DAG.ReplaceAllUsesOfValueWith(N1, Tmp, &DeadNodes); 4701 removeFromWorkList(TheXor); 4702 DAG.DeleteNode(TheXor); 4703 return DAG.getNode(ISD::BRCOND, N->getDebugLoc(), 4704 MVT::Other, Chain, Tmp, N2); 4705 } 4706 } 4707 4708 if (Op0.getOpcode() != ISD::SETCC && Op1.getOpcode() != ISD::SETCC) { 4709 bool Equal = false; 4710 if (ConstantSDNode *RHSCI = dyn_cast<ConstantSDNode>(Op0)) 4711 if (RHSCI->getAPIntValue() == 1 && Op0.hasOneUse() && 4712 Op0.getOpcode() == ISD::XOR) { 4713 TheXor = Op0.getNode(); 4714 Equal = true; 4715 } 4716 4717 SDValue NodeToReplace = Trunc ? SDValue(Trunc, 0) : N1; 4718 4719 EVT SetCCVT = NodeToReplace.getValueType(); 4720 if (LegalTypes) 4721 SetCCVT = TLI.getSetCCResultType(SetCCVT); 4722 SDValue SetCC = DAG.getSetCC(TheXor->getDebugLoc(), 4723 SetCCVT, 4724 Op0, Op1, 4725 Equal ? ISD::SETEQ : ISD::SETNE); 4726 // Replace the uses of XOR with SETCC 4727 WorkListRemover DeadNodes(*this); 4728 DAG.ReplaceAllUsesOfValueWith(NodeToReplace, SetCC, &DeadNodes); 4729 removeFromWorkList(NodeToReplace.getNode()); 4730 DAG.DeleteNode(NodeToReplace.getNode()); 4731 return DAG.getNode(ISD::BRCOND, N->getDebugLoc(), 4732 MVT::Other, Chain, SetCC, N2); 4733 } 4734 } 4735 4736 return SDValue(); 4737} 4738 4739// Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB. 4740// 4741SDValue DAGCombiner::visitBR_CC(SDNode *N) { 4742 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1)); 4743 SDValue CondLHS = N->getOperand(2), CondRHS = N->getOperand(3); 4744 4745 // If N is a constant we could fold this into a fallthrough or unconditional 4746 // branch. However that doesn't happen very often in normal code, because 4747 // Instcombine/SimplifyCFG should have handled the available opportunities. 4748 // If we did this folding here, it would be necessary to update the 4749 // MachineBasicBlock CFG, which is awkward. 4750 4751 // Use SimplifySetCC to simplify SETCC's. 4752 SDValue Simp = SimplifySetCC(TLI.getSetCCResultType(CondLHS.getValueType()), 4753 CondLHS, CondRHS, CC->get(), N->getDebugLoc(), 4754 false); 4755 if (Simp.getNode()) AddToWorkList(Simp.getNode()); 4756 4757 // fold to a simpler setcc 4758 if (Simp.getNode() && Simp.getOpcode() == ISD::SETCC) 4759 return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other, 4760 N->getOperand(0), Simp.getOperand(2), 4761 Simp.getOperand(0), Simp.getOperand(1), 4762 N->getOperand(4)); 4763 4764 return SDValue(); 4765} 4766 4767/// CombineToPreIndexedLoadStore - Try turning a load / store into a 4768/// pre-indexed load / store when the base pointer is an add or subtract 4769/// and it has other uses besides the load / store. After the 4770/// transformation, the new indexed load / store has effectively folded 4771/// the add / subtract in and all of its other uses are redirected to the 4772/// new load / store. 4773bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) { 4774 if (!LegalOperations) 4775 return false; 4776 4777 bool isLoad = true; 4778 SDValue Ptr; 4779 EVT VT; 4780 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 4781 if (LD->isIndexed()) 4782 return false; 4783 VT = LD->getMemoryVT(); 4784 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) && 4785 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT)) 4786 return false; 4787 Ptr = LD->getBasePtr(); 4788 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 4789 if (ST->isIndexed()) 4790 return false; 4791 VT = ST->getMemoryVT(); 4792 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) && 4793 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT)) 4794 return false; 4795 Ptr = ST->getBasePtr(); 4796 isLoad = false; 4797 } else { 4798 return false; 4799 } 4800 4801 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail 4802 // out. There is no reason to make this a preinc/predec. 4803 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) || 4804 Ptr.getNode()->hasOneUse()) 4805 return false; 4806 4807 // Ask the target to do addressing mode selection. 4808 SDValue BasePtr; 4809 SDValue Offset; 4810 ISD::MemIndexedMode AM = ISD::UNINDEXED; 4811 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG)) 4812 return false; 4813 // Don't create a indexed load / store with zero offset. 4814 if (isa<ConstantSDNode>(Offset) && 4815 cast<ConstantSDNode>(Offset)->isNullValue()) 4816 return false; 4817 4818 // Try turning it into a pre-indexed load / store except when: 4819 // 1) The new base ptr is a frame index. 4820 // 2) If N is a store and the new base ptr is either the same as or is a 4821 // predecessor of the value being stored. 4822 // 3) Another use of old base ptr is a predecessor of N. If ptr is folded 4823 // that would create a cycle. 4824 // 4) All uses are load / store ops that use it as old base ptr. 4825 4826 // Check #1. Preinc'ing a frame index would require copying the stack pointer 4827 // (plus the implicit offset) to a register to preinc anyway. 4828 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr)) 4829 return false; 4830 4831 // Check #2. 4832 if (!isLoad) { 4833 SDValue Val = cast<StoreSDNode>(N)->getValue(); 4834 if (Val == BasePtr || BasePtr.getNode()->isPredecessorOf(Val.getNode())) 4835 return false; 4836 } 4837 4838 // Now check for #3 and #4. 4839 bool RealUse = false; 4840 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(), 4841 E = Ptr.getNode()->use_end(); I != E; ++I) { 4842 SDNode *Use = *I; 4843 if (Use == N) 4844 continue; 4845 if (Use->isPredecessorOf(N)) 4846 return false; 4847 4848 if (!((Use->getOpcode() == ISD::LOAD && 4849 cast<LoadSDNode>(Use)->getBasePtr() == Ptr) || 4850 (Use->getOpcode() == ISD::STORE && 4851 cast<StoreSDNode>(Use)->getBasePtr() == Ptr))) 4852 RealUse = true; 4853 } 4854 4855 if (!RealUse) 4856 return false; 4857 4858 SDValue Result; 4859 if (isLoad) 4860 Result = DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(), 4861 BasePtr, Offset, AM); 4862 else 4863 Result = DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(), 4864 BasePtr, Offset, AM); 4865 ++PreIndexedNodes; 4866 ++NodesCombined; 4867 DEBUG(dbgs() << "\nReplacing.4 "; 4868 N->dump(&DAG); 4869 dbgs() << "\nWith: "; 4870 Result.getNode()->dump(&DAG); 4871 dbgs() << '\n'); 4872 WorkListRemover DeadNodes(*this); 4873 if (isLoad) { 4874 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0), 4875 &DeadNodes); 4876 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2), 4877 &DeadNodes); 4878 } else { 4879 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1), 4880 &DeadNodes); 4881 } 4882 4883 // Finally, since the node is now dead, remove it from the graph. 4884 DAG.DeleteNode(N); 4885 4886 // Replace the uses of Ptr with uses of the updated base value. 4887 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0), 4888 &DeadNodes); 4889 removeFromWorkList(Ptr.getNode()); 4890 DAG.DeleteNode(Ptr.getNode()); 4891 4892 return true; 4893} 4894 4895/// CombineToPostIndexedLoadStore - Try to combine a load / store with a 4896/// add / sub of the base pointer node into a post-indexed load / store. 4897/// The transformation folded the add / subtract into the new indexed 4898/// load / store effectively and all of its uses are redirected to the 4899/// new load / store. 4900bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) { 4901 if (!LegalOperations) 4902 return false; 4903 4904 bool isLoad = true; 4905 SDValue Ptr; 4906 EVT VT; 4907 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 4908 if (LD->isIndexed()) 4909 return false; 4910 VT = LD->getMemoryVT(); 4911 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) && 4912 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT)) 4913 return false; 4914 Ptr = LD->getBasePtr(); 4915 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 4916 if (ST->isIndexed()) 4917 return false; 4918 VT = ST->getMemoryVT(); 4919 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) && 4920 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT)) 4921 return false; 4922 Ptr = ST->getBasePtr(); 4923 isLoad = false; 4924 } else { 4925 return false; 4926 } 4927 4928 if (Ptr.getNode()->hasOneUse()) 4929 return false; 4930 4931 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(), 4932 E = Ptr.getNode()->use_end(); I != E; ++I) { 4933 SDNode *Op = *I; 4934 if (Op == N || 4935 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB)) 4936 continue; 4937 4938 SDValue BasePtr; 4939 SDValue Offset; 4940 ISD::MemIndexedMode AM = ISD::UNINDEXED; 4941 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) { 4942 if (Ptr == Offset && Op->getOpcode() == ISD::ADD) 4943 std::swap(BasePtr, Offset); 4944 if (Ptr != BasePtr) 4945 continue; 4946 // Don't create a indexed load / store with zero offset. 4947 if (isa<ConstantSDNode>(Offset) && 4948 cast<ConstantSDNode>(Offset)->isNullValue()) 4949 continue; 4950 4951 // Try turning it into a post-indexed load / store except when 4952 // 1) All uses are load / store ops that use it as base ptr. 4953 // 2) Op must be independent of N, i.e. Op is neither a predecessor 4954 // nor a successor of N. Otherwise, if Op is folded that would 4955 // create a cycle. 4956 4957 if (isa<FrameIndexSDNode>(BasePtr) || isa<RegisterSDNode>(BasePtr)) 4958 continue; 4959 4960 // Check for #1. 4961 bool TryNext = false; 4962 for (SDNode::use_iterator II = BasePtr.getNode()->use_begin(), 4963 EE = BasePtr.getNode()->use_end(); II != EE; ++II) { 4964 SDNode *Use = *II; 4965 if (Use == Ptr.getNode()) 4966 continue; 4967 4968 // If all the uses are load / store addresses, then don't do the 4969 // transformation. 4970 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){ 4971 bool RealUse = false; 4972 for (SDNode::use_iterator III = Use->use_begin(), 4973 EEE = Use->use_end(); III != EEE; ++III) { 4974 SDNode *UseUse = *III; 4975 if (!((UseUse->getOpcode() == ISD::LOAD && 4976 cast<LoadSDNode>(UseUse)->getBasePtr().getNode() == Use) || 4977 (UseUse->getOpcode() == ISD::STORE && 4978 cast<StoreSDNode>(UseUse)->getBasePtr().getNode() == Use))) 4979 RealUse = true; 4980 } 4981 4982 if (!RealUse) { 4983 TryNext = true; 4984 break; 4985 } 4986 } 4987 } 4988 4989 if (TryNext) 4990 continue; 4991 4992 // Check for #2 4993 if (!Op->isPredecessorOf(N) && !N->isPredecessorOf(Op)) { 4994 SDValue Result = isLoad 4995 ? DAG.getIndexedLoad(SDValue(N,0), N->getDebugLoc(), 4996 BasePtr, Offset, AM) 4997 : DAG.getIndexedStore(SDValue(N,0), N->getDebugLoc(), 4998 BasePtr, Offset, AM); 4999 ++PostIndexedNodes; 5000 ++NodesCombined; 5001 DEBUG(dbgs() << "\nReplacing.5 "; 5002 N->dump(&DAG); 5003 dbgs() << "\nWith: "; 5004 Result.getNode()->dump(&DAG); 5005 dbgs() << '\n'); 5006 WorkListRemover DeadNodes(*this); 5007 if (isLoad) { 5008 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0), 5009 &DeadNodes); 5010 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2), 5011 &DeadNodes); 5012 } else { 5013 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1), 5014 &DeadNodes); 5015 } 5016 5017 // Finally, since the node is now dead, remove it from the graph. 5018 DAG.DeleteNode(N); 5019 5020 // Replace the uses of Use with uses of the updated base value. 5021 DAG.ReplaceAllUsesOfValueWith(SDValue(Op, 0), 5022 Result.getValue(isLoad ? 1 : 0), 5023 &DeadNodes); 5024 removeFromWorkList(Op); 5025 DAG.DeleteNode(Op); 5026 return true; 5027 } 5028 } 5029 } 5030 5031 return false; 5032} 5033 5034SDValue DAGCombiner::visitLOAD(SDNode *N) { 5035 LoadSDNode *LD = cast<LoadSDNode>(N); 5036 SDValue Chain = LD->getChain(); 5037 SDValue Ptr = LD->getBasePtr(); 5038 5039 // If load is not volatile and there are no uses of the loaded value (and 5040 // the updated indexed value in case of indexed loads), change uses of the 5041 // chain value into uses of the chain input (i.e. delete the dead load). 5042 if (!LD->isVolatile()) { 5043 if (N->getValueType(1) == MVT::Other) { 5044 // Unindexed loads. 5045 if (N->hasNUsesOfValue(0, 0)) { 5046 // It's not safe to use the two value CombineTo variant here. e.g. 5047 // v1, chain2 = load chain1, loc 5048 // v2, chain3 = load chain2, loc 5049 // v3 = add v2, c 5050 // Now we replace use of chain2 with chain1. This makes the second load 5051 // isomorphic to the one we are deleting, and thus makes this load live. 5052 DEBUG(dbgs() << "\nReplacing.6 "; 5053 N->dump(&DAG); 5054 dbgs() << "\nWith chain: "; 5055 Chain.getNode()->dump(&DAG); 5056 dbgs() << "\n"); 5057 WorkListRemover DeadNodes(*this); 5058 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Chain, &DeadNodes); 5059 5060 if (N->use_empty()) { 5061 removeFromWorkList(N); 5062 DAG.DeleteNode(N); 5063 } 5064 5065 return SDValue(N, 0); // Return N so it doesn't get rechecked! 5066 } 5067 } else { 5068 // Indexed loads. 5069 assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?"); 5070 if (N->hasNUsesOfValue(0, 0) && N->hasNUsesOfValue(0, 1)) { 5071 SDValue Undef = DAG.getUNDEF(N->getValueType(0)); 5072 DEBUG(dbgs() << "\nReplacing.7 "; 5073 N->dump(&DAG); 5074 dbgs() << "\nWith: "; 5075 Undef.getNode()->dump(&DAG); 5076 dbgs() << " and 2 other values\n"); 5077 WorkListRemover DeadNodes(*this); 5078 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Undef, &DeadNodes); 5079 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), 5080 DAG.getUNDEF(N->getValueType(1)), 5081 &DeadNodes); 5082 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 2), Chain, &DeadNodes); 5083 removeFromWorkList(N); 5084 DAG.DeleteNode(N); 5085 return SDValue(N, 0); // Return N so it doesn't get rechecked! 5086 } 5087 } 5088 } 5089 5090 // If this load is directly stored, replace the load value with the stored 5091 // value. 5092 // TODO: Handle store large -> read small portion. 5093 // TODO: Handle TRUNCSTORE/LOADEXT 5094 if (LD->getExtensionType() == ISD::NON_EXTLOAD && 5095 !LD->isVolatile()) { 5096 if (ISD::isNON_TRUNCStore(Chain.getNode())) { 5097 StoreSDNode *PrevST = cast<StoreSDNode>(Chain); 5098 if (PrevST->getBasePtr() == Ptr && 5099 PrevST->getValue().getValueType() == N->getValueType(0)) 5100 return CombineTo(N, Chain.getOperand(1), Chain); 5101 } 5102 } 5103 5104 // Try to infer better alignment information than the load already has. 5105 if (OptLevel != CodeGenOpt::None && LD->isUnindexed()) { 5106 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) { 5107 if (Align > LD->getAlignment()) 5108 return DAG.getExtLoad(LD->getExtensionType(), N->getDebugLoc(), 5109 LD->getValueType(0), 5110 Chain, Ptr, LD->getSrcValue(), 5111 LD->getSrcValueOffset(), LD->getMemoryVT(), 5112 LD->isVolatile(), LD->isNonTemporal(), Align); 5113 } 5114 } 5115 5116 if (CombinerAA) { 5117 // Walk up chain skipping non-aliasing memory nodes. 5118 SDValue BetterChain = FindBetterChain(N, Chain); 5119 5120 // If there is a better chain. 5121 if (Chain != BetterChain) { 5122 SDValue ReplLoad; 5123 5124 // Replace the chain to void dependency. 5125 if (LD->getExtensionType() == ISD::NON_EXTLOAD) { 5126 ReplLoad = DAG.getLoad(N->getValueType(0), LD->getDebugLoc(), 5127 BetterChain, Ptr, 5128 LD->getSrcValue(), LD->getSrcValueOffset(), 5129 LD->isVolatile(), LD->isNonTemporal(), 5130 LD->getAlignment()); 5131 } else { 5132 ReplLoad = DAG.getExtLoad(LD->getExtensionType(), LD->getDebugLoc(), 5133 LD->getValueType(0), 5134 BetterChain, Ptr, LD->getSrcValue(), 5135 LD->getSrcValueOffset(), 5136 LD->getMemoryVT(), 5137 LD->isVolatile(), 5138 LD->isNonTemporal(), 5139 LD->getAlignment()); 5140 } 5141 5142 // Create token factor to keep old chain connected. 5143 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 5144 MVT::Other, Chain, ReplLoad.getValue(1)); 5145 5146 // Make sure the new and old chains are cleaned up. 5147 AddToWorkList(Token.getNode()); 5148 5149 // Replace uses with load result and token factor. Don't add users 5150 // to work list. 5151 return CombineTo(N, ReplLoad.getValue(0), Token, false); 5152 } 5153 } 5154 5155 // Try transforming N to an indexed load. 5156 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 5157 return SDValue(N, 0); 5158 5159 return SDValue(); 5160} 5161 5162/// CheckForMaskedLoad - Check to see if V is (and load (ptr), imm), where the 5163/// load is having specific bytes cleared out. If so, return the byte size 5164/// being masked out and the shift amount. 5165static std::pair<unsigned, unsigned> 5166CheckForMaskedLoad(SDValue V, SDValue Ptr, SDValue Chain) { 5167 std::pair<unsigned, unsigned> Result(0, 0); 5168 5169 // Check for the structure we're looking for. 5170 if (V->getOpcode() != ISD::AND || 5171 !isa<ConstantSDNode>(V->getOperand(1)) || 5172 !ISD::isNormalLoad(V->getOperand(0).getNode())) 5173 return Result; 5174 5175 // Check the chain and pointer. The store should be chained directly to the 5176 // load (TODO: Or through a TF node!) since it's to the same address. 5177 LoadSDNode *LD = cast<LoadSDNode>(V->getOperand(0)); 5178 if (LD->getBasePtr() != Ptr || 5179 V->getOperand(0).getNode() != Chain.getNode()) 5180 return Result; 5181 5182 // This only handles simple types. 5183 if (V.getValueType() != MVT::i16 && 5184 V.getValueType() != MVT::i32 && 5185 V.getValueType() != MVT::i64) 5186 return Result; 5187 5188 // Check the constant mask. Invert it so that the bits being masked out are 5189 // 0 and the bits being kept are 1. Use getSExtValue so that leading bits 5190 // follow the sign bit for uniformity. 5191 uint64_t NotMask = ~cast<ConstantSDNode>(V->getOperand(1))->getSExtValue(); 5192 unsigned NotMaskLZ = CountLeadingZeros_64(NotMask); 5193 if (NotMaskLZ & 7) return Result; // Must be multiple of a byte. 5194 unsigned NotMaskTZ = CountTrailingZeros_64(NotMask); 5195 if (NotMaskTZ & 7) return Result; // Must be multiple of a byte. 5196 if (NotMaskLZ == 64) return Result; // All zero mask. 5197 5198 // See if we have a continuous run of bits. If so, we have 0*1+0* 5199 if (CountTrailingOnes_64(NotMask >> NotMaskTZ)+NotMaskTZ+NotMaskLZ != 64) 5200 return Result; 5201 5202 // Adjust NotMaskLZ down to be from the actual size of the int instead of i64. 5203 if (V.getValueType() != MVT::i64 && NotMaskLZ) 5204 NotMaskLZ -= 64-V.getValueSizeInBits(); 5205 5206 unsigned MaskedBytes = (V.getValueSizeInBits()-NotMaskLZ-NotMaskTZ)/8; 5207 switch (MaskedBytes) { 5208 case 1: 5209 case 2: 5210 case 4: break; 5211 default: return Result; // All one mask, or 5-byte mask. 5212 } 5213 5214 // Verify that the first bit starts at a multiple of mask so that the access 5215 // is aligned the same as the access width. 5216 if (NotMaskTZ && NotMaskTZ/8 % MaskedBytes) return Result; 5217 5218 Result.first = MaskedBytes; 5219 Result.second = NotMaskTZ/8; 5220 return Result; 5221} 5222 5223 5224/// ShrinkLoadReplaceStoreWithStore - Check to see if IVal is something that 5225/// provides a value as specified by MaskInfo. If so, replace the specified 5226/// store with a narrower store of truncated IVal. 5227static SDNode * 5228ShrinkLoadReplaceStoreWithStore(const std::pair<unsigned, unsigned> &MaskInfo, 5229 SDValue IVal, StoreSDNode *St, 5230 DAGCombiner *DC) { 5231 unsigned NumBytes = MaskInfo.first; 5232 unsigned ByteShift = MaskInfo.second; 5233 SelectionDAG &DAG = DC->getDAG(); 5234 5235 // Check to see if IVal is all zeros in the part being masked in by the 'or' 5236 // that uses this. If not, this is not a replacement. 5237 APInt Mask = ~APInt::getBitsSet(IVal.getValueSizeInBits(), 5238 ByteShift*8, (ByteShift+NumBytes)*8); 5239 if (!DAG.MaskedValueIsZero(IVal, Mask)) return 0; 5240 5241 // Check that it is legal on the target to do this. It is legal if the new 5242 // VT we're shrinking to (i8/i16/i32) is legal or we're still before type 5243 // legalization. 5244 MVT VT = MVT::getIntegerVT(NumBytes*8); 5245 if (!DC->isTypeLegal(VT)) 5246 return 0; 5247 5248 // Okay, we can do this! Replace the 'St' store with a store of IVal that is 5249 // shifted by ByteShift and truncated down to NumBytes. 5250 if (ByteShift) 5251 IVal = DAG.getNode(ISD::SRL, IVal->getDebugLoc(), IVal.getValueType(), IVal, 5252 DAG.getConstant(ByteShift*8, DC->getShiftAmountTy())); 5253 5254 // Figure out the offset for the store and the alignment of the access. 5255 unsigned StOffset; 5256 unsigned NewAlign = St->getAlignment(); 5257 5258 if (DAG.getTargetLoweringInfo().isLittleEndian()) 5259 StOffset = ByteShift; 5260 else 5261 StOffset = IVal.getValueType().getStoreSize() - ByteShift - NumBytes; 5262 5263 SDValue Ptr = St->getBasePtr(); 5264 if (StOffset) { 5265 Ptr = DAG.getNode(ISD::ADD, IVal->getDebugLoc(), Ptr.getValueType(), 5266 Ptr, DAG.getConstant(StOffset, Ptr.getValueType())); 5267 NewAlign = MinAlign(NewAlign, StOffset); 5268 } 5269 5270 // Truncate down to the new size. 5271 IVal = DAG.getNode(ISD::TRUNCATE, IVal->getDebugLoc(), VT, IVal); 5272 5273 ++OpsNarrowed; 5274 return DAG.getStore(St->getChain(), St->getDebugLoc(), IVal, Ptr, 5275 St->getSrcValue(), St->getSrcValueOffset()+StOffset, 5276 false, false, NewAlign).getNode(); 5277} 5278 5279 5280/// ReduceLoadOpStoreWidth - Look for sequence of load / op / store where op is 5281/// one of 'or', 'xor', and 'and' of immediates. If 'op' is only touching some 5282/// of the loaded bits, try narrowing the load and store if it would end up 5283/// being a win for performance or code size. 5284SDValue DAGCombiner::ReduceLoadOpStoreWidth(SDNode *N) { 5285 StoreSDNode *ST = cast<StoreSDNode>(N); 5286 if (ST->isVolatile()) 5287 return SDValue(); 5288 5289 SDValue Chain = ST->getChain(); 5290 SDValue Value = ST->getValue(); 5291 SDValue Ptr = ST->getBasePtr(); 5292 EVT VT = Value.getValueType(); 5293 5294 if (ST->isTruncatingStore() || VT.isVector() || !Value.hasOneUse()) 5295 return SDValue(); 5296 5297 unsigned Opc = Value.getOpcode(); 5298 5299 // If this is "store (or X, Y), P" and X is "(and (load P), cst)", where cst 5300 // is a byte mask indicating a consecutive number of bytes, check to see if 5301 // Y is known to provide just those bytes. If so, we try to replace the 5302 // load + replace + store sequence with a single (narrower) store, which makes 5303 // the load dead. 5304 if (Opc == ISD::OR) { 5305 std::pair<unsigned, unsigned> MaskedLoad; 5306 MaskedLoad = CheckForMaskedLoad(Value.getOperand(0), Ptr, Chain); 5307 if (MaskedLoad.first) 5308 if (SDNode *NewST = ShrinkLoadReplaceStoreWithStore(MaskedLoad, 5309 Value.getOperand(1), ST,this)) 5310 return SDValue(NewST, 0); 5311 5312 // Or is commutative, so try swapping X and Y. 5313 MaskedLoad = CheckForMaskedLoad(Value.getOperand(1), Ptr, Chain); 5314 if (MaskedLoad.first) 5315 if (SDNode *NewST = ShrinkLoadReplaceStoreWithStore(MaskedLoad, 5316 Value.getOperand(0), ST,this)) 5317 return SDValue(NewST, 0); 5318 } 5319 5320 if ((Opc != ISD::OR && Opc != ISD::XOR && Opc != ISD::AND) || 5321 Value.getOperand(1).getOpcode() != ISD::Constant) 5322 return SDValue(); 5323 5324 SDValue N0 = Value.getOperand(0); 5325 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse()) { 5326 LoadSDNode *LD = cast<LoadSDNode>(N0); 5327 if (LD->getBasePtr() != Ptr) 5328 return SDValue(); 5329 5330 // Find the type to narrow it the load / op / store to. 5331 SDValue N1 = Value.getOperand(1); 5332 unsigned BitWidth = N1.getValueSizeInBits(); 5333 APInt Imm = cast<ConstantSDNode>(N1)->getAPIntValue(); 5334 if (Opc == ISD::AND) 5335 Imm ^= APInt::getAllOnesValue(BitWidth); 5336 if (Imm == 0 || Imm.isAllOnesValue()) 5337 return SDValue(); 5338 unsigned ShAmt = Imm.countTrailingZeros(); 5339 unsigned MSB = BitWidth - Imm.countLeadingZeros() - 1; 5340 unsigned NewBW = NextPowerOf2(MSB - ShAmt); 5341 EVT NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW); 5342 while (NewBW < BitWidth && 5343 !(TLI.isOperationLegalOrCustom(Opc, NewVT) && 5344 TLI.isNarrowingProfitable(VT, NewVT))) { 5345 NewBW = NextPowerOf2(NewBW); 5346 NewVT = EVT::getIntegerVT(*DAG.getContext(), NewBW); 5347 } 5348 if (NewBW >= BitWidth) 5349 return SDValue(); 5350 5351 // If the lsb changed does not start at the type bitwidth boundary, 5352 // start at the previous one. 5353 if (ShAmt % NewBW) 5354 ShAmt = (((ShAmt + NewBW - 1) / NewBW) * NewBW) - NewBW; 5355 APInt Mask = APInt::getBitsSet(BitWidth, ShAmt, ShAmt + NewBW); 5356 if ((Imm & Mask) == Imm) { 5357 APInt NewImm = (Imm & Mask).lshr(ShAmt).trunc(NewBW); 5358 if (Opc == ISD::AND) 5359 NewImm ^= APInt::getAllOnesValue(NewBW); 5360 uint64_t PtrOff = ShAmt / 8; 5361 // For big endian targets, we need to adjust the offset to the pointer to 5362 // load the correct bytes. 5363 if (TLI.isBigEndian()) 5364 PtrOff = (BitWidth + 7 - NewBW) / 8 - PtrOff; 5365 5366 unsigned NewAlign = MinAlign(LD->getAlignment(), PtrOff); 5367 const Type *NewVTTy = NewVT.getTypeForEVT(*DAG.getContext()); 5368 if (NewAlign < TLI.getTargetData()->getABITypeAlignment(NewVTTy)) 5369 return SDValue(); 5370 5371 SDValue NewPtr = DAG.getNode(ISD::ADD, LD->getDebugLoc(), 5372 Ptr.getValueType(), Ptr, 5373 DAG.getConstant(PtrOff, Ptr.getValueType())); 5374 SDValue NewLD = DAG.getLoad(NewVT, N0.getDebugLoc(), 5375 LD->getChain(), NewPtr, 5376 LD->getSrcValue(), LD->getSrcValueOffset(), 5377 LD->isVolatile(), LD->isNonTemporal(), 5378 NewAlign); 5379 SDValue NewVal = DAG.getNode(Opc, Value.getDebugLoc(), NewVT, NewLD, 5380 DAG.getConstant(NewImm, NewVT)); 5381 SDValue NewST = DAG.getStore(Chain, N->getDebugLoc(), 5382 NewVal, NewPtr, 5383 ST->getSrcValue(), ST->getSrcValueOffset(), 5384 false, false, NewAlign); 5385 5386 AddToWorkList(NewPtr.getNode()); 5387 AddToWorkList(NewLD.getNode()); 5388 AddToWorkList(NewVal.getNode()); 5389 WorkListRemover DeadNodes(*this); 5390 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), NewLD.getValue(1), 5391 &DeadNodes); 5392 ++OpsNarrowed; 5393 return NewST; 5394 } 5395 } 5396 5397 return SDValue(); 5398} 5399 5400SDValue DAGCombiner::visitSTORE(SDNode *N) { 5401 StoreSDNode *ST = cast<StoreSDNode>(N); 5402 SDValue Chain = ST->getChain(); 5403 SDValue Value = ST->getValue(); 5404 SDValue Ptr = ST->getBasePtr(); 5405 5406 // If this is a store of a bit convert, store the input value if the 5407 // resultant store does not need a higher alignment than the original. 5408 if (Value.getOpcode() == ISD::BIT_CONVERT && !ST->isTruncatingStore() && 5409 ST->isUnindexed()) { 5410 unsigned OrigAlign = ST->getAlignment(); 5411 EVT SVT = Value.getOperand(0).getValueType(); 5412 unsigned Align = TLI.getTargetData()-> 5413 getABITypeAlignment(SVT.getTypeForEVT(*DAG.getContext())); 5414 if (Align <= OrigAlign && 5415 ((!LegalOperations && !ST->isVolatile()) || 5416 TLI.isOperationLegalOrCustom(ISD::STORE, SVT))) 5417 return DAG.getStore(Chain, N->getDebugLoc(), Value.getOperand(0), 5418 Ptr, ST->getSrcValue(), 5419 ST->getSrcValueOffset(), ST->isVolatile(), 5420 ST->isNonTemporal(), OrigAlign); 5421 } 5422 5423 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 5424 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) { 5425 // NOTE: If the original store is volatile, this transform must not increase 5426 // the number of stores. For example, on x86-32 an f64 can be stored in one 5427 // processor operation but an i64 (which is not legal) requires two. So the 5428 // transform should not be done in this case. 5429 if (Value.getOpcode() != ISD::TargetConstantFP) { 5430 SDValue Tmp; 5431 switch (CFP->getValueType(0).getSimpleVT().SimpleTy) { 5432 default: llvm_unreachable("Unknown FP type"); 5433 case MVT::f80: // We don't do this for these yet. 5434 case MVT::f128: 5435 case MVT::ppcf128: 5436 break; 5437 case MVT::f32: 5438 if ((isTypeLegal(MVT::i32) && !LegalOperations && !ST->isVolatile()) || 5439 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) { 5440 Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF(). 5441 bitcastToAPInt().getZExtValue(), MVT::i32); 5442 return DAG.getStore(Chain, N->getDebugLoc(), Tmp, 5443 Ptr, ST->getSrcValue(), 5444 ST->getSrcValueOffset(), ST->isVolatile(), 5445 ST->isNonTemporal(), ST->getAlignment()); 5446 } 5447 break; 5448 case MVT::f64: 5449 if ((TLI.isTypeLegal(MVT::i64) && !LegalOperations && 5450 !ST->isVolatile()) || 5451 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i64)) { 5452 Tmp = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt(). 5453 getZExtValue(), MVT::i64); 5454 return DAG.getStore(Chain, N->getDebugLoc(), Tmp, 5455 Ptr, ST->getSrcValue(), 5456 ST->getSrcValueOffset(), ST->isVolatile(), 5457 ST->isNonTemporal(), ST->getAlignment()); 5458 } else if (!ST->isVolatile() && 5459 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) { 5460 // Many FP stores are not made apparent until after legalize, e.g. for 5461 // argument passing. Since this is so common, custom legalize the 5462 // 64-bit integer store into two 32-bit stores. 5463 uint64_t Val = CFP->getValueAPF().bitcastToAPInt().getZExtValue(); 5464 SDValue Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32); 5465 SDValue Hi = DAG.getConstant(Val >> 32, MVT::i32); 5466 if (TLI.isBigEndian()) std::swap(Lo, Hi); 5467 5468 int SVOffset = ST->getSrcValueOffset(); 5469 unsigned Alignment = ST->getAlignment(); 5470 bool isVolatile = ST->isVolatile(); 5471 bool isNonTemporal = ST->isNonTemporal(); 5472 5473 SDValue St0 = DAG.getStore(Chain, ST->getDebugLoc(), Lo, 5474 Ptr, ST->getSrcValue(), 5475 ST->getSrcValueOffset(), 5476 isVolatile, isNonTemporal, 5477 ST->getAlignment()); 5478 Ptr = DAG.getNode(ISD::ADD, N->getDebugLoc(), Ptr.getValueType(), Ptr, 5479 DAG.getConstant(4, Ptr.getValueType())); 5480 SVOffset += 4; 5481 Alignment = MinAlign(Alignment, 4U); 5482 SDValue St1 = DAG.getStore(Chain, ST->getDebugLoc(), Hi, 5483 Ptr, ST->getSrcValue(), 5484 SVOffset, isVolatile, isNonTemporal, 5485 Alignment); 5486 return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, 5487 St0, St1); 5488 } 5489 5490 break; 5491 } 5492 } 5493 } 5494 5495 // Try to infer better alignment information than the store already has. 5496 if (OptLevel != CodeGenOpt::None && ST->isUnindexed()) { 5497 if (unsigned Align = DAG.InferPtrAlignment(Ptr)) { 5498 if (Align > ST->getAlignment()) 5499 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value, 5500 Ptr, ST->getSrcValue(), 5501 ST->getSrcValueOffset(), ST->getMemoryVT(), 5502 ST->isVolatile(), ST->isNonTemporal(), Align); 5503 } 5504 } 5505 5506 if (CombinerAA) { 5507 // Walk up chain skipping non-aliasing memory nodes. 5508 SDValue BetterChain = FindBetterChain(N, Chain); 5509 5510 // If there is a better chain. 5511 if (Chain != BetterChain) { 5512 SDValue ReplStore; 5513 5514 // Replace the chain to avoid dependency. 5515 if (ST->isTruncatingStore()) { 5516 ReplStore = DAG.getTruncStore(BetterChain, N->getDebugLoc(), Value, Ptr, 5517 ST->getSrcValue(),ST->getSrcValueOffset(), 5518 ST->getMemoryVT(), ST->isVolatile(), 5519 ST->isNonTemporal(), ST->getAlignment()); 5520 } else { 5521 ReplStore = DAG.getStore(BetterChain, N->getDebugLoc(), Value, Ptr, 5522 ST->getSrcValue(), ST->getSrcValueOffset(), 5523 ST->isVolatile(), ST->isNonTemporal(), 5524 ST->getAlignment()); 5525 } 5526 5527 // Create token to keep both nodes around. 5528 SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), 5529 MVT::Other, Chain, ReplStore); 5530 5531 // Make sure the new and old chains are cleaned up. 5532 AddToWorkList(Token.getNode()); 5533 5534 // Don't add users to work list. 5535 return CombineTo(N, Token, false); 5536 } 5537 } 5538 5539 // Try transforming N to an indexed store. 5540 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 5541 return SDValue(N, 0); 5542 5543 // FIXME: is there such a thing as a truncating indexed store? 5544 if (ST->isTruncatingStore() && ST->isUnindexed() && 5545 Value.getValueType().isInteger()) { 5546 // See if we can simplify the input to this truncstore with knowledge that 5547 // only the low bits are being used. For example: 5548 // "truncstore (or (shl x, 8), y), i8" -> "truncstore y, i8" 5549 SDValue Shorter = 5550 GetDemandedBits(Value, 5551 APInt::getLowBitsSet(Value.getValueSizeInBits(), 5552 ST->getMemoryVT().getSizeInBits())); 5553 AddToWorkList(Value.getNode()); 5554 if (Shorter.getNode()) 5555 return DAG.getTruncStore(Chain, N->getDebugLoc(), Shorter, 5556 Ptr, ST->getSrcValue(), 5557 ST->getSrcValueOffset(), ST->getMemoryVT(), 5558 ST->isVolatile(), ST->isNonTemporal(), 5559 ST->getAlignment()); 5560 5561 // Otherwise, see if we can simplify the operation with 5562 // SimplifyDemandedBits, which only works if the value has a single use. 5563 if (SimplifyDemandedBits(Value, 5564 APInt::getLowBitsSet( 5565 Value.getValueType().getScalarType().getSizeInBits(), 5566 ST->getMemoryVT().getScalarType().getSizeInBits()))) 5567 return SDValue(N, 0); 5568 } 5569 5570 // If this is a load followed by a store to the same location, then the store 5571 // is dead/noop. 5572 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Value)) { 5573 if (Ld->getBasePtr() == Ptr && ST->getMemoryVT() == Ld->getMemoryVT() && 5574 ST->isUnindexed() && !ST->isVolatile() && 5575 // There can't be any side effects between the load and store, such as 5576 // a call or store. 5577 Chain.reachesChainWithoutSideEffects(SDValue(Ld, 1))) { 5578 // The store is dead, remove it. 5579 return Chain; 5580 } 5581 } 5582 5583 // If this is an FP_ROUND or TRUNC followed by a store, fold this into a 5584 // truncating store. We can do this even if this is already a truncstore. 5585 if ((Value.getOpcode() == ISD::FP_ROUND || Value.getOpcode() == ISD::TRUNCATE) 5586 && Value.getNode()->hasOneUse() && ST->isUnindexed() && 5587 TLI.isTruncStoreLegal(Value.getOperand(0).getValueType(), 5588 ST->getMemoryVT())) { 5589 return DAG.getTruncStore(Chain, N->getDebugLoc(), Value.getOperand(0), 5590 Ptr, ST->getSrcValue(), 5591 ST->getSrcValueOffset(), ST->getMemoryVT(), 5592 ST->isVolatile(), ST->isNonTemporal(), 5593 ST->getAlignment()); 5594 } 5595 5596 return ReduceLoadOpStoreWidth(N); 5597} 5598 5599SDValue DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) { 5600 SDValue InVec = N->getOperand(0); 5601 SDValue InVal = N->getOperand(1); 5602 SDValue EltNo = N->getOperand(2); 5603 5604 // If the invec is a BUILD_VECTOR and if EltNo is a constant, build a new 5605 // vector with the inserted element. 5606 if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) { 5607 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 5608 SmallVector<SDValue, 8> Ops(InVec.getNode()->op_begin(), 5609 InVec.getNode()->op_end()); 5610 if (Elt < Ops.size()) 5611 Ops[Elt] = InVal; 5612 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 5613 InVec.getValueType(), &Ops[0], Ops.size()); 5614 } 5615 // If the invec is an UNDEF and if EltNo is a constant, create a new 5616 // BUILD_VECTOR with undef elements and the inserted element. 5617 if (!LegalOperations && InVec.getOpcode() == ISD::UNDEF && 5618 isa<ConstantSDNode>(EltNo)) { 5619 EVT VT = InVec.getValueType(); 5620 EVT EltVT = VT.getVectorElementType(); 5621 unsigned NElts = VT.getVectorNumElements(); 5622 SmallVector<SDValue, 8> Ops(NElts, DAG.getUNDEF(EltVT)); 5623 5624 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 5625 if (Elt < Ops.size()) 5626 Ops[Elt] = InVal; 5627 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 5628 InVec.getValueType(), &Ops[0], Ops.size()); 5629 } 5630 return SDValue(); 5631} 5632 5633SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) { 5634 // (vextract (scalar_to_vector val, 0) -> val 5635 SDValue InVec = N->getOperand(0); 5636 5637 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) { 5638 // Check if the result type doesn't match the inserted element type. A 5639 // SCALAR_TO_VECTOR may truncate the inserted element and the 5640 // EXTRACT_VECTOR_ELT may widen the extracted vector. 5641 EVT EltVT = InVec.getValueType().getVectorElementType(); 5642 SDValue InOp = InVec.getOperand(0); 5643 EVT NVT = N->getValueType(0); 5644 if (InOp.getValueType() != NVT) { 5645 assert(InOp.getValueType().isInteger() && NVT.isInteger()); 5646 return DAG.getSExtOrTrunc(InOp, InVec.getDebugLoc(), NVT); 5647 } 5648 return InOp; 5649 } 5650 5651 // Perform only after legalization to ensure build_vector / vector_shuffle 5652 // optimizations have already been done. 5653 if (!LegalOperations) return SDValue(); 5654 5655 // (vextract (v4f32 load $addr), c) -> (f32 load $addr+c*size) 5656 // (vextract (v4f32 s2v (f32 load $addr)), c) -> (f32 load $addr+c*size) 5657 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), 0) -> (f32 load $addr) 5658 SDValue EltNo = N->getOperand(1); 5659 5660 if (isa<ConstantSDNode>(EltNo)) { 5661 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 5662 bool NewLoad = false; 5663 bool BCNumEltsChanged = false; 5664 EVT VT = InVec.getValueType(); 5665 EVT ExtVT = VT.getVectorElementType(); 5666 EVT LVT = ExtVT; 5667 5668 if (InVec.getOpcode() == ISD::BIT_CONVERT) { 5669 EVT BCVT = InVec.getOperand(0).getValueType(); 5670 if (!BCVT.isVector() || ExtVT.bitsGT(BCVT.getVectorElementType())) 5671 return SDValue(); 5672 if (VT.getVectorNumElements() != BCVT.getVectorNumElements()) 5673 BCNumEltsChanged = true; 5674 InVec = InVec.getOperand(0); 5675 ExtVT = BCVT.getVectorElementType(); 5676 NewLoad = true; 5677 } 5678 5679 LoadSDNode *LN0 = NULL; 5680 const ShuffleVectorSDNode *SVN = NULL; 5681 if (ISD::isNormalLoad(InVec.getNode())) { 5682 LN0 = cast<LoadSDNode>(InVec); 5683 } else if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR && 5684 InVec.getOperand(0).getValueType() == ExtVT && 5685 ISD::isNormalLoad(InVec.getOperand(0).getNode())) { 5686 LN0 = cast<LoadSDNode>(InVec.getOperand(0)); 5687 } else if ((SVN = dyn_cast<ShuffleVectorSDNode>(InVec))) { 5688 // (vextract (vector_shuffle (load $addr), v2, <1, u, u, u>), 1) 5689 // => 5690 // (load $addr+1*size) 5691 5692 // If the bit convert changed the number of elements, it is unsafe 5693 // to examine the mask. 5694 if (BCNumEltsChanged) 5695 return SDValue(); 5696 5697 // Select the input vector, guarding against out of range extract vector. 5698 unsigned NumElems = VT.getVectorNumElements(); 5699 int Idx = (Elt > NumElems) ? -1 : SVN->getMaskElt(Elt); 5700 InVec = (Idx < (int)NumElems) ? InVec.getOperand(0) : InVec.getOperand(1); 5701 5702 if (InVec.getOpcode() == ISD::BIT_CONVERT) 5703 InVec = InVec.getOperand(0); 5704 if (ISD::isNormalLoad(InVec.getNode())) { 5705 LN0 = cast<LoadSDNode>(InVec); 5706 Elt = (Idx < (int)NumElems) ? Idx : Idx - (int)NumElems; 5707 } 5708 } 5709 5710 if (!LN0 || !LN0->hasOneUse() || LN0->isVolatile()) 5711 return SDValue(); 5712 5713 unsigned Align = LN0->getAlignment(); 5714 if (NewLoad) { 5715 // Check the resultant load doesn't need a higher alignment than the 5716 // original load. 5717 unsigned NewAlign = 5718 TLI.getTargetData()->getABITypeAlignment(LVT.getTypeForEVT(*DAG.getContext())); 5719 5720 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, LVT)) 5721 return SDValue(); 5722 5723 Align = NewAlign; 5724 } 5725 5726 SDValue NewPtr = LN0->getBasePtr(); 5727 if (Elt) { 5728 unsigned PtrOff = LVT.getSizeInBits() * Elt / 8; 5729 EVT PtrType = NewPtr.getValueType(); 5730 if (TLI.isBigEndian()) 5731 PtrOff = VT.getSizeInBits() / 8 - PtrOff; 5732 NewPtr = DAG.getNode(ISD::ADD, N->getDebugLoc(), PtrType, NewPtr, 5733 DAG.getConstant(PtrOff, PtrType)); 5734 } 5735 5736 return DAG.getLoad(LVT, N->getDebugLoc(), LN0->getChain(), NewPtr, 5737 LN0->getSrcValue(), LN0->getSrcValueOffset(), 5738 LN0->isVolatile(), LN0->isNonTemporal(), Align); 5739 } 5740 5741 return SDValue(); 5742} 5743 5744SDValue DAGCombiner::visitBUILD_VECTOR(SDNode *N) { 5745 unsigned NumInScalars = N->getNumOperands(); 5746 EVT VT = N->getValueType(0); 5747 5748 // Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT 5749 // operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from 5750 // at most two distinct vectors, turn this into a shuffle node. 5751 SDValue VecIn1, VecIn2; 5752 for (unsigned i = 0; i != NumInScalars; ++i) { 5753 // Ignore undef inputs. 5754 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 5755 5756 // If this input is something other than a EXTRACT_VECTOR_ELT with a 5757 // constant index, bail out. 5758 if (N->getOperand(i).getOpcode() != ISD::EXTRACT_VECTOR_ELT || 5759 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) { 5760 VecIn1 = VecIn2 = SDValue(0, 0); 5761 break; 5762 } 5763 5764 // If the input vector type disagrees with the result of the build_vector, 5765 // we can't make a shuffle. 5766 SDValue ExtractedFromVec = N->getOperand(i).getOperand(0); 5767 if (ExtractedFromVec.getValueType() != VT) { 5768 VecIn1 = VecIn2 = SDValue(0, 0); 5769 break; 5770 } 5771 5772 // Otherwise, remember this. We allow up to two distinct input vectors. 5773 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2) 5774 continue; 5775 5776 if (VecIn1.getNode() == 0) { 5777 VecIn1 = ExtractedFromVec; 5778 } else if (VecIn2.getNode() == 0) { 5779 VecIn2 = ExtractedFromVec; 5780 } else { 5781 // Too many inputs. 5782 VecIn1 = VecIn2 = SDValue(0, 0); 5783 break; 5784 } 5785 } 5786 5787 // If everything is good, we can make a shuffle operation. 5788 if (VecIn1.getNode()) { 5789 SmallVector<int, 8> Mask; 5790 for (unsigned i = 0; i != NumInScalars; ++i) { 5791 if (N->getOperand(i).getOpcode() == ISD::UNDEF) { 5792 Mask.push_back(-1); 5793 continue; 5794 } 5795 5796 // If extracting from the first vector, just use the index directly. 5797 SDValue Extract = N->getOperand(i); 5798 SDValue ExtVal = Extract.getOperand(1); 5799 if (Extract.getOperand(0) == VecIn1) { 5800 unsigned ExtIndex = cast<ConstantSDNode>(ExtVal)->getZExtValue(); 5801 if (ExtIndex > VT.getVectorNumElements()) 5802 return SDValue(); 5803 5804 Mask.push_back(ExtIndex); 5805 continue; 5806 } 5807 5808 // Otherwise, use InIdx + VecSize 5809 unsigned Idx = cast<ConstantSDNode>(ExtVal)->getZExtValue(); 5810 Mask.push_back(Idx+NumInScalars); 5811 } 5812 5813 // Add count and size info. 5814 if (!isTypeLegal(VT)) 5815 return SDValue(); 5816 5817 // Return the new VECTOR_SHUFFLE node. 5818 SDValue Ops[2]; 5819 Ops[0] = VecIn1; 5820 Ops[1] = VecIn2.getNode() ? VecIn2 : DAG.getUNDEF(VT); 5821 return DAG.getVectorShuffle(VT, N->getDebugLoc(), Ops[0], Ops[1], &Mask[0]); 5822 } 5823 5824 return SDValue(); 5825} 5826 5827SDValue DAGCombiner::visitCONCAT_VECTORS(SDNode *N) { 5828 // TODO: Check to see if this is a CONCAT_VECTORS of a bunch of 5829 // EXTRACT_SUBVECTOR operations. If so, and if the EXTRACT_SUBVECTOR vector 5830 // inputs come from at most two distinct vectors, turn this into a shuffle 5831 // node. 5832 5833 // If we only have one input vector, we don't need to do any concatenation. 5834 if (N->getNumOperands() == 1) 5835 return N->getOperand(0); 5836 5837 return SDValue(); 5838} 5839 5840SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) { 5841 return SDValue(); 5842 5843 EVT VT = N->getValueType(0); 5844 unsigned NumElts = VT.getVectorNumElements(); 5845 5846 SDValue N0 = N->getOperand(0); 5847 5848 assert(N0.getValueType().getVectorNumElements() == NumElts && 5849 "Vector shuffle must be normalized in DAG"); 5850 5851 // FIXME: implement canonicalizations from DAG.getVectorShuffle() 5852 5853 // If it is a splat, check if the argument vector is a build_vector with 5854 // all scalar elements the same. 5855 if (cast<ShuffleVectorSDNode>(N)->isSplat()) { 5856 SDNode *V = N0.getNode(); 5857 5858 5859 // If this is a bit convert that changes the element type of the vector but 5860 // not the number of vector elements, look through it. Be careful not to 5861 // look though conversions that change things like v4f32 to v2f64. 5862 if (V->getOpcode() == ISD::BIT_CONVERT) { 5863 SDValue ConvInput = V->getOperand(0); 5864 if (ConvInput.getValueType().isVector() && 5865 ConvInput.getValueType().getVectorNumElements() == NumElts) 5866 V = ConvInput.getNode(); 5867 } 5868 5869 if (V->getOpcode() == ISD::BUILD_VECTOR) { 5870 unsigned NumElems = V->getNumOperands(); 5871 unsigned BaseIdx = cast<ShuffleVectorSDNode>(N)->getSplatIndex(); 5872 if (NumElems > BaseIdx) { 5873 SDValue Base; 5874 bool AllSame = true; 5875 for (unsigned i = 0; i != NumElems; ++i) { 5876 if (V->getOperand(i).getOpcode() != ISD::UNDEF) { 5877 Base = V->getOperand(i); 5878 break; 5879 } 5880 } 5881 // Splat of <u, u, u, u>, return <u, u, u, u> 5882 if (!Base.getNode()) 5883 return N0; 5884 for (unsigned i = 0; i != NumElems; ++i) { 5885 if (V->getOperand(i) != Base) { 5886 AllSame = false; 5887 break; 5888 } 5889 } 5890 // Splat of <x, x, x, x>, return <x, x, x, x> 5891 if (AllSame) 5892 return N0; 5893 } 5894 } 5895 } 5896 return SDValue(); 5897} 5898 5899/// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform 5900/// an AND to a vector_shuffle with the destination vector and a zero vector. 5901/// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==> 5902/// vector_shuffle V, Zero, <0, 4, 2, 4> 5903SDValue DAGCombiner::XformToShuffleWithZero(SDNode *N) { 5904 EVT VT = N->getValueType(0); 5905 DebugLoc dl = N->getDebugLoc(); 5906 SDValue LHS = N->getOperand(0); 5907 SDValue RHS = N->getOperand(1); 5908 if (N->getOpcode() == ISD::AND) { 5909 if (RHS.getOpcode() == ISD::BIT_CONVERT) 5910 RHS = RHS.getOperand(0); 5911 if (RHS.getOpcode() == ISD::BUILD_VECTOR) { 5912 SmallVector<int, 8> Indices; 5913 unsigned NumElts = RHS.getNumOperands(); 5914 for (unsigned i = 0; i != NumElts; ++i) { 5915 SDValue Elt = RHS.getOperand(i); 5916 if (!isa<ConstantSDNode>(Elt)) 5917 return SDValue(); 5918 else if (cast<ConstantSDNode>(Elt)->isAllOnesValue()) 5919 Indices.push_back(i); 5920 else if (cast<ConstantSDNode>(Elt)->isNullValue()) 5921 Indices.push_back(NumElts); 5922 else 5923 return SDValue(); 5924 } 5925 5926 // Let's see if the target supports this vector_shuffle. 5927 EVT RVT = RHS.getValueType(); 5928 if (!TLI.isVectorClearMaskLegal(Indices, RVT)) 5929 return SDValue(); 5930 5931 // Return the new VECTOR_SHUFFLE node. 5932 EVT EltVT = RVT.getVectorElementType(); 5933 SmallVector<SDValue,8> ZeroOps(RVT.getVectorNumElements(), 5934 DAG.getConstant(0, EltVT)); 5935 SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), 5936 RVT, &ZeroOps[0], ZeroOps.size()); 5937 LHS = DAG.getNode(ISD::BIT_CONVERT, dl, RVT, LHS); 5938 SDValue Shuf = DAG.getVectorShuffle(RVT, dl, LHS, Zero, &Indices[0]); 5939 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Shuf); 5940 } 5941 } 5942 5943 return SDValue(); 5944} 5945 5946/// SimplifyVBinOp - Visit a binary vector operation, like ADD. 5947SDValue DAGCombiner::SimplifyVBinOp(SDNode *N) { 5948 // After legalize, the target may be depending on adds and other 5949 // binary ops to provide legal ways to construct constants or other 5950 // things. Simplifying them may result in a loss of legality. 5951 if (LegalOperations) return SDValue(); 5952 5953 EVT VT = N->getValueType(0); 5954 assert(VT.isVector() && "SimplifyVBinOp only works on vectors!"); 5955 5956 EVT EltType = VT.getVectorElementType(); 5957 SDValue LHS = N->getOperand(0); 5958 SDValue RHS = N->getOperand(1); 5959 SDValue Shuffle = XformToShuffleWithZero(N); 5960 if (Shuffle.getNode()) return Shuffle; 5961 5962 // If the LHS and RHS are BUILD_VECTOR nodes, see if we can constant fold 5963 // this operation. 5964 if (LHS.getOpcode() == ISD::BUILD_VECTOR && 5965 RHS.getOpcode() == ISD::BUILD_VECTOR) { 5966 SmallVector<SDValue, 8> Ops; 5967 for (unsigned i = 0, e = LHS.getNumOperands(); i != e; ++i) { 5968 SDValue LHSOp = LHS.getOperand(i); 5969 SDValue RHSOp = RHS.getOperand(i); 5970 // If these two elements can't be folded, bail out. 5971 if ((LHSOp.getOpcode() != ISD::UNDEF && 5972 LHSOp.getOpcode() != ISD::Constant && 5973 LHSOp.getOpcode() != ISD::ConstantFP) || 5974 (RHSOp.getOpcode() != ISD::UNDEF && 5975 RHSOp.getOpcode() != ISD::Constant && 5976 RHSOp.getOpcode() != ISD::ConstantFP)) 5977 break; 5978 5979 // Can't fold divide by zero. 5980 if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV || 5981 N->getOpcode() == ISD::FDIV) { 5982 if ((RHSOp.getOpcode() == ISD::Constant && 5983 cast<ConstantSDNode>(RHSOp.getNode())->isNullValue()) || 5984 (RHSOp.getOpcode() == ISD::ConstantFP && 5985 cast<ConstantFPSDNode>(RHSOp.getNode())->getValueAPF().isZero())) 5986 break; 5987 } 5988 5989 Ops.push_back(DAG.getNode(N->getOpcode(), LHS.getDebugLoc(), 5990 EltType, LHSOp, RHSOp)); 5991 AddToWorkList(Ops.back().getNode()); 5992 assert((Ops.back().getOpcode() == ISD::UNDEF || 5993 Ops.back().getOpcode() == ISD::Constant || 5994 Ops.back().getOpcode() == ISD::ConstantFP) && 5995 "Scalar binop didn't fold!"); 5996 } 5997 5998 if (Ops.size() == LHS.getNumOperands()) { 5999 EVT VT = LHS.getValueType(); 6000 return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT, 6001 &Ops[0], Ops.size()); 6002 } 6003 } 6004 6005 return SDValue(); 6006} 6007 6008SDValue DAGCombiner::SimplifySelect(DebugLoc DL, SDValue N0, 6009 SDValue N1, SDValue N2){ 6010 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!"); 6011 6012 SDValue SCC = SimplifySelectCC(DL, N0.getOperand(0), N0.getOperand(1), N1, N2, 6013 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 6014 6015 // If we got a simplified select_cc node back from SimplifySelectCC, then 6016 // break it down into a new SETCC node, and a new SELECT node, and then return 6017 // the SELECT node, since we were called with a SELECT node. 6018 if (SCC.getNode()) { 6019 // Check to see if we got a select_cc back (to turn into setcc/select). 6020 // Otherwise, just return whatever node we got back, like fabs. 6021 if (SCC.getOpcode() == ISD::SELECT_CC) { 6022 SDValue SETCC = DAG.getNode(ISD::SETCC, N0.getDebugLoc(), 6023 N0.getValueType(), 6024 SCC.getOperand(0), SCC.getOperand(1), 6025 SCC.getOperand(4)); 6026 AddToWorkList(SETCC.getNode()); 6027 return DAG.getNode(ISD::SELECT, SCC.getDebugLoc(), SCC.getValueType(), 6028 SCC.getOperand(2), SCC.getOperand(3), SETCC); 6029 } 6030 6031 return SCC; 6032 } 6033 return SDValue(); 6034} 6035 6036/// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS 6037/// are the two values being selected between, see if we can simplify the 6038/// select. Callers of this should assume that TheSelect is deleted if this 6039/// returns true. As such, they should return the appropriate thing (e.g. the 6040/// node) back to the top-level of the DAG combiner loop to avoid it being 6041/// looked at. 6042bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDValue LHS, 6043 SDValue RHS) { 6044 6045 // If this is a select from two identical things, try to pull the operation 6046 // through the select. 6047 if (LHS.getOpcode() == RHS.getOpcode() && LHS.hasOneUse() && RHS.hasOneUse()){ 6048 // If this is a load and the token chain is identical, replace the select 6049 // of two loads with a load through a select of the address to load from. 6050 // This triggers in things like "select bool X, 10.0, 123.0" after the FP 6051 // constants have been dropped into the constant pool. 6052 if (LHS.getOpcode() == ISD::LOAD && 6053 // Do not let this transformation reduce the number of volatile loads. 6054 !cast<LoadSDNode>(LHS)->isVolatile() && 6055 !cast<LoadSDNode>(RHS)->isVolatile() && 6056 // Token chains must be identical. 6057 LHS.getOperand(0) == RHS.getOperand(0)) { 6058 LoadSDNode *LLD = cast<LoadSDNode>(LHS); 6059 LoadSDNode *RLD = cast<LoadSDNode>(RHS); 6060 6061 // If this is an EXTLOAD, the VT's must match. 6062 if (LLD->getMemoryVT() == RLD->getMemoryVT()) { 6063 // FIXME: this discards src value information. This is 6064 // over-conservative. It would be beneficial to be able to remember 6065 // both potential memory locations. Since we are discarding 6066 // src value info, don't do the transformation if the memory 6067 // locations are not in the default address space. 6068 unsigned LLDAddrSpace = 0, RLDAddrSpace = 0; 6069 if (const Value *LLDVal = LLD->getMemOperand()->getValue()) { 6070 if (const PointerType *PT = dyn_cast<PointerType>(LLDVal->getType())) 6071 LLDAddrSpace = PT->getAddressSpace(); 6072 } 6073 if (const Value *RLDVal = RLD->getMemOperand()->getValue()) { 6074 if (const PointerType *PT = dyn_cast<PointerType>(RLDVal->getType())) 6075 RLDAddrSpace = PT->getAddressSpace(); 6076 } 6077 SDValue Addr; 6078 if (LLDAddrSpace == 0 && RLDAddrSpace == 0) { 6079 if (TheSelect->getOpcode() == ISD::SELECT) { 6080 // Check that the condition doesn't reach either load. If so, folding 6081 // this will induce a cycle into the DAG. 6082 if ((!LLD->hasAnyUseOfValue(1) || 6083 !LLD->isPredecessorOf(TheSelect->getOperand(0).getNode())) && 6084 (!RLD->hasAnyUseOfValue(1) || 6085 !RLD->isPredecessorOf(TheSelect->getOperand(0).getNode()))) { 6086 Addr = DAG.getNode(ISD::SELECT, TheSelect->getDebugLoc(), 6087 LLD->getBasePtr().getValueType(), 6088 TheSelect->getOperand(0), LLD->getBasePtr(), 6089 RLD->getBasePtr()); 6090 } 6091 } else { 6092 // Check that the condition doesn't reach either load. If so, folding 6093 // this will induce a cycle into the DAG. 6094 if ((!LLD->hasAnyUseOfValue(1) || 6095 (!LLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) && 6096 !LLD->isPredecessorOf(TheSelect->getOperand(1).getNode()))) && 6097 (!RLD->hasAnyUseOfValue(1) || 6098 (!RLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) && 6099 !RLD->isPredecessorOf(TheSelect->getOperand(1).getNode())))) { 6100 Addr = DAG.getNode(ISD::SELECT_CC, TheSelect->getDebugLoc(), 6101 LLD->getBasePtr().getValueType(), 6102 TheSelect->getOperand(0), 6103 TheSelect->getOperand(1), 6104 LLD->getBasePtr(), RLD->getBasePtr(), 6105 TheSelect->getOperand(4)); 6106 } 6107 } 6108 } 6109 6110 if (Addr.getNode()) { 6111 SDValue Load; 6112 if (LLD->getExtensionType() == ISD::NON_EXTLOAD) { 6113 Load = DAG.getLoad(TheSelect->getValueType(0), 6114 TheSelect->getDebugLoc(), 6115 LLD->getChain(), 6116 Addr, 0, 0, 6117 LLD->isVolatile(), 6118 LLD->isNonTemporal(), 6119 LLD->getAlignment()); 6120 } else { 6121 Load = DAG.getExtLoad(LLD->getExtensionType(), 6122 TheSelect->getDebugLoc(), 6123 TheSelect->getValueType(0), 6124 LLD->getChain(), Addr, 0, 0, 6125 LLD->getMemoryVT(), 6126 LLD->isVolatile(), 6127 LLD->isNonTemporal(), 6128 LLD->getAlignment()); 6129 } 6130 6131 // Users of the select now use the result of the load. 6132 CombineTo(TheSelect, Load); 6133 6134 // Users of the old loads now use the new load's chain. We know the 6135 // old-load value is dead now. 6136 CombineTo(LHS.getNode(), Load.getValue(0), Load.getValue(1)); 6137 CombineTo(RHS.getNode(), Load.getValue(0), Load.getValue(1)); 6138 return true; 6139 } 6140 } 6141 } 6142 } 6143 6144 return false; 6145} 6146 6147/// SimplifySelectCC - Simplify an expression of the form (N0 cond N1) ? N2 : N3 6148/// where 'cond' is the comparison specified by CC. 6149SDValue DAGCombiner::SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, 6150 SDValue N2, SDValue N3, 6151 ISD::CondCode CC, bool NotExtCompare) { 6152 // (x ? y : y) -> y. 6153 if (N2 == N3) return N2; 6154 6155 EVT VT = N2.getValueType(); 6156 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 6157 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode()); 6158 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.getNode()); 6159 6160 // Determine if the condition we're dealing with is constant 6161 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0.getValueType()), 6162 N0, N1, CC, DL, false); 6163 if (SCC.getNode()) AddToWorkList(SCC.getNode()); 6164 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode()); 6165 6166 // fold select_cc true, x, y -> x 6167 if (SCCC && !SCCC->isNullValue()) 6168 return N2; 6169 // fold select_cc false, x, y -> y 6170 if (SCCC && SCCC->isNullValue()) 6171 return N3; 6172 6173 // Check to see if we can simplify the select into an fabs node 6174 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) { 6175 // Allow either -0.0 or 0.0 6176 if (CFP->getValueAPF().isZero()) { 6177 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs 6178 if ((CC == ISD::SETGE || CC == ISD::SETGT) && 6179 N0 == N2 && N3.getOpcode() == ISD::FNEG && 6180 N2 == N3.getOperand(0)) 6181 return DAG.getNode(ISD::FABS, DL, VT, N0); 6182 6183 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs 6184 if ((CC == ISD::SETLT || CC == ISD::SETLE) && 6185 N0 == N3 && N2.getOpcode() == ISD::FNEG && 6186 N2.getOperand(0) == N3) 6187 return DAG.getNode(ISD::FABS, DL, VT, N3); 6188 } 6189 } 6190 6191 // Turn "(a cond b) ? 1.0f : 2.0f" into "load (tmp + ((a cond b) ? 0 : 4)" 6192 // where "tmp" is a constant pool entry containing an array with 1.0 and 2.0 6193 // in it. This is a win when the constant is not otherwise available because 6194 // it replaces two constant pool loads with one. We only do this if the FP 6195 // type is known to be legal, because if it isn't, then we are before legalize 6196 // types an we want the other legalization to happen first (e.g. to avoid 6197 // messing with soft float) and if the ConstantFP is not legal, because if 6198 // it is legal, we may not need to store the FP constant in a constant pool. 6199 if (ConstantFPSDNode *TV = dyn_cast<ConstantFPSDNode>(N2)) 6200 if (ConstantFPSDNode *FV = dyn_cast<ConstantFPSDNode>(N3)) { 6201 if (TLI.isTypeLegal(N2.getValueType()) && 6202 (TLI.getOperationAction(ISD::ConstantFP, N2.getValueType()) != 6203 TargetLowering::Legal) && 6204 // If both constants have multiple uses, then we won't need to do an 6205 // extra load, they are likely around in registers for other users. 6206 (TV->hasOneUse() || FV->hasOneUse())) { 6207 Constant *Elts[] = { 6208 const_cast<ConstantFP*>(FV->getConstantFPValue()), 6209 const_cast<ConstantFP*>(TV->getConstantFPValue()) 6210 }; 6211 const Type *FPTy = Elts[0]->getType(); 6212 const TargetData &TD = *TLI.getTargetData(); 6213 6214 // Create a ConstantArray of the two constants. 6215 Constant *CA = ConstantArray::get(ArrayType::get(FPTy, 2), Elts, 2); 6216 SDValue CPIdx = DAG.getConstantPool(CA, TLI.getPointerTy(), 6217 TD.getPrefTypeAlignment(FPTy)); 6218 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 6219 6220 // Get the offsets to the 0 and 1 element of the array so that we can 6221 // select between them. 6222 SDValue Zero = DAG.getIntPtrConstant(0); 6223 unsigned EltSize = (unsigned)TD.getTypeAllocSize(Elts[0]->getType()); 6224 SDValue One = DAG.getIntPtrConstant(EltSize); 6225 6226 SDValue Cond = DAG.getSetCC(DL, 6227 TLI.getSetCCResultType(N0.getValueType()), 6228 N0, N1, CC); 6229 SDValue CstOffset = DAG.getNode(ISD::SELECT, DL, Zero.getValueType(), 6230 Cond, One, Zero); 6231 CPIdx = DAG.getNode(ISD::ADD, DL, TLI.getPointerTy(), CPIdx, 6232 CstOffset); 6233 return DAG.getLoad(TV->getValueType(0), DL, DAG.getEntryNode(), CPIdx, 6234 PseudoSourceValue::getConstantPool(), 0, false, 6235 false, Alignment); 6236 6237 } 6238 } 6239 6240 // Check to see if we can perform the "gzip trick", transforming 6241 // (select_cc setlt X, 0, A, 0) -> (and (sra X, (sub size(X), 1), A) 6242 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT && 6243 N0.getValueType().isInteger() && 6244 N2.getValueType().isInteger() && 6245 (N1C->isNullValue() || // (a < 0) ? b : 0 6246 (N1C->getAPIntValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0 6247 EVT XType = N0.getValueType(); 6248 EVT AType = N2.getValueType(); 6249 if (XType.bitsGE(AType)) { 6250 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a 6251 // single-bit constant. 6252 if (N2C && ((N2C->getAPIntValue() & (N2C->getAPIntValue()-1)) == 0)) { 6253 unsigned ShCtV = N2C->getAPIntValue().logBase2(); 6254 ShCtV = XType.getSizeInBits()-ShCtV-1; 6255 SDValue ShCt = DAG.getConstant(ShCtV, getShiftAmountTy()); 6256 SDValue Shift = DAG.getNode(ISD::SRL, N0.getDebugLoc(), 6257 XType, N0, ShCt); 6258 AddToWorkList(Shift.getNode()); 6259 6260 if (XType.bitsGT(AType)) { 6261 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift); 6262 AddToWorkList(Shift.getNode()); 6263 } 6264 6265 return DAG.getNode(ISD::AND, DL, AType, Shift, N2); 6266 } 6267 6268 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), 6269 XType, N0, 6270 DAG.getConstant(XType.getSizeInBits()-1, 6271 getShiftAmountTy())); 6272 AddToWorkList(Shift.getNode()); 6273 6274 if (XType.bitsGT(AType)) { 6275 Shift = DAG.getNode(ISD::TRUNCATE, DL, AType, Shift); 6276 AddToWorkList(Shift.getNode()); 6277 } 6278 6279 return DAG.getNode(ISD::AND, DL, AType, Shift, N2); 6280 } 6281 } 6282 6283 // fold select C, 16, 0 -> shl C, 4 6284 if (N2C && N3C && N3C->isNullValue() && N2C->getAPIntValue().isPowerOf2() && 6285 TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent) { 6286 6287 // If the caller doesn't want us to simplify this into a zext of a compare, 6288 // don't do it. 6289 if (NotExtCompare && N2C->getAPIntValue() == 1) 6290 return SDValue(); 6291 6292 // Get a SetCC of the condition 6293 // FIXME: Should probably make sure that setcc is legal if we ever have a 6294 // target where it isn't. 6295 SDValue Temp, SCC; 6296 // cast from setcc result type to select result type 6297 if (LegalTypes) { 6298 SCC = DAG.getSetCC(DL, TLI.getSetCCResultType(N0.getValueType()), 6299 N0, N1, CC); 6300 if (N2.getValueType().bitsLT(SCC.getValueType())) 6301 Temp = DAG.getZeroExtendInReg(SCC, N2.getDebugLoc(), N2.getValueType()); 6302 else 6303 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(), 6304 N2.getValueType(), SCC); 6305 } else { 6306 SCC = DAG.getSetCC(N0.getDebugLoc(), MVT::i1, N0, N1, CC); 6307 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(), 6308 N2.getValueType(), SCC); 6309 } 6310 6311 AddToWorkList(SCC.getNode()); 6312 AddToWorkList(Temp.getNode()); 6313 6314 if (N2C->getAPIntValue() == 1) 6315 return Temp; 6316 6317 // shl setcc result by log2 n2c 6318 return DAG.getNode(ISD::SHL, DL, N2.getValueType(), Temp, 6319 DAG.getConstant(N2C->getAPIntValue().logBase2(), 6320 getShiftAmountTy())); 6321 } 6322 6323 // Check to see if this is the equivalent of setcc 6324 // FIXME: Turn all of these into setcc if setcc if setcc is legal 6325 // otherwise, go ahead with the folds. 6326 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getAPIntValue() == 1ULL)) { 6327 EVT XType = N0.getValueType(); 6328 if (!LegalOperations || 6329 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(XType))) { 6330 SDValue Res = DAG.getSetCC(DL, TLI.getSetCCResultType(XType), N0, N1, CC); 6331 if (Res.getValueType() != VT) 6332 Res = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, Res); 6333 return Res; 6334 } 6335 6336 // fold (seteq X, 0) -> (srl (ctlz X, log2(size(X)))) 6337 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ && 6338 (!LegalOperations || 6339 TLI.isOperationLegal(ISD::CTLZ, XType))) { 6340 SDValue Ctlz = DAG.getNode(ISD::CTLZ, N0.getDebugLoc(), XType, N0); 6341 return DAG.getNode(ISD::SRL, DL, XType, Ctlz, 6342 DAG.getConstant(Log2_32(XType.getSizeInBits()), 6343 getShiftAmountTy())); 6344 } 6345 // fold (setgt X, 0) -> (srl (and (-X, ~X), size(X)-1)) 6346 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) { 6347 SDValue NegN0 = DAG.getNode(ISD::SUB, N0.getDebugLoc(), 6348 XType, DAG.getConstant(0, XType), N0); 6349 SDValue NotN0 = DAG.getNOT(N0.getDebugLoc(), N0, XType); 6350 return DAG.getNode(ISD::SRL, DL, XType, 6351 DAG.getNode(ISD::AND, DL, XType, NegN0, NotN0), 6352 DAG.getConstant(XType.getSizeInBits()-1, 6353 getShiftAmountTy())); 6354 } 6355 // fold (setgt X, -1) -> (xor (srl (X, size(X)-1), 1)) 6356 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) { 6357 SDValue Sign = DAG.getNode(ISD::SRL, N0.getDebugLoc(), XType, N0, 6358 DAG.getConstant(XType.getSizeInBits()-1, 6359 getShiftAmountTy())); 6360 return DAG.getNode(ISD::XOR, DL, XType, Sign, DAG.getConstant(1, XType)); 6361 } 6362 } 6363 6364 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X -> 6365 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 6366 if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) && 6367 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1) && 6368 N2.getOperand(0) == N1 && N0.getValueType().isInteger()) { 6369 EVT XType = N0.getValueType(); 6370 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), XType, N0, 6371 DAG.getConstant(XType.getSizeInBits()-1, 6372 getShiftAmountTy())); 6373 SDValue Add = DAG.getNode(ISD::ADD, N0.getDebugLoc(), XType, 6374 N0, Shift); 6375 AddToWorkList(Shift.getNode()); 6376 AddToWorkList(Add.getNode()); 6377 return DAG.getNode(ISD::XOR, DL, XType, Add, Shift); 6378 } 6379 // Check to see if this is an integer abs. select_cc setgt X, -1, X, -X -> 6380 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 6381 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT && 6382 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1)) { 6383 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0))) { 6384 EVT XType = N0.getValueType(); 6385 if (SubC->isNullValue() && XType.isInteger()) { 6386 SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), XType, 6387 N0, 6388 DAG.getConstant(XType.getSizeInBits()-1, 6389 getShiftAmountTy())); 6390 SDValue Add = DAG.getNode(ISD::ADD, N0.getDebugLoc(), 6391 XType, N0, Shift); 6392 AddToWorkList(Shift.getNode()); 6393 AddToWorkList(Add.getNode()); 6394 return DAG.getNode(ISD::XOR, DL, XType, Add, Shift); 6395 } 6396 } 6397 } 6398 6399 return SDValue(); 6400} 6401 6402/// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC. 6403SDValue DAGCombiner::SimplifySetCC(EVT VT, SDValue N0, 6404 SDValue N1, ISD::CondCode Cond, 6405 DebugLoc DL, bool foldBooleans) { 6406 TargetLowering::DAGCombinerInfo 6407 DagCombineInfo(DAG, !LegalTypes, !LegalOperations, false, this); 6408 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo, DL); 6409} 6410 6411/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 6412/// return a DAG expression to select that will generate the same value by 6413/// multiplying by a magic number. See: 6414/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 6415SDValue DAGCombiner::BuildSDIV(SDNode *N) { 6416 std::vector<SDNode*> Built; 6417 SDValue S = TLI.BuildSDIV(N, DAG, &Built); 6418 6419 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 6420 ii != ee; ++ii) 6421 AddToWorkList(*ii); 6422 return S; 6423} 6424 6425/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 6426/// return a DAG expression to select that will generate the same value by 6427/// multiplying by a magic number. See: 6428/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 6429SDValue DAGCombiner::BuildUDIV(SDNode *N) { 6430 std::vector<SDNode*> Built; 6431 SDValue S = TLI.BuildUDIV(N, DAG, &Built); 6432 6433 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 6434 ii != ee; ++ii) 6435 AddToWorkList(*ii); 6436 return S; 6437} 6438 6439/// FindBaseOffset - Return true if base is a frame index, which is known not 6440// to alias with anything but itself. Provides base object and offset as results. 6441static bool FindBaseOffset(SDValue Ptr, SDValue &Base, int64_t &Offset, 6442 const GlobalValue *&GV, void *&CV) { 6443 // Assume it is a primitive operation. 6444 Base = Ptr; Offset = 0; GV = 0; CV = 0; 6445 6446 // If it's an adding a simple constant then integrate the offset. 6447 if (Base.getOpcode() == ISD::ADD) { 6448 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) { 6449 Base = Base.getOperand(0); 6450 Offset += C->getZExtValue(); 6451 } 6452 } 6453 6454 // Return the underlying GlobalValue, and update the Offset. Return false 6455 // for GlobalAddressSDNode since the same GlobalAddress may be represented 6456 // by multiple nodes with different offsets. 6457 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Base)) { 6458 GV = G->getGlobal(); 6459 Offset += G->getOffset(); 6460 return false; 6461 } 6462 6463 // Return the underlying Constant value, and update the Offset. Return false 6464 // for ConstantSDNodes since the same constant pool entry may be represented 6465 // by multiple nodes with different offsets. 6466 if (ConstantPoolSDNode *C = dyn_cast<ConstantPoolSDNode>(Base)) { 6467 CV = C->isMachineConstantPoolEntry() ? (void *)C->getMachineCPVal() 6468 : (void *)C->getConstVal(); 6469 Offset += C->getOffset(); 6470 return false; 6471 } 6472 // If it's any of the following then it can't alias with anything but itself. 6473 return isa<FrameIndexSDNode>(Base); 6474} 6475 6476/// isAlias - Return true if there is any possibility that the two addresses 6477/// overlap. 6478bool DAGCombiner::isAlias(SDValue Ptr1, int64_t Size1, 6479 const Value *SrcValue1, int SrcValueOffset1, 6480 unsigned SrcValueAlign1, 6481 SDValue Ptr2, int64_t Size2, 6482 const Value *SrcValue2, int SrcValueOffset2, 6483 unsigned SrcValueAlign2) const { 6484 // If they are the same then they must be aliases. 6485 if (Ptr1 == Ptr2) return true; 6486 6487 // Gather base node and offset information. 6488 SDValue Base1, Base2; 6489 int64_t Offset1, Offset2; 6490 const GlobalValue *GV1, *GV2; 6491 void *CV1, *CV2; 6492 bool isFrameIndex1 = FindBaseOffset(Ptr1, Base1, Offset1, GV1, CV1); 6493 bool isFrameIndex2 = FindBaseOffset(Ptr2, Base2, Offset2, GV2, CV2); 6494 6495 // If they have a same base address then check to see if they overlap. 6496 if (Base1 == Base2 || (GV1 && (GV1 == GV2)) || (CV1 && (CV1 == CV2))) 6497 return !((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1); 6498 6499 // If we know what the bases are, and they aren't identical, then we know they 6500 // cannot alias. 6501 if ((isFrameIndex1 || CV1 || GV1) && (isFrameIndex2 || CV2 || GV2)) 6502 return false; 6503 6504 // If we know required SrcValue1 and SrcValue2 have relatively large alignment 6505 // compared to the size and offset of the access, we may be able to prove they 6506 // do not alias. This check is conservative for now to catch cases created by 6507 // splitting vector types. 6508 if ((SrcValueAlign1 == SrcValueAlign2) && 6509 (SrcValueOffset1 != SrcValueOffset2) && 6510 (Size1 == Size2) && (SrcValueAlign1 > Size1)) { 6511 int64_t OffAlign1 = SrcValueOffset1 % SrcValueAlign1; 6512 int64_t OffAlign2 = SrcValueOffset2 % SrcValueAlign1; 6513 6514 // There is no overlap between these relatively aligned accesses of similar 6515 // size, return no alias. 6516 if ((OffAlign1 + Size1) <= OffAlign2 || (OffAlign2 + Size2) <= OffAlign1) 6517 return false; 6518 } 6519 6520 if (CombinerGlobalAA) { 6521 // Use alias analysis information. 6522 int64_t MinOffset = std::min(SrcValueOffset1, SrcValueOffset2); 6523 int64_t Overlap1 = Size1 + SrcValueOffset1 - MinOffset; 6524 int64_t Overlap2 = Size2 + SrcValueOffset2 - MinOffset; 6525 AliasAnalysis::AliasResult AAResult = 6526 AA.alias(SrcValue1, Overlap1, SrcValue2, Overlap2); 6527 if (AAResult == AliasAnalysis::NoAlias) 6528 return false; 6529 } 6530 6531 // Otherwise we have to assume they alias. 6532 return true; 6533} 6534 6535/// FindAliasInfo - Extracts the relevant alias information from the memory 6536/// node. Returns true if the operand was a load. 6537bool DAGCombiner::FindAliasInfo(SDNode *N, 6538 SDValue &Ptr, int64_t &Size, 6539 const Value *&SrcValue, 6540 int &SrcValueOffset, 6541 unsigned &SrcValueAlign) const { 6542 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 6543 Ptr = LD->getBasePtr(); 6544 Size = LD->getMemoryVT().getSizeInBits() >> 3; 6545 SrcValue = LD->getSrcValue(); 6546 SrcValueOffset = LD->getSrcValueOffset(); 6547 SrcValueAlign = LD->getOriginalAlignment(); 6548 return true; 6549 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 6550 Ptr = ST->getBasePtr(); 6551 Size = ST->getMemoryVT().getSizeInBits() >> 3; 6552 SrcValue = ST->getSrcValue(); 6553 SrcValueOffset = ST->getSrcValueOffset(); 6554 SrcValueAlign = ST->getOriginalAlignment(); 6555 } else { 6556 llvm_unreachable("FindAliasInfo expected a memory operand"); 6557 } 6558 6559 return false; 6560} 6561 6562/// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 6563/// looking for aliasing nodes and adding them to the Aliases vector. 6564void DAGCombiner::GatherAllAliases(SDNode *N, SDValue OriginalChain, 6565 SmallVector<SDValue, 8> &Aliases) { 6566 SmallVector<SDValue, 8> Chains; // List of chains to visit. 6567 SmallPtrSet<SDNode *, 16> Visited; // Visited node set. 6568 6569 // Get alias information for node. 6570 SDValue Ptr; 6571 int64_t Size; 6572 const Value *SrcValue; 6573 int SrcValueOffset; 6574 unsigned SrcValueAlign; 6575 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset, 6576 SrcValueAlign); 6577 6578 // Starting off. 6579 Chains.push_back(OriginalChain); 6580 unsigned Depth = 0; 6581 6582 // Look at each chain and determine if it is an alias. If so, add it to the 6583 // aliases list. If not, then continue up the chain looking for the next 6584 // candidate. 6585 while (!Chains.empty()) { 6586 SDValue Chain = Chains.back(); 6587 Chains.pop_back(); 6588 6589 // For TokenFactor nodes, look at each operand and only continue up the 6590 // chain until we find two aliases. If we've seen two aliases, assume we'll 6591 // find more and revert to original chain since the xform is unlikely to be 6592 // profitable. 6593 // 6594 // FIXME: The depth check could be made to return the last non-aliasing 6595 // chain we found before we hit a tokenfactor rather than the original 6596 // chain. 6597 if (Depth > 6 || Aliases.size() == 2) { 6598 Aliases.clear(); 6599 Aliases.push_back(OriginalChain); 6600 break; 6601 } 6602 6603 // Don't bother if we've been before. 6604 if (!Visited.insert(Chain.getNode())) 6605 continue; 6606 6607 switch (Chain.getOpcode()) { 6608 case ISD::EntryToken: 6609 // Entry token is ideal chain operand, but handled in FindBetterChain. 6610 break; 6611 6612 case ISD::LOAD: 6613 case ISD::STORE: { 6614 // Get alias information for Chain. 6615 SDValue OpPtr; 6616 int64_t OpSize; 6617 const Value *OpSrcValue; 6618 int OpSrcValueOffset; 6619 unsigned OpSrcValueAlign; 6620 bool IsOpLoad = FindAliasInfo(Chain.getNode(), OpPtr, OpSize, 6621 OpSrcValue, OpSrcValueOffset, 6622 OpSrcValueAlign); 6623 6624 // If chain is alias then stop here. 6625 if (!(IsLoad && IsOpLoad) && 6626 isAlias(Ptr, Size, SrcValue, SrcValueOffset, SrcValueAlign, 6627 OpPtr, OpSize, OpSrcValue, OpSrcValueOffset, 6628 OpSrcValueAlign)) { 6629 Aliases.push_back(Chain); 6630 } else { 6631 // Look further up the chain. 6632 Chains.push_back(Chain.getOperand(0)); 6633 ++Depth; 6634 } 6635 break; 6636 } 6637 6638 case ISD::TokenFactor: 6639 // We have to check each of the operands of the token factor for "small" 6640 // token factors, so we queue them up. Adding the operands to the queue 6641 // (stack) in reverse order maintains the original order and increases the 6642 // likelihood that getNode will find a matching token factor (CSE.) 6643 if (Chain.getNumOperands() > 16) { 6644 Aliases.push_back(Chain); 6645 break; 6646 } 6647 for (unsigned n = Chain.getNumOperands(); n;) 6648 Chains.push_back(Chain.getOperand(--n)); 6649 ++Depth; 6650 break; 6651 6652 default: 6653 // For all other instructions we will just have to take what we can get. 6654 Aliases.push_back(Chain); 6655 break; 6656 } 6657 } 6658} 6659 6660/// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking 6661/// for a better chain (aliasing node.) 6662SDValue DAGCombiner::FindBetterChain(SDNode *N, SDValue OldChain) { 6663 SmallVector<SDValue, 8> Aliases; // Ops for replacing token factor. 6664 6665 // Accumulate all the aliases to this node. 6666 GatherAllAliases(N, OldChain, Aliases); 6667 6668 if (Aliases.size() == 0) { 6669 // If no operands then chain to entry token. 6670 return DAG.getEntryNode(); 6671 } else if (Aliases.size() == 1) { 6672 // If a single operand then chain to it. We don't need to revisit it. 6673 return Aliases[0]; 6674 } 6675 6676 // Construct a custom tailored token factor. 6677 return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, 6678 &Aliases[0], Aliases.size()); 6679} 6680 6681// SelectionDAG::Combine - This is the entry point for the file. 6682// 6683void SelectionDAG::Combine(CombineLevel Level, AliasAnalysis &AA, 6684 CodeGenOpt::Level OptLevel) { 6685 /// run - This is the main entry point to this class. 6686 /// 6687 DAGCombiner(*this, AA, OptLevel).Run(Level); 6688} 6689