DAGCombiner.cpp revision f98840531a8da37e481a838971abd9ab4ee69eb9 
1//===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file was developed by Nate Begeman and is distributed under the
6// University of Illinois Open Source License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This pass combines dag nodes to form fewer, simpler DAG nodes.  It can be run
11// both before and after the DAG is legalized.
12//
13// FIXME: Missing folds
14// sdiv, udiv, srem, urem (X, const) where X is an integer can be expanded into
15//  a sequence of multiplies, shifts, and adds.  This should be controlled by
16//  some kind of hint from the target that int div is expensive.
17// various folds of mulh[s,u] by constants such as -1, powers of 2, etc.
18//
19// FIXME: Should add a corresponding version of fold AND with
20// ZERO_EXTEND/SIGN_EXTEND by converting them to an ANY_EXTEND node which
21// we don't have yet.
22//
23// FIXME: select C, pow2, pow2 -> something smart
24// FIXME: trunc(select X, Y, Z) -> select X, trunc(Y), trunc(Z)
25// FIXME: (select C, load A, load B) -> load (select C, A, B)
26// FIXME: Dead stores -> nuke
27// FIXME: shr X, (and Y,31) -> shr X, Y
28// FIXME: TRUNC (LOAD)   -> EXT_LOAD/LOAD(smaller)
29// FIXME: mul (x, const) -> shifts + adds
30// FIXME: undef values
31// FIXME: make truncate see through SIGN_EXTEND and AND
32// FIXME: (sra (sra x, c1), c2) -> (sra x, c1+c2)
33// FIXME: verify that getNode can't return extends with an operand whose type
34//        is >= to that of the extend.
35// FIXME: divide by zero is currently left unfolded.  do we want to turn this
36//        into an undef?
37// FIXME: select ne (select cc, 1, 0), 0, true, false -> select cc, true, false
38// FIXME: reassociate (X+C)+Y  into (X+Y)+C  if the inner expression has one use
39//
40//===----------------------------------------------------------------------===//
41
42#define DEBUG_TYPE "dagcombine"
43#include "llvm/ADT/Statistic.h"
44#include "llvm/CodeGen/SelectionDAG.h"
45#include "llvm/Support/Debug.h"
46#include "llvm/Support/MathExtras.h"
47#include "llvm/Target/TargetLowering.h"
48#include <algorithm>
49#include <cmath>
50using namespace llvm;
51
52namespace {
53  Statistic<> NodesCombined ("dagcombiner", "Number of dag nodes combined");
54
55  class DAGCombiner {
56    SelectionDAG &DAG;
57    TargetLowering &TLI;
58    bool AfterLegalize;
59
60    // Worklist of all of the nodes that need to be simplified.
61    std::vector<SDNode*> WorkList;
62
63    /// AddUsersToWorkList - When an instruction is simplified, add all users of
64    /// the instruction to the work lists because they might get more simplified
65    /// now.
66    ///
67    void AddUsersToWorkList(SDNode *N) {
68      for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
69           UI != UE; ++UI)
70        WorkList.push_back(*UI);
71    }
72
73    /// removeFromWorkList - remove all instances of N from the worklist.
74    void removeFromWorkList(SDNode *N) {
75      WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N),
76                     WorkList.end());
77    }
78
79    SDOperand CombineTo(SDNode *N, const std::vector<SDOperand> &To) {
80      ++NodesCombined;
81      DEBUG(std::cerr << "\nReplacing "; N->dump();
82            std::cerr << "\nWith: "; To[0].Val->dump();
83            std::cerr << " and " << To.size()-1 << " other values\n");
84      std::vector<SDNode*> NowDead;
85      DAG.ReplaceAllUsesWith(N, To, &NowDead);
86
87      // Push the new nodes and any users onto the worklist
88      for (unsigned i = 0, e = To.size(); i != e; ++i) {
89        WorkList.push_back(To[i].Val);
90        AddUsersToWorkList(To[i].Val);
91      }
92
93      // Nodes can end up on the worklist more than once.  Make sure we do
94      // not process a node that has been replaced.
95      removeFromWorkList(N);
96      for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
97        removeFromWorkList(NowDead[i]);
98
99      // Finally, since the node is now dead, remove it from the graph.
100      DAG.DeleteNode(N);
101      return SDOperand(N, 0);
102    }
103
104    SDOperand CombineTo(SDNode *N, SDOperand Res) {
105      std::vector<SDOperand> To;
106      To.push_back(Res);
107      return CombineTo(N, To);
108    }
109
110    SDOperand CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1) {
111      std::vector<SDOperand> To;
112      To.push_back(Res0);
113      To.push_back(Res1);
114      return CombineTo(N, To);
115    }
116
117    /// visit - call the node-specific routine that knows how to fold each
118    /// particular type of node.
119    SDOperand visit(SDNode *N);
120
121    // Visitation implementation - Implement dag node combining for different
122    // node types.  The semantics are as follows:
123    // Return Value:
124    //   SDOperand.Val == 0   - No change was made
125    //   SDOperand.Val == N   - N was replaced, is dead, and is already handled.
126    //   otherwise            - N should be replaced by the returned Operand.
127    //
128    SDOperand visitTokenFactor(SDNode *N);
129    SDOperand visitADD(SDNode *N);
130    SDOperand visitSUB(SDNode *N);
131    SDOperand visitMUL(SDNode *N);
132    SDOperand visitSDIV(SDNode *N);
133    SDOperand visitUDIV(SDNode *N);
134    SDOperand visitSREM(SDNode *N);
135    SDOperand visitUREM(SDNode *N);
136    SDOperand visitMULHU(SDNode *N);
137    SDOperand visitMULHS(SDNode *N);
138    SDOperand visitAND(SDNode *N);
139    SDOperand visitOR(SDNode *N);
140    SDOperand visitXOR(SDNode *N);
141    SDOperand visitSHL(SDNode *N);
142    SDOperand visitSRA(SDNode *N);
143    SDOperand visitSRL(SDNode *N);
144    SDOperand visitCTLZ(SDNode *N);
145    SDOperand visitCTTZ(SDNode *N);
146    SDOperand visitCTPOP(SDNode *N);
147    SDOperand visitSELECT(SDNode *N);
148    SDOperand visitSELECT_CC(SDNode *N);
149    SDOperand visitSETCC(SDNode *N);
150    SDOperand visitSIGN_EXTEND(SDNode *N);
151    SDOperand visitZERO_EXTEND(SDNode *N);
152    SDOperand visitSIGN_EXTEND_INREG(SDNode *N);
153    SDOperand visitTRUNCATE(SDNode *N);
154
155    SDOperand visitFADD(SDNode *N);
156    SDOperand visitFSUB(SDNode *N);
157    SDOperand visitFMUL(SDNode *N);
158    SDOperand visitFDIV(SDNode *N);
159    SDOperand visitFREM(SDNode *N);
160    SDOperand visitSINT_TO_FP(SDNode *N);
161    SDOperand visitUINT_TO_FP(SDNode *N);
162    SDOperand visitFP_TO_SINT(SDNode *N);
163    SDOperand visitFP_TO_UINT(SDNode *N);
164    SDOperand visitFP_ROUND(SDNode *N);
165    SDOperand visitFP_ROUND_INREG(SDNode *N);
166    SDOperand visitFP_EXTEND(SDNode *N);
167    SDOperand visitFNEG(SDNode *N);
168    SDOperand visitFABS(SDNode *N);
169    SDOperand visitBRCOND(SDNode *N);
170    SDOperand visitBRCONDTWOWAY(SDNode *N);
171    SDOperand visitBR_CC(SDNode *N);
172    SDOperand visitBRTWOWAY_CC(SDNode *N);
173
174    SDOperand visitLOAD(SDNode *N);
175    SDOperand visitSTORE(SDNode *N);
176
177    SDOperand SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2);
178    SDOperand SimplifySelectCC(SDOperand N0, SDOperand N1, SDOperand N2,
179                               SDOperand N3, ISD::CondCode CC);
180    SDOperand SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1,
181                            ISD::CondCode Cond, bool foldBooleans = true);
182public:
183    DAGCombiner(SelectionDAG &D)
184      : DAG(D), TLI(D.getTargetLoweringInfo()), AfterLegalize(false) {}
185
186    /// Run - runs the dag combiner on all nodes in the work list
187    void Run(bool RunningAfterLegalize);
188  };
189}
190
191/// MaskedValueIsZero - Return true if 'Op & Mask' is known to be zero.  We use
192/// this predicate to simplify operations downstream.  Op and Mask are known to
193/// be the same type.
194static bool MaskedValueIsZero(const SDOperand &Op, uint64_t Mask,
195                              const TargetLowering &TLI) {
196  unsigned SrcBits;
197  if (Mask == 0) return true;
198
199  // If we know the result of a setcc has the top bits zero, use this info.
200  switch (Op.getOpcode()) {
201  case ISD::Constant:
202    return (cast<ConstantSDNode>(Op)->getValue() & Mask) == 0;
203  case ISD::SETCC:
204    return ((Mask & 1) == 0) &&
205    TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult;
206  case ISD::ZEXTLOAD:
207    SrcBits = MVT::getSizeInBits(cast<VTSDNode>(Op.getOperand(3))->getVT());
208    return (Mask & ((1ULL << SrcBits)-1)) == 0; // Returning only the zext bits.
209  case ISD::ZERO_EXTEND:
210    SrcBits = MVT::getSizeInBits(Op.getOperand(0).getValueType());
211    return MaskedValueIsZero(Op.getOperand(0),Mask & ((1ULL << SrcBits)-1),TLI);
212  case ISD::AssertZext:
213    SrcBits = MVT::getSizeInBits(cast<VTSDNode>(Op.getOperand(1))->getVT());
214    return (Mask & ((1ULL << SrcBits)-1)) == 0; // Returning only the zext bits.
215  case ISD::AND:
216    // If either of the operands has zero bits, the result will too.
217    if (MaskedValueIsZero(Op.getOperand(1), Mask, TLI) ||
218        MaskedValueIsZero(Op.getOperand(0), Mask, TLI))
219      return true;
220    // (X & C1) & C2 == 0   iff   C1 & C2 == 0.
221    if (ConstantSDNode *AndRHS = dyn_cast<ConstantSDNode>(Op.getOperand(1)))
222      return MaskedValueIsZero(Op.getOperand(0),AndRHS->getValue() & Mask, TLI);
223    return false;
224  case ISD::OR:
225  case ISD::XOR:
226    return MaskedValueIsZero(Op.getOperand(0), Mask, TLI) &&
227    MaskedValueIsZero(Op.getOperand(1), Mask, TLI);
228  case ISD::SELECT:
229    return MaskedValueIsZero(Op.getOperand(1), Mask, TLI) &&
230    MaskedValueIsZero(Op.getOperand(2), Mask, TLI);
231  case ISD::SELECT_CC:
232    return MaskedValueIsZero(Op.getOperand(2), Mask, TLI) &&
233    MaskedValueIsZero(Op.getOperand(3), Mask, TLI);
234  case ISD::SRL:
235    // (ushr X, C1) & C2 == 0   iff  X & (C2 << C1) == 0
236    if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
237      uint64_t NewVal = Mask << ShAmt->getValue();
238      SrcBits = MVT::getSizeInBits(Op.getValueType());
239      if (SrcBits != 64) NewVal &= (1ULL << SrcBits)-1;
240      return MaskedValueIsZero(Op.getOperand(0), NewVal, TLI);
241    }
242    return false;
243  case ISD::SHL:
244    // (ushl X, C1) & C2 == 0   iff  X & (C2 >> C1) == 0
245    if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
246      uint64_t NewVal = Mask >> ShAmt->getValue();
247      return MaskedValueIsZero(Op.getOperand(0), NewVal, TLI);
248    }
249    return false;
250  case ISD::ADD:
251    // (add X, Y) & C == 0 iff (X&C)|(Y&C) == 0 and all bits are low bits.
252    if ((Mask&(Mask+1)) == 0) {  // All low bits
253      if (MaskedValueIsZero(Op.getOperand(0), Mask, TLI) &&
254          MaskedValueIsZero(Op.getOperand(1), Mask, TLI))
255        return true;
256    }
257    break;
258  case ISD::SUB:
259    if (ConstantSDNode *CLHS = dyn_cast<ConstantSDNode>(Op.getOperand(0))) {
260      // We know that the top bits of C-X are clear if X contains less bits
261      // than C (i.e. no wrap-around can happen).  For example, 20-X is
262      // positive if we can prove that X is >= 0 and < 16.
263      unsigned Bits = MVT::getSizeInBits(CLHS->getValueType(0));
264      if ((CLHS->getValue() & (1 << (Bits-1))) == 0) {  // sign bit clear
265        unsigned NLZ = CountLeadingZeros_64(CLHS->getValue()+1);
266        uint64_t MaskV = (1ULL << (63-NLZ))-1;
267        if (MaskedValueIsZero(Op.getOperand(1), ~MaskV, TLI)) {
268          // High bits are clear this value is known to be >= C.
269          unsigned NLZ2 = CountLeadingZeros_64(CLHS->getValue());
270          if ((Mask & ((1ULL << (64-NLZ2))-1)) == 0)
271            return true;
272        }
273      }
274    }
275    break;
276  case ISD::CTTZ:
277  case ISD::CTLZ:
278  case ISD::CTPOP:
279    // Bit counting instructions can not set the high bits of the result
280    // register.  The max number of bits sets depends on the input.
281    return (Mask & (MVT::getSizeInBits(Op.getValueType())*2-1)) == 0;
282  default: break;
283  }
284  return false;
285}
286
287// isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc
288// that selects between the values 1 and 0, making it equivalent to a setcc.
289// Also, set the incoming LHS, RHS, and CC references to the appropriate
290// nodes based on the type of node we are checking.  This simplifies life a
291// bit for the callers.
292static bool isSetCCEquivalent(SDOperand N, SDOperand &LHS, SDOperand &RHS,
293                              SDOperand &CC) {
294  if (N.getOpcode() == ISD::SETCC) {
295    LHS = N.getOperand(0);
296    RHS = N.getOperand(1);
297    CC  = N.getOperand(2);
298    return true;
299  }
300  if (N.getOpcode() == ISD::SELECT_CC &&
301      N.getOperand(2).getOpcode() == ISD::Constant &&
302      N.getOperand(3).getOpcode() == ISD::Constant &&
303      cast<ConstantSDNode>(N.getOperand(2))->getValue() == 1 &&
304      cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) {
305    LHS = N.getOperand(0);
306    RHS = N.getOperand(1);
307    CC  = N.getOperand(4);
308    return true;
309  }
310  return false;
311}
312
313// isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only
314// one use.  If this is true, it allows the users to invert the operation for
315// free when it is profitable to do so.
316static bool isOneUseSetCC(SDOperand N) {
317  SDOperand N0, N1, N2;
318  if (isSetCCEquivalent(N, N0, N1, N2) && N.Val->hasOneUse())
319    return true;
320  return false;
321}
322
323// FIXME: This should probably go in the ISD class rather than being duplicated
324// in several files.
325static bool isCommutativeBinOp(unsigned Opcode) {
326  switch (Opcode) {
327    case ISD::ADD:
328    case ISD::MUL:
329    case ISD::AND:
330    case ISD::OR:
331    case ISD::XOR: return true;
332    default: return false; // FIXME: Need commutative info for user ops!
333  }
334}
335
336void DAGCombiner::Run(bool RunningAfterLegalize) {
337  // set the instance variable, so that the various visit routines may use it.
338  AfterLegalize = RunningAfterLegalize;
339
340  // Add all the dag nodes to the worklist.
341  WorkList.insert(WorkList.end(), DAG.allnodes_begin(), DAG.allnodes_end());
342
343  // Create a dummy node (which is not added to allnodes), that adds a reference
344  // to the root node, preventing it from being deleted, and tracking any
345  // changes of the root.
346  HandleSDNode Dummy(DAG.getRoot());
347
348  // while the worklist isn't empty, inspect the node on the end of it and
349  // try and combine it.
350  while (!WorkList.empty()) {
351    SDNode *N = WorkList.back();
352    WorkList.pop_back();
353
354    // If N has no uses, it is dead.  Make sure to revisit all N's operands once
355    // N is deleted from the DAG, since they too may now be dead or may have a
356    // reduced number of uses, allowing other xforms.
357    if (N->use_empty() && N != &Dummy) {
358      for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
359        WorkList.push_back(N->getOperand(i).Val);
360
361      removeFromWorkList(N);
362      DAG.DeleteNode(N);
363      continue;
364    }
365
366    SDOperand RV = visit(N);
367    if (RV.Val) {
368      ++NodesCombined;
369      // If we get back the same node we passed in, rather than a new node or
370      // zero, we know that the node must have defined multiple values and
371      // CombineTo was used.  Since CombineTo takes care of the worklist
372      // mechanics for us, we have no work to do in this case.
373      if (RV.Val != N) {
374        DEBUG(std::cerr << "\nReplacing "; N->dump();
375              std::cerr << "\nWith: "; RV.Val->dump();
376              std::cerr << '\n');
377        std::vector<SDNode*> NowDead;
378        DAG.ReplaceAllUsesWith(N, std::vector<SDOperand>(1, RV), &NowDead);
379
380        // Push the new node and any users onto the worklist
381        WorkList.push_back(RV.Val);
382        AddUsersToWorkList(RV.Val);
383
384        // Nodes can end up on the worklist more than once.  Make sure we do
385        // not process a node that has been replaced.
386        removeFromWorkList(N);
387        for (unsigned i = 0, e = NowDead.size(); i != e; ++i)
388          removeFromWorkList(NowDead[i]);
389
390        // Finally, since the node is now dead, remove it from the graph.
391        DAG.DeleteNode(N);
392      }
393    }
394  }
395
396  // If the root changed (e.g. it was a dead load, update the root).
397  DAG.setRoot(Dummy.getValue());
398}
399
400SDOperand DAGCombiner::visit(SDNode *N) {
401  switch(N->getOpcode()) {
402  default: break;
403  case ISD::TokenFactor:        return visitTokenFactor(N);
404  case ISD::ADD:                return visitADD(N);
405  case ISD::SUB:                return visitSUB(N);
406  case ISD::MUL:                return visitMUL(N);
407  case ISD::SDIV:               return visitSDIV(N);
408  case ISD::UDIV:               return visitUDIV(N);
409  case ISD::SREM:               return visitSREM(N);
410  case ISD::UREM:               return visitUREM(N);
411  case ISD::MULHU:              return visitMULHU(N);
412  case ISD::MULHS:              return visitMULHS(N);
413  case ISD::AND:                return visitAND(N);
414  case ISD::OR:                 return visitOR(N);
415  case ISD::XOR:                return visitXOR(N);
416  case ISD::SHL:                return visitSHL(N);
417  case ISD::SRA:                return visitSRA(N);
418  case ISD::SRL:                return visitSRL(N);
419  case ISD::CTLZ:               return visitCTLZ(N);
420  case ISD::CTTZ:               return visitCTTZ(N);
421  case ISD::CTPOP:              return visitCTPOP(N);
422  case ISD::SELECT:             return visitSELECT(N);
423  case ISD::SELECT_CC:          return visitSELECT_CC(N);
424  case ISD::SETCC:              return visitSETCC(N);
425  case ISD::SIGN_EXTEND:        return visitSIGN_EXTEND(N);
426  case ISD::ZERO_EXTEND:        return visitZERO_EXTEND(N);
427  case ISD::SIGN_EXTEND_INREG:  return visitSIGN_EXTEND_INREG(N);
428  case ISD::TRUNCATE:           return visitTRUNCATE(N);
429  case ISD::FADD:               return visitFADD(N);
430  case ISD::FSUB:               return visitFSUB(N);
431  case ISD::FMUL:               return visitFMUL(N);
432  case ISD::FDIV:               return visitFDIV(N);
433  case ISD::FREM:               return visitFREM(N);
434  case ISD::SINT_TO_FP:         return visitSINT_TO_FP(N);
435  case ISD::UINT_TO_FP:         return visitUINT_TO_FP(N);
436  case ISD::FP_TO_SINT:         return visitFP_TO_SINT(N);
437  case ISD::FP_TO_UINT:         return visitFP_TO_UINT(N);
438  case ISD::FP_ROUND:           return visitFP_ROUND(N);
439  case ISD::FP_ROUND_INREG:     return visitFP_ROUND_INREG(N);
440  case ISD::FP_EXTEND:          return visitFP_EXTEND(N);
441  case ISD::FNEG:               return visitFNEG(N);
442  case ISD::FABS:               return visitFABS(N);
443  case ISD::BRCOND:             return visitBRCOND(N);
444  case ISD::BRCONDTWOWAY:       return visitBRCONDTWOWAY(N);
445  case ISD::BR_CC:              return visitBR_CC(N);
446  case ISD::BRTWOWAY_CC:        return visitBRTWOWAY_CC(N);
447  case ISD::LOAD:               return visitLOAD(N);
448  case ISD::STORE:              return visitSTORE(N);
449  }
450  return SDOperand();
451}
452
453SDOperand DAGCombiner::visitTokenFactor(SDNode *N) {
454  std::vector<SDOperand> Ops;
455  bool Changed = false;
456
457  // If the token factor has two operands and one is the entry token, replace
458  // the token factor with the other operand.
459  if (N->getNumOperands() == 2) {
460    if (N->getOperand(0).getOpcode() == ISD::EntryToken)
461      return N->getOperand(1);
462    if (N->getOperand(1).getOpcode() == ISD::EntryToken)
463      return N->getOperand(0);
464  }
465  // fold (tokenfactor (tokenfactor)) -> tokenfactor
466  for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
467    SDOperand Op = N->getOperand(i);
468    if (Op.getOpcode() == ISD::TokenFactor && Op.hasOneUse()) {
469      Changed = true;
470      for (unsigned j = 0, e = Op.getNumOperands(); j != e; ++j)
471        Ops.push_back(Op.getOperand(j));
472    } else {
473      Ops.push_back(Op);
474    }
475  }
476  if (Changed)
477    return DAG.getNode(ISD::TokenFactor, MVT::Other, Ops);
478  return SDOperand();
479}
480
481SDOperand DAGCombiner::visitADD(SDNode *N) {
482  SDOperand N0 = N->getOperand(0);
483  SDOperand N1 = N->getOperand(1);
484  ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
485  ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
486  MVT::ValueType VT = N0.getValueType();
487
488  // fold (add c1, c2) -> c1+c2
489  if (N0C && N1C)
490    return DAG.getConstant(N0C->getValue() + N1C->getValue(), VT);
491  // canonicalize constant to RHS
492  if (N0C && !N1C) {
493    std::swap(N0, N1);
494    std::swap(N0C, N1C);
495  }
496  // fold (add x, 0) -> x
497  if (N1C && N1C->isNullValue())
498    return N0;
499  // fold (add (add x, c1), c2) -> (add x, c1+c2)
500  if (N1C && N0.getOpcode() == ISD::ADD) {
501    ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0));
502    ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
503    if (N00C)
504      return DAG.getNode(ISD::ADD, VT, N0.getOperand(1),
505                         DAG.getConstant(N1C->getValue()+N00C->getValue(), VT));
506    if (N01C)
507      return DAG.getNode(ISD::ADD, VT, N0.getOperand(0),
508                         DAG.getConstant(N1C->getValue()+N01C->getValue(), VT));
509  }
510  // fold ((0-A) + B) -> B-A
511  if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) &&
512      cast<ConstantSDNode>(N0.getOperand(0))->isNullValue())
513    return DAG.getNode(ISD::SUB, VT, N1, N0.getOperand(1));
514  // fold (A + (0-B)) -> A-B
515  if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) &&
516      cast<ConstantSDNode>(N1.getOperand(0))->isNullValue())
517    return DAG.getNode(ISD::SUB, VT, N0, N1.getOperand(1));
518  // fold (A+(B-A)) -> B
519  if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1))
520    return N1.getOperand(0);
521  return SDOperand();
522}
523
524SDOperand DAGCombiner::visitSUB(SDNode *N) {
525  SDOperand N0 = N->getOperand(0);
526  SDOperand N1 = N->getOperand(1);
527  ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
528  ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
529
530  // fold (sub c1, c2) -> c1-c2
531  if (N0C && N1C)
532    return DAG.getConstant(N0C->getValue() - N1C->getValue(),
533                           N->getValueType(0));
534  // fold (sub x, c) -> (add x, -c)
535  if (N1C)
536    return DAG.getNode(ISD::ADD, N0.getValueType(), N0,
537                       DAG.getConstant(-N1C->getValue(), N0.getValueType()));
538
539  // fold (A+B)-A -> B
540  if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1)
541    return N0.getOperand(1);
542  // fold (A+B)-B -> A
543  if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1)
544    return N0.getOperand(0);
545  return SDOperand();
546}
547
548SDOperand DAGCombiner::visitMUL(SDNode *N) {
549  SDOperand N0 = N->getOperand(0);
550  SDOperand N1 = N->getOperand(1);
551  ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
552  ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
553  MVT::ValueType VT = N0.getValueType();
554
555  // fold (mul c1, c2) -> c1*c2
556  if (N0C && N1C)
557    return DAG.getConstant(N0C->getValue() * N1C->getValue(),
558                           N->getValueType(0));
559  // canonicalize constant to RHS
560  if (N0C && !N1C) {
561    std::swap(N0, N1);
562    std::swap(N0C, N1C);
563  }
564  // fold (mul x, 0) -> 0
565  if (N1C && N1C->isNullValue())
566    return N1;
567  // fold (mul x, -1) -> 0-x
568  if (N1C && N1C->isAllOnesValue())
569    return DAG.getNode(ISD::SUB, N->getValueType(0),
570                       DAG.getConstant(0, N->getValueType(0)), N0);
571  // fold (mul x, (1 << c)) -> x << c
572  if (N1C && isPowerOf2_64(N1C->getValue()))
573    return DAG.getNode(ISD::SHL, N->getValueType(0), N0,
574                       DAG.getConstant(Log2_64(N1C->getValue()),
575                                       TLI.getShiftAmountTy()));
576  // fold (mul (mul x, c1), c2) -> (mul x, c1*c2)
577  if (N1C && N0.getOpcode() == ISD::MUL) {
578    ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0));
579    ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
580    if (N00C)
581      return DAG.getNode(ISD::MUL, VT, N0.getOperand(1),
582                         DAG.getConstant(N1C->getValue()*N00C->getValue(), VT));
583    if (N01C)
584      return DAG.getNode(ISD::MUL, VT, N0.getOperand(0),
585                         DAG.getConstant(N1C->getValue()*N01C->getValue(), VT));
586  }
587  return SDOperand();
588}
589
590SDOperand DAGCombiner::visitSDIV(SDNode *N) {
591  SDOperand N0 = N->getOperand(0);
592  SDOperand N1 = N->getOperand(1);
593  MVT::ValueType VT = N->getValueType(0);
594  ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
595  ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
596
597  // fold (sdiv c1, c2) -> c1/c2
598  if (N0C && N1C && !N1C->isNullValue())
599    return DAG.getConstant(N0C->getSignExtended() / N1C->getSignExtended(),
600                           N->getValueType(0));
601  // If we know the sign bits of both operands are zero, strength reduce to a
602  // udiv instead.  Handles (X&15) /s 4 -> X&15 >> 2
603  uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1);
604  if (MaskedValueIsZero(N1, SignBit, TLI) &&
605      MaskedValueIsZero(N0, SignBit, TLI))
606    return DAG.getNode(ISD::UDIV, N1.getValueType(), N0, N1);
607  return SDOperand();
608}
609
610SDOperand DAGCombiner::visitUDIV(SDNode *N) {
611  SDOperand N0 = N->getOperand(0);
612  SDOperand N1 = N->getOperand(1);
613  ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
614  ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
615
616  // fold (udiv c1, c2) -> c1/c2
617  if (N0C && N1C && !N1C->isNullValue())
618    return DAG.getConstant(N0C->getValue() / N1C->getValue(),
619                           N->getValueType(0));
620  // fold (udiv x, (1 << c)) -> x >>u c
621  if (N1C && isPowerOf2_64(N1C->getValue()))
622    return DAG.getNode(ISD::SRL, N->getValueType(0), N0,
623                       DAG.getConstant(Log2_64(N1C->getValue()),
624                                       TLI.getShiftAmountTy()));
625  return SDOperand();
626}
627
628SDOperand DAGCombiner::visitSREM(SDNode *N) {
629  SDOperand N0 = N->getOperand(0);
630  SDOperand N1 = N->getOperand(1);
631  MVT::ValueType VT = N->getValueType(0);
632  ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
633  ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
634
635  // fold (srem c1, c2) -> c1%c2
636  if (N0C && N1C && !N1C->isNullValue())
637    return DAG.getConstant(N0C->getSignExtended() % N1C->getSignExtended(),
638                           N->getValueType(0));
639  // If we know the sign bits of both operands are zero, strength reduce to a
640  // urem instead.  Handles (X & 0x0FFFFFFF) %s 16 -> X&15
641  uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1);
642  if (MaskedValueIsZero(N1, SignBit, TLI) &&
643      MaskedValueIsZero(N0, SignBit, TLI))
644    return DAG.getNode(ISD::UREM, N1.getValueType(), N0, N1);
645  return SDOperand();
646}
647
648SDOperand DAGCombiner::visitUREM(SDNode *N) {
649  SDOperand N0 = N->getOperand(0);
650  SDOperand N1 = N->getOperand(1);
651  ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
652  ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
653
654  // fold (urem c1, c2) -> c1%c2
655  if (N0C && N1C && !N1C->isNullValue())
656    return DAG.getConstant(N0C->getValue() % N1C->getValue(),
657                           N->getValueType(0));
658  // fold (urem x, pow2) -> (and x, pow2-1)
659  if (N1C && !N1C->isNullValue() && isPowerOf2_64(N1C->getValue()))
660    return DAG.getNode(ISD::AND, N0.getValueType(), N0,
661                       DAG.getConstant(N1C->getValue()-1, N1.getValueType()));
662  return SDOperand();
663}
664
665SDOperand DAGCombiner::visitMULHS(SDNode *N) {
666  SDOperand N0 = N->getOperand(0);
667  SDOperand N1 = N->getOperand(1);
668  ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
669
670  // fold (mulhs x, 0) -> 0
671  if (N1C && N1C->isNullValue())
672    return N1;
673  // fold (mulhs x, 1) -> (sra x, size(x)-1)
674  if (N1C && N1C->getValue() == 1)
675    return DAG.getNode(ISD::SRA, N0.getValueType(), N0,
676                       DAG.getConstant(MVT::getSizeInBits(N0.getValueType())-1,
677                                       TLI.getShiftAmountTy()));
678  return SDOperand();
679}
680
681SDOperand DAGCombiner::visitMULHU(SDNode *N) {
682  SDOperand N0 = N->getOperand(0);
683  SDOperand N1 = N->getOperand(1);
684  ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
685
686  // fold (mulhu x, 0) -> 0
687  if (N1C && N1C->isNullValue())
688    return N1;
689  // fold (mulhu x, 1) -> 0
690  if (N1C && N1C->getValue() == 1)
691    return DAG.getConstant(0, N0.getValueType());
692  return SDOperand();
693}
694
695SDOperand DAGCombiner::visitAND(SDNode *N) {
696  SDOperand N0 = N->getOperand(0);
697  SDOperand N1 = N->getOperand(1);
698  SDOperand LL, LR, RL, RR, CC0, CC1;
699  ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
700  ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
701  MVT::ValueType VT = N1.getValueType();
702  unsigned OpSizeInBits = MVT::getSizeInBits(VT);
703
704  // fold (and c1, c2) -> c1&c2
705  if (N0C && N1C)
706    return DAG.getConstant(N0C->getValue() & N1C->getValue(), VT);
707  // canonicalize constant to RHS
708  if (N0C && !N1C) {
709    std::swap(N0, N1);
710    std::swap(N0C, N1C);
711  }
712  // fold (and x, -1) -> x
713  if (N1C && N1C->isAllOnesValue())
714    return N0;
715  // if (and x, c) is known to be zero, return 0
716  if (N1C && MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits),TLI))
717    return DAG.getConstant(0, VT);
718  // fold (and x, c) -> x iff (x & ~c) == 0
719  if (N1C && MaskedValueIsZero(N0,~N1C->getValue() & (~0ULL>>(64-OpSizeInBits)),
720                               TLI))
721    return N0;
722  // fold (and (and x, c1), c2) -> (and x, c1^c2)
723  if (N1C && N0.getOpcode() == ISD::AND) {
724    ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0));
725    ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
726    if (N00C)
727      return DAG.getNode(ISD::AND, VT, N0.getOperand(1),
728                         DAG.getConstant(N1C->getValue()&N00C->getValue(), VT));
729    if (N01C)
730      return DAG.getNode(ISD::AND, VT, N0.getOperand(0),
731                         DAG.getConstant(N1C->getValue()&N01C->getValue(), VT));
732  }
733  // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1)
734  if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG) {
735    unsigned ExtendBits =
736    MVT::getSizeInBits(cast<VTSDNode>(N0.getOperand(1))->getVT());
737    if ((N1C->getValue() & (~0ULL << ExtendBits)) == 0)
738      return DAG.getNode(ISD::AND, VT, N0.getOperand(0), N1);
739  }
740  // fold (and (or x, 0xFFFF), 0xFF) -> 0xFF
741  if (N0.getOpcode() == ISD::OR && N1C)
742    if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
743      if ((ORI->getValue() & N1C->getValue()) == N1C->getValue())
744        return N1;
745  // fold (and (setcc x), (setcc y)) -> (setcc (and x, y))
746  if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
747    ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
748    ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
749
750    if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
751        MVT::isInteger(LL.getValueType())) {
752      // fold (X == 0) & (Y == 0) -> (X|Y == 0)
753      if (cast<ConstantSDNode>(LR)->getValue() == 0 && Op1 == ISD::SETEQ) {
754        SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
755        WorkList.push_back(ORNode.Val);
756        return DAG.getSetCC(VT, ORNode, LR, Op1);
757      }
758      // fold (X == -1) & (Y == -1) -> (X&Y == -1)
759      if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) {
760        SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL);
761        WorkList.push_back(ANDNode.Val);
762        return DAG.getSetCC(VT, ANDNode, LR, Op1);
763      }
764      // fold (X >  -1) & (Y >  -1) -> (X|Y > -1)
765      if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) {
766        SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
767        WorkList.push_back(ORNode.Val);
768        return DAG.getSetCC(VT, ORNode, LR, Op1);
769      }
770    }
771    // canonicalize equivalent to ll == rl
772    if (LL == RR && LR == RL) {
773      Op1 = ISD::getSetCCSwappedOperands(Op1);
774      std::swap(RL, RR);
775    }
776    if (LL == RL && LR == RR) {
777      bool isInteger = MVT::isInteger(LL.getValueType());
778      ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger);
779      if (Result != ISD::SETCC_INVALID)
780        return DAG.getSetCC(N0.getValueType(), LL, LR, Result);
781    }
782  }
783  // fold (and (zext x), (zext y)) -> (zext (and x, y))
784  if (N0.getOpcode() == ISD::ZERO_EXTEND &&
785      N1.getOpcode() == ISD::ZERO_EXTEND &&
786      N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) {
787    SDOperand ANDNode = DAG.getNode(ISD::AND, N0.getOperand(0).getValueType(),
788                                    N0.getOperand(0), N1.getOperand(0));
789    WorkList.push_back(ANDNode.Val);
790    return DAG.getNode(ISD::ZERO_EXTEND, VT, ANDNode);
791  }
792  // fold (and (shl/srl x), (shl/srl y)) -> (shl/srl (and x, y))
793  if (((N0.getOpcode() == ISD::SHL && N1.getOpcode() == ISD::SHL) ||
794       (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SRL)) &&
795      N0.getOperand(1) == N1.getOperand(1)) {
796    SDOperand ANDNode = DAG.getNode(ISD::AND, N0.getOperand(0).getValueType(),
797                                    N0.getOperand(0), N1.getOperand(0));
798    WorkList.push_back(ANDNode.Val);
799    return DAG.getNode(N0.getOpcode(), VT, ANDNode, N0.getOperand(1));
800  }
801  // fold (zext_inreg (extload x)) -> (zextload x)
802  if (N1C && N0.getOpcode() == ISD::EXTLOAD) {
803    MVT::ValueType EVT = cast<VTSDNode>(N0.getOperand(3))->getVT();
804    // If we zero all the possible extended bits, then we can turn this into
805    // a zextload if we are running before legalize or the operation is legal.
806    if (MaskedValueIsZero(SDOperand(N,0), ~0ULL<<MVT::getSizeInBits(EVT),TLI) &&
807        (!AfterLegalize || TLI.isOperationLegal(ISD::ZEXTLOAD, EVT))) {
808      SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0),
809                                         N0.getOperand(1), N0.getOperand(2),
810                                         EVT);
811      WorkList.push_back(N);
812      CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
813      return SDOperand();
814    }
815  }
816  // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use
817  if (N1C && N0.getOpcode() == ISD::SEXTLOAD && N0.Val->hasNUsesOfValue(1, 0)) {
818    MVT::ValueType EVT = cast<VTSDNode>(N0.getOperand(3))->getVT();
819    // If we zero all the possible extended bits, then we can turn this into
820    // a zextload if we are running before legalize or the operation is legal.
821    if (MaskedValueIsZero(SDOperand(N,0), ~0ULL<<MVT::getSizeInBits(EVT),TLI) &&
822        (!AfterLegalize || TLI.isOperationLegal(ISD::ZEXTLOAD, EVT))) {
823      SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0),
824                                         N0.getOperand(1), N0.getOperand(2),
825                                         EVT);
826      WorkList.push_back(N);
827      CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
828      return SDOperand();
829    }
830  }
831  return SDOperand();
832}
833
834SDOperand DAGCombiner::visitOR(SDNode *N) {
835  SDOperand N0 = N->getOperand(0);
836  SDOperand N1 = N->getOperand(1);
837  SDOperand LL, LR, RL, RR, CC0, CC1;
838  ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
839  ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
840  MVT::ValueType VT = N1.getValueType();
841  unsigned OpSizeInBits = MVT::getSizeInBits(VT);
842
843  // fold (or c1, c2) -> c1|c2
844  if (N0C && N1C)
845    return DAG.getConstant(N0C->getValue() | N1C->getValue(),
846                           N->getValueType(0));
847  // canonicalize constant to RHS
848  if (N0C && !N1C) {
849    std::swap(N0, N1);
850    std::swap(N0C, N1C);
851  }
852  // fold (or x, 0) -> x
853  if (N1C && N1C->isNullValue())
854    return N0;
855  // fold (or x, -1) -> -1
856  if (N1C && N1C->isAllOnesValue())
857    return N1;
858  // fold (or x, c) -> c iff (x & ~c) == 0
859  if (N1C && MaskedValueIsZero(N0,~N1C->getValue() & (~0ULL>>(64-OpSizeInBits)),
860                               TLI))
861    return N1;
862  // fold (or (or x, c1), c2) -> (or x, c1|c2)
863  if (N1C && N0.getOpcode() == ISD::OR) {
864    ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0));
865    ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
866    if (N00C)
867      return DAG.getNode(ISD::OR, VT, N0.getOperand(1),
868                         DAG.getConstant(N1C->getValue()|N00C->getValue(), VT));
869    if (N01C)
870      return DAG.getNode(ISD::OR, VT, N0.getOperand(0),
871                         DAG.getConstant(N1C->getValue()|N01C->getValue(), VT));
872  }
873  // fold (or (setcc x), (setcc y)) -> (setcc (or x, y))
874  if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){
875    ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
876    ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
877
878    if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
879        MVT::isInteger(LL.getValueType())) {
880      // fold (X != 0) | (Y != 0) -> (X|Y != 0)
881      // fold (X <  0) | (Y <  0) -> (X|Y < 0)
882      if (cast<ConstantSDNode>(LR)->getValue() == 0 &&
883          (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) {
884        SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL);
885        WorkList.push_back(ORNode.Val);
886        return DAG.getSetCC(VT, ORNode, LR, Op1);
887      }
888      // fold (X != -1) | (Y != -1) -> (X&Y != -1)
889      // fold (X >  -1) | (Y >  -1) -> (X&Y >  -1)
890      if (cast<ConstantSDNode>(LR)->isAllOnesValue() &&
891          (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) {
892        SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL);
893        WorkList.push_back(ANDNode.Val);
894        return DAG.getSetCC(VT, ANDNode, LR, Op1);
895      }
896    }
897    // canonicalize equivalent to ll == rl
898    if (LL == RR && LR == RL) {
899      Op1 = ISD::getSetCCSwappedOperands(Op1);
900      std::swap(RL, RR);
901    }
902    if (LL == RL && LR == RR) {
903      bool isInteger = MVT::isInteger(LL.getValueType());
904      ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger);
905      if (Result != ISD::SETCC_INVALID)
906        return DAG.getSetCC(N0.getValueType(), LL, LR, Result);
907    }
908  }
909  // fold (or (zext x), (zext y)) -> (zext (or x, y))
910  if (N0.getOpcode() == ISD::ZERO_EXTEND &&
911      N1.getOpcode() == ISD::ZERO_EXTEND &&
912      N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) {
913    SDOperand ORNode = DAG.getNode(ISD::OR, N0.getOperand(0).getValueType(),
914                                   N0.getOperand(0), N1.getOperand(0));
915    WorkList.push_back(ORNode.Val);
916    return DAG.getNode(ISD::ZERO_EXTEND, VT, ORNode);
917  }
918  return SDOperand();
919}
920
921SDOperand DAGCombiner::visitXOR(SDNode *N) {
922  SDOperand N0 = N->getOperand(0);
923  SDOperand N1 = N->getOperand(1);
924  SDOperand LHS, RHS, CC;
925  ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
926  ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
927  MVT::ValueType VT = N0.getValueType();
928
929  // fold (xor c1, c2) -> c1^c2
930  if (N0C && N1C)
931    return DAG.getConstant(N0C->getValue() ^ N1C->getValue(), VT);
932  // canonicalize constant to RHS
933  if (N0C && !N1C) {
934    std::swap(N0, N1);
935    std::swap(N0C, N1C);
936  }
937  // fold (xor x, 0) -> x
938  if (N1C && N1C->isNullValue())
939    return N0;
940  // fold !(x cc y) -> (x !cc y)
941  if (N1C && N1C->getValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) {
942    bool isInt = MVT::isInteger(LHS.getValueType());
943    ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(),
944                                               isInt);
945    if (N0.getOpcode() == ISD::SETCC)
946      return DAG.getSetCC(VT, LHS, RHS, NotCC);
947    if (N0.getOpcode() == ISD::SELECT_CC)
948      return DAG.getSelectCC(LHS, RHS, N0.getOperand(2),N0.getOperand(3),NotCC);
949    assert(0 && "Unhandled SetCC Equivalent!");
950    abort();
951  }
952  // fold !(x or y) -> (!x and !y) iff x or y are setcc
953  if (N1C && N1C->getValue() == 1 &&
954      (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
955    SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1);
956    if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) {
957      unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
958      LHS = DAG.getNode(ISD::XOR, VT, LHS, N1);  // RHS = ~LHS
959      RHS = DAG.getNode(ISD::XOR, VT, RHS, N1);  // RHS = ~RHS
960      WorkList.push_back(LHS.Val); WorkList.push_back(RHS.Val);
961      return DAG.getNode(NewOpcode, VT, LHS, RHS);
962    }
963  }
964  // fold !(x or y) -> (!x and !y) iff x or y are constants
965  if (N1C && N1C->isAllOnesValue() &&
966      (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
967    SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1);
968    if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) {
969      unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
970      LHS = DAG.getNode(ISD::XOR, VT, LHS, N1);  // RHS = ~LHS
971      RHS = DAG.getNode(ISD::XOR, VT, RHS, N1);  // RHS = ~RHS
972      WorkList.push_back(LHS.Val); WorkList.push_back(RHS.Val);
973      return DAG.getNode(NewOpcode, VT, LHS, RHS);
974    }
975  }
976  // fold (xor (xor x, c1), c2) -> (xor x, c1^c2)
977  if (N1C && N0.getOpcode() == ISD::XOR) {
978    ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0));
979    ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
980    if (N00C)
981      return DAG.getNode(ISD::XOR, VT, N0.getOperand(1),
982                         DAG.getConstant(N1C->getValue()^N00C->getValue(), VT));
983    if (N01C)
984      return DAG.getNode(ISD::XOR, VT, N0.getOperand(0),
985                         DAG.getConstant(N1C->getValue()^N01C->getValue(), VT));
986  }
987  // fold (xor x, x) -> 0
988  if (N0 == N1)
989    return DAG.getConstant(0, VT);
990  // fold (xor (zext x), (zext y)) -> (zext (xor x, y))
991  if (N0.getOpcode() == ISD::ZERO_EXTEND &&
992      N1.getOpcode() == ISD::ZERO_EXTEND &&
993      N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) {
994    SDOperand XORNode = DAG.getNode(ISD::XOR, N0.getOperand(0).getValueType(),
995                                   N0.getOperand(0), N1.getOperand(0));
996    WorkList.push_back(XORNode.Val);
997    return DAG.getNode(ISD::ZERO_EXTEND, VT, XORNode);
998  }
999  return SDOperand();
1000}
1001
1002SDOperand DAGCombiner::visitSHL(SDNode *N) {
1003  SDOperand N0 = N->getOperand(0);
1004  SDOperand N1 = N->getOperand(1);
1005  ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1006  ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1007  MVT::ValueType VT = N0.getValueType();
1008  unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1009
1010  // fold (shl c1, c2) -> c1<<c2
1011  if (N0C && N1C)
1012    return DAG.getConstant(N0C->getValue() << N1C->getValue(), VT);
1013  // fold (shl 0, x) -> 0
1014  if (N0C && N0C->isNullValue())
1015    return N0;
1016  // fold (shl x, c >= size(x)) -> undef
1017  if (N1C && N1C->getValue() >= OpSizeInBits)
1018    return DAG.getNode(ISD::UNDEF, VT);
1019  // fold (shl x, 0) -> x
1020  if (N1C && N1C->isNullValue())
1021    return N0;
1022  // if (shl x, c) is known to be zero, return 0
1023  if (N1C && MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits),TLI))
1024    return DAG.getConstant(0, VT);
1025  // fold (shl (shl x, c1), c2) -> 0 or (shl x, c1+c2)
1026  if (N1C && N0.getOpcode() == ISD::SHL &&
1027      N0.getOperand(1).getOpcode() == ISD::Constant) {
1028    uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1029    uint64_t c2 = N1C->getValue();
1030    if (c1 + c2 > OpSizeInBits)
1031      return DAG.getConstant(0, VT);
1032    return DAG.getNode(ISD::SHL, VT, N0.getOperand(0),
1033                       DAG.getConstant(c1 + c2, N1.getValueType()));
1034  }
1035  // fold (shl (srl x, c1), c2) -> (shl (and x, -1 << c1), c2-c1) or
1036  //                               (srl (and x, -1 << c1), c1-c2)
1037  if (N1C && N0.getOpcode() == ISD::SRL &&
1038      N0.getOperand(1).getOpcode() == ISD::Constant) {
1039    uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1040    uint64_t c2 = N1C->getValue();
1041    SDOperand Mask = DAG.getNode(ISD::AND, VT, N0.getOperand(0),
1042                                 DAG.getConstant(~0ULL << c1, VT));
1043    if (c2 > c1)
1044      return DAG.getNode(ISD::SHL, VT, Mask,
1045                         DAG.getConstant(c2-c1, N1.getValueType()));
1046    else
1047      return DAG.getNode(ISD::SRL, VT, Mask,
1048                         DAG.getConstant(c1-c2, N1.getValueType()));
1049  }
1050  // fold (shl (sra x, c1), c1) -> (and x, -1 << c1)
1051  if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1))
1052    return DAG.getNode(ISD::AND, VT, N0.getOperand(0),
1053                       DAG.getConstant(~0ULL << N1C->getValue(), VT));
1054  return SDOperand();
1055}
1056
1057SDOperand DAGCombiner::visitSRA(SDNode *N) {
1058  SDOperand N0 = N->getOperand(0);
1059  SDOperand N1 = N->getOperand(1);
1060  ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1061  ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1062  MVT::ValueType VT = N0.getValueType();
1063  unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1064
1065  // fold (sra c1, c2) -> c1>>c2
1066  if (N0C && N1C)
1067    return DAG.getConstant(N0C->getSignExtended() >> N1C->getValue(), VT);
1068  // fold (sra 0, x) -> 0
1069  if (N0C && N0C->isNullValue())
1070    return N0;
1071  // fold (sra -1, x) -> -1
1072  if (N0C && N0C->isAllOnesValue())
1073    return N0;
1074  // fold (sra x, c >= size(x)) -> undef
1075  if (N1C && N1C->getValue() >= OpSizeInBits)
1076    return DAG.getNode(ISD::UNDEF, VT);
1077  // fold (sra x, 0) -> x
1078  if (N1C && N1C->isNullValue())
1079    return N0;
1080  // If the sign bit is known to be zero, switch this to a SRL.
1081  if (MaskedValueIsZero(N0, (1ULL << (OpSizeInBits-1)), TLI))
1082    return DAG.getNode(ISD::SRL, VT, N0, N1);
1083  return SDOperand();
1084}
1085
1086SDOperand DAGCombiner::visitSRL(SDNode *N) {
1087  SDOperand N0 = N->getOperand(0);
1088  SDOperand N1 = N->getOperand(1);
1089  ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1090  ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1091  MVT::ValueType VT = N0.getValueType();
1092  unsigned OpSizeInBits = MVT::getSizeInBits(VT);
1093
1094  // fold (srl c1, c2) -> c1 >>u c2
1095  if (N0C && N1C)
1096    return DAG.getConstant(N0C->getValue() >> N1C->getValue(), VT);
1097  // fold (srl 0, x) -> 0
1098  if (N0C && N0C->isNullValue())
1099    return N0;
1100  // fold (srl x, c >= size(x)) -> undef
1101  if (N1C && N1C->getValue() >= OpSizeInBits)
1102    return DAG.getNode(ISD::UNDEF, VT);
1103  // fold (srl x, 0) -> x
1104  if (N1C && N1C->isNullValue())
1105    return N0;
1106  // if (srl x, c) is known to be zero, return 0
1107  if (N1C && MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits),TLI))
1108    return DAG.getConstant(0, VT);
1109  // fold (srl (srl x, c1), c2) -> 0 or (srl x, c1+c2)
1110  if (N1C && N0.getOpcode() == ISD::SRL &&
1111      N0.getOperand(1).getOpcode() == ISD::Constant) {
1112    uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue();
1113    uint64_t c2 = N1C->getValue();
1114    if (c1 + c2 > OpSizeInBits)
1115      return DAG.getConstant(0, VT);
1116    return DAG.getNode(ISD::SRL, VT, N0.getOperand(0),
1117                       DAG.getConstant(c1 + c2, N1.getValueType()));
1118  }
1119  return SDOperand();
1120}
1121
1122SDOperand DAGCombiner::visitCTLZ(SDNode *N) {
1123  SDOperand N0 = N->getOperand(0);
1124  ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1125
1126  // fold (ctlz c1) -> c2
1127  if (N0C)
1128    return DAG.getConstant(CountLeadingZeros_64(N0C->getValue()),
1129                           N0.getValueType());
1130  return SDOperand();
1131}
1132
1133SDOperand DAGCombiner::visitCTTZ(SDNode *N) {
1134  SDOperand N0 = N->getOperand(0);
1135  ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1136
1137  // fold (cttz c1) -> c2
1138  if (N0C)
1139    return DAG.getConstant(CountTrailingZeros_64(N0C->getValue()),
1140                           N0.getValueType());
1141  return SDOperand();
1142}
1143
1144SDOperand DAGCombiner::visitCTPOP(SDNode *N) {
1145  SDOperand N0 = N->getOperand(0);
1146  ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1147
1148  // fold (ctpop c1) -> c2
1149  if (N0C)
1150    return DAG.getConstant(CountPopulation_64(N0C->getValue()),
1151                           N0.getValueType());
1152  return SDOperand();
1153}
1154
1155SDOperand DAGCombiner::visitSELECT(SDNode *N) {
1156  SDOperand N0 = N->getOperand(0);
1157  SDOperand N1 = N->getOperand(1);
1158  SDOperand N2 = N->getOperand(2);
1159  ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1160  ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1161  ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
1162  MVT::ValueType VT = N->getValueType(0);
1163
1164  // fold select C, X, X -> X
1165  if (N1 == N2)
1166    return N1;
1167  // fold select true, X, Y -> X
1168  if (N0C && !N0C->isNullValue())
1169    return N1;
1170  // fold select false, X, Y -> Y
1171  if (N0C && N0C->isNullValue())
1172    return N2;
1173  // fold select C, 1, X -> C | X
1174  if (MVT::i1 == VT && N1C && N1C->getValue() == 1)
1175    return DAG.getNode(ISD::OR, VT, N0, N2);
1176  // fold select C, 0, X -> ~C & X
1177  // FIXME: this should check for C type == X type, not i1?
1178  if (MVT::i1 == VT && N1C && N1C->isNullValue()) {
1179    SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT));
1180    WorkList.push_back(XORNode.Val);
1181    return DAG.getNode(ISD::AND, VT, XORNode, N2);
1182  }
1183  // fold select C, X, 1 -> ~C | X
1184  if (MVT::i1 == VT && N2C && N2C->getValue() == 1) {
1185    SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT));
1186    WorkList.push_back(XORNode.Val);
1187    return DAG.getNode(ISD::OR, VT, XORNode, N1);
1188  }
1189  // fold select C, X, 0 -> C & X
1190  // FIXME: this should check for C type == X type, not i1?
1191  if (MVT::i1 == VT && N2C && N2C->isNullValue())
1192    return DAG.getNode(ISD::AND, VT, N0, N1);
1193  // fold  X ? X : Y --> X ? 1 : Y --> X | Y
1194  if (MVT::i1 == VT && N0 == N1)
1195    return DAG.getNode(ISD::OR, VT, N0, N2);
1196  // fold X ? Y : X --> X ? Y : 0 --> X & Y
1197  if (MVT::i1 == VT && N0 == N2)
1198    return DAG.getNode(ISD::AND, VT, N0, N1);
1199  // fold selects based on a setcc into other things, such as min/max/abs
1200  if (N0.getOpcode() == ISD::SETCC)
1201    return SimplifySelect(N0, N1, N2);
1202  return SDOperand();
1203}
1204
1205SDOperand DAGCombiner::visitSELECT_CC(SDNode *N) {
1206  SDOperand N0 = N->getOperand(0);
1207  SDOperand N1 = N->getOperand(1);
1208  SDOperand N2 = N->getOperand(2);
1209  SDOperand N3 = N->getOperand(3);
1210  SDOperand N4 = N->getOperand(4);
1211  ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1212  ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1213  ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
1214  ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get();
1215
1216  // Determine if the condition we're dealing with is constant
1217  SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false);
1218  ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val);
1219
1220  // fold select_cc lhs, rhs, x, x, cc -> x
1221  if (N2 == N3)
1222    return N2;
1223  // fold select_cc into other things, such as min/max/abs
1224  return SimplifySelectCC(N0, N1, N2, N3, CC);
1225}
1226
1227SDOperand DAGCombiner::visitSETCC(SDNode *N) {
1228  return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1),
1229                       cast<CondCodeSDNode>(N->getOperand(2))->get());
1230}
1231
1232SDOperand DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
1233  SDOperand N0 = N->getOperand(0);
1234  ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1235  MVT::ValueType VT = N->getValueType(0);
1236
1237  // fold (sext c1) -> c1
1238  if (N0C)
1239    return DAG.getConstant(N0C->getSignExtended(), VT);
1240  // fold (sext (sext x)) -> (sext x)
1241  if (N0.getOpcode() == ISD::SIGN_EXTEND)
1242    return DAG.getNode(ISD::SIGN_EXTEND, VT, N0.getOperand(0));
1243  // fold (sext (sextload x)) -> (sextload x)
1244  if (N0.getOpcode() == ISD::SEXTLOAD && VT == N0.getValueType())
1245    return N0;
1246  // fold (sext (load x)) -> (sextload x)
1247  if (N0.getOpcode() == ISD::LOAD && N0.Val->hasNUsesOfValue(1, 0)) {
1248    SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N0.getOperand(0),
1249                                       N0.getOperand(1), N0.getOperand(2),
1250                                       N0.getValueType());
1251    WorkList.push_back(N);
1252    CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad),
1253              ExtLoad.getValue(1));
1254    return SDOperand();
1255  }
1256  return SDOperand();
1257}
1258
1259SDOperand DAGCombiner::visitZERO_EXTEND(SDNode *N) {
1260  SDOperand N0 = N->getOperand(0);
1261  ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1262  MVT::ValueType VT = N->getValueType(0);
1263
1264  // fold (zext c1) -> c1
1265  if (N0C)
1266    return DAG.getConstant(N0C->getValue(), VT);
1267  // fold (zext (zext x)) -> (zext x)
1268  if (N0.getOpcode() == ISD::ZERO_EXTEND)
1269    return DAG.getNode(ISD::ZERO_EXTEND, VT, N0.getOperand(0));
1270  return SDOperand();
1271}
1272
1273SDOperand DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
1274  SDOperand N0 = N->getOperand(0);
1275  SDOperand N1 = N->getOperand(1);
1276  ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1277  MVT::ValueType VT = N->getValueType(0);
1278  MVT::ValueType EVT = cast<VTSDNode>(N1)->getVT();
1279  unsigned EVTBits = MVT::getSizeInBits(EVT);
1280
1281  // fold (sext_in_reg c1) -> c1
1282  if (N0C) {
1283    SDOperand Truncate = DAG.getConstant(N0C->getValue(), EVT);
1284    return DAG.getNode(ISD::SIGN_EXTEND, VT, Truncate);
1285  }
1286  // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt1
1287  if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
1288      cast<VTSDNode>(N0.getOperand(1))->getVT() < EVT) {
1289    return N0;
1290  }
1291  // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2
1292  if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
1293      EVT < cast<VTSDNode>(N0.getOperand(1))->getVT()) {
1294    return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), N1);
1295  }
1296  // fold (sext_in_reg (assert_sext x)) -> (assert_sext x)
1297  if (N0.getOpcode() == ISD::AssertSext &&
1298      cast<VTSDNode>(N0.getOperand(1))->getVT() <= EVT) {
1299    return N0;
1300  }
1301  // fold (sext_in_reg (sextload x)) -> (sextload x)
1302  if (N0.getOpcode() == ISD::SEXTLOAD &&
1303      cast<VTSDNode>(N0.getOperand(3))->getVT() <= EVT) {
1304    return N0;
1305  }
1306  // fold (sext_in_reg (setcc x)) -> setcc x iff (setcc x) == 0 or -1
1307  if (N0.getOpcode() == ISD::SETCC &&
1308      TLI.getSetCCResultContents() ==
1309        TargetLowering::ZeroOrNegativeOneSetCCResult)
1310    return N0;
1311  // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is zero
1312  if (MaskedValueIsZero(N0, 1ULL << (EVTBits-1), TLI))
1313    return DAG.getNode(ISD::AND, N0.getValueType(), N0,
1314                       DAG.getConstant(~0ULL >> (64-EVTBits), VT));
1315  // fold (sext_in_reg (srl x)) -> sra x
1316  if (N0.getOpcode() == ISD::SRL &&
1317      N0.getOperand(1).getOpcode() == ISD::Constant &&
1318      cast<ConstantSDNode>(N0.getOperand(1))->getValue() == EVTBits) {
1319    return DAG.getNode(ISD::SRA, N0.getValueType(), N0.getOperand(0),
1320                       N0.getOperand(1));
1321  }
1322  // fold (sext_inreg (extload x)) -> (sextload x)
1323  if (N0.getOpcode() == ISD::EXTLOAD &&
1324      EVT == cast<VTSDNode>(N0.getOperand(3))->getVT() &&
1325      (!AfterLegalize || TLI.isOperationLegal(ISD::SEXTLOAD, EVT))) {
1326    SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N0.getOperand(0),
1327                                       N0.getOperand(1), N0.getOperand(2),
1328                                       EVT);
1329    WorkList.push_back(N);
1330    CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
1331    return SDOperand();
1332  }
1333  // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use
1334  if (N0.getOpcode() == ISD::ZEXTLOAD && N0.Val->hasNUsesOfValue(1, 0) &&
1335      EVT == cast<VTSDNode>(N0.getOperand(3))->getVT() &&
1336      (!AfterLegalize || TLI.isOperationLegal(ISD::SEXTLOAD, EVT))) {
1337    SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N0.getOperand(0),
1338                                       N0.getOperand(1), N0.getOperand(2),
1339                                       EVT);
1340    WorkList.push_back(N);
1341    CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1));
1342    return SDOperand();
1343  }
1344  return SDOperand();
1345}
1346
1347SDOperand DAGCombiner::visitTRUNCATE(SDNode *N) {
1348  SDOperand N0 = N->getOperand(0);
1349  ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1350  MVT::ValueType VT = N->getValueType(0);
1351
1352  // noop truncate
1353  if (N0.getValueType() == N->getValueType(0))
1354    return N0;
1355  // fold (truncate c1) -> c1
1356  if (N0C)
1357    return DAG.getConstant(N0C->getValue(), VT);
1358  // fold (truncate (truncate x)) -> (truncate x)
1359  if (N0.getOpcode() == ISD::TRUNCATE)
1360    return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0));
1361  // fold (truncate (ext x)) -> (ext x) or (truncate x) or x
1362  if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::SIGN_EXTEND){
1363    if (N0.getValueType() < VT)
1364      // if the source is smaller than the dest, we still need an extend
1365      return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0));
1366    else if (N0.getValueType() > VT)
1367      // if the source is larger than the dest, than we just need the truncate
1368      return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0));
1369    else
1370      // if the source and dest are the same type, we can drop both the extend
1371      // and the truncate
1372      return N0.getOperand(0);
1373  }
1374  // fold (truncate (load x)) -> (smaller load x)
1375  if (N0.getOpcode() == ISD::LOAD && N0.Val->hasNUsesOfValue(1, 0)) {
1376    assert(MVT::getSizeInBits(N0.getValueType()) > MVT::getSizeInBits(VT) &&
1377           "Cannot truncate to larger type!");
1378    MVT::ValueType PtrType = N0.getOperand(1).getValueType();
1379    // For big endian targets, we need to add an offset to the pointer to load
1380    // the correct bytes.  For little endian systems, we merely need to read
1381    // fewer bytes from the same pointer.
1382    uint64_t PtrOff =
1383      (MVT::getSizeInBits(N0.getValueType()) - MVT::getSizeInBits(VT)) / 8;
1384    SDOperand NewPtr = TLI.isLittleEndian() ? N0.getOperand(1) :
1385      DAG.getNode(ISD::ADD, PtrType, N0.getOperand(1),
1386                  DAG.getConstant(PtrOff, PtrType));
1387    WorkList.push_back(NewPtr.Val);
1388    SDOperand Load = DAG.getLoad(VT, N0.getOperand(0), NewPtr,N0.getOperand(2));
1389    CombineTo(N0.Val, Load, Load.getOperand(0));
1390    WorkList.push_back(N);
1391    return SDOperand();
1392  }
1393  return SDOperand();
1394}
1395
1396SDOperand DAGCombiner::visitFADD(SDNode *N) {
1397  SDOperand N0 = N->getOperand(0);
1398  SDOperand N1 = N->getOperand(1);
1399  MVT::ValueType VT = N->getValueType(0);
1400
1401  if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0))
1402    if (ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1)) {
1403      // fold floating point (fadd c1, c2)
1404      return DAG.getConstantFP(N0CFP->getValue() + N1CFP->getValue(),
1405                               N->getValueType(0));
1406    }
1407  // fold (A + (-B)) -> A-B
1408  if (N1.getOpcode() == ISD::FNEG)
1409    return DAG.getNode(ISD::FSUB, VT, N0, N1.getOperand(0));
1410
1411  // fold ((-A) + B) -> B-A
1412  if (N0.getOpcode() == ISD::FNEG)
1413    return DAG.getNode(ISD::FSUB, VT, N1, N0.getOperand(0));
1414
1415  return SDOperand();
1416}
1417
1418SDOperand DAGCombiner::visitFSUB(SDNode *N) {
1419  SDOperand N0 = N->getOperand(0);
1420  SDOperand N1 = N->getOperand(1);
1421  MVT::ValueType VT = N->getValueType(0);
1422
1423  if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0))
1424    if (ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1)) {
1425      // fold floating point (fsub c1, c2)
1426      return DAG.getConstantFP(N0CFP->getValue() - N1CFP->getValue(),
1427                               N->getValueType(0));
1428    }
1429  // fold (A-(-B)) -> A+B
1430  if (N1.getOpcode() == ISD::FNEG)
1431    return DAG.getNode(ISD::FADD, N0.getValueType(), N0, N1.getOperand(0));
1432
1433  return SDOperand();
1434}
1435
1436SDOperand DAGCombiner::visitFMUL(SDNode *N) {
1437  SDOperand N0 = N->getOperand(0);
1438  SDOperand N1 = N->getOperand(1);
1439  MVT::ValueType VT = N->getValueType(0);
1440
1441  if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0))
1442    if (ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1)) {
1443      // fold floating point (fmul c1, c2)
1444      return DAG.getConstantFP(N0CFP->getValue() * N1CFP->getValue(),
1445                               N->getValueType(0));
1446    }
1447  return SDOperand();
1448}
1449
1450SDOperand DAGCombiner::visitFDIV(SDNode *N) {
1451  SDOperand N0 = N->getOperand(0);
1452  SDOperand N1 = N->getOperand(1);
1453  MVT::ValueType VT = N->getValueType(0);
1454
1455  if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0))
1456    if (ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1)) {
1457      // fold floating point (fdiv c1, c2)
1458      return DAG.getConstantFP(N0CFP->getValue() / N1CFP->getValue(),
1459                               N->getValueType(0));
1460    }
1461  return SDOperand();
1462}
1463
1464SDOperand DAGCombiner::visitFREM(SDNode *N) {
1465  SDOperand N0 = N->getOperand(0);
1466  SDOperand N1 = N->getOperand(1);
1467  MVT::ValueType VT = N->getValueType(0);
1468
1469  if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0))
1470    if (ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1)) {
1471      // fold floating point (frem c1, c2) -> fmod(c1, c2)
1472      return DAG.getConstantFP(fmod(N0CFP->getValue(),N1CFP->getValue()),
1473                               N->getValueType(0));
1474    }
1475  return SDOperand();
1476}
1477
1478
1479SDOperand DAGCombiner::visitSINT_TO_FP(SDNode *N) {
1480  SDOperand N0 = N->getOperand(0);
1481  ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1482
1483  // fold (sint_to_fp c1) -> c1fp
1484  if (N0C)
1485    return DAG.getConstantFP(N0C->getSignExtended(), N->getValueType(0));
1486  return SDOperand();
1487}
1488
1489SDOperand DAGCombiner::visitUINT_TO_FP(SDNode *N) {
1490  SDOperand N0 = N->getOperand(0);
1491  ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1492
1493  // fold (uint_to_fp c1) -> c1fp
1494  if (N0C)
1495    return DAG.getConstantFP(N0C->getValue(), N->getValueType(0));
1496  return SDOperand();
1497}
1498
1499SDOperand DAGCombiner::visitFP_TO_SINT(SDNode *N) {
1500  ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0));
1501
1502  // fold (fp_to_sint c1fp) -> c1
1503  if (N0CFP)
1504    return DAG.getConstant((int64_t)N0CFP->getValue(), N->getValueType(0));
1505  return SDOperand();
1506}
1507
1508SDOperand DAGCombiner::visitFP_TO_UINT(SDNode *N) {
1509  ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0));
1510
1511  // fold (fp_to_uint c1fp) -> c1
1512  if (N0CFP)
1513    return DAG.getConstant((uint64_t)N0CFP->getValue(), N->getValueType(0));
1514  return SDOperand();
1515}
1516
1517SDOperand DAGCombiner::visitFP_ROUND(SDNode *N) {
1518  ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0));
1519
1520  // fold (fp_round c1fp) -> c1fp
1521  if (N0CFP)
1522    return DAG.getConstantFP(N0CFP->getValue(), N->getValueType(0));
1523  return SDOperand();
1524}
1525
1526SDOperand DAGCombiner::visitFP_ROUND_INREG(SDNode *N) {
1527  SDOperand N0 = N->getOperand(0);
1528  MVT::ValueType VT = N->getValueType(0);
1529  MVT::ValueType EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
1530  ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
1531
1532  // fold (fp_round_inreg c1fp) -> c1fp
1533  if (N0CFP) {
1534    SDOperand Round = DAG.getConstantFP(N0CFP->getValue(), EVT);
1535    return DAG.getNode(ISD::FP_EXTEND, VT, Round);
1536  }
1537  return SDOperand();
1538}
1539
1540SDOperand DAGCombiner::visitFP_EXTEND(SDNode *N) {
1541  ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0));
1542
1543  // fold (fp_extend c1fp) -> c1fp
1544  if (N0CFP)
1545    return DAG.getConstantFP(N0CFP->getValue(), N->getValueType(0));
1546  return SDOperand();
1547}
1548
1549SDOperand DAGCombiner::visitFNEG(SDNode *N) {
1550  ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0));
1551  // fold (neg c1) -> -c1
1552  if (N0CFP)
1553    return DAG.getConstantFP(-N0CFP->getValue(), N->getValueType(0));
1554  // fold (neg (sub x, y)) -> (sub y, x)
1555  if (N->getOperand(0).getOpcode() == ISD::SUB)
1556    return DAG.getNode(ISD::SUB, N->getValueType(0), N->getOperand(1),
1557                       N->getOperand(0));
1558  // fold (neg (neg x)) -> x
1559  if (N->getOperand(0).getOpcode() == ISD::FNEG)
1560    return N->getOperand(0).getOperand(0);
1561  return SDOperand();
1562}
1563
1564SDOperand DAGCombiner::visitFABS(SDNode *N) {
1565  ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0));
1566  // fold (fabs c1) -> fabs(c1)
1567  if (N0CFP)
1568    return DAG.getConstantFP(fabs(N0CFP->getValue()), N->getValueType(0));
1569  // fold (fabs (fabs x)) -> (fabs x)
1570  if (N->getOperand(0).getOpcode() == ISD::FABS)
1571    return N->getOperand(0);
1572  // fold (fabs (fneg x)) -> (fabs x)
1573  if (N->getOperand(0).getOpcode() == ISD::FNEG)
1574    return DAG.getNode(ISD::FABS, N->getValueType(0),
1575                       N->getOperand(0).getOperand(0));
1576  return SDOperand();
1577}
1578
1579SDOperand DAGCombiner::visitBRCOND(SDNode *N) {
1580  SDOperand Chain = N->getOperand(0);
1581  SDOperand N1 = N->getOperand(1);
1582  SDOperand N2 = N->getOperand(2);
1583  ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1584
1585  // never taken branch, fold to chain
1586  if (N1C && N1C->isNullValue())
1587    return Chain;
1588  // unconditional branch
1589  if (N1C && N1C->getValue() == 1)
1590    return DAG.getNode(ISD::BR, MVT::Other, Chain, N2);
1591  return SDOperand();
1592}
1593
1594SDOperand DAGCombiner::visitBRCONDTWOWAY(SDNode *N) {
1595  SDOperand Chain = N->getOperand(0);
1596  SDOperand N1 = N->getOperand(1);
1597  SDOperand N2 = N->getOperand(2);
1598  SDOperand N3 = N->getOperand(3);
1599  ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1600
1601  // unconditional branch to true mbb
1602  if (N1C && N1C->getValue() == 1)
1603    return DAG.getNode(ISD::BR, MVT::Other, Chain, N2);
1604  // unconditional branch to false mbb
1605  if (N1C && N1C->isNullValue())
1606    return DAG.getNode(ISD::BR, MVT::Other, Chain, N3);
1607  return SDOperand();
1608}
1609
1610// Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB.
1611//
1612SDOperand DAGCombiner::visitBR_CC(SDNode *N) {
1613  CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1));
1614  SDOperand CondLHS = N->getOperand(2), CondRHS = N->getOperand(3);
1615
1616  // Use SimplifySetCC  to simplify SETCC's.
1617  SDOperand Simp = SimplifySetCC(MVT::i1, CondLHS, CondRHS, CC->get(), false);
1618  ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(Simp.Val);
1619
1620  // fold br_cc true, dest -> br dest (unconditional branch)
1621  if (SCCC && SCCC->getValue())
1622    return DAG.getNode(ISD::BR, MVT::Other, N->getOperand(0),
1623                       N->getOperand(4));
1624  // fold br_cc false, dest -> unconditional fall through
1625  if (SCCC && SCCC->isNullValue())
1626    return N->getOperand(0);
1627  // fold to a simpler setcc
1628  if (Simp.Val && Simp.getOpcode() == ISD::SETCC)
1629    return DAG.getNode(ISD::BR_CC, MVT::Other, N->getOperand(0),
1630                       Simp.getOperand(2), Simp.getOperand(0),
1631                       Simp.getOperand(1), N->getOperand(4));
1632  return SDOperand();
1633}
1634
1635SDOperand DAGCombiner::visitBRTWOWAY_CC(SDNode *N) {
1636  SDOperand Chain = N->getOperand(0);
1637  SDOperand CCN = N->getOperand(1);
1638  SDOperand LHS = N->getOperand(2);
1639  SDOperand RHS = N->getOperand(3);
1640  SDOperand N4 = N->getOperand(4);
1641  SDOperand N5 = N->getOperand(5);
1642
1643  SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), LHS, RHS,
1644                                cast<CondCodeSDNode>(CCN)->get(), false);
1645  ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val);
1646
1647  // fold select_cc lhs, rhs, x, x, cc -> x
1648  if (N4 == N5)
1649    return DAG.getNode(ISD::BR, MVT::Other, Chain, N4);
1650  // fold select_cc true, x, y -> x
1651  if (SCCC && SCCC->getValue())
1652    return DAG.getNode(ISD::BR, MVT::Other, Chain, N4);
1653  // fold select_cc false, x, y -> y
1654  if (SCCC && SCCC->isNullValue())
1655    return DAG.getNode(ISD::BR, MVT::Other, Chain, N5);
1656  // fold to a simpler setcc
1657  if (SCC.Val && SCC.getOpcode() == ISD::SETCC)
1658    return DAG.getBR2Way_CC(Chain, SCC.getOperand(2), SCC.getOperand(0),
1659                            SCC.getOperand(1), N4, N5);
1660  return SDOperand();
1661}
1662
1663SDOperand DAGCombiner::visitLOAD(SDNode *N) {
1664  SDOperand Chain    = N->getOperand(0);
1665  SDOperand Ptr      = N->getOperand(1);
1666  SDOperand SrcValue = N->getOperand(2);
1667
1668  // If this load is directly stored, replace the load value with the stored
1669  // value.
1670  // TODO: Handle store large -> read small portion.
1671  // TODO: Handle TRUNCSTORE/EXTLOAD
1672  if (Chain.getOpcode() == ISD::STORE && Chain.getOperand(2) == Ptr &&
1673      Chain.getOperand(1).getValueType() == N->getValueType(0))
1674    return CombineTo(N, Chain.getOperand(1), Chain);
1675
1676  return SDOperand();
1677}
1678
1679SDOperand DAGCombiner::visitSTORE(SDNode *N) {
1680  SDOperand Chain    = N->getOperand(0);
1681  SDOperand Value    = N->getOperand(1);
1682  SDOperand Ptr      = N->getOperand(2);
1683  SDOperand SrcValue = N->getOperand(3);
1684
1685  // If this is a store that kills a previous store, remove the previous store.
1686  if (Chain.getOpcode() == ISD::STORE && Chain.getOperand(2) == Ptr &&
1687      Chain.Val->hasOneUse() /* Avoid introducing DAG cycles */) {
1688    // Create a new store of Value that replaces both stores.
1689    SDNode *PrevStore = Chain.Val;
1690    if (PrevStore->getOperand(1) == Value) // Same value multiply stored.
1691      return Chain;
1692    SDOperand NewStore = DAG.getNode(ISD::STORE, MVT::Other,
1693                                     PrevStore->getOperand(0), Value, Ptr,
1694                                     SrcValue);
1695    CombineTo(N, NewStore);                 // Nuke this store.
1696    CombineTo(PrevStore, NewStore);  // Nuke the previous store.
1697    return SDOperand(N, 0);
1698  }
1699
1700  return SDOperand();
1701}
1702
1703SDOperand DAGCombiner::SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2){
1704  assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!");
1705
1706  SDOperand SCC = SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), N1, N2,
1707                                 cast<CondCodeSDNode>(N0.getOperand(2))->get());
1708  // If we got a simplified select_cc node back from SimplifySelectCC, then
1709  // break it down into a new SETCC node, and a new SELECT node, and then return
1710  // the SELECT node, since we were called with a SELECT node.
1711  if (SCC.Val) {
1712    // Check to see if we got a select_cc back (to turn into setcc/select).
1713    // Otherwise, just return whatever node we got back, like fabs.
1714    if (SCC.getOpcode() == ISD::SELECT_CC) {
1715      SDOperand SETCC = DAG.getNode(ISD::SETCC, N0.getValueType(),
1716                                    SCC.getOperand(0), SCC.getOperand(1),
1717                                    SCC.getOperand(4));
1718      WorkList.push_back(SETCC.Val);
1719      return DAG.getNode(ISD::SELECT, SCC.getValueType(), SCC.getOperand(2),
1720                         SCC.getOperand(3), SETCC);
1721    }
1722    return SCC;
1723  }
1724  return SDOperand();
1725}
1726
1727SDOperand DAGCombiner::SimplifySelectCC(SDOperand N0, SDOperand N1,
1728                                        SDOperand N2, SDOperand N3,
1729                                        ISD::CondCode CC) {
1730
1731  MVT::ValueType VT = N2.getValueType();
1732  ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val);
1733  ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val);
1734  ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val);
1735  ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.Val);
1736
1737  // Determine if the condition we're dealing with is constant
1738  SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false);
1739  ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val);
1740
1741  // fold select_cc true, x, y -> x
1742  if (SCCC && SCCC->getValue())
1743    return N2;
1744  // fold select_cc false, x, y -> y
1745  if (SCCC && SCCC->getValue() == 0)
1746    return N3;
1747
1748  // Check to see if we can simplify the select into an fabs node
1749  if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) {
1750    // Allow either -0.0 or 0.0
1751    if (CFP->getValue() == 0.0) {
1752      // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs
1753      if ((CC == ISD::SETGE || CC == ISD::SETGT) &&
1754          N0 == N2 && N3.getOpcode() == ISD::FNEG &&
1755          N2 == N3.getOperand(0))
1756        return DAG.getNode(ISD::FABS, VT, N0);
1757
1758      // select (setl[te] X, +/-0.0), fneg(X), X -> fabs
1759      if ((CC == ISD::SETLT || CC == ISD::SETLE) &&
1760          N0 == N3 && N2.getOpcode() == ISD::FNEG &&
1761          N2.getOperand(0) == N3)
1762        return DAG.getNode(ISD::FABS, VT, N3);
1763    }
1764  }
1765
1766  // Check to see if we can perform the "gzip trick", transforming
1767  // select_cc setlt X, 0, A, 0 -> and (sra X, size(X)-1), A
1768  if (N1C && N1C->isNullValue() && N3C && N3C->isNullValue() &&
1769      MVT::isInteger(N0.getValueType()) &&
1770      MVT::isInteger(N2.getValueType()) && CC == ISD::SETLT) {
1771    MVT::ValueType XType = N0.getValueType();
1772    MVT::ValueType AType = N2.getValueType();
1773    if (XType >= AType) {
1774      // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a
1775      // single-bit constant.
1776      if (N2C && ((N2C->getValue() & (N2C->getValue()-1)) == 0)) {
1777        unsigned ShCtV = Log2_64(N2C->getValue());
1778        ShCtV = MVT::getSizeInBits(XType)-ShCtV-1;
1779        SDOperand ShCt = DAG.getConstant(ShCtV, TLI.getShiftAmountTy());
1780        SDOperand Shift = DAG.getNode(ISD::SRL, XType, N0, ShCt);
1781        WorkList.push_back(Shift.Val);
1782        if (XType > AType) {
1783          Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift);
1784          WorkList.push_back(Shift.Val);
1785        }
1786        return DAG.getNode(ISD::AND, AType, Shift, N2);
1787      }
1788      SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0,
1789                                    DAG.getConstant(MVT::getSizeInBits(XType)-1,
1790                                                    TLI.getShiftAmountTy()));
1791      WorkList.push_back(Shift.Val);
1792      if (XType > AType) {
1793        Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift);
1794        WorkList.push_back(Shift.Val);
1795      }
1796      return DAG.getNode(ISD::AND, AType, Shift, N2);
1797    }
1798  }
1799
1800  // fold select C, 16, 0 -> shl C, 4
1801  if (N2C && N3C && N3C->isNullValue() && isPowerOf2_64(N2C->getValue()) &&
1802      TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult) {
1803    // Get a SetCC of the condition
1804    // FIXME: Should probably make sure that setcc is legal if we ever have a
1805    // target where it isn't.
1806    SDOperand Temp, SCC = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC);
1807    WorkList.push_back(SCC.Val);
1808    // cast from setcc result type to select result type
1809    if (AfterLegalize)
1810      Temp = DAG.getZeroExtendInReg(SCC, N2.getValueType());
1811    else
1812      Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC);
1813    WorkList.push_back(Temp.Val);
1814    // shl setcc result by log2 n2c
1815    return DAG.getNode(ISD::SHL, N2.getValueType(), Temp,
1816                       DAG.getConstant(Log2_64(N2C->getValue()),
1817                                       TLI.getShiftAmountTy()));
1818  }
1819
1820  // Check to see if this is the equivalent of setcc
1821  // FIXME: Turn all of these into setcc if setcc if setcc is legal
1822  // otherwise, go ahead with the folds.
1823  if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getValue() == 1ULL)) {
1824    MVT::ValueType XType = N0.getValueType();
1825    if (TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultTy())) {
1826      SDOperand Res = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC);
1827      if (Res.getValueType() != VT)
1828        Res = DAG.getNode(ISD::ZERO_EXTEND, VT, Res);
1829      return Res;
1830    }
1831
1832    // seteq X, 0 -> srl (ctlz X, log2(size(X)))
1833    if (N1C && N1C->isNullValue() && CC == ISD::SETEQ &&
1834        TLI.isOperationLegal(ISD::CTLZ, XType)) {
1835      SDOperand Ctlz = DAG.getNode(ISD::CTLZ, XType, N0);
1836      return DAG.getNode(ISD::SRL, XType, Ctlz,
1837                         DAG.getConstant(Log2_32(MVT::getSizeInBits(XType)),
1838                                         TLI.getShiftAmountTy()));
1839    }
1840    // setgt X, 0 -> srl (and (-X, ~X), size(X)-1)
1841    if (N1C && N1C->isNullValue() && CC == ISD::SETGT) {
1842      SDOperand NegN0 = DAG.getNode(ISD::SUB, XType, DAG.getConstant(0, XType),
1843                                    N0);
1844      SDOperand NotN0 = DAG.getNode(ISD::XOR, XType, N0,
1845                                    DAG.getConstant(~0ULL, XType));
1846      return DAG.getNode(ISD::SRL, XType,
1847                         DAG.getNode(ISD::AND, XType, NegN0, NotN0),
1848                         DAG.getConstant(MVT::getSizeInBits(XType)-1,
1849                                         TLI.getShiftAmountTy()));
1850    }
1851    // setgt X, -1 -> xor (srl (X, size(X)-1), 1)
1852    if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) {
1853      SDOperand Sign = DAG.getNode(ISD::SRL, XType, N0,
1854                                   DAG.getConstant(MVT::getSizeInBits(XType)-1,
1855                                                   TLI.getShiftAmountTy()));
1856      return DAG.getNode(ISD::XOR, XType, Sign, DAG.getConstant(1, XType));
1857    }
1858  }
1859
1860  // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X ->
1861  // Y = sra (X, size(X)-1); xor (add (X, Y), Y)
1862  if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) &&
1863      N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1)) {
1864    if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N2.getOperand(0))) {
1865      MVT::ValueType XType = N0.getValueType();
1866      if (SubC->isNullValue() && MVT::isInteger(XType)) {
1867        SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0,
1868                                    DAG.getConstant(MVT::getSizeInBits(XType)-1,
1869                                                    TLI.getShiftAmountTy()));
1870        SDOperand Add = DAG.getNode(ISD::ADD, XType, N0, Shift);
1871        WorkList.push_back(Shift.Val);
1872        WorkList.push_back(Add.Val);
1873        return DAG.getNode(ISD::XOR, XType, Add, Shift);
1874      }
1875    }
1876  }
1877
1878  return SDOperand();
1879}
1880
1881SDOperand DAGCombiner::SimplifySetCC(MVT::ValueType VT, SDOperand N0,
1882                                     SDOperand N1, ISD::CondCode Cond,
1883                                     bool foldBooleans) {
1884  // These setcc operations always fold.
1885  switch (Cond) {
1886  default: break;
1887  case ISD::SETFALSE:
1888  case ISD::SETFALSE2: return DAG.getConstant(0, VT);
1889  case ISD::SETTRUE:
1890  case ISD::SETTRUE2:  return DAG.getConstant(1, VT);
1891  }
1892
1893  if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val)) {
1894    uint64_t C1 = N1C->getValue();
1895    if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val)) {
1896      uint64_t C0 = N0C->getValue();
1897
1898      // Sign extend the operands if required
1899      if (ISD::isSignedIntSetCC(Cond)) {
1900        C0 = N0C->getSignExtended();
1901        C1 = N1C->getSignExtended();
1902      }
1903
1904      switch (Cond) {
1905      default: assert(0 && "Unknown integer setcc!");
1906      case ISD::SETEQ:  return DAG.getConstant(C0 == C1, VT);
1907      case ISD::SETNE:  return DAG.getConstant(C0 != C1, VT);
1908      case ISD::SETULT: return DAG.getConstant(C0 <  C1, VT);
1909      case ISD::SETUGT: return DAG.getConstant(C0 >  C1, VT);
1910      case ISD::SETULE: return DAG.getConstant(C0 <= C1, VT);
1911      case ISD::SETUGE: return DAG.getConstant(C0 >= C1, VT);
1912      case ISD::SETLT:  return DAG.getConstant((int64_t)C0 <  (int64_t)C1, VT);
1913      case ISD::SETGT:  return DAG.getConstant((int64_t)C0 >  (int64_t)C1, VT);
1914      case ISD::SETLE:  return DAG.getConstant((int64_t)C0 <= (int64_t)C1, VT);
1915      case ISD::SETGE:  return DAG.getConstant((int64_t)C0 >= (int64_t)C1, VT);
1916      }
1917    } else {
1918      // If the LHS is a ZERO_EXTEND, perform the comparison on the input.
1919      if (N0.getOpcode() == ISD::ZERO_EXTEND) {
1920        unsigned InSize = MVT::getSizeInBits(N0.getOperand(0).getValueType());
1921
1922        // If the comparison constant has bits in the upper part, the
1923        // zero-extended value could never match.
1924        if (C1 & (~0ULL << InSize)) {
1925          unsigned VSize = MVT::getSizeInBits(N0.getValueType());
1926          switch (Cond) {
1927          case ISD::SETUGT:
1928          case ISD::SETUGE:
1929          case ISD::SETEQ: return DAG.getConstant(0, VT);
1930          case ISD::SETULT:
1931          case ISD::SETULE:
1932          case ISD::SETNE: return DAG.getConstant(1, VT);
1933          case ISD::SETGT:
1934          case ISD::SETGE:
1935            // True if the sign bit of C1 is set.
1936            return DAG.getConstant((C1 & (1ULL << VSize)) != 0, VT);
1937          case ISD::SETLT:
1938          case ISD::SETLE:
1939            // True if the sign bit of C1 isn't set.
1940            return DAG.getConstant((C1 & (1ULL << VSize)) == 0, VT);
1941          default:
1942            break;
1943          }
1944        }
1945
1946        // Otherwise, we can perform the comparison with the low bits.
1947        switch (Cond) {
1948        case ISD::SETEQ:
1949        case ISD::SETNE:
1950        case ISD::SETUGT:
1951        case ISD::SETUGE:
1952        case ISD::SETULT:
1953        case ISD::SETULE:
1954          return DAG.getSetCC(VT, N0.getOperand(0),
1955                          DAG.getConstant(C1, N0.getOperand(0).getValueType()),
1956                          Cond);
1957        default:
1958          break;   // todo, be more careful with signed comparisons
1959        }
1960      } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
1961                 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
1962        MVT::ValueType ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT();
1963        unsigned ExtSrcTyBits = MVT::getSizeInBits(ExtSrcTy);
1964        MVT::ValueType ExtDstTy = N0.getValueType();
1965        unsigned ExtDstTyBits = MVT::getSizeInBits(ExtDstTy);
1966
1967        // If the extended part has any inconsistent bits, it cannot ever
1968        // compare equal.  In other words, they have to be all ones or all
1969        // zeros.
1970        uint64_t ExtBits =
1971          (~0ULL >> (64-ExtSrcTyBits)) & (~0ULL << (ExtDstTyBits-1));
1972        if ((C1 & ExtBits) != 0 && (C1 & ExtBits) != ExtBits)
1973          return DAG.getConstant(Cond == ISD::SETNE, VT);
1974
1975        SDOperand ZextOp;
1976        MVT::ValueType Op0Ty = N0.getOperand(0).getValueType();
1977        if (Op0Ty == ExtSrcTy) {
1978          ZextOp = N0.getOperand(0);
1979        } else {
1980          int64_t Imm = ~0ULL >> (64-ExtSrcTyBits);
1981          ZextOp = DAG.getNode(ISD::AND, Op0Ty, N0.getOperand(0),
1982                               DAG.getConstant(Imm, Op0Ty));
1983        }
1984        WorkList.push_back(ZextOp.Val);
1985        // Otherwise, make this a use of a zext.
1986        return DAG.getSetCC(VT, ZextOp,
1987                            DAG.getConstant(C1 & (~0ULL>>(64-ExtSrcTyBits)),
1988                                            ExtDstTy),
1989                            Cond);
1990      }
1991
1992      uint64_t MinVal, MaxVal;
1993      unsigned OperandBitSize = MVT::getSizeInBits(N1C->getValueType(0));
1994      if (ISD::isSignedIntSetCC(Cond)) {
1995        MinVal = 1ULL << (OperandBitSize-1);
1996        if (OperandBitSize != 1)   // Avoid X >> 64, which is undefined.
1997          MaxVal = ~0ULL >> (65-OperandBitSize);
1998        else
1999          MaxVal = 0;
2000      } else {
2001        MinVal = 0;
2002        MaxVal = ~0ULL >> (64-OperandBitSize);
2003      }
2004
2005      // Canonicalize GE/LE comparisons to use GT/LT comparisons.
2006      if (Cond == ISD::SETGE || Cond == ISD::SETUGE) {
2007        if (C1 == MinVal) return DAG.getConstant(1, VT);   // X >= MIN --> true
2008        --C1;                                          // X >= C0 --> X > (C0-1)
2009        return DAG.getSetCC(VT, N0, DAG.getConstant(C1, N1.getValueType()),
2010                        (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT);
2011      }
2012
2013      if (Cond == ISD::SETLE || Cond == ISD::SETULE) {
2014        if (C1 == MaxVal) return DAG.getConstant(1, VT);   // X <= MAX --> true
2015        ++C1;                                          // X <= C0 --> X < (C0+1)
2016        return DAG.getSetCC(VT, N0, DAG.getConstant(C1, N1.getValueType()),
2017                        (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT);
2018      }
2019
2020      if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal)
2021        return DAG.getConstant(0, VT);      // X < MIN --> false
2022
2023      // Canonicalize setgt X, Min --> setne X, Min
2024      if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal)
2025        return DAG.getSetCC(VT, N0, N1, ISD::SETNE);
2026
2027      // If we have setult X, 1, turn it into seteq X, 0
2028      if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1)
2029        return DAG.getSetCC(VT, N0, DAG.getConstant(MinVal, N0.getValueType()),
2030                        ISD::SETEQ);
2031      // If we have setugt X, Max-1, turn it into seteq X, Max
2032      else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1)
2033        return DAG.getSetCC(VT, N0, DAG.getConstant(MaxVal, N0.getValueType()),
2034                        ISD::SETEQ);
2035
2036      // If we have "setcc X, C0", check to see if we can shrink the immediate
2037      // by changing cc.
2038
2039      // SETUGT X, SINTMAX  -> SETLT X, 0
2040      if (Cond == ISD::SETUGT && OperandBitSize != 1 &&
2041          C1 == (~0ULL >> (65-OperandBitSize)))
2042        return DAG.getSetCC(VT, N0, DAG.getConstant(0, N1.getValueType()),
2043                            ISD::SETLT);
2044
2045      // FIXME: Implement the rest of these.
2046
2047      // Fold bit comparisons when we can.
2048      if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
2049          VT == N0.getValueType() && N0.getOpcode() == ISD::AND)
2050        if (ConstantSDNode *AndRHS =
2051                    dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
2052          if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0  -->  (X & 8) >> 3
2053            // Perform the xform if the AND RHS is a single bit.
2054            if ((AndRHS->getValue() & (AndRHS->getValue()-1)) == 0) {
2055              return DAG.getNode(ISD::SRL, VT, N0,
2056                             DAG.getConstant(Log2_64(AndRHS->getValue()),
2057                                                   TLI.getShiftAmountTy()));
2058            }
2059          } else if (Cond == ISD::SETEQ && C1 == AndRHS->getValue()) {
2060            // (X & 8) == 8  -->  (X & 8) >> 3
2061            // Perform the xform if C1 is a single bit.
2062            if ((C1 & (C1-1)) == 0) {
2063              return DAG.getNode(ISD::SRL, VT, N0,
2064                             DAG.getConstant(Log2_64(C1),TLI.getShiftAmountTy()));
2065            }
2066          }
2067        }
2068    }
2069  } else if (isa<ConstantSDNode>(N0.Val)) {
2070      // Ensure that the constant occurs on the RHS.
2071    return DAG.getSetCC(VT, N1, N0, ISD::getSetCCSwappedOperands(Cond));
2072  }
2073
2074  if (ConstantFPSDNode *N0C = dyn_cast<ConstantFPSDNode>(N0.Val))
2075    if (ConstantFPSDNode *N1C = dyn_cast<ConstantFPSDNode>(N1.Val)) {
2076      double C0 = N0C->getValue(), C1 = N1C->getValue();
2077
2078      switch (Cond) {
2079      default: break; // FIXME: Implement the rest of these!
2080      case ISD::SETEQ:  return DAG.getConstant(C0 == C1, VT);
2081      case ISD::SETNE:  return DAG.getConstant(C0 != C1, VT);
2082      case ISD::SETLT:  return DAG.getConstant(C0 < C1, VT);
2083      case ISD::SETGT:  return DAG.getConstant(C0 > C1, VT);
2084      case ISD::SETLE:  return DAG.getConstant(C0 <= C1, VT);
2085      case ISD::SETGE:  return DAG.getConstant(C0 >= C1, VT);
2086      }
2087    } else {
2088      // Ensure that the constant occurs on the RHS.
2089      return DAG.getSetCC(VT, N1, N0, ISD::getSetCCSwappedOperands(Cond));
2090    }
2091
2092  if (N0 == N1) {
2093    // We can always fold X == Y for integer setcc's.
2094    if (MVT::isInteger(N0.getValueType()))
2095      return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
2096    unsigned UOF = ISD::getUnorderedFlavor(Cond);
2097    if (UOF == 2)   // FP operators that are undefined on NaNs.
2098      return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT);
2099    if (UOF == unsigned(ISD::isTrueWhenEqual(Cond)))
2100      return DAG.getConstant(UOF, VT);
2101    // Otherwise, we can't fold it.  However, we can simplify it to SETUO/SETO
2102    // if it is not already.
2103    ISD::CondCode NewCond = UOF == 0 ? ISD::SETUO : ISD::SETO;
2104    if (NewCond != Cond)
2105      return DAG.getSetCC(VT, N0, N1, NewCond);
2106  }
2107
2108  if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
2109      MVT::isInteger(N0.getValueType())) {
2110    if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB ||
2111        N0.getOpcode() == ISD::XOR) {
2112      // Simplify (X+Y) == (X+Z) -->  Y == Z
2113      if (N0.getOpcode() == N1.getOpcode()) {
2114        if (N0.getOperand(0) == N1.getOperand(0))
2115          return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(1), Cond);
2116        if (N0.getOperand(1) == N1.getOperand(1))
2117          return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(0), Cond);
2118        if (isCommutativeBinOp(N0.getOpcode())) {
2119          // If X op Y == Y op X, try other combinations.
2120          if (N0.getOperand(0) == N1.getOperand(1))
2121            return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(0), Cond);
2122          if (N0.getOperand(1) == N1.getOperand(0))
2123            return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(1), Cond);
2124        }
2125      }
2126
2127      // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0.  Common for condcodes.
2128      if (N0.getOpcode() == ISD::XOR)
2129        if (ConstantSDNode *XORC = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
2130          if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) {
2131            // If we know that all of the inverted bits are zero, don't bother
2132            // performing the inversion.
2133            if (MaskedValueIsZero(N0.getOperand(0), ~XORC->getValue(), TLI))
2134              return DAG.getSetCC(VT, N0.getOperand(0),
2135                              DAG.getConstant(XORC->getValue()^RHSC->getValue(),
2136                                              N0.getValueType()), Cond);
2137          }
2138
2139      // Simplify (X+Z) == X -->  Z == 0
2140      if (N0.getOperand(0) == N1)
2141        return DAG.getSetCC(VT, N0.getOperand(1),
2142                        DAG.getConstant(0, N0.getValueType()), Cond);
2143      if (N0.getOperand(1) == N1) {
2144        if (isCommutativeBinOp(N0.getOpcode()))
2145          return DAG.getSetCC(VT, N0.getOperand(0),
2146                          DAG.getConstant(0, N0.getValueType()), Cond);
2147        else {
2148          assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!");
2149          // (Z-X) == X  --> Z == X<<1
2150          SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(),
2151                                     N1,
2152                                     DAG.getConstant(1,TLI.getShiftAmountTy()));
2153          WorkList.push_back(SH.Val);
2154          return DAG.getSetCC(VT, N0.getOperand(0), SH, Cond);
2155        }
2156      }
2157    }
2158
2159    if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB ||
2160        N1.getOpcode() == ISD::XOR) {
2161      // Simplify  X == (X+Z) -->  Z == 0
2162      if (N1.getOperand(0) == N0) {
2163        return DAG.getSetCC(VT, N1.getOperand(1),
2164                        DAG.getConstant(0, N1.getValueType()), Cond);
2165      } else if (N1.getOperand(1) == N0) {
2166        if (isCommutativeBinOp(N1.getOpcode())) {
2167          return DAG.getSetCC(VT, N1.getOperand(0),
2168                          DAG.getConstant(0, N1.getValueType()), Cond);
2169        } else {
2170          assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!");
2171          // X == (Z-X)  --> X<<1 == Z
2172          SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(), N0,
2173                                     DAG.getConstant(1,TLI.getShiftAmountTy()));
2174          WorkList.push_back(SH.Val);
2175          return DAG.getSetCC(VT, SH, N1.getOperand(0), Cond);
2176        }
2177      }
2178    }
2179  }
2180
2181  // Fold away ALL boolean setcc's.
2182  SDOperand Temp;
2183  if (N0.getValueType() == MVT::i1 && foldBooleans) {
2184    switch (Cond) {
2185    default: assert(0 && "Unknown integer setcc!");
2186    case ISD::SETEQ:  // X == Y  -> (X^Y)^1
2187      Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, N1);
2188      N0 = DAG.getNode(ISD::XOR, MVT::i1, Temp, DAG.getConstant(1, MVT::i1));
2189      WorkList.push_back(Temp.Val);
2190      break;
2191    case ISD::SETNE:  // X != Y   -->  (X^Y)
2192      N0 = DAG.getNode(ISD::XOR, MVT::i1, N0, N1);
2193      break;
2194    case ISD::SETGT:  // X >s Y   -->  X == 0 & Y == 1  -->  X^1 & Y
2195    case ISD::SETULT: // X <u Y   -->  X == 0 & Y == 1  -->  X^1 & Y
2196      Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1));
2197      N0 = DAG.getNode(ISD::AND, MVT::i1, N1, Temp);
2198      WorkList.push_back(Temp.Val);
2199      break;
2200    case ISD::SETLT:  // X <s Y   --> X == 1 & Y == 0  -->  Y^1 & X
2201    case ISD::SETUGT: // X >u Y   --> X == 1 & Y == 0  -->  Y^1 & X
2202      Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1));
2203      N0 = DAG.getNode(ISD::AND, MVT::i1, N0, Temp);
2204      WorkList.push_back(Temp.Val);
2205      break;
2206    case ISD::SETULE: // X <=u Y  --> X == 0 | Y == 1  -->  X^1 | Y
2207    case ISD::SETGE:  // X >=s Y  --> X == 0 | Y == 1  -->  X^1 | Y
2208      Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1));
2209      N0 = DAG.getNode(ISD::OR, MVT::i1, N1, Temp);
2210      WorkList.push_back(Temp.Val);
2211      break;
2212    case ISD::SETUGE: // X >=u Y  --> X == 1 | Y == 0  -->  Y^1 | X
2213    case ISD::SETLE:  // X <=s Y  --> X == 1 | Y == 0  -->  Y^1 | X
2214      Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1));
2215      N0 = DAG.getNode(ISD::OR, MVT::i1, N0, Temp);
2216      break;
2217    }
2218    if (VT != MVT::i1) {
2219      WorkList.push_back(N0.Val);
2220      // FIXME: If running after legalize, we probably can't do this.
2221      N0 = DAG.getNode(ISD::ZERO_EXTEND, VT, N0);
2222    }
2223    return N0;
2224  }
2225
2226  // Could not fold it.
2227  return SDOperand();
2228}
2229
2230// SelectionDAG::Combine - This is the entry point for the file.
2231//
2232void SelectionDAG::Combine(bool RunningAfterLegalize) {
2233  /// run - This is the main entry point to this class.
2234  ///
2235  DAGCombiner(*this).Run(RunningAfterLegalize);
2236}
2237