DAGCombiner.cpp revision fb5e4bdded9c204c5f50c4770431544c074ef7bb
1//===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by Nate Begeman and is distributed under the 6// University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run 11// both before and after the DAG is legalized. 12// 13// FIXME: Missing folds 14// sdiv, udiv, srem, urem (X, const) where X is an integer can be expanded into 15// a sequence of multiplies, shifts, and adds. This should be controlled by 16// some kind of hint from the target that int div is expensive. 17// various folds of mulh[s,u] by constants such as -1, powers of 2, etc. 18// 19// FIXME: Should add a corresponding version of fold AND with 20// ZERO_EXTEND/SIGN_EXTEND by converting them to an ANY_EXTEND node which 21// we don't have yet. 22// 23// FIXME: select C, pow2, pow2 -> something smart 24// FIXME: trunc(select X, Y, Z) -> select X, trunc(Y), trunc(Z) 25// FIXME: Dead stores -> nuke 26// FIXME: shr X, (and Y,31) -> shr X, Y (TRICKY!) 27// FIXME: mul (x, const) -> shifts + adds 28// FIXME: undef values 29// FIXME: make truncate see through SIGN_EXTEND and AND 30// FIXME: (sra (sra x, c1), c2) -> (sra x, c1+c2) 31// FIXME: verify that getNode can't return extends with an operand whose type 32// is >= to that of the extend. 33// FIXME: divide by zero is currently left unfolded. do we want to turn this 34// into an undef? 35// FIXME: select ne (select cc, 1, 0), 0, true, false -> select cc, true, false 36// 37//===----------------------------------------------------------------------===// 38 39#define DEBUG_TYPE "dagcombine" 40#include "llvm/ADT/Statistic.h" 41#include "llvm/CodeGen/SelectionDAG.h" 42#include "llvm/Support/Debug.h" 43#include "llvm/Support/MathExtras.h" 44#include "llvm/Target/TargetLowering.h" 45#include <algorithm> 46#include <cmath> 47#include <iostream> 48using namespace llvm; 49 50namespace { 51 Statistic<> NodesCombined ("dagcombiner", "Number of dag nodes combined"); 52 53 class DAGCombiner { 54 SelectionDAG &DAG; 55 TargetLowering &TLI; 56 bool AfterLegalize; 57 58 // Worklist of all of the nodes that need to be simplified. 59 std::vector<SDNode*> WorkList; 60 61 /// AddUsersToWorkList - When an instruction is simplified, add all users of 62 /// the instruction to the work lists because they might get more simplified 63 /// now. 64 /// 65 void AddUsersToWorkList(SDNode *N) { 66 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 67 UI != UE; ++UI) 68 WorkList.push_back(*UI); 69 } 70 71 /// removeFromWorkList - remove all instances of N from the worklist. 72 void removeFromWorkList(SDNode *N) { 73 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N), 74 WorkList.end()); 75 } 76 77 SDOperand CombineTo(SDNode *N, const std::vector<SDOperand> &To) { 78 ++NodesCombined; 79 DEBUG(std::cerr << "\nReplacing "; N->dump(); 80 std::cerr << "\nWith: "; To[0].Val->dump(); 81 std::cerr << " and " << To.size()-1 << " other values\n"); 82 std::vector<SDNode*> NowDead; 83 DAG.ReplaceAllUsesWith(N, To, &NowDead); 84 85 // Push the new nodes and any users onto the worklist 86 for (unsigned i = 0, e = To.size(); i != e; ++i) { 87 WorkList.push_back(To[i].Val); 88 AddUsersToWorkList(To[i].Val); 89 } 90 91 // Nodes can end up on the worklist more than once. Make sure we do 92 // not process a node that has been replaced. 93 removeFromWorkList(N); 94 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 95 removeFromWorkList(NowDead[i]); 96 97 // Finally, since the node is now dead, remove it from the graph. 98 DAG.DeleteNode(N); 99 return SDOperand(N, 0); 100 } 101 102 SDOperand CombineTo(SDNode *N, SDOperand Res) { 103 std::vector<SDOperand> To; 104 To.push_back(Res); 105 return CombineTo(N, To); 106 } 107 108 SDOperand CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1) { 109 std::vector<SDOperand> To; 110 To.push_back(Res0); 111 To.push_back(Res1); 112 return CombineTo(N, To); 113 } 114 115 /// visit - call the node-specific routine that knows how to fold each 116 /// particular type of node. 117 SDOperand visit(SDNode *N); 118 119 // Visitation implementation - Implement dag node combining for different 120 // node types. The semantics are as follows: 121 // Return Value: 122 // SDOperand.Val == 0 - No change was made 123 // SDOperand.Val == N - N was replaced, is dead, and is already handled. 124 // otherwise - N should be replaced by the returned Operand. 125 // 126 SDOperand visitTokenFactor(SDNode *N); 127 SDOperand visitADD(SDNode *N); 128 SDOperand visitSUB(SDNode *N); 129 SDOperand visitMUL(SDNode *N); 130 SDOperand visitSDIV(SDNode *N); 131 SDOperand visitUDIV(SDNode *N); 132 SDOperand visitSREM(SDNode *N); 133 SDOperand visitUREM(SDNode *N); 134 SDOperand visitMULHU(SDNode *N); 135 SDOperand visitMULHS(SDNode *N); 136 SDOperand visitAND(SDNode *N); 137 SDOperand visitOR(SDNode *N); 138 SDOperand visitXOR(SDNode *N); 139 SDOperand visitSHL(SDNode *N); 140 SDOperand visitSRA(SDNode *N); 141 SDOperand visitSRL(SDNode *N); 142 SDOperand visitCTLZ(SDNode *N); 143 SDOperand visitCTTZ(SDNode *N); 144 SDOperand visitCTPOP(SDNode *N); 145 SDOperand visitSELECT(SDNode *N); 146 SDOperand visitSELECT_CC(SDNode *N); 147 SDOperand visitSETCC(SDNode *N); 148 SDOperand visitADD_PARTS(SDNode *N); 149 SDOperand visitSUB_PARTS(SDNode *N); 150 SDOperand visitSIGN_EXTEND(SDNode *N); 151 SDOperand visitZERO_EXTEND(SDNode *N); 152 SDOperand visitSIGN_EXTEND_INREG(SDNode *N); 153 SDOperand visitTRUNCATE(SDNode *N); 154 SDOperand visitBIT_CONVERT(SDNode *N); 155 156 SDOperand visitFADD(SDNode *N); 157 SDOperand visitFSUB(SDNode *N); 158 SDOperand visitFMUL(SDNode *N); 159 SDOperand visitFDIV(SDNode *N); 160 SDOperand visitFREM(SDNode *N); 161 SDOperand visitSINT_TO_FP(SDNode *N); 162 SDOperand visitUINT_TO_FP(SDNode *N); 163 SDOperand visitFP_TO_SINT(SDNode *N); 164 SDOperand visitFP_TO_UINT(SDNode *N); 165 SDOperand visitFP_ROUND(SDNode *N); 166 SDOperand visitFP_ROUND_INREG(SDNode *N); 167 SDOperand visitFP_EXTEND(SDNode *N); 168 SDOperand visitFNEG(SDNode *N); 169 SDOperand visitFABS(SDNode *N); 170 SDOperand visitBRCOND(SDNode *N); 171 SDOperand visitBRCONDTWOWAY(SDNode *N); 172 SDOperand visitBR_CC(SDNode *N); 173 SDOperand visitBRTWOWAY_CC(SDNode *N); 174 175 SDOperand visitLOAD(SDNode *N); 176 SDOperand visitSTORE(SDNode *N); 177 178 SDOperand visitLOCATION(SDNode *N); 179 SDOperand visitDEBUGLOC(SDNode *N); 180 181 SDOperand ReassociateOps(unsigned Opc, SDOperand LHS, SDOperand RHS); 182 183 bool SimplifySelectOps(SDNode *SELECT, SDOperand LHS, SDOperand RHS); 184 SDOperand SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2); 185 SDOperand SimplifySelectCC(SDOperand N0, SDOperand N1, SDOperand N2, 186 SDOperand N3, ISD::CondCode CC); 187 SDOperand SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1, 188 ISD::CondCode Cond, bool foldBooleans = true); 189 190 SDOperand BuildSDIV(SDNode *N); 191 SDOperand BuildUDIV(SDNode *N); 192public: 193 DAGCombiner(SelectionDAG &D) 194 : DAG(D), TLI(D.getTargetLoweringInfo()), AfterLegalize(false) {} 195 196 /// Run - runs the dag combiner on all nodes in the work list 197 void Run(bool RunningAfterLegalize); 198 }; 199} 200 201struct ms { 202 int64_t m; // magic number 203 int64_t s; // shift amount 204}; 205 206struct mu { 207 uint64_t m; // magic number 208 int64_t a; // add indicator 209 int64_t s; // shift amount 210}; 211 212/// magic - calculate the magic numbers required to codegen an integer sdiv as 213/// a sequence of multiply and shifts. Requires that the divisor not be 0, 1, 214/// or -1. 215static ms magic32(int32_t d) { 216 int32_t p; 217 uint32_t ad, anc, delta, q1, r1, q2, r2, t; 218 const uint32_t two31 = 0x80000000U; 219 struct ms mag; 220 221 ad = abs(d); 222 t = two31 + ((uint32_t)d >> 31); 223 anc = t - 1 - t%ad; // absolute value of nc 224 p = 31; // initialize p 225 q1 = two31/anc; // initialize q1 = 2p/abs(nc) 226 r1 = two31 - q1*anc; // initialize r1 = rem(2p,abs(nc)) 227 q2 = two31/ad; // initialize q2 = 2p/abs(d) 228 r2 = two31 - q2*ad; // initialize r2 = rem(2p,abs(d)) 229 do { 230 p = p + 1; 231 q1 = 2*q1; // update q1 = 2p/abs(nc) 232 r1 = 2*r1; // update r1 = rem(2p/abs(nc)) 233 if (r1 >= anc) { // must be unsigned comparison 234 q1 = q1 + 1; 235 r1 = r1 - anc; 236 } 237 q2 = 2*q2; // update q2 = 2p/abs(d) 238 r2 = 2*r2; // update r2 = rem(2p/abs(d)) 239 if (r2 >= ad) { // must be unsigned comparison 240 q2 = q2 + 1; 241 r2 = r2 - ad; 242 } 243 delta = ad - r2; 244 } while (q1 < delta || (q1 == delta && r1 == 0)); 245 246 mag.m = (int32_t)(q2 + 1); // make sure to sign extend 247 if (d < 0) mag.m = -mag.m; // resulting magic number 248 mag.s = p - 32; // resulting shift 249 return mag; 250} 251 252/// magicu - calculate the magic numbers required to codegen an integer udiv as 253/// a sequence of multiply, add and shifts. Requires that the divisor not be 0. 254static mu magicu32(uint32_t d) { 255 int32_t p; 256 uint32_t nc, delta, q1, r1, q2, r2; 257 struct mu magu; 258 magu.a = 0; // initialize "add" indicator 259 nc = - 1 - (-d)%d; 260 p = 31; // initialize p 261 q1 = 0x80000000/nc; // initialize q1 = 2p/nc 262 r1 = 0x80000000 - q1*nc; // initialize r1 = rem(2p,nc) 263 q2 = 0x7FFFFFFF/d; // initialize q2 = (2p-1)/d 264 r2 = 0x7FFFFFFF - q2*d; // initialize r2 = rem((2p-1),d) 265 do { 266 p = p + 1; 267 if (r1 >= nc - r1 ) { 268 q1 = 2*q1 + 1; // update q1 269 r1 = 2*r1 - nc; // update r1 270 } 271 else { 272 q1 = 2*q1; // update q1 273 r1 = 2*r1; // update r1 274 } 275 if (r2 + 1 >= d - r2) { 276 if (q2 >= 0x7FFFFFFF) magu.a = 1; 277 q2 = 2*q2 + 1; // update q2 278 r2 = 2*r2 + 1 - d; // update r2 279 } 280 else { 281 if (q2 >= 0x80000000) magu.a = 1; 282 q2 = 2*q2; // update q2 283 r2 = 2*r2 + 1; // update r2 284 } 285 delta = d - 1 - r2; 286 } while (p < 64 && (q1 < delta || (q1 == delta && r1 == 0))); 287 magu.m = q2 + 1; // resulting magic number 288 magu.s = p - 32; // resulting shift 289 return magu; 290} 291 292/// magic - calculate the magic numbers required to codegen an integer sdiv as 293/// a sequence of multiply and shifts. Requires that the divisor not be 0, 1, 294/// or -1. 295static ms magic64(int64_t d) { 296 int64_t p; 297 uint64_t ad, anc, delta, q1, r1, q2, r2, t; 298 const uint64_t two63 = 9223372036854775808ULL; // 2^63 299 struct ms mag; 300 301 ad = d >= 0 ? d : -d; 302 t = two63 + ((uint64_t)d >> 63); 303 anc = t - 1 - t%ad; // absolute value of nc 304 p = 63; // initialize p 305 q1 = two63/anc; // initialize q1 = 2p/abs(nc) 306 r1 = two63 - q1*anc; // initialize r1 = rem(2p,abs(nc)) 307 q2 = two63/ad; // initialize q2 = 2p/abs(d) 308 r2 = two63 - q2*ad; // initialize r2 = rem(2p,abs(d)) 309 do { 310 p = p + 1; 311 q1 = 2*q1; // update q1 = 2p/abs(nc) 312 r1 = 2*r1; // update r1 = rem(2p/abs(nc)) 313 if (r1 >= anc) { // must be unsigned comparison 314 q1 = q1 + 1; 315 r1 = r1 - anc; 316 } 317 q2 = 2*q2; // update q2 = 2p/abs(d) 318 r2 = 2*r2; // update r2 = rem(2p/abs(d)) 319 if (r2 >= ad) { // must be unsigned comparison 320 q2 = q2 + 1; 321 r2 = r2 - ad; 322 } 323 delta = ad - r2; 324 } while (q1 < delta || (q1 == delta && r1 == 0)); 325 326 mag.m = q2 + 1; 327 if (d < 0) mag.m = -mag.m; // resulting magic number 328 mag.s = p - 64; // resulting shift 329 return mag; 330} 331 332/// magicu - calculate the magic numbers required to codegen an integer udiv as 333/// a sequence of multiply, add and shifts. Requires that the divisor not be 0. 334static mu magicu64(uint64_t d) 335{ 336 int64_t p; 337 uint64_t nc, delta, q1, r1, q2, r2; 338 struct mu magu; 339 magu.a = 0; // initialize "add" indicator 340 nc = - 1 - (-d)%d; 341 p = 63; // initialize p 342 q1 = 0x8000000000000000ull/nc; // initialize q1 = 2p/nc 343 r1 = 0x8000000000000000ull - q1*nc; // initialize r1 = rem(2p,nc) 344 q2 = 0x7FFFFFFFFFFFFFFFull/d; // initialize q2 = (2p-1)/d 345 r2 = 0x7FFFFFFFFFFFFFFFull - q2*d; // initialize r2 = rem((2p-1),d) 346 do { 347 p = p + 1; 348 if (r1 >= nc - r1 ) { 349 q1 = 2*q1 + 1; // update q1 350 r1 = 2*r1 - nc; // update r1 351 } 352 else { 353 q1 = 2*q1; // update q1 354 r1 = 2*r1; // update r1 355 } 356 if (r2 + 1 >= d - r2) { 357 if (q2 >= 0x7FFFFFFFFFFFFFFFull) magu.a = 1; 358 q2 = 2*q2 + 1; // update q2 359 r2 = 2*r2 + 1 - d; // update r2 360 } 361 else { 362 if (q2 >= 0x8000000000000000ull) magu.a = 1; 363 q2 = 2*q2; // update q2 364 r2 = 2*r2 + 1; // update r2 365 } 366 delta = d - 1 - r2; 367 } while (p < 64 && (q1 < delta || (q1 == delta && r1 == 0))); 368 magu.m = q2 + 1; // resulting magic number 369 magu.s = p - 64; // resulting shift 370 return magu; 371} 372 373// isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc 374// that selects between the values 1 and 0, making it equivalent to a setcc. 375// Also, set the incoming LHS, RHS, and CC references to the appropriate 376// nodes based on the type of node we are checking. This simplifies life a 377// bit for the callers. 378static bool isSetCCEquivalent(SDOperand N, SDOperand &LHS, SDOperand &RHS, 379 SDOperand &CC) { 380 if (N.getOpcode() == ISD::SETCC) { 381 LHS = N.getOperand(0); 382 RHS = N.getOperand(1); 383 CC = N.getOperand(2); 384 return true; 385 } 386 if (N.getOpcode() == ISD::SELECT_CC && 387 N.getOperand(2).getOpcode() == ISD::Constant && 388 N.getOperand(3).getOpcode() == ISD::Constant && 389 cast<ConstantSDNode>(N.getOperand(2))->getValue() == 1 && 390 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) { 391 LHS = N.getOperand(0); 392 RHS = N.getOperand(1); 393 CC = N.getOperand(4); 394 return true; 395 } 396 return false; 397} 398 399// isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only 400// one use. If this is true, it allows the users to invert the operation for 401// free when it is profitable to do so. 402static bool isOneUseSetCC(SDOperand N) { 403 SDOperand N0, N1, N2; 404 if (isSetCCEquivalent(N, N0, N1, N2) && N.Val->hasOneUse()) 405 return true; 406 return false; 407} 408 409// FIXME: This should probably go in the ISD class rather than being duplicated 410// in several files. 411static bool isCommutativeBinOp(unsigned Opcode) { 412 switch (Opcode) { 413 case ISD::ADD: 414 case ISD::MUL: 415 case ISD::AND: 416 case ISD::OR: 417 case ISD::XOR: return true; 418 default: return false; // FIXME: Need commutative info for user ops! 419 } 420} 421 422SDOperand DAGCombiner::ReassociateOps(unsigned Opc, SDOperand N0, SDOperand N1){ 423 MVT::ValueType VT = N0.getValueType(); 424 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use 425 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2)) 426 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) { 427 if (isa<ConstantSDNode>(N1)) { 428 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(1), N1); 429 WorkList.push_back(OpNode.Val); 430 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(0)); 431 } else if (N0.hasOneUse()) { 432 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(0), N1); 433 WorkList.push_back(OpNode.Val); 434 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(1)); 435 } 436 } 437 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use 438 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2)) 439 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) { 440 if (isa<ConstantSDNode>(N0)) { 441 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(1), N0); 442 WorkList.push_back(OpNode.Val); 443 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(0)); 444 } else if (N1.hasOneUse()) { 445 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(0), N0); 446 WorkList.push_back(OpNode.Val); 447 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(1)); 448 } 449 } 450 return SDOperand(); 451} 452 453void DAGCombiner::Run(bool RunningAfterLegalize) { 454 // set the instance variable, so that the various visit routines may use it. 455 AfterLegalize = RunningAfterLegalize; 456 457 // Add all the dag nodes to the worklist. 458 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 459 E = DAG.allnodes_end(); I != E; ++I) 460 WorkList.push_back(I); 461 462 // Create a dummy node (which is not added to allnodes), that adds a reference 463 // to the root node, preventing it from being deleted, and tracking any 464 // changes of the root. 465 HandleSDNode Dummy(DAG.getRoot()); 466 467 // while the worklist isn't empty, inspect the node on the end of it and 468 // try and combine it. 469 while (!WorkList.empty()) { 470 SDNode *N = WorkList.back(); 471 WorkList.pop_back(); 472 473 // If N has no uses, it is dead. Make sure to revisit all N's operands once 474 // N is deleted from the DAG, since they too may now be dead or may have a 475 // reduced number of uses, allowing other xforms. 476 if (N->use_empty() && N != &Dummy) { 477 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 478 WorkList.push_back(N->getOperand(i).Val); 479 480 removeFromWorkList(N); 481 DAG.DeleteNode(N); 482 continue; 483 } 484 485 SDOperand RV = visit(N); 486 if (RV.Val) { 487 ++NodesCombined; 488 // If we get back the same node we passed in, rather than a new node or 489 // zero, we know that the node must have defined multiple values and 490 // CombineTo was used. Since CombineTo takes care of the worklist 491 // mechanics for us, we have no work to do in this case. 492 if (RV.Val != N) { 493 DEBUG(std::cerr << "\nReplacing "; N->dump(); 494 std::cerr << "\nWith: "; RV.Val->dump(); 495 std::cerr << '\n'); 496 std::vector<SDNode*> NowDead; 497 DAG.ReplaceAllUsesWith(N, std::vector<SDOperand>(1, RV), &NowDead); 498 499 // Push the new node and any users onto the worklist 500 WorkList.push_back(RV.Val); 501 AddUsersToWorkList(RV.Val); 502 503 // Nodes can end up on the worklist more than once. Make sure we do 504 // not process a node that has been replaced. 505 removeFromWorkList(N); 506 for (unsigned i = 0, e = NowDead.size(); i != e; ++i) 507 removeFromWorkList(NowDead[i]); 508 509 // Finally, since the node is now dead, remove it from the graph. 510 DAG.DeleteNode(N); 511 } 512 } 513 } 514 515 // If the root changed (e.g. it was a dead load, update the root). 516 DAG.setRoot(Dummy.getValue()); 517} 518 519SDOperand DAGCombiner::visit(SDNode *N) { 520 switch(N->getOpcode()) { 521 default: break; 522 case ISD::TokenFactor: return visitTokenFactor(N); 523 case ISD::ADD: return visitADD(N); 524 case ISD::SUB: return visitSUB(N); 525 case ISD::MUL: return visitMUL(N); 526 case ISD::SDIV: return visitSDIV(N); 527 case ISD::UDIV: return visitUDIV(N); 528 case ISD::SREM: return visitSREM(N); 529 case ISD::UREM: return visitUREM(N); 530 case ISD::MULHU: return visitMULHU(N); 531 case ISD::MULHS: return visitMULHS(N); 532 case ISD::AND: return visitAND(N); 533 case ISD::OR: return visitOR(N); 534 case ISD::XOR: return visitXOR(N); 535 case ISD::SHL: return visitSHL(N); 536 case ISD::SRA: return visitSRA(N); 537 case ISD::SRL: return visitSRL(N); 538 case ISD::CTLZ: return visitCTLZ(N); 539 case ISD::CTTZ: return visitCTTZ(N); 540 case ISD::CTPOP: return visitCTPOP(N); 541 case ISD::SELECT: return visitSELECT(N); 542 case ISD::SELECT_CC: return visitSELECT_CC(N); 543 case ISD::SETCC: return visitSETCC(N); 544 case ISD::ADD_PARTS: return visitADD_PARTS(N); 545 case ISD::SUB_PARTS: return visitSUB_PARTS(N); 546 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N); 547 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N); 548 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N); 549 case ISD::TRUNCATE: return visitTRUNCATE(N); 550 case ISD::BIT_CONVERT: return visitBIT_CONVERT(N); 551 case ISD::FADD: return visitFADD(N); 552 case ISD::FSUB: return visitFSUB(N); 553 case ISD::FMUL: return visitFMUL(N); 554 case ISD::FDIV: return visitFDIV(N); 555 case ISD::FREM: return visitFREM(N); 556 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N); 557 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N); 558 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N); 559 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N); 560 case ISD::FP_ROUND: return visitFP_ROUND(N); 561 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N); 562 case ISD::FP_EXTEND: return visitFP_EXTEND(N); 563 case ISD::FNEG: return visitFNEG(N); 564 case ISD::FABS: return visitFABS(N); 565 case ISD::BRCOND: return visitBRCOND(N); 566 case ISD::BRCONDTWOWAY: return visitBRCONDTWOWAY(N); 567 case ISD::BR_CC: return visitBR_CC(N); 568 case ISD::BRTWOWAY_CC: return visitBRTWOWAY_CC(N); 569 case ISD::LOAD: return visitLOAD(N); 570 case ISD::STORE: return visitSTORE(N); 571 case ISD::LOCATION: return visitLOCATION(N); 572 case ISD::DEBUG_LOC: return visitDEBUGLOC(N); 573 } 574 return SDOperand(); 575} 576 577SDOperand DAGCombiner::visitTokenFactor(SDNode *N) { 578 std::vector<SDOperand> Ops; 579 bool Changed = false; 580 581 // If the token factor has two operands and one is the entry token, replace 582 // the token factor with the other operand. 583 if (N->getNumOperands() == 2) { 584 if (N->getOperand(0).getOpcode() == ISD::EntryToken) 585 return N->getOperand(1); 586 if (N->getOperand(1).getOpcode() == ISD::EntryToken) 587 return N->getOperand(0); 588 } 589 590 // fold (tokenfactor (tokenfactor)) -> tokenfactor 591 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) { 592 SDOperand Op = N->getOperand(i); 593 if (Op.getOpcode() == ISD::TokenFactor && Op.hasOneUse()) { 594 Changed = true; 595 for (unsigned j = 0, e = Op.getNumOperands(); j != e; ++j) 596 Ops.push_back(Op.getOperand(j)); 597 } else { 598 Ops.push_back(Op); 599 } 600 } 601 if (Changed) 602 return DAG.getNode(ISD::TokenFactor, MVT::Other, Ops); 603 return SDOperand(); 604} 605 606SDOperand DAGCombiner::visitADD(SDNode *N) { 607 SDOperand N0 = N->getOperand(0); 608 SDOperand N1 = N->getOperand(1); 609 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 610 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 611 MVT::ValueType VT = N0.getValueType(); 612 613 // fold (add c1, c2) -> c1+c2 614 if (N0C && N1C) 615 return DAG.getNode(ISD::ADD, VT, N0, N1); 616 // canonicalize constant to RHS 617 if (N0C && !N1C) 618 return DAG.getNode(ISD::ADD, VT, N1, N0); 619 // fold (add x, 0) -> x 620 if (N1C && N1C->isNullValue()) 621 return N0; 622 // fold ((c1-A)+c2) -> (c1+c2)-A 623 if (N1C && N0.getOpcode() == ISD::SUB) 624 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0))) 625 return DAG.getNode(ISD::SUB, VT, 626 DAG.getConstant(N1C->getValue()+N0C->getValue(), VT), 627 N0.getOperand(1)); 628 // reassociate add 629 SDOperand RADD = ReassociateOps(ISD::ADD, N0, N1); 630 if (RADD.Val != 0) 631 return RADD; 632 // fold ((0-A) + B) -> B-A 633 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) && 634 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue()) 635 return DAG.getNode(ISD::SUB, VT, N1, N0.getOperand(1)); 636 // fold (A + (0-B)) -> A-B 637 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) && 638 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue()) 639 return DAG.getNode(ISD::SUB, VT, N0, N1.getOperand(1)); 640 // fold (A+(B-A)) -> B 641 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1)) 642 return N1.getOperand(0); 643 return SDOperand(); 644} 645 646SDOperand DAGCombiner::visitSUB(SDNode *N) { 647 SDOperand N0 = N->getOperand(0); 648 SDOperand N1 = N->getOperand(1); 649 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 650 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 651 MVT::ValueType VT = N0.getValueType(); 652 653 // fold (sub x, x) -> 0 654 if (N0 == N1) 655 return DAG.getConstant(0, N->getValueType(0)); 656 // fold (sub c1, c2) -> c1-c2 657 if (N0C && N1C) 658 return DAG.getNode(ISD::SUB, VT, N0, N1); 659 // fold (sub x, c) -> (add x, -c) 660 if (N1C) 661 return DAG.getNode(ISD::ADD, VT, N0, DAG.getConstant(-N1C->getValue(), VT)); 662 // fold (A+B)-A -> B 663 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1) 664 return N0.getOperand(1); 665 // fold (A+B)-B -> A 666 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1) 667 return N0.getOperand(0); 668 return SDOperand(); 669} 670 671SDOperand DAGCombiner::visitMUL(SDNode *N) { 672 SDOperand N0 = N->getOperand(0); 673 SDOperand N1 = N->getOperand(1); 674 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 675 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 676 MVT::ValueType VT = N0.getValueType(); 677 678 // fold (mul c1, c2) -> c1*c2 679 if (N0C && N1C) 680 return DAG.getNode(ISD::MUL, VT, N0, N1); 681 // canonicalize constant to RHS 682 if (N0C && !N1C) 683 return DAG.getNode(ISD::MUL, VT, N1, N0); 684 // fold (mul x, 0) -> 0 685 if (N1C && N1C->isNullValue()) 686 return N1; 687 // fold (mul x, -1) -> 0-x 688 if (N1C && N1C->isAllOnesValue()) 689 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0); 690 // fold (mul x, (1 << c)) -> x << c 691 if (N1C && isPowerOf2_64(N1C->getValue())) 692 return DAG.getNode(ISD::SHL, VT, N0, 693 DAG.getConstant(Log2_64(N1C->getValue()), 694 TLI.getShiftAmountTy())); 695 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c 696 if (N1C && isPowerOf2_64(-N1C->getSignExtended())) { 697 // FIXME: If the input is something that is easily negated (e.g. a 698 // single-use add), we should put the negate there. 699 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), 700 DAG.getNode(ISD::SHL, VT, N0, 701 DAG.getConstant(Log2_64(-N1C->getSignExtended()), 702 TLI.getShiftAmountTy()))); 703 } 704 // reassociate mul 705 SDOperand RMUL = ReassociateOps(ISD::MUL, N0, N1); 706 if (RMUL.Val != 0) 707 return RMUL; 708 return SDOperand(); 709} 710 711SDOperand DAGCombiner::visitSDIV(SDNode *N) { 712 SDOperand N0 = N->getOperand(0); 713 SDOperand N1 = N->getOperand(1); 714 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 715 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 716 MVT::ValueType VT = N->getValueType(0); 717 718 // fold (sdiv c1, c2) -> c1/c2 719 if (N0C && N1C && !N1C->isNullValue()) 720 return DAG.getNode(ISD::SDIV, VT, N0, N1); 721 // fold (sdiv X, 1) -> X 722 if (N1C && N1C->getSignExtended() == 1LL) 723 return N0; 724 // fold (sdiv X, -1) -> 0-X 725 if (N1C && N1C->isAllOnesValue()) 726 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0); 727 // If we know the sign bits of both operands are zero, strength reduce to a 728 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2 729 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1); 730 if (TLI.MaskedValueIsZero(N1, SignBit) && 731 TLI.MaskedValueIsZero(N0, SignBit)) 732 return DAG.getNode(ISD::UDIV, N1.getValueType(), N0, N1); 733 // fold (sdiv X, pow2) -> (add (sra X, log(pow2)), (srl X, sizeof(X)-1)) 734 if (N1C && N1C->getValue() && !TLI.isIntDivCheap() && 735 (isPowerOf2_64(N1C->getSignExtended()) || 736 isPowerOf2_64(-N1C->getSignExtended()))) { 737 // If dividing by powers of two is cheap, then don't perform the following 738 // fold. 739 if (TLI.isPow2DivCheap()) 740 return SDOperand(); 741 int64_t pow2 = N1C->getSignExtended(); 742 int64_t abs2 = pow2 > 0 ? pow2 : -pow2; 743 SDOperand SRL = DAG.getNode(ISD::SRL, VT, N0, 744 DAG.getConstant(MVT::getSizeInBits(VT)-1, 745 TLI.getShiftAmountTy())); 746 WorkList.push_back(SRL.Val); 747 SDOperand SGN = DAG.getNode(ISD::ADD, VT, N0, SRL); 748 WorkList.push_back(SGN.Val); 749 SDOperand SRA = DAG.getNode(ISD::SRA, VT, SGN, 750 DAG.getConstant(Log2_64(abs2), 751 TLI.getShiftAmountTy())); 752 // If we're dividing by a positive value, we're done. Otherwise, we must 753 // negate the result. 754 if (pow2 > 0) 755 return SRA; 756 WorkList.push_back(SRA.Val); 757 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), SRA); 758 } 759 // if integer divide is expensive and we satisfy the requirements, emit an 760 // alternate sequence. 761 if (N1C && (N1C->getSignExtended() < -1 || N1C->getSignExtended() > 1) && 762 !TLI.isIntDivCheap()) { 763 SDOperand Op = BuildSDIV(N); 764 if (Op.Val) return Op; 765 } 766 return SDOperand(); 767} 768 769SDOperand DAGCombiner::visitUDIV(SDNode *N) { 770 SDOperand N0 = N->getOperand(0); 771 SDOperand N1 = N->getOperand(1); 772 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 773 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 774 MVT::ValueType VT = N->getValueType(0); 775 776 // fold (udiv c1, c2) -> c1/c2 777 if (N0C && N1C && !N1C->isNullValue()) 778 return DAG.getNode(ISD::UDIV, VT, N0, N1); 779 // fold (udiv x, (1 << c)) -> x >>u c 780 if (N1C && isPowerOf2_64(N1C->getValue())) 781 return DAG.getNode(ISD::SRL, VT, N0, 782 DAG.getConstant(Log2_64(N1C->getValue()), 783 TLI.getShiftAmountTy())); 784 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2 785 if (N1.getOpcode() == ISD::SHL) { 786 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 787 if (isPowerOf2_64(SHC->getValue())) { 788 MVT::ValueType ADDVT = N1.getOperand(1).getValueType(); 789 return DAG.getNode(ISD::SRL, VT, N0, 790 DAG.getNode(ISD::ADD, ADDVT, N1.getOperand(1), 791 DAG.getConstant(Log2_64(SHC->getValue()), 792 ADDVT))); 793 } 794 } 795 } 796 // fold (udiv x, c) -> alternate 797 if (N1C && N1C->getValue() && !TLI.isIntDivCheap()) { 798 SDOperand Op = BuildUDIV(N); 799 if (Op.Val) return Op; 800 } 801 return SDOperand(); 802} 803 804SDOperand DAGCombiner::visitSREM(SDNode *N) { 805 SDOperand N0 = N->getOperand(0); 806 SDOperand N1 = N->getOperand(1); 807 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 808 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 809 MVT::ValueType VT = N->getValueType(0); 810 811 // fold (srem c1, c2) -> c1%c2 812 if (N0C && N1C && !N1C->isNullValue()) 813 return DAG.getNode(ISD::SREM, VT, N0, N1); 814 // If we know the sign bits of both operands are zero, strength reduce to a 815 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15 816 uint64_t SignBit = 1ULL << (MVT::getSizeInBits(VT)-1); 817 if (TLI.MaskedValueIsZero(N1, SignBit) && 818 TLI.MaskedValueIsZero(N0, SignBit)) 819 return DAG.getNode(ISD::UREM, VT, N0, N1); 820 return SDOperand(); 821} 822 823SDOperand DAGCombiner::visitUREM(SDNode *N) { 824 SDOperand N0 = N->getOperand(0); 825 SDOperand N1 = N->getOperand(1); 826 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 827 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 828 MVT::ValueType VT = N->getValueType(0); 829 830 // fold (urem c1, c2) -> c1%c2 831 if (N0C && N1C && !N1C->isNullValue()) 832 return DAG.getNode(ISD::UREM, VT, N0, N1); 833 // fold (urem x, pow2) -> (and x, pow2-1) 834 if (N1C && !N1C->isNullValue() && isPowerOf2_64(N1C->getValue())) 835 return DAG.getNode(ISD::AND, VT, N0, DAG.getConstant(N1C->getValue()-1,VT)); 836 return SDOperand(); 837} 838 839SDOperand DAGCombiner::visitMULHS(SDNode *N) { 840 SDOperand N0 = N->getOperand(0); 841 SDOperand N1 = N->getOperand(1); 842 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 843 844 // fold (mulhs x, 0) -> 0 845 if (N1C && N1C->isNullValue()) 846 return N1; 847 // fold (mulhs x, 1) -> (sra x, size(x)-1) 848 if (N1C && N1C->getValue() == 1) 849 return DAG.getNode(ISD::SRA, N0.getValueType(), N0, 850 DAG.getConstant(MVT::getSizeInBits(N0.getValueType())-1, 851 TLI.getShiftAmountTy())); 852 return SDOperand(); 853} 854 855SDOperand DAGCombiner::visitMULHU(SDNode *N) { 856 SDOperand N0 = N->getOperand(0); 857 SDOperand N1 = N->getOperand(1); 858 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 859 860 // fold (mulhu x, 0) -> 0 861 if (N1C && N1C->isNullValue()) 862 return N1; 863 // fold (mulhu x, 1) -> 0 864 if (N1C && N1C->getValue() == 1) 865 return DAG.getConstant(0, N0.getValueType()); 866 return SDOperand(); 867} 868 869SDOperand DAGCombiner::visitAND(SDNode *N) { 870 SDOperand N0 = N->getOperand(0); 871 SDOperand N1 = N->getOperand(1); 872 SDOperand LL, LR, RL, RR, CC0, CC1, Old, New; 873 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 874 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 875 MVT::ValueType VT = N1.getValueType(); 876 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 877 878 // fold (and c1, c2) -> c1&c2 879 if (N0C && N1C) 880 return DAG.getNode(ISD::AND, VT, N0, N1); 881 // canonicalize constant to RHS 882 if (N0C && !N1C) 883 return DAG.getNode(ISD::AND, VT, N1, N0); 884 // fold (and x, -1) -> x 885 if (N1C && N1C->isAllOnesValue()) 886 return N0; 887 // if (and x, c) is known to be zero, return 0 888 if (N1C && TLI.MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits))) 889 return DAG.getConstant(0, VT); 890 // fold (and x, c) -> x iff (x & ~c) == 0 891 if (N1C && 892 TLI.MaskedValueIsZero(N0, ~N1C->getValue() & (~0ULL>>(64-OpSizeInBits)))) 893 return N0; 894 // reassociate and 895 SDOperand RAND = ReassociateOps(ISD::AND, N0, N1); 896 if (RAND.Val != 0) 897 return RAND; 898 // fold (and (or x, 0xFFFF), 0xFF) -> 0xFF 899 if (N1C && N0.getOpcode() == ISD::OR) 900 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 901 if ((ORI->getValue() & N1C->getValue()) == N1C->getValue()) 902 return N1; 903 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits. 904 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 905 unsigned InBits = MVT::getSizeInBits(N0.getOperand(0).getValueType()); 906 if (TLI.MaskedValueIsZero(N0.getOperand(0), 907 ~N1C->getValue() & ((1ULL << InBits)-1))) { 908 // We actually want to replace all uses of the any_extend with the 909 // zero_extend, to avoid duplicating things. This will later cause this 910 // AND to be folded. 911 CombineTo(N0.Val, DAG.getNode(ISD::ZERO_EXTEND, N0.getValueType(), 912 N0.getOperand(0))); 913 return SDOperand(); 914 } 915 } 916 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y)) 917 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 918 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 919 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 920 921 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 922 MVT::isInteger(LL.getValueType())) { 923 // fold (X == 0) & (Y == 0) -> (X|Y == 0) 924 if (cast<ConstantSDNode>(LR)->getValue() == 0 && Op1 == ISD::SETEQ) { 925 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 926 WorkList.push_back(ORNode.Val); 927 return DAG.getSetCC(VT, ORNode, LR, Op1); 928 } 929 // fold (X == -1) & (Y == -1) -> (X&Y == -1) 930 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) { 931 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL); 932 WorkList.push_back(ANDNode.Val); 933 return DAG.getSetCC(VT, ANDNode, LR, Op1); 934 } 935 // fold (X > -1) & (Y > -1) -> (X|Y > -1) 936 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) { 937 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 938 WorkList.push_back(ORNode.Val); 939 return DAG.getSetCC(VT, ORNode, LR, Op1); 940 } 941 } 942 // canonicalize equivalent to ll == rl 943 if (LL == RR && LR == RL) { 944 Op1 = ISD::getSetCCSwappedOperands(Op1); 945 std::swap(RL, RR); 946 } 947 if (LL == RL && LR == RR) { 948 bool isInteger = MVT::isInteger(LL.getValueType()); 949 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger); 950 if (Result != ISD::SETCC_INVALID) 951 return DAG.getSetCC(N0.getValueType(), LL, LR, Result); 952 } 953 } 954 // fold (and (zext x), (zext y)) -> (zext (and x, y)) 955 if (N0.getOpcode() == ISD::ZERO_EXTEND && 956 N1.getOpcode() == ISD::ZERO_EXTEND && 957 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) { 958 SDOperand ANDNode = DAG.getNode(ISD::AND, N0.getOperand(0).getValueType(), 959 N0.getOperand(0), N1.getOperand(0)); 960 WorkList.push_back(ANDNode.Val); 961 return DAG.getNode(ISD::ZERO_EXTEND, VT, ANDNode); 962 } 963 // fold (and (shl/srl/sra x), (shl/srl/sra y)) -> (shl/srl/sra (and x, y)) 964 if (((N0.getOpcode() == ISD::SHL && N1.getOpcode() == ISD::SHL) || 965 (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SRL) || 966 (N0.getOpcode() == ISD::SRA && N1.getOpcode() == ISD::SRA)) && 967 N0.getOperand(1) == N1.getOperand(1)) { 968 SDOperand ANDNode = DAG.getNode(ISD::AND, N0.getOperand(0).getValueType(), 969 N0.getOperand(0), N1.getOperand(0)); 970 WorkList.push_back(ANDNode.Val); 971 return DAG.getNode(N0.getOpcode(), VT, ANDNode, N0.getOperand(1)); 972 } 973 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1) 974 // fold (and (sra)) -> (and (srl)) when possible. 975 if (TLI.DemandedBitsAreZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits), Old, 976 New, DAG)) { 977 WorkList.push_back(N); 978 CombineTo(Old.Val, New); 979 return SDOperand(); 980 } 981 // FIXME: DemandedBitsAreZero cannot currently handle AND with non-constant 982 // RHS and propagate known cleared bits to LHS. For this reason, we must keep 983 // this fold, for now, for the following testcase: 984 // 985 //int %test2(uint %mode.0.i.0) { 986 // %tmp.79 = cast uint %mode.0.i.0 to int 987 // %tmp.80 = shr int %tmp.79, ubyte 15 988 // %tmp.81 = shr uint %mode.0.i.0, ubyte 16 989 // %tmp.82 = cast uint %tmp.81 to int 990 // %tmp.83 = and int %tmp.80, %tmp.82 991 // ret int %tmp.83 992 //} 993 // fold (and (sra)) -> (and (srl)) when possible. 994 if (N0.getOpcode() == ISD::SRA && N0.Val->hasOneUse()) { 995 if (ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 996 // If the RHS of the AND has zeros where the sign bits of the SRA will 997 // land, turn the SRA into an SRL. 998 if (TLI.MaskedValueIsZero(N1, (~0ULL << (OpSizeInBits-N01C->getValue())) & 999 (~0ULL>>(64-OpSizeInBits)))) { 1000 WorkList.push_back(N); 1001 CombineTo(N0.Val, DAG.getNode(ISD::SRL, VT, N0.getOperand(0), 1002 N0.getOperand(1))); 1003 return SDOperand(); 1004 } 1005 } 1006 } 1007 // fold (zext_inreg (extload x)) -> (zextload x) 1008 if (N0.getOpcode() == ISD::EXTLOAD) { 1009 MVT::ValueType EVT = cast<VTSDNode>(N0.getOperand(3))->getVT(); 1010 // If we zero all the possible extended bits, then we can turn this into 1011 // a zextload if we are running before legalize or the operation is legal. 1012 if (TLI.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) && 1013 (!AfterLegalize || TLI.isOperationLegal(ISD::ZEXTLOAD, EVT))) { 1014 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0), 1015 N0.getOperand(1), N0.getOperand(2), 1016 EVT); 1017 WorkList.push_back(N); 1018 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 1019 return SDOperand(); 1020 } 1021 } 1022 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use 1023 if (N0.getOpcode() == ISD::SEXTLOAD && N0.hasOneUse()) { 1024 MVT::ValueType EVT = cast<VTSDNode>(N0.getOperand(3))->getVT(); 1025 // If we zero all the possible extended bits, then we can turn this into 1026 // a zextload if we are running before legalize or the operation is legal. 1027 if (TLI.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) && 1028 (!AfterLegalize || TLI.isOperationLegal(ISD::ZEXTLOAD, EVT))) { 1029 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0), 1030 N0.getOperand(1), N0.getOperand(2), 1031 EVT); 1032 WorkList.push_back(N); 1033 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 1034 return SDOperand(); 1035 } 1036 } 1037 return SDOperand(); 1038} 1039 1040SDOperand DAGCombiner::visitOR(SDNode *N) { 1041 SDOperand N0 = N->getOperand(0); 1042 SDOperand N1 = N->getOperand(1); 1043 SDOperand LL, LR, RL, RR, CC0, CC1; 1044 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1045 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1046 MVT::ValueType VT = N1.getValueType(); 1047 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 1048 1049 // fold (or c1, c2) -> c1|c2 1050 if (N0C && N1C) 1051 return DAG.getNode(ISD::OR, VT, N0, N1); 1052 // canonicalize constant to RHS 1053 if (N0C && !N1C) 1054 return DAG.getNode(ISD::OR, VT, N1, N0); 1055 // fold (or x, 0) -> x 1056 if (N1C && N1C->isNullValue()) 1057 return N0; 1058 // fold (or x, -1) -> -1 1059 if (N1C && N1C->isAllOnesValue()) 1060 return N1; 1061 // fold (or x, c) -> c iff (x & ~c) == 0 1062 if (N1C && 1063 TLI.MaskedValueIsZero(N0,~N1C->getValue() & (~0ULL>>(64-OpSizeInBits)))) 1064 return N1; 1065 // reassociate or 1066 SDOperand ROR = ReassociateOps(ISD::OR, N0, N1); 1067 if (ROR.Val != 0) 1068 return ROR; 1069 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2) 1070 if (N1C && N0.getOpcode() == ISD::AND && N0.Val->hasOneUse() && 1071 isa<ConstantSDNode>(N0.getOperand(1))) { 1072 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1)); 1073 return DAG.getNode(ISD::AND, VT, DAG.getNode(ISD::OR, VT, N0.getOperand(0), 1074 N1), 1075 DAG.getConstant(N1C->getValue() | C1->getValue(), VT)); 1076 } 1077 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y)) 1078 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 1079 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 1080 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 1081 1082 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 1083 MVT::isInteger(LL.getValueType())) { 1084 // fold (X != 0) | (Y != 0) -> (X|Y != 0) 1085 // fold (X < 0) | (Y < 0) -> (X|Y < 0) 1086 if (cast<ConstantSDNode>(LR)->getValue() == 0 && 1087 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) { 1088 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 1089 WorkList.push_back(ORNode.Val); 1090 return DAG.getSetCC(VT, ORNode, LR, Op1); 1091 } 1092 // fold (X != -1) | (Y != -1) -> (X&Y != -1) 1093 // fold (X > -1) | (Y > -1) -> (X&Y > -1) 1094 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && 1095 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) { 1096 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL); 1097 WorkList.push_back(ANDNode.Val); 1098 return DAG.getSetCC(VT, ANDNode, LR, Op1); 1099 } 1100 } 1101 // canonicalize equivalent to ll == rl 1102 if (LL == RR && LR == RL) { 1103 Op1 = ISD::getSetCCSwappedOperands(Op1); 1104 std::swap(RL, RR); 1105 } 1106 if (LL == RL && LR == RR) { 1107 bool isInteger = MVT::isInteger(LL.getValueType()); 1108 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger); 1109 if (Result != ISD::SETCC_INVALID) 1110 return DAG.getSetCC(N0.getValueType(), LL, LR, Result); 1111 } 1112 } 1113 // fold (or (zext x), (zext y)) -> (zext (or x, y)) 1114 if (N0.getOpcode() == ISD::ZERO_EXTEND && 1115 N1.getOpcode() == ISD::ZERO_EXTEND && 1116 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) { 1117 SDOperand ORNode = DAG.getNode(ISD::OR, N0.getOperand(0).getValueType(), 1118 N0.getOperand(0), N1.getOperand(0)); 1119 WorkList.push_back(ORNode.Val); 1120 return DAG.getNode(ISD::ZERO_EXTEND, VT, ORNode); 1121 } 1122 // fold (or (shl/srl/sra x), (shl/srl/sra y)) -> (shl/srl/sra (or x, y)) 1123 if (((N0.getOpcode() == ISD::SHL && N1.getOpcode() == ISD::SHL) || 1124 (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SRL) || 1125 (N0.getOpcode() == ISD::SRA && N1.getOpcode() == ISD::SRA)) && 1126 N0.getOperand(1) == N1.getOperand(1)) { 1127 SDOperand ORNode = DAG.getNode(ISD::OR, N0.getOperand(0).getValueType(), 1128 N0.getOperand(0), N1.getOperand(0)); 1129 WorkList.push_back(ORNode.Val); 1130 return DAG.getNode(N0.getOpcode(), VT, ORNode, N0.getOperand(1)); 1131 } 1132 // canonicalize shl to left side in a shl/srl pair, to match rotate 1133 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL) 1134 std::swap(N0, N1); 1135 // check for rotl, rotr 1136 if (N0.getOpcode() == ISD::SHL && N1.getOpcode() == ISD::SRL && 1137 N0.getOperand(0) == N1.getOperand(0) && 1138 TLI.isOperationLegal(ISD::ROTL, VT) && TLI.isTypeLegal(VT)) { 1139 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1) 1140 if (N0.getOperand(1).getOpcode() == ISD::Constant && 1141 N1.getOperand(1).getOpcode() == ISD::Constant) { 1142 uint64_t c1val = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 1143 uint64_t c2val = cast<ConstantSDNode>(N1.getOperand(1))->getValue(); 1144 if ((c1val + c2val) == OpSizeInBits) 1145 return DAG.getNode(ISD::ROTL, VT, N0.getOperand(0), N0.getOperand(1)); 1146 } 1147 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y) 1148 if (N1.getOperand(1).getOpcode() == ISD::SUB && 1149 N0.getOperand(1) == N1.getOperand(1).getOperand(1)) 1150 if (ConstantSDNode *SUBC = 1151 dyn_cast<ConstantSDNode>(N1.getOperand(1).getOperand(0))) 1152 if (SUBC->getValue() == OpSizeInBits) 1153 return DAG.getNode(ISD::ROTL, VT, N0.getOperand(0), N0.getOperand(1)); 1154 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y) 1155 if (N0.getOperand(1).getOpcode() == ISD::SUB && 1156 N1.getOperand(1) == N0.getOperand(1).getOperand(1)) 1157 if (ConstantSDNode *SUBC = 1158 dyn_cast<ConstantSDNode>(N0.getOperand(1).getOperand(0))) 1159 if (SUBC->getValue() == OpSizeInBits) { 1160 if (TLI.isOperationLegal(ISD::ROTR, VT) && TLI.isTypeLegal(VT)) 1161 return DAG.getNode(ISD::ROTR, VT, N0.getOperand(0), 1162 N1.getOperand(1)); 1163 else 1164 return DAG.getNode(ISD::ROTL, VT, N0.getOperand(0), 1165 N0.getOperand(1)); 1166 } 1167 } 1168 return SDOperand(); 1169} 1170 1171SDOperand DAGCombiner::visitXOR(SDNode *N) { 1172 SDOperand N0 = N->getOperand(0); 1173 SDOperand N1 = N->getOperand(1); 1174 SDOperand LHS, RHS, CC; 1175 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1176 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1177 MVT::ValueType VT = N0.getValueType(); 1178 1179 // fold (xor c1, c2) -> c1^c2 1180 if (N0C && N1C) 1181 return DAG.getNode(ISD::XOR, VT, N0, N1); 1182 // canonicalize constant to RHS 1183 if (N0C && !N1C) 1184 return DAG.getNode(ISD::XOR, VT, N1, N0); 1185 // fold (xor x, 0) -> x 1186 if (N1C && N1C->isNullValue()) 1187 return N0; 1188 // reassociate xor 1189 SDOperand RXOR = ReassociateOps(ISD::XOR, N0, N1); 1190 if (RXOR.Val != 0) 1191 return RXOR; 1192 // fold !(x cc y) -> (x !cc y) 1193 if (N1C && N1C->getValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) { 1194 bool isInt = MVT::isInteger(LHS.getValueType()); 1195 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(), 1196 isInt); 1197 if (N0.getOpcode() == ISD::SETCC) 1198 return DAG.getSetCC(VT, LHS, RHS, NotCC); 1199 if (N0.getOpcode() == ISD::SELECT_CC) 1200 return DAG.getSelectCC(LHS, RHS, N0.getOperand(2),N0.getOperand(3),NotCC); 1201 assert(0 && "Unhandled SetCC Equivalent!"); 1202 abort(); 1203 } 1204 // fold !(x or y) -> (!x and !y) iff x or y are setcc 1205 if (N1C && N1C->getValue() == 1 && 1206 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 1207 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1); 1208 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) { 1209 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 1210 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS 1211 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS 1212 WorkList.push_back(LHS.Val); WorkList.push_back(RHS.Val); 1213 return DAG.getNode(NewOpcode, VT, LHS, RHS); 1214 } 1215 } 1216 // fold !(x or y) -> (!x and !y) iff x or y are constants 1217 if (N1C && N1C->isAllOnesValue() && 1218 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 1219 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1); 1220 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) { 1221 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 1222 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS 1223 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS 1224 WorkList.push_back(LHS.Val); WorkList.push_back(RHS.Val); 1225 return DAG.getNode(NewOpcode, VT, LHS, RHS); 1226 } 1227 } 1228 // fold (xor (xor x, c1), c2) -> (xor x, c1^c2) 1229 if (N1C && N0.getOpcode() == ISD::XOR) { 1230 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0)); 1231 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 1232 if (N00C) 1233 return DAG.getNode(ISD::XOR, VT, N0.getOperand(1), 1234 DAG.getConstant(N1C->getValue()^N00C->getValue(), VT)); 1235 if (N01C) 1236 return DAG.getNode(ISD::XOR, VT, N0.getOperand(0), 1237 DAG.getConstant(N1C->getValue()^N01C->getValue(), VT)); 1238 } 1239 // fold (xor x, x) -> 0 1240 if (N0 == N1) 1241 return DAG.getConstant(0, VT); 1242 // fold (xor (zext x), (zext y)) -> (zext (xor x, y)) 1243 if (N0.getOpcode() == ISD::ZERO_EXTEND && 1244 N1.getOpcode() == ISD::ZERO_EXTEND && 1245 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) { 1246 SDOperand XORNode = DAG.getNode(ISD::XOR, N0.getOperand(0).getValueType(), 1247 N0.getOperand(0), N1.getOperand(0)); 1248 WorkList.push_back(XORNode.Val); 1249 return DAG.getNode(ISD::ZERO_EXTEND, VT, XORNode); 1250 } 1251 // fold (xor (shl/srl/sra x), (shl/srl/sra y)) -> (shl/srl/sra (xor x, y)) 1252 if (((N0.getOpcode() == ISD::SHL && N1.getOpcode() == ISD::SHL) || 1253 (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SRL) || 1254 (N0.getOpcode() == ISD::SRA && N1.getOpcode() == ISD::SRA)) && 1255 N0.getOperand(1) == N1.getOperand(1)) { 1256 SDOperand XORNode = DAG.getNode(ISD::XOR, N0.getOperand(0).getValueType(), 1257 N0.getOperand(0), N1.getOperand(0)); 1258 WorkList.push_back(XORNode.Val); 1259 return DAG.getNode(N0.getOpcode(), VT, XORNode, N0.getOperand(1)); 1260 } 1261 return SDOperand(); 1262} 1263 1264SDOperand DAGCombiner::visitSHL(SDNode *N) { 1265 SDOperand N0 = N->getOperand(0); 1266 SDOperand N1 = N->getOperand(1); 1267 SDOperand Old = SDOperand(); 1268 SDOperand New = SDOperand(); 1269 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1270 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1271 MVT::ValueType VT = N0.getValueType(); 1272 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 1273 1274 // fold (shl c1, c2) -> c1<<c2 1275 if (N0C && N1C) 1276 return DAG.getNode(ISD::SHL, VT, N0, N1); 1277 // fold (shl 0, x) -> 0 1278 if (N0C && N0C->isNullValue()) 1279 return N0; 1280 // fold (shl x, c >= size(x)) -> undef 1281 if (N1C && N1C->getValue() >= OpSizeInBits) 1282 return DAG.getNode(ISD::UNDEF, VT); 1283 // fold (shl x, 0) -> x 1284 if (N1C && N1C->isNullValue()) 1285 return N0; 1286 // if (shl x, c) is known to be zero, return 0 1287 if (N1C && TLI.MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits))) 1288 return DAG.getConstant(0, VT); 1289 if (N1C && TLI.DemandedBitsAreZero(SDOperand(N,0), ~0ULL >> (64-OpSizeInBits), 1290 Old, New, DAG)) { 1291 WorkList.push_back(N); 1292 CombineTo(Old.Val, New); 1293 return SDOperand(); 1294 } 1295 // fold (shl (shl x, c1), c2) -> 0 or (shl x, c1+c2) 1296 if (N1C && N0.getOpcode() == ISD::SHL && 1297 N0.getOperand(1).getOpcode() == ISD::Constant) { 1298 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 1299 uint64_t c2 = N1C->getValue(); 1300 if (c1 + c2 > OpSizeInBits) 1301 return DAG.getConstant(0, VT); 1302 return DAG.getNode(ISD::SHL, VT, N0.getOperand(0), 1303 DAG.getConstant(c1 + c2, N1.getValueType())); 1304 } 1305 // fold (shl (srl x, c1), c2) -> (shl (and x, -1 << c1), c2-c1) or 1306 // (srl (and x, -1 << c1), c1-c2) 1307 if (N1C && N0.getOpcode() == ISD::SRL && 1308 N0.getOperand(1).getOpcode() == ISD::Constant) { 1309 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 1310 uint64_t c2 = N1C->getValue(); 1311 SDOperand Mask = DAG.getNode(ISD::AND, VT, N0.getOperand(0), 1312 DAG.getConstant(~0ULL << c1, VT)); 1313 if (c2 > c1) 1314 return DAG.getNode(ISD::SHL, VT, Mask, 1315 DAG.getConstant(c2-c1, N1.getValueType())); 1316 else 1317 return DAG.getNode(ISD::SRL, VT, Mask, 1318 DAG.getConstant(c1-c2, N1.getValueType())); 1319 } 1320 // fold (shl (sra x, c1), c1) -> (and x, -1 << c1) 1321 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) 1322 return DAG.getNode(ISD::AND, VT, N0.getOperand(0), 1323 DAG.getConstant(~0ULL << N1C->getValue(), VT)); 1324 return SDOperand(); 1325} 1326 1327SDOperand DAGCombiner::visitSRA(SDNode *N) { 1328 SDOperand N0 = N->getOperand(0); 1329 SDOperand N1 = N->getOperand(1); 1330 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1331 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1332 MVT::ValueType VT = N0.getValueType(); 1333 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 1334 1335 // fold (sra c1, c2) -> c1>>c2 1336 if (N0C && N1C) 1337 return DAG.getNode(ISD::SRA, VT, N0, N1); 1338 // fold (sra 0, x) -> 0 1339 if (N0C && N0C->isNullValue()) 1340 return N0; 1341 // fold (sra -1, x) -> -1 1342 if (N0C && N0C->isAllOnesValue()) 1343 return N0; 1344 // fold (sra x, c >= size(x)) -> undef 1345 if (N1C && N1C->getValue() >= OpSizeInBits) 1346 return DAG.getNode(ISD::UNDEF, VT); 1347 // fold (sra x, 0) -> x 1348 if (N1C && N1C->isNullValue()) 1349 return N0; 1350 // If the sign bit is known to be zero, switch this to a SRL. 1351 if (TLI.MaskedValueIsZero(N0, (1ULL << (OpSizeInBits-1)))) 1352 return DAG.getNode(ISD::SRL, VT, N0, N1); 1353 return SDOperand(); 1354} 1355 1356SDOperand DAGCombiner::visitSRL(SDNode *N) { 1357 SDOperand N0 = N->getOperand(0); 1358 SDOperand N1 = N->getOperand(1); 1359 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1360 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1361 MVT::ValueType VT = N0.getValueType(); 1362 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 1363 1364 // fold (srl c1, c2) -> c1 >>u c2 1365 if (N0C && N1C) 1366 return DAG.getNode(ISD::SRL, VT, N0, N1); 1367 // fold (srl 0, x) -> 0 1368 if (N0C && N0C->isNullValue()) 1369 return N0; 1370 // fold (srl x, c >= size(x)) -> undef 1371 if (N1C && N1C->getValue() >= OpSizeInBits) 1372 return DAG.getNode(ISD::UNDEF, VT); 1373 // fold (srl x, 0) -> x 1374 if (N1C && N1C->isNullValue()) 1375 return N0; 1376 // if (srl x, c) is known to be zero, return 0 1377 if (N1C && TLI.MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits))) 1378 return DAG.getConstant(0, VT); 1379 // fold (srl (srl x, c1), c2) -> 0 or (srl x, c1+c2) 1380 if (N1C && N0.getOpcode() == ISD::SRL && 1381 N0.getOperand(1).getOpcode() == ISD::Constant) { 1382 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 1383 uint64_t c2 = N1C->getValue(); 1384 if (c1 + c2 > OpSizeInBits) 1385 return DAG.getConstant(0, VT); 1386 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0), 1387 DAG.getConstant(c1 + c2, N1.getValueType())); 1388 } 1389 return SDOperand(); 1390} 1391 1392SDOperand DAGCombiner::visitCTLZ(SDNode *N) { 1393 SDOperand N0 = N->getOperand(0); 1394 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1395 MVT::ValueType VT = N->getValueType(0); 1396 1397 // fold (ctlz c1) -> c2 1398 if (N0C) 1399 return DAG.getNode(ISD::CTLZ, VT, N0); 1400 return SDOperand(); 1401} 1402 1403SDOperand DAGCombiner::visitCTTZ(SDNode *N) { 1404 SDOperand N0 = N->getOperand(0); 1405 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1406 MVT::ValueType VT = N->getValueType(0); 1407 1408 // fold (cttz c1) -> c2 1409 if (N0C) 1410 return DAG.getNode(ISD::CTTZ, VT, N0); 1411 return SDOperand(); 1412} 1413 1414SDOperand DAGCombiner::visitCTPOP(SDNode *N) { 1415 SDOperand N0 = N->getOperand(0); 1416 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1417 MVT::ValueType VT = N->getValueType(0); 1418 1419 // fold (ctpop c1) -> c2 1420 if (N0C) 1421 return DAG.getNode(ISD::CTPOP, VT, N0); 1422 return SDOperand(); 1423} 1424 1425SDOperand DAGCombiner::visitSELECT(SDNode *N) { 1426 SDOperand N0 = N->getOperand(0); 1427 SDOperand N1 = N->getOperand(1); 1428 SDOperand N2 = N->getOperand(2); 1429 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1430 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1431 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2); 1432 MVT::ValueType VT = N->getValueType(0); 1433 1434 // fold select C, X, X -> X 1435 if (N1 == N2) 1436 return N1; 1437 // fold select true, X, Y -> X 1438 if (N0C && !N0C->isNullValue()) 1439 return N1; 1440 // fold select false, X, Y -> Y 1441 if (N0C && N0C->isNullValue()) 1442 return N2; 1443 // fold select C, 1, X -> C | X 1444 if (MVT::i1 == VT && N1C && N1C->getValue() == 1) 1445 return DAG.getNode(ISD::OR, VT, N0, N2); 1446 // fold select C, 0, X -> ~C & X 1447 // FIXME: this should check for C type == X type, not i1? 1448 if (MVT::i1 == VT && N1C && N1C->isNullValue()) { 1449 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT)); 1450 WorkList.push_back(XORNode.Val); 1451 return DAG.getNode(ISD::AND, VT, XORNode, N2); 1452 } 1453 // fold select C, X, 1 -> ~C | X 1454 if (MVT::i1 == VT && N2C && N2C->getValue() == 1) { 1455 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT)); 1456 WorkList.push_back(XORNode.Val); 1457 return DAG.getNode(ISD::OR, VT, XORNode, N1); 1458 } 1459 // fold select C, X, 0 -> C & X 1460 // FIXME: this should check for C type == X type, not i1? 1461 if (MVT::i1 == VT && N2C && N2C->isNullValue()) 1462 return DAG.getNode(ISD::AND, VT, N0, N1); 1463 // fold X ? X : Y --> X ? 1 : Y --> X | Y 1464 if (MVT::i1 == VT && N0 == N1) 1465 return DAG.getNode(ISD::OR, VT, N0, N2); 1466 // fold X ? Y : X --> X ? Y : 0 --> X & Y 1467 if (MVT::i1 == VT && N0 == N2) 1468 return DAG.getNode(ISD::AND, VT, N0, N1); 1469 // If we can fold this based on the true/false value, do so. 1470 if (SimplifySelectOps(N, N1, N2)) 1471 return SDOperand(); 1472 // fold selects based on a setcc into other things, such as min/max/abs 1473 if (N0.getOpcode() == ISD::SETCC) 1474 // FIXME: 1475 // Check against MVT::Other for SELECT_CC, which is a workaround for targets 1476 // having to say they don't support SELECT_CC on every type the DAG knows 1477 // about, since there is no way to mark an opcode illegal at all value types 1478 if (TLI.isOperationLegal(ISD::SELECT_CC, MVT::Other)) 1479 return DAG.getNode(ISD::SELECT_CC, VT, N0.getOperand(0), N0.getOperand(1), 1480 N1, N2, N0.getOperand(2)); 1481 else 1482 return SimplifySelect(N0, N1, N2); 1483 return SDOperand(); 1484} 1485 1486SDOperand DAGCombiner::visitSELECT_CC(SDNode *N) { 1487 SDOperand N0 = N->getOperand(0); 1488 SDOperand N1 = N->getOperand(1); 1489 SDOperand N2 = N->getOperand(2); 1490 SDOperand N3 = N->getOperand(3); 1491 SDOperand N4 = N->getOperand(4); 1492 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1493 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1494 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2); 1495 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get(); 1496 1497 // Determine if the condition we're dealing with is constant 1498 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false); 1499 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val); 1500 1501 // fold select_cc lhs, rhs, x, x, cc -> x 1502 if (N2 == N3) 1503 return N2; 1504 1505 // If we can fold this based on the true/false value, do so. 1506 if (SimplifySelectOps(N, N2, N3)) 1507 return SDOperand(); 1508 1509 // fold select_cc into other things, such as min/max/abs 1510 return SimplifySelectCC(N0, N1, N2, N3, CC); 1511} 1512 1513SDOperand DAGCombiner::visitSETCC(SDNode *N) { 1514 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1), 1515 cast<CondCodeSDNode>(N->getOperand(2))->get()); 1516} 1517 1518SDOperand DAGCombiner::visitADD_PARTS(SDNode *N) { 1519 SDOperand LHSLo = N->getOperand(0); 1520 SDOperand RHSLo = N->getOperand(2); 1521 MVT::ValueType VT = LHSLo.getValueType(); 1522 1523 // fold (a_Hi, 0) + (b_Hi, b_Lo) -> (b_Hi + a_Hi, b_Lo) 1524 if (TLI.MaskedValueIsZero(LHSLo, (1ULL << MVT::getSizeInBits(VT))-1)) { 1525 SDOperand Hi = DAG.getNode(ISD::ADD, VT, N->getOperand(1), 1526 N->getOperand(3)); 1527 WorkList.push_back(Hi.Val); 1528 CombineTo(N, RHSLo, Hi); 1529 return SDOperand(); 1530 } 1531 // fold (a_Hi, a_Lo) + (b_Hi, 0) -> (a_Hi + b_Hi, a_Lo) 1532 if (TLI.MaskedValueIsZero(RHSLo, (1ULL << MVT::getSizeInBits(VT))-1)) { 1533 SDOperand Hi = DAG.getNode(ISD::ADD, VT, N->getOperand(1), 1534 N->getOperand(3)); 1535 WorkList.push_back(Hi.Val); 1536 CombineTo(N, LHSLo, Hi); 1537 return SDOperand(); 1538 } 1539 return SDOperand(); 1540} 1541 1542SDOperand DAGCombiner::visitSUB_PARTS(SDNode *N) { 1543 SDOperand LHSLo = N->getOperand(0); 1544 SDOperand RHSLo = N->getOperand(2); 1545 MVT::ValueType VT = LHSLo.getValueType(); 1546 1547 // fold (a_Hi, a_Lo) - (b_Hi, 0) -> (a_Hi - b_Hi, a_Lo) 1548 if (TLI.MaskedValueIsZero(RHSLo, (1ULL << MVT::getSizeInBits(VT))-1)) { 1549 SDOperand Hi = DAG.getNode(ISD::SUB, VT, N->getOperand(1), 1550 N->getOperand(3)); 1551 WorkList.push_back(Hi.Val); 1552 CombineTo(N, LHSLo, Hi); 1553 return SDOperand(); 1554 } 1555 return SDOperand(); 1556} 1557 1558SDOperand DAGCombiner::visitSIGN_EXTEND(SDNode *N) { 1559 SDOperand N0 = N->getOperand(0); 1560 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1561 MVT::ValueType VT = N->getValueType(0); 1562 1563 // fold (sext c1) -> c1 1564 if (N0C) 1565 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0); 1566 // fold (sext (sext x)) -> (sext x) 1567 if (N0.getOpcode() == ISD::SIGN_EXTEND) 1568 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0.getOperand(0)); 1569 // fold (sext (truncate x)) -> (sextinreg x) iff x size == sext size. 1570 if (N0.getOpcode() == ISD::TRUNCATE && N0.getOperand(0).getValueType() == VT&& 1571 (!AfterLegalize || 1572 TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, N0.getValueType()))) 1573 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), 1574 DAG.getValueType(N0.getValueType())); 1575 // fold (sext (load x)) -> (sext (truncate (sextload x))) 1576 if (N0.getOpcode() == ISD::LOAD && N0.hasOneUse() && 1577 (!AfterLegalize||TLI.isOperationLegal(ISD::SEXTLOAD, N0.getValueType()))){ 1578 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N0.getOperand(0), 1579 N0.getOperand(1), N0.getOperand(2), 1580 N0.getValueType()); 1581 CombineTo(N, ExtLoad); 1582 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 1583 ExtLoad.getValue(1)); 1584 return SDOperand(); 1585 } 1586 1587 // fold (sext (sextload x)) -> (sext (truncate (sextload x))) 1588 // fold (sext ( extload x)) -> (sext (truncate (sextload x))) 1589 if ((N0.getOpcode() == ISD::SEXTLOAD || N0.getOpcode() == ISD::EXTLOAD) && 1590 N0.hasOneUse()) { 1591 SDOperand ExtLoad = DAG.getNode(ISD::SEXTLOAD, VT, N0.getOperand(0), 1592 N0.getOperand(1), N0.getOperand(2), 1593 N0.getOperand(3)); 1594 CombineTo(N, ExtLoad); 1595 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 1596 ExtLoad.getValue(1)); 1597 return SDOperand(); 1598 } 1599 1600 return SDOperand(); 1601} 1602 1603SDOperand DAGCombiner::visitZERO_EXTEND(SDNode *N) { 1604 SDOperand N0 = N->getOperand(0); 1605 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1606 MVT::ValueType VT = N->getValueType(0); 1607 1608 // fold (zext c1) -> c1 1609 if (N0C) 1610 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0); 1611 // fold (zext (zext x)) -> (zext x) 1612 if (N0.getOpcode() == ISD::ZERO_EXTEND) 1613 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0.getOperand(0)); 1614 // fold (zext (truncate x)) -> (zextinreg x) iff x size == zext size. 1615 if (N0.getOpcode() == ISD::TRUNCATE && N0.getOperand(0).getValueType() == VT&& 1616 (!AfterLegalize || TLI.isOperationLegal(ISD::AND, N0.getValueType()))) 1617 return DAG.getZeroExtendInReg(N0.getOperand(0), N0.getValueType()); 1618 // fold (zext (load x)) -> (zext (truncate (zextload x))) 1619 if (N0.getOpcode() == ISD::LOAD && N0.hasOneUse() && 1620 (!AfterLegalize||TLI.isOperationLegal(ISD::ZEXTLOAD, N0.getValueType()))){ 1621 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, N0.getOperand(0), 1622 N0.getOperand(1), N0.getOperand(2), 1623 N0.getValueType()); 1624 CombineTo(N, ExtLoad); 1625 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 1626 ExtLoad.getValue(1)); 1627 return SDOperand(); 1628 } 1629 1630 // fold (zext (zextload x)) -> (zext (truncate (zextload x))) 1631 // fold (zext ( extload x)) -> (zext (truncate (zextload x))) 1632 if ((N0.getOpcode() == ISD::ZEXTLOAD || N0.getOpcode() == ISD::EXTLOAD) && 1633 N0.hasOneUse()) { 1634 SDOperand ExtLoad = DAG.getNode(ISD::ZEXTLOAD, VT, N0.getOperand(0), 1635 N0.getOperand(1), N0.getOperand(2), 1636 N0.getOperand(3)); 1637 CombineTo(N, ExtLoad); 1638 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 1639 ExtLoad.getValue(1)); 1640 return SDOperand(); 1641 } 1642 return SDOperand(); 1643} 1644 1645SDOperand DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) { 1646 SDOperand N0 = N->getOperand(0); 1647 SDOperand N1 = N->getOperand(1); 1648 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1649 MVT::ValueType VT = N->getValueType(0); 1650 MVT::ValueType EVT = cast<VTSDNode>(N1)->getVT(); 1651 unsigned EVTBits = MVT::getSizeInBits(EVT); 1652 1653 // fold (sext_in_reg c1) -> c1 1654 if (N0C) { 1655 SDOperand Truncate = DAG.getConstant(N0C->getValue(), EVT); 1656 return DAG.getNode(ISD::SIGN_EXTEND, VT, Truncate); 1657 } 1658 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt1 1659 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 1660 cast<VTSDNode>(N0.getOperand(1))->getVT() <= EVT) { 1661 return N0; 1662 } 1663 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2 1664 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 1665 EVT < cast<VTSDNode>(N0.getOperand(1))->getVT()) { 1666 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), N1); 1667 } 1668 // fold (sext_in_reg (assert_sext x)) -> (assert_sext x) 1669 if (N0.getOpcode() == ISD::AssertSext && 1670 cast<VTSDNode>(N0.getOperand(1))->getVT() <= EVT) { 1671 return N0; 1672 } 1673 // fold (sext_in_reg (sextload x)) -> (sextload x) 1674 if (N0.getOpcode() == ISD::SEXTLOAD && 1675 cast<VTSDNode>(N0.getOperand(3))->getVT() <= EVT) { 1676 return N0; 1677 } 1678 // fold (sext_in_reg (setcc x)) -> setcc x iff (setcc x) == 0 or -1 1679 if (N0.getOpcode() == ISD::SETCC && 1680 TLI.getSetCCResultContents() == 1681 TargetLowering::ZeroOrNegativeOneSetCCResult) 1682 return N0; 1683 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is zero 1684 if (TLI.MaskedValueIsZero(N0, 1ULL << (EVTBits-1))) 1685 return DAG.getZeroExtendInReg(N0, EVT); 1686 // fold (sext_in_reg (srl x)) -> sra x 1687 if (N0.getOpcode() == ISD::SRL && 1688 N0.getOperand(1).getOpcode() == ISD::Constant && 1689 cast<ConstantSDNode>(N0.getOperand(1))->getValue() == EVTBits) { 1690 return DAG.getNode(ISD::SRA, N0.getValueType(), N0.getOperand(0), 1691 N0.getOperand(1)); 1692 } 1693 // fold (sext_inreg (extload x)) -> (sextload x) 1694 if (N0.getOpcode() == ISD::EXTLOAD && 1695 EVT == cast<VTSDNode>(N0.getOperand(3))->getVT() && 1696 (!AfterLegalize || TLI.isOperationLegal(ISD::SEXTLOAD, EVT))) { 1697 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N0.getOperand(0), 1698 N0.getOperand(1), N0.getOperand(2), 1699 EVT); 1700 CombineTo(N, ExtLoad); 1701 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 1702 return SDOperand(); 1703 } 1704 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use 1705 if (N0.getOpcode() == ISD::ZEXTLOAD && N0.hasOneUse() && 1706 EVT == cast<VTSDNode>(N0.getOperand(3))->getVT() && 1707 (!AfterLegalize || TLI.isOperationLegal(ISD::SEXTLOAD, EVT))) { 1708 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, N0.getOperand(0), 1709 N0.getOperand(1), N0.getOperand(2), 1710 EVT); 1711 CombineTo(N, ExtLoad); 1712 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 1713 return SDOperand(); 1714 } 1715 return SDOperand(); 1716} 1717 1718SDOperand DAGCombiner::visitTRUNCATE(SDNode *N) { 1719 SDOperand N0 = N->getOperand(0); 1720 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1721 MVT::ValueType VT = N->getValueType(0); 1722 1723 // noop truncate 1724 if (N0.getValueType() == N->getValueType(0)) 1725 return N0; 1726 // fold (truncate c1) -> c1 1727 if (N0C) 1728 return DAG.getNode(ISD::TRUNCATE, VT, N0); 1729 // fold (truncate (truncate x)) -> (truncate x) 1730 if (N0.getOpcode() == ISD::TRUNCATE) 1731 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0)); 1732 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x 1733 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::SIGN_EXTEND){ 1734 if (N0.getValueType() < VT) 1735 // if the source is smaller than the dest, we still need an extend 1736 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0)); 1737 else if (N0.getValueType() > VT) 1738 // if the source is larger than the dest, than we just need the truncate 1739 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0)); 1740 else 1741 // if the source and dest are the same type, we can drop both the extend 1742 // and the truncate 1743 return N0.getOperand(0); 1744 } 1745 // fold (truncate (load x)) -> (smaller load x) 1746 if (N0.getOpcode() == ISD::LOAD && N0.hasOneUse()) { 1747 assert(MVT::getSizeInBits(N0.getValueType()) > MVT::getSizeInBits(VT) && 1748 "Cannot truncate to larger type!"); 1749 MVT::ValueType PtrType = N0.getOperand(1).getValueType(); 1750 // For big endian targets, we need to add an offset to the pointer to load 1751 // the correct bytes. For little endian systems, we merely need to read 1752 // fewer bytes from the same pointer. 1753 uint64_t PtrOff = 1754 (MVT::getSizeInBits(N0.getValueType()) - MVT::getSizeInBits(VT)) / 8; 1755 SDOperand NewPtr = TLI.isLittleEndian() ? N0.getOperand(1) : 1756 DAG.getNode(ISD::ADD, PtrType, N0.getOperand(1), 1757 DAG.getConstant(PtrOff, PtrType)); 1758 WorkList.push_back(NewPtr.Val); 1759 SDOperand Load = DAG.getLoad(VT, N0.getOperand(0), NewPtr,N0.getOperand(2)); 1760 WorkList.push_back(N); 1761 CombineTo(N0.Val, Load, Load.getValue(1)); 1762 return SDOperand(); 1763 } 1764 return SDOperand(); 1765} 1766 1767SDOperand DAGCombiner::visitBIT_CONVERT(SDNode *N) { 1768 SDOperand N0 = N->getOperand(0); 1769 MVT::ValueType VT = N->getValueType(0); 1770 1771 // If the input is a constant, let getNode() fold it. 1772 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) { 1773 SDOperand Res = DAG.getNode(ISD::BIT_CONVERT, VT, N0); 1774 if (Res.Val != N) return Res; 1775 } 1776 1777 if (N0.getOpcode() == ISD::BIT_CONVERT) // conv(conv(x,t1),t2) -> conv(x,t2) 1778 return DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0)); 1779 1780 // fold (conv (load x)) -> (load (conv*)x) 1781 // FIXME: These xforms need to know that the resultant load doesn't need a 1782 // higher alignment than the original! 1783 if (0 && N0.getOpcode() == ISD::LOAD && N0.hasOneUse()) { 1784 SDOperand Load = DAG.getLoad(VT, N0.getOperand(0), N0.getOperand(1), 1785 N0.getOperand(2)); 1786 WorkList.push_back(N); 1787 CombineTo(N0.Val, DAG.getNode(ISD::BIT_CONVERT, N0.getValueType(), Load), 1788 Load.getValue(1)); 1789 return Load; 1790 } 1791 1792 return SDOperand(); 1793} 1794 1795SDOperand DAGCombiner::visitFADD(SDNode *N) { 1796 SDOperand N0 = N->getOperand(0); 1797 SDOperand N1 = N->getOperand(1); 1798 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 1799 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 1800 MVT::ValueType VT = N->getValueType(0); 1801 1802 // fold (fadd c1, c2) -> c1+c2 1803 if (N0CFP && N1CFP) 1804 return DAG.getNode(ISD::FADD, VT, N0, N1); 1805 // canonicalize constant to RHS 1806 if (N0CFP && !N1CFP) 1807 return DAG.getNode(ISD::FADD, VT, N1, N0); 1808 // fold (A + (-B)) -> A-B 1809 if (N1.getOpcode() == ISD::FNEG) 1810 return DAG.getNode(ISD::FSUB, VT, N0, N1.getOperand(0)); 1811 // fold ((-A) + B) -> B-A 1812 if (N0.getOpcode() == ISD::FNEG) 1813 return DAG.getNode(ISD::FSUB, VT, N1, N0.getOperand(0)); 1814 return SDOperand(); 1815} 1816 1817SDOperand DAGCombiner::visitFSUB(SDNode *N) { 1818 SDOperand N0 = N->getOperand(0); 1819 SDOperand N1 = N->getOperand(1); 1820 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 1821 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 1822 MVT::ValueType VT = N->getValueType(0); 1823 1824 // fold (fsub c1, c2) -> c1-c2 1825 if (N0CFP && N1CFP) 1826 return DAG.getNode(ISD::FSUB, VT, N0, N1); 1827 // fold (A-(-B)) -> A+B 1828 if (N1.getOpcode() == ISD::FNEG) 1829 return DAG.getNode(ISD::FADD, VT, N0, N1.getOperand(0)); 1830 return SDOperand(); 1831} 1832 1833SDOperand DAGCombiner::visitFMUL(SDNode *N) { 1834 SDOperand N0 = N->getOperand(0); 1835 SDOperand N1 = N->getOperand(1); 1836 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 1837 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 1838 MVT::ValueType VT = N->getValueType(0); 1839 1840 // fold (fmul c1, c2) -> c1*c2 1841 if (N0CFP && N1CFP) 1842 return DAG.getNode(ISD::FMUL, VT, N0, N1); 1843 // canonicalize constant to RHS 1844 if (N0CFP && !N1CFP) 1845 return DAG.getNode(ISD::FMUL, VT, N1, N0); 1846 // fold (fmul X, 2.0) -> (fadd X, X) 1847 if (N1CFP && N1CFP->isExactlyValue(+2.0)) 1848 return DAG.getNode(ISD::FADD, VT, N0, N0); 1849 return SDOperand(); 1850} 1851 1852SDOperand DAGCombiner::visitFDIV(SDNode *N) { 1853 SDOperand N0 = N->getOperand(0); 1854 SDOperand N1 = N->getOperand(1); 1855 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 1856 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 1857 MVT::ValueType VT = N->getValueType(0); 1858 1859 // fold (fdiv c1, c2) -> c1/c2 1860 if (N0CFP && N1CFP) 1861 return DAG.getNode(ISD::FDIV, VT, N0, N1); 1862 return SDOperand(); 1863} 1864 1865SDOperand DAGCombiner::visitFREM(SDNode *N) { 1866 SDOperand N0 = N->getOperand(0); 1867 SDOperand N1 = N->getOperand(1); 1868 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 1869 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 1870 MVT::ValueType VT = N->getValueType(0); 1871 1872 // fold (frem c1, c2) -> fmod(c1,c2) 1873 if (N0CFP && N1CFP) 1874 return DAG.getNode(ISD::FREM, VT, N0, N1); 1875 return SDOperand(); 1876} 1877 1878 1879SDOperand DAGCombiner::visitSINT_TO_FP(SDNode *N) { 1880 SDOperand N0 = N->getOperand(0); 1881 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1882 MVT::ValueType VT = N->getValueType(0); 1883 1884 // fold (sint_to_fp c1) -> c1fp 1885 if (N0C) 1886 return DAG.getNode(ISD::SINT_TO_FP, VT, N0); 1887 return SDOperand(); 1888} 1889 1890SDOperand DAGCombiner::visitUINT_TO_FP(SDNode *N) { 1891 SDOperand N0 = N->getOperand(0); 1892 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1893 MVT::ValueType VT = N->getValueType(0); 1894 1895 // fold (uint_to_fp c1) -> c1fp 1896 if (N0C) 1897 return DAG.getNode(ISD::UINT_TO_FP, VT, N0); 1898 return SDOperand(); 1899} 1900 1901SDOperand DAGCombiner::visitFP_TO_SINT(SDNode *N) { 1902 SDOperand N0 = N->getOperand(0); 1903 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 1904 MVT::ValueType VT = N->getValueType(0); 1905 1906 // fold (fp_to_sint c1fp) -> c1 1907 if (N0CFP) 1908 return DAG.getNode(ISD::FP_TO_SINT, VT, N0); 1909 return SDOperand(); 1910} 1911 1912SDOperand DAGCombiner::visitFP_TO_UINT(SDNode *N) { 1913 SDOperand N0 = N->getOperand(0); 1914 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 1915 MVT::ValueType VT = N->getValueType(0); 1916 1917 // fold (fp_to_uint c1fp) -> c1 1918 if (N0CFP) 1919 return DAG.getNode(ISD::FP_TO_UINT, VT, N0); 1920 return SDOperand(); 1921} 1922 1923SDOperand DAGCombiner::visitFP_ROUND(SDNode *N) { 1924 SDOperand N0 = N->getOperand(0); 1925 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 1926 MVT::ValueType VT = N->getValueType(0); 1927 1928 // fold (fp_round c1fp) -> c1fp 1929 if (N0CFP) 1930 return DAG.getNode(ISD::FP_ROUND, VT, N0); 1931 return SDOperand(); 1932} 1933 1934SDOperand DAGCombiner::visitFP_ROUND_INREG(SDNode *N) { 1935 SDOperand N0 = N->getOperand(0); 1936 MVT::ValueType VT = N->getValueType(0); 1937 MVT::ValueType EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 1938 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 1939 1940 // fold (fp_round_inreg c1fp) -> c1fp 1941 if (N0CFP) { 1942 SDOperand Round = DAG.getConstantFP(N0CFP->getValue(), EVT); 1943 return DAG.getNode(ISD::FP_EXTEND, VT, Round); 1944 } 1945 return SDOperand(); 1946} 1947 1948SDOperand DAGCombiner::visitFP_EXTEND(SDNode *N) { 1949 SDOperand N0 = N->getOperand(0); 1950 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 1951 MVT::ValueType VT = N->getValueType(0); 1952 1953 // fold (fp_extend c1fp) -> c1fp 1954 if (N0CFP) 1955 return DAG.getNode(ISD::FP_EXTEND, VT, N0); 1956 return SDOperand(); 1957} 1958 1959SDOperand DAGCombiner::visitFNEG(SDNode *N) { 1960 SDOperand N0 = N->getOperand(0); 1961 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 1962 MVT::ValueType VT = N->getValueType(0); 1963 1964 // fold (fneg c1) -> -c1 1965 if (N0CFP) 1966 return DAG.getNode(ISD::FNEG, VT, N0); 1967 // fold (fneg (sub x, y)) -> (sub y, x) 1968 if (N->getOperand(0).getOpcode() == ISD::SUB) 1969 return DAG.getNode(ISD::SUB, VT, N->getOperand(1), N->getOperand(0)); 1970 // fold (fneg (fneg x)) -> x 1971 if (N->getOperand(0).getOpcode() == ISD::FNEG) 1972 return N->getOperand(0).getOperand(0); 1973 return SDOperand(); 1974} 1975 1976SDOperand DAGCombiner::visitFABS(SDNode *N) { 1977 SDOperand N0 = N->getOperand(0); 1978 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 1979 MVT::ValueType VT = N->getValueType(0); 1980 1981 // fold (fabs c1) -> fabs(c1) 1982 if (N0CFP) 1983 return DAG.getNode(ISD::FABS, VT, N0); 1984 // fold (fabs (fabs x)) -> (fabs x) 1985 if (N->getOperand(0).getOpcode() == ISD::FABS) 1986 return N->getOperand(0); 1987 // fold (fabs (fneg x)) -> (fabs x) 1988 if (N->getOperand(0).getOpcode() == ISD::FNEG) 1989 return DAG.getNode(ISD::FABS, VT, N->getOperand(0).getOperand(0)); 1990 return SDOperand(); 1991} 1992 1993SDOperand DAGCombiner::visitBRCOND(SDNode *N) { 1994 SDOperand Chain = N->getOperand(0); 1995 SDOperand N1 = N->getOperand(1); 1996 SDOperand N2 = N->getOperand(2); 1997 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1998 1999 // never taken branch, fold to chain 2000 if (N1C && N1C->isNullValue()) 2001 return Chain; 2002 // unconditional branch 2003 if (N1C && N1C->getValue() == 1) 2004 return DAG.getNode(ISD::BR, MVT::Other, Chain, N2); 2005 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal 2006 // on the target. 2007 if (N1.getOpcode() == ISD::SETCC && 2008 TLI.isOperationLegal(ISD::BR_CC, MVT::Other)) { 2009 return DAG.getNode(ISD::BR_CC, MVT::Other, Chain, N1.getOperand(2), 2010 N1.getOperand(0), N1.getOperand(1), N2); 2011 } 2012 return SDOperand(); 2013} 2014 2015SDOperand DAGCombiner::visitBRCONDTWOWAY(SDNode *N) { 2016 SDOperand Chain = N->getOperand(0); 2017 SDOperand N1 = N->getOperand(1); 2018 SDOperand N2 = N->getOperand(2); 2019 SDOperand N3 = N->getOperand(3); 2020 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2021 2022 // unconditional branch to true mbb 2023 if (N1C && N1C->getValue() == 1) 2024 return DAG.getNode(ISD::BR, MVT::Other, Chain, N2); 2025 // unconditional branch to false mbb 2026 if (N1C && N1C->isNullValue()) 2027 return DAG.getNode(ISD::BR, MVT::Other, Chain, N3); 2028 // fold a brcondtwoway with a setcc condition into a BRTWOWAY_CC node if 2029 // BRTWOWAY_CC is legal on the target. 2030 if (N1.getOpcode() == ISD::SETCC && 2031 TLI.isOperationLegal(ISD::BRTWOWAY_CC, MVT::Other)) { 2032 std::vector<SDOperand> Ops; 2033 Ops.push_back(Chain); 2034 Ops.push_back(N1.getOperand(2)); 2035 Ops.push_back(N1.getOperand(0)); 2036 Ops.push_back(N1.getOperand(1)); 2037 Ops.push_back(N2); 2038 Ops.push_back(N3); 2039 return DAG.getNode(ISD::BRTWOWAY_CC, MVT::Other, Ops); 2040 } 2041 return SDOperand(); 2042} 2043 2044// Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB. 2045// 2046SDOperand DAGCombiner::visitBR_CC(SDNode *N) { 2047 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1)); 2048 SDOperand CondLHS = N->getOperand(2), CondRHS = N->getOperand(3); 2049 2050 // Use SimplifySetCC to simplify SETCC's. 2051 SDOperand Simp = SimplifySetCC(MVT::i1, CondLHS, CondRHS, CC->get(), false); 2052 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(Simp.Val); 2053 2054 // fold br_cc true, dest -> br dest (unconditional branch) 2055 if (SCCC && SCCC->getValue()) 2056 return DAG.getNode(ISD::BR, MVT::Other, N->getOperand(0), 2057 N->getOperand(4)); 2058 // fold br_cc false, dest -> unconditional fall through 2059 if (SCCC && SCCC->isNullValue()) 2060 return N->getOperand(0); 2061 // fold to a simpler setcc 2062 if (Simp.Val && Simp.getOpcode() == ISD::SETCC) 2063 return DAG.getNode(ISD::BR_CC, MVT::Other, N->getOperand(0), 2064 Simp.getOperand(2), Simp.getOperand(0), 2065 Simp.getOperand(1), N->getOperand(4)); 2066 return SDOperand(); 2067} 2068 2069SDOperand DAGCombiner::visitBRTWOWAY_CC(SDNode *N) { 2070 SDOperand Chain = N->getOperand(0); 2071 SDOperand CCN = N->getOperand(1); 2072 SDOperand LHS = N->getOperand(2); 2073 SDOperand RHS = N->getOperand(3); 2074 SDOperand N4 = N->getOperand(4); 2075 SDOperand N5 = N->getOperand(5); 2076 2077 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), LHS, RHS, 2078 cast<CondCodeSDNode>(CCN)->get(), false); 2079 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val); 2080 2081 // fold select_cc lhs, rhs, x, x, cc -> x 2082 if (N4 == N5) 2083 return DAG.getNode(ISD::BR, MVT::Other, Chain, N4); 2084 // fold select_cc true, x, y -> x 2085 if (SCCC && SCCC->getValue()) 2086 return DAG.getNode(ISD::BR, MVT::Other, Chain, N4); 2087 // fold select_cc false, x, y -> y 2088 if (SCCC && SCCC->isNullValue()) 2089 return DAG.getNode(ISD::BR, MVT::Other, Chain, N5); 2090 // fold to a simpler setcc 2091 if (SCC.Val && SCC.getOpcode() == ISD::SETCC) { 2092 std::vector<SDOperand> Ops; 2093 Ops.push_back(Chain); 2094 Ops.push_back(SCC.getOperand(2)); 2095 Ops.push_back(SCC.getOperand(0)); 2096 Ops.push_back(SCC.getOperand(1)); 2097 Ops.push_back(N4); 2098 Ops.push_back(N5); 2099 return DAG.getNode(ISD::BRTWOWAY_CC, MVT::Other, Ops); 2100 } 2101 return SDOperand(); 2102} 2103 2104SDOperand DAGCombiner::visitLOAD(SDNode *N) { 2105 SDOperand Chain = N->getOperand(0); 2106 SDOperand Ptr = N->getOperand(1); 2107 SDOperand SrcValue = N->getOperand(2); 2108 2109 // If this load is directly stored, replace the load value with the stored 2110 // value. 2111 // TODO: Handle store large -> read small portion. 2112 // TODO: Handle TRUNCSTORE/EXTLOAD 2113 if (Chain.getOpcode() == ISD::STORE && Chain.getOperand(2) == Ptr && 2114 Chain.getOperand(1).getValueType() == N->getValueType(0)) 2115 return CombineTo(N, Chain.getOperand(1), Chain); 2116 2117 return SDOperand(); 2118} 2119 2120SDOperand DAGCombiner::visitSTORE(SDNode *N) { 2121 SDOperand Chain = N->getOperand(0); 2122 SDOperand Value = N->getOperand(1); 2123 SDOperand Ptr = N->getOperand(2); 2124 SDOperand SrcValue = N->getOperand(3); 2125 2126 // If this is a store that kills a previous store, remove the previous store. 2127 if (Chain.getOpcode() == ISD::STORE && Chain.getOperand(2) == Ptr && 2128 Chain.Val->hasOneUse() /* Avoid introducing DAG cycles */ && 2129 // Make sure that these stores are the same value type: 2130 // FIXME: we really care that the second store is >= size of the first. 2131 Value.getValueType() == Chain.getOperand(1).getValueType()) { 2132 // Create a new store of Value that replaces both stores. 2133 SDNode *PrevStore = Chain.Val; 2134 if (PrevStore->getOperand(1) == Value) // Same value multiply stored. 2135 return Chain; 2136 SDOperand NewStore = DAG.getNode(ISD::STORE, MVT::Other, 2137 PrevStore->getOperand(0), Value, Ptr, 2138 SrcValue); 2139 CombineTo(N, NewStore); // Nuke this store. 2140 CombineTo(PrevStore, NewStore); // Nuke the previous store. 2141 return SDOperand(N, 0); 2142 } 2143 2144 // If this is a store of a bit convert, store the input value. 2145 // FIXME: This needs to know that the resultant store does not need a 2146 // higher alignment than the original. 2147 if (0 && Value.getOpcode() == ISD::BIT_CONVERT) 2148 return DAG.getNode(ISD::STORE, MVT::Other, Chain, Value.getOperand(0), 2149 Ptr, SrcValue); 2150 2151 return SDOperand(); 2152} 2153 2154SDOperand DAGCombiner::visitLOCATION(SDNode *N) { 2155 SDOperand Chain = N->getOperand(0); 2156 2157 // Remove redundant locations (last one holds) 2158 if (Chain.getOpcode() == ISD::LOCATION && Chain.hasOneUse()) { 2159 return DAG.getNode(ISD::LOCATION, MVT::Other, Chain.getOperand(0), 2160 N->getOperand(1), 2161 N->getOperand(2), 2162 N->getOperand(3), 2163 N->getOperand(4)); 2164 } 2165 2166 return SDOperand(); 2167} 2168 2169SDOperand DAGCombiner::visitDEBUGLOC(SDNode *N) { 2170 SDOperand Chain = N->getOperand(0); 2171 2172 // Remove redundant debug locations (last one holds) 2173 if (Chain.getOpcode() == ISD::DEBUG_LOC && Chain.hasOneUse()) { 2174 return DAG.getNode(ISD::DEBUG_LOC, MVT::Other, Chain.getOperand(0), 2175 N->getOperand(1), 2176 N->getOperand(2), 2177 N->getOperand(3)); 2178 } 2179 2180 return SDOperand(); 2181} 2182 2183SDOperand DAGCombiner::SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2){ 2184 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!"); 2185 2186 SDOperand SCC = SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), N1, N2, 2187 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 2188 // If we got a simplified select_cc node back from SimplifySelectCC, then 2189 // break it down into a new SETCC node, and a new SELECT node, and then return 2190 // the SELECT node, since we were called with a SELECT node. 2191 if (SCC.Val) { 2192 // Check to see if we got a select_cc back (to turn into setcc/select). 2193 // Otherwise, just return whatever node we got back, like fabs. 2194 if (SCC.getOpcode() == ISD::SELECT_CC) { 2195 SDOperand SETCC = DAG.getNode(ISD::SETCC, N0.getValueType(), 2196 SCC.getOperand(0), SCC.getOperand(1), 2197 SCC.getOperand(4)); 2198 WorkList.push_back(SETCC.Val); 2199 return DAG.getNode(ISD::SELECT, SCC.getValueType(), SCC.getOperand(2), 2200 SCC.getOperand(3), SETCC); 2201 } 2202 return SCC; 2203 } 2204 return SDOperand(); 2205} 2206 2207/// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS 2208/// are the two values being selected between, see if we can simplify the 2209/// select. 2210/// 2211bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDOperand LHS, 2212 SDOperand RHS) { 2213 2214 // If this is a select from two identical things, try to pull the operation 2215 // through the select. 2216 if (LHS.getOpcode() == RHS.getOpcode() && LHS.hasOneUse() && RHS.hasOneUse()){ 2217#if 0 2218 std::cerr << "SELECT: ["; LHS.Val->dump(); 2219 std::cerr << "] ["; RHS.Val->dump(); 2220 std::cerr << "]\n"; 2221#endif 2222 2223 // If this is a load and the token chain is identical, replace the select 2224 // of two loads with a load through a select of the address to load from. 2225 // This triggers in things like "select bool X, 10.0, 123.0" after the FP 2226 // constants have been dropped into the constant pool. 2227 if ((LHS.getOpcode() == ISD::LOAD || 2228 LHS.getOpcode() == ISD::EXTLOAD || 2229 LHS.getOpcode() == ISD::ZEXTLOAD || 2230 LHS.getOpcode() == ISD::SEXTLOAD) && 2231 // Token chains must be identical. 2232 LHS.getOperand(0) == RHS.getOperand(0) && 2233 // If this is an EXTLOAD, the VT's must match. 2234 (LHS.getOpcode() == ISD::LOAD || 2235 LHS.getOperand(3) == RHS.getOperand(3))) { 2236 // FIXME: this conflates two src values, discarding one. This is not 2237 // the right thing to do, but nothing uses srcvalues now. When they do, 2238 // turn SrcValue into a list of locations. 2239 SDOperand Addr; 2240 if (TheSelect->getOpcode() == ISD::SELECT) 2241 Addr = DAG.getNode(ISD::SELECT, LHS.getOperand(1).getValueType(), 2242 TheSelect->getOperand(0), LHS.getOperand(1), 2243 RHS.getOperand(1)); 2244 else 2245 Addr = DAG.getNode(ISD::SELECT_CC, LHS.getOperand(1).getValueType(), 2246 TheSelect->getOperand(0), 2247 TheSelect->getOperand(1), 2248 LHS.getOperand(1), RHS.getOperand(1), 2249 TheSelect->getOperand(4)); 2250 2251 SDOperand Load; 2252 if (LHS.getOpcode() == ISD::LOAD) 2253 Load = DAG.getLoad(TheSelect->getValueType(0), LHS.getOperand(0), 2254 Addr, LHS.getOperand(2)); 2255 else 2256 Load = DAG.getExtLoad(LHS.getOpcode(), TheSelect->getValueType(0), 2257 LHS.getOperand(0), Addr, LHS.getOperand(2), 2258 cast<VTSDNode>(LHS.getOperand(3))->getVT()); 2259 // Users of the select now use the result of the load. 2260 CombineTo(TheSelect, Load); 2261 2262 // Users of the old loads now use the new load's chain. We know the 2263 // old-load value is dead now. 2264 CombineTo(LHS.Val, Load.getValue(0), Load.getValue(1)); 2265 CombineTo(RHS.Val, Load.getValue(0), Load.getValue(1)); 2266 return true; 2267 } 2268 } 2269 2270 return false; 2271} 2272 2273SDOperand DAGCombiner::SimplifySelectCC(SDOperand N0, SDOperand N1, 2274 SDOperand N2, SDOperand N3, 2275 ISD::CondCode CC) { 2276 2277 MVT::ValueType VT = N2.getValueType(); 2278 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 2279 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 2280 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val); 2281 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.Val); 2282 2283 // Determine if the condition we're dealing with is constant 2284 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false); 2285 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val); 2286 2287 // fold select_cc true, x, y -> x 2288 if (SCCC && SCCC->getValue()) 2289 return N2; 2290 // fold select_cc false, x, y -> y 2291 if (SCCC && SCCC->getValue() == 0) 2292 return N3; 2293 2294 // Check to see if we can simplify the select into an fabs node 2295 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) { 2296 // Allow either -0.0 or 0.0 2297 if (CFP->getValue() == 0.0) { 2298 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs 2299 if ((CC == ISD::SETGE || CC == ISD::SETGT) && 2300 N0 == N2 && N3.getOpcode() == ISD::FNEG && 2301 N2 == N3.getOperand(0)) 2302 return DAG.getNode(ISD::FABS, VT, N0); 2303 2304 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs 2305 if ((CC == ISD::SETLT || CC == ISD::SETLE) && 2306 N0 == N3 && N2.getOpcode() == ISD::FNEG && 2307 N2.getOperand(0) == N3) 2308 return DAG.getNode(ISD::FABS, VT, N3); 2309 } 2310 } 2311 2312 // Check to see if we can perform the "gzip trick", transforming 2313 // select_cc setlt X, 0, A, 0 -> and (sra X, size(X)-1), A 2314 if (N1C && N1C->isNullValue() && N3C && N3C->isNullValue() && 2315 MVT::isInteger(N0.getValueType()) && 2316 MVT::isInteger(N2.getValueType()) && CC == ISD::SETLT) { 2317 MVT::ValueType XType = N0.getValueType(); 2318 MVT::ValueType AType = N2.getValueType(); 2319 if (XType >= AType) { 2320 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a 2321 // single-bit constant. 2322 if (N2C && ((N2C->getValue() & (N2C->getValue()-1)) == 0)) { 2323 unsigned ShCtV = Log2_64(N2C->getValue()); 2324 ShCtV = MVT::getSizeInBits(XType)-ShCtV-1; 2325 SDOperand ShCt = DAG.getConstant(ShCtV, TLI.getShiftAmountTy()); 2326 SDOperand Shift = DAG.getNode(ISD::SRL, XType, N0, ShCt); 2327 WorkList.push_back(Shift.Val); 2328 if (XType > AType) { 2329 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift); 2330 WorkList.push_back(Shift.Val); 2331 } 2332 return DAG.getNode(ISD::AND, AType, Shift, N2); 2333 } 2334 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0, 2335 DAG.getConstant(MVT::getSizeInBits(XType)-1, 2336 TLI.getShiftAmountTy())); 2337 WorkList.push_back(Shift.Val); 2338 if (XType > AType) { 2339 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift); 2340 WorkList.push_back(Shift.Val); 2341 } 2342 return DAG.getNode(ISD::AND, AType, Shift, N2); 2343 } 2344 } 2345 2346 // fold select C, 16, 0 -> shl C, 4 2347 if (N2C && N3C && N3C->isNullValue() && isPowerOf2_64(N2C->getValue()) && 2348 TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult) { 2349 // Get a SetCC of the condition 2350 // FIXME: Should probably make sure that setcc is legal if we ever have a 2351 // target where it isn't. 2352 SDOperand Temp, SCC = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC); 2353 WorkList.push_back(SCC.Val); 2354 // cast from setcc result type to select result type 2355 if (AfterLegalize) 2356 Temp = DAG.getZeroExtendInReg(SCC, N2.getValueType()); 2357 else 2358 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC); 2359 WorkList.push_back(Temp.Val); 2360 // shl setcc result by log2 n2c 2361 return DAG.getNode(ISD::SHL, N2.getValueType(), Temp, 2362 DAG.getConstant(Log2_64(N2C->getValue()), 2363 TLI.getShiftAmountTy())); 2364 } 2365 2366 // Check to see if this is the equivalent of setcc 2367 // FIXME: Turn all of these into setcc if setcc if setcc is legal 2368 // otherwise, go ahead with the folds. 2369 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getValue() == 1ULL)) { 2370 MVT::ValueType XType = N0.getValueType(); 2371 if (TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultTy())) { 2372 SDOperand Res = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC); 2373 if (Res.getValueType() != VT) 2374 Res = DAG.getNode(ISD::ZERO_EXTEND, VT, Res); 2375 return Res; 2376 } 2377 2378 // seteq X, 0 -> srl (ctlz X, log2(size(X))) 2379 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ && 2380 TLI.isOperationLegal(ISD::CTLZ, XType)) { 2381 SDOperand Ctlz = DAG.getNode(ISD::CTLZ, XType, N0); 2382 return DAG.getNode(ISD::SRL, XType, Ctlz, 2383 DAG.getConstant(Log2_32(MVT::getSizeInBits(XType)), 2384 TLI.getShiftAmountTy())); 2385 } 2386 // setgt X, 0 -> srl (and (-X, ~X), size(X)-1) 2387 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) { 2388 SDOperand NegN0 = DAG.getNode(ISD::SUB, XType, DAG.getConstant(0, XType), 2389 N0); 2390 SDOperand NotN0 = DAG.getNode(ISD::XOR, XType, N0, 2391 DAG.getConstant(~0ULL, XType)); 2392 return DAG.getNode(ISD::SRL, XType, 2393 DAG.getNode(ISD::AND, XType, NegN0, NotN0), 2394 DAG.getConstant(MVT::getSizeInBits(XType)-1, 2395 TLI.getShiftAmountTy())); 2396 } 2397 // setgt X, -1 -> xor (srl (X, size(X)-1), 1) 2398 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) { 2399 SDOperand Sign = DAG.getNode(ISD::SRL, XType, N0, 2400 DAG.getConstant(MVT::getSizeInBits(XType)-1, 2401 TLI.getShiftAmountTy())); 2402 return DAG.getNode(ISD::XOR, XType, Sign, DAG.getConstant(1, XType)); 2403 } 2404 } 2405 2406 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X -> 2407 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 2408 if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) && 2409 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1)) { 2410 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N2.getOperand(0))) { 2411 MVT::ValueType XType = N0.getValueType(); 2412 if (SubC->isNullValue() && MVT::isInteger(XType)) { 2413 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0, 2414 DAG.getConstant(MVT::getSizeInBits(XType)-1, 2415 TLI.getShiftAmountTy())); 2416 SDOperand Add = DAG.getNode(ISD::ADD, XType, N0, Shift); 2417 WorkList.push_back(Shift.Val); 2418 WorkList.push_back(Add.Val); 2419 return DAG.getNode(ISD::XOR, XType, Add, Shift); 2420 } 2421 } 2422 } 2423 2424 return SDOperand(); 2425} 2426 2427SDOperand DAGCombiner::SimplifySetCC(MVT::ValueType VT, SDOperand N0, 2428 SDOperand N1, ISD::CondCode Cond, 2429 bool foldBooleans) { 2430 // These setcc operations always fold. 2431 switch (Cond) { 2432 default: break; 2433 case ISD::SETFALSE: 2434 case ISD::SETFALSE2: return DAG.getConstant(0, VT); 2435 case ISD::SETTRUE: 2436 case ISD::SETTRUE2: return DAG.getConstant(1, VT); 2437 } 2438 2439 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val)) { 2440 uint64_t C1 = N1C->getValue(); 2441 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val)) { 2442 uint64_t C0 = N0C->getValue(); 2443 2444 // Sign extend the operands if required 2445 if (ISD::isSignedIntSetCC(Cond)) { 2446 C0 = N0C->getSignExtended(); 2447 C1 = N1C->getSignExtended(); 2448 } 2449 2450 switch (Cond) { 2451 default: assert(0 && "Unknown integer setcc!"); 2452 case ISD::SETEQ: return DAG.getConstant(C0 == C1, VT); 2453 case ISD::SETNE: return DAG.getConstant(C0 != C1, VT); 2454 case ISD::SETULT: return DAG.getConstant(C0 < C1, VT); 2455 case ISD::SETUGT: return DAG.getConstant(C0 > C1, VT); 2456 case ISD::SETULE: return DAG.getConstant(C0 <= C1, VT); 2457 case ISD::SETUGE: return DAG.getConstant(C0 >= C1, VT); 2458 case ISD::SETLT: return DAG.getConstant((int64_t)C0 < (int64_t)C1, VT); 2459 case ISD::SETGT: return DAG.getConstant((int64_t)C0 > (int64_t)C1, VT); 2460 case ISD::SETLE: return DAG.getConstant((int64_t)C0 <= (int64_t)C1, VT); 2461 case ISD::SETGE: return DAG.getConstant((int64_t)C0 >= (int64_t)C1, VT); 2462 } 2463 } else { 2464 // If the LHS is a ZERO_EXTEND, perform the comparison on the input. 2465 if (N0.getOpcode() == ISD::ZERO_EXTEND) { 2466 unsigned InSize = MVT::getSizeInBits(N0.getOperand(0).getValueType()); 2467 2468 // If the comparison constant has bits in the upper part, the 2469 // zero-extended value could never match. 2470 if (C1 & (~0ULL << InSize)) { 2471 unsigned VSize = MVT::getSizeInBits(N0.getValueType()); 2472 switch (Cond) { 2473 case ISD::SETUGT: 2474 case ISD::SETUGE: 2475 case ISD::SETEQ: return DAG.getConstant(0, VT); 2476 case ISD::SETULT: 2477 case ISD::SETULE: 2478 case ISD::SETNE: return DAG.getConstant(1, VT); 2479 case ISD::SETGT: 2480 case ISD::SETGE: 2481 // True if the sign bit of C1 is set. 2482 return DAG.getConstant((C1 & (1ULL << VSize)) != 0, VT); 2483 case ISD::SETLT: 2484 case ISD::SETLE: 2485 // True if the sign bit of C1 isn't set. 2486 return DAG.getConstant((C1 & (1ULL << VSize)) == 0, VT); 2487 default: 2488 break; 2489 } 2490 } 2491 2492 // Otherwise, we can perform the comparison with the low bits. 2493 switch (Cond) { 2494 case ISD::SETEQ: 2495 case ISD::SETNE: 2496 case ISD::SETUGT: 2497 case ISD::SETUGE: 2498 case ISD::SETULT: 2499 case ISD::SETULE: 2500 return DAG.getSetCC(VT, N0.getOperand(0), 2501 DAG.getConstant(C1, N0.getOperand(0).getValueType()), 2502 Cond); 2503 default: 2504 break; // todo, be more careful with signed comparisons 2505 } 2506 } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 2507 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { 2508 MVT::ValueType ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT(); 2509 unsigned ExtSrcTyBits = MVT::getSizeInBits(ExtSrcTy); 2510 MVT::ValueType ExtDstTy = N0.getValueType(); 2511 unsigned ExtDstTyBits = MVT::getSizeInBits(ExtDstTy); 2512 2513 // If the extended part has any inconsistent bits, it cannot ever 2514 // compare equal. In other words, they have to be all ones or all 2515 // zeros. 2516 uint64_t ExtBits = 2517 (~0ULL >> (64-ExtSrcTyBits)) & (~0ULL << (ExtDstTyBits-1)); 2518 if ((C1 & ExtBits) != 0 && (C1 & ExtBits) != ExtBits) 2519 return DAG.getConstant(Cond == ISD::SETNE, VT); 2520 2521 SDOperand ZextOp; 2522 MVT::ValueType Op0Ty = N0.getOperand(0).getValueType(); 2523 if (Op0Ty == ExtSrcTy) { 2524 ZextOp = N0.getOperand(0); 2525 } else { 2526 int64_t Imm = ~0ULL >> (64-ExtSrcTyBits); 2527 ZextOp = DAG.getNode(ISD::AND, Op0Ty, N0.getOperand(0), 2528 DAG.getConstant(Imm, Op0Ty)); 2529 } 2530 WorkList.push_back(ZextOp.Val); 2531 // Otherwise, make this a use of a zext. 2532 return DAG.getSetCC(VT, ZextOp, 2533 DAG.getConstant(C1 & (~0ULL>>(64-ExtSrcTyBits)), 2534 ExtDstTy), 2535 Cond); 2536 } 2537 2538 uint64_t MinVal, MaxVal; 2539 unsigned OperandBitSize = MVT::getSizeInBits(N1C->getValueType(0)); 2540 if (ISD::isSignedIntSetCC(Cond)) { 2541 MinVal = 1ULL << (OperandBitSize-1); 2542 if (OperandBitSize != 1) // Avoid X >> 64, which is undefined. 2543 MaxVal = ~0ULL >> (65-OperandBitSize); 2544 else 2545 MaxVal = 0; 2546 } else { 2547 MinVal = 0; 2548 MaxVal = ~0ULL >> (64-OperandBitSize); 2549 } 2550 2551 // Canonicalize GE/LE comparisons to use GT/LT comparisons. 2552 if (Cond == ISD::SETGE || Cond == ISD::SETUGE) { 2553 if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true 2554 --C1; // X >= C0 --> X > (C0-1) 2555 return DAG.getSetCC(VT, N0, DAG.getConstant(C1, N1.getValueType()), 2556 (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT); 2557 } 2558 2559 if (Cond == ISD::SETLE || Cond == ISD::SETULE) { 2560 if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true 2561 ++C1; // X <= C0 --> X < (C0+1) 2562 return DAG.getSetCC(VT, N0, DAG.getConstant(C1, N1.getValueType()), 2563 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT); 2564 } 2565 2566 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal) 2567 return DAG.getConstant(0, VT); // X < MIN --> false 2568 2569 // Canonicalize setgt X, Min --> setne X, Min 2570 if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal) 2571 return DAG.getSetCC(VT, N0, N1, ISD::SETNE); 2572 // Canonicalize setlt X, Max --> setne X, Max 2573 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal) 2574 return DAG.getSetCC(VT, N0, N1, ISD::SETNE); 2575 2576 // If we have setult X, 1, turn it into seteq X, 0 2577 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1) 2578 return DAG.getSetCC(VT, N0, DAG.getConstant(MinVal, N0.getValueType()), 2579 ISD::SETEQ); 2580 // If we have setugt X, Max-1, turn it into seteq X, Max 2581 else if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1) 2582 return DAG.getSetCC(VT, N0, DAG.getConstant(MaxVal, N0.getValueType()), 2583 ISD::SETEQ); 2584 2585 // If we have "setcc X, C0", check to see if we can shrink the immediate 2586 // by changing cc. 2587 2588 // SETUGT X, SINTMAX -> SETLT X, 0 2589 if (Cond == ISD::SETUGT && OperandBitSize != 1 && 2590 C1 == (~0ULL >> (65-OperandBitSize))) 2591 return DAG.getSetCC(VT, N0, DAG.getConstant(0, N1.getValueType()), 2592 ISD::SETLT); 2593 2594 // FIXME: Implement the rest of these. 2595 2596 // Fold bit comparisons when we can. 2597 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 2598 VT == N0.getValueType() && N0.getOpcode() == ISD::AND) 2599 if (ConstantSDNode *AndRHS = 2600 dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 2601 if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3 2602 // Perform the xform if the AND RHS is a single bit. 2603 if ((AndRHS->getValue() & (AndRHS->getValue()-1)) == 0) { 2604 return DAG.getNode(ISD::SRL, VT, N0, 2605 DAG.getConstant(Log2_64(AndRHS->getValue()), 2606 TLI.getShiftAmountTy())); 2607 } 2608 } else if (Cond == ISD::SETEQ && C1 == AndRHS->getValue()) { 2609 // (X & 8) == 8 --> (X & 8) >> 3 2610 // Perform the xform if C1 is a single bit. 2611 if ((C1 & (C1-1)) == 0) { 2612 return DAG.getNode(ISD::SRL, VT, N0, 2613 DAG.getConstant(Log2_64(C1),TLI.getShiftAmountTy())); 2614 } 2615 } 2616 } 2617 } 2618 } else if (isa<ConstantSDNode>(N0.Val)) { 2619 // Ensure that the constant occurs on the RHS. 2620 return DAG.getSetCC(VT, N1, N0, ISD::getSetCCSwappedOperands(Cond)); 2621 } 2622 2623 if (ConstantFPSDNode *N0C = dyn_cast<ConstantFPSDNode>(N0.Val)) 2624 if (ConstantFPSDNode *N1C = dyn_cast<ConstantFPSDNode>(N1.Val)) { 2625 double C0 = N0C->getValue(), C1 = N1C->getValue(); 2626 2627 switch (Cond) { 2628 default: break; // FIXME: Implement the rest of these! 2629 case ISD::SETEQ: return DAG.getConstant(C0 == C1, VT); 2630 case ISD::SETNE: return DAG.getConstant(C0 != C1, VT); 2631 case ISD::SETLT: return DAG.getConstant(C0 < C1, VT); 2632 case ISD::SETGT: return DAG.getConstant(C0 > C1, VT); 2633 case ISD::SETLE: return DAG.getConstant(C0 <= C1, VT); 2634 case ISD::SETGE: return DAG.getConstant(C0 >= C1, VT); 2635 } 2636 } else { 2637 // Ensure that the constant occurs on the RHS. 2638 return DAG.getSetCC(VT, N1, N0, ISD::getSetCCSwappedOperands(Cond)); 2639 } 2640 2641 if (N0 == N1) { 2642 // We can always fold X == Y for integer setcc's. 2643 if (MVT::isInteger(N0.getValueType())) 2644 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT); 2645 unsigned UOF = ISD::getUnorderedFlavor(Cond); 2646 if (UOF == 2) // FP operators that are undefined on NaNs. 2647 return DAG.getConstant(ISD::isTrueWhenEqual(Cond), VT); 2648 if (UOF == unsigned(ISD::isTrueWhenEqual(Cond))) 2649 return DAG.getConstant(UOF, VT); 2650 // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO 2651 // if it is not already. 2652 ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO; 2653 if (NewCond != Cond) 2654 return DAG.getSetCC(VT, N0, N1, NewCond); 2655 } 2656 2657 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && 2658 MVT::isInteger(N0.getValueType())) { 2659 if (N0.getOpcode() == ISD::ADD || N0.getOpcode() == ISD::SUB || 2660 N0.getOpcode() == ISD::XOR) { 2661 // Simplify (X+Y) == (X+Z) --> Y == Z 2662 if (N0.getOpcode() == N1.getOpcode()) { 2663 if (N0.getOperand(0) == N1.getOperand(0)) 2664 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(1), Cond); 2665 if (N0.getOperand(1) == N1.getOperand(1)) 2666 return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(0), Cond); 2667 if (isCommutativeBinOp(N0.getOpcode())) { 2668 // If X op Y == Y op X, try other combinations. 2669 if (N0.getOperand(0) == N1.getOperand(1)) 2670 return DAG.getSetCC(VT, N0.getOperand(1), N1.getOperand(0), Cond); 2671 if (N0.getOperand(1) == N1.getOperand(0)) 2672 return DAG.getSetCC(VT, N0.getOperand(0), N1.getOperand(1), Cond); 2673 } 2674 } 2675 2676 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(N1)) { 2677 if (ConstantSDNode *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 2678 // Turn (X+C1) == C2 --> X == C2-C1 2679 if (N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse()) { 2680 return DAG.getSetCC(VT, N0.getOperand(0), 2681 DAG.getConstant(RHSC->getValue()-LHSR->getValue(), 2682 N0.getValueType()), Cond); 2683 } 2684 2685 // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0. 2686 if (N0.getOpcode() == ISD::XOR) 2687 // If we know that all of the inverted bits are zero, don't bother 2688 // performing the inversion. 2689 if (TLI.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getValue())) 2690 return DAG.getSetCC(VT, N0.getOperand(0), 2691 DAG.getConstant(LHSR->getValue()^RHSC->getValue(), 2692 N0.getValueType()), Cond); 2693 } 2694 2695 // Turn (C1-X) == C2 --> X == C1-C2 2696 if (ConstantSDNode *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) { 2697 if (N0.getOpcode() == ISD::SUB && N0.Val->hasOneUse()) { 2698 return DAG.getSetCC(VT, N0.getOperand(1), 2699 DAG.getConstant(SUBC->getValue()-RHSC->getValue(), 2700 N0.getValueType()), Cond); 2701 } 2702 } 2703 } 2704 2705 // Simplify (X+Z) == X --> Z == 0 2706 if (N0.getOperand(0) == N1) 2707 return DAG.getSetCC(VT, N0.getOperand(1), 2708 DAG.getConstant(0, N0.getValueType()), Cond); 2709 if (N0.getOperand(1) == N1) { 2710 if (isCommutativeBinOp(N0.getOpcode())) 2711 return DAG.getSetCC(VT, N0.getOperand(0), 2712 DAG.getConstant(0, N0.getValueType()), Cond); 2713 else { 2714 assert(N0.getOpcode() == ISD::SUB && "Unexpected operation!"); 2715 // (Z-X) == X --> Z == X<<1 2716 SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(), 2717 N1, 2718 DAG.getConstant(1,TLI.getShiftAmountTy())); 2719 WorkList.push_back(SH.Val); 2720 return DAG.getSetCC(VT, N0.getOperand(0), SH, Cond); 2721 } 2722 } 2723 } 2724 2725 if (N1.getOpcode() == ISD::ADD || N1.getOpcode() == ISD::SUB || 2726 N1.getOpcode() == ISD::XOR) { 2727 // Simplify X == (X+Z) --> Z == 0 2728 if (N1.getOperand(0) == N0) { 2729 return DAG.getSetCC(VT, N1.getOperand(1), 2730 DAG.getConstant(0, N1.getValueType()), Cond); 2731 } else if (N1.getOperand(1) == N0) { 2732 if (isCommutativeBinOp(N1.getOpcode())) { 2733 return DAG.getSetCC(VT, N1.getOperand(0), 2734 DAG.getConstant(0, N1.getValueType()), Cond); 2735 } else { 2736 assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!"); 2737 // X == (Z-X) --> X<<1 == Z 2738 SDOperand SH = DAG.getNode(ISD::SHL, N1.getValueType(), N0, 2739 DAG.getConstant(1,TLI.getShiftAmountTy())); 2740 WorkList.push_back(SH.Val); 2741 return DAG.getSetCC(VT, SH, N1.getOperand(0), Cond); 2742 } 2743 } 2744 } 2745 } 2746 2747 // Fold away ALL boolean setcc's. 2748 SDOperand Temp; 2749 if (N0.getValueType() == MVT::i1 && foldBooleans) { 2750 switch (Cond) { 2751 default: assert(0 && "Unknown integer setcc!"); 2752 case ISD::SETEQ: // X == Y -> (X^Y)^1 2753 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, N1); 2754 N0 = DAG.getNode(ISD::XOR, MVT::i1, Temp, DAG.getConstant(1, MVT::i1)); 2755 WorkList.push_back(Temp.Val); 2756 break; 2757 case ISD::SETNE: // X != Y --> (X^Y) 2758 N0 = DAG.getNode(ISD::XOR, MVT::i1, N0, N1); 2759 break; 2760 case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> X^1 & Y 2761 case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> X^1 & Y 2762 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1)); 2763 N0 = DAG.getNode(ISD::AND, MVT::i1, N1, Temp); 2764 WorkList.push_back(Temp.Val); 2765 break; 2766 case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> Y^1 & X 2767 case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> Y^1 & X 2768 Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1)); 2769 N0 = DAG.getNode(ISD::AND, MVT::i1, N0, Temp); 2770 WorkList.push_back(Temp.Val); 2771 break; 2772 case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> X^1 | Y 2773 case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> X^1 | Y 2774 Temp = DAG.getNode(ISD::XOR, MVT::i1, N0, DAG.getConstant(1, MVT::i1)); 2775 N0 = DAG.getNode(ISD::OR, MVT::i1, N1, Temp); 2776 WorkList.push_back(Temp.Val); 2777 break; 2778 case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> Y^1 | X 2779 case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> Y^1 | X 2780 Temp = DAG.getNode(ISD::XOR, MVT::i1, N1, DAG.getConstant(1, MVT::i1)); 2781 N0 = DAG.getNode(ISD::OR, MVT::i1, N0, Temp); 2782 break; 2783 } 2784 if (VT != MVT::i1) { 2785 WorkList.push_back(N0.Val); 2786 // FIXME: If running after legalize, we probably can't do this. 2787 N0 = DAG.getNode(ISD::ZERO_EXTEND, VT, N0); 2788 } 2789 return N0; 2790 } 2791 2792 // Could not fold it. 2793 return SDOperand(); 2794} 2795 2796/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 2797/// return a DAG expression to select that will generate the same value by 2798/// multiplying by a magic number. See: 2799/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 2800SDOperand DAGCombiner::BuildSDIV(SDNode *N) { 2801 MVT::ValueType VT = N->getValueType(0); 2802 2803 // Check to see if we can do this. 2804 if (!TLI.isTypeLegal(VT) || (VT != MVT::i32 && VT != MVT::i64)) 2805 return SDOperand(); // BuildSDIV only operates on i32 or i64 2806 if (!TLI.isOperationLegal(ISD::MULHS, VT)) 2807 return SDOperand(); // Make sure the target supports MULHS. 2808 2809 int64_t d = cast<ConstantSDNode>(N->getOperand(1))->getSignExtended(); 2810 ms magics = (VT == MVT::i32) ? magic32(d) : magic64(d); 2811 2812 // Multiply the numerator (operand 0) by the magic value 2813 SDOperand Q = DAG.getNode(ISD::MULHS, VT, N->getOperand(0), 2814 DAG.getConstant(magics.m, VT)); 2815 // If d > 0 and m < 0, add the numerator 2816 if (d > 0 && magics.m < 0) { 2817 Q = DAG.getNode(ISD::ADD, VT, Q, N->getOperand(0)); 2818 WorkList.push_back(Q.Val); 2819 } 2820 // If d < 0 and m > 0, subtract the numerator. 2821 if (d < 0 && magics.m > 0) { 2822 Q = DAG.getNode(ISD::SUB, VT, Q, N->getOperand(0)); 2823 WorkList.push_back(Q.Val); 2824 } 2825 // Shift right algebraic if shift value is nonzero 2826 if (magics.s > 0) { 2827 Q = DAG.getNode(ISD::SRA, VT, Q, 2828 DAG.getConstant(magics.s, TLI.getShiftAmountTy())); 2829 WorkList.push_back(Q.Val); 2830 } 2831 // Extract the sign bit and add it to the quotient 2832 SDOperand T = 2833 DAG.getNode(ISD::SRL, VT, Q, DAG.getConstant(MVT::getSizeInBits(VT)-1, 2834 TLI.getShiftAmountTy())); 2835 WorkList.push_back(T.Val); 2836 return DAG.getNode(ISD::ADD, VT, Q, T); 2837} 2838 2839/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 2840/// return a DAG expression to select that will generate the same value by 2841/// multiplying by a magic number. See: 2842/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 2843SDOperand DAGCombiner::BuildUDIV(SDNode *N) { 2844 MVT::ValueType VT = N->getValueType(0); 2845 2846 // Check to see if we can do this. 2847 if (!TLI.isTypeLegal(VT) || (VT != MVT::i32 && VT != MVT::i64)) 2848 return SDOperand(); // BuildUDIV only operates on i32 or i64 2849 if (!TLI.isOperationLegal(ISD::MULHU, VT)) 2850 return SDOperand(); // Make sure the target supports MULHU. 2851 2852 uint64_t d = cast<ConstantSDNode>(N->getOperand(1))->getValue(); 2853 mu magics = (VT == MVT::i32) ? magicu32(d) : magicu64(d); 2854 2855 // Multiply the numerator (operand 0) by the magic value 2856 SDOperand Q = DAG.getNode(ISD::MULHU, VT, N->getOperand(0), 2857 DAG.getConstant(magics.m, VT)); 2858 WorkList.push_back(Q.Val); 2859 2860 if (magics.a == 0) { 2861 return DAG.getNode(ISD::SRL, VT, Q, 2862 DAG.getConstant(magics.s, TLI.getShiftAmountTy())); 2863 } else { 2864 SDOperand NPQ = DAG.getNode(ISD::SUB, VT, N->getOperand(0), Q); 2865 WorkList.push_back(NPQ.Val); 2866 NPQ = DAG.getNode(ISD::SRL, VT, NPQ, 2867 DAG.getConstant(1, TLI.getShiftAmountTy())); 2868 WorkList.push_back(NPQ.Val); 2869 NPQ = DAG.getNode(ISD::ADD, VT, NPQ, Q); 2870 WorkList.push_back(NPQ.Val); 2871 return DAG.getNode(ISD::SRL, VT, NPQ, 2872 DAG.getConstant(magics.s-1, TLI.getShiftAmountTy())); 2873 } 2874} 2875 2876// SelectionDAG::Combine - This is the entry point for the file. 2877// 2878void SelectionDAG::Combine(bool RunningAfterLegalize) { 2879 /// run - This is the main entry point to this class. 2880 /// 2881 DAGCombiner(*this).Run(RunningAfterLegalize); 2882} 2883