DAGCombiner.cpp revision fd3b7b7df3d539d1244933d375a766d7a7fe6c91
1//===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run 11// both before and after the DAG is legalized. 12// 13//===----------------------------------------------------------------------===// 14 15#define DEBUG_TYPE "dagcombine" 16#include "llvm/CodeGen/SelectionDAG.h" 17#include "llvm/CodeGen/MachineFunction.h" 18#include "llvm/CodeGen/MachineFrameInfo.h" 19#include "llvm/Analysis/AliasAnalysis.h" 20#include "llvm/Target/TargetData.h" 21#include "llvm/Target/TargetFrameInfo.h" 22#include "llvm/Target/TargetLowering.h" 23#include "llvm/Target/TargetMachine.h" 24#include "llvm/Target/TargetOptions.h" 25#include "llvm/ADT/SmallPtrSet.h" 26#include "llvm/ADT/Statistic.h" 27#include "llvm/Support/Compiler.h" 28#include "llvm/Support/CommandLine.h" 29#include "llvm/Support/Debug.h" 30#include "llvm/Support/MathExtras.h" 31#include <algorithm> 32#include <set> 33using namespace llvm; 34 35STATISTIC(NodesCombined , "Number of dag nodes combined"); 36STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created"); 37STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created"); 38 39namespace { 40 static cl::opt<bool> 41 CombinerAA("combiner-alias-analysis", cl::Hidden, 42 cl::desc("Turn on alias analysis during testing")); 43 44 static cl::opt<bool> 45 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden, 46 cl::desc("Include global information in alias analysis")); 47 48//------------------------------ DAGCombiner ---------------------------------// 49 50 class VISIBILITY_HIDDEN DAGCombiner { 51 SelectionDAG &DAG; 52 TargetLowering &TLI; 53 CombineLevel Level; 54 bool LegalOperations; 55 bool LegalTypes; 56 bool Fast; 57 58 // Worklist of all of the nodes that need to be simplified. 59 std::vector<SDNode*> WorkList; 60 61 // AA - Used for DAG load/store alias analysis. 62 AliasAnalysis &AA; 63 64 /// AddUsersToWorkList - When an instruction is simplified, add all users of 65 /// the instruction to the work lists because they might get more simplified 66 /// now. 67 /// 68 void AddUsersToWorkList(SDNode *N) { 69 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 70 UI != UE; ++UI) 71 AddToWorkList(*UI); 72 } 73 74 /// visit - call the node-specific routine that knows how to fold each 75 /// particular type of node. 76 SDValue visit(SDNode *N); 77 78 public: 79 /// AddToWorkList - Add to the work list making sure it's instance is at the 80 /// the back (next to be processed.) 81 void AddToWorkList(SDNode *N) { 82 removeFromWorkList(N); 83 WorkList.push_back(N); 84 } 85 86 /// removeFromWorkList - remove all instances of N from the worklist. 87 /// 88 void removeFromWorkList(SDNode *N) { 89 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N), 90 WorkList.end()); 91 } 92 93 SDValue CombineTo(SDNode *N, const SDValue *To, unsigned NumTo, 94 bool AddTo = true); 95 96 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true) { 97 return CombineTo(N, &Res, 1, AddTo); 98 } 99 100 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, 101 bool AddTo = true) { 102 SDValue To[] = { Res0, Res1 }; 103 return CombineTo(N, To, 2, AddTo); 104 } 105 106 private: 107 108 /// SimplifyDemandedBits - Check the specified integer node value to see if 109 /// it can be simplified or if things it uses can be simplified by bit 110 /// propagation. If so, return true. 111 bool SimplifyDemandedBits(SDValue Op) { 112 APInt Demanded = APInt::getAllOnesValue(Op.getValueSizeInBits()); 113 return SimplifyDemandedBits(Op, Demanded); 114 } 115 116 bool SimplifyDemandedBits(SDValue Op, const APInt &Demanded); 117 118 bool CombineToPreIndexedLoadStore(SDNode *N); 119 bool CombineToPostIndexedLoadStore(SDNode *N); 120 121 122 /// combine - call the node-specific routine that knows how to fold each 123 /// particular type of node. If that doesn't do anything, try the 124 /// target-specific DAG combines. 125 SDValue combine(SDNode *N); 126 127 // Visitation implementation - Implement dag node combining for different 128 // node types. The semantics are as follows: 129 // Return Value: 130 // SDValue.getNode() == 0 - No change was made 131 // SDValue.getNode() == N - N was replaced, is dead and has been handled. 132 // otherwise - N should be replaced by the returned Operand. 133 // 134 SDValue visitTokenFactor(SDNode *N); 135 SDValue visitMERGE_VALUES(SDNode *N); 136 SDValue visitADD(SDNode *N); 137 SDValue visitSUB(SDNode *N); 138 SDValue visitADDC(SDNode *N); 139 SDValue visitADDE(SDNode *N); 140 SDValue visitMUL(SDNode *N); 141 SDValue visitSDIV(SDNode *N); 142 SDValue visitUDIV(SDNode *N); 143 SDValue visitSREM(SDNode *N); 144 SDValue visitUREM(SDNode *N); 145 SDValue visitMULHU(SDNode *N); 146 SDValue visitMULHS(SDNode *N); 147 SDValue visitSMUL_LOHI(SDNode *N); 148 SDValue visitUMUL_LOHI(SDNode *N); 149 SDValue visitSDIVREM(SDNode *N); 150 SDValue visitUDIVREM(SDNode *N); 151 SDValue visitAND(SDNode *N); 152 SDValue visitOR(SDNode *N); 153 SDValue visitXOR(SDNode *N); 154 SDValue SimplifyVBinOp(SDNode *N); 155 SDValue visitSHL(SDNode *N); 156 SDValue visitSRA(SDNode *N); 157 SDValue visitSRL(SDNode *N); 158 SDValue visitCTLZ(SDNode *N); 159 SDValue visitCTTZ(SDNode *N); 160 SDValue visitCTPOP(SDNode *N); 161 SDValue visitSELECT(SDNode *N); 162 SDValue visitSELECT_CC(SDNode *N); 163 SDValue visitSETCC(SDNode *N); 164 SDValue visitSIGN_EXTEND(SDNode *N); 165 SDValue visitZERO_EXTEND(SDNode *N); 166 SDValue visitANY_EXTEND(SDNode *N); 167 SDValue visitSIGN_EXTEND_INREG(SDNode *N); 168 SDValue visitTRUNCATE(SDNode *N); 169 SDValue visitBIT_CONVERT(SDNode *N); 170 SDValue visitBUILD_PAIR(SDNode *N); 171 SDValue visitFADD(SDNode *N); 172 SDValue visitFSUB(SDNode *N); 173 SDValue visitFMUL(SDNode *N); 174 SDValue visitFDIV(SDNode *N); 175 SDValue visitFREM(SDNode *N); 176 SDValue visitFCOPYSIGN(SDNode *N); 177 SDValue visitSINT_TO_FP(SDNode *N); 178 SDValue visitUINT_TO_FP(SDNode *N); 179 SDValue visitFP_TO_SINT(SDNode *N); 180 SDValue visitFP_TO_UINT(SDNode *N); 181 SDValue visitFP_ROUND(SDNode *N); 182 SDValue visitFP_ROUND_INREG(SDNode *N); 183 SDValue visitFP_EXTEND(SDNode *N); 184 SDValue visitFNEG(SDNode *N); 185 SDValue visitFABS(SDNode *N); 186 SDValue visitBRCOND(SDNode *N); 187 SDValue visitBR_CC(SDNode *N); 188 SDValue visitLOAD(SDNode *N); 189 SDValue visitSTORE(SDNode *N); 190 SDValue visitINSERT_VECTOR_ELT(SDNode *N); 191 SDValue visitEXTRACT_VECTOR_ELT(SDNode *N); 192 SDValue visitBUILD_VECTOR(SDNode *N); 193 SDValue visitCONCAT_VECTORS(SDNode *N); 194 SDValue visitVECTOR_SHUFFLE(SDNode *N); 195 196 SDValue XformToShuffleWithZero(SDNode *N); 197 SDValue ReassociateOps(unsigned Opc, SDValue LHS, SDValue RHS); 198 199 SDValue visitShiftByConstant(SDNode *N, unsigned Amt); 200 201 bool SimplifySelectOps(SDNode *SELECT, SDValue LHS, SDValue RHS); 202 SDValue SimplifyBinOpWithSameOpcodeHands(SDNode *N); 203 SDValue SimplifySelect(SDValue N0, SDValue N1, SDValue N2); 204 SDValue SimplifySelectCC(SDValue N0, SDValue N1, SDValue N2, 205 SDValue N3, ISD::CondCode CC, 206 bool NotExtCompare = false); 207 SDValue SimplifySetCC(MVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond, 208 bool foldBooleans = true); 209 SDValue SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 210 unsigned HiOp); 211 SDValue CombineConsecutiveLoads(SDNode *N, MVT VT); 212 SDValue ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *, MVT); 213 SDValue BuildSDIV(SDNode *N); 214 SDValue BuildUDIV(SDNode *N); 215 SDNode *MatchRotate(SDValue LHS, SDValue RHS); 216 SDValue ReduceLoadWidth(SDNode *N); 217 218 SDValue GetDemandedBits(SDValue V, const APInt &Mask); 219 220 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 221 /// looking for aliasing nodes and adding them to the Aliases vector. 222 void GatherAllAliases(SDNode *N, SDValue OriginalChain, 223 SmallVector<SDValue, 8> &Aliases); 224 225 /// isAlias - Return true if there is any possibility that the two addresses 226 /// overlap. 227 bool isAlias(SDValue Ptr1, int64_t Size1, 228 const Value *SrcValue1, int SrcValueOffset1, 229 SDValue Ptr2, int64_t Size2, 230 const Value *SrcValue2, int SrcValueOffset2); 231 232 /// FindAliasInfo - Extracts the relevant alias information from the memory 233 /// node. Returns true if the operand was a load. 234 bool FindAliasInfo(SDNode *N, 235 SDValue &Ptr, int64_t &Size, 236 const Value *&SrcValue, int &SrcValueOffset); 237 238 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, 239 /// looking for a better chain (aliasing node.) 240 SDValue FindBetterChain(SDNode *N, SDValue Chain); 241 242public: 243 DAGCombiner(SelectionDAG &D, AliasAnalysis &A, bool fast) 244 : DAG(D), 245 TLI(D.getTargetLoweringInfo()), 246 Level(Unrestricted), 247 LegalOperations(false), 248 LegalTypes(false), 249 Fast(fast), 250 AA(A) {} 251 252 /// Run - runs the dag combiner on all nodes in the work list 253 void Run(CombineLevel AtLevel); 254 }; 255} 256 257 258namespace { 259/// WorkListRemover - This class is a DAGUpdateListener that removes any deleted 260/// nodes from the worklist. 261class VISIBILITY_HIDDEN WorkListRemover : 262 public SelectionDAG::DAGUpdateListener { 263 DAGCombiner &DC; 264public: 265 explicit WorkListRemover(DAGCombiner &dc) : DC(dc) {} 266 267 virtual void NodeDeleted(SDNode *N, SDNode *E) { 268 DC.removeFromWorkList(N); 269 } 270 271 virtual void NodeUpdated(SDNode *N) { 272 // Ignore updates. 273 } 274}; 275} 276 277//===----------------------------------------------------------------------===// 278// TargetLowering::DAGCombinerInfo implementation 279//===----------------------------------------------------------------------===// 280 281void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) { 282 ((DAGCombiner*)DC)->AddToWorkList(N); 283} 284 285SDValue TargetLowering::DAGCombinerInfo:: 286CombineTo(SDNode *N, const std::vector<SDValue> &To) { 287 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size()); 288} 289 290SDValue TargetLowering::DAGCombinerInfo:: 291CombineTo(SDNode *N, SDValue Res) { 292 return ((DAGCombiner*)DC)->CombineTo(N, Res); 293} 294 295 296SDValue TargetLowering::DAGCombinerInfo:: 297CombineTo(SDNode *N, SDValue Res0, SDValue Res1) { 298 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1); 299} 300 301 302//===----------------------------------------------------------------------===// 303// Helper Functions 304//===----------------------------------------------------------------------===// 305 306/// isNegatibleForFree - Return 1 if we can compute the negated form of the 307/// specified expression for the same cost as the expression itself, or 2 if we 308/// can compute the negated form more cheaply than the expression itself. 309static char isNegatibleForFree(SDValue Op, bool LegalOperations, 310 unsigned Depth = 0) { 311 // No compile time optimizations on this type. 312 if (Op.getValueType() == MVT::ppcf128) 313 return 0; 314 315 // fneg is removable even if it has multiple uses. 316 if (Op.getOpcode() == ISD::FNEG) return 2; 317 318 // Don't allow anything with multiple uses. 319 if (!Op.hasOneUse()) return 0; 320 321 // Don't recurse exponentially. 322 if (Depth > 6) return 0; 323 324 switch (Op.getOpcode()) { 325 default: return false; 326 case ISD::ConstantFP: 327 // Don't invert constant FP values after legalize. The negated constant 328 // isn't necessarily legal. 329 return LegalOperations ? 0 : 1; 330 case ISD::FADD: 331 // FIXME: determine better conditions for this xform. 332 if (!UnsafeFPMath) return 0; 333 334 // -(A+B) -> -A - B 335 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 336 return V; 337 // -(A+B) -> -B - A 338 return isNegatibleForFree(Op.getOperand(1), LegalOperations, Depth+1); 339 case ISD::FSUB: 340 // We can't turn -(A-B) into B-A when we honor signed zeros. 341 if (!UnsafeFPMath) return 0; 342 343 // -(A-B) -> B-A 344 return 1; 345 346 case ISD::FMUL: 347 case ISD::FDIV: 348 if (HonorSignDependentRoundingFPMath()) return 0; 349 350 // -(X*Y) -> (-X * Y) or (X*-Y) 351 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 352 return V; 353 354 return isNegatibleForFree(Op.getOperand(1), LegalOperations, Depth+1); 355 356 case ISD::FP_EXTEND: 357 case ISD::FP_ROUND: 358 case ISD::FSIN: 359 return isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1); 360 } 361} 362 363/// GetNegatedExpression - If isNegatibleForFree returns true, this function 364/// returns the newly negated expression. 365static SDValue GetNegatedExpression(SDValue Op, SelectionDAG &DAG, 366 bool LegalOperations, unsigned Depth = 0) { 367 // fneg is removable even if it has multiple uses. 368 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0); 369 370 // Don't allow anything with multiple uses. 371 assert(Op.hasOneUse() && "Unknown reuse!"); 372 373 assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree"); 374 switch (Op.getOpcode()) { 375 default: assert(0 && "Unknown code"); 376 case ISD::ConstantFP: { 377 APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF(); 378 V.changeSign(); 379 return DAG.getConstantFP(V, Op.getValueType()); 380 } 381 case ISD::FADD: 382 // FIXME: determine better conditions for this xform. 383 assert(UnsafeFPMath); 384 385 // -(A+B) -> -A - B 386 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 387 return DAG.getNode(ISD::FSUB, Op.getValueType(), 388 GetNegatedExpression(Op.getOperand(0), DAG, 389 LegalOperations, Depth+1), 390 Op.getOperand(1)); 391 // -(A+B) -> -B - A 392 return DAG.getNode(ISD::FSUB, Op.getValueType(), 393 GetNegatedExpression(Op.getOperand(1), DAG, 394 LegalOperations, Depth+1), 395 Op.getOperand(0)); 396 case ISD::FSUB: 397 // We can't turn -(A-B) into B-A when we honor signed zeros. 398 assert(UnsafeFPMath); 399 400 // -(0-B) -> B 401 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(Op.getOperand(0))) 402 if (N0CFP->getValueAPF().isZero()) 403 return Op.getOperand(1); 404 405 // -(A-B) -> B-A 406 return DAG.getNode(ISD::FSUB, Op.getValueType(), Op.getOperand(1), 407 Op.getOperand(0)); 408 409 case ISD::FMUL: 410 case ISD::FDIV: 411 assert(!HonorSignDependentRoundingFPMath()); 412 413 // -(X*Y) -> -X * Y 414 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) 415 return DAG.getNode(Op.getOpcode(), Op.getValueType(), 416 GetNegatedExpression(Op.getOperand(0), DAG, 417 LegalOperations, Depth+1), 418 Op.getOperand(1)); 419 420 // -(X*Y) -> X * -Y 421 return DAG.getNode(Op.getOpcode(), Op.getValueType(), 422 Op.getOperand(0), 423 GetNegatedExpression(Op.getOperand(1), DAG, 424 LegalOperations, Depth+1)); 425 426 case ISD::FP_EXTEND: 427 case ISD::FSIN: 428 return DAG.getNode(Op.getOpcode(), Op.getValueType(), 429 GetNegatedExpression(Op.getOperand(0), DAG, 430 LegalOperations, Depth+1)); 431 case ISD::FP_ROUND: 432 return DAG.getNode(ISD::FP_ROUND, Op.getValueType(), 433 GetNegatedExpression(Op.getOperand(0), DAG, 434 LegalOperations, Depth+1), 435 Op.getOperand(1)); 436 } 437} 438 439 440// isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc 441// that selects between the values 1 and 0, making it equivalent to a setcc. 442// Also, set the incoming LHS, RHS, and CC references to the appropriate 443// nodes based on the type of node we are checking. This simplifies life a 444// bit for the callers. 445static bool isSetCCEquivalent(SDValue N, SDValue &LHS, SDValue &RHS, 446 SDValue &CC) { 447 if (N.getOpcode() == ISD::SETCC) { 448 LHS = N.getOperand(0); 449 RHS = N.getOperand(1); 450 CC = N.getOperand(2); 451 return true; 452 } 453 if (N.getOpcode() == ISD::SELECT_CC && 454 N.getOperand(2).getOpcode() == ISD::Constant && 455 N.getOperand(3).getOpcode() == ISD::Constant && 456 cast<ConstantSDNode>(N.getOperand(2))->getAPIntValue() == 1 && 457 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) { 458 LHS = N.getOperand(0); 459 RHS = N.getOperand(1); 460 CC = N.getOperand(4); 461 return true; 462 } 463 return false; 464} 465 466// isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only 467// one use. If this is true, it allows the users to invert the operation for 468// free when it is profitable to do so. 469static bool isOneUseSetCC(SDValue N) { 470 SDValue N0, N1, N2; 471 if (isSetCCEquivalent(N, N0, N1, N2) && N.getNode()->hasOneUse()) 472 return true; 473 return false; 474} 475 476SDValue DAGCombiner::ReassociateOps(unsigned Opc, SDValue N0, SDValue N1){ 477 MVT VT = N0.getValueType(); 478 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use 479 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2)) 480 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) { 481 if (isa<ConstantSDNode>(N1)) { 482 SDValue OpNode = DAG.getNode(Opc, VT, N0.getOperand(1), N1); 483 AddToWorkList(OpNode.getNode()); 484 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(0)); 485 } else if (N0.hasOneUse()) { 486 SDValue OpNode = DAG.getNode(Opc, VT, N0.getOperand(0), N1); 487 AddToWorkList(OpNode.getNode()); 488 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(1)); 489 } 490 } 491 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use 492 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2)) 493 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) { 494 if (isa<ConstantSDNode>(N0)) { 495 SDValue OpNode = DAG.getNode(Opc, VT, N1.getOperand(1), N0); 496 AddToWorkList(OpNode.getNode()); 497 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(0)); 498 } else if (N1.hasOneUse()) { 499 SDValue OpNode = DAG.getNode(Opc, VT, N1.getOperand(0), N0); 500 AddToWorkList(OpNode.getNode()); 501 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(1)); 502 } 503 } 504 return SDValue(); 505} 506 507SDValue DAGCombiner::CombineTo(SDNode *N, const SDValue *To, unsigned NumTo, 508 bool AddTo) { 509 assert(N->getNumValues() == NumTo && "Broken CombineTo call!"); 510 ++NodesCombined; 511 DOUT << "\nReplacing.1 "; DEBUG(N->dump(&DAG)); 512 DOUT << "\nWith: "; DEBUG(To[0].getNode()->dump(&DAG)); 513 DOUT << " and " << NumTo-1 << " other values\n"; 514 WorkListRemover DeadNodes(*this); 515 DAG.ReplaceAllUsesWith(N, To, &DeadNodes); 516 517 if (AddTo) { 518 // Push the new nodes and any users onto the worklist 519 for (unsigned i = 0, e = NumTo; i != e; ++i) { 520 AddToWorkList(To[i].getNode()); 521 AddUsersToWorkList(To[i].getNode()); 522 } 523 } 524 525 // Nodes can be reintroduced into the worklist. Make sure we do not 526 // process a node that has been replaced. 527 removeFromWorkList(N); 528 529 // Finally, since the node is now dead, remove it from the graph. 530 DAG.DeleteNode(N); 531 return SDValue(N, 0); 532} 533 534/// SimplifyDemandedBits - Check the specified integer node value to see if 535/// it can be simplified or if things it uses can be simplified by bit 536/// propagation. If so, return true. 537bool DAGCombiner::SimplifyDemandedBits(SDValue Op, const APInt &Demanded) { 538 TargetLowering::TargetLoweringOpt TLO(DAG); 539 APInt KnownZero, KnownOne; 540 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO)) 541 return false; 542 543 // Revisit the node. 544 AddToWorkList(Op.getNode()); 545 546 // Replace the old value with the new one. 547 ++NodesCombined; 548 DOUT << "\nReplacing.2 "; DEBUG(TLO.Old.getNode()->dump(&DAG)); 549 DOUT << "\nWith: "; DEBUG(TLO.New.getNode()->dump(&DAG)); 550 DOUT << '\n'; 551 552 // Replace all uses. If any nodes become isomorphic to other nodes and 553 // are deleted, make sure to remove them from our worklist. 554 WorkListRemover DeadNodes(*this); 555 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &DeadNodes); 556 557 // Push the new node and any (possibly new) users onto the worklist. 558 AddToWorkList(TLO.New.getNode()); 559 AddUsersToWorkList(TLO.New.getNode()); 560 561 // Finally, if the node is now dead, remove it from the graph. The node 562 // may not be dead if the replacement process recursively simplified to 563 // something else needing this node. 564 if (TLO.Old.getNode()->use_empty()) { 565 removeFromWorkList(TLO.Old.getNode()); 566 567 // If the operands of this node are only used by the node, they will now 568 // be dead. Make sure to visit them first to delete dead nodes early. 569 for (unsigned i = 0, e = TLO.Old.getNode()->getNumOperands(); i != e; ++i) 570 if (TLO.Old.getNode()->getOperand(i).getNode()->hasOneUse()) 571 AddToWorkList(TLO.Old.getNode()->getOperand(i).getNode()); 572 573 DAG.DeleteNode(TLO.Old.getNode()); 574 } 575 return true; 576} 577 578//===----------------------------------------------------------------------===// 579// Main DAG Combiner implementation 580//===----------------------------------------------------------------------===// 581 582void DAGCombiner::Run(CombineLevel AtLevel) { 583 // set the instance variables, so that the various visit routines may use it. 584 Level = AtLevel; 585 LegalOperations = Level >= NoIllegalOperations; 586 LegalTypes = Level >= NoIllegalTypes; 587 588 // Add all the dag nodes to the worklist. 589 WorkList.reserve(DAG.allnodes_size()); 590 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 591 E = DAG.allnodes_end(); I != E; ++I) 592 WorkList.push_back(I); 593 594 // Create a dummy node (which is not added to allnodes), that adds a reference 595 // to the root node, preventing it from being deleted, and tracking any 596 // changes of the root. 597 HandleSDNode Dummy(DAG.getRoot()); 598 599 // The root of the dag may dangle to deleted nodes until the dag combiner is 600 // done. Set it to null to avoid confusion. 601 DAG.setRoot(SDValue()); 602 603 // while the worklist isn't empty, inspect the node on the end of it and 604 // try and combine it. 605 while (!WorkList.empty()) { 606 SDNode *N = WorkList.back(); 607 WorkList.pop_back(); 608 609 // If N has no uses, it is dead. Make sure to revisit all N's operands once 610 // N is deleted from the DAG, since they too may now be dead or may have a 611 // reduced number of uses, allowing other xforms. 612 if (N->use_empty() && N != &Dummy) { 613 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 614 AddToWorkList(N->getOperand(i).getNode()); 615 616 DAG.DeleteNode(N); 617 continue; 618 } 619 620 SDValue RV = combine(N); 621 622 if (RV.getNode() == 0) 623 continue; 624 625 ++NodesCombined; 626 627 // If we get back the same node we passed in, rather than a new node or 628 // zero, we know that the node must have defined multiple values and 629 // CombineTo was used. Since CombineTo takes care of the worklist 630 // mechanics for us, we have no work to do in this case. 631 if (RV.getNode() == N) 632 continue; 633 634 assert(N->getOpcode() != ISD::DELETED_NODE && 635 RV.getNode()->getOpcode() != ISD::DELETED_NODE && 636 "Node was deleted but visit returned new node!"); 637 638 DOUT << "\nReplacing.3 "; DEBUG(N->dump(&DAG)); 639 DOUT << "\nWith: "; DEBUG(RV.getNode()->dump(&DAG)); 640 DOUT << '\n'; 641 WorkListRemover DeadNodes(*this); 642 if (N->getNumValues() == RV.getNode()->getNumValues()) 643 DAG.ReplaceAllUsesWith(N, RV.getNode(), &DeadNodes); 644 else { 645 assert(N->getValueType(0) == RV.getValueType() && 646 N->getNumValues() == 1 && "Type mismatch"); 647 SDValue OpV = RV; 648 DAG.ReplaceAllUsesWith(N, &OpV, &DeadNodes); 649 } 650 651 // Push the new node and any users onto the worklist 652 AddToWorkList(RV.getNode()); 653 AddUsersToWorkList(RV.getNode()); 654 655 // Add any uses of the old node to the worklist in case this node is the 656 // last one that uses them. They may become dead after this node is 657 // deleted. 658 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 659 AddToWorkList(N->getOperand(i).getNode()); 660 661 // Nodes can be reintroduced into the worklist. Make sure we do not 662 // process a node that has been replaced. 663 removeFromWorkList(N); 664 665 // Finally, since the node is now dead, remove it from the graph. 666 DAG.DeleteNode(N); 667 } 668 669 // If the root changed (e.g. it was a dead load, update the root). 670 DAG.setRoot(Dummy.getValue()); 671} 672 673SDValue DAGCombiner::visit(SDNode *N) { 674 switch(N->getOpcode()) { 675 default: break; 676 case ISD::TokenFactor: return visitTokenFactor(N); 677 case ISD::MERGE_VALUES: return visitMERGE_VALUES(N); 678 case ISD::ADD: return visitADD(N); 679 case ISD::SUB: return visitSUB(N); 680 case ISD::ADDC: return visitADDC(N); 681 case ISD::ADDE: return visitADDE(N); 682 case ISD::MUL: return visitMUL(N); 683 case ISD::SDIV: return visitSDIV(N); 684 case ISD::UDIV: return visitUDIV(N); 685 case ISD::SREM: return visitSREM(N); 686 case ISD::UREM: return visitUREM(N); 687 case ISD::MULHU: return visitMULHU(N); 688 case ISD::MULHS: return visitMULHS(N); 689 case ISD::SMUL_LOHI: return visitSMUL_LOHI(N); 690 case ISD::UMUL_LOHI: return visitUMUL_LOHI(N); 691 case ISD::SDIVREM: return visitSDIVREM(N); 692 case ISD::UDIVREM: return visitUDIVREM(N); 693 case ISD::AND: return visitAND(N); 694 case ISD::OR: return visitOR(N); 695 case ISD::XOR: return visitXOR(N); 696 case ISD::SHL: return visitSHL(N); 697 case ISD::SRA: return visitSRA(N); 698 case ISD::SRL: return visitSRL(N); 699 case ISD::CTLZ: return visitCTLZ(N); 700 case ISD::CTTZ: return visitCTTZ(N); 701 case ISD::CTPOP: return visitCTPOP(N); 702 case ISD::SELECT: return visitSELECT(N); 703 case ISD::SELECT_CC: return visitSELECT_CC(N); 704 case ISD::SETCC: return visitSETCC(N); 705 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N); 706 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N); 707 case ISD::ANY_EXTEND: return visitANY_EXTEND(N); 708 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N); 709 case ISD::TRUNCATE: return visitTRUNCATE(N); 710 case ISD::BIT_CONVERT: return visitBIT_CONVERT(N); 711 case ISD::BUILD_PAIR: return visitBUILD_PAIR(N); 712 case ISD::FADD: return visitFADD(N); 713 case ISD::FSUB: return visitFSUB(N); 714 case ISD::FMUL: return visitFMUL(N); 715 case ISD::FDIV: return visitFDIV(N); 716 case ISD::FREM: return visitFREM(N); 717 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N); 718 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N); 719 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N); 720 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N); 721 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N); 722 case ISD::FP_ROUND: return visitFP_ROUND(N); 723 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N); 724 case ISD::FP_EXTEND: return visitFP_EXTEND(N); 725 case ISD::FNEG: return visitFNEG(N); 726 case ISD::FABS: return visitFABS(N); 727 case ISD::BRCOND: return visitBRCOND(N); 728 case ISD::BR_CC: return visitBR_CC(N); 729 case ISD::LOAD: return visitLOAD(N); 730 case ISD::STORE: return visitSTORE(N); 731 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N); 732 case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N); 733 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N); 734 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N); 735 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N); 736 } 737 return SDValue(); 738} 739 740SDValue DAGCombiner::combine(SDNode *N) { 741 742 SDValue RV = visit(N); 743 744 // If nothing happened, try a target-specific DAG combine. 745 if (RV.getNode() == 0) { 746 assert(N->getOpcode() != ISD::DELETED_NODE && 747 "Node was deleted but visit returned NULL!"); 748 749 if (N->getOpcode() >= ISD::BUILTIN_OP_END || 750 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) { 751 752 // Expose the DAG combiner to the target combiner impls. 753 TargetLowering::DAGCombinerInfo 754 DagCombineInfo(DAG, Level == Unrestricted, false, this); 755 756 RV = TLI.PerformDAGCombine(N, DagCombineInfo); 757 } 758 } 759 760 // If N is a commutative binary node, try commuting it to enable more 761 // sdisel CSE. 762 if (RV.getNode() == 0 && 763 SelectionDAG::isCommutativeBinOp(N->getOpcode()) && 764 N->getNumValues() == 1) { 765 SDValue N0 = N->getOperand(0); 766 SDValue N1 = N->getOperand(1); 767 // Constant operands are canonicalized to RHS. 768 if (isa<ConstantSDNode>(N0) || !isa<ConstantSDNode>(N1)) { 769 SDValue Ops[] = { N1, N0 }; 770 SDNode *CSENode = DAG.getNodeIfExists(N->getOpcode(), N->getVTList(), 771 Ops, 2); 772 if (CSENode) 773 return SDValue(CSENode, 0); 774 } 775 } 776 777 return RV; 778} 779 780/// getInputChainForNode - Given a node, return its input chain if it has one, 781/// otherwise return a null sd operand. 782static SDValue getInputChainForNode(SDNode *N) { 783 if (unsigned NumOps = N->getNumOperands()) { 784 if (N->getOperand(0).getValueType() == MVT::Other) 785 return N->getOperand(0); 786 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other) 787 return N->getOperand(NumOps-1); 788 for (unsigned i = 1; i < NumOps-1; ++i) 789 if (N->getOperand(i).getValueType() == MVT::Other) 790 return N->getOperand(i); 791 } 792 return SDValue(0, 0); 793} 794 795SDValue DAGCombiner::visitTokenFactor(SDNode *N) { 796 // If N has two operands, where one has an input chain equal to the other, 797 // the 'other' chain is redundant. 798 if (N->getNumOperands() == 2) { 799 if (getInputChainForNode(N->getOperand(0).getNode()) == N->getOperand(1)) 800 return N->getOperand(0); 801 if (getInputChainForNode(N->getOperand(1).getNode()) == N->getOperand(0)) 802 return N->getOperand(1); 803 } 804 805 SmallVector<SDNode *, 8> TFs; // List of token factors to visit. 806 SmallVector<SDValue, 8> Ops; // Ops for replacing token factor. 807 SmallPtrSet<SDNode*, 16> SeenOps; 808 bool Changed = false; // If we should replace this token factor. 809 810 // Start out with this token factor. 811 TFs.push_back(N); 812 813 // Iterate through token factors. The TFs grows when new token factors are 814 // encountered. 815 for (unsigned i = 0; i < TFs.size(); ++i) { 816 SDNode *TF = TFs[i]; 817 818 // Check each of the operands. 819 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) { 820 SDValue Op = TF->getOperand(i); 821 822 switch (Op.getOpcode()) { 823 case ISD::EntryToken: 824 // Entry tokens don't need to be added to the list. They are 825 // rededundant. 826 Changed = true; 827 break; 828 829 case ISD::TokenFactor: 830 if ((CombinerAA || Op.hasOneUse()) && 831 std::find(TFs.begin(), TFs.end(), Op.getNode()) == TFs.end()) { 832 // Queue up for processing. 833 TFs.push_back(Op.getNode()); 834 // Clean up in case the token factor is removed. 835 AddToWorkList(Op.getNode()); 836 Changed = true; 837 break; 838 } 839 // Fall thru 840 841 default: 842 // Only add if it isn't already in the list. 843 if (SeenOps.insert(Op.getNode())) 844 Ops.push_back(Op); 845 else 846 Changed = true; 847 break; 848 } 849 } 850 } 851 852 SDValue Result; 853 854 // If we've change things around then replace token factor. 855 if (Changed) { 856 if (Ops.empty()) { 857 // The entry token is the only possible outcome. 858 Result = DAG.getEntryNode(); 859 } else { 860 // New and improved token factor. 861 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, &Ops[0], Ops.size()); 862 } 863 864 // Don't add users to work list. 865 return CombineTo(N, Result, false); 866 } 867 868 return Result; 869} 870 871/// MERGE_VALUES can always be eliminated. 872SDValue DAGCombiner::visitMERGE_VALUES(SDNode *N) { 873 WorkListRemover DeadNodes(*this); 874 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 875 DAG.ReplaceAllUsesOfValueWith(SDValue(N, i), N->getOperand(i), 876 &DeadNodes); 877 removeFromWorkList(N); 878 DAG.DeleteNode(N); 879 return SDValue(N, 0); // Return N so it doesn't get rechecked! 880} 881 882 883static 884SDValue combineShlAddConstant(SDValue N0, SDValue N1, SelectionDAG &DAG) { 885 MVT VT = N0.getValueType(); 886 SDValue N00 = N0.getOperand(0); 887 SDValue N01 = N0.getOperand(1); 888 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01); 889 if (N01C && N00.getOpcode() == ISD::ADD && N00.getNode()->hasOneUse() && 890 isa<ConstantSDNode>(N00.getOperand(1))) { 891 N0 = DAG.getNode(ISD::ADD, VT, 892 DAG.getNode(ISD::SHL, VT, N00.getOperand(0), N01), 893 DAG.getNode(ISD::SHL, VT, N00.getOperand(1), N01)); 894 return DAG.getNode(ISD::ADD, VT, N0, N1); 895 } 896 return SDValue(); 897} 898 899static 900SDValue combineSelectAndUse(SDNode *N, SDValue Slct, SDValue OtherOp, 901 SelectionDAG &DAG, const TargetLowering &TLI, 902 bool LegalOperations) { 903 MVT VT = N->getValueType(0); 904 unsigned Opc = N->getOpcode(); 905 bool isSlctCC = Slct.getOpcode() == ISD::SELECT_CC; 906 SDValue LHS = isSlctCC ? Slct.getOperand(2) : Slct.getOperand(1); 907 SDValue RHS = isSlctCC ? Slct.getOperand(3) : Slct.getOperand(2); 908 ISD::CondCode CC = ISD::SETCC_INVALID; 909 910 if (isSlctCC) { 911 CC = cast<CondCodeSDNode>(Slct.getOperand(4))->get(); 912 } else { 913 SDValue CCOp = Slct.getOperand(0); 914 if (CCOp.getOpcode() == ISD::SETCC) 915 CC = cast<CondCodeSDNode>(CCOp.getOperand(2))->get(); 916 } 917 918 bool DoXform = false; 919 bool InvCC = false; 920 assert ((Opc == ISD::ADD || (Opc == ISD::SUB && Slct == N->getOperand(1))) && 921 "Bad input!"); 922 923 if (LHS.getOpcode() == ISD::Constant && 924 cast<ConstantSDNode>(LHS)->isNullValue()) { 925 DoXform = true; 926 } else if (CC != ISD::SETCC_INVALID && 927 RHS.getOpcode() == ISD::Constant && 928 cast<ConstantSDNode>(RHS)->isNullValue()) { 929 std::swap(LHS, RHS); 930 SDValue Op0 = Slct.getOperand(0); 931 MVT OpVT = isSlctCC ? Op0.getValueType() : 932 Op0.getOperand(0).getValueType(); 933 bool isInt = OpVT.isInteger(); 934 CC = ISD::getSetCCInverse(CC, isInt); 935 936 if (LegalOperations && !TLI.isCondCodeLegal(CC, OpVT)) 937 return SDValue(); // Inverse operator isn't legal. 938 939 DoXform = true; 940 InvCC = true; 941 } 942 943 if (DoXform) { 944 SDValue Result = DAG.getNode(Opc, VT, OtherOp, RHS); 945 if (isSlctCC) 946 return DAG.getSelectCC(OtherOp, Result, 947 Slct.getOperand(0), Slct.getOperand(1), CC); 948 SDValue CCOp = Slct.getOperand(0); 949 if (InvCC) 950 CCOp = DAG.getSetCC(CCOp.getValueType(), CCOp.getOperand(0), 951 CCOp.getOperand(1), CC); 952 return DAG.getNode(ISD::SELECT, VT, CCOp, OtherOp, Result); 953 } 954 return SDValue(); 955} 956 957SDValue DAGCombiner::visitADD(SDNode *N) { 958 SDValue N0 = N->getOperand(0); 959 SDValue N1 = N->getOperand(1); 960 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 961 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 962 MVT VT = N0.getValueType(); 963 964 // fold vector ops 965 if (VT.isVector()) { 966 SDValue FoldedVOp = SimplifyVBinOp(N); 967 if (FoldedVOp.getNode()) return FoldedVOp; 968 } 969 970 // fold (add x, undef) -> undef 971 if (N0.getOpcode() == ISD::UNDEF) 972 return N0; 973 if (N1.getOpcode() == ISD::UNDEF) 974 return N1; 975 // fold (add c1, c2) -> c1+c2 976 if (N0C && N1C) 977 return DAG.FoldConstantArithmetic(ISD::ADD, VT, N0C, N1C); 978 // canonicalize constant to RHS 979 if (N0C && !N1C) 980 return DAG.getNode(ISD::ADD, VT, N1, N0); 981 // fold (add x, 0) -> x 982 if (N1C && N1C->isNullValue()) 983 return N0; 984 // fold (add Sym, c) -> Sym+c 985 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0)) 986 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA) && N1C && 987 GA->getOpcode() == ISD::GlobalAddress) 988 return DAG.getGlobalAddress(GA->getGlobal(), VT, 989 GA->getOffset() + 990 (uint64_t)N1C->getSExtValue()); 991 // fold ((c1-A)+c2) -> (c1+c2)-A 992 if (N1C && N0.getOpcode() == ISD::SUB) 993 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0))) 994 return DAG.getNode(ISD::SUB, VT, 995 DAG.getConstant(N1C->getAPIntValue()+ 996 N0C->getAPIntValue(), VT), 997 N0.getOperand(1)); 998 // reassociate add 999 SDValue RADD = ReassociateOps(ISD::ADD, N0, N1); 1000 if (RADD.getNode() != 0) 1001 return RADD; 1002 // fold ((0-A) + B) -> B-A 1003 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) && 1004 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue()) 1005 return DAG.getNode(ISD::SUB, VT, N1, N0.getOperand(1)); 1006 // fold (A + (0-B)) -> A-B 1007 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) && 1008 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue()) 1009 return DAG.getNode(ISD::SUB, VT, N0, N1.getOperand(1)); 1010 // fold (A+(B-A)) -> B 1011 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1)) 1012 return N1.getOperand(0); 1013 // fold ((B-A)+A) -> B 1014 if (N0.getOpcode() == ISD::SUB && N1 == N0.getOperand(1)) 1015 return N0.getOperand(0); 1016 // fold (A+(B-(A+C))) to (B-C) 1017 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD && 1018 N0 == N1.getOperand(1).getOperand(0)) { 1019 return DAG.getNode(ISD::SUB, VT, N1.getOperand(0), 1020 N1.getOperand(1).getOperand(1)); 1021 } 1022 // fold (A+(B-(C+A))) to (B-C) 1023 if (N1.getOpcode() == ISD::SUB && N1.getOperand(1).getOpcode() == ISD::ADD && 1024 N0 == N1.getOperand(1).getOperand(1)) { 1025 return DAG.getNode(ISD::SUB, VT, N1.getOperand(0), 1026 N1.getOperand(1).getOperand(0)); 1027 } 1028 // fold (A+((B-A)+-C)) to (B+-C) 1029 if ((N1.getOpcode() == ISD::SUB || N1.getOpcode() == ISD::ADD) && 1030 N1.getOperand(0).getOpcode() == ISD::SUB && 1031 N0 == N1.getOperand(0).getOperand(1)) { 1032 return DAG.getNode(N1.getOpcode(), VT, N1.getOperand(0).getOperand(0), 1033 N1.getOperand(1)); 1034 } 1035 1036 // fold (A-B)+(C-D) to (A+C)-(B+D) when A or C is constant 1037 if (N0.getOpcode() == ISD::SUB && N1.getOpcode() == ISD::SUB) { 1038 SDValue N00 = N0.getOperand(0); 1039 SDValue N01 = N0.getOperand(1); 1040 SDValue N10 = N1.getOperand(0); 1041 SDValue N11 = N1.getOperand(1); 1042 if (isa<ConstantSDNode>(N00) || isa<ConstantSDNode>(N10)) { 1043 return DAG.getNode(ISD::SUB, VT, 1044 DAG.getNode(ISD::ADD, VT, N00, N10), 1045 DAG.getNode(ISD::ADD, VT, N01, N11)); 1046 } 1047 } 1048 1049 if (!VT.isVector() && SimplifyDemandedBits(SDValue(N, 0))) 1050 return SDValue(N, 0); 1051 1052 // fold (a+b) -> (a|b) iff a and b share no bits. 1053 if (VT.isInteger() && !VT.isVector()) { 1054 APInt LHSZero, LHSOne; 1055 APInt RHSZero, RHSOne; 1056 APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits()); 1057 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 1058 if (LHSZero.getBoolValue()) { 1059 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 1060 1061 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1062 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1063 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 1064 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 1065 return DAG.getNode(ISD::OR, VT, N0, N1); 1066 } 1067 } 1068 1069 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 1070 if (N0.getOpcode() == ISD::SHL && N0.getNode()->hasOneUse()) { 1071 SDValue Result = combineShlAddConstant(N0, N1, DAG); 1072 if (Result.getNode()) return Result; 1073 } 1074 if (N1.getOpcode() == ISD::SHL && N1.getNode()->hasOneUse()) { 1075 SDValue Result = combineShlAddConstant(N1, N0, DAG); 1076 if (Result.getNode()) return Result; 1077 } 1078 1079 // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c)) 1080 if (N0.getOpcode() == ISD::SELECT && N0.getNode()->hasOneUse()) { 1081 SDValue Result = combineSelectAndUse(N, N0, N1, DAG, TLI, LegalOperations); 1082 if (Result.getNode()) return Result; 1083 } 1084 if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) { 1085 SDValue Result = combineSelectAndUse(N, N1, N0, DAG, TLI, LegalOperations); 1086 if (Result.getNode()) return Result; 1087 } 1088 1089 return SDValue(); 1090} 1091 1092SDValue DAGCombiner::visitADDC(SDNode *N) { 1093 SDValue N0 = N->getOperand(0); 1094 SDValue N1 = N->getOperand(1); 1095 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1096 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1097 MVT VT = N0.getValueType(); 1098 1099 // If the flag result is dead, turn this into an ADD. 1100 if (N->hasNUsesOfValue(0, 1)) 1101 return CombineTo(N, DAG.getNode(ISD::ADD, VT, N1, N0), 1102 DAG.getNode(ISD::CARRY_FALSE, MVT::Flag)); 1103 1104 // canonicalize constant to RHS. 1105 if (N0C && !N1C) 1106 return DAG.getNode(ISD::ADDC, N->getVTList(), N1, N0); 1107 1108 // fold (addc x, 0) -> x + no carry out 1109 if (N1C && N1C->isNullValue()) 1110 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, MVT::Flag)); 1111 1112 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits. 1113 APInt LHSZero, LHSOne; 1114 APInt RHSZero, RHSOne; 1115 APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits()); 1116 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 1117 if (LHSZero.getBoolValue()) { 1118 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 1119 1120 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1121 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1122 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 1123 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 1124 return CombineTo(N, DAG.getNode(ISD::OR, VT, N0, N1), 1125 DAG.getNode(ISD::CARRY_FALSE, MVT::Flag)); 1126 } 1127 1128 return SDValue(); 1129} 1130 1131SDValue DAGCombiner::visitADDE(SDNode *N) { 1132 SDValue N0 = N->getOperand(0); 1133 SDValue N1 = N->getOperand(1); 1134 SDValue CarryIn = N->getOperand(2); 1135 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1136 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1137 //MVT VT = N0.getValueType(); 1138 1139 // canonicalize constant to RHS 1140 if (N0C && !N1C) 1141 return DAG.getNode(ISD::ADDE, N->getVTList(), N1, N0, CarryIn); 1142 1143 // fold (adde x, y, false) -> (addc x, y) 1144 if (CarryIn.getOpcode() == ISD::CARRY_FALSE) 1145 return DAG.getNode(ISD::ADDC, N->getVTList(), N1, N0); 1146 1147 return SDValue(); 1148} 1149 1150 1151 1152SDValue DAGCombiner::visitSUB(SDNode *N) { 1153 SDValue N0 = N->getOperand(0); 1154 SDValue N1 = N->getOperand(1); 1155 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1156 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1157 MVT VT = N0.getValueType(); 1158 1159 // fold vector ops 1160 if (VT.isVector()) { 1161 SDValue FoldedVOp = SimplifyVBinOp(N); 1162 if (FoldedVOp.getNode()) return FoldedVOp; 1163 } 1164 1165 // fold (sub x, x) -> 0 1166 if (N0 == N1) 1167 return DAG.getConstant(0, N->getValueType(0)); 1168 // fold (sub c1, c2) -> c1-c2 1169 if (N0C && N1C) 1170 return DAG.FoldConstantArithmetic(ISD::SUB, VT, N0C, N1C); 1171 // fold (sub x, c) -> (add x, -c) 1172 if (N1C) 1173 return DAG.getNode(ISD::ADD, VT, N0, 1174 DAG.getConstant(-N1C->getAPIntValue(), VT)); 1175 // fold (A+B)-A -> B 1176 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1) 1177 return N0.getOperand(1); 1178 // fold (A+B)-B -> A 1179 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1) 1180 return N0.getOperand(0); 1181 // fold ((A+(B-C))-B) -> A-C 1182 if (N0.getOpcode() == ISD::ADD && 1183 N0.getOperand(1).getOpcode() == ISD::SUB && 1184 N0.getOperand(1).getOperand(0) == N1) 1185 return DAG.getNode(ISD::SUB, VT, N0.getOperand(0), 1186 N0.getOperand(1).getOperand(1)); 1187 // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c)) 1188 if (N1.getOpcode() == ISD::SELECT && N1.getNode()->hasOneUse()) { 1189 SDValue Result = combineSelectAndUse(N, N1, N0, DAG, TLI, LegalOperations); 1190 if (Result.getNode()) return Result; 1191 } 1192 // If either operand of a sub is undef, the result is undef 1193 if (N0.getOpcode() == ISD::UNDEF) 1194 return N0; 1195 if (N1.getOpcode() == ISD::UNDEF) 1196 return N1; 1197 1198 // If the relocation model supports it, consider symbol offsets. 1199 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(N0)) 1200 if (!LegalOperations && TLI.isOffsetFoldingLegal(GA)) { 1201 // fold (sub Sym, c) -> Sym-c 1202 if (N1C && GA->getOpcode() == ISD::GlobalAddress) 1203 return DAG.getGlobalAddress(GA->getGlobal(), VT, 1204 GA->getOffset() - 1205 (uint64_t)N1C->getSExtValue()); 1206 // fold (sub Sym+c1, Sym+c2) -> c1-c2 1207 if (GlobalAddressSDNode *GB = dyn_cast<GlobalAddressSDNode>(N1)) 1208 if (GA->getGlobal() == GB->getGlobal()) 1209 return DAG.getConstant((uint64_t)GA->getOffset() - GB->getOffset(), 1210 VT); 1211 } 1212 1213 return SDValue(); 1214} 1215 1216SDValue DAGCombiner::visitMUL(SDNode *N) { 1217 SDValue N0 = N->getOperand(0); 1218 SDValue N1 = N->getOperand(1); 1219 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1220 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1221 MVT VT = N0.getValueType(); 1222 1223 // fold vector ops 1224 if (VT.isVector()) { 1225 SDValue FoldedVOp = SimplifyVBinOp(N); 1226 if (FoldedVOp.getNode()) return FoldedVOp; 1227 } 1228 1229 // fold (mul x, undef) -> 0 1230 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1231 return DAG.getConstant(0, VT); 1232 // fold (mul c1, c2) -> c1*c2 1233 if (N0C && N1C) 1234 return DAG.FoldConstantArithmetic(ISD::MUL, VT, N0C, N1C); 1235 // canonicalize constant to RHS 1236 if (N0C && !N1C) 1237 return DAG.getNode(ISD::MUL, VT, N1, N0); 1238 // fold (mul x, 0) -> 0 1239 if (N1C && N1C->isNullValue()) 1240 return N1; 1241 // fold (mul x, -1) -> 0-x 1242 if (N1C && N1C->isAllOnesValue()) 1243 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0); 1244 // fold (mul x, (1 << c)) -> x << c 1245 if (N1C && N1C->getAPIntValue().isPowerOf2()) 1246 return DAG.getNode(ISD::SHL, VT, N0, 1247 DAG.getConstant(N1C->getAPIntValue().logBase2(), 1248 TLI.getShiftAmountTy())); 1249 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c 1250 if (N1C && isPowerOf2_64(-N1C->getSExtValue())) { 1251 // FIXME: If the input is something that is easily negated (e.g. a 1252 // single-use add), we should put the negate there. 1253 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), 1254 DAG.getNode(ISD::SHL, VT, N0, 1255 DAG.getConstant(Log2_64(-N1C->getSExtValue()), 1256 TLI.getShiftAmountTy()))); 1257 } 1258 1259 // (mul (shl X, c1), c2) -> (mul X, c2 << c1) 1260 if (N1C && N0.getOpcode() == ISD::SHL && 1261 isa<ConstantSDNode>(N0.getOperand(1))) { 1262 SDValue C3 = DAG.getNode(ISD::SHL, VT, N1, N0.getOperand(1)); 1263 AddToWorkList(C3.getNode()); 1264 return DAG.getNode(ISD::MUL, VT, N0.getOperand(0), C3); 1265 } 1266 1267 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one 1268 // use. 1269 { 1270 SDValue Sh(0,0), Y(0,0); 1271 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)). 1272 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) && 1273 N0.getNode()->hasOneUse()) { 1274 Sh = N0; Y = N1; 1275 } else if (N1.getOpcode() == ISD::SHL && 1276 isa<ConstantSDNode>(N1.getOperand(1)) && 1277 N1.getNode()->hasOneUse()) { 1278 Sh = N1; Y = N0; 1279 } 1280 if (Sh.getNode()) { 1281 SDValue Mul = DAG.getNode(ISD::MUL, VT, Sh.getOperand(0), Y); 1282 return DAG.getNode(ISD::SHL, VT, Mul, Sh.getOperand(1)); 1283 } 1284 } 1285 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2) 1286 if (N1C && N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse() && 1287 isa<ConstantSDNode>(N0.getOperand(1))) { 1288 return DAG.getNode(ISD::ADD, VT, 1289 DAG.getNode(ISD::MUL, VT, N0.getOperand(0), N1), 1290 DAG.getNode(ISD::MUL, VT, N0.getOperand(1), N1)); 1291 } 1292 1293 // reassociate mul 1294 SDValue RMUL = ReassociateOps(ISD::MUL, N0, N1); 1295 if (RMUL.getNode() != 0) 1296 return RMUL; 1297 1298 return SDValue(); 1299} 1300 1301SDValue DAGCombiner::visitSDIV(SDNode *N) { 1302 SDValue N0 = N->getOperand(0); 1303 SDValue N1 = N->getOperand(1); 1304 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1305 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1306 MVT VT = N->getValueType(0); 1307 1308 // fold vector ops 1309 if (VT.isVector()) { 1310 SDValue FoldedVOp = SimplifyVBinOp(N); 1311 if (FoldedVOp.getNode()) return FoldedVOp; 1312 } 1313 1314 // fold (sdiv c1, c2) -> c1/c2 1315 if (N0C && N1C && !N1C->isNullValue()) 1316 return DAG.FoldConstantArithmetic(ISD::SDIV, VT, N0C, N1C); 1317 // fold (sdiv X, 1) -> X 1318 if (N1C && N1C->getSExtValue() == 1LL) 1319 return N0; 1320 // fold (sdiv X, -1) -> 0-X 1321 if (N1C && N1C->isAllOnesValue()) 1322 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0); 1323 // If we know the sign bits of both operands are zero, strength reduce to a 1324 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2 1325 if (!VT.isVector()) { 1326 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 1327 return DAG.getNode(ISD::UDIV, N1.getValueType(), N0, N1); 1328 } 1329 // fold (sdiv X, pow2) -> simple ops after legalize 1330 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap() && 1331 (isPowerOf2_64(N1C->getSExtValue()) || 1332 isPowerOf2_64(-N1C->getSExtValue()))) { 1333 // If dividing by powers of two is cheap, then don't perform the following 1334 // fold. 1335 if (TLI.isPow2DivCheap()) 1336 return SDValue(); 1337 int64_t pow2 = N1C->getSExtValue(); 1338 int64_t abs2 = pow2 > 0 ? pow2 : -pow2; 1339 unsigned lg2 = Log2_64(abs2); 1340 // Splat the sign bit into the register 1341 SDValue SGN = DAG.getNode(ISD::SRA, VT, N0, 1342 DAG.getConstant(VT.getSizeInBits()-1, 1343 TLI.getShiftAmountTy())); 1344 AddToWorkList(SGN.getNode()); 1345 // Add (N0 < 0) ? abs2 - 1 : 0; 1346 SDValue SRL = DAG.getNode(ISD::SRL, VT, SGN, 1347 DAG.getConstant(VT.getSizeInBits()-lg2, 1348 TLI.getShiftAmountTy())); 1349 SDValue ADD = DAG.getNode(ISD::ADD, VT, N0, SRL); 1350 AddToWorkList(SRL.getNode()); 1351 AddToWorkList(ADD.getNode()); // Divide by pow2 1352 SDValue SRA = DAG.getNode(ISD::SRA, VT, ADD, 1353 DAG.getConstant(lg2, TLI.getShiftAmountTy())); 1354 // If we're dividing by a positive value, we're done. Otherwise, we must 1355 // negate the result. 1356 if (pow2 > 0) 1357 return SRA; 1358 AddToWorkList(SRA.getNode()); 1359 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), SRA); 1360 } 1361 // if integer divide is expensive and we satisfy the requirements, emit an 1362 // alternate sequence. 1363 if (N1C && (N1C->getSExtValue() < -1 || N1C->getSExtValue() > 1) && 1364 !TLI.isIntDivCheap()) { 1365 SDValue Op = BuildSDIV(N); 1366 if (Op.getNode()) return Op; 1367 } 1368 1369 // undef / X -> 0 1370 if (N0.getOpcode() == ISD::UNDEF) 1371 return DAG.getConstant(0, VT); 1372 // X / undef -> undef 1373 if (N1.getOpcode() == ISD::UNDEF) 1374 return N1; 1375 1376 return SDValue(); 1377} 1378 1379SDValue DAGCombiner::visitUDIV(SDNode *N) { 1380 SDValue N0 = N->getOperand(0); 1381 SDValue N1 = N->getOperand(1); 1382 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode()); 1383 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 1384 MVT VT = N->getValueType(0); 1385 1386 // fold vector ops 1387 if (VT.isVector()) { 1388 SDValue FoldedVOp = SimplifyVBinOp(N); 1389 if (FoldedVOp.getNode()) return FoldedVOp; 1390 } 1391 1392 // fold (udiv c1, c2) -> c1/c2 1393 if (N0C && N1C && !N1C->isNullValue()) 1394 return DAG.FoldConstantArithmetic(ISD::UDIV, VT, N0C, N1C); 1395 // fold (udiv x, (1 << c)) -> x >>u c 1396 if (N1C && N1C->getAPIntValue().isPowerOf2()) 1397 return DAG.getNode(ISD::SRL, VT, N0, 1398 DAG.getConstant(N1C->getAPIntValue().logBase2(), 1399 TLI.getShiftAmountTy())); 1400 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2 1401 if (N1.getOpcode() == ISD::SHL) { 1402 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1403 if (SHC->getAPIntValue().isPowerOf2()) { 1404 MVT ADDVT = N1.getOperand(1).getValueType(); 1405 SDValue Add = DAG.getNode(ISD::ADD, ADDVT, N1.getOperand(1), 1406 DAG.getConstant(SHC->getAPIntValue() 1407 .logBase2(), 1408 ADDVT)); 1409 AddToWorkList(Add.getNode()); 1410 return DAG.getNode(ISD::SRL, VT, N0, Add); 1411 } 1412 } 1413 } 1414 // fold (udiv x, c) -> alternate 1415 if (N1C && !N1C->isNullValue() && !TLI.isIntDivCheap()) { 1416 SDValue Op = BuildUDIV(N); 1417 if (Op.getNode()) return Op; 1418 } 1419 1420 // undef / X -> 0 1421 if (N0.getOpcode() == ISD::UNDEF) 1422 return DAG.getConstant(0, VT); 1423 // X / undef -> undef 1424 if (N1.getOpcode() == ISD::UNDEF) 1425 return N1; 1426 1427 return SDValue(); 1428} 1429 1430SDValue DAGCombiner::visitSREM(SDNode *N) { 1431 SDValue N0 = N->getOperand(0); 1432 SDValue N1 = N->getOperand(1); 1433 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1434 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1435 MVT VT = N->getValueType(0); 1436 1437 // fold (srem c1, c2) -> c1%c2 1438 if (N0C && N1C && !N1C->isNullValue()) 1439 return DAG.FoldConstantArithmetic(ISD::SREM, VT, N0C, N1C); 1440 // If we know the sign bits of both operands are zero, strength reduce to a 1441 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15 1442 if (!VT.isVector()) { 1443 if (DAG.SignBitIsZero(N1) && DAG.SignBitIsZero(N0)) 1444 return DAG.getNode(ISD::UREM, VT, N0, N1); 1445 } 1446 1447 // If X/C can be simplified by the division-by-constant logic, lower 1448 // X%C to the equivalent of X-X/C*C. 1449 if (N1C && !N1C->isNullValue()) { 1450 SDValue Div = DAG.getNode(ISD::SDIV, VT, N0, N1); 1451 AddToWorkList(Div.getNode()); 1452 SDValue OptimizedDiv = combine(Div.getNode()); 1453 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) { 1454 SDValue Mul = DAG.getNode(ISD::MUL, VT, OptimizedDiv, N1); 1455 SDValue Sub = DAG.getNode(ISD::SUB, VT, N0, Mul); 1456 AddToWorkList(Mul.getNode()); 1457 return Sub; 1458 } 1459 } 1460 1461 // undef % X -> 0 1462 if (N0.getOpcode() == ISD::UNDEF) 1463 return DAG.getConstant(0, VT); 1464 // X % undef -> undef 1465 if (N1.getOpcode() == ISD::UNDEF) 1466 return N1; 1467 1468 return SDValue(); 1469} 1470 1471SDValue DAGCombiner::visitUREM(SDNode *N) { 1472 SDValue N0 = N->getOperand(0); 1473 SDValue N1 = N->getOperand(1); 1474 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1475 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1476 MVT VT = N->getValueType(0); 1477 1478 // fold (urem c1, c2) -> c1%c2 1479 if (N0C && N1C && !N1C->isNullValue()) 1480 return DAG.FoldConstantArithmetic(ISD::UREM, VT, N0C, N1C); 1481 // fold (urem x, pow2) -> (and x, pow2-1) 1482 if (N1C && !N1C->isNullValue() && N1C->getAPIntValue().isPowerOf2()) 1483 return DAG.getNode(ISD::AND, VT, N0, 1484 DAG.getConstant(N1C->getAPIntValue()-1,VT)); 1485 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1)) 1486 if (N1.getOpcode() == ISD::SHL) { 1487 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1488 if (SHC->getAPIntValue().isPowerOf2()) { 1489 SDValue Add = 1490 DAG.getNode(ISD::ADD, VT, N1, 1491 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), 1492 VT)); 1493 AddToWorkList(Add.getNode()); 1494 return DAG.getNode(ISD::AND, VT, N0, Add); 1495 } 1496 } 1497 } 1498 1499 // If X/C can be simplified by the division-by-constant logic, lower 1500 // X%C to the equivalent of X-X/C*C. 1501 if (N1C && !N1C->isNullValue()) { 1502 SDValue Div = DAG.getNode(ISD::UDIV, VT, N0, N1); 1503 AddToWorkList(Div.getNode()); 1504 SDValue OptimizedDiv = combine(Div.getNode()); 1505 if (OptimizedDiv.getNode() && OptimizedDiv.getNode() != Div.getNode()) { 1506 SDValue Mul = DAG.getNode(ISD::MUL, VT, OptimizedDiv, N1); 1507 SDValue Sub = DAG.getNode(ISD::SUB, VT, N0, Mul); 1508 AddToWorkList(Mul.getNode()); 1509 return Sub; 1510 } 1511 } 1512 1513 // undef % X -> 0 1514 if (N0.getOpcode() == ISD::UNDEF) 1515 return DAG.getConstant(0, VT); 1516 // X % undef -> undef 1517 if (N1.getOpcode() == ISD::UNDEF) 1518 return N1; 1519 1520 return SDValue(); 1521} 1522 1523SDValue DAGCombiner::visitMULHS(SDNode *N) { 1524 SDValue N0 = N->getOperand(0); 1525 SDValue N1 = N->getOperand(1); 1526 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1527 MVT VT = N->getValueType(0); 1528 1529 // fold (mulhs x, 0) -> 0 1530 if (N1C && N1C->isNullValue()) 1531 return N1; 1532 // fold (mulhs x, 1) -> (sra x, size(x)-1) 1533 if (N1C && N1C->getAPIntValue() == 1) 1534 return DAG.getNode(ISD::SRA, N0.getValueType(), N0, 1535 DAG.getConstant(N0.getValueType().getSizeInBits()-1, 1536 TLI.getShiftAmountTy())); 1537 // fold (mulhs x, undef) -> 0 1538 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1539 return DAG.getConstant(0, VT); 1540 1541 return SDValue(); 1542} 1543 1544SDValue DAGCombiner::visitMULHU(SDNode *N) { 1545 SDValue N0 = N->getOperand(0); 1546 SDValue N1 = N->getOperand(1); 1547 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1548 MVT VT = N->getValueType(0); 1549 1550 // fold (mulhu x, 0) -> 0 1551 if (N1C && N1C->isNullValue()) 1552 return N1; 1553 // fold (mulhu x, 1) -> 0 1554 if (N1C && N1C->getAPIntValue() == 1) 1555 return DAG.getConstant(0, N0.getValueType()); 1556 // fold (mulhu x, undef) -> 0 1557 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1558 return DAG.getConstant(0, VT); 1559 1560 return SDValue(); 1561} 1562 1563/// SimplifyNodeWithTwoResults - Perform optimizations common to nodes that 1564/// compute two values. LoOp and HiOp give the opcodes for the two computations 1565/// that are being performed. Return true if a simplification was made. 1566/// 1567SDValue DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 1568 unsigned HiOp) { 1569 // If the high half is not needed, just compute the low half. 1570 bool HiExists = N->hasAnyUseOfValue(1); 1571 if (!HiExists && 1572 (!LegalOperations || 1573 TLI.isOperationLegal(LoOp, N->getValueType(0)))) { 1574 SDValue Res = DAG.getNode(LoOp, N->getValueType(0), N->op_begin(), 1575 N->getNumOperands()); 1576 return CombineTo(N, Res, Res); 1577 } 1578 1579 // If the low half is not needed, just compute the high half. 1580 bool LoExists = N->hasAnyUseOfValue(0); 1581 if (!LoExists && 1582 (!LegalOperations || 1583 TLI.isOperationLegal(HiOp, N->getValueType(1)))) { 1584 SDValue Res = DAG.getNode(HiOp, N->getValueType(1), N->op_begin(), 1585 N->getNumOperands()); 1586 return CombineTo(N, Res, Res); 1587 } 1588 1589 // If both halves are used, return as it is. 1590 if (LoExists && HiExists) 1591 return SDValue(); 1592 1593 // If the two computed results can be simplified separately, separate them. 1594 if (LoExists) { 1595 SDValue Lo = DAG.getNode(LoOp, N->getValueType(0), 1596 N->op_begin(), N->getNumOperands()); 1597 AddToWorkList(Lo.getNode()); 1598 SDValue LoOpt = combine(Lo.getNode()); 1599 if (LoOpt.getNode() && LoOpt.getNode() != Lo.getNode() && 1600 (!LegalOperations || 1601 TLI.isOperationLegal(LoOpt.getOpcode(), LoOpt.getValueType()))) 1602 return CombineTo(N, LoOpt, LoOpt); 1603 } 1604 1605 if (HiExists) { 1606 SDValue Hi = DAG.getNode(HiOp, N->getValueType(1), 1607 N->op_begin(), N->getNumOperands()); 1608 AddToWorkList(Hi.getNode()); 1609 SDValue HiOpt = combine(Hi.getNode()); 1610 if (HiOpt.getNode() && HiOpt != Hi && 1611 (!LegalOperations || 1612 TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType()))) 1613 return CombineTo(N, HiOpt, HiOpt); 1614 } 1615 return SDValue(); 1616} 1617 1618SDValue DAGCombiner::visitSMUL_LOHI(SDNode *N) { 1619 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS); 1620 if (Res.getNode()) return Res; 1621 1622 return SDValue(); 1623} 1624 1625SDValue DAGCombiner::visitUMUL_LOHI(SDNode *N) { 1626 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU); 1627 if (Res.getNode()) return Res; 1628 1629 return SDValue(); 1630} 1631 1632SDValue DAGCombiner::visitSDIVREM(SDNode *N) { 1633 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM); 1634 if (Res.getNode()) return Res; 1635 1636 return SDValue(); 1637} 1638 1639SDValue DAGCombiner::visitUDIVREM(SDNode *N) { 1640 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM); 1641 if (Res.getNode()) return Res; 1642 1643 return SDValue(); 1644} 1645 1646/// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with 1647/// two operands of the same opcode, try to simplify it. 1648SDValue DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) { 1649 SDValue N0 = N->getOperand(0), N1 = N->getOperand(1); 1650 MVT VT = N0.getValueType(); 1651 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!"); 1652 1653 // For each of OP in AND/OR/XOR: 1654 // fold (OP (zext x), (zext y)) -> (zext (OP x, y)) 1655 // fold (OP (sext x), (sext y)) -> (sext (OP x, y)) 1656 // fold (OP (aext x), (aext y)) -> (aext (OP x, y)) 1657 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y)) 1658 if ((N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND|| 1659 N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::TRUNCATE) && 1660 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) { 1661 SDValue ORNode = DAG.getNode(N->getOpcode(), 1662 N0.getOperand(0).getValueType(), 1663 N0.getOperand(0), N1.getOperand(0)); 1664 AddToWorkList(ORNode.getNode()); 1665 return DAG.getNode(N0.getOpcode(), VT, ORNode); 1666 } 1667 1668 // For each of OP in SHL/SRL/SRA/AND... 1669 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z) 1670 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z) 1671 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z) 1672 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL || 1673 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) && 1674 N0.getOperand(1) == N1.getOperand(1)) { 1675 SDValue ORNode = DAG.getNode(N->getOpcode(), 1676 N0.getOperand(0).getValueType(), 1677 N0.getOperand(0), N1.getOperand(0)); 1678 AddToWorkList(ORNode.getNode()); 1679 return DAG.getNode(N0.getOpcode(), VT, ORNode, N0.getOperand(1)); 1680 } 1681 1682 return SDValue(); 1683} 1684 1685SDValue DAGCombiner::visitAND(SDNode *N) { 1686 SDValue N0 = N->getOperand(0); 1687 SDValue N1 = N->getOperand(1); 1688 SDValue LL, LR, RL, RR, CC0, CC1; 1689 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1690 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1691 MVT VT = N1.getValueType(); 1692 unsigned BitWidth = VT.getSizeInBits(); 1693 1694 // fold vector ops 1695 if (VT.isVector()) { 1696 SDValue FoldedVOp = SimplifyVBinOp(N); 1697 if (FoldedVOp.getNode()) return FoldedVOp; 1698 } 1699 1700 // fold (and x, undef) -> 0 1701 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1702 return DAG.getConstant(0, VT); 1703 // fold (and c1, c2) -> c1&c2 1704 if (N0C && N1C) 1705 return DAG.FoldConstantArithmetic(ISD::AND, VT, N0C, N1C); 1706 // canonicalize constant to RHS 1707 if (N0C && !N1C) 1708 return DAG.getNode(ISD::AND, VT, N1, N0); 1709 // fold (and x, -1) -> x 1710 if (N1C && N1C->isAllOnesValue()) 1711 return N0; 1712 // if (and x, c) is known to be zero, return 0 1713 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0), 1714 APInt::getAllOnesValue(BitWidth))) 1715 return DAG.getConstant(0, VT); 1716 // reassociate and 1717 SDValue RAND = ReassociateOps(ISD::AND, N0, N1); 1718 if (RAND.getNode() != 0) 1719 return RAND; 1720 // fold (and (or x, 0xFFFF), 0xFF) -> 0xFF 1721 if (N1C && N0.getOpcode() == ISD::OR) 1722 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 1723 if ((ORI->getAPIntValue() & N1C->getAPIntValue()) == N1C->getAPIntValue()) 1724 return N1; 1725 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits. 1726 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 1727 SDValue N0Op0 = N0.getOperand(0); 1728 APInt Mask = ~N1C->getAPIntValue(); 1729 Mask.trunc(N0Op0.getValueSizeInBits()); 1730 if (DAG.MaskedValueIsZero(N0Op0, Mask)) { 1731 SDValue Zext = DAG.getNode(ISD::ZERO_EXTEND, N0.getValueType(), 1732 N0Op0); 1733 1734 // Replace uses of the AND with uses of the Zero extend node. 1735 CombineTo(N, Zext); 1736 1737 // We actually want to replace all uses of the any_extend with the 1738 // zero_extend, to avoid duplicating things. This will later cause this 1739 // AND to be folded. 1740 CombineTo(N0.getNode(), Zext); 1741 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1742 } 1743 } 1744 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y)) 1745 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 1746 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 1747 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 1748 1749 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 1750 LL.getValueType().isInteger()) { 1751 // fold (X == 0) & (Y == 0) -> (X|Y == 0) 1752 if (cast<ConstantSDNode>(LR)->isNullValue() && Op1 == ISD::SETEQ) { 1753 SDValue ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 1754 AddToWorkList(ORNode.getNode()); 1755 return DAG.getSetCC(VT, ORNode, LR, Op1); 1756 } 1757 // fold (X == -1) & (Y == -1) -> (X&Y == -1) 1758 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) { 1759 SDValue ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL); 1760 AddToWorkList(ANDNode.getNode()); 1761 return DAG.getSetCC(VT, ANDNode, LR, Op1); 1762 } 1763 // fold (X > -1) & (Y > -1) -> (X|Y > -1) 1764 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) { 1765 SDValue ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 1766 AddToWorkList(ORNode.getNode()); 1767 return DAG.getSetCC(VT, ORNode, LR, Op1); 1768 } 1769 } 1770 // canonicalize equivalent to ll == rl 1771 if (LL == RR && LR == RL) { 1772 Op1 = ISD::getSetCCSwappedOperands(Op1); 1773 std::swap(RL, RR); 1774 } 1775 if (LL == RL && LR == RR) { 1776 bool isInteger = LL.getValueType().isInteger(); 1777 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger); 1778 if (Result != ISD::SETCC_INVALID && 1779 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType()))) 1780 return DAG.getSetCC(N0.getValueType(), LL, LR, Result); 1781 } 1782 } 1783 1784 // Simplify: and (op x...), (op y...) -> (op (and x, y)) 1785 if (N0.getOpcode() == N1.getOpcode()) { 1786 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 1787 if (Tmp.getNode()) return Tmp; 1788 } 1789 1790 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1) 1791 // fold (and (sra)) -> (and (srl)) when possible. 1792 if (!VT.isVector() && 1793 SimplifyDemandedBits(SDValue(N, 0))) 1794 return SDValue(N, 0); 1795 // fold (zext_inreg (extload x)) -> (zextload x) 1796 if (ISD::isEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode())) { 1797 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1798 MVT EVT = LN0->getMemoryVT(); 1799 // If we zero all the possible extended bits, then we can turn this into 1800 // a zextload if we are running before legalize or the operation is legal. 1801 unsigned BitWidth = N1.getValueSizeInBits(); 1802 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 1803 BitWidth - EVT.getSizeInBits())) && 1804 ((!LegalOperations && !LN0->isVolatile()) || 1805 TLI.isLoadExtLegal(ISD::ZEXTLOAD, EVT))) { 1806 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 1807 LN0->getBasePtr(), LN0->getSrcValue(), 1808 LN0->getSrcValueOffset(), EVT, 1809 LN0->isVolatile(), LN0->getAlignment()); 1810 AddToWorkList(N); 1811 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 1812 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1813 } 1814 } 1815 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use 1816 if (ISD::isSEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 1817 N0.hasOneUse()) { 1818 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1819 MVT EVT = LN0->getMemoryVT(); 1820 // If we zero all the possible extended bits, then we can turn this into 1821 // a zextload if we are running before legalize or the operation is legal. 1822 unsigned BitWidth = N1.getValueSizeInBits(); 1823 if (DAG.MaskedValueIsZero(N1, APInt::getHighBitsSet(BitWidth, 1824 BitWidth - EVT.getSizeInBits())) && 1825 ((!LegalOperations && !LN0->isVolatile()) || 1826 TLI.isLoadExtLegal(ISD::ZEXTLOAD, EVT))) { 1827 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 1828 LN0->getBasePtr(), LN0->getSrcValue(), 1829 LN0->getSrcValueOffset(), EVT, 1830 LN0->isVolatile(), LN0->getAlignment()); 1831 AddToWorkList(N); 1832 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 1833 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1834 } 1835 } 1836 1837 // fold (and (load x), 255) -> (zextload x, i8) 1838 // fold (and (extload x, i16), 255) -> (zextload x, i8) 1839 if (N1C && N0.getOpcode() == ISD::LOAD) { 1840 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1841 if (LN0->getExtensionType() != ISD::SEXTLOAD && 1842 LN0->isUnindexed() && N0.hasOneUse() && 1843 // Do not change the width of a volatile load. 1844 !LN0->isVolatile()) { 1845 MVT EVT = MVT::Other; 1846 uint32_t ActiveBits = N1C->getAPIntValue().getActiveBits(); 1847 if (ActiveBits > 0 && APIntOps::isMask(ActiveBits, N1C->getAPIntValue())) 1848 EVT = MVT::getIntegerVT(ActiveBits); 1849 1850 MVT LoadedVT = LN0->getMemoryVT(); 1851 // Do not generate loads of non-round integer types since these can 1852 // be expensive (and would be wrong if the type is not byte sized). 1853 if (EVT != MVT::Other && LoadedVT.bitsGT(EVT) && EVT.isRound() && 1854 (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, EVT))) { 1855 MVT PtrType = N0.getOperand(1).getValueType(); 1856 // For big endian targets, we need to add an offset to the pointer to 1857 // load the correct bytes. For little endian systems, we merely need to 1858 // read fewer bytes from the same pointer. 1859 unsigned LVTStoreBytes = LoadedVT.getStoreSizeInBits()/8; 1860 unsigned EVTStoreBytes = EVT.getStoreSizeInBits()/8; 1861 unsigned PtrOff = LVTStoreBytes - EVTStoreBytes; 1862 unsigned Alignment = LN0->getAlignment(); 1863 SDValue NewPtr = LN0->getBasePtr(); 1864 if (TLI.isBigEndian()) { 1865 NewPtr = DAG.getNode(ISD::ADD, PtrType, NewPtr, 1866 DAG.getConstant(PtrOff, PtrType)); 1867 Alignment = MinAlign(Alignment, PtrOff); 1868 } 1869 AddToWorkList(NewPtr.getNode()); 1870 SDValue Load = 1871 DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), NewPtr, 1872 LN0->getSrcValue(), LN0->getSrcValueOffset(), EVT, 1873 LN0->isVolatile(), Alignment); 1874 AddToWorkList(N); 1875 CombineTo(N0.getNode(), Load, Load.getValue(1)); 1876 return SDValue(N, 0); // Return N so it doesn't get rechecked! 1877 } 1878 } 1879 } 1880 1881 return SDValue(); 1882} 1883 1884SDValue DAGCombiner::visitOR(SDNode *N) { 1885 SDValue N0 = N->getOperand(0); 1886 SDValue N1 = N->getOperand(1); 1887 SDValue LL, LR, RL, RR, CC0, CC1; 1888 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1889 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1890 MVT VT = N1.getValueType(); 1891 1892 // fold vector ops 1893 if (VT.isVector()) { 1894 SDValue FoldedVOp = SimplifyVBinOp(N); 1895 if (FoldedVOp.getNode()) return FoldedVOp; 1896 } 1897 1898 // fold (or x, undef) -> -1 1899 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1900 return DAG.getConstant(~0ULL, VT); 1901 // fold (or c1, c2) -> c1|c2 1902 if (N0C && N1C) 1903 return DAG.FoldConstantArithmetic(ISD::OR, VT, N0C, N1C); 1904 // canonicalize constant to RHS 1905 if (N0C && !N1C) 1906 return DAG.getNode(ISD::OR, VT, N1, N0); 1907 // fold (or x, 0) -> x 1908 if (N1C && N1C->isNullValue()) 1909 return N0; 1910 // fold (or x, -1) -> -1 1911 if (N1C && N1C->isAllOnesValue()) 1912 return N1; 1913 // fold (or x, c) -> c iff (x & ~c) == 0 1914 if (N1C && DAG.MaskedValueIsZero(N0, ~N1C->getAPIntValue())) 1915 return N1; 1916 // reassociate or 1917 SDValue ROR = ReassociateOps(ISD::OR, N0, N1); 1918 if (ROR.getNode() != 0) 1919 return ROR; 1920 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2) 1921 if (N1C && N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() && 1922 isa<ConstantSDNode>(N0.getOperand(1))) { 1923 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1)); 1924 return DAG.getNode(ISD::AND, VT, DAG.getNode(ISD::OR, VT, N0.getOperand(0), 1925 N1), 1926 DAG.getConstant(N1C->getAPIntValue() | 1927 C1->getAPIntValue(), VT)); 1928 } 1929 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y)) 1930 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 1931 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 1932 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 1933 1934 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 1935 LL.getValueType().isInteger()) { 1936 // fold (X != 0) | (Y != 0) -> (X|Y != 0) 1937 // fold (X < 0) | (Y < 0) -> (X|Y < 0) 1938 if (cast<ConstantSDNode>(LR)->isNullValue() && 1939 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) { 1940 SDValue ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 1941 AddToWorkList(ORNode.getNode()); 1942 return DAG.getSetCC(VT, ORNode, LR, Op1); 1943 } 1944 // fold (X != -1) | (Y != -1) -> (X&Y != -1) 1945 // fold (X > -1) | (Y > -1) -> (X&Y > -1) 1946 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && 1947 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) { 1948 SDValue ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL); 1949 AddToWorkList(ANDNode.getNode()); 1950 return DAG.getSetCC(VT, ANDNode, LR, Op1); 1951 } 1952 } 1953 // canonicalize equivalent to ll == rl 1954 if (LL == RR && LR == RL) { 1955 Op1 = ISD::getSetCCSwappedOperands(Op1); 1956 std::swap(RL, RR); 1957 } 1958 if (LL == RL && LR == RR) { 1959 bool isInteger = LL.getValueType().isInteger(); 1960 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger); 1961 if (Result != ISD::SETCC_INVALID && 1962 (!LegalOperations || TLI.isCondCodeLegal(Result, LL.getValueType()))) 1963 return DAG.getSetCC(N0.getValueType(), LL, LR, Result); 1964 } 1965 } 1966 1967 // Simplify: or (op x...), (op y...) -> (op (or x, y)) 1968 if (N0.getOpcode() == N1.getOpcode()) { 1969 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 1970 if (Tmp.getNode()) return Tmp; 1971 } 1972 1973 // (X & C1) | (Y & C2) -> (X|Y) & C3 if possible. 1974 if (N0.getOpcode() == ISD::AND && 1975 N1.getOpcode() == ISD::AND && 1976 N0.getOperand(1).getOpcode() == ISD::Constant && 1977 N1.getOperand(1).getOpcode() == ISD::Constant && 1978 // Don't increase # computations. 1979 (N0.getNode()->hasOneUse() || N1.getNode()->hasOneUse())) { 1980 // We can only do this xform if we know that bits from X that are set in C2 1981 // but not in C1 are already zero. Likewise for Y. 1982 const APInt &LHSMask = 1983 cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 1984 const APInt &RHSMask = 1985 cast<ConstantSDNode>(N1.getOperand(1))->getAPIntValue(); 1986 1987 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) && 1988 DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) { 1989 SDValue X =DAG.getNode(ISD::OR, VT, N0.getOperand(0), N1.getOperand(0)); 1990 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(LHSMask|RHSMask, VT)); 1991 } 1992 } 1993 1994 1995 // See if this is some rotate idiom. 1996 if (SDNode *Rot = MatchRotate(N0, N1)) 1997 return SDValue(Rot, 0); 1998 1999 return SDValue(); 2000} 2001 2002 2003/// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present. 2004static bool MatchRotateHalf(SDValue Op, SDValue &Shift, SDValue &Mask) { 2005 if (Op.getOpcode() == ISD::AND) { 2006 if (isa<ConstantSDNode>(Op.getOperand(1))) { 2007 Mask = Op.getOperand(1); 2008 Op = Op.getOperand(0); 2009 } else { 2010 return false; 2011 } 2012 } 2013 2014 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) { 2015 Shift = Op; 2016 return true; 2017 } 2018 return false; 2019} 2020 2021 2022// MatchRotate - Handle an 'or' of two operands. If this is one of the many 2023// idioms for rotate, and if the target supports rotation instructions, generate 2024// a rot[lr]. 2025SDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS) { 2026 // Must be a legal type. Expanded 'n promoted things won't work with rotates. 2027 MVT VT = LHS.getValueType(); 2028 if (!TLI.isTypeLegal(VT)) return 0; 2029 2030 // The target must have at least one rotate flavor. 2031 bool HasROTL = TLI.isOperationLegal(ISD::ROTL, VT); 2032 bool HasROTR = TLI.isOperationLegal(ISD::ROTR, VT); 2033 if (!HasROTL && !HasROTR) return 0; 2034 2035 // Match "(X shl/srl V1) & V2" where V2 may not be present. 2036 SDValue LHSShift; // The shift. 2037 SDValue LHSMask; // AND value if any. 2038 if (!MatchRotateHalf(LHS, LHSShift, LHSMask)) 2039 return 0; // Not part of a rotate. 2040 2041 SDValue RHSShift; // The shift. 2042 SDValue RHSMask; // AND value if any. 2043 if (!MatchRotateHalf(RHS, RHSShift, RHSMask)) 2044 return 0; // Not part of a rotate. 2045 2046 if (LHSShift.getOperand(0) != RHSShift.getOperand(0)) 2047 return 0; // Not shifting the same value. 2048 2049 if (LHSShift.getOpcode() == RHSShift.getOpcode()) 2050 return 0; // Shifts must disagree. 2051 2052 // Canonicalize shl to left side in a shl/srl pair. 2053 if (RHSShift.getOpcode() == ISD::SHL) { 2054 std::swap(LHS, RHS); 2055 std::swap(LHSShift, RHSShift); 2056 std::swap(LHSMask , RHSMask ); 2057 } 2058 2059 unsigned OpSizeInBits = VT.getSizeInBits(); 2060 SDValue LHSShiftArg = LHSShift.getOperand(0); 2061 SDValue LHSShiftAmt = LHSShift.getOperand(1); 2062 SDValue RHSShiftAmt = RHSShift.getOperand(1); 2063 2064 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1) 2065 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2) 2066 if (LHSShiftAmt.getOpcode() == ISD::Constant && 2067 RHSShiftAmt.getOpcode() == ISD::Constant) { 2068 uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getZExtValue(); 2069 uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getZExtValue(); 2070 if ((LShVal + RShVal) != OpSizeInBits) 2071 return 0; 2072 2073 SDValue Rot; 2074 if (HasROTL) 2075 Rot = DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt); 2076 else 2077 Rot = DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt); 2078 2079 // If there is an AND of either shifted operand, apply it to the result. 2080 if (LHSMask.getNode() || RHSMask.getNode()) { 2081 APInt Mask = APInt::getAllOnesValue(OpSizeInBits); 2082 2083 if (LHSMask.getNode()) { 2084 APInt RHSBits = APInt::getLowBitsSet(OpSizeInBits, LShVal); 2085 Mask &= cast<ConstantSDNode>(LHSMask)->getAPIntValue() | RHSBits; 2086 } 2087 if (RHSMask.getNode()) { 2088 APInt LHSBits = APInt::getHighBitsSet(OpSizeInBits, RShVal); 2089 Mask &= cast<ConstantSDNode>(RHSMask)->getAPIntValue() | LHSBits; 2090 } 2091 2092 Rot = DAG.getNode(ISD::AND, VT, Rot, DAG.getConstant(Mask, VT)); 2093 } 2094 2095 return Rot.getNode(); 2096 } 2097 2098 // If there is a mask here, and we have a variable shift, we can't be sure 2099 // that we're masking out the right stuff. 2100 if (LHSMask.getNode() || RHSMask.getNode()) 2101 return 0; 2102 2103 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y) 2104 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y)) 2105 if (RHSShiftAmt.getOpcode() == ISD::SUB && 2106 LHSShiftAmt == RHSShiftAmt.getOperand(1)) { 2107 if (ConstantSDNode *SUBC = 2108 dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) { 2109 if (SUBC->getAPIntValue() == OpSizeInBits) { 2110 if (HasROTL) 2111 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).getNode(); 2112 else 2113 return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).getNode(); 2114 } 2115 } 2116 } 2117 2118 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y) 2119 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y)) 2120 if (LHSShiftAmt.getOpcode() == ISD::SUB && 2121 RHSShiftAmt == LHSShiftAmt.getOperand(1)) { 2122 if (ConstantSDNode *SUBC = 2123 dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) { 2124 if (SUBC->getAPIntValue() == OpSizeInBits) { 2125 if (HasROTR) 2126 return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).getNode(); 2127 else 2128 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).getNode(); 2129 } 2130 } 2131 } 2132 2133 // Look for sign/zext/any-extended or truncate cases: 2134 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 2135 || LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 2136 || LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND 2137 || LHSShiftAmt.getOpcode() == ISD::TRUNCATE) && 2138 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 2139 || RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 2140 || RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND 2141 || RHSShiftAmt.getOpcode() == ISD::TRUNCATE)) { 2142 SDValue LExtOp0 = LHSShiftAmt.getOperand(0); 2143 SDValue RExtOp0 = RHSShiftAmt.getOperand(0); 2144 if (RExtOp0.getOpcode() == ISD::SUB && 2145 RExtOp0.getOperand(1) == LExtOp0) { 2146 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 2147 // (rotl x, y) 2148 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 2149 // (rotr x, (sub 32, y)) 2150 if (ConstantSDNode *SUBC = 2151 dyn_cast<ConstantSDNode>(RExtOp0.getOperand(0))) { 2152 if (SUBC->getAPIntValue() == OpSizeInBits) { 2153 return DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, VT, LHSShiftArg, 2154 HasROTL ? LHSShiftAmt : RHSShiftAmt).getNode(); 2155 } 2156 } 2157 } else if (LExtOp0.getOpcode() == ISD::SUB && 2158 RExtOp0 == LExtOp0.getOperand(1)) { 2159 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) -> 2160 // (rotr x, y) 2161 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext y))) -> 2162 // (rotl x, (sub 32, y)) 2163 if (ConstantSDNode *SUBC = 2164 dyn_cast<ConstantSDNode>(LExtOp0.getOperand(0))) { 2165 if (SUBC->getAPIntValue() == OpSizeInBits) { 2166 return DAG.getNode(HasROTR ? ISD::ROTR : ISD::ROTL, VT, LHSShiftArg, 2167 HasROTR ? RHSShiftAmt : LHSShiftAmt).getNode(); 2168 } 2169 } 2170 } 2171 } 2172 2173 return 0; 2174} 2175 2176 2177SDValue DAGCombiner::visitXOR(SDNode *N) { 2178 SDValue N0 = N->getOperand(0); 2179 SDValue N1 = N->getOperand(1); 2180 SDValue LHS, RHS, CC; 2181 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2182 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2183 MVT VT = N0.getValueType(); 2184 2185 // fold vector ops 2186 if (VT.isVector()) { 2187 SDValue FoldedVOp = SimplifyVBinOp(N); 2188 if (FoldedVOp.getNode()) return FoldedVOp; 2189 } 2190 2191 // fold (xor undef, undef) -> 0. This is a common idiom (misuse). 2192 if (N0.getOpcode() == ISD::UNDEF && N1.getOpcode() == ISD::UNDEF) 2193 return DAG.getConstant(0, VT); 2194 // fold (xor x, undef) -> undef 2195 if (N0.getOpcode() == ISD::UNDEF) 2196 return N0; 2197 if (N1.getOpcode() == ISD::UNDEF) 2198 return N1; 2199 // fold (xor c1, c2) -> c1^c2 2200 if (N0C && N1C) 2201 return DAG.FoldConstantArithmetic(ISD::XOR, VT, N0C, N1C); 2202 // canonicalize constant to RHS 2203 if (N0C && !N1C) 2204 return DAG.getNode(ISD::XOR, VT, N1, N0); 2205 // fold (xor x, 0) -> x 2206 if (N1C && N1C->isNullValue()) 2207 return N0; 2208 // reassociate xor 2209 SDValue RXOR = ReassociateOps(ISD::XOR, N0, N1); 2210 if (RXOR.getNode() != 0) 2211 return RXOR; 2212 2213 // fold !(x cc y) -> (x !cc y) 2214 if (N1C && N1C->getAPIntValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) { 2215 bool isInt = LHS.getValueType().isInteger(); 2216 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(), 2217 isInt); 2218 2219 if (!LegalOperations || TLI.isCondCodeLegal(NotCC, LHS.getValueType())) { 2220 switch (N0.getOpcode()) { 2221 default: 2222 assert(0 && "Unhandled SetCC Equivalent!"); 2223 abort(); 2224 case ISD::SETCC: 2225 return DAG.getSetCC(VT, LHS, RHS, NotCC); 2226 case ISD::SELECT_CC: 2227 return DAG.getSelectCC(LHS, RHS, N0.getOperand(2), 2228 N0.getOperand(3), NotCC); 2229 } 2230 } 2231 } 2232 2233 // fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y))) 2234 if (N1C && N1C->getAPIntValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND && 2235 N0.getNode()->hasOneUse() && 2236 isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){ 2237 SDValue V = N0.getOperand(0); 2238 V = DAG.getNode(ISD::XOR, V.getValueType(), V, 2239 DAG.getConstant(1, V.getValueType())); 2240 AddToWorkList(V.getNode()); 2241 return DAG.getNode(ISD::ZERO_EXTEND, VT, V); 2242 } 2243 2244 // fold !(x or y) -> (!x and !y) iff x or y are setcc 2245 if (N1C && N1C->getAPIntValue() == 1 && VT == MVT::i1 && 2246 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 2247 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1); 2248 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) { 2249 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 2250 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS 2251 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS 2252 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode()); 2253 return DAG.getNode(NewOpcode, VT, LHS, RHS); 2254 } 2255 } 2256 // fold !(x or y) -> (!x and !y) iff x or y are constants 2257 if (N1C && N1C->isAllOnesValue() && 2258 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 2259 SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1); 2260 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) { 2261 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 2262 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS 2263 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS 2264 AddToWorkList(LHS.getNode()); AddToWorkList(RHS.getNode()); 2265 return DAG.getNode(NewOpcode, VT, LHS, RHS); 2266 } 2267 } 2268 // fold (xor (xor x, c1), c2) -> (xor x, c1^c2) 2269 if (N1C && N0.getOpcode() == ISD::XOR) { 2270 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0)); 2271 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2272 if (N00C) 2273 return DAG.getNode(ISD::XOR, VT, N0.getOperand(1), 2274 DAG.getConstant(N1C->getAPIntValue()^ 2275 N00C->getAPIntValue(), VT)); 2276 if (N01C) 2277 return DAG.getNode(ISD::XOR, VT, N0.getOperand(0), 2278 DAG.getConstant(N1C->getAPIntValue()^ 2279 N01C->getAPIntValue(), VT)); 2280 } 2281 // fold (xor x, x) -> 0 2282 if (N0 == N1) { 2283 if (!VT.isVector()) { 2284 return DAG.getConstant(0, VT); 2285 } else if (!LegalOperations || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)){ 2286 // Produce a vector of zeros. 2287 SDValue El = DAG.getConstant(0, VT.getVectorElementType()); 2288 std::vector<SDValue> Ops(VT.getVectorNumElements(), El); 2289 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 2290 } 2291 } 2292 2293 // Simplify: xor (op x...), (op y...) -> (op (xor x, y)) 2294 if (N0.getOpcode() == N1.getOpcode()) { 2295 SDValue Tmp = SimplifyBinOpWithSameOpcodeHands(N); 2296 if (Tmp.getNode()) return Tmp; 2297 } 2298 2299 // Simplify the expression using non-local knowledge. 2300 if (!VT.isVector() && 2301 SimplifyDemandedBits(SDValue(N, 0))) 2302 return SDValue(N, 0); 2303 2304 return SDValue(); 2305} 2306 2307/// visitShiftByConstant - Handle transforms common to the three shifts, when 2308/// the shift amount is a constant. 2309SDValue DAGCombiner::visitShiftByConstant(SDNode *N, unsigned Amt) { 2310 SDNode *LHS = N->getOperand(0).getNode(); 2311 if (!LHS->hasOneUse()) return SDValue(); 2312 2313 // We want to pull some binops through shifts, so that we have (and (shift)) 2314 // instead of (shift (and)), likewise for add, or, xor, etc. This sort of 2315 // thing happens with address calculations, so it's important to canonicalize 2316 // it. 2317 bool HighBitSet = false; // Can we transform this if the high bit is set? 2318 2319 switch (LHS->getOpcode()) { 2320 default: return SDValue(); 2321 case ISD::OR: 2322 case ISD::XOR: 2323 HighBitSet = false; // We can only transform sra if the high bit is clear. 2324 break; 2325 case ISD::AND: 2326 HighBitSet = true; // We can only transform sra if the high bit is set. 2327 break; 2328 case ISD::ADD: 2329 if (N->getOpcode() != ISD::SHL) 2330 return SDValue(); // only shl(add) not sr[al](add). 2331 HighBitSet = false; // We can only transform sra if the high bit is clear. 2332 break; 2333 } 2334 2335 // We require the RHS of the binop to be a constant as well. 2336 ConstantSDNode *BinOpCst = dyn_cast<ConstantSDNode>(LHS->getOperand(1)); 2337 if (!BinOpCst) return SDValue(); 2338 2339 2340 // FIXME: disable this for unless the input to the binop is a shift by a 2341 // constant. If it is not a shift, it pessimizes some common cases like: 2342 // 2343 //void foo(int *X, int i) { X[i & 1235] = 1; } 2344 //int bar(int *X, int i) { return X[i & 255]; } 2345 SDNode *BinOpLHSVal = LHS->getOperand(0).getNode(); 2346 if ((BinOpLHSVal->getOpcode() != ISD::SHL && 2347 BinOpLHSVal->getOpcode() != ISD::SRA && 2348 BinOpLHSVal->getOpcode() != ISD::SRL) || 2349 !isa<ConstantSDNode>(BinOpLHSVal->getOperand(1))) 2350 return SDValue(); 2351 2352 MVT VT = N->getValueType(0); 2353 2354 // If this is a signed shift right, and the high bit is modified 2355 // by the logical operation, do not perform the transformation. 2356 // The highBitSet boolean indicates the value of the high bit of 2357 // the constant which would cause it to be modified for this 2358 // operation. 2359 if (N->getOpcode() == ISD::SRA) { 2360 bool BinOpRHSSignSet = BinOpCst->getAPIntValue().isNegative(); 2361 if (BinOpRHSSignSet != HighBitSet) 2362 return SDValue(); 2363 } 2364 2365 // Fold the constants, shifting the binop RHS by the shift amount. 2366 SDValue NewRHS = DAG.getNode(N->getOpcode(), N->getValueType(0), 2367 LHS->getOperand(1), N->getOperand(1)); 2368 2369 // Create the new shift. 2370 SDValue NewShift = DAG.getNode(N->getOpcode(), VT, LHS->getOperand(0), 2371 N->getOperand(1)); 2372 2373 // Create the new binop. 2374 return DAG.getNode(LHS->getOpcode(), VT, NewShift, NewRHS); 2375} 2376 2377 2378SDValue DAGCombiner::visitSHL(SDNode *N) { 2379 SDValue N0 = N->getOperand(0); 2380 SDValue N1 = N->getOperand(1); 2381 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2382 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2383 MVT VT = N0.getValueType(); 2384 unsigned OpSizeInBits = VT.getSizeInBits(); 2385 2386 // fold (shl c1, c2) -> c1<<c2 2387 if (N0C && N1C) 2388 return DAG.FoldConstantArithmetic(ISD::SHL, VT, N0C, N1C); 2389 // fold (shl 0, x) -> 0 2390 if (N0C && N0C->isNullValue()) 2391 return N0; 2392 // fold (shl x, c >= size(x)) -> undef 2393 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 2394 return DAG.getNode(ISD::UNDEF, VT); 2395 // fold (shl x, 0) -> x 2396 if (N1C && N1C->isNullValue()) 2397 return N0; 2398 // if (shl x, c) is known to be zero, return 0 2399 if (DAG.MaskedValueIsZero(SDValue(N, 0), 2400 APInt::getAllOnesValue(VT.getSizeInBits()))) 2401 return DAG.getConstant(0, VT); 2402 // fold (shl x, (trunc (and y, c))) -> (shl x, (and (trunc y), c)) 2403 // iff (trunc c) == c 2404 if (N1.getOpcode() == ISD::TRUNCATE && 2405 N1.getOperand(0).getOpcode() == ISD::AND && 2406 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 2407 SDValue N101 = N1.getOperand(0).getOperand(1); 2408 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 2409 MVT TruncVT = N1.getValueType(); 2410 SDValue N100 = N1.getOperand(0).getOperand(0); 2411 return DAG.getNode(ISD::SHL, VT, N0, 2412 DAG.getNode(ISD::AND, TruncVT, 2413 DAG.getNode(ISD::TRUNCATE, TruncVT, N100), 2414 DAG.getConstant(N101C->getZExtValue(), 2415 TruncVT))); 2416 } 2417 } 2418 2419 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 2420 return SDValue(N, 0); 2421 // fold (shl (shl x, c1), c2) -> 0 or (shl x, c1+c2) 2422 if (N1C && N0.getOpcode() == ISD::SHL && 2423 N0.getOperand(1).getOpcode() == ISD::Constant) { 2424 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 2425 uint64_t c2 = N1C->getZExtValue(); 2426 if (c1 + c2 > OpSizeInBits) 2427 return DAG.getConstant(0, VT); 2428 return DAG.getNode(ISD::SHL, VT, N0.getOperand(0), 2429 DAG.getConstant(c1 + c2, N1.getValueType())); 2430 } 2431 // fold (shl (srl x, c1), c2) -> (shl (and x, -1 << c1), c2-c1) or 2432 // (srl (and x, -1 << c1), c1-c2) 2433 if (N1C && N0.getOpcode() == ISD::SRL && 2434 N0.getOperand(1).getOpcode() == ISD::Constant) { 2435 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 2436 uint64_t c2 = N1C->getZExtValue(); 2437 SDValue Mask = DAG.getNode(ISD::AND, VT, N0.getOperand(0), 2438 DAG.getConstant(~0ULL << c1, VT)); 2439 if (c2 > c1) 2440 return DAG.getNode(ISD::SHL, VT, Mask, 2441 DAG.getConstant(c2-c1, N1.getValueType())); 2442 else 2443 return DAG.getNode(ISD::SRL, VT, Mask, 2444 DAG.getConstant(c1-c2, N1.getValueType())); 2445 } 2446 // fold (shl (sra x, c1), c1) -> (and x, -1 << c1) 2447 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) 2448 return DAG.getNode(ISD::AND, VT, N0.getOperand(0), 2449 DAG.getConstant(~0ULL << N1C->getZExtValue(), VT)); 2450 2451 return N1C ? visitShiftByConstant(N, N1C->getZExtValue()) : SDValue(); 2452} 2453 2454SDValue DAGCombiner::visitSRA(SDNode *N) { 2455 SDValue N0 = N->getOperand(0); 2456 SDValue N1 = N->getOperand(1); 2457 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2458 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2459 MVT VT = N0.getValueType(); 2460 2461 // fold (sra c1, c2) -> c1>>c2 2462 if (N0C && N1C) 2463 return DAG.FoldConstantArithmetic(ISD::SRA, VT, N0C, N1C); 2464 // fold (sra 0, x) -> 0 2465 if (N0C && N0C->isNullValue()) 2466 return N0; 2467 // fold (sra -1, x) -> -1 2468 if (N0C && N0C->isAllOnesValue()) 2469 return N0; 2470 // fold (sra x, c >= size(x)) -> undef 2471 if (N1C && N1C->getZExtValue() >= VT.getSizeInBits()) 2472 return DAG.getNode(ISD::UNDEF, VT); 2473 // fold (sra x, 0) -> x 2474 if (N1C && N1C->isNullValue()) 2475 return N0; 2476 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports 2477 // sext_inreg. 2478 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) { 2479 unsigned LowBits = VT.getSizeInBits() - (unsigned)N1C->getZExtValue(); 2480 MVT EVT = MVT::getIntegerVT(LowBits); 2481 if ((!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, EVT))) 2482 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), 2483 DAG.getValueType(EVT)); 2484 } 2485 2486 // fold (sra (sra x, c1), c2) -> (sra x, c1+c2) 2487 if (N1C && N0.getOpcode() == ISD::SRA) { 2488 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 2489 unsigned Sum = N1C->getZExtValue() + C1->getZExtValue(); 2490 if (Sum >= VT.getSizeInBits()) Sum = VT.getSizeInBits()-1; 2491 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0), 2492 DAG.getConstant(Sum, N1C->getValueType(0))); 2493 } 2494 } 2495 2496 // fold sra (shl X, m), result_size - n 2497 // -> (sign_extend (trunc (shl X, result_size - n - m))) for 2498 // result_size - n != m. 2499 // If truncate is free for the target sext(shl) is likely to result in better 2500 // code. 2501 if (N0.getOpcode() == ISD::SHL) { 2502 // Get the two constanst of the shifts, CN0 = m, CN = n. 2503 const ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2504 if (N01C && N1C) { 2505 // Determine what the truncate's result bitsize and type would be. 2506 unsigned VTValSize = VT.getSizeInBits(); 2507 MVT TruncVT = 2508 MVT::getIntegerVT(VTValSize - N1C->getZExtValue()); 2509 // Determine the residual right-shift amount. 2510 unsigned ShiftAmt = N1C->getZExtValue() - N01C->getZExtValue(); 2511 2512 // If the shift is not a no-op (in which case this should be just a sign 2513 // extend already), the truncated to type is legal, sign_extend is legal 2514 // on that type, and the the truncate to that type is both legal and free, 2515 // perform the transform. 2516 if (ShiftAmt && 2517 TLI.isOperationLegal(ISD::SIGN_EXTEND, TruncVT) && 2518 TLI.isOperationLegal(ISD::TRUNCATE, VT) && 2519 TLI.isTruncateFree(VT, TruncVT)) { 2520 2521 SDValue Amt = DAG.getConstant(ShiftAmt, TLI.getShiftAmountTy()); 2522 SDValue Shift = DAG.getNode(ISD::SRL, VT, N0.getOperand(0), Amt); 2523 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, TruncVT, Shift); 2524 return DAG.getNode(ISD::SIGN_EXTEND, N->getValueType(0), Trunc); 2525 } 2526 } 2527 } 2528 2529 // fold (sra x, (trunc (and y, c))) -> (sra x, (and (trunc y), c)) 2530 // iff (trunc c) == c 2531 if (N1.getOpcode() == ISD::TRUNCATE && 2532 N1.getOperand(0).getOpcode() == ISD::AND && 2533 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 2534 SDValue N101 = N1.getOperand(0).getOperand(1); 2535 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 2536 MVT TruncVT = N1.getValueType(); 2537 SDValue N100 = N1.getOperand(0).getOperand(0); 2538 return DAG.getNode(ISD::SRA, VT, N0, 2539 DAG.getNode(ISD::AND, TruncVT, 2540 DAG.getNode(ISD::TRUNCATE, TruncVT, N100), 2541 DAG.getConstant(N101C->getZExtValue(), 2542 TruncVT))); 2543 } 2544 } 2545 2546 // Simplify, based on bits shifted out of the LHS. 2547 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 2548 return SDValue(N, 0); 2549 2550 2551 // If the sign bit is known to be zero, switch this to a SRL. 2552 if (DAG.SignBitIsZero(N0)) 2553 return DAG.getNode(ISD::SRL, VT, N0, N1); 2554 2555 return N1C ? visitShiftByConstant(N, N1C->getZExtValue()) : SDValue(); 2556} 2557 2558SDValue DAGCombiner::visitSRL(SDNode *N) { 2559 SDValue N0 = N->getOperand(0); 2560 SDValue N1 = N->getOperand(1); 2561 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2562 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2563 MVT VT = N0.getValueType(); 2564 unsigned OpSizeInBits = VT.getSizeInBits(); 2565 2566 // fold (srl c1, c2) -> c1 >>u c2 2567 if (N0C && N1C) 2568 return DAG.FoldConstantArithmetic(ISD::SRL, VT, N0C, N1C); 2569 // fold (srl 0, x) -> 0 2570 if (N0C && N0C->isNullValue()) 2571 return N0; 2572 // fold (srl x, c >= size(x)) -> undef 2573 if (N1C && N1C->getZExtValue() >= OpSizeInBits) 2574 return DAG.getNode(ISD::UNDEF, VT); 2575 // fold (srl x, 0) -> x 2576 if (N1C && N1C->isNullValue()) 2577 return N0; 2578 // if (srl x, c) is known to be zero, return 0 2579 if (N1C && DAG.MaskedValueIsZero(SDValue(N, 0), 2580 APInt::getAllOnesValue(OpSizeInBits))) 2581 return DAG.getConstant(0, VT); 2582 2583 // fold (srl (srl x, c1), c2) -> 0 or (srl x, c1+c2) 2584 if (N1C && N0.getOpcode() == ISD::SRL && 2585 N0.getOperand(1).getOpcode() == ISD::Constant) { 2586 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue(); 2587 uint64_t c2 = N1C->getZExtValue(); 2588 if (c1 + c2 > OpSizeInBits) 2589 return DAG.getConstant(0, VT); 2590 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0), 2591 DAG.getConstant(c1 + c2, N1.getValueType())); 2592 } 2593 2594 // fold (srl (anyextend x), c) -> (anyextend (srl x, c)) 2595 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 2596 // Shifting in all undef bits? 2597 MVT SmallVT = N0.getOperand(0).getValueType(); 2598 if (N1C->getZExtValue() >= SmallVT.getSizeInBits()) 2599 return DAG.getNode(ISD::UNDEF, VT); 2600 2601 SDValue SmallShift = DAG.getNode(ISD::SRL, SmallVT, N0.getOperand(0), N1); 2602 AddToWorkList(SmallShift.getNode()); 2603 return DAG.getNode(ISD::ANY_EXTEND, VT, SmallShift); 2604 } 2605 2606 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign 2607 // bit, which is unmodified by sra. 2608 if (N1C && N1C->getZExtValue()+1 == VT.getSizeInBits()) { 2609 if (N0.getOpcode() == ISD::SRA) 2610 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0), N1); 2611 } 2612 2613 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit). 2614 if (N1C && N0.getOpcode() == ISD::CTLZ && 2615 N1C->getAPIntValue() == Log2_32(VT.getSizeInBits())) { 2616 APInt KnownZero, KnownOne; 2617 APInt Mask = APInt::getAllOnesValue(VT.getSizeInBits()); 2618 DAG.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne); 2619 2620 // If any of the input bits are KnownOne, then the input couldn't be all 2621 // zeros, thus the result of the srl will always be zero. 2622 if (KnownOne.getBoolValue()) return DAG.getConstant(0, VT); 2623 2624 // If all of the bits input the to ctlz node are known to be zero, then 2625 // the result of the ctlz is "32" and the result of the shift is one. 2626 APInt UnknownBits = ~KnownZero & Mask; 2627 if (UnknownBits == 0) return DAG.getConstant(1, VT); 2628 2629 // Otherwise, check to see if there is exactly one bit input to the ctlz. 2630 if ((UnknownBits & (UnknownBits-1)) == 0) { 2631 // Okay, we know that only that the single bit specified by UnknownBits 2632 // could be set on input to the CTLZ node. If this bit is set, the SRL 2633 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair 2634 // to an SRL,XOR pair, which is likely to simplify more. 2635 unsigned ShAmt = UnknownBits.countTrailingZeros(); 2636 SDValue Op = N0.getOperand(0); 2637 if (ShAmt) { 2638 Op = DAG.getNode(ISD::SRL, VT, Op, 2639 DAG.getConstant(ShAmt, TLI.getShiftAmountTy())); 2640 AddToWorkList(Op.getNode()); 2641 } 2642 return DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(1, VT)); 2643 } 2644 } 2645 2646 // fold (srl x, (trunc (and y, c))) -> (srl x, (and (trunc y), c)) 2647 // iff (trunc c) == c 2648 if (N1.getOpcode() == ISD::TRUNCATE && 2649 N1.getOperand(0).getOpcode() == ISD::AND && 2650 N1.hasOneUse() && N1.getOperand(0).hasOneUse()) { 2651 SDValue N101 = N1.getOperand(0).getOperand(1); 2652 if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) { 2653 MVT TruncVT = N1.getValueType(); 2654 SDValue N100 = N1.getOperand(0).getOperand(0); 2655 return DAG.getNode(ISD::SRL, VT, N0, 2656 DAG.getNode(ISD::AND, TruncVT, 2657 DAG.getNode(ISD::TRUNCATE, TruncVT, N100), 2658 DAG.getConstant(N101C->getZExtValue(), 2659 TruncVT))); 2660 } 2661 } 2662 2663 // fold operands of srl based on knowledge that the low bits are not 2664 // demanded. 2665 if (N1C && SimplifyDemandedBits(SDValue(N, 0))) 2666 return SDValue(N, 0); 2667 2668 return N1C ? visitShiftByConstant(N, N1C->getZExtValue()) : SDValue(); 2669} 2670 2671SDValue DAGCombiner::visitCTLZ(SDNode *N) { 2672 SDValue N0 = N->getOperand(0); 2673 MVT VT = N->getValueType(0); 2674 2675 // fold (ctlz c1) -> c2 2676 if (isa<ConstantSDNode>(N0)) 2677 return DAG.getNode(ISD::CTLZ, VT, N0); 2678 return SDValue(); 2679} 2680 2681SDValue DAGCombiner::visitCTTZ(SDNode *N) { 2682 SDValue N0 = N->getOperand(0); 2683 MVT VT = N->getValueType(0); 2684 2685 // fold (cttz c1) -> c2 2686 if (isa<ConstantSDNode>(N0)) 2687 return DAG.getNode(ISD::CTTZ, VT, N0); 2688 return SDValue(); 2689} 2690 2691SDValue DAGCombiner::visitCTPOP(SDNode *N) { 2692 SDValue N0 = N->getOperand(0); 2693 MVT VT = N->getValueType(0); 2694 2695 // fold (ctpop c1) -> c2 2696 if (isa<ConstantSDNode>(N0)) 2697 return DAG.getNode(ISD::CTPOP, VT, N0); 2698 return SDValue(); 2699} 2700 2701SDValue DAGCombiner::visitSELECT(SDNode *N) { 2702 SDValue N0 = N->getOperand(0); 2703 SDValue N1 = N->getOperand(1); 2704 SDValue N2 = N->getOperand(2); 2705 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2706 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2707 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2); 2708 MVT VT = N->getValueType(0); 2709 MVT VT0 = N0.getValueType(); 2710 2711 // fold select C, X, X -> X 2712 if (N1 == N2) 2713 return N1; 2714 // fold select true, X, Y -> X 2715 if (N0C && !N0C->isNullValue()) 2716 return N1; 2717 // fold select false, X, Y -> Y 2718 if (N0C && N0C->isNullValue()) 2719 return N2; 2720 // fold select C, 1, X -> C | X 2721 if (VT == MVT::i1 && N1C && N1C->getAPIntValue() == 1) 2722 return DAG.getNode(ISD::OR, VT, N0, N2); 2723 // fold select C, 0, 1 -> ~C 2724 if (VT.isInteger() && VT0.isInteger() && 2725 N1C && N2C && N1C->isNullValue() && N2C->getAPIntValue() == 1) { 2726 SDValue XORNode = DAG.getNode(ISD::XOR, VT0, N0, DAG.getConstant(1, VT0)); 2727 if (VT == VT0) 2728 return XORNode; 2729 AddToWorkList(XORNode.getNode()); 2730 if (VT.bitsGT(VT0)) 2731 return DAG.getNode(ISD::ZERO_EXTEND, VT, XORNode); 2732 return DAG.getNode(ISD::TRUNCATE, VT, XORNode); 2733 } 2734 // fold select C, 0, X -> ~C & X 2735 if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) { 2736 SDValue XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT)); 2737 AddToWorkList(XORNode.getNode()); 2738 return DAG.getNode(ISD::AND, VT, XORNode, N2); 2739 } 2740 // fold select C, X, 1 -> ~C | X 2741 if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getAPIntValue() == 1) { 2742 SDValue XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT)); 2743 AddToWorkList(XORNode.getNode()); 2744 return DAG.getNode(ISD::OR, VT, XORNode, N1); 2745 } 2746 // fold select C, X, 0 -> C & X 2747 // FIXME: this should check for C type == X type, not i1? 2748 if (VT == MVT::i1 && N2C && N2C->isNullValue()) 2749 return DAG.getNode(ISD::AND, VT, N0, N1); 2750 // fold X ? X : Y --> X ? 1 : Y --> X | Y 2751 if (VT == MVT::i1 && N0 == N1) 2752 return DAG.getNode(ISD::OR, VT, N0, N2); 2753 // fold X ? Y : X --> X ? Y : 0 --> X & Y 2754 if (VT == MVT::i1 && N0 == N2) 2755 return DAG.getNode(ISD::AND, VT, N0, N1); 2756 2757 // If we can fold this based on the true/false value, do so. 2758 if (SimplifySelectOps(N, N1, N2)) 2759 return SDValue(N, 0); // Don't revisit N. 2760 2761 // fold selects based on a setcc into other things, such as min/max/abs 2762 if (N0.getOpcode() == ISD::SETCC) { 2763 // FIXME: 2764 // Check against MVT::Other for SELECT_CC, which is a workaround for targets 2765 // having to say they don't support SELECT_CC on every type the DAG knows 2766 // about, since there is no way to mark an opcode illegal at all value types 2767 if (TLI.isOperationLegal(ISD::SELECT_CC, MVT::Other)) 2768 return DAG.getNode(ISD::SELECT_CC, VT, N0.getOperand(0), N0.getOperand(1), 2769 N1, N2, N0.getOperand(2)); 2770 else 2771 return SimplifySelect(N0, N1, N2); 2772 } 2773 return SDValue(); 2774} 2775 2776SDValue DAGCombiner::visitSELECT_CC(SDNode *N) { 2777 SDValue N0 = N->getOperand(0); 2778 SDValue N1 = N->getOperand(1); 2779 SDValue N2 = N->getOperand(2); 2780 SDValue N3 = N->getOperand(3); 2781 SDValue N4 = N->getOperand(4); 2782 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get(); 2783 2784 // fold select_cc lhs, rhs, x, x, cc -> x 2785 if (N2 == N3) 2786 return N2; 2787 2788 // Determine if the condition we're dealing with is constant 2789 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0), N0, N1, CC, false); 2790 if (SCC.getNode()) AddToWorkList(SCC.getNode()); 2791 2792 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode())) { 2793 if (!SCCC->isNullValue()) 2794 return N2; // cond always true -> true val 2795 else 2796 return N3; // cond always false -> false val 2797 } 2798 2799 // Fold to a simpler select_cc 2800 if (SCC.getNode() && SCC.getOpcode() == ISD::SETCC) 2801 return DAG.getNode(ISD::SELECT_CC, N2.getValueType(), 2802 SCC.getOperand(0), SCC.getOperand(1), N2, N3, 2803 SCC.getOperand(2)); 2804 2805 // If we can fold this based on the true/false value, do so. 2806 if (SimplifySelectOps(N, N2, N3)) 2807 return SDValue(N, 0); // Don't revisit N. 2808 2809 // fold select_cc into other things, such as min/max/abs 2810 return SimplifySelectCC(N0, N1, N2, N3, CC); 2811} 2812 2813SDValue DAGCombiner::visitSETCC(SDNode *N) { 2814 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1), 2815 cast<CondCodeSDNode>(N->getOperand(2))->get()); 2816} 2817 2818// ExtendUsesToFormExtLoad - Trying to extend uses of a load to enable this: 2819// "fold ({s|z}ext (load x)) -> ({s|z}ext (truncate ({s|z}extload x)))" 2820// transformation. Returns true if extension are possible and the above 2821// mentioned transformation is profitable. 2822static bool ExtendUsesToFormExtLoad(SDNode *N, SDValue N0, 2823 unsigned ExtOpc, 2824 SmallVector<SDNode*, 4> &ExtendNodes, 2825 TargetLowering &TLI) { 2826 bool HasCopyToRegUses = false; 2827 bool isTruncFree = TLI.isTruncateFree(N->getValueType(0), N0.getValueType()); 2828 for (SDNode::use_iterator UI = N0.getNode()->use_begin(), 2829 UE = N0.getNode()->use_end(); 2830 UI != UE; ++UI) { 2831 SDNode *User = *UI; 2832 if (User == N) 2833 continue; 2834 // FIXME: Only extend SETCC N, N and SETCC N, c for now. 2835 if (User->getOpcode() == ISD::SETCC) { 2836 ISD::CondCode CC = cast<CondCodeSDNode>(User->getOperand(2))->get(); 2837 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC)) 2838 // Sign bits will be lost after a zext. 2839 return false; 2840 bool Add = false; 2841 for (unsigned i = 0; i != 2; ++i) { 2842 SDValue UseOp = User->getOperand(i); 2843 if (UseOp == N0) 2844 continue; 2845 if (!isa<ConstantSDNode>(UseOp)) 2846 return false; 2847 Add = true; 2848 } 2849 if (Add) 2850 ExtendNodes.push_back(User); 2851 } else { 2852 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) { 2853 SDValue UseOp = User->getOperand(i); 2854 if (UseOp == N0) { 2855 // If truncate from extended type to original load type is free 2856 // on this target, then it's ok to extend a CopyToReg. 2857 if (isTruncFree && User->getOpcode() == ISD::CopyToReg) 2858 HasCopyToRegUses = true; 2859 else 2860 return false; 2861 } 2862 } 2863 } 2864 } 2865 2866 if (HasCopyToRegUses) { 2867 bool BothLiveOut = false; 2868 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 2869 UI != UE; ++UI) { 2870 SDNode *User = *UI; 2871 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) { 2872 SDValue UseOp = User->getOperand(i); 2873 if (UseOp.getNode() == N && UseOp.getResNo() == 0) { 2874 BothLiveOut = true; 2875 break; 2876 } 2877 } 2878 } 2879 if (BothLiveOut) 2880 // Both unextended and extended values are live out. There had better be 2881 // good a reason for the transformation. 2882 return ExtendNodes.size(); 2883 } 2884 return true; 2885} 2886 2887SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) { 2888 SDValue N0 = N->getOperand(0); 2889 MVT VT = N->getValueType(0); 2890 2891 // fold (sext c1) -> c1 2892 if (isa<ConstantSDNode>(N0)) 2893 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0); 2894 2895 // fold (sext (sext x)) -> (sext x) 2896 // fold (sext (aext x)) -> (sext x) 2897 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 2898 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0.getOperand(0)); 2899 2900 if (N0.getOpcode() == ISD::TRUNCATE) { 2901 // fold (sext (truncate (load x))) -> (sext (smaller load x)) 2902 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n))) 2903 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 2904 if (NarrowLoad.getNode()) { 2905 if (NarrowLoad.getNode() != N0.getNode()) 2906 CombineTo(N0.getNode(), NarrowLoad); 2907 return DAG.getNode(ISD::SIGN_EXTEND, VT, NarrowLoad); 2908 } 2909 2910 // See if the value being truncated is already sign extended. If so, just 2911 // eliminate the trunc/sext pair. 2912 SDValue Op = N0.getOperand(0); 2913 unsigned OpBits = Op.getValueType().getSizeInBits(); 2914 unsigned MidBits = N0.getValueType().getSizeInBits(); 2915 unsigned DestBits = VT.getSizeInBits(); 2916 unsigned NumSignBits = DAG.ComputeNumSignBits(Op); 2917 2918 if (OpBits == DestBits) { 2919 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign 2920 // bits, it is already ready. 2921 if (NumSignBits > DestBits-MidBits) 2922 return Op; 2923 } else if (OpBits < DestBits) { 2924 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign 2925 // bits, just sext from i32. 2926 if (NumSignBits > OpBits-MidBits) 2927 return DAG.getNode(ISD::SIGN_EXTEND, VT, Op); 2928 } else { 2929 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign 2930 // bits, just truncate to i32. 2931 if (NumSignBits > OpBits-MidBits) 2932 return DAG.getNode(ISD::TRUNCATE, VT, Op); 2933 } 2934 2935 // fold (sext (truncate x)) -> (sextinreg x). 2936 if (!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, 2937 N0.getValueType())) { 2938 if (Op.getValueType().bitsLT(VT)) 2939 Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op); 2940 else if (Op.getValueType().bitsGT(VT)) 2941 Op = DAG.getNode(ISD::TRUNCATE, VT, Op); 2942 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, Op, 2943 DAG.getValueType(N0.getValueType())); 2944 } 2945 } 2946 2947 // fold (sext (load x)) -> (sext (truncate (sextload x))) 2948 if (ISD::isNON_EXTLoad(N0.getNode()) && 2949 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 2950 TLI.isLoadExtLegal(ISD::SEXTLOAD, N0.getValueType()))) { 2951 bool DoXform = true; 2952 SmallVector<SDNode*, 4> SetCCs; 2953 if (!N0.hasOneUse()) 2954 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::SIGN_EXTEND, SetCCs, TLI); 2955 if (DoXform) { 2956 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2957 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 2958 LN0->getBasePtr(), LN0->getSrcValue(), 2959 LN0->getSrcValueOffset(), 2960 N0.getValueType(), 2961 LN0->isVolatile(), LN0->getAlignment()); 2962 CombineTo(N, ExtLoad); 2963 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad); 2964 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 2965 // Extend SetCC uses if necessary. 2966 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 2967 SDNode *SetCC = SetCCs[i]; 2968 SmallVector<SDValue, 4> Ops; 2969 for (unsigned j = 0; j != 2; ++j) { 2970 SDValue SOp = SetCC->getOperand(j); 2971 if (SOp == Trunc) 2972 Ops.push_back(ExtLoad); 2973 else 2974 Ops.push_back(DAG.getNode(ISD::SIGN_EXTEND, VT, SOp)); 2975 } 2976 Ops.push_back(SetCC->getOperand(2)); 2977 CombineTo(SetCC, DAG.getNode(ISD::SETCC, SetCC->getValueType(0), 2978 &Ops[0], Ops.size())); 2979 } 2980 return SDValue(N, 0); // Return N so it doesn't get rechecked! 2981 } 2982 } 2983 2984 // fold (sext (sextload x)) -> (sext (truncate (sextload x))) 2985 // fold (sext ( extload x)) -> (sext (truncate (sextload x))) 2986 if ((ISD::isSEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) && 2987 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) { 2988 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2989 MVT EVT = LN0->getMemoryVT(); 2990 if ((!LegalOperations && !LN0->isVolatile()) || 2991 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT)) { 2992 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 2993 LN0->getBasePtr(), LN0->getSrcValue(), 2994 LN0->getSrcValueOffset(), EVT, 2995 LN0->isVolatile(), LN0->getAlignment()); 2996 CombineTo(N, ExtLoad); 2997 CombineTo(N0.getNode(), 2998 DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 2999 ExtLoad.getValue(1)); 3000 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3001 } 3002 } 3003 3004 // sext(setcc x,y,cc) -> select_cc x, y, -1, 0, cc 3005 if (N0.getOpcode() == ISD::SETCC) { 3006 SDValue SCC = 3007 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), 3008 DAG.getConstant(~0ULL, VT), DAG.getConstant(0, VT), 3009 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 3010 if (SCC.getNode()) return SCC; 3011 } 3012 3013 // fold (sext x) -> (zext x) if the sign bit is known zero. 3014 if ((!LegalOperations || TLI.isOperationLegal(ISD::ZERO_EXTEND, VT)) && 3015 DAG.SignBitIsZero(N0)) 3016 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0); 3017 3018 return SDValue(); 3019} 3020 3021SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) { 3022 SDValue N0 = N->getOperand(0); 3023 MVT VT = N->getValueType(0); 3024 3025 // fold (zext c1) -> c1 3026 if (isa<ConstantSDNode>(N0)) 3027 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0); 3028 // fold (zext (zext x)) -> (zext x) 3029 // fold (zext (aext x)) -> (zext x) 3030 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 3031 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0.getOperand(0)); 3032 3033 // fold (zext (truncate (load x))) -> (zext (smaller load x)) 3034 // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n))) 3035 if (N0.getOpcode() == ISD::TRUNCATE) { 3036 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 3037 if (NarrowLoad.getNode()) { 3038 if (NarrowLoad.getNode() != N0.getNode()) 3039 CombineTo(N0.getNode(), NarrowLoad); 3040 return DAG.getNode(ISD::ZERO_EXTEND, VT, NarrowLoad); 3041 } 3042 } 3043 3044 // fold (zext (truncate x)) -> (and x, mask) 3045 if (N0.getOpcode() == ISD::TRUNCATE && 3046 (!LegalOperations || TLI.isOperationLegal(ISD::AND, VT))) { 3047 SDValue Op = N0.getOperand(0); 3048 if (Op.getValueType().bitsLT(VT)) { 3049 Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op); 3050 } else if (Op.getValueType().bitsGT(VT)) { 3051 Op = DAG.getNode(ISD::TRUNCATE, VT, Op); 3052 } 3053 return DAG.getZeroExtendInReg(Op, N0.getValueType()); 3054 } 3055 3056 // fold (zext (and (trunc x), cst)) -> (and x, cst). 3057 if (N0.getOpcode() == ISD::AND && 3058 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 3059 N0.getOperand(1).getOpcode() == ISD::Constant) { 3060 SDValue X = N0.getOperand(0).getOperand(0); 3061 if (X.getValueType().bitsLT(VT)) { 3062 X = DAG.getNode(ISD::ANY_EXTEND, VT, X); 3063 } else if (X.getValueType().bitsGT(VT)) { 3064 X = DAG.getNode(ISD::TRUNCATE, VT, X); 3065 } 3066 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 3067 Mask.zext(VT.getSizeInBits()); 3068 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT)); 3069 } 3070 3071 // fold (zext (load x)) -> (zext (truncate (zextload x))) 3072 if (ISD::isNON_EXTLoad(N0.getNode()) && 3073 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3074 TLI.isLoadExtLegal(ISD::ZEXTLOAD, N0.getValueType()))) { 3075 bool DoXform = true; 3076 SmallVector<SDNode*, 4> SetCCs; 3077 if (!N0.hasOneUse()) 3078 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ZERO_EXTEND, SetCCs, TLI); 3079 if (DoXform) { 3080 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3081 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 3082 LN0->getBasePtr(), LN0->getSrcValue(), 3083 LN0->getSrcValueOffset(), 3084 N0.getValueType(), 3085 LN0->isVolatile(), LN0->getAlignment()); 3086 CombineTo(N, ExtLoad); 3087 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad); 3088 CombineTo(N0.getNode(), Trunc, ExtLoad.getValue(1)); 3089 // Extend SetCC uses if necessary. 3090 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 3091 SDNode *SetCC = SetCCs[i]; 3092 SmallVector<SDValue, 4> Ops; 3093 for (unsigned j = 0; j != 2; ++j) { 3094 SDValue SOp = SetCC->getOperand(j); 3095 if (SOp == Trunc) 3096 Ops.push_back(ExtLoad); 3097 else 3098 Ops.push_back(DAG.getNode(ISD::ZERO_EXTEND, VT, SOp)); 3099 } 3100 Ops.push_back(SetCC->getOperand(2)); 3101 CombineTo(SetCC, DAG.getNode(ISD::SETCC, SetCC->getValueType(0), 3102 &Ops[0], Ops.size())); 3103 } 3104 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3105 } 3106 } 3107 3108 // fold (zext (zextload x)) -> (zext (truncate (zextload x))) 3109 // fold (zext ( extload x)) -> (zext (truncate (zextload x))) 3110 if ((ISD::isZEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) && 3111 ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) { 3112 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3113 MVT EVT = LN0->getMemoryVT(); 3114 if ((!LegalOperations && !LN0->isVolatile()) || 3115 TLI.isLoadExtLegal(ISD::ZEXTLOAD, EVT)) { 3116 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 3117 LN0->getBasePtr(), LN0->getSrcValue(), 3118 LN0->getSrcValueOffset(), EVT, 3119 LN0->isVolatile(), LN0->getAlignment()); 3120 CombineTo(N, ExtLoad); 3121 CombineTo(N0.getNode(), 3122 DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 3123 ExtLoad.getValue(1)); 3124 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3125 } 3126 } 3127 3128 // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 3129 if (N0.getOpcode() == ISD::SETCC) { 3130 SDValue SCC = 3131 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), 3132 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 3133 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 3134 if (SCC.getNode()) return SCC; 3135 } 3136 3137 return SDValue(); 3138} 3139 3140SDValue DAGCombiner::visitANY_EXTEND(SDNode *N) { 3141 SDValue N0 = N->getOperand(0); 3142 MVT VT = N->getValueType(0); 3143 3144 // fold (aext c1) -> c1 3145 if (isa<ConstantSDNode>(N0)) 3146 return DAG.getNode(ISD::ANY_EXTEND, VT, N0); 3147 // fold (aext (aext x)) -> (aext x) 3148 // fold (aext (zext x)) -> (zext x) 3149 // fold (aext (sext x)) -> (sext x) 3150 if (N0.getOpcode() == ISD::ANY_EXTEND || 3151 N0.getOpcode() == ISD::ZERO_EXTEND || 3152 N0.getOpcode() == ISD::SIGN_EXTEND) 3153 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0)); 3154 3155 // fold (aext (truncate (load x))) -> (aext (smaller load x)) 3156 // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n))) 3157 if (N0.getOpcode() == ISD::TRUNCATE) { 3158 SDValue NarrowLoad = ReduceLoadWidth(N0.getNode()); 3159 if (NarrowLoad.getNode()) { 3160 if (NarrowLoad.getNode() != N0.getNode()) 3161 CombineTo(N0.getNode(), NarrowLoad); 3162 return DAG.getNode(ISD::ANY_EXTEND, VT, NarrowLoad); 3163 } 3164 } 3165 3166 // fold (aext (truncate x)) 3167 if (N0.getOpcode() == ISD::TRUNCATE) { 3168 SDValue TruncOp = N0.getOperand(0); 3169 if (TruncOp.getValueType() == VT) 3170 return TruncOp; // x iff x size == zext size. 3171 if (TruncOp.getValueType().bitsGT(VT)) 3172 return DAG.getNode(ISD::TRUNCATE, VT, TruncOp); 3173 return DAG.getNode(ISD::ANY_EXTEND, VT, TruncOp); 3174 } 3175 3176 // fold (aext (and (trunc x), cst)) -> (and x, cst). 3177 if (N0.getOpcode() == ISD::AND && 3178 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 3179 N0.getOperand(1).getOpcode() == ISD::Constant) { 3180 SDValue X = N0.getOperand(0).getOperand(0); 3181 if (X.getValueType().bitsLT(VT)) { 3182 X = DAG.getNode(ISD::ANY_EXTEND, VT, X); 3183 } else if (X.getValueType().bitsGT(VT)) { 3184 X = DAG.getNode(ISD::TRUNCATE, VT, X); 3185 } 3186 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 3187 Mask.zext(VT.getSizeInBits()); 3188 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT)); 3189 } 3190 3191 // fold (aext (load x)) -> (aext (truncate (extload x))) 3192 if (ISD::isNON_EXTLoad(N0.getNode()) && N0.hasOneUse() && 3193 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3194 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) { 3195 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3196 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, LN0->getChain(), 3197 LN0->getBasePtr(), LN0->getSrcValue(), 3198 LN0->getSrcValueOffset(), 3199 N0.getValueType(), 3200 LN0->isVolatile(), LN0->getAlignment()); 3201 CombineTo(N, ExtLoad); 3202 // Redirect any chain users to the new load. 3203 DAG.ReplaceAllUsesOfValueWith(SDValue(LN0, 1), 3204 SDValue(ExtLoad.getNode(), 1)); 3205 // If any node needs the original loaded value, recompute it. 3206 if (!LN0->use_empty()) 3207 CombineTo(LN0, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 3208 ExtLoad.getValue(1)); 3209 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3210 } 3211 3212 // fold (aext (zextload x)) -> (aext (truncate (zextload x))) 3213 // fold (aext (sextload x)) -> (aext (truncate (sextload x))) 3214 // fold (aext ( extload x)) -> (aext (truncate (extload x))) 3215 if (N0.getOpcode() == ISD::LOAD && 3216 !ISD::isNON_EXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 3217 N0.hasOneUse()) { 3218 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3219 MVT EVT = LN0->getMemoryVT(); 3220 SDValue ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), VT, 3221 LN0->getChain(), LN0->getBasePtr(), 3222 LN0->getSrcValue(), 3223 LN0->getSrcValueOffset(), EVT, 3224 LN0->isVolatile(), LN0->getAlignment()); 3225 CombineTo(N, ExtLoad); 3226 CombineTo(N0.getNode(), 3227 DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 3228 ExtLoad.getValue(1)); 3229 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3230 } 3231 3232 // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 3233 if (N0.getOpcode() == ISD::SETCC) { 3234 SDValue SCC = 3235 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), 3236 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 3237 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 3238 if (SCC.getNode()) 3239 return SCC; 3240 } 3241 3242 return SDValue(); 3243} 3244 3245/// GetDemandedBits - See if the specified operand can be simplified with the 3246/// knowledge that only the bits specified by Mask are used. If so, return the 3247/// simpler operand, otherwise return a null SDValue. 3248SDValue DAGCombiner::GetDemandedBits(SDValue V, const APInt &Mask) { 3249 switch (V.getOpcode()) { 3250 default: break; 3251 case ISD::OR: 3252 case ISD::XOR: 3253 // If the LHS or RHS don't contribute bits to the or, drop them. 3254 if (DAG.MaskedValueIsZero(V.getOperand(0), Mask)) 3255 return V.getOperand(1); 3256 if (DAG.MaskedValueIsZero(V.getOperand(1), Mask)) 3257 return V.getOperand(0); 3258 break; 3259 case ISD::SRL: 3260 // Only look at single-use SRLs. 3261 if (!V.getNode()->hasOneUse()) 3262 break; 3263 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(V.getOperand(1))) { 3264 // See if we can recursively simplify the LHS. 3265 unsigned Amt = RHSC->getZExtValue(); 3266 APInt NewMask = Mask << Amt; 3267 SDValue SimplifyLHS = GetDemandedBits(V.getOperand(0), NewMask); 3268 if (SimplifyLHS.getNode()) { 3269 return DAG.getNode(ISD::SRL, V.getValueType(), 3270 SimplifyLHS, V.getOperand(1)); 3271 } 3272 } 3273 } 3274 return SDValue(); 3275} 3276 3277/// ReduceLoadWidth - If the result of a wider load is shifted to right of N 3278/// bits and then truncated to a narrower type and where N is a multiple 3279/// of number of bits of the narrower type, transform it to a narrower load 3280/// from address + N / num of bits of new type. If the result is to be 3281/// extended, also fold the extension to form a extending load. 3282SDValue DAGCombiner::ReduceLoadWidth(SDNode *N) { 3283 unsigned Opc = N->getOpcode(); 3284 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD; 3285 SDValue N0 = N->getOperand(0); 3286 MVT VT = N->getValueType(0); 3287 MVT EVT = N->getValueType(0); 3288 3289 // This transformation isn't valid for vector loads. 3290 if (VT.isVector()) 3291 return SDValue(); 3292 3293 // Special case: SIGN_EXTEND_INREG is basically truncating to EVT then 3294 // extended to VT. 3295 if (Opc == ISD::SIGN_EXTEND_INREG) { 3296 ExtType = ISD::SEXTLOAD; 3297 EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 3298 if (LegalOperations && !TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT)) 3299 return SDValue(); 3300 } 3301 3302 unsigned EVTBits = EVT.getSizeInBits(); 3303 unsigned ShAmt = 0; 3304 bool CombineSRL = false; 3305 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) { 3306 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 3307 ShAmt = N01->getZExtValue(); 3308 // Is the shift amount a multiple of size of VT? 3309 if ((ShAmt & (EVTBits-1)) == 0) { 3310 N0 = N0.getOperand(0); 3311 if (N0.getValueType().getSizeInBits() <= EVTBits) 3312 return SDValue(); 3313 CombineSRL = true; 3314 } 3315 } 3316 } 3317 3318 // Do not generate loads of non-round integer types since these can 3319 // be expensive (and would be wrong if the type is not byte sized). 3320 if (isa<LoadSDNode>(N0) && N0.hasOneUse() && VT.isRound() && 3321 cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits() > EVTBits && 3322 // Do not change the width of a volatile load. 3323 !cast<LoadSDNode>(N0)->isVolatile()) { 3324 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3325 MVT PtrType = N0.getOperand(1).getValueType(); 3326 // For big endian targets, we need to adjust the offset to the pointer to 3327 // load the correct bytes. 3328 if (TLI.isBigEndian()) { 3329 unsigned LVTStoreBits = LN0->getMemoryVT().getStoreSizeInBits(); 3330 unsigned EVTStoreBits = EVT.getStoreSizeInBits(); 3331 ShAmt = LVTStoreBits - EVTStoreBits - ShAmt; 3332 } 3333 uint64_t PtrOff = ShAmt / 8; 3334 unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff); 3335 SDValue NewPtr = DAG.getNode(ISD::ADD, PtrType, LN0->getBasePtr(), 3336 DAG.getConstant(PtrOff, PtrType)); 3337 AddToWorkList(NewPtr.getNode()); 3338 SDValue Load = (ExtType == ISD::NON_EXTLOAD) 3339 ? DAG.getLoad(VT, LN0->getChain(), NewPtr, 3340 LN0->getSrcValue(), LN0->getSrcValueOffset() + PtrOff, 3341 LN0->isVolatile(), NewAlign) 3342 : DAG.getExtLoad(ExtType, VT, LN0->getChain(), NewPtr, 3343 LN0->getSrcValue(), LN0->getSrcValueOffset() + PtrOff, 3344 EVT, LN0->isVolatile(), NewAlign); 3345 AddToWorkList(N); 3346 if (CombineSRL) { 3347 WorkListRemover DeadNodes(*this); 3348 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1), 3349 &DeadNodes); 3350 CombineTo(N->getOperand(0).getNode(), Load); 3351 } else 3352 CombineTo(N0.getNode(), Load, Load.getValue(1)); 3353 if (ShAmt) { 3354 if (Opc == ISD::SIGN_EXTEND_INREG) 3355 return DAG.getNode(Opc, VT, Load, N->getOperand(1)); 3356 else 3357 return DAG.getNode(Opc, VT, Load); 3358 } 3359 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3360 } 3361 3362 return SDValue(); 3363} 3364 3365 3366SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) { 3367 SDValue N0 = N->getOperand(0); 3368 SDValue N1 = N->getOperand(1); 3369 MVT VT = N->getValueType(0); 3370 MVT EVT = cast<VTSDNode>(N1)->getVT(); 3371 unsigned VTBits = VT.getSizeInBits(); 3372 unsigned EVTBits = EVT.getSizeInBits(); 3373 3374 // fold (sext_in_reg c1) -> c1 3375 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF) 3376 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0, N1); 3377 3378 // If the input is already sign extended, just drop the extension. 3379 if (DAG.ComputeNumSignBits(N0) >= VT.getSizeInBits()-EVTBits+1) 3380 return N0; 3381 3382 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2 3383 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 3384 EVT.bitsLT(cast<VTSDNode>(N0.getOperand(1))->getVT())) { 3385 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), N1); 3386 } 3387 3388 // fold (sext_in_reg (sext x)) -> (sext x) 3389 // fold (sext_in_reg (aext x)) -> (sext x) 3390 // if x is small enough. 3391 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) { 3392 SDValue N00 = N0.getOperand(0); 3393 if (N00.getValueType().getSizeInBits() < EVTBits) 3394 return DAG.getNode(ISD::SIGN_EXTEND, VT, N00, N1); 3395 } 3396 3397 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero. 3398 if (DAG.MaskedValueIsZero(N0, APInt::getBitsSet(VTBits, EVTBits-1, EVTBits))) 3399 return DAG.getZeroExtendInReg(N0, EVT); 3400 3401 // fold operands of sext_in_reg based on knowledge that the top bits are not 3402 // demanded. 3403 if (SimplifyDemandedBits(SDValue(N, 0))) 3404 return SDValue(N, 0); 3405 3406 // fold (sext_in_reg (load x)) -> (smaller sextload x) 3407 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits)) 3408 SDValue NarrowLoad = ReduceLoadWidth(N); 3409 if (NarrowLoad.getNode()) 3410 return NarrowLoad; 3411 3412 // fold (sext_in_reg (srl X, 24), i8) -> sra X, 24 3413 // fold (sext_in_reg (srl X, 23), i8) -> sra X, 23 iff possible. 3414 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above. 3415 if (N0.getOpcode() == ISD::SRL) { 3416 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 3417 if (ShAmt->getZExtValue()+EVTBits <= VT.getSizeInBits()) { 3418 // We can turn this into an SRA iff the input to the SRL is already sign 3419 // extended enough. 3420 unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0)); 3421 if (VT.getSizeInBits()-(ShAmt->getZExtValue()+EVTBits) < InSignBits) 3422 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0), N0.getOperand(1)); 3423 } 3424 } 3425 3426 // fold (sext_inreg (extload x)) -> (sextload x) 3427 if (ISD::isEXTLoad(N0.getNode()) && 3428 ISD::isUNINDEXEDLoad(N0.getNode()) && 3429 EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 3430 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3431 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) { 3432 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3433 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 3434 LN0->getBasePtr(), LN0->getSrcValue(), 3435 LN0->getSrcValueOffset(), EVT, 3436 LN0->isVolatile(), LN0->getAlignment()); 3437 CombineTo(N, ExtLoad); 3438 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 3439 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3440 } 3441 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use 3442 if (ISD::isZEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) && 3443 N0.hasOneUse() && 3444 EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 3445 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 3446 TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))) { 3447 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3448 SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 3449 LN0->getBasePtr(), LN0->getSrcValue(), 3450 LN0->getSrcValueOffset(), EVT, 3451 LN0->isVolatile(), LN0->getAlignment()); 3452 CombineTo(N, ExtLoad); 3453 CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1)); 3454 return SDValue(N, 0); // Return N so it doesn't get rechecked! 3455 } 3456 return SDValue(); 3457} 3458 3459SDValue DAGCombiner::visitTRUNCATE(SDNode *N) { 3460 SDValue N0 = N->getOperand(0); 3461 MVT VT = N->getValueType(0); 3462 3463 // noop truncate 3464 if (N0.getValueType() == N->getValueType(0)) 3465 return N0; 3466 // fold (truncate c1) -> c1 3467 if (isa<ConstantSDNode>(N0)) 3468 return DAG.getNode(ISD::TRUNCATE, VT, N0); 3469 // fold (truncate (truncate x)) -> (truncate x) 3470 if (N0.getOpcode() == ISD::TRUNCATE) 3471 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0)); 3472 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x 3473 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::SIGN_EXTEND|| 3474 N0.getOpcode() == ISD::ANY_EXTEND) { 3475 if (N0.getOperand(0).getValueType().bitsLT(VT)) 3476 // if the source is smaller than the dest, we still need an extend 3477 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0)); 3478 else if (N0.getOperand(0).getValueType().bitsGT(VT)) 3479 // if the source is larger than the dest, than we just need the truncate 3480 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0)); 3481 else 3482 // if the source and dest are the same type, we can drop both the extend 3483 // and the truncate 3484 return N0.getOperand(0); 3485 } 3486 3487 // See if we can simplify the input to this truncate through knowledge that 3488 // only the low bits are being used. For example "trunc (or (shl x, 8), y)" 3489 // -> trunc y 3490 SDValue Shorter = 3491 GetDemandedBits(N0, APInt::getLowBitsSet(N0.getValueSizeInBits(), 3492 VT.getSizeInBits())); 3493 if (Shorter.getNode()) 3494 return DAG.getNode(ISD::TRUNCATE, VT, Shorter); 3495 3496 // fold (truncate (load x)) -> (smaller load x) 3497 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits)) 3498 return ReduceLoadWidth(N); 3499} 3500 3501static SDNode *getBuildPairElt(SDNode *N, unsigned i) { 3502 SDValue Elt = N->getOperand(i); 3503 if (Elt.getOpcode() != ISD::MERGE_VALUES) 3504 return Elt.getNode(); 3505 return Elt.getOperand(Elt.getResNo()).getNode(); 3506} 3507 3508/// CombineConsecutiveLoads - build_pair (load, load) -> load 3509/// if load locations are consecutive. 3510SDValue DAGCombiner::CombineConsecutiveLoads(SDNode *N, MVT VT) { 3511 assert(N->getOpcode() == ISD::BUILD_PAIR); 3512 3513 SDNode *LD1 = getBuildPairElt(N, 0); 3514 if (!ISD::isNON_EXTLoad(LD1) || !LD1->hasOneUse()) 3515 return SDValue(); 3516 MVT LD1VT = LD1->getValueType(0); 3517 SDNode *LD2 = getBuildPairElt(N, 1); 3518 const MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 3519 if (ISD::isNON_EXTLoad(LD2) && 3520 LD2->hasOneUse() && 3521 // If both are volatile this would reduce the number of volatile loads. 3522 // If one is volatile it might be ok, but play conservative and bail out. 3523 !cast<LoadSDNode>(LD1)->isVolatile() && 3524 !cast<LoadSDNode>(LD2)->isVolatile() && 3525 TLI.isConsecutiveLoad(LD2, LD1, LD1VT.getSizeInBits()/8, 1, MFI)) { 3526 LoadSDNode *LD = cast<LoadSDNode>(LD1); 3527 unsigned Align = LD->getAlignment(); 3528 unsigned NewAlign = TLI.getTargetData()-> 3529 getABITypeAlignment(VT.getTypeForMVT()); 3530 if (NewAlign <= Align && 3531 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) 3532 return DAG.getLoad(VT, LD->getChain(), LD->getBasePtr(), 3533 LD->getSrcValue(), LD->getSrcValueOffset(), 3534 false, Align); 3535 } 3536 return SDValue(); 3537} 3538 3539SDValue DAGCombiner::visitBIT_CONVERT(SDNode *N) { 3540 SDValue N0 = N->getOperand(0); 3541 MVT VT = N->getValueType(0); 3542 3543 // If the input is a BUILD_VECTOR with all constant elements, fold this now. 3544 // Only do this before legalize, since afterward the target may be depending 3545 // on the bitconvert. 3546 // First check to see if this is all constant. 3547 if (!LegalTypes && 3548 N0.getOpcode() == ISD::BUILD_VECTOR && N0.getNode()->hasOneUse() && 3549 VT.isVector()) { 3550 bool isSimple = true; 3551 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i) 3552 if (N0.getOperand(i).getOpcode() != ISD::UNDEF && 3553 N0.getOperand(i).getOpcode() != ISD::Constant && 3554 N0.getOperand(i).getOpcode() != ISD::ConstantFP) { 3555 isSimple = false; 3556 break; 3557 } 3558 3559 MVT DestEltVT = N->getValueType(0).getVectorElementType(); 3560 assert(!DestEltVT.isVector() && 3561 "Element type of vector ValueType must not be vector!"); 3562 if (isSimple) { 3563 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(N0.getNode(), DestEltVT); 3564 } 3565 } 3566 3567 // If the input is a constant, let getNode fold it. 3568 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) { 3569 SDValue Res = DAG.getNode(ISD::BIT_CONVERT, VT, N0); 3570 if (Res.getNode() != N) return Res; 3571 } 3572 3573 if (N0.getOpcode() == ISD::BIT_CONVERT) // conv(conv(x,t1),t2) -> conv(x,t2) 3574 return DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0)); 3575 3576 // fold (conv (load x)) -> (load (conv*)x) 3577 // If the resultant load doesn't need a higher alignment than the original! 3578 if (ISD::isNormalLoad(N0.getNode()) && N0.hasOneUse() && 3579 // Do not change the width of a volatile load. 3580 !cast<LoadSDNode>(N0)->isVolatile() && 3581 (!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) { 3582 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3583 unsigned Align = TLI.getTargetData()-> 3584 getABITypeAlignment(VT.getTypeForMVT()); 3585 unsigned OrigAlign = LN0->getAlignment(); 3586 if (Align <= OrigAlign) { 3587 SDValue Load = DAG.getLoad(VT, LN0->getChain(), LN0->getBasePtr(), 3588 LN0->getSrcValue(), LN0->getSrcValueOffset(), 3589 LN0->isVolatile(), OrigAlign); 3590 AddToWorkList(N); 3591 CombineTo(N0.getNode(), 3592 DAG.getNode(ISD::BIT_CONVERT, N0.getValueType(), Load), 3593 Load.getValue(1)); 3594 return Load; 3595 } 3596 } 3597 3598 // Fold bitconvert(fneg(x)) -> xor(bitconvert(x), signbit) 3599 // Fold bitconvert(fabs(x)) -> and(bitconvert(x), ~signbit) 3600 // This often reduces constant pool loads. 3601 if ((N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FABS) && 3602 N0.getNode()->hasOneUse() && VT.isInteger() && !VT.isVector()) { 3603 SDValue NewConv = DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0)); 3604 AddToWorkList(NewConv.getNode()); 3605 3606 APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); 3607 if (N0.getOpcode() == ISD::FNEG) 3608 return DAG.getNode(ISD::XOR, VT, NewConv, DAG.getConstant(SignBit, VT)); 3609 assert(N0.getOpcode() == ISD::FABS); 3610 return DAG.getNode(ISD::AND, VT, NewConv, DAG.getConstant(~SignBit, VT)); 3611 } 3612 3613 // Fold bitconvert(fcopysign(cst, x)) -> bitconvert(x)&sign | cst&~sign' 3614 // Note that we don't handle copysign(x,cst) because this can always be folded 3615 // to an fneg or fabs. 3616 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse() && 3617 isa<ConstantFPSDNode>(N0.getOperand(0)) && 3618 VT.isInteger() && !VT.isVector()) { 3619 unsigned OrigXWidth = N0.getOperand(1).getValueType().getSizeInBits(); 3620 MVT IntXVT = MVT::getIntegerVT(OrigXWidth); 3621 if (TLI.isTypeLegal(IntXVT) || !LegalTypes) { 3622 SDValue X = DAG.getNode(ISD::BIT_CONVERT, IntXVT, N0.getOperand(1)); 3623 AddToWorkList(X.getNode()); 3624 3625 // If X has a different width than the result/lhs, sext it or truncate it. 3626 unsigned VTWidth = VT.getSizeInBits(); 3627 if (OrigXWidth < VTWidth) { 3628 X = DAG.getNode(ISD::SIGN_EXTEND, VT, X); 3629 AddToWorkList(X.getNode()); 3630 } else if (OrigXWidth > VTWidth) { 3631 // To get the sign bit in the right place, we have to shift it right 3632 // before truncating. 3633 X = DAG.getNode(ISD::SRL, X.getValueType(), X, 3634 DAG.getConstant(OrigXWidth-VTWidth, X.getValueType())); 3635 AddToWorkList(X.getNode()); 3636 X = DAG.getNode(ISD::TRUNCATE, VT, X); 3637 AddToWorkList(X.getNode()); 3638 } 3639 3640 APInt SignBit = APInt::getSignBit(VT.getSizeInBits()); 3641 X = DAG.getNode(ISD::AND, VT, X, DAG.getConstant(SignBit, VT)); 3642 AddToWorkList(X.getNode()); 3643 3644 SDValue Cst = DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0)); 3645 Cst = DAG.getNode(ISD::AND, VT, Cst, DAG.getConstant(~SignBit, VT)); 3646 AddToWorkList(Cst.getNode()); 3647 3648 return DAG.getNode(ISD::OR, VT, X, Cst); 3649 } 3650 } 3651 3652 // bitconvert(build_pair(ld, ld)) -> ld iff load locations are consecutive. 3653 if (N0.getOpcode() == ISD::BUILD_PAIR) { 3654 SDValue CombineLD = CombineConsecutiveLoads(N0.getNode(), VT); 3655 if (CombineLD.getNode()) 3656 return CombineLD; 3657 } 3658 3659 return SDValue(); 3660} 3661 3662SDValue DAGCombiner::visitBUILD_PAIR(SDNode *N) { 3663 MVT VT = N->getValueType(0); 3664 return CombineConsecutiveLoads(N, VT); 3665} 3666 3667/// ConstantFoldBIT_CONVERTofBUILD_VECTOR - We know that BV is a build_vector 3668/// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the 3669/// destination element value type. 3670SDValue DAGCombiner:: 3671ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *BV, MVT DstEltVT) { 3672 MVT SrcEltVT = BV->getOperand(0).getValueType(); 3673 3674 // If this is already the right type, we're done. 3675 if (SrcEltVT == DstEltVT) return SDValue(BV, 0); 3676 3677 unsigned SrcBitSize = SrcEltVT.getSizeInBits(); 3678 unsigned DstBitSize = DstEltVT.getSizeInBits(); 3679 3680 // If this is a conversion of N elements of one type to N elements of another 3681 // type, convert each element. This handles FP<->INT cases. 3682 if (SrcBitSize == DstBitSize) { 3683 SmallVector<SDValue, 8> Ops; 3684 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 3685 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, DstEltVT, BV->getOperand(i))); 3686 AddToWorkList(Ops.back().getNode()); 3687 } 3688 MVT VT = MVT::getVectorVT(DstEltVT, 3689 BV->getValueType(0).getVectorNumElements()); 3690 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 3691 } 3692 3693 // Otherwise, we're growing or shrinking the elements. To avoid having to 3694 // handle annoying details of growing/shrinking FP values, we convert them to 3695 // int first. 3696 if (SrcEltVT.isFloatingPoint()) { 3697 // Convert the input float vector to a int vector where the elements are the 3698 // same sizes. 3699 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!"); 3700 MVT IntVT = MVT::getIntegerVT(SrcEltVT.getSizeInBits()); 3701 BV = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, IntVT).getNode(); 3702 SrcEltVT = IntVT; 3703 } 3704 3705 // Now we know the input is an integer vector. If the output is a FP type, 3706 // convert to integer first, then to FP of the right size. 3707 if (DstEltVT.isFloatingPoint()) { 3708 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!"); 3709 MVT TmpVT = MVT::getIntegerVT(DstEltVT.getSizeInBits()); 3710 SDNode *Tmp = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, TmpVT).getNode(); 3711 3712 // Next, convert to FP elements of the same size. 3713 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(Tmp, DstEltVT); 3714 } 3715 3716 // Okay, we know the src/dst types are both integers of differing types. 3717 // Handling growing first. 3718 assert(SrcEltVT.isInteger() && DstEltVT.isInteger()); 3719 if (SrcBitSize < DstBitSize) { 3720 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize; 3721 3722 SmallVector<SDValue, 8> Ops; 3723 for (unsigned i = 0, e = BV->getNumOperands(); i != e; 3724 i += NumInputsPerOutput) { 3725 bool isLE = TLI.isLittleEndian(); 3726 APInt NewBits = APInt(DstBitSize, 0); 3727 bool EltIsUndef = true; 3728 for (unsigned j = 0; j != NumInputsPerOutput; ++j) { 3729 // Shift the previously computed bits over. 3730 NewBits <<= SrcBitSize; 3731 SDValue Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j)); 3732 if (Op.getOpcode() == ISD::UNDEF) continue; 3733 EltIsUndef = false; 3734 3735 NewBits |= 3736 APInt(cast<ConstantSDNode>(Op)->getAPIntValue()).zext(DstBitSize); 3737 } 3738 3739 if (EltIsUndef) 3740 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT)); 3741 else 3742 Ops.push_back(DAG.getConstant(NewBits, DstEltVT)); 3743 } 3744 3745 MVT VT = MVT::getVectorVT(DstEltVT, Ops.size()); 3746 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 3747 } 3748 3749 // Finally, this must be the case where we are shrinking elements: each input 3750 // turns into multiple outputs. 3751 bool isS2V = ISD::isScalarToVector(BV); 3752 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize; 3753 MVT VT = MVT::getVectorVT(DstEltVT, NumOutputsPerInput*BV->getNumOperands()); 3754 SmallVector<SDValue, 8> Ops; 3755 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 3756 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) { 3757 for (unsigned j = 0; j != NumOutputsPerInput; ++j) 3758 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT)); 3759 continue; 3760 } 3761 APInt OpVal = cast<ConstantSDNode>(BV->getOperand(i))->getAPIntValue(); 3762 for (unsigned j = 0; j != NumOutputsPerInput; ++j) { 3763 APInt ThisVal = APInt(OpVal).trunc(DstBitSize); 3764 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT)); 3765 if (isS2V && i == 0 && j == 0 && APInt(ThisVal).zext(SrcBitSize) == OpVal) 3766 // Simply turn this into a SCALAR_TO_VECTOR of the new type. 3767 return DAG.getNode(ISD::SCALAR_TO_VECTOR, VT, Ops[0]); 3768 OpVal = OpVal.lshr(DstBitSize); 3769 } 3770 3771 // For big endian targets, swap the order of the pieces of each element. 3772 if (TLI.isBigEndian()) 3773 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end()); 3774 } 3775 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 3776} 3777 3778 3779 3780SDValue DAGCombiner::visitFADD(SDNode *N) { 3781 SDValue N0 = N->getOperand(0); 3782 SDValue N1 = N->getOperand(1); 3783 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3784 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3785 MVT VT = N->getValueType(0); 3786 3787 // fold vector ops 3788 if (VT.isVector()) { 3789 SDValue FoldedVOp = SimplifyVBinOp(N); 3790 if (FoldedVOp.getNode()) return FoldedVOp; 3791 } 3792 3793 // fold (fadd c1, c2) -> c1+c2 3794 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3795 return DAG.getNode(ISD::FADD, VT, N0, N1); 3796 // canonicalize constant to RHS 3797 if (N0CFP && !N1CFP) 3798 return DAG.getNode(ISD::FADD, VT, N1, N0); 3799 // fold (A + (-B)) -> A-B 3800 if (isNegatibleForFree(N1, LegalOperations) == 2) 3801 return DAG.getNode(ISD::FSUB, VT, N0, 3802 GetNegatedExpression(N1, DAG, LegalOperations)); 3803 // fold ((-A) + B) -> B-A 3804 if (isNegatibleForFree(N0, LegalOperations) == 2) 3805 return DAG.getNode(ISD::FSUB, VT, N1, 3806 GetNegatedExpression(N0, DAG, LegalOperations)); 3807 3808 // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2)) 3809 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FADD && 3810 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 3811 return DAG.getNode(ISD::FADD, VT, N0.getOperand(0), 3812 DAG.getNode(ISD::FADD, VT, N0.getOperand(1), N1)); 3813 3814 return SDValue(); 3815} 3816 3817SDValue DAGCombiner::visitFSUB(SDNode *N) { 3818 SDValue N0 = N->getOperand(0); 3819 SDValue N1 = N->getOperand(1); 3820 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3821 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3822 MVT VT = N->getValueType(0); 3823 3824 // fold vector ops 3825 if (VT.isVector()) { 3826 SDValue FoldedVOp = SimplifyVBinOp(N); 3827 if (FoldedVOp.getNode()) return FoldedVOp; 3828 } 3829 3830 // fold (fsub c1, c2) -> c1-c2 3831 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3832 return DAG.getNode(ISD::FSUB, VT, N0, N1); 3833 // fold (0-B) -> -B 3834 if (UnsafeFPMath && N0CFP && N0CFP->getValueAPF().isZero()) { 3835 if (isNegatibleForFree(N1, LegalOperations)) 3836 return GetNegatedExpression(N1, DAG, LegalOperations); 3837 return DAG.getNode(ISD::FNEG, VT, N1); 3838 } 3839 // fold (A-(-B)) -> A+B 3840 if (isNegatibleForFree(N1, LegalOperations)) 3841 return DAG.getNode(ISD::FADD, VT, N0, 3842 GetNegatedExpression(N1, DAG, LegalOperations)); 3843 3844 return SDValue(); 3845} 3846 3847SDValue DAGCombiner::visitFMUL(SDNode *N) { 3848 SDValue N0 = N->getOperand(0); 3849 SDValue N1 = N->getOperand(1); 3850 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3851 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3852 MVT VT = N->getValueType(0); 3853 3854 // fold vector ops 3855 if (VT.isVector()) { 3856 SDValue FoldedVOp = SimplifyVBinOp(N); 3857 if (FoldedVOp.getNode()) return FoldedVOp; 3858 } 3859 3860 // fold (fmul c1, c2) -> c1*c2 3861 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3862 return DAG.getNode(ISD::FMUL, VT, N0, N1); 3863 // canonicalize constant to RHS 3864 if (N0CFP && !N1CFP) 3865 return DAG.getNode(ISD::FMUL, VT, N1, N0); 3866 // fold (fmul X, 2.0) -> (fadd X, X) 3867 if (N1CFP && N1CFP->isExactlyValue(+2.0)) 3868 return DAG.getNode(ISD::FADD, VT, N0, N0); 3869 // fold (fmul X, -1.0) -> (fneg X) 3870 if (N1CFP && N1CFP->isExactlyValue(-1.0)) 3871 return DAG.getNode(ISD::FNEG, VT, N0); 3872 3873 // -X * -Y -> X*Y 3874 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations)) { 3875 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations)) { 3876 // Both can be negated for free, check to see if at least one is cheaper 3877 // negated. 3878 if (LHSNeg == 2 || RHSNeg == 2) 3879 return DAG.getNode(ISD::FMUL, VT, 3880 GetNegatedExpression(N0, DAG, LegalOperations), 3881 GetNegatedExpression(N1, DAG, LegalOperations)); 3882 } 3883 } 3884 3885 // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2)) 3886 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FMUL && 3887 N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 3888 return DAG.getNode(ISD::FMUL, VT, N0.getOperand(0), 3889 DAG.getNode(ISD::FMUL, VT, N0.getOperand(1), N1)); 3890 3891 return SDValue(); 3892} 3893 3894SDValue DAGCombiner::visitFDIV(SDNode *N) { 3895 SDValue N0 = N->getOperand(0); 3896 SDValue N1 = N->getOperand(1); 3897 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3898 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3899 MVT VT = N->getValueType(0); 3900 3901 // fold vector ops 3902 if (VT.isVector()) { 3903 SDValue FoldedVOp = SimplifyVBinOp(N); 3904 if (FoldedVOp.getNode()) return FoldedVOp; 3905 } 3906 3907 // fold (fdiv c1, c2) -> c1/c2 3908 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3909 return DAG.getNode(ISD::FDIV, VT, N0, N1); 3910 3911 3912 // -X / -Y -> X*Y 3913 if (char LHSNeg = isNegatibleForFree(N0, LegalOperations)) { 3914 if (char RHSNeg = isNegatibleForFree(N1, LegalOperations)) { 3915 // Both can be negated for free, check to see if at least one is cheaper 3916 // negated. 3917 if (LHSNeg == 2 || RHSNeg == 2) 3918 return DAG.getNode(ISD::FDIV, VT, 3919 GetNegatedExpression(N0, DAG, LegalOperations), 3920 GetNegatedExpression(N1, DAG, LegalOperations)); 3921 } 3922 } 3923 3924 return SDValue(); 3925} 3926 3927SDValue DAGCombiner::visitFREM(SDNode *N) { 3928 SDValue N0 = N->getOperand(0); 3929 SDValue N1 = N->getOperand(1); 3930 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3931 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3932 MVT VT = N->getValueType(0); 3933 3934 // fold (frem c1, c2) -> fmod(c1,c2) 3935 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3936 return DAG.getNode(ISD::FREM, VT, N0, N1); 3937 3938 return SDValue(); 3939} 3940 3941SDValue DAGCombiner::visitFCOPYSIGN(SDNode *N) { 3942 SDValue N0 = N->getOperand(0); 3943 SDValue N1 = N->getOperand(1); 3944 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3945 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3946 MVT VT = N->getValueType(0); 3947 3948 if (N0CFP && N1CFP && VT != MVT::ppcf128) // Constant fold 3949 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1); 3950 3951 if (N1CFP) { 3952 const APFloat& V = N1CFP->getValueAPF(); 3953 // copysign(x, c1) -> fabs(x) iff ispos(c1) 3954 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1) 3955 if (!V.isNegative()) 3956 return DAG.getNode(ISD::FABS, VT, N0); 3957 else 3958 return DAG.getNode(ISD::FNEG, VT, DAG.getNode(ISD::FABS, VT, N0)); 3959 } 3960 3961 // copysign(fabs(x), y) -> copysign(x, y) 3962 // copysign(fneg(x), y) -> copysign(x, y) 3963 // copysign(copysign(x,z), y) -> copysign(x, y) 3964 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG || 3965 N0.getOpcode() == ISD::FCOPYSIGN) 3966 return DAG.getNode(ISD::FCOPYSIGN, VT, N0.getOperand(0), N1); 3967 3968 // copysign(x, abs(y)) -> abs(x) 3969 if (N1.getOpcode() == ISD::FABS) 3970 return DAG.getNode(ISD::FABS, VT, N0); 3971 3972 // copysign(x, copysign(y,z)) -> copysign(x, z) 3973 if (N1.getOpcode() == ISD::FCOPYSIGN) 3974 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(1)); 3975 3976 // copysign(x, fp_extend(y)) -> copysign(x, y) 3977 // copysign(x, fp_round(y)) -> copysign(x, y) 3978 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND) 3979 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(0)); 3980 3981 return SDValue(); 3982} 3983 3984 3985 3986SDValue DAGCombiner::visitSINT_TO_FP(SDNode *N) { 3987 SDValue N0 = N->getOperand(0); 3988 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3989 MVT VT = N->getValueType(0); 3990 MVT OpVT = N0.getValueType(); 3991 3992 // fold (sint_to_fp c1) -> c1fp 3993 if (N0C && OpVT != MVT::ppcf128) 3994 return DAG.getNode(ISD::SINT_TO_FP, VT, N0); 3995 3996 // If the input is a legal type, and SINT_TO_FP is not legal on this target, 3997 // but UINT_TO_FP is legal on this target, try to convert. 3998 if (!TLI.isOperationLegal(ISD::SINT_TO_FP, OpVT) && 3999 TLI.isOperationLegal(ISD::UINT_TO_FP, OpVT)) { 4000 // If the sign bit is known to be zero, we can change this to UINT_TO_FP. 4001 if (DAG.SignBitIsZero(N0)) 4002 return DAG.getNode(ISD::UINT_TO_FP, VT, N0); 4003 } 4004 4005 4006 return SDValue(); 4007} 4008 4009SDValue DAGCombiner::visitUINT_TO_FP(SDNode *N) { 4010 SDValue N0 = N->getOperand(0); 4011 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 4012 MVT VT = N->getValueType(0); 4013 MVT OpVT = N0.getValueType(); 4014 4015 // fold (uint_to_fp c1) -> c1fp 4016 if (N0C && OpVT != MVT::ppcf128) 4017 return DAG.getNode(ISD::UINT_TO_FP, VT, N0); 4018 4019 // If the input is a legal type, and UINT_TO_FP is not legal on this target, 4020 // but SINT_TO_FP is legal on this target, try to convert. 4021 if (!TLI.isOperationLegal(ISD::UINT_TO_FP, OpVT) && 4022 TLI.isOperationLegal(ISD::SINT_TO_FP, OpVT)) { 4023 // If the sign bit is known to be zero, we can change this to SINT_TO_FP. 4024 if (DAG.SignBitIsZero(N0)) 4025 return DAG.getNode(ISD::SINT_TO_FP, VT, N0); 4026 } 4027 4028 return SDValue(); 4029} 4030 4031SDValue DAGCombiner::visitFP_TO_SINT(SDNode *N) { 4032 SDValue N0 = N->getOperand(0); 4033 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4034 MVT VT = N->getValueType(0); 4035 4036 // fold (fp_to_sint c1fp) -> c1 4037 if (N0CFP) 4038 return DAG.getNode(ISD::FP_TO_SINT, VT, N0); 4039 return SDValue(); 4040} 4041 4042SDValue DAGCombiner::visitFP_TO_UINT(SDNode *N) { 4043 SDValue N0 = N->getOperand(0); 4044 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4045 MVT VT = N->getValueType(0); 4046 4047 // fold (fp_to_uint c1fp) -> c1 4048 if (N0CFP && VT != MVT::ppcf128) 4049 return DAG.getNode(ISD::FP_TO_UINT, VT, N0); 4050 return SDValue(); 4051} 4052 4053SDValue DAGCombiner::visitFP_ROUND(SDNode *N) { 4054 SDValue N0 = N->getOperand(0); 4055 SDValue N1 = N->getOperand(1); 4056 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4057 MVT VT = N->getValueType(0); 4058 4059 // fold (fp_round c1fp) -> c1fp 4060 if (N0CFP && N0.getValueType() != MVT::ppcf128) 4061 return DAG.getNode(ISD::FP_ROUND, VT, N0, N1); 4062 4063 // fold (fp_round (fp_extend x)) -> x 4064 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType()) 4065 return N0.getOperand(0); 4066 4067 // fold (fp_round (fp_round x)) -> (fp_round x) 4068 if (N0.getOpcode() == ISD::FP_ROUND) { 4069 // This is a value preserving truncation if both round's are. 4070 bool IsTrunc = N->getConstantOperandVal(1) == 1 && 4071 N0.getNode()->getConstantOperandVal(1) == 1; 4072 return DAG.getNode(ISD::FP_ROUND, VT, N0.getOperand(0), 4073 DAG.getIntPtrConstant(IsTrunc)); 4074 } 4075 4076 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y) 4077 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.getNode()->hasOneUse()) { 4078 SDValue Tmp = DAG.getNode(ISD::FP_ROUND, VT, N0.getOperand(0), N1); 4079 AddToWorkList(Tmp.getNode()); 4080 return DAG.getNode(ISD::FCOPYSIGN, VT, Tmp, N0.getOperand(1)); 4081 } 4082 4083 return SDValue(); 4084} 4085 4086SDValue DAGCombiner::visitFP_ROUND_INREG(SDNode *N) { 4087 SDValue N0 = N->getOperand(0); 4088 MVT VT = N->getValueType(0); 4089 MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 4090 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4091 4092 // fold (fp_round_inreg c1fp) -> c1fp 4093 if (N0CFP && (TLI.isTypeLegal(EVT) || !LegalTypes)) { 4094 SDValue Round = DAG.getConstantFP(*N0CFP->getConstantFPValue(), EVT); 4095 return DAG.getNode(ISD::FP_EXTEND, VT, Round); 4096 } 4097 return SDValue(); 4098} 4099 4100SDValue DAGCombiner::visitFP_EXTEND(SDNode *N) { 4101 SDValue N0 = N->getOperand(0); 4102 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4103 MVT VT = N->getValueType(0); 4104 4105 // If this is fp_round(fpextend), don't fold it, allow ourselves to be folded. 4106 if (N->hasOneUse() && 4107 N->use_begin().getUse().getSDValue().getOpcode() == ISD::FP_ROUND) 4108 return SDValue(); 4109 4110 // fold (fp_extend c1fp) -> c1fp 4111 if (N0CFP && VT != MVT::ppcf128) 4112 return DAG.getNode(ISD::FP_EXTEND, VT, N0); 4113 4114 // Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't affect the 4115 // value of X. 4116 if (N0.getOpcode() == ISD::FP_ROUND 4117 && N0.getNode()->getConstantOperandVal(1) == 1) { 4118 SDValue In = N0.getOperand(0); 4119 if (In.getValueType() == VT) return In; 4120 if (VT.bitsLT(In.getValueType())) 4121 return DAG.getNode(ISD::FP_ROUND, VT, In, N0.getOperand(1)); 4122 return DAG.getNode(ISD::FP_EXTEND, VT, In); 4123 } 4124 4125 // fold (fpext (load x)) -> (fpext (fptrunc (extload x))) 4126 if (ISD::isNON_EXTLoad(N0.getNode()) && N0.hasOneUse() && 4127 ((!LegalOperations && !cast<LoadSDNode>(N0)->isVolatile()) || 4128 TLI.isLoadExtLegal(ISD::EXTLOAD, N0.getValueType()))) { 4129 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 4130 SDValue ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, LN0->getChain(), 4131 LN0->getBasePtr(), LN0->getSrcValue(), 4132 LN0->getSrcValueOffset(), 4133 N0.getValueType(), 4134 LN0->isVolatile(), LN0->getAlignment()); 4135 CombineTo(N, ExtLoad); 4136 CombineTo(N0.getNode(), DAG.getNode(ISD::FP_ROUND, N0.getValueType(), 4137 ExtLoad, DAG.getIntPtrConstant(1)), 4138 ExtLoad.getValue(1)); 4139 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4140 } 4141 4142 return SDValue(); 4143} 4144 4145SDValue DAGCombiner::visitFNEG(SDNode *N) { 4146 SDValue N0 = N->getOperand(0); 4147 4148 if (isNegatibleForFree(N0, LegalOperations)) 4149 return GetNegatedExpression(N0, DAG, LegalOperations); 4150 4151 // Transform fneg(bitconvert(x)) -> bitconvert(x^sign) to avoid loading 4152 // constant pool values. 4153 if (N0.getOpcode() == ISD::BIT_CONVERT && N0.getNode()->hasOneUse() && 4154 N0.getOperand(0).getValueType().isInteger() && 4155 !N0.getOperand(0).getValueType().isVector()) { 4156 SDValue Int = N0.getOperand(0); 4157 MVT IntVT = Int.getValueType(); 4158 if (IntVT.isInteger() && !IntVT.isVector()) { 4159 Int = DAG.getNode(ISD::XOR, IntVT, Int, 4160 DAG.getConstant(IntVT.getIntegerVTSignBit(), IntVT)); 4161 AddToWorkList(Int.getNode()); 4162 return DAG.getNode(ISD::BIT_CONVERT, N->getValueType(0), Int); 4163 } 4164 } 4165 4166 return SDValue(); 4167} 4168 4169SDValue DAGCombiner::visitFABS(SDNode *N) { 4170 SDValue N0 = N->getOperand(0); 4171 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 4172 MVT VT = N->getValueType(0); 4173 4174 // fold (fabs c1) -> fabs(c1) 4175 if (N0CFP && VT != MVT::ppcf128) 4176 return DAG.getNode(ISD::FABS, VT, N0); 4177 // fold (fabs (fabs x)) -> (fabs x) 4178 if (N0.getOpcode() == ISD::FABS) 4179 return N->getOperand(0); 4180 // fold (fabs (fneg x)) -> (fabs x) 4181 // fold (fabs (fcopysign x, y)) -> (fabs x) 4182 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN) 4183 return DAG.getNode(ISD::FABS, VT, N0.getOperand(0)); 4184 4185 // Transform fabs(bitconvert(x)) -> bitconvert(x&~sign) to avoid loading 4186 // constant pool values. 4187 if (N0.getOpcode() == ISD::BIT_CONVERT && N0.getNode()->hasOneUse() && 4188 N0.getOperand(0).getValueType().isInteger() && 4189 !N0.getOperand(0).getValueType().isVector()) { 4190 SDValue Int = N0.getOperand(0); 4191 MVT IntVT = Int.getValueType(); 4192 if (IntVT.isInteger() && !IntVT.isVector()) { 4193 Int = DAG.getNode(ISD::AND, IntVT, Int, 4194 DAG.getConstant(~IntVT.getIntegerVTSignBit(), IntVT)); 4195 AddToWorkList(Int.getNode()); 4196 return DAG.getNode(ISD::BIT_CONVERT, N->getValueType(0), Int); 4197 } 4198 } 4199 4200 return SDValue(); 4201} 4202 4203SDValue DAGCombiner::visitBRCOND(SDNode *N) { 4204 SDValue Chain = N->getOperand(0); 4205 SDValue N1 = N->getOperand(1); 4206 SDValue N2 = N->getOperand(2); 4207 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 4208 4209 // never taken branch, fold to chain 4210 if (N1C && N1C->isNullValue()) 4211 return Chain; 4212 // unconditional branch 4213 if (N1C && N1C->getAPIntValue() == 1) 4214 return DAG.getNode(ISD::BR, MVT::Other, Chain, N2); 4215 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal 4216 // on the target. 4217 if (N1.getOpcode() == ISD::SETCC && 4218 TLI.isOperationLegal(ISD::BR_CC, MVT::Other)) { 4219 return DAG.getNode(ISD::BR_CC, MVT::Other, Chain, N1.getOperand(2), 4220 N1.getOperand(0), N1.getOperand(1), N2); 4221 } 4222 return SDValue(); 4223} 4224 4225// Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB. 4226// 4227SDValue DAGCombiner::visitBR_CC(SDNode *N) { 4228 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1)); 4229 SDValue CondLHS = N->getOperand(2), CondRHS = N->getOperand(3); 4230 4231 // Use SimplifySetCC to simplify SETCC's. 4232 SDValue Simp = SimplifySetCC(TLI.getSetCCResultType(CondLHS), 4233 CondLHS, CondRHS, CC->get(), false); 4234 if (Simp.getNode()) AddToWorkList(Simp.getNode()); 4235 4236 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(Simp.getNode()); 4237 4238 // fold br_cc true, dest -> br dest (unconditional branch) 4239 if (SCCC && !SCCC->isNullValue()) 4240 return DAG.getNode(ISD::BR, MVT::Other, N->getOperand(0), 4241 N->getOperand(4)); 4242 // fold br_cc false, dest -> unconditional fall through 4243 if (SCCC && SCCC->isNullValue()) 4244 return N->getOperand(0); 4245 4246 // fold to a simpler setcc 4247 if (Simp.getNode() && Simp.getOpcode() == ISD::SETCC) 4248 return DAG.getNode(ISD::BR_CC, MVT::Other, N->getOperand(0), 4249 Simp.getOperand(2), Simp.getOperand(0), 4250 Simp.getOperand(1), N->getOperand(4)); 4251 return SDValue(); 4252} 4253 4254 4255/// CombineToPreIndexedLoadStore - Try turning a load / store into a 4256/// pre-indexed load / store when the base pointer is an add or subtract 4257/// and it has other uses besides the load / store. After the 4258/// transformation, the new indexed load / store has effectively folded 4259/// the add / subtract in and all of its other uses are redirected to the 4260/// new load / store. 4261bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) { 4262 if (!LegalOperations) 4263 return false; 4264 4265 bool isLoad = true; 4266 SDValue Ptr; 4267 MVT VT; 4268 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 4269 if (LD->isIndexed()) 4270 return false; 4271 VT = LD->getMemoryVT(); 4272 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) && 4273 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT)) 4274 return false; 4275 Ptr = LD->getBasePtr(); 4276 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 4277 if (ST->isIndexed()) 4278 return false; 4279 VT = ST->getMemoryVT(); 4280 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) && 4281 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT)) 4282 return false; 4283 Ptr = ST->getBasePtr(); 4284 isLoad = false; 4285 } else 4286 return false; 4287 4288 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail 4289 // out. There is no reason to make this a preinc/predec. 4290 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) || 4291 Ptr.getNode()->hasOneUse()) 4292 return false; 4293 4294 // Ask the target to do addressing mode selection. 4295 SDValue BasePtr; 4296 SDValue Offset; 4297 ISD::MemIndexedMode AM = ISD::UNINDEXED; 4298 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG)) 4299 return false; 4300 // Don't create a indexed load / store with zero offset. 4301 if (isa<ConstantSDNode>(Offset) && 4302 cast<ConstantSDNode>(Offset)->isNullValue()) 4303 return false; 4304 4305 // Try turning it into a pre-indexed load / store except when: 4306 // 1) The new base ptr is a frame index. 4307 // 2) If N is a store and the new base ptr is either the same as or is a 4308 // predecessor of the value being stored. 4309 // 3) Another use of old base ptr is a predecessor of N. If ptr is folded 4310 // that would create a cycle. 4311 // 4) All uses are load / store ops that use it as old base ptr. 4312 4313 // Check #1. Preinc'ing a frame index would require copying the stack pointer 4314 // (plus the implicit offset) to a register to preinc anyway. 4315 if (isa<FrameIndexSDNode>(BasePtr)) 4316 return false; 4317 4318 // Check #2. 4319 if (!isLoad) { 4320 SDValue Val = cast<StoreSDNode>(N)->getValue(); 4321 if (Val == BasePtr || BasePtr.getNode()->isPredecessorOf(Val.getNode())) 4322 return false; 4323 } 4324 4325 // Now check for #3 and #4. 4326 bool RealUse = false; 4327 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(), 4328 E = Ptr.getNode()->use_end(); I != E; ++I) { 4329 SDNode *Use = *I; 4330 if (Use == N) 4331 continue; 4332 if (Use->isPredecessorOf(N)) 4333 return false; 4334 4335 if (!((Use->getOpcode() == ISD::LOAD && 4336 cast<LoadSDNode>(Use)->getBasePtr() == Ptr) || 4337 (Use->getOpcode() == ISD::STORE && 4338 cast<StoreSDNode>(Use)->getBasePtr() == Ptr))) 4339 RealUse = true; 4340 } 4341 if (!RealUse) 4342 return false; 4343 4344 SDValue Result; 4345 if (isLoad) 4346 Result = DAG.getIndexedLoad(SDValue(N,0), BasePtr, Offset, AM); 4347 else 4348 Result = DAG.getIndexedStore(SDValue(N,0), BasePtr, Offset, AM); 4349 ++PreIndexedNodes; 4350 ++NodesCombined; 4351 DOUT << "\nReplacing.4 "; DEBUG(N->dump(&DAG)); 4352 DOUT << "\nWith: "; DEBUG(Result.getNode()->dump(&DAG)); 4353 DOUT << '\n'; 4354 WorkListRemover DeadNodes(*this); 4355 if (isLoad) { 4356 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0), 4357 &DeadNodes); 4358 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2), 4359 &DeadNodes); 4360 } else { 4361 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1), 4362 &DeadNodes); 4363 } 4364 4365 // Finally, since the node is now dead, remove it from the graph. 4366 DAG.DeleteNode(N); 4367 4368 // Replace the uses of Ptr with uses of the updated base value. 4369 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0), 4370 &DeadNodes); 4371 removeFromWorkList(Ptr.getNode()); 4372 DAG.DeleteNode(Ptr.getNode()); 4373 4374 return true; 4375} 4376 4377/// CombineToPostIndexedLoadStore - Try to combine a load / store with a 4378/// add / sub of the base pointer node into a post-indexed load / store. 4379/// The transformation folded the add / subtract into the new indexed 4380/// load / store effectively and all of its uses are redirected to the 4381/// new load / store. 4382bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) { 4383 if (!LegalOperations) 4384 return false; 4385 4386 bool isLoad = true; 4387 SDValue Ptr; 4388 MVT VT; 4389 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 4390 if (LD->isIndexed()) 4391 return false; 4392 VT = LD->getMemoryVT(); 4393 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) && 4394 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT)) 4395 return false; 4396 Ptr = LD->getBasePtr(); 4397 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 4398 if (ST->isIndexed()) 4399 return false; 4400 VT = ST->getMemoryVT(); 4401 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) && 4402 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT)) 4403 return false; 4404 Ptr = ST->getBasePtr(); 4405 isLoad = false; 4406 } else 4407 return false; 4408 4409 if (Ptr.getNode()->hasOneUse()) 4410 return false; 4411 4412 for (SDNode::use_iterator I = Ptr.getNode()->use_begin(), 4413 E = Ptr.getNode()->use_end(); I != E; ++I) { 4414 SDNode *Op = *I; 4415 if (Op == N || 4416 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB)) 4417 continue; 4418 4419 SDValue BasePtr; 4420 SDValue Offset; 4421 ISD::MemIndexedMode AM = ISD::UNINDEXED; 4422 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) { 4423 if (Ptr == Offset) 4424 std::swap(BasePtr, Offset); 4425 if (Ptr != BasePtr) 4426 continue; 4427 // Don't create a indexed load / store with zero offset. 4428 if (isa<ConstantSDNode>(Offset) && 4429 cast<ConstantSDNode>(Offset)->isNullValue()) 4430 continue; 4431 4432 // Try turning it into a post-indexed load / store except when 4433 // 1) All uses are load / store ops that use it as base ptr. 4434 // 2) Op must be independent of N, i.e. Op is neither a predecessor 4435 // nor a successor of N. Otherwise, if Op is folded that would 4436 // create a cycle. 4437 4438 // Check for #1. 4439 bool TryNext = false; 4440 for (SDNode::use_iterator II = BasePtr.getNode()->use_begin(), 4441 EE = BasePtr.getNode()->use_end(); II != EE; ++II) { 4442 SDNode *Use = *II; 4443 if (Use == Ptr.getNode()) 4444 continue; 4445 4446 // If all the uses are load / store addresses, then don't do the 4447 // transformation. 4448 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){ 4449 bool RealUse = false; 4450 for (SDNode::use_iterator III = Use->use_begin(), 4451 EEE = Use->use_end(); III != EEE; ++III) { 4452 SDNode *UseUse = *III; 4453 if (!((UseUse->getOpcode() == ISD::LOAD && 4454 cast<LoadSDNode>(UseUse)->getBasePtr().getNode() == Use) || 4455 (UseUse->getOpcode() == ISD::STORE && 4456 cast<StoreSDNode>(UseUse)->getBasePtr().getNode() == Use))) 4457 RealUse = true; 4458 } 4459 4460 if (!RealUse) { 4461 TryNext = true; 4462 break; 4463 } 4464 } 4465 } 4466 if (TryNext) 4467 continue; 4468 4469 // Check for #2 4470 if (!Op->isPredecessorOf(N) && !N->isPredecessorOf(Op)) { 4471 SDValue Result = isLoad 4472 ? DAG.getIndexedLoad(SDValue(N,0), BasePtr, Offset, AM) 4473 : DAG.getIndexedStore(SDValue(N,0), BasePtr, Offset, AM); 4474 ++PostIndexedNodes; 4475 ++NodesCombined; 4476 DOUT << "\nReplacing.5 "; DEBUG(N->dump(&DAG)); 4477 DOUT << "\nWith: "; DEBUG(Result.getNode()->dump(&DAG)); 4478 DOUT << '\n'; 4479 WorkListRemover DeadNodes(*this); 4480 if (isLoad) { 4481 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(0), 4482 &DeadNodes); 4483 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Result.getValue(2), 4484 &DeadNodes); 4485 } else { 4486 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result.getValue(1), 4487 &DeadNodes); 4488 } 4489 4490 // Finally, since the node is now dead, remove it from the graph. 4491 DAG.DeleteNode(N); 4492 4493 // Replace the uses of Use with uses of the updated base value. 4494 DAG.ReplaceAllUsesOfValueWith(SDValue(Op, 0), 4495 Result.getValue(isLoad ? 1 : 0), 4496 &DeadNodes); 4497 removeFromWorkList(Op); 4498 DAG.DeleteNode(Op); 4499 return true; 4500 } 4501 } 4502 } 4503 return false; 4504} 4505 4506/// InferAlignment - If we can infer some alignment information from this 4507/// pointer, return it. 4508static unsigned InferAlignment(SDValue Ptr, SelectionDAG &DAG) { 4509 // If this is a direct reference to a stack slot, use information about the 4510 // stack slot's alignment. 4511 int FrameIdx = 1 << 31; 4512 int64_t FrameOffset = 0; 4513 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Ptr)) { 4514 FrameIdx = FI->getIndex(); 4515 } else if (Ptr.getOpcode() == ISD::ADD && 4516 isa<ConstantSDNode>(Ptr.getOperand(1)) && 4517 isa<FrameIndexSDNode>(Ptr.getOperand(0))) { 4518 FrameIdx = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex(); 4519 FrameOffset = Ptr.getConstantOperandVal(1); 4520 } 4521 4522 if (FrameIdx != (1 << 31)) { 4523 // FIXME: Handle FI+CST. 4524 const MachineFrameInfo &MFI = *DAG.getMachineFunction().getFrameInfo(); 4525 if (MFI.isFixedObjectIndex(FrameIdx)) { 4526 int64_t ObjectOffset = MFI.getObjectOffset(FrameIdx) + FrameOffset; 4527 4528 // The alignment of the frame index can be determined from its offset from 4529 // the incoming frame position. If the frame object is at offset 32 and 4530 // the stack is guaranteed to be 16-byte aligned, then we know that the 4531 // object is 16-byte aligned. 4532 unsigned StackAlign = DAG.getTarget().getFrameInfo()->getStackAlignment(); 4533 unsigned Align = MinAlign(ObjectOffset, StackAlign); 4534 4535 // Finally, the frame object itself may have a known alignment. Factor 4536 // the alignment + offset into a new alignment. For example, if we know 4537 // the FI is 8 byte aligned, but the pointer is 4 off, we really have a 4538 // 4-byte alignment of the resultant pointer. Likewise align 4 + 4-byte 4539 // offset = 4-byte alignment, align 4 + 1-byte offset = align 1, etc. 4540 unsigned FIInfoAlign = MinAlign(MFI.getObjectAlignment(FrameIdx), 4541 FrameOffset); 4542 return std::max(Align, FIInfoAlign); 4543 } 4544 } 4545 4546 return 0; 4547} 4548 4549SDValue DAGCombiner::visitLOAD(SDNode *N) { 4550 LoadSDNode *LD = cast<LoadSDNode>(N); 4551 SDValue Chain = LD->getChain(); 4552 SDValue Ptr = LD->getBasePtr(); 4553 4554 // Try to infer better alignment information than the load already has. 4555 if (!Fast && LD->isUnindexed()) { 4556 if (unsigned Align = InferAlignment(Ptr, DAG)) { 4557 if (Align > LD->getAlignment()) 4558 return DAG.getExtLoad(LD->getExtensionType(), LD->getValueType(0), 4559 Chain, Ptr, LD->getSrcValue(), 4560 LD->getSrcValueOffset(), LD->getMemoryVT(), 4561 LD->isVolatile(), Align); 4562 } 4563 } 4564 4565 4566 // If load is not volatile and there are no uses of the loaded value (and 4567 // the updated indexed value in case of indexed loads), change uses of the 4568 // chain value into uses of the chain input (i.e. delete the dead load). 4569 if (!LD->isVolatile()) { 4570 if (N->getValueType(1) == MVT::Other) { 4571 // Unindexed loads. 4572 if (N->hasNUsesOfValue(0, 0)) { 4573 // It's not safe to use the two value CombineTo variant here. e.g. 4574 // v1, chain2 = load chain1, loc 4575 // v2, chain3 = load chain2, loc 4576 // v3 = add v2, c 4577 // Now we replace use of chain2 with chain1. This makes the second load 4578 // isomorphic to the one we are deleting, and thus makes this load live. 4579 DOUT << "\nReplacing.6 "; DEBUG(N->dump(&DAG)); 4580 DOUT << "\nWith chain: "; DEBUG(Chain.getNode()->dump(&DAG)); 4581 DOUT << "\n"; 4582 WorkListRemover DeadNodes(*this); 4583 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), Chain, &DeadNodes); 4584 if (N->use_empty()) { 4585 removeFromWorkList(N); 4586 DAG.DeleteNode(N); 4587 } 4588 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4589 } 4590 } else { 4591 // Indexed loads. 4592 assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?"); 4593 if (N->hasNUsesOfValue(0, 0) && N->hasNUsesOfValue(0, 1)) { 4594 SDValue Undef = DAG.getNode(ISD::UNDEF, N->getValueType(0)); 4595 DOUT << "\nReplacing.6 "; DEBUG(N->dump(&DAG)); 4596 DOUT << "\nWith: "; DEBUG(Undef.getNode()->dump(&DAG)); 4597 DOUT << " and 2 other values\n"; 4598 WorkListRemover DeadNodes(*this); 4599 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Undef, &DeadNodes); 4600 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), 4601 DAG.getNode(ISD::UNDEF, N->getValueType(1)), 4602 &DeadNodes); 4603 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 2), Chain, &DeadNodes); 4604 removeFromWorkList(N); 4605 DAG.DeleteNode(N); 4606 return SDValue(N, 0); // Return N so it doesn't get rechecked! 4607 } 4608 } 4609 } 4610 4611 // If this load is directly stored, replace the load value with the stored 4612 // value. 4613 // TODO: Handle store large -> read small portion. 4614 // TODO: Handle TRUNCSTORE/LOADEXT 4615 if (LD->getExtensionType() == ISD::NON_EXTLOAD && 4616 !LD->isVolatile()) { 4617 if (ISD::isNON_TRUNCStore(Chain.getNode())) { 4618 StoreSDNode *PrevST = cast<StoreSDNode>(Chain); 4619 if (PrevST->getBasePtr() == Ptr && 4620 PrevST->getValue().getValueType() == N->getValueType(0)) 4621 return CombineTo(N, Chain.getOperand(1), Chain); 4622 } 4623 } 4624 4625 if (CombinerAA) { 4626 // Walk up chain skipping non-aliasing memory nodes. 4627 SDValue BetterChain = FindBetterChain(N, Chain); 4628 4629 // If there is a better chain. 4630 if (Chain != BetterChain) { 4631 SDValue ReplLoad; 4632 4633 // Replace the chain to void dependency. 4634 if (LD->getExtensionType() == ISD::NON_EXTLOAD) { 4635 ReplLoad = DAG.getLoad(N->getValueType(0), BetterChain, Ptr, 4636 LD->getSrcValue(), LD->getSrcValueOffset(), 4637 LD->isVolatile(), LD->getAlignment()); 4638 } else { 4639 ReplLoad = DAG.getExtLoad(LD->getExtensionType(), 4640 LD->getValueType(0), 4641 BetterChain, Ptr, LD->getSrcValue(), 4642 LD->getSrcValueOffset(), 4643 LD->getMemoryVT(), 4644 LD->isVolatile(), 4645 LD->getAlignment()); 4646 } 4647 4648 // Create token factor to keep old chain connected. 4649 SDValue Token = DAG.getNode(ISD::TokenFactor, MVT::Other, 4650 Chain, ReplLoad.getValue(1)); 4651 4652 // Replace uses with load result and token factor. Don't add users 4653 // to work list. 4654 return CombineTo(N, ReplLoad.getValue(0), Token, false); 4655 } 4656 } 4657 4658 // Try transforming N to an indexed load. 4659 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 4660 return SDValue(N, 0); 4661 4662 return SDValue(); 4663} 4664 4665 4666SDValue DAGCombiner::visitSTORE(SDNode *N) { 4667 StoreSDNode *ST = cast<StoreSDNode>(N); 4668 SDValue Chain = ST->getChain(); 4669 SDValue Value = ST->getValue(); 4670 SDValue Ptr = ST->getBasePtr(); 4671 4672 // Try to infer better alignment information than the store already has. 4673 if (!Fast && ST->isUnindexed()) { 4674 if (unsigned Align = InferAlignment(Ptr, DAG)) { 4675 if (Align > ST->getAlignment()) 4676 return DAG.getTruncStore(Chain, Value, Ptr, ST->getSrcValue(), 4677 ST->getSrcValueOffset(), ST->getMemoryVT(), 4678 ST->isVolatile(), Align); 4679 } 4680 } 4681 4682 // If this is a store of a bit convert, store the input value if the 4683 // resultant store does not need a higher alignment than the original. 4684 if (Value.getOpcode() == ISD::BIT_CONVERT && !ST->isTruncatingStore() && 4685 ST->isUnindexed()) { 4686 unsigned Align = ST->getAlignment(); 4687 MVT SVT = Value.getOperand(0).getValueType(); 4688 unsigned OrigAlign = TLI.getTargetData()-> 4689 getABITypeAlignment(SVT.getTypeForMVT()); 4690 if (Align <= OrigAlign && 4691 ((!LegalOperations && !ST->isVolatile()) || 4692 TLI.isOperationLegal(ISD::STORE, SVT))) 4693 return DAG.getStore(Chain, Value.getOperand(0), Ptr, ST->getSrcValue(), 4694 ST->getSrcValueOffset(), ST->isVolatile(), OrigAlign); 4695 } 4696 4697 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 4698 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) { 4699 // NOTE: If the original store is volatile, this transform must not increase 4700 // the number of stores. For example, on x86-32 an f64 can be stored in one 4701 // processor operation but an i64 (which is not legal) requires two. So the 4702 // transform should not be done in this case. 4703 if (Value.getOpcode() != ISD::TargetConstantFP) { 4704 SDValue Tmp; 4705 switch (CFP->getValueType(0).getSimpleVT()) { 4706 default: assert(0 && "Unknown FP type"); 4707 case MVT::f80: // We don't do this for these yet. 4708 case MVT::f128: 4709 case MVT::ppcf128: 4710 break; 4711 case MVT::f32: 4712 if (((TLI.isTypeLegal(MVT::i32) || !LegalTypes) && !LegalOperations && 4713 !ST->isVolatile()) || TLI.isOperationLegal(ISD::STORE, MVT::i32)) { 4714 Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF(). 4715 bitcastToAPInt().getZExtValue(), MVT::i32); 4716 return DAG.getStore(Chain, Tmp, Ptr, ST->getSrcValue(), 4717 ST->getSrcValueOffset(), ST->isVolatile(), 4718 ST->getAlignment()); 4719 } 4720 break; 4721 case MVT::f64: 4722 if (((TLI.isTypeLegal(MVT::i64) || !LegalTypes) && !LegalOperations && 4723 !ST->isVolatile()) || TLI.isOperationLegal(ISD::STORE, MVT::i64)) { 4724 Tmp = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt(). 4725 getZExtValue(), MVT::i64); 4726 return DAG.getStore(Chain, Tmp, Ptr, ST->getSrcValue(), 4727 ST->getSrcValueOffset(), ST->isVolatile(), 4728 ST->getAlignment()); 4729 } else if (!ST->isVolatile() && 4730 TLI.isOperationLegal(ISD::STORE, MVT::i32)) { 4731 // Many FP stores are not made apparent until after legalize, e.g. for 4732 // argument passing. Since this is so common, custom legalize the 4733 // 64-bit integer store into two 32-bit stores. 4734 uint64_t Val = CFP->getValueAPF().bitcastToAPInt().getZExtValue(); 4735 SDValue Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32); 4736 SDValue Hi = DAG.getConstant(Val >> 32, MVT::i32); 4737 if (TLI.isBigEndian()) std::swap(Lo, Hi); 4738 4739 int SVOffset = ST->getSrcValueOffset(); 4740 unsigned Alignment = ST->getAlignment(); 4741 bool isVolatile = ST->isVolatile(); 4742 4743 SDValue St0 = DAG.getStore(Chain, Lo, Ptr, ST->getSrcValue(), 4744 ST->getSrcValueOffset(), 4745 isVolatile, ST->getAlignment()); 4746 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 4747 DAG.getConstant(4, Ptr.getValueType())); 4748 SVOffset += 4; 4749 Alignment = MinAlign(Alignment, 4U); 4750 SDValue St1 = DAG.getStore(Chain, Hi, Ptr, ST->getSrcValue(), 4751 SVOffset, isVolatile, Alignment); 4752 return DAG.getNode(ISD::TokenFactor, MVT::Other, St0, St1); 4753 } 4754 break; 4755 } 4756 } 4757 } 4758 4759 if (CombinerAA) { 4760 // Walk up chain skipping non-aliasing memory nodes. 4761 SDValue BetterChain = FindBetterChain(N, Chain); 4762 4763 // If there is a better chain. 4764 if (Chain != BetterChain) { 4765 // Replace the chain to avoid dependency. 4766 SDValue ReplStore; 4767 if (ST->isTruncatingStore()) { 4768 ReplStore = DAG.getTruncStore(BetterChain, Value, Ptr, 4769 ST->getSrcValue(),ST->getSrcValueOffset(), 4770 ST->getMemoryVT(), 4771 ST->isVolatile(), ST->getAlignment()); 4772 } else { 4773 ReplStore = DAG.getStore(BetterChain, Value, Ptr, 4774 ST->getSrcValue(), ST->getSrcValueOffset(), 4775 ST->isVolatile(), ST->getAlignment()); 4776 } 4777 4778 // Create token to keep both nodes around. 4779 SDValue Token = 4780 DAG.getNode(ISD::TokenFactor, MVT::Other, Chain, ReplStore); 4781 4782 // Don't add users to work list. 4783 return CombineTo(N, Token, false); 4784 } 4785 } 4786 4787 // Try transforming N to an indexed store. 4788 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 4789 return SDValue(N, 0); 4790 4791 // FIXME: is there such a thing as a truncating indexed store? 4792 if (ST->isTruncatingStore() && ST->isUnindexed() && 4793 Value.getValueType().isInteger()) { 4794 // See if we can simplify the input to this truncstore with knowledge that 4795 // only the low bits are being used. For example: 4796 // "truncstore (or (shl x, 8), y), i8" -> "truncstore y, i8" 4797 SDValue Shorter = 4798 GetDemandedBits(Value, 4799 APInt::getLowBitsSet(Value.getValueSizeInBits(), 4800 ST->getMemoryVT().getSizeInBits())); 4801 AddToWorkList(Value.getNode()); 4802 if (Shorter.getNode()) 4803 return DAG.getTruncStore(Chain, Shorter, Ptr, ST->getSrcValue(), 4804 ST->getSrcValueOffset(), ST->getMemoryVT(), 4805 ST->isVolatile(), ST->getAlignment()); 4806 4807 // Otherwise, see if we can simplify the operation with 4808 // SimplifyDemandedBits, which only works if the value has a single use. 4809 if (SimplifyDemandedBits(Value, 4810 APInt::getLowBitsSet( 4811 Value.getValueSizeInBits(), 4812 ST->getMemoryVT().getSizeInBits()))) 4813 return SDValue(N, 0); 4814 } 4815 4816 // If this is a load followed by a store to the same location, then the store 4817 // is dead/noop. 4818 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Value)) { 4819 if (Ld->getBasePtr() == Ptr && ST->getMemoryVT() == Ld->getMemoryVT() && 4820 ST->isUnindexed() && !ST->isVolatile() && 4821 // There can't be any side effects between the load and store, such as 4822 // a call or store. 4823 Chain.reachesChainWithoutSideEffects(SDValue(Ld, 1))) { 4824 // The store is dead, remove it. 4825 return Chain; 4826 } 4827 } 4828 4829 // If this is an FP_ROUND or TRUNC followed by a store, fold this into a 4830 // truncating store. We can do this even if this is already a truncstore. 4831 if ((Value.getOpcode() == ISD::FP_ROUND || Value.getOpcode() == ISD::TRUNCATE) 4832 && Value.getNode()->hasOneUse() && ST->isUnindexed() && 4833 TLI.isTruncStoreLegal(Value.getOperand(0).getValueType(), 4834 ST->getMemoryVT())) { 4835 return DAG.getTruncStore(Chain, Value.getOperand(0), Ptr, ST->getSrcValue(), 4836 ST->getSrcValueOffset(), ST->getMemoryVT(), 4837 ST->isVolatile(), ST->getAlignment()); 4838 } 4839 4840 return SDValue(); 4841} 4842 4843SDValue DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) { 4844 SDValue InVec = N->getOperand(0); 4845 SDValue InVal = N->getOperand(1); 4846 SDValue EltNo = N->getOperand(2); 4847 4848 // If the invec is a BUILD_VECTOR and if EltNo is a constant, build a new 4849 // vector with the inserted element. 4850 if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) { 4851 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 4852 SmallVector<SDValue, 8> Ops(InVec.getNode()->op_begin(), 4853 InVec.getNode()->op_end()); 4854 if (Elt < Ops.size()) 4855 Ops[Elt] = InVal; 4856 return DAG.getNode(ISD::BUILD_VECTOR, InVec.getValueType(), 4857 &Ops[0], Ops.size()); 4858 } 4859 4860 return SDValue(); 4861} 4862 4863SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) { 4864 // (vextract (v4f32 load $addr), c) -> (f32 load $addr+c*size) 4865 // (vextract (v4f32 s2v (f32 load $addr)), c) -> (f32 load $addr+c*size) 4866 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), 0) -> (f32 load $addr) 4867 4868 // Perform only after legalization to ensure build_vector / vector_shuffle 4869 // optimizations have already been done. 4870 if (!LegalOperations) return SDValue(); 4871 4872 SDValue InVec = N->getOperand(0); 4873 SDValue EltNo = N->getOperand(1); 4874 4875 if (isa<ConstantSDNode>(EltNo)) { 4876 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 4877 bool NewLoad = false; 4878 bool BCNumEltsChanged = false; 4879 MVT VT = InVec.getValueType(); 4880 MVT EVT = VT.getVectorElementType(); 4881 MVT LVT = EVT; 4882 if (InVec.getOpcode() == ISD::BIT_CONVERT) { 4883 MVT BCVT = InVec.getOperand(0).getValueType(); 4884 if (!BCVT.isVector() || EVT.bitsGT(BCVT.getVectorElementType())) 4885 return SDValue(); 4886 if (VT.getVectorNumElements() != BCVT.getVectorNumElements()) 4887 BCNumEltsChanged = true; 4888 InVec = InVec.getOperand(0); 4889 EVT = BCVT.getVectorElementType(); 4890 NewLoad = true; 4891 } 4892 4893 LoadSDNode *LN0 = NULL; 4894 if (ISD::isNormalLoad(InVec.getNode())) 4895 LN0 = cast<LoadSDNode>(InVec); 4896 else if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR && 4897 InVec.getOperand(0).getValueType() == EVT && 4898 ISD::isNormalLoad(InVec.getOperand(0).getNode())) { 4899 LN0 = cast<LoadSDNode>(InVec.getOperand(0)); 4900 } else if (InVec.getOpcode() == ISD::VECTOR_SHUFFLE) { 4901 // (vextract (vector_shuffle (load $addr), v2, <1, u, u, u>), 1) 4902 // => 4903 // (load $addr+1*size) 4904 4905 // If the bit convert changed the number of elements, it is unsafe 4906 // to examine the mask. 4907 if (BCNumEltsChanged) 4908 return SDValue(); 4909 unsigned Idx = cast<ConstantSDNode>(InVec.getOperand(2). 4910 getOperand(Elt))->getZExtValue(); 4911 unsigned NumElems = InVec.getOperand(2).getNumOperands(); 4912 InVec = (Idx < NumElems) ? InVec.getOperand(0) : InVec.getOperand(1); 4913 if (InVec.getOpcode() == ISD::BIT_CONVERT) 4914 InVec = InVec.getOperand(0); 4915 if (ISD::isNormalLoad(InVec.getNode())) { 4916 LN0 = cast<LoadSDNode>(InVec); 4917 Elt = (Idx < NumElems) ? Idx : Idx - NumElems; 4918 } 4919 } 4920 if (!LN0 || !LN0->hasOneUse() || LN0->isVolatile()) 4921 return SDValue(); 4922 4923 unsigned Align = LN0->getAlignment(); 4924 if (NewLoad) { 4925 // Check the resultant load doesn't need a higher alignment than the 4926 // original load. 4927 unsigned NewAlign = TLI.getTargetData()-> 4928 getABITypeAlignment(LVT.getTypeForMVT()); 4929 if (NewAlign > Align || !TLI.isOperationLegal(ISD::LOAD, LVT)) 4930 return SDValue(); 4931 Align = NewAlign; 4932 } 4933 4934 SDValue NewPtr = LN0->getBasePtr(); 4935 if (Elt) { 4936 unsigned PtrOff = LVT.getSizeInBits() * Elt / 8; 4937 MVT PtrType = NewPtr.getValueType(); 4938 if (TLI.isBigEndian()) 4939 PtrOff = VT.getSizeInBits() / 8 - PtrOff; 4940 NewPtr = DAG.getNode(ISD::ADD, PtrType, NewPtr, 4941 DAG.getConstant(PtrOff, PtrType)); 4942 } 4943 return DAG.getLoad(LVT, LN0->getChain(), NewPtr, 4944 LN0->getSrcValue(), LN0->getSrcValueOffset(), 4945 LN0->isVolatile(), Align); 4946 } 4947 return SDValue(); 4948} 4949 4950 4951SDValue DAGCombiner::visitBUILD_VECTOR(SDNode *N) { 4952 unsigned NumInScalars = N->getNumOperands(); 4953 MVT VT = N->getValueType(0); 4954 unsigned NumElts = VT.getVectorNumElements(); 4955 MVT EltType = VT.getVectorElementType(); 4956 4957 // Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT 4958 // operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from 4959 // at most two distinct vectors, turn this into a shuffle node. 4960 SDValue VecIn1, VecIn2; 4961 for (unsigned i = 0; i != NumInScalars; ++i) { 4962 // Ignore undef inputs. 4963 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 4964 4965 // If this input is something other than a EXTRACT_VECTOR_ELT with a 4966 // constant index, bail out. 4967 if (N->getOperand(i).getOpcode() != ISD::EXTRACT_VECTOR_ELT || 4968 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) { 4969 VecIn1 = VecIn2 = SDValue(0, 0); 4970 break; 4971 } 4972 4973 // If the input vector type disagrees with the result of the build_vector, 4974 // we can't make a shuffle. 4975 SDValue ExtractedFromVec = N->getOperand(i).getOperand(0); 4976 if (ExtractedFromVec.getValueType() != VT) { 4977 VecIn1 = VecIn2 = SDValue(0, 0); 4978 break; 4979 } 4980 4981 // Otherwise, remember this. We allow up to two distinct input vectors. 4982 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2) 4983 continue; 4984 4985 if (VecIn1.getNode() == 0) { 4986 VecIn1 = ExtractedFromVec; 4987 } else if (VecIn2.getNode() == 0) { 4988 VecIn2 = ExtractedFromVec; 4989 } else { 4990 // Too many inputs. 4991 VecIn1 = VecIn2 = SDValue(0, 0); 4992 break; 4993 } 4994 } 4995 4996 // If everything is good, we can make a shuffle operation. 4997 if (VecIn1.getNode()) { 4998 SmallVector<SDValue, 8> BuildVecIndices; 4999 for (unsigned i = 0; i != NumInScalars; ++i) { 5000 if (N->getOperand(i).getOpcode() == ISD::UNDEF) { 5001 BuildVecIndices.push_back(DAG.getNode(ISD::UNDEF, TLI.getPointerTy())); 5002 continue; 5003 } 5004 5005 SDValue Extract = N->getOperand(i); 5006 5007 // If extracting from the first vector, just use the index directly. 5008 if (Extract.getOperand(0) == VecIn1) { 5009 BuildVecIndices.push_back(Extract.getOperand(1)); 5010 continue; 5011 } 5012 5013 // Otherwise, use InIdx + VecSize 5014 unsigned Idx = 5015 cast<ConstantSDNode>(Extract.getOperand(1))->getZExtValue(); 5016 BuildVecIndices.push_back(DAG.getIntPtrConstant(Idx+NumInScalars)); 5017 } 5018 5019 // Add count and size info. 5020 MVT BuildVecVT = MVT::getVectorVT(TLI.getPointerTy(), NumElts); 5021 if (!TLI.isTypeLegal(BuildVecVT) && LegalTypes) 5022 return SDValue(); 5023 5024 // Return the new VECTOR_SHUFFLE node. 5025 SDValue Ops[5]; 5026 Ops[0] = VecIn1; 5027 if (VecIn2.getNode()) { 5028 Ops[1] = VecIn2; 5029 } else { 5030 // Use an undef build_vector as input for the second operand. 5031 std::vector<SDValue> UnOps(NumInScalars, 5032 DAG.getNode(ISD::UNDEF, 5033 EltType)); 5034 Ops[1] = DAG.getNode(ISD::BUILD_VECTOR, VT, 5035 &UnOps[0], UnOps.size()); 5036 AddToWorkList(Ops[1].getNode()); 5037 } 5038 Ops[2] = DAG.getNode(ISD::BUILD_VECTOR, BuildVecVT, 5039 &BuildVecIndices[0], BuildVecIndices.size()); 5040 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, Ops, 3); 5041 } 5042 5043 return SDValue(); 5044} 5045 5046SDValue DAGCombiner::visitCONCAT_VECTORS(SDNode *N) { 5047 // TODO: Check to see if this is a CONCAT_VECTORS of a bunch of 5048 // EXTRACT_SUBVECTOR operations. If so, and if the EXTRACT_SUBVECTOR vector 5049 // inputs come from at most two distinct vectors, turn this into a shuffle 5050 // node. 5051 5052 // If we only have one input vector, we don't need to do any concatenation. 5053 if (N->getNumOperands() == 1) { 5054 return N->getOperand(0); 5055 } 5056 5057 return SDValue(); 5058} 5059 5060SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) { 5061 SDValue ShufMask = N->getOperand(2); 5062 unsigned NumElts = ShufMask.getNumOperands(); 5063 5064 SDValue N0 = N->getOperand(0); 5065 SDValue N1 = N->getOperand(1); 5066 5067 assert(N0.getValueType().getVectorNumElements() == NumElts && 5068 "Vector shuffle must be normalized in DAG"); 5069 5070 // If the shuffle mask is an identity operation on the LHS, return the LHS. 5071 bool isIdentity = true; 5072 for (unsigned i = 0; i != NumElts; ++i) { 5073 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF && 5074 cast<ConstantSDNode>(ShufMask.getOperand(i))->getZExtValue() != i) { 5075 isIdentity = false; 5076 break; 5077 } 5078 } 5079 if (isIdentity) return N->getOperand(0); 5080 5081 // If the shuffle mask is an identity operation on the RHS, return the RHS. 5082 isIdentity = true; 5083 for (unsigned i = 0; i != NumElts; ++i) { 5084 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF && 5085 cast<ConstantSDNode>(ShufMask.getOperand(i))->getZExtValue() != 5086 i+NumElts) { 5087 isIdentity = false; 5088 break; 5089 } 5090 } 5091 if (isIdentity) return N->getOperand(1); 5092 5093 // Check if the shuffle is a unary shuffle, i.e. one of the vectors is not 5094 // needed at all. 5095 bool isUnary = true; 5096 bool isSplat = true; 5097 int VecNum = -1; 5098 unsigned BaseIdx = 0; 5099 for (unsigned i = 0; i != NumElts; ++i) 5100 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF) { 5101 unsigned Idx=cast<ConstantSDNode>(ShufMask.getOperand(i))->getZExtValue(); 5102 int V = (Idx < NumElts) ? 0 : 1; 5103 if (VecNum == -1) { 5104 VecNum = V; 5105 BaseIdx = Idx; 5106 } else { 5107 if (BaseIdx != Idx) 5108 isSplat = false; 5109 if (VecNum != V) { 5110 isUnary = false; 5111 break; 5112 } 5113 } 5114 } 5115 5116 // Normalize unary shuffle so the RHS is undef. 5117 if (isUnary && VecNum == 1) 5118 std::swap(N0, N1); 5119 5120 // If it is a splat, check if the argument vector is a build_vector with 5121 // all scalar elements the same. 5122 if (isSplat) { 5123 SDNode *V = N0.getNode(); 5124 5125 // If this is a bit convert that changes the element type of the vector but 5126 // not the number of vector elements, look through it. Be careful not to 5127 // look though conversions that change things like v4f32 to v2f64. 5128 if (V->getOpcode() == ISD::BIT_CONVERT) { 5129 SDValue ConvInput = V->getOperand(0); 5130 if (ConvInput.getValueType().isVector() && 5131 ConvInput.getValueType().getVectorNumElements() == NumElts) 5132 V = ConvInput.getNode(); 5133 } 5134 5135 if (V->getOpcode() == ISD::BUILD_VECTOR) { 5136 unsigned NumElems = V->getNumOperands(); 5137 if (NumElems > BaseIdx) { 5138 SDValue Base; 5139 bool AllSame = true; 5140 for (unsigned i = 0; i != NumElems; ++i) { 5141 if (V->getOperand(i).getOpcode() != ISD::UNDEF) { 5142 Base = V->getOperand(i); 5143 break; 5144 } 5145 } 5146 // Splat of <u, u, u, u>, return <u, u, u, u> 5147 if (!Base.getNode()) 5148 return N0; 5149 for (unsigned i = 0; i != NumElems; ++i) { 5150 if (V->getOperand(i) != Base) { 5151 AllSame = false; 5152 break; 5153 } 5154 } 5155 // Splat of <x, x, x, x>, return <x, x, x, x> 5156 if (AllSame) 5157 return N0; 5158 } 5159 } 5160 } 5161 5162 // If it is a unary or the LHS and the RHS are the same node, turn the RHS 5163 // into an undef. 5164 if (isUnary || N0 == N1) { 5165 // Check the SHUFFLE mask, mapping any inputs from the 2nd operand into the 5166 // first operand. 5167 SmallVector<SDValue, 8> MappedOps; 5168 for (unsigned i = 0; i != NumElts; ++i) { 5169 if (ShufMask.getOperand(i).getOpcode() == ISD::UNDEF || 5170 cast<ConstantSDNode>(ShufMask.getOperand(i))->getZExtValue() < 5171 NumElts) { 5172 MappedOps.push_back(ShufMask.getOperand(i)); 5173 } else { 5174 unsigned NewIdx = 5175 cast<ConstantSDNode>(ShufMask.getOperand(i))->getZExtValue() - 5176 NumElts; 5177 MappedOps.push_back(DAG.getConstant(NewIdx, 5178 ShufMask.getOperand(i).getValueType())); 5179 } 5180 } 5181 ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMask.getValueType(), 5182 &MappedOps[0], MappedOps.size()); 5183 AddToWorkList(ShufMask.getNode()); 5184 return DAG.getNode(ISD::VECTOR_SHUFFLE, N->getValueType(0), 5185 N0, 5186 DAG.getNode(ISD::UNDEF, N->getValueType(0)), 5187 ShufMask); 5188 } 5189 5190 return SDValue(); 5191} 5192 5193/// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform 5194/// an AND to a vector_shuffle with the destination vector and a zero vector. 5195/// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==> 5196/// vector_shuffle V, Zero, <0, 4, 2, 4> 5197SDValue DAGCombiner::XformToShuffleWithZero(SDNode *N) { 5198 SDValue LHS = N->getOperand(0); 5199 SDValue RHS = N->getOperand(1); 5200 if (N->getOpcode() == ISD::AND) { 5201 if (RHS.getOpcode() == ISD::BIT_CONVERT) 5202 RHS = RHS.getOperand(0); 5203 if (RHS.getOpcode() == ISD::BUILD_VECTOR) { 5204 std::vector<SDValue> IdxOps; 5205 unsigned NumOps = RHS.getNumOperands(); 5206 unsigned NumElts = NumOps; 5207 for (unsigned i = 0; i != NumElts; ++i) { 5208 SDValue Elt = RHS.getOperand(i); 5209 if (!isa<ConstantSDNode>(Elt)) 5210 return SDValue(); 5211 else if (cast<ConstantSDNode>(Elt)->isAllOnesValue()) 5212 IdxOps.push_back(DAG.getIntPtrConstant(i)); 5213 else if (cast<ConstantSDNode>(Elt)->isNullValue()) 5214 IdxOps.push_back(DAG.getIntPtrConstant(NumElts)); 5215 else 5216 return SDValue(); 5217 } 5218 5219 // Let's see if the target supports this vector_shuffle. 5220 if (!TLI.isVectorClearMaskLegal(IdxOps, TLI.getPointerTy(), DAG)) 5221 return SDValue(); 5222 5223 // Return the new VECTOR_SHUFFLE node. 5224 MVT EVT = RHS.getValueType().getVectorElementType(); 5225 MVT VT = MVT::getVectorVT(EVT, NumElts); 5226 MVT MaskVT = MVT::getVectorVT(TLI.getPointerTy(), NumElts); 5227 std::vector<SDValue> Ops; 5228 LHS = DAG.getNode(ISD::BIT_CONVERT, VT, LHS); 5229 Ops.push_back(LHS); 5230 AddToWorkList(LHS.getNode()); 5231 std::vector<SDValue> ZeroOps(NumElts, DAG.getConstant(0, EVT)); 5232 Ops.push_back(DAG.getNode(ISD::BUILD_VECTOR, VT, 5233 &ZeroOps[0], ZeroOps.size())); 5234 Ops.push_back(DAG.getNode(ISD::BUILD_VECTOR, MaskVT, 5235 &IdxOps[0], IdxOps.size())); 5236 SDValue Result = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, 5237 &Ops[0], Ops.size()); 5238 if (VT != N->getValueType(0)) 5239 Result = DAG.getNode(ISD::BIT_CONVERT, N->getValueType(0), Result); 5240 return Result; 5241 } 5242 } 5243 return SDValue(); 5244} 5245 5246/// SimplifyVBinOp - Visit a binary vector operation, like ADD. 5247SDValue DAGCombiner::SimplifyVBinOp(SDNode *N) { 5248 // After legalize, the target may be depending on adds and other 5249 // binary ops to provide legal ways to construct constants or other 5250 // things. Simplifying them may result in a loss of legality. 5251 if (LegalOperations) return SDValue(); 5252 5253 MVT VT = N->getValueType(0); 5254 assert(VT.isVector() && "SimplifyVBinOp only works on vectors!"); 5255 5256 MVT EltType = VT.getVectorElementType(); 5257 SDValue LHS = N->getOperand(0); 5258 SDValue RHS = N->getOperand(1); 5259 SDValue Shuffle = XformToShuffleWithZero(N); 5260 if (Shuffle.getNode()) return Shuffle; 5261 5262 // If the LHS and RHS are BUILD_VECTOR nodes, see if we can constant fold 5263 // this operation. 5264 if (LHS.getOpcode() == ISD::BUILD_VECTOR && 5265 RHS.getOpcode() == ISD::BUILD_VECTOR) { 5266 SmallVector<SDValue, 8> Ops; 5267 for (unsigned i = 0, e = LHS.getNumOperands(); i != e; ++i) { 5268 SDValue LHSOp = LHS.getOperand(i); 5269 SDValue RHSOp = RHS.getOperand(i); 5270 // If these two elements can't be folded, bail out. 5271 if ((LHSOp.getOpcode() != ISD::UNDEF && 5272 LHSOp.getOpcode() != ISD::Constant && 5273 LHSOp.getOpcode() != ISD::ConstantFP) || 5274 (RHSOp.getOpcode() != ISD::UNDEF && 5275 RHSOp.getOpcode() != ISD::Constant && 5276 RHSOp.getOpcode() != ISD::ConstantFP)) 5277 break; 5278 // Can't fold divide by zero. 5279 if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV || 5280 N->getOpcode() == ISD::FDIV) { 5281 if ((RHSOp.getOpcode() == ISD::Constant && 5282 cast<ConstantSDNode>(RHSOp.getNode())->isNullValue()) || 5283 (RHSOp.getOpcode() == ISD::ConstantFP && 5284 cast<ConstantFPSDNode>(RHSOp.getNode())->getValueAPF().isZero())) 5285 break; 5286 } 5287 Ops.push_back(DAG.getNode(N->getOpcode(), EltType, LHSOp, RHSOp)); 5288 AddToWorkList(Ops.back().getNode()); 5289 assert((Ops.back().getOpcode() == ISD::UNDEF || 5290 Ops.back().getOpcode() == ISD::Constant || 5291 Ops.back().getOpcode() == ISD::ConstantFP) && 5292 "Scalar binop didn't fold!"); 5293 } 5294 5295 if (Ops.size() == LHS.getNumOperands()) { 5296 MVT VT = LHS.getValueType(); 5297 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 5298 } 5299 } 5300 5301 return SDValue(); 5302} 5303 5304SDValue DAGCombiner::SimplifySelect(SDValue N0, SDValue N1, SDValue N2){ 5305 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!"); 5306 5307 SDValue SCC = SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), N1, N2, 5308 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 5309 // If we got a simplified select_cc node back from SimplifySelectCC, then 5310 // break it down into a new SETCC node, and a new SELECT node, and then return 5311 // the SELECT node, since we were called with a SELECT node. 5312 if (SCC.getNode()) { 5313 // Check to see if we got a select_cc back (to turn into setcc/select). 5314 // Otherwise, just return whatever node we got back, like fabs. 5315 if (SCC.getOpcode() == ISD::SELECT_CC) { 5316 SDValue SETCC = DAG.getNode(ISD::SETCC, N0.getValueType(), 5317 SCC.getOperand(0), SCC.getOperand(1), 5318 SCC.getOperand(4)); 5319 AddToWorkList(SETCC.getNode()); 5320 return DAG.getNode(ISD::SELECT, SCC.getValueType(), SCC.getOperand(2), 5321 SCC.getOperand(3), SETCC); 5322 } 5323 return SCC; 5324 } 5325 return SDValue(); 5326} 5327 5328/// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS 5329/// are the two values being selected between, see if we can simplify the 5330/// select. Callers of this should assume that TheSelect is deleted if this 5331/// returns true. As such, they should return the appropriate thing (e.g. the 5332/// node) back to the top-level of the DAG combiner loop to avoid it being 5333/// looked at. 5334/// 5335bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDValue LHS, 5336 SDValue RHS) { 5337 5338 // If this is a select from two identical things, try to pull the operation 5339 // through the select. 5340 if (LHS.getOpcode() == RHS.getOpcode() && LHS.hasOneUse() && RHS.hasOneUse()){ 5341 // If this is a load and the token chain is identical, replace the select 5342 // of two loads with a load through a select of the address to load from. 5343 // This triggers in things like "select bool X, 10.0, 123.0" after the FP 5344 // constants have been dropped into the constant pool. 5345 if (LHS.getOpcode() == ISD::LOAD && 5346 // Do not let this transformation reduce the number of volatile loads. 5347 !cast<LoadSDNode>(LHS)->isVolatile() && 5348 !cast<LoadSDNode>(RHS)->isVolatile() && 5349 // Token chains must be identical. 5350 LHS.getOperand(0) == RHS.getOperand(0)) { 5351 LoadSDNode *LLD = cast<LoadSDNode>(LHS); 5352 LoadSDNode *RLD = cast<LoadSDNode>(RHS); 5353 5354 // If this is an EXTLOAD, the VT's must match. 5355 if (LLD->getMemoryVT() == RLD->getMemoryVT()) { 5356 // FIXME: this conflates two src values, discarding one. This is not 5357 // the right thing to do, but nothing uses srcvalues now. When they do, 5358 // turn SrcValue into a list of locations. 5359 SDValue Addr; 5360 if (TheSelect->getOpcode() == ISD::SELECT) { 5361 // Check that the condition doesn't reach either load. If so, folding 5362 // this will induce a cycle into the DAG. 5363 if (!LLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) && 5364 !RLD->isPredecessorOf(TheSelect->getOperand(0).getNode())) { 5365 Addr = DAG.getNode(ISD::SELECT, LLD->getBasePtr().getValueType(), 5366 TheSelect->getOperand(0), LLD->getBasePtr(), 5367 RLD->getBasePtr()); 5368 } 5369 } else { 5370 // Check that the condition doesn't reach either load. If so, folding 5371 // this will induce a cycle into the DAG. 5372 if (!LLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) && 5373 !RLD->isPredecessorOf(TheSelect->getOperand(0).getNode()) && 5374 !LLD->isPredecessorOf(TheSelect->getOperand(1).getNode()) && 5375 !RLD->isPredecessorOf(TheSelect->getOperand(1).getNode())) { 5376 Addr = DAG.getNode(ISD::SELECT_CC, LLD->getBasePtr().getValueType(), 5377 TheSelect->getOperand(0), 5378 TheSelect->getOperand(1), 5379 LLD->getBasePtr(), RLD->getBasePtr(), 5380 TheSelect->getOperand(4)); 5381 } 5382 } 5383 5384 if (Addr.getNode()) { 5385 SDValue Load; 5386 if (LLD->getExtensionType() == ISD::NON_EXTLOAD) 5387 Load = DAG.getLoad(TheSelect->getValueType(0), LLD->getChain(), 5388 Addr,LLD->getSrcValue(), 5389 LLD->getSrcValueOffset(), 5390 LLD->isVolatile(), 5391 LLD->getAlignment()); 5392 else { 5393 Load = DAG.getExtLoad(LLD->getExtensionType(), 5394 TheSelect->getValueType(0), 5395 LLD->getChain(), Addr, LLD->getSrcValue(), 5396 LLD->getSrcValueOffset(), 5397 LLD->getMemoryVT(), 5398 LLD->isVolatile(), 5399 LLD->getAlignment()); 5400 } 5401 // Users of the select now use the result of the load. 5402 CombineTo(TheSelect, Load); 5403 5404 // Users of the old loads now use the new load's chain. We know the 5405 // old-load value is dead now. 5406 CombineTo(LHS.getNode(), Load.getValue(0), Load.getValue(1)); 5407 CombineTo(RHS.getNode(), Load.getValue(0), Load.getValue(1)); 5408 return true; 5409 } 5410 } 5411 } 5412 } 5413 5414 return false; 5415} 5416 5417SDValue DAGCombiner::SimplifySelectCC(SDValue N0, SDValue N1, 5418 SDValue N2, SDValue N3, 5419 ISD::CondCode CC, bool NotExtCompare) { 5420 5421 MVT VT = N2.getValueType(); 5422 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode()); 5423 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode()); 5424 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.getNode()); 5425 5426 // Determine if the condition we're dealing with is constant 5427 SDValue SCC = SimplifySetCC(TLI.getSetCCResultType(N0), N0, N1, CC, false); 5428 if (SCC.getNode()) AddToWorkList(SCC.getNode()); 5429 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode()); 5430 5431 // fold select_cc true, x, y -> x 5432 if (SCCC && !SCCC->isNullValue()) 5433 return N2; 5434 // fold select_cc false, x, y -> y 5435 if (SCCC && SCCC->isNullValue()) 5436 return N3; 5437 5438 // Check to see if we can simplify the select into an fabs node 5439 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) { 5440 // Allow either -0.0 or 0.0 5441 if (CFP->getValueAPF().isZero()) { 5442 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs 5443 if ((CC == ISD::SETGE || CC == ISD::SETGT) && 5444 N0 == N2 && N3.getOpcode() == ISD::FNEG && 5445 N2 == N3.getOperand(0)) 5446 return DAG.getNode(ISD::FABS, VT, N0); 5447 5448 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs 5449 if ((CC == ISD::SETLT || CC == ISD::SETLE) && 5450 N0 == N3 && N2.getOpcode() == ISD::FNEG && 5451 N2.getOperand(0) == N3) 5452 return DAG.getNode(ISD::FABS, VT, N3); 5453 } 5454 } 5455 5456 // Check to see if we can perform the "gzip trick", transforming 5457 // select_cc setlt X, 0, A, 0 -> and (sra X, size(X)-1), A 5458 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT && 5459 N0.getValueType().isInteger() && 5460 N2.getValueType().isInteger() && 5461 (N1C->isNullValue() || // (a < 0) ? b : 0 5462 (N1C->getAPIntValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0 5463 MVT XType = N0.getValueType(); 5464 MVT AType = N2.getValueType(); 5465 if (XType.bitsGE(AType)) { 5466 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a 5467 // single-bit constant. 5468 if (N2C && ((N2C->getAPIntValue() & (N2C->getAPIntValue()-1)) == 0)) { 5469 unsigned ShCtV = N2C->getAPIntValue().logBase2(); 5470 ShCtV = XType.getSizeInBits()-ShCtV-1; 5471 SDValue ShCt = DAG.getConstant(ShCtV, TLI.getShiftAmountTy()); 5472 SDValue Shift = DAG.getNode(ISD::SRL, XType, N0, ShCt); 5473 AddToWorkList(Shift.getNode()); 5474 if (XType.bitsGT(AType)) { 5475 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift); 5476 AddToWorkList(Shift.getNode()); 5477 } 5478 return DAG.getNode(ISD::AND, AType, Shift, N2); 5479 } 5480 SDValue Shift = DAG.getNode(ISD::SRA, XType, N0, 5481 DAG.getConstant(XType.getSizeInBits()-1, 5482 TLI.getShiftAmountTy())); 5483 AddToWorkList(Shift.getNode()); 5484 if (XType.bitsGT(AType)) { 5485 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift); 5486 AddToWorkList(Shift.getNode()); 5487 } 5488 return DAG.getNode(ISD::AND, AType, Shift, N2); 5489 } 5490 } 5491 5492 // fold select C, 16, 0 -> shl C, 4 5493 if (N2C && N3C && N3C->isNullValue() && N2C->getAPIntValue().isPowerOf2() && 5494 TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent) { 5495 5496 // If the caller doesn't want us to simplify this into a zext of a compare, 5497 // don't do it. 5498 if (NotExtCompare && N2C->getAPIntValue() == 1) 5499 return SDValue(); 5500 5501 // Get a SetCC of the condition 5502 // FIXME: Should probably make sure that setcc is legal if we ever have a 5503 // target where it isn't. 5504 SDValue Temp, SCC; 5505 // cast from setcc result type to select result type 5506 if (LegalTypes) { 5507 SCC = DAG.getSetCC(TLI.getSetCCResultType(N0), N0, N1, CC); 5508 if (N2.getValueType().bitsLT(SCC.getValueType())) 5509 Temp = DAG.getZeroExtendInReg(SCC, N2.getValueType()); 5510 else 5511 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC); 5512 } else { 5513 SCC = DAG.getSetCC(MVT::i1, N0, N1, CC); 5514 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC); 5515 } 5516 AddToWorkList(SCC.getNode()); 5517 AddToWorkList(Temp.getNode()); 5518 5519 if (N2C->getAPIntValue() == 1) 5520 return Temp; 5521 // shl setcc result by log2 n2c 5522 return DAG.getNode(ISD::SHL, N2.getValueType(), Temp, 5523 DAG.getConstant(N2C->getAPIntValue().logBase2(), 5524 TLI.getShiftAmountTy())); 5525 } 5526 5527 // Check to see if this is the equivalent of setcc 5528 // FIXME: Turn all of these into setcc if setcc if setcc is legal 5529 // otherwise, go ahead with the folds. 5530 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getAPIntValue() == 1ULL)) { 5531 MVT XType = N0.getValueType(); 5532 if (!LegalOperations || 5533 TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(N0))) { 5534 SDValue Res = DAG.getSetCC(TLI.getSetCCResultType(N0), N0, N1, CC); 5535 if (Res.getValueType() != VT) 5536 Res = DAG.getNode(ISD::ZERO_EXTEND, VT, Res); 5537 return Res; 5538 } 5539 5540 // seteq X, 0 -> srl (ctlz X, log2(size(X))) 5541 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ && 5542 (!LegalOperations || 5543 TLI.isOperationLegal(ISD::CTLZ, XType))) { 5544 SDValue Ctlz = DAG.getNode(ISD::CTLZ, XType, N0); 5545 return DAG.getNode(ISD::SRL, XType, Ctlz, 5546 DAG.getConstant(Log2_32(XType.getSizeInBits()), 5547 TLI.getShiftAmountTy())); 5548 } 5549 // setgt X, 0 -> srl (and (-X, ~X), size(X)-1) 5550 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) { 5551 SDValue NegN0 = DAG.getNode(ISD::SUB, XType, DAG.getConstant(0, XType), 5552 N0); 5553 SDValue NotN0 = DAG.getNode(ISD::XOR, XType, N0, 5554 DAG.getConstant(~0ULL, XType)); 5555 return DAG.getNode(ISD::SRL, XType, 5556 DAG.getNode(ISD::AND, XType, NegN0, NotN0), 5557 DAG.getConstant(XType.getSizeInBits()-1, 5558 TLI.getShiftAmountTy())); 5559 } 5560 // setgt X, -1 -> xor (srl (X, size(X)-1), 1) 5561 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) { 5562 SDValue Sign = DAG.getNode(ISD::SRL, XType, N0, 5563 DAG.getConstant(XType.getSizeInBits()-1, 5564 TLI.getShiftAmountTy())); 5565 return DAG.getNode(ISD::XOR, XType, Sign, DAG.getConstant(1, XType)); 5566 } 5567 } 5568 5569 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X -> 5570 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 5571 if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) && 5572 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1) && 5573 N2.getOperand(0) == N1 && N0.getValueType().isInteger()) { 5574 MVT XType = N0.getValueType(); 5575 SDValue Shift = DAG.getNode(ISD::SRA, XType, N0, 5576 DAG.getConstant(XType.getSizeInBits()-1, 5577 TLI.getShiftAmountTy())); 5578 SDValue Add = DAG.getNode(ISD::ADD, XType, N0, Shift); 5579 AddToWorkList(Shift.getNode()); 5580 AddToWorkList(Add.getNode()); 5581 return DAG.getNode(ISD::XOR, XType, Add, Shift); 5582 } 5583 // Check to see if this is an integer abs. select_cc setgt X, -1, X, -X -> 5584 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 5585 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT && 5586 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1)) { 5587 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0))) { 5588 MVT XType = N0.getValueType(); 5589 if (SubC->isNullValue() && XType.isInteger()) { 5590 SDValue Shift = DAG.getNode(ISD::SRA, XType, N0, 5591 DAG.getConstant(XType.getSizeInBits()-1, 5592 TLI.getShiftAmountTy())); 5593 SDValue Add = DAG.getNode(ISD::ADD, XType, N0, Shift); 5594 AddToWorkList(Shift.getNode()); 5595 AddToWorkList(Add.getNode()); 5596 return DAG.getNode(ISD::XOR, XType, Add, Shift); 5597 } 5598 } 5599 } 5600 5601 return SDValue(); 5602} 5603 5604/// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC. 5605SDValue DAGCombiner::SimplifySetCC(MVT VT, SDValue N0, 5606 SDValue N1, ISD::CondCode Cond, 5607 bool foldBooleans) { 5608 TargetLowering::DAGCombinerInfo 5609 DagCombineInfo(DAG, Level == Unrestricted, false, this); 5610 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo); 5611} 5612 5613/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 5614/// return a DAG expression to select that will generate the same value by 5615/// multiplying by a magic number. See: 5616/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 5617SDValue DAGCombiner::BuildSDIV(SDNode *N) { 5618 std::vector<SDNode*> Built; 5619 SDValue S = TLI.BuildSDIV(N, DAG, &Built); 5620 5621 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 5622 ii != ee; ++ii) 5623 AddToWorkList(*ii); 5624 return S; 5625} 5626 5627/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 5628/// return a DAG expression to select that will generate the same value by 5629/// multiplying by a magic number. See: 5630/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 5631SDValue DAGCombiner::BuildUDIV(SDNode *N) { 5632 std::vector<SDNode*> Built; 5633 SDValue S = TLI.BuildUDIV(N, DAG, &Built); 5634 5635 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 5636 ii != ee; ++ii) 5637 AddToWorkList(*ii); 5638 return S; 5639} 5640 5641/// FindBaseOffset - Return true if base is known not to alias with anything 5642/// but itself. Provides base object and offset as results. 5643static bool FindBaseOffset(SDValue Ptr, SDValue &Base, int64_t &Offset) { 5644 // Assume it is a primitive operation. 5645 Base = Ptr; Offset = 0; 5646 5647 // If it's an adding a simple constant then integrate the offset. 5648 if (Base.getOpcode() == ISD::ADD) { 5649 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) { 5650 Base = Base.getOperand(0); 5651 Offset += C->getZExtValue(); 5652 } 5653 } 5654 5655 // If it's any of the following then it can't alias with anything but itself. 5656 return isa<FrameIndexSDNode>(Base) || 5657 isa<ConstantPoolSDNode>(Base) || 5658 isa<GlobalAddressSDNode>(Base); 5659} 5660 5661/// isAlias - Return true if there is any possibility that the two addresses 5662/// overlap. 5663bool DAGCombiner::isAlias(SDValue Ptr1, int64_t Size1, 5664 const Value *SrcValue1, int SrcValueOffset1, 5665 SDValue Ptr2, int64_t Size2, 5666 const Value *SrcValue2, int SrcValueOffset2) 5667{ 5668 // If they are the same then they must be aliases. 5669 if (Ptr1 == Ptr2) return true; 5670 5671 // Gather base node and offset information. 5672 SDValue Base1, Base2; 5673 int64_t Offset1, Offset2; 5674 bool KnownBase1 = FindBaseOffset(Ptr1, Base1, Offset1); 5675 bool KnownBase2 = FindBaseOffset(Ptr2, Base2, Offset2); 5676 5677 // If they have a same base address then... 5678 if (Base1 == Base2) { 5679 // Check to see if the addresses overlap. 5680 return!((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1); 5681 } 5682 5683 // If we know both bases then they can't alias. 5684 if (KnownBase1 && KnownBase2) return false; 5685 5686 if (CombinerGlobalAA) { 5687 // Use alias analysis information. 5688 int64_t MinOffset = std::min(SrcValueOffset1, SrcValueOffset2); 5689 int64_t Overlap1 = Size1 + SrcValueOffset1 - MinOffset; 5690 int64_t Overlap2 = Size2 + SrcValueOffset2 - MinOffset; 5691 AliasAnalysis::AliasResult AAResult = 5692 AA.alias(SrcValue1, Overlap1, SrcValue2, Overlap2); 5693 if (AAResult == AliasAnalysis::NoAlias) 5694 return false; 5695 } 5696 5697 // Otherwise we have to assume they alias. 5698 return true; 5699} 5700 5701/// FindAliasInfo - Extracts the relevant alias information from the memory 5702/// node. Returns true if the operand was a load. 5703bool DAGCombiner::FindAliasInfo(SDNode *N, 5704 SDValue &Ptr, int64_t &Size, 5705 const Value *&SrcValue, int &SrcValueOffset) { 5706 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 5707 Ptr = LD->getBasePtr(); 5708 Size = LD->getMemoryVT().getSizeInBits() >> 3; 5709 SrcValue = LD->getSrcValue(); 5710 SrcValueOffset = LD->getSrcValueOffset(); 5711 return true; 5712 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 5713 Ptr = ST->getBasePtr(); 5714 Size = ST->getMemoryVT().getSizeInBits() >> 3; 5715 SrcValue = ST->getSrcValue(); 5716 SrcValueOffset = ST->getSrcValueOffset(); 5717 } else { 5718 assert(0 && "FindAliasInfo expected a memory operand"); 5719 } 5720 5721 return false; 5722} 5723 5724/// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 5725/// looking for aliasing nodes and adding them to the Aliases vector. 5726void DAGCombiner::GatherAllAliases(SDNode *N, SDValue OriginalChain, 5727 SmallVector<SDValue, 8> &Aliases) { 5728 SmallVector<SDValue, 8> Chains; // List of chains to visit. 5729 std::set<SDNode *> Visited; // Visited node set. 5730 5731 // Get alias information for node. 5732 SDValue Ptr; 5733 int64_t Size; 5734 const Value *SrcValue; 5735 int SrcValueOffset; 5736 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset); 5737 5738 // Starting off. 5739 Chains.push_back(OriginalChain); 5740 5741 // Look at each chain and determine if it is an alias. If so, add it to the 5742 // aliases list. If not, then continue up the chain looking for the next 5743 // candidate. 5744 while (!Chains.empty()) { 5745 SDValue Chain = Chains.back(); 5746 Chains.pop_back(); 5747 5748 // Don't bother if we've been before. 5749 if (Visited.find(Chain.getNode()) != Visited.end()) continue; 5750 Visited.insert(Chain.getNode()); 5751 5752 switch (Chain.getOpcode()) { 5753 case ISD::EntryToken: 5754 // Entry token is ideal chain operand, but handled in FindBetterChain. 5755 break; 5756 5757 case ISD::LOAD: 5758 case ISD::STORE: { 5759 // Get alias information for Chain. 5760 SDValue OpPtr; 5761 int64_t OpSize; 5762 const Value *OpSrcValue; 5763 int OpSrcValueOffset; 5764 bool IsOpLoad = FindAliasInfo(Chain.getNode(), OpPtr, OpSize, 5765 OpSrcValue, OpSrcValueOffset); 5766 5767 // If chain is alias then stop here. 5768 if (!(IsLoad && IsOpLoad) && 5769 isAlias(Ptr, Size, SrcValue, SrcValueOffset, 5770 OpPtr, OpSize, OpSrcValue, OpSrcValueOffset)) { 5771 Aliases.push_back(Chain); 5772 } else { 5773 // Look further up the chain. 5774 Chains.push_back(Chain.getOperand(0)); 5775 // Clean up old chain. 5776 AddToWorkList(Chain.getNode()); 5777 } 5778 break; 5779 } 5780 5781 case ISD::TokenFactor: 5782 // We have to check each of the operands of the token factor, so we queue 5783 // then up. Adding the operands to the queue (stack) in reverse order 5784 // maintains the original order and increases the likelihood that getNode 5785 // will find a matching token factor (CSE.) 5786 for (unsigned n = Chain.getNumOperands(); n;) 5787 Chains.push_back(Chain.getOperand(--n)); 5788 // Eliminate the token factor if we can. 5789 AddToWorkList(Chain.getNode()); 5790 break; 5791 5792 default: 5793 // For all other instructions we will just have to take what we can get. 5794 Aliases.push_back(Chain); 5795 break; 5796 } 5797 } 5798} 5799 5800/// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking 5801/// for a better chain (aliasing node.) 5802SDValue DAGCombiner::FindBetterChain(SDNode *N, SDValue OldChain) { 5803 SmallVector<SDValue, 8> Aliases; // Ops for replacing token factor. 5804 5805 // Accumulate all the aliases to this node. 5806 GatherAllAliases(N, OldChain, Aliases); 5807 5808 if (Aliases.size() == 0) { 5809 // If no operands then chain to entry token. 5810 return DAG.getEntryNode(); 5811 } else if (Aliases.size() == 1) { 5812 // If a single operand then chain to it. We don't need to revisit it. 5813 return Aliases[0]; 5814 } 5815 5816 // Construct a custom tailored token factor. 5817 SDValue NewChain = DAG.getNode(ISD::TokenFactor, MVT::Other, 5818 &Aliases[0], Aliases.size()); 5819 5820 // Make sure the old chain gets cleaned up. 5821 if (NewChain != OldChain) AddToWorkList(OldChain.getNode()); 5822 5823 return NewChain; 5824} 5825 5826// SelectionDAG::Combine - This is the entry point for the file. 5827// 5828void SelectionDAG::Combine(CombineLevel Level, AliasAnalysis &AA, bool Fast) { 5829 /// run - This is the main entry point to this class. 5830 /// 5831 DAGCombiner(*this, AA, Fast).Run(Level); 5832} 5833