DAGCombiner.cpp revision fec42eb6daff7e8b644bd24cbf12f83d6b14bd8b
1//===-- DAGCombiner.cpp - Implement a DAG node combiner -------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This pass combines dag nodes to form fewer, simpler DAG nodes. It can be run 11// both before and after the DAG is legalized. 12// 13//===----------------------------------------------------------------------===// 14 15#define DEBUG_TYPE "dagcombine" 16#include "llvm/CodeGen/SelectionDAG.h" 17#include "llvm/CodeGen/MachineFunction.h" 18#include "llvm/CodeGen/MachineFrameInfo.h" 19#include "llvm/Analysis/AliasAnalysis.h" 20#include "llvm/Target/TargetData.h" 21#include "llvm/Target/TargetFrameInfo.h" 22#include "llvm/Target/TargetLowering.h" 23#include "llvm/Target/TargetMachine.h" 24#include "llvm/Target/TargetOptions.h" 25#include "llvm/ADT/SmallPtrSet.h" 26#include "llvm/ADT/Statistic.h" 27#include "llvm/Support/Compiler.h" 28#include "llvm/Support/CommandLine.h" 29#include "llvm/Support/Debug.h" 30#include "llvm/Support/MathExtras.h" 31#include <algorithm> 32using namespace llvm; 33 34STATISTIC(NodesCombined , "Number of dag nodes combined"); 35STATISTIC(PreIndexedNodes , "Number of pre-indexed nodes created"); 36STATISTIC(PostIndexedNodes, "Number of post-indexed nodes created"); 37 38namespace { 39#ifndef NDEBUG 40 static cl::opt<bool> 41 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden, 42 cl::desc("Pop up a window to show dags before the first " 43 "dag combine pass")); 44 static cl::opt<bool> 45 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden, 46 cl::desc("Pop up a window to show dags before the second " 47 "dag combine pass")); 48#else 49 static const bool ViewDAGCombine1 = false; 50 static const bool ViewDAGCombine2 = false; 51#endif 52 53 static cl::opt<bool> 54 CombinerAA("combiner-alias-analysis", cl::Hidden, 55 cl::desc("Turn on alias analysis during testing")); 56 57 static cl::opt<bool> 58 CombinerGlobalAA("combiner-global-alias-analysis", cl::Hidden, 59 cl::desc("Include global information in alias analysis")); 60 61//------------------------------ DAGCombiner ---------------------------------// 62 63 class VISIBILITY_HIDDEN DAGCombiner { 64 SelectionDAG &DAG; 65 TargetLowering &TLI; 66 bool AfterLegalize; 67 68 // Worklist of all of the nodes that need to be simplified. 69 std::vector<SDNode*> WorkList; 70 71 // AA - Used for DAG load/store alias analysis. 72 AliasAnalysis &AA; 73 74 /// AddUsersToWorkList - When an instruction is simplified, add all users of 75 /// the instruction to the work lists because they might get more simplified 76 /// now. 77 /// 78 void AddUsersToWorkList(SDNode *N) { 79 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 80 UI != UE; ++UI) 81 AddToWorkList(*UI); 82 } 83 84 /// visit - call the node-specific routine that knows how to fold each 85 /// particular type of node. 86 SDOperand visit(SDNode *N); 87 88 public: 89 /// AddToWorkList - Add to the work list making sure it's instance is at the 90 /// the back (next to be processed.) 91 void AddToWorkList(SDNode *N) { 92 removeFromWorkList(N); 93 WorkList.push_back(N); 94 } 95 96 /// removeFromWorkList - remove all instances of N from the worklist. 97 /// 98 void removeFromWorkList(SDNode *N) { 99 WorkList.erase(std::remove(WorkList.begin(), WorkList.end(), N), 100 WorkList.end()); 101 } 102 103 SDOperand CombineTo(SDNode *N, const SDOperand *To, unsigned NumTo, 104 bool AddTo = true); 105 106 SDOperand CombineTo(SDNode *N, SDOperand Res, bool AddTo = true) { 107 return CombineTo(N, &Res, 1, AddTo); 108 } 109 110 SDOperand CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1, 111 bool AddTo = true) { 112 SDOperand To[] = { Res0, Res1 }; 113 return CombineTo(N, To, 2, AddTo); 114 } 115 116 private: 117 118 /// SimplifyDemandedBits - Check the specified integer node value to see if 119 /// it can be simplified or if things it uses can be simplified by bit 120 /// propagation. If so, return true. 121 bool SimplifyDemandedBits(SDOperand Op, uint64_t Demanded = ~0ULL); 122 123 bool CombineToPreIndexedLoadStore(SDNode *N); 124 bool CombineToPostIndexedLoadStore(SDNode *N); 125 126 127 /// combine - call the node-specific routine that knows how to fold each 128 /// particular type of node. If that doesn't do anything, try the 129 /// target-specific DAG combines. 130 SDOperand combine(SDNode *N); 131 132 // Visitation implementation - Implement dag node combining for different 133 // node types. The semantics are as follows: 134 // Return Value: 135 // SDOperand.Val == 0 - No change was made 136 // SDOperand.Val == N - N was replaced, is dead, and is already handled. 137 // otherwise - N should be replaced by the returned Operand. 138 // 139 SDOperand visitTokenFactor(SDNode *N); 140 SDOperand visitMERGE_VALUES(SDNode *N); 141 SDOperand visitADD(SDNode *N); 142 SDOperand visitSUB(SDNode *N); 143 SDOperand visitADDC(SDNode *N); 144 SDOperand visitADDE(SDNode *N); 145 SDOperand visitMUL(SDNode *N); 146 SDOperand visitSDIV(SDNode *N); 147 SDOperand visitUDIV(SDNode *N); 148 SDOperand visitSREM(SDNode *N); 149 SDOperand visitUREM(SDNode *N); 150 SDOperand visitMULHU(SDNode *N); 151 SDOperand visitMULHS(SDNode *N); 152 SDOperand visitSMUL_LOHI(SDNode *N); 153 SDOperand visitUMUL_LOHI(SDNode *N); 154 SDOperand visitSDIVREM(SDNode *N); 155 SDOperand visitUDIVREM(SDNode *N); 156 SDOperand visitAND(SDNode *N); 157 SDOperand visitOR(SDNode *N); 158 SDOperand visitXOR(SDNode *N); 159 SDOperand SimplifyVBinOp(SDNode *N); 160 SDOperand visitSHL(SDNode *N); 161 SDOperand visitSRA(SDNode *N); 162 SDOperand visitSRL(SDNode *N); 163 SDOperand visitCTLZ(SDNode *N); 164 SDOperand visitCTTZ(SDNode *N); 165 SDOperand visitCTPOP(SDNode *N); 166 SDOperand visitSELECT(SDNode *N); 167 SDOperand visitSELECT_CC(SDNode *N); 168 SDOperand visitSETCC(SDNode *N); 169 SDOperand visitSIGN_EXTEND(SDNode *N); 170 SDOperand visitZERO_EXTEND(SDNode *N); 171 SDOperand visitANY_EXTEND(SDNode *N); 172 SDOperand visitSIGN_EXTEND_INREG(SDNode *N); 173 SDOperand visitTRUNCATE(SDNode *N); 174 SDOperand visitBIT_CONVERT(SDNode *N); 175 SDOperand visitFADD(SDNode *N); 176 SDOperand visitFSUB(SDNode *N); 177 SDOperand visitFMUL(SDNode *N); 178 SDOperand visitFDIV(SDNode *N); 179 SDOperand visitFREM(SDNode *N); 180 SDOperand visitFCOPYSIGN(SDNode *N); 181 SDOperand visitSINT_TO_FP(SDNode *N); 182 SDOperand visitUINT_TO_FP(SDNode *N); 183 SDOperand visitFP_TO_SINT(SDNode *N); 184 SDOperand visitFP_TO_UINT(SDNode *N); 185 SDOperand visitFP_ROUND(SDNode *N); 186 SDOperand visitFP_ROUND_INREG(SDNode *N); 187 SDOperand visitFP_EXTEND(SDNode *N); 188 SDOperand visitFNEG(SDNode *N); 189 SDOperand visitFABS(SDNode *N); 190 SDOperand visitBRCOND(SDNode *N); 191 SDOperand visitBR_CC(SDNode *N); 192 SDOperand visitLOAD(SDNode *N); 193 SDOperand visitSTORE(SDNode *N); 194 SDOperand visitINSERT_VECTOR_ELT(SDNode *N); 195 SDOperand visitEXTRACT_VECTOR_ELT(SDNode *N); 196 SDOperand visitBUILD_VECTOR(SDNode *N); 197 SDOperand visitCONCAT_VECTORS(SDNode *N); 198 SDOperand visitVECTOR_SHUFFLE(SDNode *N); 199 200 SDOperand XformToShuffleWithZero(SDNode *N); 201 SDOperand ReassociateOps(unsigned Opc, SDOperand LHS, SDOperand RHS); 202 203 SDOperand visitShiftByConstant(SDNode *N, unsigned Amt); 204 205 bool SimplifySelectOps(SDNode *SELECT, SDOperand LHS, SDOperand RHS); 206 SDOperand SimplifyBinOpWithSameOpcodeHands(SDNode *N); 207 SDOperand SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2); 208 SDOperand SimplifySelectCC(SDOperand N0, SDOperand N1, SDOperand N2, 209 SDOperand N3, ISD::CondCode CC, 210 bool NotExtCompare = false); 211 SDOperand SimplifySetCC(MVT::ValueType VT, SDOperand N0, SDOperand N1, 212 ISD::CondCode Cond, bool foldBooleans = true); 213 SDOperand SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 214 unsigned HiOp); 215 SDOperand ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *, MVT::ValueType); 216 SDOperand BuildSDIV(SDNode *N); 217 SDOperand BuildUDIV(SDNode *N); 218 SDNode *MatchRotate(SDOperand LHS, SDOperand RHS); 219 SDOperand ReduceLoadWidth(SDNode *N); 220 221 SDOperand GetDemandedBits(SDOperand V, uint64_t Mask); 222 223 /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 224 /// looking for aliasing nodes and adding them to the Aliases vector. 225 void GatherAllAliases(SDNode *N, SDOperand OriginalChain, 226 SmallVector<SDOperand, 8> &Aliases); 227 228 /// isAlias - Return true if there is any possibility that the two addresses 229 /// overlap. 230 bool isAlias(SDOperand Ptr1, int64_t Size1, 231 const Value *SrcValue1, int SrcValueOffset1, 232 SDOperand Ptr2, int64_t Size2, 233 const Value *SrcValue2, int SrcValueOffset2); 234 235 /// FindAliasInfo - Extracts the relevant alias information from the memory 236 /// node. Returns true if the operand was a load. 237 bool FindAliasInfo(SDNode *N, 238 SDOperand &Ptr, int64_t &Size, 239 const Value *&SrcValue, int &SrcValueOffset); 240 241 /// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, 242 /// looking for a better chain (aliasing node.) 243 SDOperand FindBetterChain(SDNode *N, SDOperand Chain); 244 245public: 246 DAGCombiner(SelectionDAG &D, AliasAnalysis &A) 247 : DAG(D), 248 TLI(D.getTargetLoweringInfo()), 249 AfterLegalize(false), 250 AA(A) {} 251 252 /// Run - runs the dag combiner on all nodes in the work list 253 void Run(bool RunningAfterLegalize); 254 }; 255} 256 257 258namespace { 259/// WorkListRemover - This class is a DAGUpdateListener that removes any deleted 260/// nodes from the worklist. 261class VISIBILITY_HIDDEN WorkListRemover : 262 public SelectionDAG::DAGUpdateListener { 263 DAGCombiner &DC; 264public: 265 WorkListRemover(DAGCombiner &dc) : DC(dc) {} 266 267 virtual void NodeDeleted(SDNode *N) { 268 DC.removeFromWorkList(N); 269 } 270 271 virtual void NodeUpdated(SDNode *N) { 272 // Ignore updates. 273 } 274}; 275} 276 277//===----------------------------------------------------------------------===// 278// TargetLowering::DAGCombinerInfo implementation 279//===----------------------------------------------------------------------===// 280 281void TargetLowering::DAGCombinerInfo::AddToWorklist(SDNode *N) { 282 ((DAGCombiner*)DC)->AddToWorkList(N); 283} 284 285SDOperand TargetLowering::DAGCombinerInfo:: 286CombineTo(SDNode *N, const std::vector<SDOperand> &To) { 287 return ((DAGCombiner*)DC)->CombineTo(N, &To[0], To.size()); 288} 289 290SDOperand TargetLowering::DAGCombinerInfo:: 291CombineTo(SDNode *N, SDOperand Res) { 292 return ((DAGCombiner*)DC)->CombineTo(N, Res); 293} 294 295 296SDOperand TargetLowering::DAGCombinerInfo:: 297CombineTo(SDNode *N, SDOperand Res0, SDOperand Res1) { 298 return ((DAGCombiner*)DC)->CombineTo(N, Res0, Res1); 299} 300 301 302//===----------------------------------------------------------------------===// 303// Helper Functions 304//===----------------------------------------------------------------------===// 305 306/// isNegatibleForFree - Return 1 if we can compute the negated form of the 307/// specified expression for the same cost as the expression itself, or 2 if we 308/// can compute the negated form more cheaply than the expression itself. 309static char isNegatibleForFree(SDOperand Op, unsigned Depth = 0) { 310 // No compile time optimizations on this type. 311 if (Op.getValueType() == MVT::ppcf128) 312 return 0; 313 314 // fneg is removable even if it has multiple uses. 315 if (Op.getOpcode() == ISD::FNEG) return 2; 316 317 // Don't allow anything with multiple uses. 318 if (!Op.hasOneUse()) return 0; 319 320 // Don't recurse exponentially. 321 if (Depth > 6) return 0; 322 323 switch (Op.getOpcode()) { 324 default: return false; 325 case ISD::ConstantFP: 326 return 1; 327 case ISD::FADD: 328 // FIXME: determine better conditions for this xform. 329 if (!UnsafeFPMath) return 0; 330 331 // -(A+B) -> -A - B 332 if (char V = isNegatibleForFree(Op.getOperand(0), Depth+1)) 333 return V; 334 // -(A+B) -> -B - A 335 return isNegatibleForFree(Op.getOperand(1), Depth+1); 336 case ISD::FSUB: 337 // We can't turn -(A-B) into B-A when we honor signed zeros. 338 if (!UnsafeFPMath) return 0; 339 340 // -(A-B) -> B-A 341 return 1; 342 343 case ISD::FMUL: 344 case ISD::FDIV: 345 if (HonorSignDependentRoundingFPMath()) return 0; 346 347 // -(X*Y) -> (-X * Y) or (X*-Y) 348 if (char V = isNegatibleForFree(Op.getOperand(0), Depth+1)) 349 return V; 350 351 return isNegatibleForFree(Op.getOperand(1), Depth+1); 352 353 case ISD::FP_EXTEND: 354 case ISD::FP_ROUND: 355 case ISD::FSIN: 356 return isNegatibleForFree(Op.getOperand(0), Depth+1); 357 } 358} 359 360/// GetNegatedExpression - If isNegatibleForFree returns true, this function 361/// returns the newly negated expression. 362static SDOperand GetNegatedExpression(SDOperand Op, SelectionDAG &DAG, 363 unsigned Depth = 0) { 364 // fneg is removable even if it has multiple uses. 365 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0); 366 367 // Don't allow anything with multiple uses. 368 assert(Op.hasOneUse() && "Unknown reuse!"); 369 370 assert(Depth <= 6 && "GetNegatedExpression doesn't match isNegatibleForFree"); 371 switch (Op.getOpcode()) { 372 default: assert(0 && "Unknown code"); 373 case ISD::ConstantFP: { 374 APFloat V = cast<ConstantFPSDNode>(Op)->getValueAPF(); 375 V.changeSign(); 376 return DAG.getConstantFP(V, Op.getValueType()); 377 } 378 case ISD::FADD: 379 // FIXME: determine better conditions for this xform. 380 assert(UnsafeFPMath); 381 382 // -(A+B) -> -A - B 383 if (isNegatibleForFree(Op.getOperand(0), Depth+1)) 384 return DAG.getNode(ISD::FSUB, Op.getValueType(), 385 GetNegatedExpression(Op.getOperand(0), DAG, Depth+1), 386 Op.getOperand(1)); 387 // -(A+B) -> -B - A 388 return DAG.getNode(ISD::FSUB, Op.getValueType(), 389 GetNegatedExpression(Op.getOperand(1), DAG, Depth+1), 390 Op.getOperand(0)); 391 case ISD::FSUB: 392 // We can't turn -(A-B) into B-A when we honor signed zeros. 393 assert(UnsafeFPMath); 394 395 // -(0-B) -> B 396 if (ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(Op.getOperand(0))) 397 if (N0CFP->getValueAPF().isZero()) 398 return Op.getOperand(1); 399 400 // -(A-B) -> B-A 401 return DAG.getNode(ISD::FSUB, Op.getValueType(), Op.getOperand(1), 402 Op.getOperand(0)); 403 404 case ISD::FMUL: 405 case ISD::FDIV: 406 assert(!HonorSignDependentRoundingFPMath()); 407 408 // -(X*Y) -> -X * Y 409 if (isNegatibleForFree(Op.getOperand(0), Depth+1)) 410 return DAG.getNode(Op.getOpcode(), Op.getValueType(), 411 GetNegatedExpression(Op.getOperand(0), DAG, Depth+1), 412 Op.getOperand(1)); 413 414 // -(X*Y) -> X * -Y 415 return DAG.getNode(Op.getOpcode(), Op.getValueType(), 416 Op.getOperand(0), 417 GetNegatedExpression(Op.getOperand(1), DAG, Depth+1)); 418 419 case ISD::FP_EXTEND: 420 case ISD::FSIN: 421 return DAG.getNode(Op.getOpcode(), Op.getValueType(), 422 GetNegatedExpression(Op.getOperand(0), DAG, Depth+1)); 423 case ISD::FP_ROUND: 424 return DAG.getNode(ISD::FP_ROUND, Op.getValueType(), 425 GetNegatedExpression(Op.getOperand(0), DAG, Depth+1), 426 Op.getOperand(1)); 427 } 428} 429 430 431// isSetCCEquivalent - Return true if this node is a setcc, or is a select_cc 432// that selects between the values 1 and 0, making it equivalent to a setcc. 433// Also, set the incoming LHS, RHS, and CC references to the appropriate 434// nodes based on the type of node we are checking. This simplifies life a 435// bit for the callers. 436static bool isSetCCEquivalent(SDOperand N, SDOperand &LHS, SDOperand &RHS, 437 SDOperand &CC) { 438 if (N.getOpcode() == ISD::SETCC) { 439 LHS = N.getOperand(0); 440 RHS = N.getOperand(1); 441 CC = N.getOperand(2); 442 return true; 443 } 444 if (N.getOpcode() == ISD::SELECT_CC && 445 N.getOperand(2).getOpcode() == ISD::Constant && 446 N.getOperand(3).getOpcode() == ISD::Constant && 447 cast<ConstantSDNode>(N.getOperand(2))->getValue() == 1 && 448 cast<ConstantSDNode>(N.getOperand(3))->isNullValue()) { 449 LHS = N.getOperand(0); 450 RHS = N.getOperand(1); 451 CC = N.getOperand(4); 452 return true; 453 } 454 return false; 455} 456 457// isOneUseSetCC - Return true if this is a SetCC-equivalent operation with only 458// one use. If this is true, it allows the users to invert the operation for 459// free when it is profitable to do so. 460static bool isOneUseSetCC(SDOperand N) { 461 SDOperand N0, N1, N2; 462 if (isSetCCEquivalent(N, N0, N1, N2) && N.Val->hasOneUse()) 463 return true; 464 return false; 465} 466 467SDOperand DAGCombiner::ReassociateOps(unsigned Opc, SDOperand N0, SDOperand N1){ 468 MVT::ValueType VT = N0.getValueType(); 469 // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use 470 // reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2)) 471 if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) { 472 if (isa<ConstantSDNode>(N1)) { 473 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(1), N1); 474 AddToWorkList(OpNode.Val); 475 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(0)); 476 } else if (N0.hasOneUse()) { 477 SDOperand OpNode = DAG.getNode(Opc, VT, N0.getOperand(0), N1); 478 AddToWorkList(OpNode.Val); 479 return DAG.getNode(Opc, VT, OpNode, N0.getOperand(1)); 480 } 481 } 482 // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use 483 // reassoc. (op c2, (op x, c1)) -> (op x, (op c1, c2)) 484 if (N1.getOpcode() == Opc && isa<ConstantSDNode>(N1.getOperand(1))) { 485 if (isa<ConstantSDNode>(N0)) { 486 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(1), N0); 487 AddToWorkList(OpNode.Val); 488 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(0)); 489 } else if (N1.hasOneUse()) { 490 SDOperand OpNode = DAG.getNode(Opc, VT, N1.getOperand(0), N0); 491 AddToWorkList(OpNode.Val); 492 return DAG.getNode(Opc, VT, OpNode, N1.getOperand(1)); 493 } 494 } 495 return SDOperand(); 496} 497 498SDOperand DAGCombiner::CombineTo(SDNode *N, const SDOperand *To, unsigned NumTo, 499 bool AddTo) { 500 assert(N->getNumValues() == NumTo && "Broken CombineTo call!"); 501 ++NodesCombined; 502 DOUT << "\nReplacing.1 "; DEBUG(N->dump(&DAG)); 503 DOUT << "\nWith: "; DEBUG(To[0].Val->dump(&DAG)); 504 DOUT << " and " << NumTo-1 << " other values\n"; 505 WorkListRemover DeadNodes(*this); 506 DAG.ReplaceAllUsesWith(N, To, &DeadNodes); 507 508 if (AddTo) { 509 // Push the new nodes and any users onto the worklist 510 for (unsigned i = 0, e = NumTo; i != e; ++i) { 511 AddToWorkList(To[i].Val); 512 AddUsersToWorkList(To[i].Val); 513 } 514 } 515 516 // Nodes can be reintroduced into the worklist. Make sure we do not 517 // process a node that has been replaced. 518 removeFromWorkList(N); 519 520 // Finally, since the node is now dead, remove it from the graph. 521 DAG.DeleteNode(N); 522 return SDOperand(N, 0); 523} 524 525/// SimplifyDemandedBits - Check the specified integer node value to see if 526/// it can be simplified or if things it uses can be simplified by bit 527/// propagation. If so, return true. 528bool DAGCombiner::SimplifyDemandedBits(SDOperand Op, uint64_t Demanded) { 529 TargetLowering::TargetLoweringOpt TLO(DAG, AfterLegalize); 530 uint64_t KnownZero, KnownOne; 531 Demanded &= MVT::getIntVTBitMask(Op.getValueType()); 532 if (!TLI.SimplifyDemandedBits(Op, Demanded, KnownZero, KnownOne, TLO)) 533 return false; 534 535 // Revisit the node. 536 AddToWorkList(Op.Val); 537 538 // Replace the old value with the new one. 539 ++NodesCombined; 540 DOUT << "\nReplacing.2 "; DEBUG(TLO.Old.Val->dump(&DAG)); 541 DOUT << "\nWith: "; DEBUG(TLO.New.Val->dump(&DAG)); 542 DOUT << '\n'; 543 544 // Replace all uses. If any nodes become isomorphic to other nodes and 545 // are deleted, make sure to remove them from our worklist. 546 WorkListRemover DeadNodes(*this); 547 DAG.ReplaceAllUsesOfValueWith(TLO.Old, TLO.New, &DeadNodes); 548 549 // Push the new node and any (possibly new) users onto the worklist. 550 AddToWorkList(TLO.New.Val); 551 AddUsersToWorkList(TLO.New.Val); 552 553 // Finally, if the node is now dead, remove it from the graph. The node 554 // may not be dead if the replacement process recursively simplified to 555 // something else needing this node. 556 if (TLO.Old.Val->use_empty()) { 557 removeFromWorkList(TLO.Old.Val); 558 559 // If the operands of this node are only used by the node, they will now 560 // be dead. Make sure to visit them first to delete dead nodes early. 561 for (unsigned i = 0, e = TLO.Old.Val->getNumOperands(); i != e; ++i) 562 if (TLO.Old.Val->getOperand(i).Val->hasOneUse()) 563 AddToWorkList(TLO.Old.Val->getOperand(i).Val); 564 565 DAG.DeleteNode(TLO.Old.Val); 566 } 567 return true; 568} 569 570//===----------------------------------------------------------------------===// 571// Main DAG Combiner implementation 572//===----------------------------------------------------------------------===// 573 574void DAGCombiner::Run(bool RunningAfterLegalize) { 575 // set the instance variable, so that the various visit routines may use it. 576 AfterLegalize = RunningAfterLegalize; 577 578 // Add all the dag nodes to the worklist. 579 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(), 580 E = DAG.allnodes_end(); I != E; ++I) 581 WorkList.push_back(I); 582 583 // Create a dummy node (which is not added to allnodes), that adds a reference 584 // to the root node, preventing it from being deleted, and tracking any 585 // changes of the root. 586 HandleSDNode Dummy(DAG.getRoot()); 587 588 // The root of the dag may dangle to deleted nodes until the dag combiner is 589 // done. Set it to null to avoid confusion. 590 DAG.setRoot(SDOperand()); 591 592 // while the worklist isn't empty, inspect the node on the end of it and 593 // try and combine it. 594 while (!WorkList.empty()) { 595 SDNode *N = WorkList.back(); 596 WorkList.pop_back(); 597 598 // If N has no uses, it is dead. Make sure to revisit all N's operands once 599 // N is deleted from the DAG, since they too may now be dead or may have a 600 // reduced number of uses, allowing other xforms. 601 if (N->use_empty() && N != &Dummy) { 602 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 603 AddToWorkList(N->getOperand(i).Val); 604 605 DAG.DeleteNode(N); 606 continue; 607 } 608 609 SDOperand RV = combine(N); 610 611 if (RV.Val == 0) 612 continue; 613 614 ++NodesCombined; 615 616 // If we get back the same node we passed in, rather than a new node or 617 // zero, we know that the node must have defined multiple values and 618 // CombineTo was used. Since CombineTo takes care of the worklist 619 // mechanics for us, we have no work to do in this case. 620 if (RV.Val == N) 621 continue; 622 623 assert(N->getOpcode() != ISD::DELETED_NODE && 624 RV.Val->getOpcode() != ISD::DELETED_NODE && 625 "Node was deleted but visit returned new node!"); 626 627 DOUT << "\nReplacing.3 "; DEBUG(N->dump(&DAG)); 628 DOUT << "\nWith: "; DEBUG(RV.Val->dump(&DAG)); 629 DOUT << '\n'; 630 WorkListRemover DeadNodes(*this); 631 if (N->getNumValues() == RV.Val->getNumValues()) 632 DAG.ReplaceAllUsesWith(N, RV.Val, &DeadNodes); 633 else { 634 assert(N->getValueType(0) == RV.getValueType() && 635 N->getNumValues() == 1 && "Type mismatch"); 636 SDOperand OpV = RV; 637 DAG.ReplaceAllUsesWith(N, &OpV, &DeadNodes); 638 } 639 640 // Push the new node and any users onto the worklist 641 AddToWorkList(RV.Val); 642 AddUsersToWorkList(RV.Val); 643 644 // Add any uses of the old node to the worklist in case this node is the 645 // last one that uses them. They may become dead after this node is 646 // deleted. 647 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 648 AddToWorkList(N->getOperand(i).Val); 649 650 // Nodes can be reintroduced into the worklist. Make sure we do not 651 // process a node that has been replaced. 652 removeFromWorkList(N); 653 654 // Finally, since the node is now dead, remove it from the graph. 655 DAG.DeleteNode(N); 656 } 657 658 // If the root changed (e.g. it was a dead load, update the root). 659 DAG.setRoot(Dummy.getValue()); 660} 661 662SDOperand DAGCombiner::visit(SDNode *N) { 663 switch(N->getOpcode()) { 664 default: break; 665 case ISD::TokenFactor: return visitTokenFactor(N); 666 case ISD::MERGE_VALUES: return visitMERGE_VALUES(N); 667 case ISD::ADD: return visitADD(N); 668 case ISD::SUB: return visitSUB(N); 669 case ISD::ADDC: return visitADDC(N); 670 case ISD::ADDE: return visitADDE(N); 671 case ISD::MUL: return visitMUL(N); 672 case ISD::SDIV: return visitSDIV(N); 673 case ISD::UDIV: return visitUDIV(N); 674 case ISD::SREM: return visitSREM(N); 675 case ISD::UREM: return visitUREM(N); 676 case ISD::MULHU: return visitMULHU(N); 677 case ISD::MULHS: return visitMULHS(N); 678 case ISD::SMUL_LOHI: return visitSMUL_LOHI(N); 679 case ISD::UMUL_LOHI: return visitUMUL_LOHI(N); 680 case ISD::SDIVREM: return visitSDIVREM(N); 681 case ISD::UDIVREM: return visitUDIVREM(N); 682 case ISD::AND: return visitAND(N); 683 case ISD::OR: return visitOR(N); 684 case ISD::XOR: return visitXOR(N); 685 case ISD::SHL: return visitSHL(N); 686 case ISD::SRA: return visitSRA(N); 687 case ISD::SRL: return visitSRL(N); 688 case ISD::CTLZ: return visitCTLZ(N); 689 case ISD::CTTZ: return visitCTTZ(N); 690 case ISD::CTPOP: return visitCTPOP(N); 691 case ISD::SELECT: return visitSELECT(N); 692 case ISD::SELECT_CC: return visitSELECT_CC(N); 693 case ISD::SETCC: return visitSETCC(N); 694 case ISD::SIGN_EXTEND: return visitSIGN_EXTEND(N); 695 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N); 696 case ISD::ANY_EXTEND: return visitANY_EXTEND(N); 697 case ISD::SIGN_EXTEND_INREG: return visitSIGN_EXTEND_INREG(N); 698 case ISD::TRUNCATE: return visitTRUNCATE(N); 699 case ISD::BIT_CONVERT: return visitBIT_CONVERT(N); 700 case ISD::FADD: return visitFADD(N); 701 case ISD::FSUB: return visitFSUB(N); 702 case ISD::FMUL: return visitFMUL(N); 703 case ISD::FDIV: return visitFDIV(N); 704 case ISD::FREM: return visitFREM(N); 705 case ISD::FCOPYSIGN: return visitFCOPYSIGN(N); 706 case ISD::SINT_TO_FP: return visitSINT_TO_FP(N); 707 case ISD::UINT_TO_FP: return visitUINT_TO_FP(N); 708 case ISD::FP_TO_SINT: return visitFP_TO_SINT(N); 709 case ISD::FP_TO_UINT: return visitFP_TO_UINT(N); 710 case ISD::FP_ROUND: return visitFP_ROUND(N); 711 case ISD::FP_ROUND_INREG: return visitFP_ROUND_INREG(N); 712 case ISD::FP_EXTEND: return visitFP_EXTEND(N); 713 case ISD::FNEG: return visitFNEG(N); 714 case ISD::FABS: return visitFABS(N); 715 case ISD::BRCOND: return visitBRCOND(N); 716 case ISD::BR_CC: return visitBR_CC(N); 717 case ISD::LOAD: return visitLOAD(N); 718 case ISD::STORE: return visitSTORE(N); 719 case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N); 720 case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N); 721 case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N); 722 case ISD::CONCAT_VECTORS: return visitCONCAT_VECTORS(N); 723 case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N); 724 } 725 return SDOperand(); 726} 727 728SDOperand DAGCombiner::combine(SDNode *N) { 729 730 SDOperand RV = visit(N); 731 732 // If nothing happened, try a target-specific DAG combine. 733 if (RV.Val == 0) { 734 assert(N->getOpcode() != ISD::DELETED_NODE && 735 "Node was deleted but visit returned NULL!"); 736 737 if (N->getOpcode() >= ISD::BUILTIN_OP_END || 738 TLI.hasTargetDAGCombine((ISD::NodeType)N->getOpcode())) { 739 740 // Expose the DAG combiner to the target combiner impls. 741 TargetLowering::DAGCombinerInfo 742 DagCombineInfo(DAG, !AfterLegalize, false, this); 743 744 RV = TLI.PerformDAGCombine(N, DagCombineInfo); 745 } 746 } 747 748 return RV; 749} 750 751/// getInputChainForNode - Given a node, return its input chain if it has one, 752/// otherwise return a null sd operand. 753static SDOperand getInputChainForNode(SDNode *N) { 754 if (unsigned NumOps = N->getNumOperands()) { 755 if (N->getOperand(0).getValueType() == MVT::Other) 756 return N->getOperand(0); 757 else if (N->getOperand(NumOps-1).getValueType() == MVT::Other) 758 return N->getOperand(NumOps-1); 759 for (unsigned i = 1; i < NumOps-1; ++i) 760 if (N->getOperand(i).getValueType() == MVT::Other) 761 return N->getOperand(i); 762 } 763 return SDOperand(0, 0); 764} 765 766SDOperand DAGCombiner::visitTokenFactor(SDNode *N) { 767 // If N has two operands, where one has an input chain equal to the other, 768 // the 'other' chain is redundant. 769 if (N->getNumOperands() == 2) { 770 if (getInputChainForNode(N->getOperand(0).Val) == N->getOperand(1)) 771 return N->getOperand(0); 772 if (getInputChainForNode(N->getOperand(1).Val) == N->getOperand(0)) 773 return N->getOperand(1); 774 } 775 776 SmallVector<SDNode *, 8> TFs; // List of token factors to visit. 777 SmallVector<SDOperand, 8> Ops; // Ops for replacing token factor. 778 SmallPtrSet<SDNode*, 16> SeenOps; 779 bool Changed = false; // If we should replace this token factor. 780 781 // Start out with this token factor. 782 TFs.push_back(N); 783 784 // Iterate through token factors. The TFs grows when new token factors are 785 // encountered. 786 for (unsigned i = 0; i < TFs.size(); ++i) { 787 SDNode *TF = TFs[i]; 788 789 // Check each of the operands. 790 for (unsigned i = 0, ie = TF->getNumOperands(); i != ie; ++i) { 791 SDOperand Op = TF->getOperand(i); 792 793 switch (Op.getOpcode()) { 794 case ISD::EntryToken: 795 // Entry tokens don't need to be added to the list. They are 796 // rededundant. 797 Changed = true; 798 break; 799 800 case ISD::TokenFactor: 801 if ((CombinerAA || Op.hasOneUse()) && 802 std::find(TFs.begin(), TFs.end(), Op.Val) == TFs.end()) { 803 // Queue up for processing. 804 TFs.push_back(Op.Val); 805 // Clean up in case the token factor is removed. 806 AddToWorkList(Op.Val); 807 Changed = true; 808 break; 809 } 810 // Fall thru 811 812 default: 813 // Only add if it isn't already in the list. 814 if (SeenOps.insert(Op.Val)) 815 Ops.push_back(Op); 816 else 817 Changed = true; 818 break; 819 } 820 } 821 } 822 823 SDOperand Result; 824 825 // If we've change things around then replace token factor. 826 if (Changed) { 827 if (Ops.empty()) { 828 // The entry token is the only possible outcome. 829 Result = DAG.getEntryNode(); 830 } else { 831 // New and improved token factor. 832 Result = DAG.getNode(ISD::TokenFactor, MVT::Other, &Ops[0], Ops.size()); 833 } 834 835 // Don't add users to work list. 836 return CombineTo(N, Result, false); 837 } 838 839 return Result; 840} 841 842/// MERGE_VALUES can always be eliminated. 843SDOperand DAGCombiner::visitMERGE_VALUES(SDNode *N) { 844 WorkListRemover DeadNodes(*this); 845 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 846 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, i), N->getOperand(i), 847 &DeadNodes); 848 removeFromWorkList(N); 849 DAG.DeleteNode(N); 850 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 851} 852 853 854static 855SDOperand combineShlAddConstant(SDOperand N0, SDOperand N1, SelectionDAG &DAG) { 856 MVT::ValueType VT = N0.getValueType(); 857 SDOperand N00 = N0.getOperand(0); 858 SDOperand N01 = N0.getOperand(1); 859 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01); 860 if (N01C && N00.getOpcode() == ISD::ADD && N00.Val->hasOneUse() && 861 isa<ConstantSDNode>(N00.getOperand(1))) { 862 N0 = DAG.getNode(ISD::ADD, VT, 863 DAG.getNode(ISD::SHL, VT, N00.getOperand(0), N01), 864 DAG.getNode(ISD::SHL, VT, N00.getOperand(1), N01)); 865 return DAG.getNode(ISD::ADD, VT, N0, N1); 866 } 867 return SDOperand(); 868} 869 870static 871SDOperand combineSelectAndUse(SDNode *N, SDOperand Slct, SDOperand OtherOp, 872 SelectionDAG &DAG) { 873 MVT::ValueType VT = N->getValueType(0); 874 unsigned Opc = N->getOpcode(); 875 bool isSlctCC = Slct.getOpcode() == ISD::SELECT_CC; 876 SDOperand LHS = isSlctCC ? Slct.getOperand(2) : Slct.getOperand(1); 877 SDOperand RHS = isSlctCC ? Slct.getOperand(3) : Slct.getOperand(2); 878 ISD::CondCode CC = ISD::SETCC_INVALID; 879 if (isSlctCC) 880 CC = cast<CondCodeSDNode>(Slct.getOperand(4))->get(); 881 else { 882 SDOperand CCOp = Slct.getOperand(0); 883 if (CCOp.getOpcode() == ISD::SETCC) 884 CC = cast<CondCodeSDNode>(CCOp.getOperand(2))->get(); 885 } 886 887 bool DoXform = false; 888 bool InvCC = false; 889 assert ((Opc == ISD::ADD || (Opc == ISD::SUB && Slct == N->getOperand(1))) && 890 "Bad input!"); 891 if (LHS.getOpcode() == ISD::Constant && 892 cast<ConstantSDNode>(LHS)->isNullValue()) 893 DoXform = true; 894 else if (CC != ISD::SETCC_INVALID && 895 RHS.getOpcode() == ISD::Constant && 896 cast<ConstantSDNode>(RHS)->isNullValue()) { 897 std::swap(LHS, RHS); 898 SDOperand Op0 = Slct.getOperand(0); 899 bool isInt = MVT::isInteger(isSlctCC ? Op0.getValueType() 900 : Op0.getOperand(0).getValueType()); 901 CC = ISD::getSetCCInverse(CC, isInt); 902 DoXform = true; 903 InvCC = true; 904 } 905 906 if (DoXform) { 907 SDOperand Result = DAG.getNode(Opc, VT, OtherOp, RHS); 908 if (isSlctCC) 909 return DAG.getSelectCC(OtherOp, Result, 910 Slct.getOperand(0), Slct.getOperand(1), CC); 911 SDOperand CCOp = Slct.getOperand(0); 912 if (InvCC) 913 CCOp = DAG.getSetCC(CCOp.getValueType(), CCOp.getOperand(0), 914 CCOp.getOperand(1), CC); 915 return DAG.getNode(ISD::SELECT, VT, CCOp, OtherOp, Result); 916 } 917 return SDOperand(); 918} 919 920SDOperand DAGCombiner::visitADD(SDNode *N) { 921 SDOperand N0 = N->getOperand(0); 922 SDOperand N1 = N->getOperand(1); 923 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 924 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 925 MVT::ValueType VT = N0.getValueType(); 926 927 // fold vector ops 928 if (MVT::isVector(VT)) { 929 SDOperand FoldedVOp = SimplifyVBinOp(N); 930 if (FoldedVOp.Val) return FoldedVOp; 931 } 932 933 // fold (add x, undef) -> undef 934 if (N0.getOpcode() == ISD::UNDEF) 935 return N0; 936 if (N1.getOpcode() == ISD::UNDEF) 937 return N1; 938 // fold (add c1, c2) -> c1+c2 939 if (N0C && N1C) 940 return DAG.getConstant(N0C->getValue() + N1C->getValue(), VT); 941 // canonicalize constant to RHS 942 if (N0C && !N1C) 943 return DAG.getNode(ISD::ADD, VT, N1, N0); 944 // fold (add x, 0) -> x 945 if (N1C && N1C->isNullValue()) 946 return N0; 947 // fold ((c1-A)+c2) -> (c1+c2)-A 948 if (N1C && N0.getOpcode() == ISD::SUB) 949 if (ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getOperand(0))) 950 return DAG.getNode(ISD::SUB, VT, 951 DAG.getConstant(N1C->getValue()+N0C->getValue(), VT), 952 N0.getOperand(1)); 953 // reassociate add 954 SDOperand RADD = ReassociateOps(ISD::ADD, N0, N1); 955 if (RADD.Val != 0) 956 return RADD; 957 // fold ((0-A) + B) -> B-A 958 if (N0.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N0.getOperand(0)) && 959 cast<ConstantSDNode>(N0.getOperand(0))->isNullValue()) 960 return DAG.getNode(ISD::SUB, VT, N1, N0.getOperand(1)); 961 // fold (A + (0-B)) -> A-B 962 if (N1.getOpcode() == ISD::SUB && isa<ConstantSDNode>(N1.getOperand(0)) && 963 cast<ConstantSDNode>(N1.getOperand(0))->isNullValue()) 964 return DAG.getNode(ISD::SUB, VT, N0, N1.getOperand(1)); 965 // fold (A+(B-A)) -> B 966 if (N1.getOpcode() == ISD::SUB && N0 == N1.getOperand(1)) 967 return N1.getOperand(0); 968 969 if (!MVT::isVector(VT) && SimplifyDemandedBits(SDOperand(N, 0))) 970 return SDOperand(N, 0); 971 972 // fold (a+b) -> (a|b) iff a and b share no bits. 973 if (MVT::isInteger(VT) && !MVT::isVector(VT)) { 974 uint64_t LHSZero, LHSOne; 975 uint64_t RHSZero, RHSOne; 976 uint64_t Mask = MVT::getIntVTBitMask(VT); 977 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 978 if (LHSZero) { 979 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 980 981 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 982 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 983 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 984 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 985 return DAG.getNode(ISD::OR, VT, N0, N1); 986 } 987 } 988 989 // fold (add (shl (add x, c1), c2), ) -> (add (add (shl x, c2), c1<<c2), ) 990 if (N0.getOpcode() == ISD::SHL && N0.Val->hasOneUse()) { 991 SDOperand Result = combineShlAddConstant(N0, N1, DAG); 992 if (Result.Val) return Result; 993 } 994 if (N1.getOpcode() == ISD::SHL && N1.Val->hasOneUse()) { 995 SDOperand Result = combineShlAddConstant(N1, N0, DAG); 996 if (Result.Val) return Result; 997 } 998 999 // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c)) 1000 if (N0.getOpcode() == ISD::SELECT && N0.Val->hasOneUse()) { 1001 SDOperand Result = combineSelectAndUse(N, N0, N1, DAG); 1002 if (Result.Val) return Result; 1003 } 1004 if (N1.getOpcode() == ISD::SELECT && N1.Val->hasOneUse()) { 1005 SDOperand Result = combineSelectAndUse(N, N1, N0, DAG); 1006 if (Result.Val) return Result; 1007 } 1008 1009 return SDOperand(); 1010} 1011 1012SDOperand DAGCombiner::visitADDC(SDNode *N) { 1013 SDOperand N0 = N->getOperand(0); 1014 SDOperand N1 = N->getOperand(1); 1015 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1016 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1017 MVT::ValueType VT = N0.getValueType(); 1018 1019 // If the flag result is dead, turn this into an ADD. 1020 if (N->hasNUsesOfValue(0, 1)) 1021 return CombineTo(N, DAG.getNode(ISD::ADD, VT, N1, N0), 1022 DAG.getNode(ISD::CARRY_FALSE, MVT::Flag)); 1023 1024 // canonicalize constant to RHS. 1025 if (N0C && !N1C) { 1026 SDOperand Ops[] = { N1, N0 }; 1027 return DAG.getNode(ISD::ADDC, N->getVTList(), Ops, 2); 1028 } 1029 1030 // fold (addc x, 0) -> x + no carry out 1031 if (N1C && N1C->isNullValue()) 1032 return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE, MVT::Flag)); 1033 1034 // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits. 1035 uint64_t LHSZero, LHSOne; 1036 uint64_t RHSZero, RHSOne; 1037 uint64_t Mask = MVT::getIntVTBitMask(VT); 1038 DAG.ComputeMaskedBits(N0, Mask, LHSZero, LHSOne); 1039 if (LHSZero) { 1040 DAG.ComputeMaskedBits(N1, Mask, RHSZero, RHSOne); 1041 1042 // If all possibly-set bits on the LHS are clear on the RHS, return an OR. 1043 // If all possibly-set bits on the RHS are clear on the LHS, return an OR. 1044 if ((RHSZero & (~LHSZero & Mask)) == (~LHSZero & Mask) || 1045 (LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask)) 1046 return CombineTo(N, DAG.getNode(ISD::OR, VT, N0, N1), 1047 DAG.getNode(ISD::CARRY_FALSE, MVT::Flag)); 1048 } 1049 1050 return SDOperand(); 1051} 1052 1053SDOperand DAGCombiner::visitADDE(SDNode *N) { 1054 SDOperand N0 = N->getOperand(0); 1055 SDOperand N1 = N->getOperand(1); 1056 SDOperand CarryIn = N->getOperand(2); 1057 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1058 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1059 //MVT::ValueType VT = N0.getValueType(); 1060 1061 // canonicalize constant to RHS 1062 if (N0C && !N1C) { 1063 SDOperand Ops[] = { N1, N0, CarryIn }; 1064 return DAG.getNode(ISD::ADDE, N->getVTList(), Ops, 3); 1065 } 1066 1067 // fold (adde x, y, false) -> (addc x, y) 1068 if (CarryIn.getOpcode() == ISD::CARRY_FALSE) { 1069 SDOperand Ops[] = { N1, N0 }; 1070 return DAG.getNode(ISD::ADDC, N->getVTList(), Ops, 2); 1071 } 1072 1073 return SDOperand(); 1074} 1075 1076 1077 1078SDOperand DAGCombiner::visitSUB(SDNode *N) { 1079 SDOperand N0 = N->getOperand(0); 1080 SDOperand N1 = N->getOperand(1); 1081 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 1082 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 1083 MVT::ValueType VT = N0.getValueType(); 1084 1085 // fold vector ops 1086 if (MVT::isVector(VT)) { 1087 SDOperand FoldedVOp = SimplifyVBinOp(N); 1088 if (FoldedVOp.Val) return FoldedVOp; 1089 } 1090 1091 // fold (sub x, x) -> 0 1092 if (N0 == N1) 1093 return DAG.getConstant(0, N->getValueType(0)); 1094 // fold (sub c1, c2) -> c1-c2 1095 if (N0C && N1C) 1096 return DAG.getNode(ISD::SUB, VT, N0, N1); 1097 // fold (sub x, c) -> (add x, -c) 1098 if (N1C) 1099 return DAG.getNode(ISD::ADD, VT, N0, DAG.getConstant(-N1C->getValue(), VT)); 1100 // fold (A+B)-A -> B 1101 if (N0.getOpcode() == ISD::ADD && N0.getOperand(0) == N1) 1102 return N0.getOperand(1); 1103 // fold (A+B)-B -> A 1104 if (N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1) 1105 return N0.getOperand(0); 1106 // fold (sub x, (select cc, 0, c)) -> (select cc, x, (sub, x, c)) 1107 if (N1.getOpcode() == ISD::SELECT && N1.Val->hasOneUse()) { 1108 SDOperand Result = combineSelectAndUse(N, N1, N0, DAG); 1109 if (Result.Val) return Result; 1110 } 1111 // If either operand of a sub is undef, the result is undef 1112 if (N0.getOpcode() == ISD::UNDEF) 1113 return N0; 1114 if (N1.getOpcode() == ISD::UNDEF) 1115 return N1; 1116 1117 return SDOperand(); 1118} 1119 1120SDOperand DAGCombiner::visitMUL(SDNode *N) { 1121 SDOperand N0 = N->getOperand(0); 1122 SDOperand N1 = N->getOperand(1); 1123 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1124 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1125 MVT::ValueType VT = N0.getValueType(); 1126 1127 // fold vector ops 1128 if (MVT::isVector(VT)) { 1129 SDOperand FoldedVOp = SimplifyVBinOp(N); 1130 if (FoldedVOp.Val) return FoldedVOp; 1131 } 1132 1133 // fold (mul x, undef) -> 0 1134 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1135 return DAG.getConstant(0, VT); 1136 // fold (mul c1, c2) -> c1*c2 1137 if (N0C && N1C) 1138 return DAG.getNode(ISD::MUL, VT, N0, N1); 1139 // canonicalize constant to RHS 1140 if (N0C && !N1C) 1141 return DAG.getNode(ISD::MUL, VT, N1, N0); 1142 // fold (mul x, 0) -> 0 1143 if (N1C && N1C->isNullValue()) 1144 return N1; 1145 // fold (mul x, -1) -> 0-x 1146 if (N1C && N1C->isAllOnesValue()) 1147 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0); 1148 // fold (mul x, (1 << c)) -> x << c 1149 if (N1C && isPowerOf2_64(N1C->getValue())) 1150 return DAG.getNode(ISD::SHL, VT, N0, 1151 DAG.getConstant(Log2_64(N1C->getValue()), 1152 TLI.getShiftAmountTy())); 1153 // fold (mul x, -(1 << c)) -> -(x << c) or (-x) << c 1154 if (N1C && isPowerOf2_64(-N1C->getSignExtended())) { 1155 // FIXME: If the input is something that is easily negated (e.g. a 1156 // single-use add), we should put the negate there. 1157 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), 1158 DAG.getNode(ISD::SHL, VT, N0, 1159 DAG.getConstant(Log2_64(-N1C->getSignExtended()), 1160 TLI.getShiftAmountTy()))); 1161 } 1162 1163 // (mul (shl X, c1), c2) -> (mul X, c2 << c1) 1164 if (N1C && N0.getOpcode() == ISD::SHL && 1165 isa<ConstantSDNode>(N0.getOperand(1))) { 1166 SDOperand C3 = DAG.getNode(ISD::SHL, VT, N1, N0.getOperand(1)); 1167 AddToWorkList(C3.Val); 1168 return DAG.getNode(ISD::MUL, VT, N0.getOperand(0), C3); 1169 } 1170 1171 // Change (mul (shl X, C), Y) -> (shl (mul X, Y), C) when the shift has one 1172 // use. 1173 { 1174 SDOperand Sh(0,0), Y(0,0); 1175 // Check for both (mul (shl X, C), Y) and (mul Y, (shl X, C)). 1176 if (N0.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N0.getOperand(1)) && 1177 N0.Val->hasOneUse()) { 1178 Sh = N0; Y = N1; 1179 } else if (N1.getOpcode() == ISD::SHL && 1180 isa<ConstantSDNode>(N1.getOperand(1)) && N1.Val->hasOneUse()) { 1181 Sh = N1; Y = N0; 1182 } 1183 if (Sh.Val) { 1184 SDOperand Mul = DAG.getNode(ISD::MUL, VT, Sh.getOperand(0), Y); 1185 return DAG.getNode(ISD::SHL, VT, Mul, Sh.getOperand(1)); 1186 } 1187 } 1188 // fold (mul (add x, c1), c2) -> (add (mul x, c2), c1*c2) 1189 if (N1C && N0.getOpcode() == ISD::ADD && N0.Val->hasOneUse() && 1190 isa<ConstantSDNode>(N0.getOperand(1))) { 1191 return DAG.getNode(ISD::ADD, VT, 1192 DAG.getNode(ISD::MUL, VT, N0.getOperand(0), N1), 1193 DAG.getNode(ISD::MUL, VT, N0.getOperand(1), N1)); 1194 } 1195 1196 // reassociate mul 1197 SDOperand RMUL = ReassociateOps(ISD::MUL, N0, N1); 1198 if (RMUL.Val != 0) 1199 return RMUL; 1200 1201 return SDOperand(); 1202} 1203 1204SDOperand DAGCombiner::visitSDIV(SDNode *N) { 1205 SDOperand N0 = N->getOperand(0); 1206 SDOperand N1 = N->getOperand(1); 1207 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 1208 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 1209 MVT::ValueType VT = N->getValueType(0); 1210 1211 // fold vector ops 1212 if (MVT::isVector(VT)) { 1213 SDOperand FoldedVOp = SimplifyVBinOp(N); 1214 if (FoldedVOp.Val) return FoldedVOp; 1215 } 1216 1217 // fold (sdiv c1, c2) -> c1/c2 1218 if (N0C && N1C && !N1C->isNullValue()) 1219 return DAG.getNode(ISD::SDIV, VT, N0, N1); 1220 // fold (sdiv X, 1) -> X 1221 if (N1C && N1C->getSignExtended() == 1LL) 1222 return N0; 1223 // fold (sdiv X, -1) -> 0-X 1224 if (N1C && N1C->isAllOnesValue()) 1225 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), N0); 1226 // If we know the sign bits of both operands are zero, strength reduce to a 1227 // udiv instead. Handles (X&15) /s 4 -> X&15 >> 2 1228 if (!MVT::isVector(VT)) { 1229 uint64_t SignBit = MVT::getIntVTSignBit(VT); 1230 if (DAG.MaskedValueIsZero(N1, SignBit) && 1231 DAG.MaskedValueIsZero(N0, SignBit)) 1232 return DAG.getNode(ISD::UDIV, N1.getValueType(), N0, N1); 1233 } 1234 // fold (sdiv X, pow2) -> simple ops after legalize 1235 if (N1C && N1C->getValue() && !TLI.isIntDivCheap() && 1236 (isPowerOf2_64(N1C->getSignExtended()) || 1237 isPowerOf2_64(-N1C->getSignExtended()))) { 1238 // If dividing by powers of two is cheap, then don't perform the following 1239 // fold. 1240 if (TLI.isPow2DivCheap()) 1241 return SDOperand(); 1242 int64_t pow2 = N1C->getSignExtended(); 1243 int64_t abs2 = pow2 > 0 ? pow2 : -pow2; 1244 unsigned lg2 = Log2_64(abs2); 1245 // Splat the sign bit into the register 1246 SDOperand SGN = DAG.getNode(ISD::SRA, VT, N0, 1247 DAG.getConstant(MVT::getSizeInBits(VT)-1, 1248 TLI.getShiftAmountTy())); 1249 AddToWorkList(SGN.Val); 1250 // Add (N0 < 0) ? abs2 - 1 : 0; 1251 SDOperand SRL = DAG.getNode(ISD::SRL, VT, SGN, 1252 DAG.getConstant(MVT::getSizeInBits(VT)-lg2, 1253 TLI.getShiftAmountTy())); 1254 SDOperand ADD = DAG.getNode(ISD::ADD, VT, N0, SRL); 1255 AddToWorkList(SRL.Val); 1256 AddToWorkList(ADD.Val); // Divide by pow2 1257 SDOperand SRA = DAG.getNode(ISD::SRA, VT, ADD, 1258 DAG.getConstant(lg2, TLI.getShiftAmountTy())); 1259 // If we're dividing by a positive value, we're done. Otherwise, we must 1260 // negate the result. 1261 if (pow2 > 0) 1262 return SRA; 1263 AddToWorkList(SRA.Val); 1264 return DAG.getNode(ISD::SUB, VT, DAG.getConstant(0, VT), SRA); 1265 } 1266 // if integer divide is expensive and we satisfy the requirements, emit an 1267 // alternate sequence. 1268 if (N1C && (N1C->getSignExtended() < -1 || N1C->getSignExtended() > 1) && 1269 !TLI.isIntDivCheap()) { 1270 SDOperand Op = BuildSDIV(N); 1271 if (Op.Val) return Op; 1272 } 1273 1274 // undef / X -> 0 1275 if (N0.getOpcode() == ISD::UNDEF) 1276 return DAG.getConstant(0, VT); 1277 // X / undef -> undef 1278 if (N1.getOpcode() == ISD::UNDEF) 1279 return N1; 1280 1281 return SDOperand(); 1282} 1283 1284SDOperand DAGCombiner::visitUDIV(SDNode *N) { 1285 SDOperand N0 = N->getOperand(0); 1286 SDOperand N1 = N->getOperand(1); 1287 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.Val); 1288 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 1289 MVT::ValueType VT = N->getValueType(0); 1290 1291 // fold vector ops 1292 if (MVT::isVector(VT)) { 1293 SDOperand FoldedVOp = SimplifyVBinOp(N); 1294 if (FoldedVOp.Val) return FoldedVOp; 1295 } 1296 1297 // fold (udiv c1, c2) -> c1/c2 1298 if (N0C && N1C && !N1C->isNullValue()) 1299 return DAG.getNode(ISD::UDIV, VT, N0, N1); 1300 // fold (udiv x, (1 << c)) -> x >>u c 1301 if (N1C && isPowerOf2_64(N1C->getValue())) 1302 return DAG.getNode(ISD::SRL, VT, N0, 1303 DAG.getConstant(Log2_64(N1C->getValue()), 1304 TLI.getShiftAmountTy())); 1305 // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2 1306 if (N1.getOpcode() == ISD::SHL) { 1307 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1308 if (isPowerOf2_64(SHC->getValue())) { 1309 MVT::ValueType ADDVT = N1.getOperand(1).getValueType(); 1310 SDOperand Add = DAG.getNode(ISD::ADD, ADDVT, N1.getOperand(1), 1311 DAG.getConstant(Log2_64(SHC->getValue()), 1312 ADDVT)); 1313 AddToWorkList(Add.Val); 1314 return DAG.getNode(ISD::SRL, VT, N0, Add); 1315 } 1316 } 1317 } 1318 // fold (udiv x, c) -> alternate 1319 if (N1C && N1C->getValue() && !TLI.isIntDivCheap()) { 1320 SDOperand Op = BuildUDIV(N); 1321 if (Op.Val) return Op; 1322 } 1323 1324 // undef / X -> 0 1325 if (N0.getOpcode() == ISD::UNDEF) 1326 return DAG.getConstant(0, VT); 1327 // X / undef -> undef 1328 if (N1.getOpcode() == ISD::UNDEF) 1329 return N1; 1330 1331 return SDOperand(); 1332} 1333 1334SDOperand DAGCombiner::visitSREM(SDNode *N) { 1335 SDOperand N0 = N->getOperand(0); 1336 SDOperand N1 = N->getOperand(1); 1337 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1338 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1339 MVT::ValueType VT = N->getValueType(0); 1340 1341 // fold (srem c1, c2) -> c1%c2 1342 if (N0C && N1C && !N1C->isNullValue()) 1343 return DAG.getNode(ISD::SREM, VT, N0, N1); 1344 // If we know the sign bits of both operands are zero, strength reduce to a 1345 // urem instead. Handles (X & 0x0FFFFFFF) %s 16 -> X&15 1346 if (!MVT::isVector(VT)) { 1347 uint64_t SignBit = MVT::getIntVTSignBit(VT); 1348 if (DAG.MaskedValueIsZero(N1, SignBit) && 1349 DAG.MaskedValueIsZero(N0, SignBit)) 1350 return DAG.getNode(ISD::UREM, VT, N0, N1); 1351 } 1352 1353 // If X/C can be simplified by the division-by-constant logic, lower 1354 // X%C to the equivalent of X-X/C*C. 1355 if (N1C && !N1C->isNullValue()) { 1356 SDOperand Div = DAG.getNode(ISD::SDIV, VT, N0, N1); 1357 AddToWorkList(Div.Val); 1358 SDOperand OptimizedDiv = combine(Div.Val); 1359 if (OptimizedDiv.Val && OptimizedDiv.Val != Div.Val) { 1360 SDOperand Mul = DAG.getNode(ISD::MUL, VT, OptimizedDiv, N1); 1361 SDOperand Sub = DAG.getNode(ISD::SUB, VT, N0, Mul); 1362 AddToWorkList(Mul.Val); 1363 return Sub; 1364 } 1365 } 1366 1367 // undef % X -> 0 1368 if (N0.getOpcode() == ISD::UNDEF) 1369 return DAG.getConstant(0, VT); 1370 // X % undef -> undef 1371 if (N1.getOpcode() == ISD::UNDEF) 1372 return N1; 1373 1374 return SDOperand(); 1375} 1376 1377SDOperand DAGCombiner::visitUREM(SDNode *N) { 1378 SDOperand N0 = N->getOperand(0); 1379 SDOperand N1 = N->getOperand(1); 1380 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1381 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1382 MVT::ValueType VT = N->getValueType(0); 1383 1384 // fold (urem c1, c2) -> c1%c2 1385 if (N0C && N1C && !N1C->isNullValue()) 1386 return DAG.getNode(ISD::UREM, VT, N0, N1); 1387 // fold (urem x, pow2) -> (and x, pow2-1) 1388 if (N1C && !N1C->isNullValue() && isPowerOf2_64(N1C->getValue())) 1389 return DAG.getNode(ISD::AND, VT, N0, DAG.getConstant(N1C->getValue()-1,VT)); 1390 // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1)) 1391 if (N1.getOpcode() == ISD::SHL) { 1392 if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) { 1393 if (isPowerOf2_64(SHC->getValue())) { 1394 SDOperand Add = DAG.getNode(ISD::ADD, VT, N1,DAG.getConstant(~0ULL,VT)); 1395 AddToWorkList(Add.Val); 1396 return DAG.getNode(ISD::AND, VT, N0, Add); 1397 } 1398 } 1399 } 1400 1401 // If X/C can be simplified by the division-by-constant logic, lower 1402 // X%C to the equivalent of X-X/C*C. 1403 if (N1C && !N1C->isNullValue()) { 1404 SDOperand Div = DAG.getNode(ISD::UDIV, VT, N0, N1); 1405 SDOperand OptimizedDiv = combine(Div.Val); 1406 if (OptimizedDiv.Val && OptimizedDiv.Val != Div.Val) { 1407 SDOperand Mul = DAG.getNode(ISD::MUL, VT, OptimizedDiv, N1); 1408 SDOperand Sub = DAG.getNode(ISD::SUB, VT, N0, Mul); 1409 AddToWorkList(Mul.Val); 1410 return Sub; 1411 } 1412 } 1413 1414 // undef % X -> 0 1415 if (N0.getOpcode() == ISD::UNDEF) 1416 return DAG.getConstant(0, VT); 1417 // X % undef -> undef 1418 if (N1.getOpcode() == ISD::UNDEF) 1419 return N1; 1420 1421 return SDOperand(); 1422} 1423 1424SDOperand DAGCombiner::visitMULHS(SDNode *N) { 1425 SDOperand N0 = N->getOperand(0); 1426 SDOperand N1 = N->getOperand(1); 1427 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1428 MVT::ValueType VT = N->getValueType(0); 1429 1430 // fold (mulhs x, 0) -> 0 1431 if (N1C && N1C->isNullValue()) 1432 return N1; 1433 // fold (mulhs x, 1) -> (sra x, size(x)-1) 1434 if (N1C && N1C->getValue() == 1) 1435 return DAG.getNode(ISD::SRA, N0.getValueType(), N0, 1436 DAG.getConstant(MVT::getSizeInBits(N0.getValueType())-1, 1437 TLI.getShiftAmountTy())); 1438 // fold (mulhs x, undef) -> 0 1439 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1440 return DAG.getConstant(0, VT); 1441 1442 return SDOperand(); 1443} 1444 1445SDOperand DAGCombiner::visitMULHU(SDNode *N) { 1446 SDOperand N0 = N->getOperand(0); 1447 SDOperand N1 = N->getOperand(1); 1448 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1449 MVT::ValueType VT = N->getValueType(0); 1450 1451 // fold (mulhu x, 0) -> 0 1452 if (N1C && N1C->isNullValue()) 1453 return N1; 1454 // fold (mulhu x, 1) -> 0 1455 if (N1C && N1C->getValue() == 1) 1456 return DAG.getConstant(0, N0.getValueType()); 1457 // fold (mulhu x, undef) -> 0 1458 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1459 return DAG.getConstant(0, VT); 1460 1461 return SDOperand(); 1462} 1463 1464/// SimplifyNodeWithTwoResults - Perform optimizations common to nodes that 1465/// compute two values. LoOp and HiOp give the opcodes for the two computations 1466/// that are being performed. Return true if a simplification was made. 1467/// 1468SDOperand DAGCombiner::SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp, 1469 unsigned HiOp) { 1470 // If the high half is not needed, just compute the low half. 1471 bool HiExists = N->hasAnyUseOfValue(1); 1472 if (!HiExists && 1473 (!AfterLegalize || 1474 TLI.isOperationLegal(LoOp, N->getValueType(0)))) { 1475 SDOperand Res = DAG.getNode(LoOp, N->getValueType(0), N->op_begin(), 1476 N->getNumOperands()); 1477 return CombineTo(N, Res, Res); 1478 } 1479 1480 // If the low half is not needed, just compute the high half. 1481 bool LoExists = N->hasAnyUseOfValue(0); 1482 if (!LoExists && 1483 (!AfterLegalize || 1484 TLI.isOperationLegal(HiOp, N->getValueType(1)))) { 1485 SDOperand Res = DAG.getNode(HiOp, N->getValueType(1), N->op_begin(), 1486 N->getNumOperands()); 1487 return CombineTo(N, Res, Res); 1488 } 1489 1490 // If both halves are used, return as it is. 1491 if (LoExists && HiExists) 1492 return SDOperand(); 1493 1494 // If the two computed results can be simplified separately, separate them. 1495 if (LoExists) { 1496 SDOperand Lo = DAG.getNode(LoOp, N->getValueType(0), 1497 N->op_begin(), N->getNumOperands()); 1498 AddToWorkList(Lo.Val); 1499 SDOperand LoOpt = combine(Lo.Val); 1500 if (LoOpt.Val && LoOpt.Val != Lo.Val && 1501 TLI.isOperationLegal(LoOpt.getOpcode(), LoOpt.getValueType())) 1502 return CombineTo(N, LoOpt, LoOpt); 1503 } 1504 1505 if (HiExists) { 1506 SDOperand Hi = DAG.getNode(HiOp, N->getValueType(1), 1507 N->op_begin(), N->getNumOperands()); 1508 AddToWorkList(Hi.Val); 1509 SDOperand HiOpt = combine(Hi.Val); 1510 if (HiOpt.Val && HiOpt != Hi && 1511 TLI.isOperationLegal(HiOpt.getOpcode(), HiOpt.getValueType())) 1512 return CombineTo(N, HiOpt, HiOpt); 1513 } 1514 return SDOperand(); 1515} 1516 1517SDOperand DAGCombiner::visitSMUL_LOHI(SDNode *N) { 1518 SDOperand Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHS); 1519 if (Res.Val) return Res; 1520 1521 return SDOperand(); 1522} 1523 1524SDOperand DAGCombiner::visitUMUL_LOHI(SDNode *N) { 1525 SDOperand Res = SimplifyNodeWithTwoResults(N, ISD::MUL, ISD::MULHU); 1526 if (Res.Val) return Res; 1527 1528 return SDOperand(); 1529} 1530 1531SDOperand DAGCombiner::visitSDIVREM(SDNode *N) { 1532 SDOperand Res = SimplifyNodeWithTwoResults(N, ISD::SDIV, ISD::SREM); 1533 if (Res.Val) return Res; 1534 1535 return SDOperand(); 1536} 1537 1538SDOperand DAGCombiner::visitUDIVREM(SDNode *N) { 1539 SDOperand Res = SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM); 1540 if (Res.Val) return Res; 1541 1542 return SDOperand(); 1543} 1544 1545/// SimplifyBinOpWithSameOpcodeHands - If this is a binary operator with 1546/// two operands of the same opcode, try to simplify it. 1547SDOperand DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) { 1548 SDOperand N0 = N->getOperand(0), N1 = N->getOperand(1); 1549 MVT::ValueType VT = N0.getValueType(); 1550 assert(N0.getOpcode() == N1.getOpcode() && "Bad input!"); 1551 1552 // For each of OP in AND/OR/XOR: 1553 // fold (OP (zext x), (zext y)) -> (zext (OP x, y)) 1554 // fold (OP (sext x), (sext y)) -> (sext (OP x, y)) 1555 // fold (OP (aext x), (aext y)) -> (aext (OP x, y)) 1556 // fold (OP (trunc x), (trunc y)) -> (trunc (OP x, y)) 1557 if ((N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND|| 1558 N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::TRUNCATE) && 1559 N0.getOperand(0).getValueType() == N1.getOperand(0).getValueType()) { 1560 SDOperand ORNode = DAG.getNode(N->getOpcode(), 1561 N0.getOperand(0).getValueType(), 1562 N0.getOperand(0), N1.getOperand(0)); 1563 AddToWorkList(ORNode.Val); 1564 return DAG.getNode(N0.getOpcode(), VT, ORNode); 1565 } 1566 1567 // For each of OP in SHL/SRL/SRA/AND... 1568 // fold (and (OP x, z), (OP y, z)) -> (OP (and x, y), z) 1569 // fold (or (OP x, z), (OP y, z)) -> (OP (or x, y), z) 1570 // fold (xor (OP x, z), (OP y, z)) -> (OP (xor x, y), z) 1571 if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL || 1572 N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::AND) && 1573 N0.getOperand(1) == N1.getOperand(1)) { 1574 SDOperand ORNode = DAG.getNode(N->getOpcode(), 1575 N0.getOperand(0).getValueType(), 1576 N0.getOperand(0), N1.getOperand(0)); 1577 AddToWorkList(ORNode.Val); 1578 return DAG.getNode(N0.getOpcode(), VT, ORNode, N0.getOperand(1)); 1579 } 1580 1581 return SDOperand(); 1582} 1583 1584SDOperand DAGCombiner::visitAND(SDNode *N) { 1585 SDOperand N0 = N->getOperand(0); 1586 SDOperand N1 = N->getOperand(1); 1587 SDOperand LL, LR, RL, RR, CC0, CC1; 1588 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1589 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1590 MVT::ValueType VT = N1.getValueType(); 1591 1592 // fold vector ops 1593 if (MVT::isVector(VT)) { 1594 SDOperand FoldedVOp = SimplifyVBinOp(N); 1595 if (FoldedVOp.Val) return FoldedVOp; 1596 } 1597 1598 // fold (and x, undef) -> 0 1599 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1600 return DAG.getConstant(0, VT); 1601 // fold (and c1, c2) -> c1&c2 1602 if (N0C && N1C) 1603 return DAG.getNode(ISD::AND, VT, N0, N1); 1604 // canonicalize constant to RHS 1605 if (N0C && !N1C) 1606 return DAG.getNode(ISD::AND, VT, N1, N0); 1607 // fold (and x, -1) -> x 1608 if (N1C && N1C->isAllOnesValue()) 1609 return N0; 1610 // if (and x, c) is known to be zero, return 0 1611 if (N1C && DAG.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT))) 1612 return DAG.getConstant(0, VT); 1613 // reassociate and 1614 SDOperand RAND = ReassociateOps(ISD::AND, N0, N1); 1615 if (RAND.Val != 0) 1616 return RAND; 1617 // fold (and (or x, 0xFFFF), 0xFF) -> 0xFF 1618 if (N1C && N0.getOpcode() == ISD::OR) 1619 if (ConstantSDNode *ORI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 1620 if ((ORI->getValue() & N1C->getValue()) == N1C->getValue()) 1621 return N1; 1622 // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits. 1623 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 1624 unsigned InMask = MVT::getIntVTBitMask(N0.getOperand(0).getValueType()); 1625 if (DAG.MaskedValueIsZero(N0.getOperand(0), 1626 ~N1C->getValue() & InMask)) { 1627 SDOperand Zext = DAG.getNode(ISD::ZERO_EXTEND, N0.getValueType(), 1628 N0.getOperand(0)); 1629 1630 // Replace uses of the AND with uses of the Zero extend node. 1631 CombineTo(N, Zext); 1632 1633 // We actually want to replace all uses of the any_extend with the 1634 // zero_extend, to avoid duplicating things. This will later cause this 1635 // AND to be folded. 1636 CombineTo(N0.Val, Zext); 1637 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1638 } 1639 } 1640 // fold (and (setcc x), (setcc y)) -> (setcc (and x, y)) 1641 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 1642 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 1643 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 1644 1645 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 1646 MVT::isInteger(LL.getValueType())) { 1647 // fold (X == 0) & (Y == 0) -> (X|Y == 0) 1648 if (cast<ConstantSDNode>(LR)->getValue() == 0 && Op1 == ISD::SETEQ) { 1649 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 1650 AddToWorkList(ORNode.Val); 1651 return DAG.getSetCC(VT, ORNode, LR, Op1); 1652 } 1653 // fold (X == -1) & (Y == -1) -> (X&Y == -1) 1654 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETEQ) { 1655 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL); 1656 AddToWorkList(ANDNode.Val); 1657 return DAG.getSetCC(VT, ANDNode, LR, Op1); 1658 } 1659 // fold (X > -1) & (Y > -1) -> (X|Y > -1) 1660 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && Op1 == ISD::SETGT) { 1661 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 1662 AddToWorkList(ORNode.Val); 1663 return DAG.getSetCC(VT, ORNode, LR, Op1); 1664 } 1665 } 1666 // canonicalize equivalent to ll == rl 1667 if (LL == RR && LR == RL) { 1668 Op1 = ISD::getSetCCSwappedOperands(Op1); 1669 std::swap(RL, RR); 1670 } 1671 if (LL == RL && LR == RR) { 1672 bool isInteger = MVT::isInteger(LL.getValueType()); 1673 ISD::CondCode Result = ISD::getSetCCAndOperation(Op0, Op1, isInteger); 1674 if (Result != ISD::SETCC_INVALID) 1675 return DAG.getSetCC(N0.getValueType(), LL, LR, Result); 1676 } 1677 } 1678 1679 // Simplify: and (op x...), (op y...) -> (op (and x, y)) 1680 if (N0.getOpcode() == N1.getOpcode()) { 1681 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N); 1682 if (Tmp.Val) return Tmp; 1683 } 1684 1685 // fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1) 1686 // fold (and (sra)) -> (and (srl)) when possible. 1687 if (!MVT::isVector(VT) && 1688 SimplifyDemandedBits(SDOperand(N, 0))) 1689 return SDOperand(N, 0); 1690 // fold (zext_inreg (extload x)) -> (zextload x) 1691 if (ISD::isEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val)) { 1692 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1693 MVT::ValueType EVT = LN0->getMemoryVT(); 1694 // If we zero all the possible extended bits, then we can turn this into 1695 // a zextload if we are running before legalize or the operation is legal. 1696 if (DAG.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) && 1697 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) { 1698 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 1699 LN0->getBasePtr(), LN0->getSrcValue(), 1700 LN0->getSrcValueOffset(), EVT, 1701 LN0->isVolatile(), 1702 LN0->getAlignment()); 1703 AddToWorkList(N); 1704 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 1705 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1706 } 1707 } 1708 // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use 1709 if (ISD::isSEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) && 1710 N0.hasOneUse()) { 1711 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1712 MVT::ValueType EVT = LN0->getMemoryVT(); 1713 // If we zero all the possible extended bits, then we can turn this into 1714 // a zextload if we are running before legalize or the operation is legal. 1715 if (DAG.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) && 1716 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) { 1717 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 1718 LN0->getBasePtr(), LN0->getSrcValue(), 1719 LN0->getSrcValueOffset(), EVT, 1720 LN0->isVolatile(), 1721 LN0->getAlignment()); 1722 AddToWorkList(N); 1723 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 1724 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1725 } 1726 } 1727 1728 // fold (and (load x), 255) -> (zextload x, i8) 1729 // fold (and (extload x, i16), 255) -> (zextload x, i8) 1730 if (N1C && N0.getOpcode() == ISD::LOAD) { 1731 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 1732 if (LN0->getExtensionType() != ISD::SEXTLOAD && 1733 LN0->isUnindexed() && N0.hasOneUse()) { 1734 MVT::ValueType EVT, LoadedVT; 1735 if (N1C->getValue() == 255) 1736 EVT = MVT::i8; 1737 else if (N1C->getValue() == 65535) 1738 EVT = MVT::i16; 1739 else if (N1C->getValue() == ~0U) 1740 EVT = MVT::i32; 1741 else 1742 EVT = MVT::Other; 1743 1744 LoadedVT = LN0->getMemoryVT(); 1745 if (EVT != MVT::Other && LoadedVT > EVT && 1746 (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) { 1747 MVT::ValueType PtrType = N0.getOperand(1).getValueType(); 1748 // For big endian targets, we need to add an offset to the pointer to 1749 // load the correct bytes. For little endian systems, we merely need to 1750 // read fewer bytes from the same pointer. 1751 unsigned LVTStoreBytes = MVT::getStoreSizeInBits(LoadedVT)/8; 1752 unsigned EVTStoreBytes = MVT::getStoreSizeInBits(EVT)/8; 1753 unsigned PtrOff = LVTStoreBytes - EVTStoreBytes; 1754 unsigned Alignment = LN0->getAlignment(); 1755 SDOperand NewPtr = LN0->getBasePtr(); 1756 if (TLI.isBigEndian()) { 1757 NewPtr = DAG.getNode(ISD::ADD, PtrType, NewPtr, 1758 DAG.getConstant(PtrOff, PtrType)); 1759 Alignment = MinAlign(Alignment, PtrOff); 1760 } 1761 AddToWorkList(NewPtr.Val); 1762 SDOperand Load = 1763 DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), NewPtr, 1764 LN0->getSrcValue(), LN0->getSrcValueOffset(), EVT, 1765 LN0->isVolatile(), Alignment); 1766 AddToWorkList(N); 1767 CombineTo(N0.Val, Load, Load.getValue(1)); 1768 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 1769 } 1770 } 1771 } 1772 1773 return SDOperand(); 1774} 1775 1776SDOperand DAGCombiner::visitOR(SDNode *N) { 1777 SDOperand N0 = N->getOperand(0); 1778 SDOperand N1 = N->getOperand(1); 1779 SDOperand LL, LR, RL, RR, CC0, CC1; 1780 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 1781 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 1782 MVT::ValueType VT = N1.getValueType(); 1783 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 1784 1785 // fold vector ops 1786 if (MVT::isVector(VT)) { 1787 SDOperand FoldedVOp = SimplifyVBinOp(N); 1788 if (FoldedVOp.Val) return FoldedVOp; 1789 } 1790 1791 // fold (or x, undef) -> -1 1792 if (N0.getOpcode() == ISD::UNDEF || N1.getOpcode() == ISD::UNDEF) 1793 return DAG.getConstant(~0ULL, VT); 1794 // fold (or c1, c2) -> c1|c2 1795 if (N0C && N1C) 1796 return DAG.getNode(ISD::OR, VT, N0, N1); 1797 // canonicalize constant to RHS 1798 if (N0C && !N1C) 1799 return DAG.getNode(ISD::OR, VT, N1, N0); 1800 // fold (or x, 0) -> x 1801 if (N1C && N1C->isNullValue()) 1802 return N0; 1803 // fold (or x, -1) -> -1 1804 if (N1C && N1C->isAllOnesValue()) 1805 return N1; 1806 // fold (or x, c) -> c iff (x & ~c) == 0 1807 if (N1C && 1808 DAG.MaskedValueIsZero(N0,~N1C->getValue() & (~0ULL>>(64-OpSizeInBits)))) 1809 return N1; 1810 // reassociate or 1811 SDOperand ROR = ReassociateOps(ISD::OR, N0, N1); 1812 if (ROR.Val != 0) 1813 return ROR; 1814 // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2) 1815 if (N1C && N0.getOpcode() == ISD::AND && N0.Val->hasOneUse() && 1816 isa<ConstantSDNode>(N0.getOperand(1))) { 1817 ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1)); 1818 return DAG.getNode(ISD::AND, VT, DAG.getNode(ISD::OR, VT, N0.getOperand(0), 1819 N1), 1820 DAG.getConstant(N1C->getValue() | C1->getValue(), VT)); 1821 } 1822 // fold (or (setcc x), (setcc y)) -> (setcc (or x, y)) 1823 if (isSetCCEquivalent(N0, LL, LR, CC0) && isSetCCEquivalent(N1, RL, RR, CC1)){ 1824 ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get(); 1825 ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get(); 1826 1827 if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 && 1828 MVT::isInteger(LL.getValueType())) { 1829 // fold (X != 0) | (Y != 0) -> (X|Y != 0) 1830 // fold (X < 0) | (Y < 0) -> (X|Y < 0) 1831 if (cast<ConstantSDNode>(LR)->getValue() == 0 && 1832 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) { 1833 SDOperand ORNode = DAG.getNode(ISD::OR, LR.getValueType(), LL, RL); 1834 AddToWorkList(ORNode.Val); 1835 return DAG.getSetCC(VT, ORNode, LR, Op1); 1836 } 1837 // fold (X != -1) | (Y != -1) -> (X&Y != -1) 1838 // fold (X > -1) | (Y > -1) -> (X&Y > -1) 1839 if (cast<ConstantSDNode>(LR)->isAllOnesValue() && 1840 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) { 1841 SDOperand ANDNode = DAG.getNode(ISD::AND, LR.getValueType(), LL, RL); 1842 AddToWorkList(ANDNode.Val); 1843 return DAG.getSetCC(VT, ANDNode, LR, Op1); 1844 } 1845 } 1846 // canonicalize equivalent to ll == rl 1847 if (LL == RR && LR == RL) { 1848 Op1 = ISD::getSetCCSwappedOperands(Op1); 1849 std::swap(RL, RR); 1850 } 1851 if (LL == RL && LR == RR) { 1852 bool isInteger = MVT::isInteger(LL.getValueType()); 1853 ISD::CondCode Result = ISD::getSetCCOrOperation(Op0, Op1, isInteger); 1854 if (Result != ISD::SETCC_INVALID) 1855 return DAG.getSetCC(N0.getValueType(), LL, LR, Result); 1856 } 1857 } 1858 1859 // Simplify: or (op x...), (op y...) -> (op (or x, y)) 1860 if (N0.getOpcode() == N1.getOpcode()) { 1861 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N); 1862 if (Tmp.Val) return Tmp; 1863 } 1864 1865 // (X & C1) | (Y & C2) -> (X|Y) & C3 if possible. 1866 if (N0.getOpcode() == ISD::AND && 1867 N1.getOpcode() == ISD::AND && 1868 N0.getOperand(1).getOpcode() == ISD::Constant && 1869 N1.getOperand(1).getOpcode() == ISD::Constant && 1870 // Don't increase # computations. 1871 (N0.Val->hasOneUse() || N1.Val->hasOneUse())) { 1872 // We can only do this xform if we know that bits from X that are set in C2 1873 // but not in C1 are already zero. Likewise for Y. 1874 uint64_t LHSMask = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 1875 uint64_t RHSMask = cast<ConstantSDNode>(N1.getOperand(1))->getValue(); 1876 1877 if (DAG.MaskedValueIsZero(N0.getOperand(0), RHSMask&~LHSMask) && 1878 DAG.MaskedValueIsZero(N1.getOperand(0), LHSMask&~RHSMask)) { 1879 SDOperand X =DAG.getNode(ISD::OR, VT, N0.getOperand(0), N1.getOperand(0)); 1880 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(LHSMask|RHSMask, VT)); 1881 } 1882 } 1883 1884 1885 // See if this is some rotate idiom. 1886 if (SDNode *Rot = MatchRotate(N0, N1)) 1887 return SDOperand(Rot, 0); 1888 1889 return SDOperand(); 1890} 1891 1892 1893/// MatchRotateHalf - Match "(X shl/srl V1) & V2" where V2 may not be present. 1894static bool MatchRotateHalf(SDOperand Op, SDOperand &Shift, SDOperand &Mask) { 1895 if (Op.getOpcode() == ISD::AND) { 1896 if (isa<ConstantSDNode>(Op.getOperand(1))) { 1897 Mask = Op.getOperand(1); 1898 Op = Op.getOperand(0); 1899 } else { 1900 return false; 1901 } 1902 } 1903 1904 if (Op.getOpcode() == ISD::SRL || Op.getOpcode() == ISD::SHL) { 1905 Shift = Op; 1906 return true; 1907 } 1908 return false; 1909} 1910 1911 1912// MatchRotate - Handle an 'or' of two operands. If this is one of the many 1913// idioms for rotate, and if the target supports rotation instructions, generate 1914// a rot[lr]. 1915SDNode *DAGCombiner::MatchRotate(SDOperand LHS, SDOperand RHS) { 1916 // Must be a legal type. Expanded an promoted things won't work with rotates. 1917 MVT::ValueType VT = LHS.getValueType(); 1918 if (!TLI.isTypeLegal(VT)) return 0; 1919 1920 // The target must have at least one rotate flavor. 1921 bool HasROTL = TLI.isOperationLegal(ISD::ROTL, VT); 1922 bool HasROTR = TLI.isOperationLegal(ISD::ROTR, VT); 1923 if (!HasROTL && !HasROTR) return 0; 1924 1925 // Match "(X shl/srl V1) & V2" where V2 may not be present. 1926 SDOperand LHSShift; // The shift. 1927 SDOperand LHSMask; // AND value if any. 1928 if (!MatchRotateHalf(LHS, LHSShift, LHSMask)) 1929 return 0; // Not part of a rotate. 1930 1931 SDOperand RHSShift; // The shift. 1932 SDOperand RHSMask; // AND value if any. 1933 if (!MatchRotateHalf(RHS, RHSShift, RHSMask)) 1934 return 0; // Not part of a rotate. 1935 1936 if (LHSShift.getOperand(0) != RHSShift.getOperand(0)) 1937 return 0; // Not shifting the same value. 1938 1939 if (LHSShift.getOpcode() == RHSShift.getOpcode()) 1940 return 0; // Shifts must disagree. 1941 1942 // Canonicalize shl to left side in a shl/srl pair. 1943 if (RHSShift.getOpcode() == ISD::SHL) { 1944 std::swap(LHS, RHS); 1945 std::swap(LHSShift, RHSShift); 1946 std::swap(LHSMask , RHSMask ); 1947 } 1948 1949 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 1950 SDOperand LHSShiftArg = LHSShift.getOperand(0); 1951 SDOperand LHSShiftAmt = LHSShift.getOperand(1); 1952 SDOperand RHSShiftAmt = RHSShift.getOperand(1); 1953 1954 // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1) 1955 // fold (or (shl x, C1), (srl x, C2)) -> (rotr x, C2) 1956 if (LHSShiftAmt.getOpcode() == ISD::Constant && 1957 RHSShiftAmt.getOpcode() == ISD::Constant) { 1958 uint64_t LShVal = cast<ConstantSDNode>(LHSShiftAmt)->getValue(); 1959 uint64_t RShVal = cast<ConstantSDNode>(RHSShiftAmt)->getValue(); 1960 if ((LShVal + RShVal) != OpSizeInBits) 1961 return 0; 1962 1963 SDOperand Rot; 1964 if (HasROTL) 1965 Rot = DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt); 1966 else 1967 Rot = DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt); 1968 1969 // If there is an AND of either shifted operand, apply it to the result. 1970 if (LHSMask.Val || RHSMask.Val) { 1971 uint64_t Mask = MVT::getIntVTBitMask(VT); 1972 1973 if (LHSMask.Val) { 1974 uint64_t RHSBits = (1ULL << LShVal)-1; 1975 Mask &= cast<ConstantSDNode>(LHSMask)->getValue() | RHSBits; 1976 } 1977 if (RHSMask.Val) { 1978 uint64_t LHSBits = ~((1ULL << (OpSizeInBits-RShVal))-1); 1979 Mask &= cast<ConstantSDNode>(RHSMask)->getValue() | LHSBits; 1980 } 1981 1982 Rot = DAG.getNode(ISD::AND, VT, Rot, DAG.getConstant(Mask, VT)); 1983 } 1984 1985 return Rot.Val; 1986 } 1987 1988 // If there is a mask here, and we have a variable shift, we can't be sure 1989 // that we're masking out the right stuff. 1990 if (LHSMask.Val || RHSMask.Val) 1991 return 0; 1992 1993 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotl x, y) 1994 // fold (or (shl x, y), (srl x, (sub 32, y))) -> (rotr x, (sub 32, y)) 1995 if (RHSShiftAmt.getOpcode() == ISD::SUB && 1996 LHSShiftAmt == RHSShiftAmt.getOperand(1)) { 1997 if (ConstantSDNode *SUBC = 1998 dyn_cast<ConstantSDNode>(RHSShiftAmt.getOperand(0))) { 1999 if (SUBC->getValue() == OpSizeInBits) 2000 if (HasROTL) 2001 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val; 2002 else 2003 return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).Val; 2004 } 2005 } 2006 2007 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotr x, y) 2008 // fold (or (shl x, (sub 32, y)), (srl x, r)) -> (rotl x, (sub 32, y)) 2009 if (LHSShiftAmt.getOpcode() == ISD::SUB && 2010 RHSShiftAmt == LHSShiftAmt.getOperand(1)) { 2011 if (ConstantSDNode *SUBC = 2012 dyn_cast<ConstantSDNode>(LHSShiftAmt.getOperand(0))) { 2013 if (SUBC->getValue() == OpSizeInBits) 2014 if (HasROTL) 2015 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val; 2016 else 2017 return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).Val; 2018 } 2019 } 2020 2021 // Look for sign/zext/any-extended cases: 2022 if ((LHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 2023 || LHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 2024 || LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND) && 2025 (RHSShiftAmt.getOpcode() == ISD::SIGN_EXTEND 2026 || RHSShiftAmt.getOpcode() == ISD::ZERO_EXTEND 2027 || RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND)) { 2028 SDOperand LExtOp0 = LHSShiftAmt.getOperand(0); 2029 SDOperand RExtOp0 = RHSShiftAmt.getOperand(0); 2030 if (RExtOp0.getOpcode() == ISD::SUB && 2031 RExtOp0.getOperand(1) == LExtOp0) { 2032 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 2033 // (rotr x, y) 2034 // fold (or (shl x, (*ext y)), (srl x, (*ext (sub 32, y)))) -> 2035 // (rotl x, (sub 32, y)) 2036 if (ConstantSDNode *SUBC = cast<ConstantSDNode>(RExtOp0.getOperand(0))) { 2037 if (SUBC->getValue() == OpSizeInBits) { 2038 if (HasROTL) 2039 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val; 2040 else 2041 return DAG.getNode(ISD::ROTR, VT, LHSShiftArg, RHSShiftAmt).Val; 2042 } 2043 } 2044 } else if (LExtOp0.getOpcode() == ISD::SUB && 2045 RExtOp0 == LExtOp0.getOperand(1)) { 2046 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext r))) -> 2047 // (rotl x, y) 2048 // fold (or (shl x, (*ext (sub 32, y))), (srl x, (*ext r))) -> 2049 // (rotr x, (sub 32, y)) 2050 if (ConstantSDNode *SUBC = cast<ConstantSDNode>(LExtOp0.getOperand(0))) { 2051 if (SUBC->getValue() == OpSizeInBits) { 2052 if (HasROTL) 2053 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, RHSShiftAmt).Val; 2054 else 2055 return DAG.getNode(ISD::ROTL, VT, LHSShiftArg, LHSShiftAmt).Val; 2056 } 2057 } 2058 } 2059 } 2060 2061 return 0; 2062} 2063 2064 2065SDOperand DAGCombiner::visitXOR(SDNode *N) { 2066 SDOperand N0 = N->getOperand(0); 2067 SDOperand N1 = N->getOperand(1); 2068 SDOperand LHS, RHS, CC; 2069 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2070 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2071 MVT::ValueType VT = N0.getValueType(); 2072 2073 // fold vector ops 2074 if (MVT::isVector(VT)) { 2075 SDOperand FoldedVOp = SimplifyVBinOp(N); 2076 if (FoldedVOp.Val) return FoldedVOp; 2077 } 2078 2079 // fold (xor x, undef) -> undef 2080 if (N0.getOpcode() == ISD::UNDEF) 2081 return N0; 2082 if (N1.getOpcode() == ISD::UNDEF) 2083 return N1; 2084 // fold (xor c1, c2) -> c1^c2 2085 if (N0C && N1C) 2086 return DAG.getNode(ISD::XOR, VT, N0, N1); 2087 // canonicalize constant to RHS 2088 if (N0C && !N1C) 2089 return DAG.getNode(ISD::XOR, VT, N1, N0); 2090 // fold (xor x, 0) -> x 2091 if (N1C && N1C->isNullValue()) 2092 return N0; 2093 // reassociate xor 2094 SDOperand RXOR = ReassociateOps(ISD::XOR, N0, N1); 2095 if (RXOR.Val != 0) 2096 return RXOR; 2097 // fold !(x cc y) -> (x !cc y) 2098 if (N1C && N1C->getValue() == 1 && isSetCCEquivalent(N0, LHS, RHS, CC)) { 2099 bool isInt = MVT::isInteger(LHS.getValueType()); 2100 ISD::CondCode NotCC = ISD::getSetCCInverse(cast<CondCodeSDNode>(CC)->get(), 2101 isInt); 2102 if (N0.getOpcode() == ISD::SETCC) 2103 return DAG.getSetCC(VT, LHS, RHS, NotCC); 2104 if (N0.getOpcode() == ISD::SELECT_CC) 2105 return DAG.getSelectCC(LHS, RHS, N0.getOperand(2),N0.getOperand(3),NotCC); 2106 assert(0 && "Unhandled SetCC Equivalent!"); 2107 abort(); 2108 } 2109 // fold (not (zext (setcc x, y))) -> (zext (not (setcc x, y))) 2110 if (N1C && N1C->getValue() == 1 && N0.getOpcode() == ISD::ZERO_EXTEND && 2111 N0.Val->hasOneUse() && isSetCCEquivalent(N0.getOperand(0), LHS, RHS, CC)){ 2112 SDOperand V = N0.getOperand(0); 2113 V = DAG.getNode(ISD::XOR, V.getValueType(), V, 2114 DAG.getConstant(1, V.getValueType())); 2115 AddToWorkList(V.Val); 2116 return DAG.getNode(ISD::ZERO_EXTEND, VT, V); 2117 } 2118 2119 // fold !(x or y) -> (!x and !y) iff x or y are setcc 2120 if (N1C && N1C->getValue() == 1 && VT == MVT::i1 && 2121 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 2122 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1); 2123 if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) { 2124 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 2125 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS 2126 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS 2127 AddToWorkList(LHS.Val); AddToWorkList(RHS.Val); 2128 return DAG.getNode(NewOpcode, VT, LHS, RHS); 2129 } 2130 } 2131 // fold !(x or y) -> (!x and !y) iff x or y are constants 2132 if (N1C && N1C->isAllOnesValue() && 2133 (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) { 2134 SDOperand LHS = N0.getOperand(0), RHS = N0.getOperand(1); 2135 if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) { 2136 unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND; 2137 LHS = DAG.getNode(ISD::XOR, VT, LHS, N1); // RHS = ~LHS 2138 RHS = DAG.getNode(ISD::XOR, VT, RHS, N1); // RHS = ~RHS 2139 AddToWorkList(LHS.Val); AddToWorkList(RHS.Val); 2140 return DAG.getNode(NewOpcode, VT, LHS, RHS); 2141 } 2142 } 2143 // fold (xor (xor x, c1), c2) -> (xor x, c1^c2) 2144 if (N1C && N0.getOpcode() == ISD::XOR) { 2145 ConstantSDNode *N00C = dyn_cast<ConstantSDNode>(N0.getOperand(0)); 2146 ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 2147 if (N00C) 2148 return DAG.getNode(ISD::XOR, VT, N0.getOperand(1), 2149 DAG.getConstant(N1C->getValue()^N00C->getValue(), VT)); 2150 if (N01C) 2151 return DAG.getNode(ISD::XOR, VT, N0.getOperand(0), 2152 DAG.getConstant(N1C->getValue()^N01C->getValue(), VT)); 2153 } 2154 // fold (xor x, x) -> 0 2155 if (N0 == N1) { 2156 if (!MVT::isVector(VT)) { 2157 return DAG.getConstant(0, VT); 2158 } else if (!AfterLegalize || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) { 2159 // Produce a vector of zeros. 2160 SDOperand El = DAG.getConstant(0, MVT::getVectorElementType(VT)); 2161 std::vector<SDOperand> Ops(MVT::getVectorNumElements(VT), El); 2162 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 2163 } 2164 } 2165 2166 // Simplify: xor (op x...), (op y...) -> (op (xor x, y)) 2167 if (N0.getOpcode() == N1.getOpcode()) { 2168 SDOperand Tmp = SimplifyBinOpWithSameOpcodeHands(N); 2169 if (Tmp.Val) return Tmp; 2170 } 2171 2172 // Simplify the expression using non-local knowledge. 2173 if (!MVT::isVector(VT) && 2174 SimplifyDemandedBits(SDOperand(N, 0))) 2175 return SDOperand(N, 0); 2176 2177 return SDOperand(); 2178} 2179 2180/// visitShiftByConstant - Handle transforms common to the three shifts, when 2181/// the shift amount is a constant. 2182SDOperand DAGCombiner::visitShiftByConstant(SDNode *N, unsigned Amt) { 2183 SDNode *LHS = N->getOperand(0).Val; 2184 if (!LHS->hasOneUse()) return SDOperand(); 2185 2186 // We want to pull some binops through shifts, so that we have (and (shift)) 2187 // instead of (shift (and)), likewise for add, or, xor, etc. This sort of 2188 // thing happens with address calculations, so it's important to canonicalize 2189 // it. 2190 bool HighBitSet = false; // Can we transform this if the high bit is set? 2191 2192 switch (LHS->getOpcode()) { 2193 default: return SDOperand(); 2194 case ISD::OR: 2195 case ISD::XOR: 2196 HighBitSet = false; // We can only transform sra if the high bit is clear. 2197 break; 2198 case ISD::AND: 2199 HighBitSet = true; // We can only transform sra if the high bit is set. 2200 break; 2201 case ISD::ADD: 2202 if (N->getOpcode() != ISD::SHL) 2203 return SDOperand(); // only shl(add) not sr[al](add). 2204 HighBitSet = false; // We can only transform sra if the high bit is clear. 2205 break; 2206 } 2207 2208 // We require the RHS of the binop to be a constant as well. 2209 ConstantSDNode *BinOpCst = dyn_cast<ConstantSDNode>(LHS->getOperand(1)); 2210 if (!BinOpCst) return SDOperand(); 2211 2212 2213 // FIXME: disable this for unless the input to the binop is a shift by a 2214 // constant. If it is not a shift, it pessimizes some common cases like: 2215 // 2216 //void foo(int *X, int i) { X[i & 1235] = 1; } 2217 //int bar(int *X, int i) { return X[i & 255]; } 2218 SDNode *BinOpLHSVal = LHS->getOperand(0).Val; 2219 if ((BinOpLHSVal->getOpcode() != ISD::SHL && 2220 BinOpLHSVal->getOpcode() != ISD::SRA && 2221 BinOpLHSVal->getOpcode() != ISD::SRL) || 2222 !isa<ConstantSDNode>(BinOpLHSVal->getOperand(1))) 2223 return SDOperand(); 2224 2225 MVT::ValueType VT = N->getValueType(0); 2226 2227 // If this is a signed shift right, and the high bit is modified 2228 // by the logical operation, do not perform the transformation. 2229 // The highBitSet boolean indicates the value of the high bit of 2230 // the constant which would cause it to be modified for this 2231 // operation. 2232 if (N->getOpcode() == ISD::SRA) { 2233 uint64_t BinOpRHSSign = BinOpCst->getValue() >> MVT::getSizeInBits(VT)-1; 2234 if ((bool)BinOpRHSSign != HighBitSet) 2235 return SDOperand(); 2236 } 2237 2238 // Fold the constants, shifting the binop RHS by the shift amount. 2239 SDOperand NewRHS = DAG.getNode(N->getOpcode(), N->getValueType(0), 2240 LHS->getOperand(1), N->getOperand(1)); 2241 2242 // Create the new shift. 2243 SDOperand NewShift = DAG.getNode(N->getOpcode(), VT, LHS->getOperand(0), 2244 N->getOperand(1)); 2245 2246 // Create the new binop. 2247 return DAG.getNode(LHS->getOpcode(), VT, NewShift, NewRHS); 2248} 2249 2250 2251SDOperand DAGCombiner::visitSHL(SDNode *N) { 2252 SDOperand N0 = N->getOperand(0); 2253 SDOperand N1 = N->getOperand(1); 2254 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2255 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2256 MVT::ValueType VT = N0.getValueType(); 2257 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 2258 2259 // fold (shl c1, c2) -> c1<<c2 2260 if (N0C && N1C) 2261 return DAG.getNode(ISD::SHL, VT, N0, N1); 2262 // fold (shl 0, x) -> 0 2263 if (N0C && N0C->isNullValue()) 2264 return N0; 2265 // fold (shl x, c >= size(x)) -> undef 2266 if (N1C && N1C->getValue() >= OpSizeInBits) 2267 return DAG.getNode(ISD::UNDEF, VT); 2268 // fold (shl x, 0) -> x 2269 if (N1C && N1C->isNullValue()) 2270 return N0; 2271 // if (shl x, c) is known to be zero, return 0 2272 if (DAG.MaskedValueIsZero(SDOperand(N, 0), MVT::getIntVTBitMask(VT))) 2273 return DAG.getConstant(0, VT); 2274 if (N1C && SimplifyDemandedBits(SDOperand(N, 0))) 2275 return SDOperand(N, 0); 2276 // fold (shl (shl x, c1), c2) -> 0 or (shl x, c1+c2) 2277 if (N1C && N0.getOpcode() == ISD::SHL && 2278 N0.getOperand(1).getOpcode() == ISD::Constant) { 2279 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 2280 uint64_t c2 = N1C->getValue(); 2281 if (c1 + c2 > OpSizeInBits) 2282 return DAG.getConstant(0, VT); 2283 return DAG.getNode(ISD::SHL, VT, N0.getOperand(0), 2284 DAG.getConstant(c1 + c2, N1.getValueType())); 2285 } 2286 // fold (shl (srl x, c1), c2) -> (shl (and x, -1 << c1), c2-c1) or 2287 // (srl (and x, -1 << c1), c1-c2) 2288 if (N1C && N0.getOpcode() == ISD::SRL && 2289 N0.getOperand(1).getOpcode() == ISD::Constant) { 2290 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 2291 uint64_t c2 = N1C->getValue(); 2292 SDOperand Mask = DAG.getNode(ISD::AND, VT, N0.getOperand(0), 2293 DAG.getConstant(~0ULL << c1, VT)); 2294 if (c2 > c1) 2295 return DAG.getNode(ISD::SHL, VT, Mask, 2296 DAG.getConstant(c2-c1, N1.getValueType())); 2297 else 2298 return DAG.getNode(ISD::SRL, VT, Mask, 2299 DAG.getConstant(c1-c2, N1.getValueType())); 2300 } 2301 // fold (shl (sra x, c1), c1) -> (and x, -1 << c1) 2302 if (N1C && N0.getOpcode() == ISD::SRA && N1 == N0.getOperand(1)) 2303 return DAG.getNode(ISD::AND, VT, N0.getOperand(0), 2304 DAG.getConstant(~0ULL << N1C->getValue(), VT)); 2305 2306 return N1C ? visitShiftByConstant(N, N1C->getValue()) : SDOperand(); 2307} 2308 2309SDOperand DAGCombiner::visitSRA(SDNode *N) { 2310 SDOperand N0 = N->getOperand(0); 2311 SDOperand N1 = N->getOperand(1); 2312 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2313 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2314 MVT::ValueType VT = N0.getValueType(); 2315 2316 // fold (sra c1, c2) -> c1>>c2 2317 if (N0C && N1C) 2318 return DAG.getNode(ISD::SRA, VT, N0, N1); 2319 // fold (sra 0, x) -> 0 2320 if (N0C && N0C->isNullValue()) 2321 return N0; 2322 // fold (sra -1, x) -> -1 2323 if (N0C && N0C->isAllOnesValue()) 2324 return N0; 2325 // fold (sra x, c >= size(x)) -> undef 2326 if (N1C && N1C->getValue() >= MVT::getSizeInBits(VT)) 2327 return DAG.getNode(ISD::UNDEF, VT); 2328 // fold (sra x, 0) -> x 2329 if (N1C && N1C->isNullValue()) 2330 return N0; 2331 // fold (sra (shl x, c1), c1) -> sext_inreg for some c1 and target supports 2332 // sext_inreg. 2333 if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) { 2334 unsigned LowBits = MVT::getSizeInBits(VT) - (unsigned)N1C->getValue(); 2335 MVT::ValueType EVT; 2336 switch (LowBits) { 2337 default: EVT = MVT::Other; break; 2338 case 1: EVT = MVT::i1; break; 2339 case 8: EVT = MVT::i8; break; 2340 case 16: EVT = MVT::i16; break; 2341 case 32: EVT = MVT::i32; break; 2342 } 2343 if (EVT > MVT::Other && TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, EVT)) 2344 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), 2345 DAG.getValueType(EVT)); 2346 } 2347 2348 // fold (sra (sra x, c1), c2) -> (sra x, c1+c2) 2349 if (N1C && N0.getOpcode() == ISD::SRA) { 2350 if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 2351 unsigned Sum = N1C->getValue() + C1->getValue(); 2352 if (Sum >= MVT::getSizeInBits(VT)) Sum = MVT::getSizeInBits(VT)-1; 2353 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0), 2354 DAG.getConstant(Sum, N1C->getValueType(0))); 2355 } 2356 } 2357 2358 // Simplify, based on bits shifted out of the LHS. 2359 if (N1C && SimplifyDemandedBits(SDOperand(N, 0))) 2360 return SDOperand(N, 0); 2361 2362 2363 // If the sign bit is known to be zero, switch this to a SRL. 2364 if (DAG.MaskedValueIsZero(N0, MVT::getIntVTSignBit(VT))) 2365 return DAG.getNode(ISD::SRL, VT, N0, N1); 2366 2367 return N1C ? visitShiftByConstant(N, N1C->getValue()) : SDOperand(); 2368} 2369 2370SDOperand DAGCombiner::visitSRL(SDNode *N) { 2371 SDOperand N0 = N->getOperand(0); 2372 SDOperand N1 = N->getOperand(1); 2373 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2374 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2375 MVT::ValueType VT = N0.getValueType(); 2376 unsigned OpSizeInBits = MVT::getSizeInBits(VT); 2377 2378 // fold (srl c1, c2) -> c1 >>u c2 2379 if (N0C && N1C) 2380 return DAG.getNode(ISD::SRL, VT, N0, N1); 2381 // fold (srl 0, x) -> 0 2382 if (N0C && N0C->isNullValue()) 2383 return N0; 2384 // fold (srl x, c >= size(x)) -> undef 2385 if (N1C && N1C->getValue() >= OpSizeInBits) 2386 return DAG.getNode(ISD::UNDEF, VT); 2387 // fold (srl x, 0) -> x 2388 if (N1C && N1C->isNullValue()) 2389 return N0; 2390 // if (srl x, c) is known to be zero, return 0 2391 if (N1C && DAG.MaskedValueIsZero(SDOperand(N, 0), ~0ULL >> (64-OpSizeInBits))) 2392 return DAG.getConstant(0, VT); 2393 2394 // fold (srl (srl x, c1), c2) -> 0 or (srl x, c1+c2) 2395 if (N1C && N0.getOpcode() == ISD::SRL && 2396 N0.getOperand(1).getOpcode() == ISD::Constant) { 2397 uint64_t c1 = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 2398 uint64_t c2 = N1C->getValue(); 2399 if (c1 + c2 > OpSizeInBits) 2400 return DAG.getConstant(0, VT); 2401 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0), 2402 DAG.getConstant(c1 + c2, N1.getValueType())); 2403 } 2404 2405 // fold (srl (anyextend x), c) -> (anyextend (srl x, c)) 2406 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { 2407 // Shifting in all undef bits? 2408 MVT::ValueType SmallVT = N0.getOperand(0).getValueType(); 2409 if (N1C->getValue() >= MVT::getSizeInBits(SmallVT)) 2410 return DAG.getNode(ISD::UNDEF, VT); 2411 2412 SDOperand SmallShift = DAG.getNode(ISD::SRL, SmallVT, N0.getOperand(0), N1); 2413 AddToWorkList(SmallShift.Val); 2414 return DAG.getNode(ISD::ANY_EXTEND, VT, SmallShift); 2415 } 2416 2417 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign 2418 // bit, which is unmodified by sra. 2419 if (N1C && N1C->getValue()+1 == MVT::getSizeInBits(VT)) { 2420 if (N0.getOpcode() == ISD::SRA) 2421 return DAG.getNode(ISD::SRL, VT, N0.getOperand(0), N1); 2422 } 2423 2424 // fold (srl (ctlz x), "5") -> x iff x has one bit set (the low bit). 2425 if (N1C && N0.getOpcode() == ISD::CTLZ && 2426 N1C->getValue() == Log2_32(MVT::getSizeInBits(VT))) { 2427 uint64_t KnownZero, KnownOne, Mask = MVT::getIntVTBitMask(VT); 2428 DAG.ComputeMaskedBits(N0.getOperand(0), Mask, KnownZero, KnownOne); 2429 2430 // If any of the input bits are KnownOne, then the input couldn't be all 2431 // zeros, thus the result of the srl will always be zero. 2432 if (KnownOne) return DAG.getConstant(0, VT); 2433 2434 // If all of the bits input the to ctlz node are known to be zero, then 2435 // the result of the ctlz is "32" and the result of the shift is one. 2436 uint64_t UnknownBits = ~KnownZero & Mask; 2437 if (UnknownBits == 0) return DAG.getConstant(1, VT); 2438 2439 // Otherwise, check to see if there is exactly one bit input to the ctlz. 2440 if ((UnknownBits & (UnknownBits-1)) == 0) { 2441 // Okay, we know that only that the single bit specified by UnknownBits 2442 // could be set on input to the CTLZ node. If this bit is set, the SRL 2443 // will return 0, if it is clear, it returns 1. Change the CTLZ/SRL pair 2444 // to an SRL,XOR pair, which is likely to simplify more. 2445 unsigned ShAmt = CountTrailingZeros_64(UnknownBits); 2446 SDOperand Op = N0.getOperand(0); 2447 if (ShAmt) { 2448 Op = DAG.getNode(ISD::SRL, VT, Op, 2449 DAG.getConstant(ShAmt, TLI.getShiftAmountTy())); 2450 AddToWorkList(Op.Val); 2451 } 2452 return DAG.getNode(ISD::XOR, VT, Op, DAG.getConstant(1, VT)); 2453 } 2454 } 2455 2456 // fold operands of srl based on knowledge that the low bits are not 2457 // demanded. 2458 if (N1C && SimplifyDemandedBits(SDOperand(N, 0))) 2459 return SDOperand(N, 0); 2460 2461 return N1C ? visitShiftByConstant(N, N1C->getValue()) : SDOperand(); 2462} 2463 2464SDOperand DAGCombiner::visitCTLZ(SDNode *N) { 2465 SDOperand N0 = N->getOperand(0); 2466 MVT::ValueType VT = N->getValueType(0); 2467 2468 // fold (ctlz c1) -> c2 2469 if (isa<ConstantSDNode>(N0)) 2470 return DAG.getNode(ISD::CTLZ, VT, N0); 2471 return SDOperand(); 2472} 2473 2474SDOperand DAGCombiner::visitCTTZ(SDNode *N) { 2475 SDOperand N0 = N->getOperand(0); 2476 MVT::ValueType VT = N->getValueType(0); 2477 2478 // fold (cttz c1) -> c2 2479 if (isa<ConstantSDNode>(N0)) 2480 return DAG.getNode(ISD::CTTZ, VT, N0); 2481 return SDOperand(); 2482} 2483 2484SDOperand DAGCombiner::visitCTPOP(SDNode *N) { 2485 SDOperand N0 = N->getOperand(0); 2486 MVT::ValueType VT = N->getValueType(0); 2487 2488 // fold (ctpop c1) -> c2 2489 if (isa<ConstantSDNode>(N0)) 2490 return DAG.getNode(ISD::CTPOP, VT, N0); 2491 return SDOperand(); 2492} 2493 2494SDOperand DAGCombiner::visitSELECT(SDNode *N) { 2495 SDOperand N0 = N->getOperand(0); 2496 SDOperand N1 = N->getOperand(1); 2497 SDOperand N2 = N->getOperand(2); 2498 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 2499 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 2500 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2); 2501 MVT::ValueType VT = N->getValueType(0); 2502 MVT::ValueType VT0 = N0.getValueType(); 2503 2504 // fold select C, X, X -> X 2505 if (N1 == N2) 2506 return N1; 2507 // fold select true, X, Y -> X 2508 if (N0C && !N0C->isNullValue()) 2509 return N1; 2510 // fold select false, X, Y -> Y 2511 if (N0C && N0C->isNullValue()) 2512 return N2; 2513 // fold select C, 1, X -> C | X 2514 if (MVT::i1 == VT && N1C && N1C->getValue() == 1) 2515 return DAG.getNode(ISD::OR, VT, N0, N2); 2516 // fold select C, 0, 1 -> ~C 2517 if (MVT::isInteger(VT) && MVT::isInteger(VT0) && 2518 N1C && N2C && N1C->isNullValue() && N2C->getValue() == 1) { 2519 SDOperand XORNode = DAG.getNode(ISD::XOR, VT0, N0, DAG.getConstant(1, VT0)); 2520 if (VT == VT0) 2521 return XORNode; 2522 AddToWorkList(XORNode.Val); 2523 if (MVT::getSizeInBits(VT) > MVT::getSizeInBits(VT0)) 2524 return DAG.getNode(ISD::ZERO_EXTEND, VT, XORNode); 2525 return DAG.getNode(ISD::TRUNCATE, VT, XORNode); 2526 } 2527 // fold select C, 0, X -> ~C & X 2528 if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) { 2529 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT)); 2530 AddToWorkList(XORNode.Val); 2531 return DAG.getNode(ISD::AND, VT, XORNode, N2); 2532 } 2533 // fold select C, X, 1 -> ~C | X 2534 if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getValue() == 1) { 2535 SDOperand XORNode = DAG.getNode(ISD::XOR, VT, N0, DAG.getConstant(1, VT)); 2536 AddToWorkList(XORNode.Val); 2537 return DAG.getNode(ISD::OR, VT, XORNode, N1); 2538 } 2539 // fold select C, X, 0 -> C & X 2540 // FIXME: this should check for C type == X type, not i1? 2541 if (MVT::i1 == VT && N2C && N2C->isNullValue()) 2542 return DAG.getNode(ISD::AND, VT, N0, N1); 2543 // fold X ? X : Y --> X ? 1 : Y --> X | Y 2544 if (MVT::i1 == VT && N0 == N1) 2545 return DAG.getNode(ISD::OR, VT, N0, N2); 2546 // fold X ? Y : X --> X ? Y : 0 --> X & Y 2547 if (MVT::i1 == VT && N0 == N2) 2548 return DAG.getNode(ISD::AND, VT, N0, N1); 2549 2550 // If we can fold this based on the true/false value, do so. 2551 if (SimplifySelectOps(N, N1, N2)) 2552 return SDOperand(N, 0); // Don't revisit N. 2553 2554 // fold selects based on a setcc into other things, such as min/max/abs 2555 if (N0.getOpcode() == ISD::SETCC) 2556 // FIXME: 2557 // Check against MVT::Other for SELECT_CC, which is a workaround for targets 2558 // having to say they don't support SELECT_CC on every type the DAG knows 2559 // about, since there is no way to mark an opcode illegal at all value types 2560 if (TLI.isOperationLegal(ISD::SELECT_CC, MVT::Other)) 2561 return DAG.getNode(ISD::SELECT_CC, VT, N0.getOperand(0), N0.getOperand(1), 2562 N1, N2, N0.getOperand(2)); 2563 else 2564 return SimplifySelect(N0, N1, N2); 2565 return SDOperand(); 2566} 2567 2568SDOperand DAGCombiner::visitSELECT_CC(SDNode *N) { 2569 SDOperand N0 = N->getOperand(0); 2570 SDOperand N1 = N->getOperand(1); 2571 SDOperand N2 = N->getOperand(2); 2572 SDOperand N3 = N->getOperand(3); 2573 SDOperand N4 = N->getOperand(4); 2574 ISD::CondCode CC = cast<CondCodeSDNode>(N4)->get(); 2575 2576 // fold select_cc lhs, rhs, x, x, cc -> x 2577 if (N2 == N3) 2578 return N2; 2579 2580 // Determine if the condition we're dealing with is constant 2581 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false); 2582 if (SCC.Val) AddToWorkList(SCC.Val); 2583 2584 if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val)) { 2585 if (SCCC->getValue()) 2586 return N2; // cond always true -> true val 2587 else 2588 return N3; // cond always false -> false val 2589 } 2590 2591 // Fold to a simpler select_cc 2592 if (SCC.Val && SCC.getOpcode() == ISD::SETCC) 2593 return DAG.getNode(ISD::SELECT_CC, N2.getValueType(), 2594 SCC.getOperand(0), SCC.getOperand(1), N2, N3, 2595 SCC.getOperand(2)); 2596 2597 // If we can fold this based on the true/false value, do so. 2598 if (SimplifySelectOps(N, N2, N3)) 2599 return SDOperand(N, 0); // Don't revisit N. 2600 2601 // fold select_cc into other things, such as min/max/abs 2602 return SimplifySelectCC(N0, N1, N2, N3, CC); 2603} 2604 2605SDOperand DAGCombiner::visitSETCC(SDNode *N) { 2606 return SimplifySetCC(N->getValueType(0), N->getOperand(0), N->getOperand(1), 2607 cast<CondCodeSDNode>(N->getOperand(2))->get()); 2608} 2609 2610// ExtendUsesToFormExtLoad - Trying to extend uses of a load to enable this: 2611// "fold ({s|z}ext (load x)) -> ({s|z}ext (truncate ({s|z}extload x)))" 2612// transformation. Returns true if extension are possible and the above 2613// mentioned transformation is profitable. 2614static bool ExtendUsesToFormExtLoad(SDNode *N, SDOperand N0, 2615 unsigned ExtOpc, 2616 SmallVector<SDNode*, 4> &ExtendNodes, 2617 TargetLowering &TLI) { 2618 bool HasCopyToRegUses = false; 2619 bool isTruncFree = TLI.isTruncateFree(N->getValueType(0), N0.getValueType()); 2620 for (SDNode::use_iterator UI = N0.Val->use_begin(), UE = N0.Val->use_end(); 2621 UI != UE; ++UI) { 2622 SDNode *User = *UI; 2623 if (User == N) 2624 continue; 2625 // FIXME: Only extend SETCC N, N and SETCC N, c for now. 2626 if (User->getOpcode() == ISD::SETCC) { 2627 ISD::CondCode CC = cast<CondCodeSDNode>(User->getOperand(2))->get(); 2628 if (ExtOpc == ISD::ZERO_EXTEND && ISD::isSignedIntSetCC(CC)) 2629 // Sign bits will be lost after a zext. 2630 return false; 2631 bool Add = false; 2632 for (unsigned i = 0; i != 2; ++i) { 2633 SDOperand UseOp = User->getOperand(i); 2634 if (UseOp == N0) 2635 continue; 2636 if (!isa<ConstantSDNode>(UseOp)) 2637 return false; 2638 Add = true; 2639 } 2640 if (Add) 2641 ExtendNodes.push_back(User); 2642 } else { 2643 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) { 2644 SDOperand UseOp = User->getOperand(i); 2645 if (UseOp == N0) { 2646 // If truncate from extended type to original load type is free 2647 // on this target, then it's ok to extend a CopyToReg. 2648 if (isTruncFree && User->getOpcode() == ISD::CopyToReg) 2649 HasCopyToRegUses = true; 2650 else 2651 return false; 2652 } 2653 } 2654 } 2655 } 2656 2657 if (HasCopyToRegUses) { 2658 bool BothLiveOut = false; 2659 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); 2660 UI != UE; ++UI) { 2661 SDNode *User = *UI; 2662 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) { 2663 SDOperand UseOp = User->getOperand(i); 2664 if (UseOp.Val == N && UseOp.ResNo == 0) { 2665 BothLiveOut = true; 2666 break; 2667 } 2668 } 2669 } 2670 if (BothLiveOut) 2671 // Both unextended and extended values are live out. There had better be 2672 // good a reason for the transformation. 2673 return ExtendNodes.size(); 2674 } 2675 return true; 2676} 2677 2678SDOperand DAGCombiner::visitSIGN_EXTEND(SDNode *N) { 2679 SDOperand N0 = N->getOperand(0); 2680 MVT::ValueType VT = N->getValueType(0); 2681 2682 // fold (sext c1) -> c1 2683 if (isa<ConstantSDNode>(N0)) 2684 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0); 2685 2686 // fold (sext (sext x)) -> (sext x) 2687 // fold (sext (aext x)) -> (sext x) 2688 if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 2689 return DAG.getNode(ISD::SIGN_EXTEND, VT, N0.getOperand(0)); 2690 2691 // fold (sext (truncate (load x))) -> (sext (smaller load x)) 2692 // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n))) 2693 if (N0.getOpcode() == ISD::TRUNCATE) { 2694 SDOperand NarrowLoad = ReduceLoadWidth(N0.Val); 2695 if (NarrowLoad.Val) { 2696 if (NarrowLoad.Val != N0.Val) 2697 CombineTo(N0.Val, NarrowLoad); 2698 return DAG.getNode(ISD::SIGN_EXTEND, VT, NarrowLoad); 2699 } 2700 } 2701 2702 // See if the value being truncated is already sign extended. If so, just 2703 // eliminate the trunc/sext pair. 2704 if (N0.getOpcode() == ISD::TRUNCATE) { 2705 SDOperand Op = N0.getOperand(0); 2706 unsigned OpBits = MVT::getSizeInBits(Op.getValueType()); 2707 unsigned MidBits = MVT::getSizeInBits(N0.getValueType()); 2708 unsigned DestBits = MVT::getSizeInBits(VT); 2709 unsigned NumSignBits = DAG.ComputeNumSignBits(Op); 2710 2711 if (OpBits == DestBits) { 2712 // Op is i32, Mid is i8, and Dest is i32. If Op has more than 24 sign 2713 // bits, it is already ready. 2714 if (NumSignBits > DestBits-MidBits) 2715 return Op; 2716 } else if (OpBits < DestBits) { 2717 // Op is i32, Mid is i8, and Dest is i64. If Op has more than 24 sign 2718 // bits, just sext from i32. 2719 if (NumSignBits > OpBits-MidBits) 2720 return DAG.getNode(ISD::SIGN_EXTEND, VT, Op); 2721 } else { 2722 // Op is i64, Mid is i8, and Dest is i32. If Op has more than 56 sign 2723 // bits, just truncate to i32. 2724 if (NumSignBits > OpBits-MidBits) 2725 return DAG.getNode(ISD::TRUNCATE, VT, Op); 2726 } 2727 2728 // fold (sext (truncate x)) -> (sextinreg x). 2729 if (!AfterLegalize || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, 2730 N0.getValueType())) { 2731 if (Op.getValueType() < VT) 2732 Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op); 2733 else if (Op.getValueType() > VT) 2734 Op = DAG.getNode(ISD::TRUNCATE, VT, Op); 2735 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, Op, 2736 DAG.getValueType(N0.getValueType())); 2737 } 2738 } 2739 2740 // fold (sext (load x)) -> (sext (truncate (sextload x))) 2741 if (ISD::isNON_EXTLoad(N0.Val) && 2742 (!AfterLegalize||TLI.isLoadXLegal(ISD::SEXTLOAD, N0.getValueType()))){ 2743 bool DoXform = true; 2744 SmallVector<SDNode*, 4> SetCCs; 2745 if (!N0.hasOneUse()) 2746 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::SIGN_EXTEND, SetCCs, TLI); 2747 if (DoXform) { 2748 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2749 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 2750 LN0->getBasePtr(), LN0->getSrcValue(), 2751 LN0->getSrcValueOffset(), 2752 N0.getValueType(), 2753 LN0->isVolatile(), 2754 LN0->getAlignment()); 2755 CombineTo(N, ExtLoad); 2756 SDOperand Trunc = DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad); 2757 CombineTo(N0.Val, Trunc, ExtLoad.getValue(1)); 2758 // Extend SetCC uses if necessary. 2759 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 2760 SDNode *SetCC = SetCCs[i]; 2761 SmallVector<SDOperand, 4> Ops; 2762 for (unsigned j = 0; j != 2; ++j) { 2763 SDOperand SOp = SetCC->getOperand(j); 2764 if (SOp == Trunc) 2765 Ops.push_back(ExtLoad); 2766 else 2767 Ops.push_back(DAG.getNode(ISD::SIGN_EXTEND, VT, SOp)); 2768 } 2769 Ops.push_back(SetCC->getOperand(2)); 2770 CombineTo(SetCC, DAG.getNode(ISD::SETCC, SetCC->getValueType(0), 2771 &Ops[0], Ops.size())); 2772 } 2773 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2774 } 2775 } 2776 2777 // fold (sext (sextload x)) -> (sext (truncate (sextload x))) 2778 // fold (sext ( extload x)) -> (sext (truncate (sextload x))) 2779 if ((ISD::isSEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) && 2780 ISD::isUNINDEXEDLoad(N0.Val) && N0.hasOneUse()) { 2781 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2782 MVT::ValueType EVT = LN0->getMemoryVT(); 2783 if (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT)) { 2784 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 2785 LN0->getBasePtr(), LN0->getSrcValue(), 2786 LN0->getSrcValueOffset(), EVT, 2787 LN0->isVolatile(), 2788 LN0->getAlignment()); 2789 CombineTo(N, ExtLoad); 2790 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 2791 ExtLoad.getValue(1)); 2792 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2793 } 2794 } 2795 2796 // sext(setcc x,y,cc) -> select_cc x, y, -1, 0, cc 2797 if (N0.getOpcode() == ISD::SETCC) { 2798 SDOperand SCC = 2799 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), 2800 DAG.getConstant(~0ULL, VT), DAG.getConstant(0, VT), 2801 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 2802 if (SCC.Val) return SCC; 2803 } 2804 2805 return SDOperand(); 2806} 2807 2808SDOperand DAGCombiner::visitZERO_EXTEND(SDNode *N) { 2809 SDOperand N0 = N->getOperand(0); 2810 MVT::ValueType VT = N->getValueType(0); 2811 2812 // fold (zext c1) -> c1 2813 if (isa<ConstantSDNode>(N0)) 2814 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0); 2815 // fold (zext (zext x)) -> (zext x) 2816 // fold (zext (aext x)) -> (zext x) 2817 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND) 2818 return DAG.getNode(ISD::ZERO_EXTEND, VT, N0.getOperand(0)); 2819 2820 // fold (zext (truncate (load x))) -> (zext (smaller load x)) 2821 // fold (zext (truncate (srl (load x), c))) -> (zext (small load (x+c/n))) 2822 if (N0.getOpcode() == ISD::TRUNCATE) { 2823 SDOperand NarrowLoad = ReduceLoadWidth(N0.Val); 2824 if (NarrowLoad.Val) { 2825 if (NarrowLoad.Val != N0.Val) 2826 CombineTo(N0.Val, NarrowLoad); 2827 return DAG.getNode(ISD::ZERO_EXTEND, VT, NarrowLoad); 2828 } 2829 } 2830 2831 // fold (zext (truncate x)) -> (and x, mask) 2832 if (N0.getOpcode() == ISD::TRUNCATE && 2833 (!AfterLegalize || TLI.isOperationLegal(ISD::AND, VT))) { 2834 SDOperand Op = N0.getOperand(0); 2835 if (Op.getValueType() < VT) { 2836 Op = DAG.getNode(ISD::ANY_EXTEND, VT, Op); 2837 } else if (Op.getValueType() > VT) { 2838 Op = DAG.getNode(ISD::TRUNCATE, VT, Op); 2839 } 2840 return DAG.getZeroExtendInReg(Op, N0.getValueType()); 2841 } 2842 2843 // fold (zext (and (trunc x), cst)) -> (and x, cst). 2844 if (N0.getOpcode() == ISD::AND && 2845 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 2846 N0.getOperand(1).getOpcode() == ISD::Constant) { 2847 SDOperand X = N0.getOperand(0).getOperand(0); 2848 if (X.getValueType() < VT) { 2849 X = DAG.getNode(ISD::ANY_EXTEND, VT, X); 2850 } else if (X.getValueType() > VT) { 2851 X = DAG.getNode(ISD::TRUNCATE, VT, X); 2852 } 2853 uint64_t Mask = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 2854 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT)); 2855 } 2856 2857 // fold (zext (load x)) -> (zext (truncate (zextload x))) 2858 if (ISD::isNON_EXTLoad(N0.Val) && 2859 (!AfterLegalize||TLI.isLoadXLegal(ISD::ZEXTLOAD, N0.getValueType()))) { 2860 bool DoXform = true; 2861 SmallVector<SDNode*, 4> SetCCs; 2862 if (!N0.hasOneUse()) 2863 DoXform = ExtendUsesToFormExtLoad(N, N0, ISD::ZERO_EXTEND, SetCCs, TLI); 2864 if (DoXform) { 2865 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2866 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 2867 LN0->getBasePtr(), LN0->getSrcValue(), 2868 LN0->getSrcValueOffset(), 2869 N0.getValueType(), 2870 LN0->isVolatile(), 2871 LN0->getAlignment()); 2872 CombineTo(N, ExtLoad); 2873 SDOperand Trunc = DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad); 2874 CombineTo(N0.Val, Trunc, ExtLoad.getValue(1)); 2875 // Extend SetCC uses if necessary. 2876 for (unsigned i = 0, e = SetCCs.size(); i != e; ++i) { 2877 SDNode *SetCC = SetCCs[i]; 2878 SmallVector<SDOperand, 4> Ops; 2879 for (unsigned j = 0; j != 2; ++j) { 2880 SDOperand SOp = SetCC->getOperand(j); 2881 if (SOp == Trunc) 2882 Ops.push_back(ExtLoad); 2883 else 2884 Ops.push_back(DAG.getNode(ISD::ZERO_EXTEND, VT, SOp)); 2885 } 2886 Ops.push_back(SetCC->getOperand(2)); 2887 CombineTo(SetCC, DAG.getNode(ISD::SETCC, SetCC->getValueType(0), 2888 &Ops[0], Ops.size())); 2889 } 2890 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2891 } 2892 } 2893 2894 // fold (zext (zextload x)) -> (zext (truncate (zextload x))) 2895 // fold (zext ( extload x)) -> (zext (truncate (zextload x))) 2896 if ((ISD::isZEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) && 2897 ISD::isUNINDEXEDLoad(N0.Val) && N0.hasOneUse()) { 2898 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2899 MVT::ValueType EVT = LN0->getMemoryVT(); 2900 SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), 2901 LN0->getBasePtr(), LN0->getSrcValue(), 2902 LN0->getSrcValueOffset(), EVT, 2903 LN0->isVolatile(), 2904 LN0->getAlignment()); 2905 CombineTo(N, ExtLoad); 2906 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 2907 ExtLoad.getValue(1)); 2908 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2909 } 2910 2911 // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 2912 if (N0.getOpcode() == ISD::SETCC) { 2913 SDOperand SCC = 2914 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), 2915 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 2916 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 2917 if (SCC.Val) return SCC; 2918 } 2919 2920 return SDOperand(); 2921} 2922 2923SDOperand DAGCombiner::visitANY_EXTEND(SDNode *N) { 2924 SDOperand N0 = N->getOperand(0); 2925 MVT::ValueType VT = N->getValueType(0); 2926 2927 // fold (aext c1) -> c1 2928 if (isa<ConstantSDNode>(N0)) 2929 return DAG.getNode(ISD::ANY_EXTEND, VT, N0); 2930 // fold (aext (aext x)) -> (aext x) 2931 // fold (aext (zext x)) -> (zext x) 2932 // fold (aext (sext x)) -> (sext x) 2933 if (N0.getOpcode() == ISD::ANY_EXTEND || 2934 N0.getOpcode() == ISD::ZERO_EXTEND || 2935 N0.getOpcode() == ISD::SIGN_EXTEND) 2936 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0)); 2937 2938 // fold (aext (truncate (load x))) -> (aext (smaller load x)) 2939 // fold (aext (truncate (srl (load x), c))) -> (aext (small load (x+c/n))) 2940 if (N0.getOpcode() == ISD::TRUNCATE) { 2941 SDOperand NarrowLoad = ReduceLoadWidth(N0.Val); 2942 if (NarrowLoad.Val) { 2943 if (NarrowLoad.Val != N0.Val) 2944 CombineTo(N0.Val, NarrowLoad); 2945 return DAG.getNode(ISD::ANY_EXTEND, VT, NarrowLoad); 2946 } 2947 } 2948 2949 // fold (aext (truncate x)) 2950 if (N0.getOpcode() == ISD::TRUNCATE) { 2951 SDOperand TruncOp = N0.getOperand(0); 2952 if (TruncOp.getValueType() == VT) 2953 return TruncOp; // x iff x size == zext size. 2954 if (TruncOp.getValueType() > VT) 2955 return DAG.getNode(ISD::TRUNCATE, VT, TruncOp); 2956 return DAG.getNode(ISD::ANY_EXTEND, VT, TruncOp); 2957 } 2958 2959 // fold (aext (and (trunc x), cst)) -> (and x, cst). 2960 if (N0.getOpcode() == ISD::AND && 2961 N0.getOperand(0).getOpcode() == ISD::TRUNCATE && 2962 N0.getOperand(1).getOpcode() == ISD::Constant) { 2963 SDOperand X = N0.getOperand(0).getOperand(0); 2964 if (X.getValueType() < VT) { 2965 X = DAG.getNode(ISD::ANY_EXTEND, VT, X); 2966 } else if (X.getValueType() > VT) { 2967 X = DAG.getNode(ISD::TRUNCATE, VT, X); 2968 } 2969 uint64_t Mask = cast<ConstantSDNode>(N0.getOperand(1))->getValue(); 2970 return DAG.getNode(ISD::AND, VT, X, DAG.getConstant(Mask, VT)); 2971 } 2972 2973 // fold (aext (load x)) -> (aext (truncate (extload x))) 2974 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() && 2975 (!AfterLegalize||TLI.isLoadXLegal(ISD::EXTLOAD, N0.getValueType()))) { 2976 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2977 SDOperand ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, LN0->getChain(), 2978 LN0->getBasePtr(), LN0->getSrcValue(), 2979 LN0->getSrcValueOffset(), 2980 N0.getValueType(), 2981 LN0->isVolatile(), 2982 LN0->getAlignment()); 2983 CombineTo(N, ExtLoad); 2984 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 2985 ExtLoad.getValue(1)); 2986 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 2987 } 2988 2989 // fold (aext (zextload x)) -> (aext (truncate (zextload x))) 2990 // fold (aext (sextload x)) -> (aext (truncate (sextload x))) 2991 // fold (aext ( extload x)) -> (aext (truncate (extload x))) 2992 if (N0.getOpcode() == ISD::LOAD && 2993 !ISD::isNON_EXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) && 2994 N0.hasOneUse()) { 2995 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 2996 MVT::ValueType EVT = LN0->getMemoryVT(); 2997 SDOperand ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), VT, 2998 LN0->getChain(), LN0->getBasePtr(), 2999 LN0->getSrcValue(), 3000 LN0->getSrcValueOffset(), EVT, 3001 LN0->isVolatile(), 3002 LN0->getAlignment()); 3003 CombineTo(N, ExtLoad); 3004 CombineTo(N0.Val, DAG.getNode(ISD::TRUNCATE, N0.getValueType(), ExtLoad), 3005 ExtLoad.getValue(1)); 3006 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 3007 } 3008 3009 // aext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc 3010 if (N0.getOpcode() == ISD::SETCC) { 3011 SDOperand SCC = 3012 SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), 3013 DAG.getConstant(1, VT), DAG.getConstant(0, VT), 3014 cast<CondCodeSDNode>(N0.getOperand(2))->get(), true); 3015 if (SCC.Val) 3016 return SCC; 3017 } 3018 3019 return SDOperand(); 3020} 3021 3022/// GetDemandedBits - See if the specified operand can be simplified with the 3023/// knowledge that only the bits specified by Mask are used. If so, return the 3024/// simpler operand, otherwise return a null SDOperand. 3025SDOperand DAGCombiner::GetDemandedBits(SDOperand V, uint64_t Mask) { 3026 switch (V.getOpcode()) { 3027 default: break; 3028 case ISD::OR: 3029 case ISD::XOR: 3030 // If the LHS or RHS don't contribute bits to the or, drop them. 3031 if (DAG.MaskedValueIsZero(V.getOperand(0), Mask)) 3032 return V.getOperand(1); 3033 if (DAG.MaskedValueIsZero(V.getOperand(1), Mask)) 3034 return V.getOperand(0); 3035 break; 3036 case ISD::SRL: 3037 // Only look at single-use SRLs. 3038 if (!V.Val->hasOneUse()) 3039 break; 3040 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(V.getOperand(1))) { 3041 // See if we can recursively simplify the LHS. 3042 unsigned Amt = RHSC->getValue(); 3043 Mask = (Mask << Amt) & MVT::getIntVTBitMask(V.getValueType()); 3044 SDOperand SimplifyLHS = GetDemandedBits(V.getOperand(0), Mask); 3045 if (SimplifyLHS.Val) { 3046 return DAG.getNode(ISD::SRL, V.getValueType(), 3047 SimplifyLHS, V.getOperand(1)); 3048 } 3049 } 3050 } 3051 return SDOperand(); 3052} 3053 3054/// ReduceLoadWidth - If the result of a wider load is shifted to right of N 3055/// bits and then truncated to a narrower type and where N is a multiple 3056/// of number of bits of the narrower type, transform it to a narrower load 3057/// from address + N / num of bits of new type. If the result is to be 3058/// extended, also fold the extension to form a extending load. 3059SDOperand DAGCombiner::ReduceLoadWidth(SDNode *N) { 3060 unsigned Opc = N->getOpcode(); 3061 ISD::LoadExtType ExtType = ISD::NON_EXTLOAD; 3062 SDOperand N0 = N->getOperand(0); 3063 MVT::ValueType VT = N->getValueType(0); 3064 MVT::ValueType EVT = N->getValueType(0); 3065 3066 // Special case: SIGN_EXTEND_INREG is basically truncating to EVT then 3067 // extended to VT. 3068 if (Opc == ISD::SIGN_EXTEND_INREG) { 3069 ExtType = ISD::SEXTLOAD; 3070 EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 3071 if (AfterLegalize && !TLI.isLoadXLegal(ISD::SEXTLOAD, EVT)) 3072 return SDOperand(); 3073 } 3074 3075 unsigned EVTBits = MVT::getSizeInBits(EVT); 3076 unsigned ShAmt = 0; 3077 bool CombineSRL = false; 3078 if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) { 3079 if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) { 3080 ShAmt = N01->getValue(); 3081 // Is the shift amount a multiple of size of VT? 3082 if ((ShAmt & (EVTBits-1)) == 0) { 3083 N0 = N0.getOperand(0); 3084 if (MVT::getSizeInBits(N0.getValueType()) <= EVTBits) 3085 return SDOperand(); 3086 CombineSRL = true; 3087 } 3088 } 3089 } 3090 3091 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() && 3092 // Do not allow folding to i1 here. i1 is implicitly stored in memory in 3093 // zero extended form: by shrinking the load, we lose track of the fact 3094 // that it is already zero extended. 3095 // FIXME: This should be reevaluated. 3096 VT != MVT::i1) { 3097 assert(MVT::getSizeInBits(N0.getValueType()) > EVTBits && 3098 "Cannot truncate to larger type!"); 3099 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3100 MVT::ValueType PtrType = N0.getOperand(1).getValueType(); 3101 // For big endian targets, we need to adjust the offset to the pointer to 3102 // load the correct bytes. 3103 if (TLI.isBigEndian()) { 3104 unsigned LVTStoreBits = MVT::getStoreSizeInBits(N0.getValueType()); 3105 unsigned EVTStoreBits = MVT::getStoreSizeInBits(EVT); 3106 ShAmt = LVTStoreBits - EVTStoreBits - ShAmt; 3107 } 3108 uint64_t PtrOff = ShAmt / 8; 3109 unsigned NewAlign = MinAlign(LN0->getAlignment(), PtrOff); 3110 SDOperand NewPtr = DAG.getNode(ISD::ADD, PtrType, LN0->getBasePtr(), 3111 DAG.getConstant(PtrOff, PtrType)); 3112 AddToWorkList(NewPtr.Val); 3113 SDOperand Load = (ExtType == ISD::NON_EXTLOAD) 3114 ? DAG.getLoad(VT, LN0->getChain(), NewPtr, 3115 LN0->getSrcValue(), LN0->getSrcValueOffset(), 3116 LN0->isVolatile(), NewAlign) 3117 : DAG.getExtLoad(ExtType, VT, LN0->getChain(), NewPtr, 3118 LN0->getSrcValue(), LN0->getSrcValueOffset(), EVT, 3119 LN0->isVolatile(), NewAlign); 3120 AddToWorkList(N); 3121 if (CombineSRL) { 3122 WorkListRemover DeadNodes(*this); 3123 DAG.ReplaceAllUsesOfValueWith(N0.getValue(1), Load.getValue(1), 3124 &DeadNodes); 3125 CombineTo(N->getOperand(0).Val, Load); 3126 } else 3127 CombineTo(N0.Val, Load, Load.getValue(1)); 3128 if (ShAmt) { 3129 if (Opc == ISD::SIGN_EXTEND_INREG) 3130 return DAG.getNode(Opc, VT, Load, N->getOperand(1)); 3131 else 3132 return DAG.getNode(Opc, VT, Load); 3133 } 3134 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 3135 } 3136 3137 return SDOperand(); 3138} 3139 3140 3141SDOperand DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) { 3142 SDOperand N0 = N->getOperand(0); 3143 SDOperand N1 = N->getOperand(1); 3144 MVT::ValueType VT = N->getValueType(0); 3145 MVT::ValueType EVT = cast<VTSDNode>(N1)->getVT(); 3146 unsigned EVTBits = MVT::getSizeInBits(EVT); 3147 3148 // fold (sext_in_reg c1) -> c1 3149 if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF) 3150 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0, N1); 3151 3152 // If the input is already sign extended, just drop the extension. 3153 if (DAG.ComputeNumSignBits(N0) >= MVT::getSizeInBits(VT)-EVTBits+1) 3154 return N0; 3155 3156 // fold (sext_in_reg (sext_in_reg x, VT2), VT1) -> (sext_in_reg x, minVT) pt2 3157 if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && 3158 EVT < cast<VTSDNode>(N0.getOperand(1))->getVT()) { 3159 return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), N1); 3160 } 3161 3162 // fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is known zero. 3163 if (DAG.MaskedValueIsZero(N0, 1ULL << (EVTBits-1))) 3164 return DAG.getZeroExtendInReg(N0, EVT); 3165 3166 // fold operands of sext_in_reg based on knowledge that the top bits are not 3167 // demanded. 3168 if (SimplifyDemandedBits(SDOperand(N, 0))) 3169 return SDOperand(N, 0); 3170 3171 // fold (sext_in_reg (load x)) -> (smaller sextload x) 3172 // fold (sext_in_reg (srl (load x), c)) -> (smaller sextload (x+c/evtbits)) 3173 SDOperand NarrowLoad = ReduceLoadWidth(N); 3174 if (NarrowLoad.Val) 3175 return NarrowLoad; 3176 3177 // fold (sext_in_reg (srl X, 24), i8) -> sra X, 24 3178 // fold (sext_in_reg (srl X, 23), i8) -> sra X, 23 iff possible. 3179 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above. 3180 if (N0.getOpcode() == ISD::SRL) { 3181 if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1))) 3182 if (ShAmt->getValue()+EVTBits <= MVT::getSizeInBits(VT)) { 3183 // We can turn this into an SRA iff the input to the SRL is already sign 3184 // extended enough. 3185 unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0)); 3186 if (MVT::getSizeInBits(VT)-(ShAmt->getValue()+EVTBits) < InSignBits) 3187 return DAG.getNode(ISD::SRA, VT, N0.getOperand(0), N0.getOperand(1)); 3188 } 3189 } 3190 3191 // fold (sext_inreg (extload x)) -> (sextload x) 3192 if (ISD::isEXTLoad(N0.Val) && 3193 ISD::isUNINDEXEDLoad(N0.Val) && 3194 EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 3195 (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))) { 3196 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3197 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 3198 LN0->getBasePtr(), LN0->getSrcValue(), 3199 LN0->getSrcValueOffset(), EVT, 3200 LN0->isVolatile(), 3201 LN0->getAlignment()); 3202 CombineTo(N, ExtLoad); 3203 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 3204 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 3205 } 3206 // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use 3207 if (ISD::isZEXTLoad(N0.Val) && ISD::isUNINDEXEDLoad(N0.Val) && 3208 N0.hasOneUse() && 3209 EVT == cast<LoadSDNode>(N0)->getMemoryVT() && 3210 (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))) { 3211 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3212 SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), 3213 LN0->getBasePtr(), LN0->getSrcValue(), 3214 LN0->getSrcValueOffset(), EVT, 3215 LN0->isVolatile(), 3216 LN0->getAlignment()); 3217 CombineTo(N, ExtLoad); 3218 CombineTo(N0.Val, ExtLoad, ExtLoad.getValue(1)); 3219 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 3220 } 3221 return SDOperand(); 3222} 3223 3224SDOperand DAGCombiner::visitTRUNCATE(SDNode *N) { 3225 SDOperand N0 = N->getOperand(0); 3226 MVT::ValueType VT = N->getValueType(0); 3227 3228 // noop truncate 3229 if (N0.getValueType() == N->getValueType(0)) 3230 return N0; 3231 // fold (truncate c1) -> c1 3232 if (isa<ConstantSDNode>(N0)) 3233 return DAG.getNode(ISD::TRUNCATE, VT, N0); 3234 // fold (truncate (truncate x)) -> (truncate x) 3235 if (N0.getOpcode() == ISD::TRUNCATE) 3236 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0)); 3237 // fold (truncate (ext x)) -> (ext x) or (truncate x) or x 3238 if (N0.getOpcode() == ISD::ZERO_EXTEND || N0.getOpcode() == ISD::SIGN_EXTEND|| 3239 N0.getOpcode() == ISD::ANY_EXTEND) { 3240 if (N0.getOperand(0).getValueType() < VT) 3241 // if the source is smaller than the dest, we still need an extend 3242 return DAG.getNode(N0.getOpcode(), VT, N0.getOperand(0)); 3243 else if (N0.getOperand(0).getValueType() > VT) 3244 // if the source is larger than the dest, than we just need the truncate 3245 return DAG.getNode(ISD::TRUNCATE, VT, N0.getOperand(0)); 3246 else 3247 // if the source and dest are the same type, we can drop both the extend 3248 // and the truncate 3249 return N0.getOperand(0); 3250 } 3251 3252 // See if we can simplify the input to this truncate through knowledge that 3253 // only the low bits are being used. For example "trunc (or (shl x, 8), y)" 3254 // -> trunc y 3255 SDOperand Shorter = GetDemandedBits(N0, MVT::getIntVTBitMask(VT)); 3256 if (Shorter.Val) 3257 return DAG.getNode(ISD::TRUNCATE, VT, Shorter); 3258 3259 // fold (truncate (load x)) -> (smaller load x) 3260 // fold (truncate (srl (load x), c)) -> (smaller load (x+c/evtbits)) 3261 return ReduceLoadWidth(N); 3262} 3263 3264SDOperand DAGCombiner::visitBIT_CONVERT(SDNode *N) { 3265 SDOperand N0 = N->getOperand(0); 3266 MVT::ValueType VT = N->getValueType(0); 3267 3268 // If the input is a BUILD_VECTOR with all constant elements, fold this now. 3269 // Only do this before legalize, since afterward the target may be depending 3270 // on the bitconvert. 3271 // First check to see if this is all constant. 3272 if (!AfterLegalize && 3273 N0.getOpcode() == ISD::BUILD_VECTOR && N0.Val->hasOneUse() && 3274 MVT::isVector(VT)) { 3275 bool isSimple = true; 3276 for (unsigned i = 0, e = N0.getNumOperands(); i != e; ++i) 3277 if (N0.getOperand(i).getOpcode() != ISD::UNDEF && 3278 N0.getOperand(i).getOpcode() != ISD::Constant && 3279 N0.getOperand(i).getOpcode() != ISD::ConstantFP) { 3280 isSimple = false; 3281 break; 3282 } 3283 3284 MVT::ValueType DestEltVT = MVT::getVectorElementType(N->getValueType(0)); 3285 assert(!MVT::isVector(DestEltVT) && 3286 "Element type of vector ValueType must not be vector!"); 3287 if (isSimple) { 3288 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(N0.Val, DestEltVT); 3289 } 3290 } 3291 3292 // If the input is a constant, let getNode() fold it. 3293 if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) { 3294 SDOperand Res = DAG.getNode(ISD::BIT_CONVERT, VT, N0); 3295 if (Res.Val != N) return Res; 3296 } 3297 3298 if (N0.getOpcode() == ISD::BIT_CONVERT) // conv(conv(x,t1),t2) -> conv(x,t2) 3299 return DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0)); 3300 3301 // fold (conv (load x)) -> (load (conv*)x) 3302 // If the resultant load doesn't need a higher alignment than the original! 3303 if (ISD::isNormalLoad(N0.Val) && N0.hasOneUse() && 3304 TLI.isOperationLegal(ISD::LOAD, VT)) { 3305 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3306 unsigned Align = TLI.getTargetMachine().getTargetData()-> 3307 getABITypeAlignment(MVT::getTypeForValueType(VT)); 3308 unsigned OrigAlign = LN0->getAlignment(); 3309 if (Align <= OrigAlign) { 3310 SDOperand Load = DAG.getLoad(VT, LN0->getChain(), LN0->getBasePtr(), 3311 LN0->getSrcValue(), LN0->getSrcValueOffset(), 3312 LN0->isVolatile(), Align); 3313 AddToWorkList(N); 3314 CombineTo(N0.Val, DAG.getNode(ISD::BIT_CONVERT, N0.getValueType(), Load), 3315 Load.getValue(1)); 3316 return Load; 3317 } 3318 } 3319 3320 // Fold bitconvert(fneg(x)) -> xor(bitconvert(x), signbit) 3321 // Fold bitconvert(fabs(x)) -> and(bitconvert(x), ~signbit) 3322 // This often reduces constant pool loads. 3323 if ((N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FABS) && 3324 N0.Val->hasOneUse() && MVT::isInteger(VT) && !MVT::isVector(VT)) { 3325 SDOperand NewConv = DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0)); 3326 AddToWorkList(NewConv.Val); 3327 3328 uint64_t SignBit = MVT::getIntVTSignBit(VT); 3329 if (N0.getOpcode() == ISD::FNEG) 3330 return DAG.getNode(ISD::XOR, VT, NewConv, DAG.getConstant(SignBit, VT)); 3331 assert(N0.getOpcode() == ISD::FABS); 3332 return DAG.getNode(ISD::AND, VT, NewConv, DAG.getConstant(~SignBit, VT)); 3333 } 3334 3335 // Fold bitconvert(fcopysign(cst, x)) -> bitconvert(x)&sign | cst&~sign' 3336 // Note that we don't handle copysign(x,cst) because this can always be folded 3337 // to an fneg or fabs. 3338 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.Val->hasOneUse() && 3339 isa<ConstantFPSDNode>(N0.getOperand(0)) && 3340 MVT::isInteger(VT) && !MVT::isVector(VT)) { 3341 unsigned OrigXWidth = MVT::getSizeInBits(N0.getOperand(1).getValueType()); 3342 SDOperand X = DAG.getNode(ISD::BIT_CONVERT, MVT::getIntegerType(OrigXWidth), 3343 N0.getOperand(1)); 3344 AddToWorkList(X.Val); 3345 3346 // If X has a different width than the result/lhs, sext it or truncate it. 3347 unsigned VTWidth = MVT::getSizeInBits(VT); 3348 if (OrigXWidth < VTWidth) { 3349 X = DAG.getNode(ISD::SIGN_EXTEND, VT, X); 3350 AddToWorkList(X.Val); 3351 } else if (OrigXWidth > VTWidth) { 3352 // To get the sign bit in the right place, we have to shift it right 3353 // before truncating. 3354 X = DAG.getNode(ISD::SRL, X.getValueType(), X, 3355 DAG.getConstant(OrigXWidth-VTWidth, X.getValueType())); 3356 AddToWorkList(X.Val); 3357 X = DAG.getNode(ISD::TRUNCATE, VT, X); 3358 AddToWorkList(X.Val); 3359 } 3360 3361 uint64_t SignBit = MVT::getIntVTSignBit(VT); 3362 X = DAG.getNode(ISD::AND, VT, X, DAG.getConstant(SignBit, VT)); 3363 AddToWorkList(X.Val); 3364 3365 SDOperand Cst = DAG.getNode(ISD::BIT_CONVERT, VT, N0.getOperand(0)); 3366 Cst = DAG.getNode(ISD::AND, VT, Cst, DAG.getConstant(~SignBit, VT)); 3367 AddToWorkList(Cst.Val); 3368 3369 return DAG.getNode(ISD::OR, VT, X, Cst); 3370 } 3371 3372 return SDOperand(); 3373} 3374 3375/// ConstantFoldBIT_CONVERTofBUILD_VECTOR - We know that BV is a build_vector 3376/// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the 3377/// destination element value type. 3378SDOperand DAGCombiner:: 3379ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *BV, MVT::ValueType DstEltVT) { 3380 MVT::ValueType SrcEltVT = BV->getOperand(0).getValueType(); 3381 3382 // If this is already the right type, we're done. 3383 if (SrcEltVT == DstEltVT) return SDOperand(BV, 0); 3384 3385 unsigned SrcBitSize = MVT::getSizeInBits(SrcEltVT); 3386 unsigned DstBitSize = MVT::getSizeInBits(DstEltVT); 3387 3388 // If this is a conversion of N elements of one type to N elements of another 3389 // type, convert each element. This handles FP<->INT cases. 3390 if (SrcBitSize == DstBitSize) { 3391 SmallVector<SDOperand, 8> Ops; 3392 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 3393 Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, DstEltVT, BV->getOperand(i))); 3394 AddToWorkList(Ops.back().Val); 3395 } 3396 MVT::ValueType VT = 3397 MVT::getVectorType(DstEltVT, 3398 MVT::getVectorNumElements(BV->getValueType(0))); 3399 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 3400 } 3401 3402 // Otherwise, we're growing or shrinking the elements. To avoid having to 3403 // handle annoying details of growing/shrinking FP values, we convert them to 3404 // int first. 3405 if (MVT::isFloatingPoint(SrcEltVT)) { 3406 // Convert the input float vector to a int vector where the elements are the 3407 // same sizes. 3408 assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!"); 3409 MVT::ValueType IntVT = SrcEltVT == MVT::f32 ? MVT::i32 : MVT::i64; 3410 BV = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, IntVT).Val; 3411 SrcEltVT = IntVT; 3412 } 3413 3414 // Now we know the input is an integer vector. If the output is a FP type, 3415 // convert to integer first, then to FP of the right size. 3416 if (MVT::isFloatingPoint(DstEltVT)) { 3417 assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!"); 3418 MVT::ValueType TmpVT = DstEltVT == MVT::f32 ? MVT::i32 : MVT::i64; 3419 SDNode *Tmp = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, TmpVT).Val; 3420 3421 // Next, convert to FP elements of the same size. 3422 return ConstantFoldBIT_CONVERTofBUILD_VECTOR(Tmp, DstEltVT); 3423 } 3424 3425 // Okay, we know the src/dst types are both integers of differing types. 3426 // Handling growing first. 3427 assert(MVT::isInteger(SrcEltVT) && MVT::isInteger(DstEltVT)); 3428 if (SrcBitSize < DstBitSize) { 3429 unsigned NumInputsPerOutput = DstBitSize/SrcBitSize; 3430 3431 SmallVector<SDOperand, 8> Ops; 3432 for (unsigned i = 0, e = BV->getNumOperands(); i != e; 3433 i += NumInputsPerOutput) { 3434 bool isLE = TLI.isLittleEndian(); 3435 uint64_t NewBits = 0; 3436 bool EltIsUndef = true; 3437 for (unsigned j = 0; j != NumInputsPerOutput; ++j) { 3438 // Shift the previously computed bits over. 3439 NewBits <<= SrcBitSize; 3440 SDOperand Op = BV->getOperand(i+ (isLE ? (NumInputsPerOutput-j-1) : j)); 3441 if (Op.getOpcode() == ISD::UNDEF) continue; 3442 EltIsUndef = false; 3443 3444 NewBits |= cast<ConstantSDNode>(Op)->getValue(); 3445 } 3446 3447 if (EltIsUndef) 3448 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT)); 3449 else 3450 Ops.push_back(DAG.getConstant(NewBits, DstEltVT)); 3451 } 3452 3453 MVT::ValueType VT = MVT::getVectorType(DstEltVT, 3454 Ops.size()); 3455 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 3456 } 3457 3458 // Finally, this must be the case where we are shrinking elements: each input 3459 // turns into multiple outputs. 3460 unsigned NumOutputsPerInput = SrcBitSize/DstBitSize; 3461 SmallVector<SDOperand, 8> Ops; 3462 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) { 3463 if (BV->getOperand(i).getOpcode() == ISD::UNDEF) { 3464 for (unsigned j = 0; j != NumOutputsPerInput; ++j) 3465 Ops.push_back(DAG.getNode(ISD::UNDEF, DstEltVT)); 3466 continue; 3467 } 3468 uint64_t OpVal = cast<ConstantSDNode>(BV->getOperand(i))->getValue(); 3469 3470 for (unsigned j = 0; j != NumOutputsPerInput; ++j) { 3471 unsigned ThisVal = OpVal & ((1ULL << DstBitSize)-1); 3472 OpVal >>= DstBitSize; 3473 Ops.push_back(DAG.getConstant(ThisVal, DstEltVT)); 3474 } 3475 3476 // For big endian targets, swap the order of the pieces of each element. 3477 if (TLI.isBigEndian()) 3478 std::reverse(Ops.end()-NumOutputsPerInput, Ops.end()); 3479 } 3480 MVT::ValueType VT = MVT::getVectorType(DstEltVT, Ops.size()); 3481 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 3482} 3483 3484 3485 3486SDOperand DAGCombiner::visitFADD(SDNode *N) { 3487 SDOperand N0 = N->getOperand(0); 3488 SDOperand N1 = N->getOperand(1); 3489 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3490 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3491 MVT::ValueType VT = N->getValueType(0); 3492 3493 // fold vector ops 3494 if (MVT::isVector(VT)) { 3495 SDOperand FoldedVOp = SimplifyVBinOp(N); 3496 if (FoldedVOp.Val) return FoldedVOp; 3497 } 3498 3499 // fold (fadd c1, c2) -> c1+c2 3500 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3501 return DAG.getNode(ISD::FADD, VT, N0, N1); 3502 // canonicalize constant to RHS 3503 if (N0CFP && !N1CFP) 3504 return DAG.getNode(ISD::FADD, VT, N1, N0); 3505 // fold (A + (-B)) -> A-B 3506 if (isNegatibleForFree(N1) == 2) 3507 return DAG.getNode(ISD::FSUB, VT, N0, GetNegatedExpression(N1, DAG)); 3508 // fold ((-A) + B) -> B-A 3509 if (isNegatibleForFree(N0) == 2) 3510 return DAG.getNode(ISD::FSUB, VT, N1, GetNegatedExpression(N0, DAG)); 3511 3512 // If allowed, fold (fadd (fadd x, c1), c2) -> (fadd x, (fadd c1, c2)) 3513 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FADD && 3514 N0.Val->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 3515 return DAG.getNode(ISD::FADD, VT, N0.getOperand(0), 3516 DAG.getNode(ISD::FADD, VT, N0.getOperand(1), N1)); 3517 3518 return SDOperand(); 3519} 3520 3521SDOperand DAGCombiner::visitFSUB(SDNode *N) { 3522 SDOperand N0 = N->getOperand(0); 3523 SDOperand N1 = N->getOperand(1); 3524 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3525 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3526 MVT::ValueType VT = N->getValueType(0); 3527 3528 // fold vector ops 3529 if (MVT::isVector(VT)) { 3530 SDOperand FoldedVOp = SimplifyVBinOp(N); 3531 if (FoldedVOp.Val) return FoldedVOp; 3532 } 3533 3534 // fold (fsub c1, c2) -> c1-c2 3535 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3536 return DAG.getNode(ISD::FSUB, VT, N0, N1); 3537 // fold (0-B) -> -B 3538 if (UnsafeFPMath && N0CFP && N0CFP->getValueAPF().isZero()) { 3539 if (isNegatibleForFree(N1)) 3540 return GetNegatedExpression(N1, DAG); 3541 return DAG.getNode(ISD::FNEG, VT, N1); 3542 } 3543 // fold (A-(-B)) -> A+B 3544 if (isNegatibleForFree(N1)) 3545 return DAG.getNode(ISD::FADD, VT, N0, GetNegatedExpression(N1, DAG)); 3546 3547 return SDOperand(); 3548} 3549 3550SDOperand DAGCombiner::visitFMUL(SDNode *N) { 3551 SDOperand N0 = N->getOperand(0); 3552 SDOperand N1 = N->getOperand(1); 3553 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3554 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3555 MVT::ValueType VT = N->getValueType(0); 3556 3557 // fold vector ops 3558 if (MVT::isVector(VT)) { 3559 SDOperand FoldedVOp = SimplifyVBinOp(N); 3560 if (FoldedVOp.Val) return FoldedVOp; 3561 } 3562 3563 // fold (fmul c1, c2) -> c1*c2 3564 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3565 return DAG.getNode(ISD::FMUL, VT, N0, N1); 3566 // canonicalize constant to RHS 3567 if (N0CFP && !N1CFP) 3568 return DAG.getNode(ISD::FMUL, VT, N1, N0); 3569 // fold (fmul X, 2.0) -> (fadd X, X) 3570 if (N1CFP && N1CFP->isExactlyValue(+2.0)) 3571 return DAG.getNode(ISD::FADD, VT, N0, N0); 3572 // fold (fmul X, -1.0) -> (fneg X) 3573 if (N1CFP && N1CFP->isExactlyValue(-1.0)) 3574 return DAG.getNode(ISD::FNEG, VT, N0); 3575 3576 // -X * -Y -> X*Y 3577 if (char LHSNeg = isNegatibleForFree(N0)) { 3578 if (char RHSNeg = isNegatibleForFree(N1)) { 3579 // Both can be negated for free, check to see if at least one is cheaper 3580 // negated. 3581 if (LHSNeg == 2 || RHSNeg == 2) 3582 return DAG.getNode(ISD::FMUL, VT, GetNegatedExpression(N0, DAG), 3583 GetNegatedExpression(N1, DAG)); 3584 } 3585 } 3586 3587 // If allowed, fold (fmul (fmul x, c1), c2) -> (fmul x, (fmul c1, c2)) 3588 if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FMUL && 3589 N0.Val->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1))) 3590 return DAG.getNode(ISD::FMUL, VT, N0.getOperand(0), 3591 DAG.getNode(ISD::FMUL, VT, N0.getOperand(1), N1)); 3592 3593 return SDOperand(); 3594} 3595 3596SDOperand DAGCombiner::visitFDIV(SDNode *N) { 3597 SDOperand N0 = N->getOperand(0); 3598 SDOperand N1 = N->getOperand(1); 3599 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3600 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3601 MVT::ValueType VT = N->getValueType(0); 3602 3603 // fold vector ops 3604 if (MVT::isVector(VT)) { 3605 SDOperand FoldedVOp = SimplifyVBinOp(N); 3606 if (FoldedVOp.Val) return FoldedVOp; 3607 } 3608 3609 // fold (fdiv c1, c2) -> c1/c2 3610 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3611 return DAG.getNode(ISD::FDIV, VT, N0, N1); 3612 3613 3614 // -X / -Y -> X*Y 3615 if (char LHSNeg = isNegatibleForFree(N0)) { 3616 if (char RHSNeg = isNegatibleForFree(N1)) { 3617 // Both can be negated for free, check to see if at least one is cheaper 3618 // negated. 3619 if (LHSNeg == 2 || RHSNeg == 2) 3620 return DAG.getNode(ISD::FDIV, VT, GetNegatedExpression(N0, DAG), 3621 GetNegatedExpression(N1, DAG)); 3622 } 3623 } 3624 3625 return SDOperand(); 3626} 3627 3628SDOperand DAGCombiner::visitFREM(SDNode *N) { 3629 SDOperand N0 = N->getOperand(0); 3630 SDOperand N1 = N->getOperand(1); 3631 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3632 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3633 MVT::ValueType VT = N->getValueType(0); 3634 3635 // fold (frem c1, c2) -> fmod(c1,c2) 3636 if (N0CFP && N1CFP && VT != MVT::ppcf128) 3637 return DAG.getNode(ISD::FREM, VT, N0, N1); 3638 3639 return SDOperand(); 3640} 3641 3642SDOperand DAGCombiner::visitFCOPYSIGN(SDNode *N) { 3643 SDOperand N0 = N->getOperand(0); 3644 SDOperand N1 = N->getOperand(1); 3645 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3646 ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1); 3647 MVT::ValueType VT = N->getValueType(0); 3648 3649 if (N0CFP && N1CFP && VT != MVT::ppcf128) // Constant fold 3650 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1); 3651 3652 if (N1CFP) { 3653 const APFloat& V = N1CFP->getValueAPF(); 3654 // copysign(x, c1) -> fabs(x) iff ispos(c1) 3655 // copysign(x, c1) -> fneg(fabs(x)) iff isneg(c1) 3656 if (!V.isNegative()) 3657 return DAG.getNode(ISD::FABS, VT, N0); 3658 else 3659 return DAG.getNode(ISD::FNEG, VT, DAG.getNode(ISD::FABS, VT, N0)); 3660 } 3661 3662 // copysign(fabs(x), y) -> copysign(x, y) 3663 // copysign(fneg(x), y) -> copysign(x, y) 3664 // copysign(copysign(x,z), y) -> copysign(x, y) 3665 if (N0.getOpcode() == ISD::FABS || N0.getOpcode() == ISD::FNEG || 3666 N0.getOpcode() == ISD::FCOPYSIGN) 3667 return DAG.getNode(ISD::FCOPYSIGN, VT, N0.getOperand(0), N1); 3668 3669 // copysign(x, abs(y)) -> abs(x) 3670 if (N1.getOpcode() == ISD::FABS) 3671 return DAG.getNode(ISD::FABS, VT, N0); 3672 3673 // copysign(x, copysign(y,z)) -> copysign(x, z) 3674 if (N1.getOpcode() == ISD::FCOPYSIGN) 3675 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(1)); 3676 3677 // copysign(x, fp_extend(y)) -> copysign(x, y) 3678 // copysign(x, fp_round(y)) -> copysign(x, y) 3679 if (N1.getOpcode() == ISD::FP_EXTEND || N1.getOpcode() == ISD::FP_ROUND) 3680 return DAG.getNode(ISD::FCOPYSIGN, VT, N0, N1.getOperand(0)); 3681 3682 return SDOperand(); 3683} 3684 3685 3686 3687SDOperand DAGCombiner::visitSINT_TO_FP(SDNode *N) { 3688 SDOperand N0 = N->getOperand(0); 3689 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3690 MVT::ValueType VT = N->getValueType(0); 3691 3692 // fold (sint_to_fp c1) -> c1fp 3693 if (N0C && N0.getValueType() != MVT::ppcf128) 3694 return DAG.getNode(ISD::SINT_TO_FP, VT, N0); 3695 return SDOperand(); 3696} 3697 3698SDOperand DAGCombiner::visitUINT_TO_FP(SDNode *N) { 3699 SDOperand N0 = N->getOperand(0); 3700 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0); 3701 MVT::ValueType VT = N->getValueType(0); 3702 3703 // fold (uint_to_fp c1) -> c1fp 3704 if (N0C && N0.getValueType() != MVT::ppcf128) 3705 return DAG.getNode(ISD::UINT_TO_FP, VT, N0); 3706 return SDOperand(); 3707} 3708 3709SDOperand DAGCombiner::visitFP_TO_SINT(SDNode *N) { 3710 SDOperand N0 = N->getOperand(0); 3711 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3712 MVT::ValueType VT = N->getValueType(0); 3713 3714 // fold (fp_to_sint c1fp) -> c1 3715 if (N0CFP) 3716 return DAG.getNode(ISD::FP_TO_SINT, VT, N0); 3717 return SDOperand(); 3718} 3719 3720SDOperand DAGCombiner::visitFP_TO_UINT(SDNode *N) { 3721 SDOperand N0 = N->getOperand(0); 3722 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3723 MVT::ValueType VT = N->getValueType(0); 3724 3725 // fold (fp_to_uint c1fp) -> c1 3726 if (N0CFP && VT != MVT::ppcf128) 3727 return DAG.getNode(ISD::FP_TO_UINT, VT, N0); 3728 return SDOperand(); 3729} 3730 3731SDOperand DAGCombiner::visitFP_ROUND(SDNode *N) { 3732 SDOperand N0 = N->getOperand(0); 3733 SDOperand N1 = N->getOperand(1); 3734 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3735 MVT::ValueType VT = N->getValueType(0); 3736 3737 // fold (fp_round c1fp) -> c1fp 3738 if (N0CFP && N0.getValueType() != MVT::ppcf128) 3739 return DAG.getNode(ISD::FP_ROUND, VT, N0, N1); 3740 3741 // fold (fp_round (fp_extend x)) -> x 3742 if (N0.getOpcode() == ISD::FP_EXTEND && VT == N0.getOperand(0).getValueType()) 3743 return N0.getOperand(0); 3744 3745 // fold (fp_round (fp_round x)) -> (fp_round x) 3746 if (N0.getOpcode() == ISD::FP_ROUND) { 3747 // This is a value preserving truncation if both round's are. 3748 bool IsTrunc = N->getConstantOperandVal(1) == 1 && 3749 N0.Val->getConstantOperandVal(1) == 1; 3750 return DAG.getNode(ISD::FP_ROUND, VT, N0.getOperand(0), 3751 DAG.getIntPtrConstant(IsTrunc)); 3752 } 3753 3754 // fold (fp_round (copysign X, Y)) -> (copysign (fp_round X), Y) 3755 if (N0.getOpcode() == ISD::FCOPYSIGN && N0.Val->hasOneUse()) { 3756 SDOperand Tmp = DAG.getNode(ISD::FP_ROUND, VT, N0.getOperand(0), N1); 3757 AddToWorkList(Tmp.Val); 3758 return DAG.getNode(ISD::FCOPYSIGN, VT, Tmp, N0.getOperand(1)); 3759 } 3760 3761 return SDOperand(); 3762} 3763 3764SDOperand DAGCombiner::visitFP_ROUND_INREG(SDNode *N) { 3765 SDOperand N0 = N->getOperand(0); 3766 MVT::ValueType VT = N->getValueType(0); 3767 MVT::ValueType EVT = cast<VTSDNode>(N->getOperand(1))->getVT(); 3768 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3769 3770 // fold (fp_round_inreg c1fp) -> c1fp 3771 if (N0CFP) { 3772 SDOperand Round = DAG.getConstantFP(N0CFP->getValueAPF(), EVT); 3773 return DAG.getNode(ISD::FP_EXTEND, VT, Round); 3774 } 3775 return SDOperand(); 3776} 3777 3778SDOperand DAGCombiner::visitFP_EXTEND(SDNode *N) { 3779 SDOperand N0 = N->getOperand(0); 3780 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3781 MVT::ValueType VT = N->getValueType(0); 3782 3783 // If this is fp_round(fpextend), don't fold it, allow ourselves to be folded. 3784 if (N->hasOneUse() && (*N->use_begin())->getOpcode() == ISD::FP_ROUND) 3785 return SDOperand(); 3786 3787 // fold (fp_extend c1fp) -> c1fp 3788 if (N0CFP && VT != MVT::ppcf128) 3789 return DAG.getNode(ISD::FP_EXTEND, VT, N0); 3790 3791 // Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't affect the 3792 // value of X. 3793 if (N0.getOpcode() == ISD::FP_ROUND && N0.Val->getConstantOperandVal(1) == 1){ 3794 SDOperand In = N0.getOperand(0); 3795 if (In.getValueType() == VT) return In; 3796 if (VT < In.getValueType()) 3797 return DAG.getNode(ISD::FP_ROUND, VT, In, N0.getOperand(1)); 3798 return DAG.getNode(ISD::FP_EXTEND, VT, In); 3799 } 3800 3801 // fold (fpext (load x)) -> (fpext (fptrunc (extload x))) 3802 if (ISD::isNON_EXTLoad(N0.Val) && N0.hasOneUse() && 3803 (!AfterLegalize||TLI.isLoadXLegal(ISD::EXTLOAD, N0.getValueType()))) { 3804 LoadSDNode *LN0 = cast<LoadSDNode>(N0); 3805 SDOperand ExtLoad = DAG.getExtLoad(ISD::EXTLOAD, VT, LN0->getChain(), 3806 LN0->getBasePtr(), LN0->getSrcValue(), 3807 LN0->getSrcValueOffset(), 3808 N0.getValueType(), 3809 LN0->isVolatile(), 3810 LN0->getAlignment()); 3811 CombineTo(N, ExtLoad); 3812 CombineTo(N0.Val, DAG.getNode(ISD::FP_ROUND, N0.getValueType(), ExtLoad, 3813 DAG.getIntPtrConstant(1)), 3814 ExtLoad.getValue(1)); 3815 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 3816 } 3817 3818 3819 return SDOperand(); 3820} 3821 3822SDOperand DAGCombiner::visitFNEG(SDNode *N) { 3823 SDOperand N0 = N->getOperand(0); 3824 3825 if (isNegatibleForFree(N0)) 3826 return GetNegatedExpression(N0, DAG); 3827 3828 // Transform fneg(bitconvert(x)) -> bitconvert(x^sign) to avoid loading 3829 // constant pool values. 3830 if (N0.getOpcode() == ISD::BIT_CONVERT && N0.Val->hasOneUse() && 3831 MVT::isInteger(N0.getOperand(0).getValueType()) && 3832 !MVT::isVector(N0.getOperand(0).getValueType())) { 3833 SDOperand Int = N0.getOperand(0); 3834 MVT::ValueType IntVT = Int.getValueType(); 3835 if (MVT::isInteger(IntVT) && !MVT::isVector(IntVT)) { 3836 Int = DAG.getNode(ISD::XOR, IntVT, Int, 3837 DAG.getConstant(MVT::getIntVTSignBit(IntVT), IntVT)); 3838 AddToWorkList(Int.Val); 3839 return DAG.getNode(ISD::BIT_CONVERT, N->getValueType(0), Int); 3840 } 3841 } 3842 3843 return SDOperand(); 3844} 3845 3846SDOperand DAGCombiner::visitFABS(SDNode *N) { 3847 SDOperand N0 = N->getOperand(0); 3848 ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0); 3849 MVT::ValueType VT = N->getValueType(0); 3850 3851 // fold (fabs c1) -> fabs(c1) 3852 if (N0CFP && VT != MVT::ppcf128) 3853 return DAG.getNode(ISD::FABS, VT, N0); 3854 // fold (fabs (fabs x)) -> (fabs x) 3855 if (N0.getOpcode() == ISD::FABS) 3856 return N->getOperand(0); 3857 // fold (fabs (fneg x)) -> (fabs x) 3858 // fold (fabs (fcopysign x, y)) -> (fabs x) 3859 if (N0.getOpcode() == ISD::FNEG || N0.getOpcode() == ISD::FCOPYSIGN) 3860 return DAG.getNode(ISD::FABS, VT, N0.getOperand(0)); 3861 3862 // Transform fabs(bitconvert(x)) -> bitconvert(x&~sign) to avoid loading 3863 // constant pool values. 3864 if (N0.getOpcode() == ISD::BIT_CONVERT && N0.Val->hasOneUse() && 3865 MVT::isInteger(N0.getOperand(0).getValueType()) && 3866 !MVT::isVector(N0.getOperand(0).getValueType())) { 3867 SDOperand Int = N0.getOperand(0); 3868 MVT::ValueType IntVT = Int.getValueType(); 3869 if (MVT::isInteger(IntVT) && !MVT::isVector(IntVT)) { 3870 Int = DAG.getNode(ISD::AND, IntVT, Int, 3871 DAG.getConstant(~MVT::getIntVTSignBit(IntVT), IntVT)); 3872 AddToWorkList(Int.Val); 3873 return DAG.getNode(ISD::BIT_CONVERT, N->getValueType(0), Int); 3874 } 3875 } 3876 3877 return SDOperand(); 3878} 3879 3880SDOperand DAGCombiner::visitBRCOND(SDNode *N) { 3881 SDOperand Chain = N->getOperand(0); 3882 SDOperand N1 = N->getOperand(1); 3883 SDOperand N2 = N->getOperand(2); 3884 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 3885 3886 // never taken branch, fold to chain 3887 if (N1C && N1C->isNullValue()) 3888 return Chain; 3889 // unconditional branch 3890 if (N1C && N1C->getValue() == 1) 3891 return DAG.getNode(ISD::BR, MVT::Other, Chain, N2); 3892 // fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal 3893 // on the target. 3894 if (N1.getOpcode() == ISD::SETCC && 3895 TLI.isOperationLegal(ISD::BR_CC, MVT::Other)) { 3896 return DAG.getNode(ISD::BR_CC, MVT::Other, Chain, N1.getOperand(2), 3897 N1.getOperand(0), N1.getOperand(1), N2); 3898 } 3899 return SDOperand(); 3900} 3901 3902// Operand List for BR_CC: Chain, CondCC, CondLHS, CondRHS, DestBB. 3903// 3904SDOperand DAGCombiner::visitBR_CC(SDNode *N) { 3905 CondCodeSDNode *CC = cast<CondCodeSDNode>(N->getOperand(1)); 3906 SDOperand CondLHS = N->getOperand(2), CondRHS = N->getOperand(3); 3907 3908 // Use SimplifySetCC to simplify SETCC's. 3909 SDOperand Simp = SimplifySetCC(MVT::i1, CondLHS, CondRHS, CC->get(), false); 3910 if (Simp.Val) AddToWorkList(Simp.Val); 3911 3912 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(Simp.Val); 3913 3914 // fold br_cc true, dest -> br dest (unconditional branch) 3915 if (SCCC && SCCC->getValue()) 3916 return DAG.getNode(ISD::BR, MVT::Other, N->getOperand(0), 3917 N->getOperand(4)); 3918 // fold br_cc false, dest -> unconditional fall through 3919 if (SCCC && SCCC->isNullValue()) 3920 return N->getOperand(0); 3921 3922 // fold to a simpler setcc 3923 if (Simp.Val && Simp.getOpcode() == ISD::SETCC) 3924 return DAG.getNode(ISD::BR_CC, MVT::Other, N->getOperand(0), 3925 Simp.getOperand(2), Simp.getOperand(0), 3926 Simp.getOperand(1), N->getOperand(4)); 3927 return SDOperand(); 3928} 3929 3930 3931/// CombineToPreIndexedLoadStore - Try turning a load / store and a 3932/// pre-indexed load / store when the base pointer is a add or subtract 3933/// and it has other uses besides the load / store. After the 3934/// transformation, the new indexed load / store has effectively folded 3935/// the add / subtract in and all of its other uses are redirected to the 3936/// new load / store. 3937bool DAGCombiner::CombineToPreIndexedLoadStore(SDNode *N) { 3938 if (!AfterLegalize) 3939 return false; 3940 3941 bool isLoad = true; 3942 SDOperand Ptr; 3943 MVT::ValueType VT; 3944 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 3945 if (LD->isIndexed()) 3946 return false; 3947 VT = LD->getMemoryVT(); 3948 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) && 3949 !TLI.isIndexedLoadLegal(ISD::PRE_DEC, VT)) 3950 return false; 3951 Ptr = LD->getBasePtr(); 3952 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 3953 if (ST->isIndexed()) 3954 return false; 3955 VT = ST->getMemoryVT(); 3956 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) && 3957 !TLI.isIndexedStoreLegal(ISD::PRE_DEC, VT)) 3958 return false; 3959 Ptr = ST->getBasePtr(); 3960 isLoad = false; 3961 } else 3962 return false; 3963 3964 // If the pointer is not an add/sub, or if it doesn't have multiple uses, bail 3965 // out. There is no reason to make this a preinc/predec. 3966 if ((Ptr.getOpcode() != ISD::ADD && Ptr.getOpcode() != ISD::SUB) || 3967 Ptr.Val->hasOneUse()) 3968 return false; 3969 3970 // Ask the target to do addressing mode selection. 3971 SDOperand BasePtr; 3972 SDOperand Offset; 3973 ISD::MemIndexedMode AM = ISD::UNINDEXED; 3974 if (!TLI.getPreIndexedAddressParts(N, BasePtr, Offset, AM, DAG)) 3975 return false; 3976 // Don't create a indexed load / store with zero offset. 3977 if (isa<ConstantSDNode>(Offset) && 3978 cast<ConstantSDNode>(Offset)->getValue() == 0) 3979 return false; 3980 3981 // Try turning it into a pre-indexed load / store except when: 3982 // 1) The new base ptr is a frame index. 3983 // 2) If N is a store and the new base ptr is either the same as or is a 3984 // predecessor of the value being stored. 3985 // 3) Another use of old base ptr is a predecessor of N. If ptr is folded 3986 // that would create a cycle. 3987 // 4) All uses are load / store ops that use it as old base ptr. 3988 3989 // Check #1. Preinc'ing a frame index would require copying the stack pointer 3990 // (plus the implicit offset) to a register to preinc anyway. 3991 if (isa<FrameIndexSDNode>(BasePtr)) 3992 return false; 3993 3994 // Check #2. 3995 if (!isLoad) { 3996 SDOperand Val = cast<StoreSDNode>(N)->getValue(); 3997 if (Val == BasePtr || BasePtr.Val->isPredecessor(Val.Val)) 3998 return false; 3999 } 4000 4001 // Now check for #3 and #4. 4002 bool RealUse = false; 4003 for (SDNode::use_iterator I = Ptr.Val->use_begin(), 4004 E = Ptr.Val->use_end(); I != E; ++I) { 4005 SDNode *Use = *I; 4006 if (Use == N) 4007 continue; 4008 if (Use->isPredecessor(N)) 4009 return false; 4010 4011 if (!((Use->getOpcode() == ISD::LOAD && 4012 cast<LoadSDNode>(Use)->getBasePtr() == Ptr) || 4013 (Use->getOpcode() == ISD::STORE) && 4014 cast<StoreSDNode>(Use)->getBasePtr() == Ptr)) 4015 RealUse = true; 4016 } 4017 if (!RealUse) 4018 return false; 4019 4020 SDOperand Result; 4021 if (isLoad) 4022 Result = DAG.getIndexedLoad(SDOperand(N,0), BasePtr, Offset, AM); 4023 else 4024 Result = DAG.getIndexedStore(SDOperand(N,0), BasePtr, Offset, AM); 4025 ++PreIndexedNodes; 4026 ++NodesCombined; 4027 DOUT << "\nReplacing.4 "; DEBUG(N->dump(&DAG)); 4028 DOUT << "\nWith: "; DEBUG(Result.Val->dump(&DAG)); 4029 DOUT << '\n'; 4030 WorkListRemover DeadNodes(*this); 4031 if (isLoad) { 4032 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(0), 4033 &DeadNodes); 4034 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1), Result.getValue(2), 4035 &DeadNodes); 4036 } else { 4037 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(1), 4038 &DeadNodes); 4039 } 4040 4041 // Finally, since the node is now dead, remove it from the graph. 4042 DAG.DeleteNode(N); 4043 4044 // Replace the uses of Ptr with uses of the updated base value. 4045 DAG.ReplaceAllUsesOfValueWith(Ptr, Result.getValue(isLoad ? 1 : 0), 4046 &DeadNodes); 4047 removeFromWorkList(Ptr.Val); 4048 DAG.DeleteNode(Ptr.Val); 4049 4050 return true; 4051} 4052 4053/// CombineToPostIndexedLoadStore - Try combine a load / store with a 4054/// add / sub of the base pointer node into a post-indexed load / store. 4055/// The transformation folded the add / subtract into the new indexed 4056/// load / store effectively and all of its uses are redirected to the 4057/// new load / store. 4058bool DAGCombiner::CombineToPostIndexedLoadStore(SDNode *N) { 4059 if (!AfterLegalize) 4060 return false; 4061 4062 bool isLoad = true; 4063 SDOperand Ptr; 4064 MVT::ValueType VT; 4065 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 4066 if (LD->isIndexed()) 4067 return false; 4068 VT = LD->getMemoryVT(); 4069 if (!TLI.isIndexedLoadLegal(ISD::POST_INC, VT) && 4070 !TLI.isIndexedLoadLegal(ISD::POST_DEC, VT)) 4071 return false; 4072 Ptr = LD->getBasePtr(); 4073 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 4074 if (ST->isIndexed()) 4075 return false; 4076 VT = ST->getMemoryVT(); 4077 if (!TLI.isIndexedStoreLegal(ISD::POST_INC, VT) && 4078 !TLI.isIndexedStoreLegal(ISD::POST_DEC, VT)) 4079 return false; 4080 Ptr = ST->getBasePtr(); 4081 isLoad = false; 4082 } else 4083 return false; 4084 4085 if (Ptr.Val->hasOneUse()) 4086 return false; 4087 4088 for (SDNode::use_iterator I = Ptr.Val->use_begin(), 4089 E = Ptr.Val->use_end(); I != E; ++I) { 4090 SDNode *Op = *I; 4091 if (Op == N || 4092 (Op->getOpcode() != ISD::ADD && Op->getOpcode() != ISD::SUB)) 4093 continue; 4094 4095 SDOperand BasePtr; 4096 SDOperand Offset; 4097 ISD::MemIndexedMode AM = ISD::UNINDEXED; 4098 if (TLI.getPostIndexedAddressParts(N, Op, BasePtr, Offset, AM, DAG)) { 4099 if (Ptr == Offset) 4100 std::swap(BasePtr, Offset); 4101 if (Ptr != BasePtr) 4102 continue; 4103 // Don't create a indexed load / store with zero offset. 4104 if (isa<ConstantSDNode>(Offset) && 4105 cast<ConstantSDNode>(Offset)->getValue() == 0) 4106 continue; 4107 4108 // Try turning it into a post-indexed load / store except when 4109 // 1) All uses are load / store ops that use it as base ptr. 4110 // 2) Op must be independent of N, i.e. Op is neither a predecessor 4111 // nor a successor of N. Otherwise, if Op is folded that would 4112 // create a cycle. 4113 4114 // Check for #1. 4115 bool TryNext = false; 4116 for (SDNode::use_iterator II = BasePtr.Val->use_begin(), 4117 EE = BasePtr.Val->use_end(); II != EE; ++II) { 4118 SDNode *Use = *II; 4119 if (Use == Ptr.Val) 4120 continue; 4121 4122 // If all the uses are load / store addresses, then don't do the 4123 // transformation. 4124 if (Use->getOpcode() == ISD::ADD || Use->getOpcode() == ISD::SUB){ 4125 bool RealUse = false; 4126 for (SDNode::use_iterator III = Use->use_begin(), 4127 EEE = Use->use_end(); III != EEE; ++III) { 4128 SDNode *UseUse = *III; 4129 if (!((UseUse->getOpcode() == ISD::LOAD && 4130 cast<LoadSDNode>(UseUse)->getBasePtr().Val == Use) || 4131 (UseUse->getOpcode() == ISD::STORE) && 4132 cast<StoreSDNode>(UseUse)->getBasePtr().Val == Use)) 4133 RealUse = true; 4134 } 4135 4136 if (!RealUse) { 4137 TryNext = true; 4138 break; 4139 } 4140 } 4141 } 4142 if (TryNext) 4143 continue; 4144 4145 // Check for #2 4146 if (!Op->isPredecessor(N) && !N->isPredecessor(Op)) { 4147 SDOperand Result = isLoad 4148 ? DAG.getIndexedLoad(SDOperand(N,0), BasePtr, Offset, AM) 4149 : DAG.getIndexedStore(SDOperand(N,0), BasePtr, Offset, AM); 4150 ++PostIndexedNodes; 4151 ++NodesCombined; 4152 DOUT << "\nReplacing.5 "; DEBUG(N->dump(&DAG)); 4153 DOUT << "\nWith: "; DEBUG(Result.Val->dump(&DAG)); 4154 DOUT << '\n'; 4155 WorkListRemover DeadNodes(*this); 4156 if (isLoad) { 4157 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(0), 4158 &DeadNodes); 4159 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1), Result.getValue(2), 4160 &DeadNodes); 4161 } else { 4162 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Result.getValue(1), 4163 &DeadNodes); 4164 } 4165 4166 // Finally, since the node is now dead, remove it from the graph. 4167 DAG.DeleteNode(N); 4168 4169 // Replace the uses of Use with uses of the updated base value. 4170 DAG.ReplaceAllUsesOfValueWith(SDOperand(Op, 0), 4171 Result.getValue(isLoad ? 1 : 0), 4172 &DeadNodes); 4173 removeFromWorkList(Op); 4174 DAG.DeleteNode(Op); 4175 return true; 4176 } 4177 } 4178 } 4179 return false; 4180} 4181 4182/// InferAlignment - If we can infer some alignment information from this 4183/// pointer, return it. 4184static unsigned InferAlignment(SDOperand Ptr, SelectionDAG &DAG) { 4185 // If this is a direct reference to a stack slot, use information about the 4186 // stack slot's alignment. 4187 int FrameIdx = 1 << 31; 4188 int64_t FrameOffset = 0; 4189 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Ptr)) { 4190 FrameIdx = FI->getIndex(); 4191 } else if (Ptr.getOpcode() == ISD::ADD && 4192 isa<ConstantSDNode>(Ptr.getOperand(1)) && 4193 isa<FrameIndexSDNode>(Ptr.getOperand(0))) { 4194 FrameIdx = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex(); 4195 FrameOffset = Ptr.getConstantOperandVal(1); 4196 } 4197 4198 if (FrameIdx != (1 << 31)) { 4199 // FIXME: Handle FI+CST. 4200 const MachineFrameInfo &MFI = *DAG.getMachineFunction().getFrameInfo(); 4201 if (MFI.isFixedObjectIndex(FrameIdx)) { 4202 int64_t ObjectOffset = MFI.getObjectOffset(FrameIdx); 4203 4204 // The alignment of the frame index can be determined from its offset from 4205 // the incoming frame position. If the frame object is at offset 32 and 4206 // the stack is guaranteed to be 16-byte aligned, then we know that the 4207 // object is 16-byte aligned. 4208 unsigned StackAlign = DAG.getTarget().getFrameInfo()->getStackAlignment(); 4209 unsigned Align = MinAlign(ObjectOffset, StackAlign); 4210 4211 // Finally, the frame object itself may have a known alignment. Factor 4212 // the alignment + offset into a new alignment. For example, if we know 4213 // the FI is 8 byte aligned, but the pointer is 4 off, we really have a 4214 // 4-byte alignment of the resultant pointer. Likewise align 4 + 4-byte 4215 // offset = 4-byte alignment, align 4 + 1-byte offset = align 1, etc. 4216 unsigned FIInfoAlign = MinAlign(MFI.getObjectAlignment(FrameIdx), 4217 FrameOffset); 4218 return std::max(Align, FIInfoAlign); 4219 } 4220 } 4221 4222 return 0; 4223} 4224 4225SDOperand DAGCombiner::visitLOAD(SDNode *N) { 4226 LoadSDNode *LD = cast<LoadSDNode>(N); 4227 SDOperand Chain = LD->getChain(); 4228 SDOperand Ptr = LD->getBasePtr(); 4229 4230 // Try to infer better alignment information than the load already has. 4231 if (LD->isUnindexed()) { 4232 if (unsigned Align = InferAlignment(Ptr, DAG)) { 4233 if (Align > LD->getAlignment()) 4234 return DAG.getExtLoad(LD->getExtensionType(), LD->getValueType(0), 4235 Chain, Ptr, LD->getSrcValue(), 4236 LD->getSrcValueOffset(), LD->getMemoryVT(), 4237 LD->isVolatile(), Align); 4238 } 4239 } 4240 4241 4242 // If load is not volatile and there are no uses of the loaded value (and 4243 // the updated indexed value in case of indexed loads), change uses of the 4244 // chain value into uses of the chain input (i.e. delete the dead load). 4245 if (!LD->isVolatile()) { 4246 if (N->getValueType(1) == MVT::Other) { 4247 // Unindexed loads. 4248 if (N->hasNUsesOfValue(0, 0)) { 4249 // It's not safe to use the two value CombineTo variant here. e.g. 4250 // v1, chain2 = load chain1, loc 4251 // v2, chain3 = load chain2, loc 4252 // v3 = add v2, c 4253 // Now we replace use of chain2 with chain1. This makes the second load 4254 // isomorphic to the one we are deleting, and thus makes this load live. 4255 DOUT << "\nReplacing.6 "; DEBUG(N->dump(&DAG)); 4256 DOUT << "\nWith chain: "; DEBUG(Chain.Val->dump(&DAG)); 4257 DOUT << "\n"; 4258 WorkListRemover DeadNodes(*this); 4259 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1), Chain, &DeadNodes); 4260 if (N->use_empty()) { 4261 removeFromWorkList(N); 4262 DAG.DeleteNode(N); 4263 } 4264 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 4265 } 4266 } else { 4267 // Indexed loads. 4268 assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?"); 4269 if (N->hasNUsesOfValue(0, 0) && N->hasNUsesOfValue(0, 1)) { 4270 SDOperand Undef = DAG.getNode(ISD::UNDEF, N->getValueType(0)); 4271 DOUT << "\nReplacing.6 "; DEBUG(N->dump(&DAG)); 4272 DOUT << "\nWith: "; DEBUG(Undef.Val->dump(&DAG)); 4273 DOUT << " and 2 other values\n"; 4274 WorkListRemover DeadNodes(*this); 4275 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 0), Undef, &DeadNodes); 4276 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 1), 4277 DAG.getNode(ISD::UNDEF, N->getValueType(1)), 4278 &DeadNodes); 4279 DAG.ReplaceAllUsesOfValueWith(SDOperand(N, 2), Chain, &DeadNodes); 4280 removeFromWorkList(N); 4281 DAG.DeleteNode(N); 4282 return SDOperand(N, 0); // Return N so it doesn't get rechecked! 4283 } 4284 } 4285 } 4286 4287 // If this load is directly stored, replace the load value with the stored 4288 // value. 4289 // TODO: Handle store large -> read small portion. 4290 // TODO: Handle TRUNCSTORE/LOADEXT 4291 if (LD->getExtensionType() == ISD::NON_EXTLOAD) { 4292 if (ISD::isNON_TRUNCStore(Chain.Val)) { 4293 StoreSDNode *PrevST = cast<StoreSDNode>(Chain); 4294 if (PrevST->getBasePtr() == Ptr && 4295 PrevST->getValue().getValueType() == N->getValueType(0)) 4296 return CombineTo(N, Chain.getOperand(1), Chain); 4297 } 4298 } 4299 4300 if (CombinerAA) { 4301 // Walk up chain skipping non-aliasing memory nodes. 4302 SDOperand BetterChain = FindBetterChain(N, Chain); 4303 4304 // If there is a better chain. 4305 if (Chain != BetterChain) { 4306 SDOperand ReplLoad; 4307 4308 // Replace the chain to void dependency. 4309 if (LD->getExtensionType() == ISD::NON_EXTLOAD) { 4310 ReplLoad = DAG.getLoad(N->getValueType(0), BetterChain, Ptr, 4311 LD->getSrcValue(), LD->getSrcValueOffset(), 4312 LD->isVolatile(), LD->getAlignment()); 4313 } else { 4314 ReplLoad = DAG.getExtLoad(LD->getExtensionType(), 4315 LD->getValueType(0), 4316 BetterChain, Ptr, LD->getSrcValue(), 4317 LD->getSrcValueOffset(), 4318 LD->getMemoryVT(), 4319 LD->isVolatile(), 4320 LD->getAlignment()); 4321 } 4322 4323 // Create token factor to keep old chain connected. 4324 SDOperand Token = DAG.getNode(ISD::TokenFactor, MVT::Other, 4325 Chain, ReplLoad.getValue(1)); 4326 4327 // Replace uses with load result and token factor. Don't add users 4328 // to work list. 4329 return CombineTo(N, ReplLoad.getValue(0), Token, false); 4330 } 4331 } 4332 4333 // Try transforming N to an indexed load. 4334 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 4335 return SDOperand(N, 0); 4336 4337 return SDOperand(); 4338} 4339 4340 4341SDOperand DAGCombiner::visitSTORE(SDNode *N) { 4342 StoreSDNode *ST = cast<StoreSDNode>(N); 4343 SDOperand Chain = ST->getChain(); 4344 SDOperand Value = ST->getValue(); 4345 SDOperand Ptr = ST->getBasePtr(); 4346 4347 // Try to infer better alignment information than the store already has. 4348 if (ST->isUnindexed()) { 4349 if (unsigned Align = InferAlignment(Ptr, DAG)) { 4350 if (Align > ST->getAlignment()) 4351 return DAG.getTruncStore(Chain, Value, Ptr, ST->getSrcValue(), 4352 ST->getSrcValueOffset(), ST->getMemoryVT(), 4353 ST->isVolatile(), Align); 4354 } 4355 } 4356 4357 // If this is a store of a bit convert, store the input value if the 4358 // resultant store does not need a higher alignment than the original. 4359 if (Value.getOpcode() == ISD::BIT_CONVERT && !ST->isTruncatingStore() && 4360 ST->isUnindexed()) { 4361 unsigned Align = ST->getAlignment(); 4362 MVT::ValueType SVT = Value.getOperand(0).getValueType(); 4363 unsigned OrigAlign = TLI.getTargetMachine().getTargetData()-> 4364 getABITypeAlignment(MVT::getTypeForValueType(SVT)); 4365 if (Align <= OrigAlign && TLI.isOperationLegal(ISD::STORE, SVT)) 4366 return DAG.getStore(Chain, Value.getOperand(0), Ptr, ST->getSrcValue(), 4367 ST->getSrcValueOffset(), ST->isVolatile(), Align); 4368 } 4369 4370 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 4371 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Value)) { 4372 if (Value.getOpcode() != ISD::TargetConstantFP) { 4373 SDOperand Tmp; 4374 switch (CFP->getValueType(0)) { 4375 default: assert(0 && "Unknown FP type"); 4376 case MVT::f80: // We don't do this for these yet. 4377 case MVT::f128: 4378 case MVT::ppcf128: 4379 break; 4380 case MVT::f32: 4381 if (!AfterLegalize || TLI.isTypeLegal(MVT::i32)) { 4382 Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF(). 4383 convertToAPInt().getZExtValue(), MVT::i32); 4384 return DAG.getStore(Chain, Tmp, Ptr, ST->getSrcValue(), 4385 ST->getSrcValueOffset(), ST->isVolatile(), 4386 ST->getAlignment()); 4387 } 4388 break; 4389 case MVT::f64: 4390 if (!AfterLegalize || TLI.isTypeLegal(MVT::i64)) { 4391 Tmp = DAG.getConstant(CFP->getValueAPF().convertToAPInt(). 4392 getZExtValue(), MVT::i64); 4393 return DAG.getStore(Chain, Tmp, Ptr, ST->getSrcValue(), 4394 ST->getSrcValueOffset(), ST->isVolatile(), 4395 ST->getAlignment()); 4396 } else if (TLI.isTypeLegal(MVT::i32)) { 4397 // Many FP stores are not made apparent until after legalize, e.g. for 4398 // argument passing. Since this is so common, custom legalize the 4399 // 64-bit integer store into two 32-bit stores. 4400 uint64_t Val = CFP->getValueAPF().convertToAPInt().getZExtValue(); 4401 SDOperand Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32); 4402 SDOperand Hi = DAG.getConstant(Val >> 32, MVT::i32); 4403 if (TLI.isBigEndian()) std::swap(Lo, Hi); 4404 4405 int SVOffset = ST->getSrcValueOffset(); 4406 unsigned Alignment = ST->getAlignment(); 4407 bool isVolatile = ST->isVolatile(); 4408 4409 SDOperand St0 = DAG.getStore(Chain, Lo, Ptr, ST->getSrcValue(), 4410 ST->getSrcValueOffset(), 4411 isVolatile, ST->getAlignment()); 4412 Ptr = DAG.getNode(ISD::ADD, Ptr.getValueType(), Ptr, 4413 DAG.getConstant(4, Ptr.getValueType())); 4414 SVOffset += 4; 4415 Alignment = MinAlign(Alignment, 4U); 4416 SDOperand St1 = DAG.getStore(Chain, Hi, Ptr, ST->getSrcValue(), 4417 SVOffset, isVolatile, Alignment); 4418 return DAG.getNode(ISD::TokenFactor, MVT::Other, St0, St1); 4419 } 4420 break; 4421 } 4422 } 4423 } 4424 4425 if (CombinerAA) { 4426 // Walk up chain skipping non-aliasing memory nodes. 4427 SDOperand BetterChain = FindBetterChain(N, Chain); 4428 4429 // If there is a better chain. 4430 if (Chain != BetterChain) { 4431 // Replace the chain to avoid dependency. 4432 SDOperand ReplStore; 4433 if (ST->isTruncatingStore()) { 4434 ReplStore = DAG.getTruncStore(BetterChain, Value, Ptr, 4435 ST->getSrcValue(),ST->getSrcValueOffset(), 4436 ST->getMemoryVT(), 4437 ST->isVolatile(), ST->getAlignment()); 4438 } else { 4439 ReplStore = DAG.getStore(BetterChain, Value, Ptr, 4440 ST->getSrcValue(), ST->getSrcValueOffset(), 4441 ST->isVolatile(), ST->getAlignment()); 4442 } 4443 4444 // Create token to keep both nodes around. 4445 SDOperand Token = 4446 DAG.getNode(ISD::TokenFactor, MVT::Other, Chain, ReplStore); 4447 4448 // Don't add users to work list. 4449 return CombineTo(N, Token, false); 4450 } 4451 } 4452 4453 // Try transforming N to an indexed store. 4454 if (CombineToPreIndexedLoadStore(N) || CombineToPostIndexedLoadStore(N)) 4455 return SDOperand(N, 0); 4456 4457 // FIXME: is there such a thing as a truncating indexed store? 4458 if (ST->isTruncatingStore() && ST->isUnindexed() && 4459 MVT::isInteger(Value.getValueType())) { 4460 // See if we can simplify the input to this truncstore with knowledge that 4461 // only the low bits are being used. For example: 4462 // "truncstore (or (shl x, 8), y), i8" -> "truncstore y, i8" 4463 SDOperand Shorter = 4464 GetDemandedBits(Value, MVT::getIntVTBitMask(ST->getMemoryVT())); 4465 AddToWorkList(Value.Val); 4466 if (Shorter.Val) 4467 return DAG.getTruncStore(Chain, Shorter, Ptr, ST->getSrcValue(), 4468 ST->getSrcValueOffset(), ST->getMemoryVT(), 4469 ST->isVolatile(), ST->getAlignment()); 4470 4471 // Otherwise, see if we can simplify the operation with 4472 // SimplifyDemandedBits, which only works if the value has a single use. 4473 if (SimplifyDemandedBits(Value, MVT::getIntVTBitMask(ST->getMemoryVT()))) 4474 return SDOperand(N, 0); 4475 } 4476 4477 // If this is a load followed by a store to the same location, then the store 4478 // is dead/noop. 4479 if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Value)) { 4480 if (Ld->getBasePtr() == Ptr && ST->getMemoryVT() == Ld->getMemoryVT() && 4481 ST->isUnindexed() && !ST->isVolatile() && 4482 // There can't be any side effects between the load and store, such as 4483 // a call or store. 4484 Chain.reachesChainWithoutSideEffects(SDOperand(Ld, 1))) { 4485 // The store is dead, remove it. 4486 return Chain; 4487 } 4488 } 4489 4490 // If this is an FP_ROUND or TRUNC followed by a store, fold this into a 4491 // truncating store. We can do this even if this is already a truncstore. 4492 if ((Value.getOpcode() == ISD::FP_ROUND || Value.getOpcode() == ISD::TRUNCATE) 4493 && TLI.isTypeLegal(Value.getOperand(0).getValueType()) && 4494 Value.Val->hasOneUse() && ST->isUnindexed() && 4495 TLI.isTruncStoreLegal(Value.getOperand(0).getValueType(), 4496 ST->getMemoryVT())) { 4497 return DAG.getTruncStore(Chain, Value.getOperand(0), Ptr, ST->getSrcValue(), 4498 ST->getSrcValueOffset(), ST->getMemoryVT(), 4499 ST->isVolatile(), ST->getAlignment()); 4500 } 4501 4502 return SDOperand(); 4503} 4504 4505SDOperand DAGCombiner::visitINSERT_VECTOR_ELT(SDNode *N) { 4506 SDOperand InVec = N->getOperand(0); 4507 SDOperand InVal = N->getOperand(1); 4508 SDOperand EltNo = N->getOperand(2); 4509 4510 // If the invec is a BUILD_VECTOR and if EltNo is a constant, build a new 4511 // vector with the inserted element. 4512 if (InVec.getOpcode() == ISD::BUILD_VECTOR && isa<ConstantSDNode>(EltNo)) { 4513 unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue(); 4514 SmallVector<SDOperand, 8> Ops(InVec.Val->op_begin(), InVec.Val->op_end()); 4515 if (Elt < Ops.size()) 4516 Ops[Elt] = InVal; 4517 return DAG.getNode(ISD::BUILD_VECTOR, InVec.getValueType(), 4518 &Ops[0], Ops.size()); 4519 } 4520 4521 return SDOperand(); 4522} 4523 4524SDOperand DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) { 4525 SDOperand InVec = N->getOperand(0); 4526 SDOperand EltNo = N->getOperand(1); 4527 4528 // (vextract (v4f32 s2v (f32 load $addr)), 0) -> (f32 load $addr) 4529 // (vextract (v4i32 bc (v4f32 s2v (f32 load $addr))), 0) -> (i32 load $addr) 4530 if (isa<ConstantSDNode>(EltNo)) { 4531 unsigned Elt = cast<ConstantSDNode>(EltNo)->getValue(); 4532 bool NewLoad = false; 4533 if (Elt == 0) { 4534 MVT::ValueType VT = InVec.getValueType(); 4535 MVT::ValueType EVT = MVT::getVectorElementType(VT); 4536 MVT::ValueType LVT = EVT; 4537 unsigned NumElts = MVT::getVectorNumElements(VT); 4538 if (InVec.getOpcode() == ISD::BIT_CONVERT) { 4539 MVT::ValueType BCVT = InVec.getOperand(0).getValueType(); 4540 if (!MVT::isVector(BCVT) || 4541 NumElts != MVT::getVectorNumElements(BCVT)) 4542 return SDOperand(); 4543 InVec = InVec.getOperand(0); 4544 EVT = MVT::getVectorElementType(BCVT); 4545 NewLoad = true; 4546 } 4547 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR && 4548 InVec.getOperand(0).getValueType() == EVT && 4549 ISD::isNormalLoad(InVec.getOperand(0).Val) && 4550 InVec.getOperand(0).hasOneUse()) { 4551 LoadSDNode *LN0 = cast<LoadSDNode>(InVec.getOperand(0)); 4552 unsigned Align = LN0->getAlignment(); 4553 if (NewLoad) { 4554 // Check the resultant load doesn't need a higher alignment than the 4555 // original load. 4556 unsigned NewAlign = TLI.getTargetMachine().getTargetData()-> 4557 getABITypeAlignment(MVT::getTypeForValueType(LVT)); 4558 if (!TLI.isOperationLegal(ISD::LOAD, LVT) || NewAlign > Align) 4559 return SDOperand(); 4560 Align = NewAlign; 4561 } 4562 4563 return DAG.getLoad(LVT, LN0->getChain(), LN0->getBasePtr(), 4564 LN0->getSrcValue(), LN0->getSrcValueOffset(), 4565 LN0->isVolatile(), Align); 4566 } 4567 } 4568 } 4569 return SDOperand(); 4570} 4571 4572 4573SDOperand DAGCombiner::visitBUILD_VECTOR(SDNode *N) { 4574 unsigned NumInScalars = N->getNumOperands(); 4575 MVT::ValueType VT = N->getValueType(0); 4576 unsigned NumElts = MVT::getVectorNumElements(VT); 4577 MVT::ValueType EltType = MVT::getVectorElementType(VT); 4578 4579 // Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT 4580 // operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from 4581 // at most two distinct vectors, turn this into a shuffle node. 4582 SDOperand VecIn1, VecIn2; 4583 for (unsigned i = 0; i != NumInScalars; ++i) { 4584 // Ignore undef inputs. 4585 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue; 4586 4587 // If this input is something other than a EXTRACT_VECTOR_ELT with a 4588 // constant index, bail out. 4589 if (N->getOperand(i).getOpcode() != ISD::EXTRACT_VECTOR_ELT || 4590 !isa<ConstantSDNode>(N->getOperand(i).getOperand(1))) { 4591 VecIn1 = VecIn2 = SDOperand(0, 0); 4592 break; 4593 } 4594 4595 // If the input vector type disagrees with the result of the build_vector, 4596 // we can't make a shuffle. 4597 SDOperand ExtractedFromVec = N->getOperand(i).getOperand(0); 4598 if (ExtractedFromVec.getValueType() != VT) { 4599 VecIn1 = VecIn2 = SDOperand(0, 0); 4600 break; 4601 } 4602 4603 // Otherwise, remember this. We allow up to two distinct input vectors. 4604 if (ExtractedFromVec == VecIn1 || ExtractedFromVec == VecIn2) 4605 continue; 4606 4607 if (VecIn1.Val == 0) { 4608 VecIn1 = ExtractedFromVec; 4609 } else if (VecIn2.Val == 0) { 4610 VecIn2 = ExtractedFromVec; 4611 } else { 4612 // Too many inputs. 4613 VecIn1 = VecIn2 = SDOperand(0, 0); 4614 break; 4615 } 4616 } 4617 4618 // If everything is good, we can make a shuffle operation. 4619 if (VecIn1.Val) { 4620 SmallVector<SDOperand, 8> BuildVecIndices; 4621 for (unsigned i = 0; i != NumInScalars; ++i) { 4622 if (N->getOperand(i).getOpcode() == ISD::UNDEF) { 4623 BuildVecIndices.push_back(DAG.getNode(ISD::UNDEF, TLI.getPointerTy())); 4624 continue; 4625 } 4626 4627 SDOperand Extract = N->getOperand(i); 4628 4629 // If extracting from the first vector, just use the index directly. 4630 if (Extract.getOperand(0) == VecIn1) { 4631 BuildVecIndices.push_back(Extract.getOperand(1)); 4632 continue; 4633 } 4634 4635 // Otherwise, use InIdx + VecSize 4636 unsigned Idx = cast<ConstantSDNode>(Extract.getOperand(1))->getValue(); 4637 BuildVecIndices.push_back(DAG.getIntPtrConstant(Idx+NumInScalars)); 4638 } 4639 4640 // Add count and size info. 4641 MVT::ValueType BuildVecVT = MVT::getVectorType(TLI.getPointerTy(), NumElts); 4642 4643 // Return the new VECTOR_SHUFFLE node. 4644 SDOperand Ops[5]; 4645 Ops[0] = VecIn1; 4646 if (VecIn2.Val) { 4647 Ops[1] = VecIn2; 4648 } else { 4649 // Use an undef build_vector as input for the second operand. 4650 std::vector<SDOperand> UnOps(NumInScalars, 4651 DAG.getNode(ISD::UNDEF, 4652 EltType)); 4653 Ops[1] = DAG.getNode(ISD::BUILD_VECTOR, VT, 4654 &UnOps[0], UnOps.size()); 4655 AddToWorkList(Ops[1].Val); 4656 } 4657 Ops[2] = DAG.getNode(ISD::BUILD_VECTOR, BuildVecVT, 4658 &BuildVecIndices[0], BuildVecIndices.size()); 4659 return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, Ops, 3); 4660 } 4661 4662 return SDOperand(); 4663} 4664 4665SDOperand DAGCombiner::visitCONCAT_VECTORS(SDNode *N) { 4666 // TODO: Check to see if this is a CONCAT_VECTORS of a bunch of 4667 // EXTRACT_SUBVECTOR operations. If so, and if the EXTRACT_SUBVECTOR vector 4668 // inputs come from at most two distinct vectors, turn this into a shuffle 4669 // node. 4670 4671 // If we only have one input vector, we don't need to do any concatenation. 4672 if (N->getNumOperands() == 1) { 4673 return N->getOperand(0); 4674 } 4675 4676 return SDOperand(); 4677} 4678 4679SDOperand DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) { 4680 SDOperand ShufMask = N->getOperand(2); 4681 unsigned NumElts = ShufMask.getNumOperands(); 4682 4683 // If the shuffle mask is an identity operation on the LHS, return the LHS. 4684 bool isIdentity = true; 4685 for (unsigned i = 0; i != NumElts; ++i) { 4686 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF && 4687 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i) { 4688 isIdentity = false; 4689 break; 4690 } 4691 } 4692 if (isIdentity) return N->getOperand(0); 4693 4694 // If the shuffle mask is an identity operation on the RHS, return the RHS. 4695 isIdentity = true; 4696 for (unsigned i = 0; i != NumElts; ++i) { 4697 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF && 4698 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() != i+NumElts) { 4699 isIdentity = false; 4700 break; 4701 } 4702 } 4703 if (isIdentity) return N->getOperand(1); 4704 4705 // Check if the shuffle is a unary shuffle, i.e. one of the vectors is not 4706 // needed at all. 4707 bool isUnary = true; 4708 bool isSplat = true; 4709 int VecNum = -1; 4710 unsigned BaseIdx = 0; 4711 for (unsigned i = 0; i != NumElts; ++i) 4712 if (ShufMask.getOperand(i).getOpcode() != ISD::UNDEF) { 4713 unsigned Idx = cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue(); 4714 int V = (Idx < NumElts) ? 0 : 1; 4715 if (VecNum == -1) { 4716 VecNum = V; 4717 BaseIdx = Idx; 4718 } else { 4719 if (BaseIdx != Idx) 4720 isSplat = false; 4721 if (VecNum != V) { 4722 isUnary = false; 4723 break; 4724 } 4725 } 4726 } 4727 4728 SDOperand N0 = N->getOperand(0); 4729 SDOperand N1 = N->getOperand(1); 4730 // Normalize unary shuffle so the RHS is undef. 4731 if (isUnary && VecNum == 1) 4732 std::swap(N0, N1); 4733 4734 // If it is a splat, check if the argument vector is a build_vector with 4735 // all scalar elements the same. 4736 if (isSplat) { 4737 SDNode *V = N0.Val; 4738 4739 // If this is a bit convert that changes the element type of the vector but 4740 // not the number of vector elements, look through it. Be careful not to 4741 // look though conversions that change things like v4f32 to v2f64. 4742 if (V->getOpcode() == ISD::BIT_CONVERT) { 4743 SDOperand ConvInput = V->getOperand(0); 4744 if (MVT::getVectorNumElements(ConvInput.getValueType()) == NumElts) 4745 V = ConvInput.Val; 4746 } 4747 4748 if (V->getOpcode() == ISD::BUILD_VECTOR) { 4749 unsigned NumElems = V->getNumOperands(); 4750 if (NumElems > BaseIdx) { 4751 SDOperand Base; 4752 bool AllSame = true; 4753 for (unsigned i = 0; i != NumElems; ++i) { 4754 if (V->getOperand(i).getOpcode() != ISD::UNDEF) { 4755 Base = V->getOperand(i); 4756 break; 4757 } 4758 } 4759 // Splat of <u, u, u, u>, return <u, u, u, u> 4760 if (!Base.Val) 4761 return N0; 4762 for (unsigned i = 0; i != NumElems; ++i) { 4763 if (V->getOperand(i) != Base) { 4764 AllSame = false; 4765 break; 4766 } 4767 } 4768 // Splat of <x, x, x, x>, return <x, x, x, x> 4769 if (AllSame) 4770 return N0; 4771 } 4772 } 4773 } 4774 4775 // If it is a unary or the LHS and the RHS are the same node, turn the RHS 4776 // into an undef. 4777 if (isUnary || N0 == N1) { 4778 // Check the SHUFFLE mask, mapping any inputs from the 2nd operand into the 4779 // first operand. 4780 SmallVector<SDOperand, 8> MappedOps; 4781 for (unsigned i = 0; i != NumElts; ++i) { 4782 if (ShufMask.getOperand(i).getOpcode() == ISD::UNDEF || 4783 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() < NumElts) { 4784 MappedOps.push_back(ShufMask.getOperand(i)); 4785 } else { 4786 unsigned NewIdx = 4787 cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() - NumElts; 4788 MappedOps.push_back(DAG.getConstant(NewIdx, MVT::i32)); 4789 } 4790 } 4791 ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMask.getValueType(), 4792 &MappedOps[0], MappedOps.size()); 4793 AddToWorkList(ShufMask.Val); 4794 return DAG.getNode(ISD::VECTOR_SHUFFLE, N->getValueType(0), 4795 N0, 4796 DAG.getNode(ISD::UNDEF, N->getValueType(0)), 4797 ShufMask); 4798 } 4799 4800 return SDOperand(); 4801} 4802 4803/// XformToShuffleWithZero - Returns a vector_shuffle if it able to transform 4804/// an AND to a vector_shuffle with the destination vector and a zero vector. 4805/// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==> 4806/// vector_shuffle V, Zero, <0, 4, 2, 4> 4807SDOperand DAGCombiner::XformToShuffleWithZero(SDNode *N) { 4808 SDOperand LHS = N->getOperand(0); 4809 SDOperand RHS = N->getOperand(1); 4810 if (N->getOpcode() == ISD::AND) { 4811 if (RHS.getOpcode() == ISD::BIT_CONVERT) 4812 RHS = RHS.getOperand(0); 4813 if (RHS.getOpcode() == ISD::BUILD_VECTOR) { 4814 std::vector<SDOperand> IdxOps; 4815 unsigned NumOps = RHS.getNumOperands(); 4816 unsigned NumElts = NumOps; 4817 MVT::ValueType EVT = MVT::getVectorElementType(RHS.getValueType()); 4818 for (unsigned i = 0; i != NumElts; ++i) { 4819 SDOperand Elt = RHS.getOperand(i); 4820 if (!isa<ConstantSDNode>(Elt)) 4821 return SDOperand(); 4822 else if (cast<ConstantSDNode>(Elt)->isAllOnesValue()) 4823 IdxOps.push_back(DAG.getConstant(i, EVT)); 4824 else if (cast<ConstantSDNode>(Elt)->isNullValue()) 4825 IdxOps.push_back(DAG.getConstant(NumElts, EVT)); 4826 else 4827 return SDOperand(); 4828 } 4829 4830 // Let's see if the target supports this vector_shuffle. 4831 if (!TLI.isVectorClearMaskLegal(IdxOps, EVT, DAG)) 4832 return SDOperand(); 4833 4834 // Return the new VECTOR_SHUFFLE node. 4835 MVT::ValueType VT = MVT::getVectorType(EVT, NumElts); 4836 std::vector<SDOperand> Ops; 4837 LHS = DAG.getNode(ISD::BIT_CONVERT, VT, LHS); 4838 Ops.push_back(LHS); 4839 AddToWorkList(LHS.Val); 4840 std::vector<SDOperand> ZeroOps(NumElts, DAG.getConstant(0, EVT)); 4841 Ops.push_back(DAG.getNode(ISD::BUILD_VECTOR, VT, 4842 &ZeroOps[0], ZeroOps.size())); 4843 Ops.push_back(DAG.getNode(ISD::BUILD_VECTOR, VT, 4844 &IdxOps[0], IdxOps.size())); 4845 SDOperand Result = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, 4846 &Ops[0], Ops.size()); 4847 if (VT != LHS.getValueType()) { 4848 Result = DAG.getNode(ISD::BIT_CONVERT, LHS.getValueType(), Result); 4849 } 4850 return Result; 4851 } 4852 } 4853 return SDOperand(); 4854} 4855 4856/// SimplifyVBinOp - Visit a binary vector operation, like ADD. 4857SDOperand DAGCombiner::SimplifyVBinOp(SDNode *N) { 4858 // After legalize, the target may be depending on adds and other 4859 // binary ops to provide legal ways to construct constants or other 4860 // things. Simplifying them may result in a loss of legality. 4861 if (AfterLegalize) return SDOperand(); 4862 4863 MVT::ValueType VT = N->getValueType(0); 4864 assert(MVT::isVector(VT) && "SimplifyVBinOp only works on vectors!"); 4865 4866 MVT::ValueType EltType = MVT::getVectorElementType(VT); 4867 SDOperand LHS = N->getOperand(0); 4868 SDOperand RHS = N->getOperand(1); 4869 SDOperand Shuffle = XformToShuffleWithZero(N); 4870 if (Shuffle.Val) return Shuffle; 4871 4872 // If the LHS and RHS are BUILD_VECTOR nodes, see if we can constant fold 4873 // this operation. 4874 if (LHS.getOpcode() == ISD::BUILD_VECTOR && 4875 RHS.getOpcode() == ISD::BUILD_VECTOR) { 4876 SmallVector<SDOperand, 8> Ops; 4877 for (unsigned i = 0, e = LHS.getNumOperands(); i != e; ++i) { 4878 SDOperand LHSOp = LHS.getOperand(i); 4879 SDOperand RHSOp = RHS.getOperand(i); 4880 // If these two elements can't be folded, bail out. 4881 if ((LHSOp.getOpcode() != ISD::UNDEF && 4882 LHSOp.getOpcode() != ISD::Constant && 4883 LHSOp.getOpcode() != ISD::ConstantFP) || 4884 (RHSOp.getOpcode() != ISD::UNDEF && 4885 RHSOp.getOpcode() != ISD::Constant && 4886 RHSOp.getOpcode() != ISD::ConstantFP)) 4887 break; 4888 // Can't fold divide by zero. 4889 if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV || 4890 N->getOpcode() == ISD::FDIV) { 4891 if ((RHSOp.getOpcode() == ISD::Constant && 4892 cast<ConstantSDNode>(RHSOp.Val)->isNullValue()) || 4893 (RHSOp.getOpcode() == ISD::ConstantFP && 4894 cast<ConstantFPSDNode>(RHSOp.Val)->getValueAPF().isZero())) 4895 break; 4896 } 4897 Ops.push_back(DAG.getNode(N->getOpcode(), EltType, LHSOp, RHSOp)); 4898 AddToWorkList(Ops.back().Val); 4899 assert((Ops.back().getOpcode() == ISD::UNDEF || 4900 Ops.back().getOpcode() == ISD::Constant || 4901 Ops.back().getOpcode() == ISD::ConstantFP) && 4902 "Scalar binop didn't fold!"); 4903 } 4904 4905 if (Ops.size() == LHS.getNumOperands()) { 4906 MVT::ValueType VT = LHS.getValueType(); 4907 return DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], Ops.size()); 4908 } 4909 } 4910 4911 return SDOperand(); 4912} 4913 4914SDOperand DAGCombiner::SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2){ 4915 assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!"); 4916 4917 SDOperand SCC = SimplifySelectCC(N0.getOperand(0), N0.getOperand(1), N1, N2, 4918 cast<CondCodeSDNode>(N0.getOperand(2))->get()); 4919 // If we got a simplified select_cc node back from SimplifySelectCC, then 4920 // break it down into a new SETCC node, and a new SELECT node, and then return 4921 // the SELECT node, since we were called with a SELECT node. 4922 if (SCC.Val) { 4923 // Check to see if we got a select_cc back (to turn into setcc/select). 4924 // Otherwise, just return whatever node we got back, like fabs. 4925 if (SCC.getOpcode() == ISD::SELECT_CC) { 4926 SDOperand SETCC = DAG.getNode(ISD::SETCC, N0.getValueType(), 4927 SCC.getOperand(0), SCC.getOperand(1), 4928 SCC.getOperand(4)); 4929 AddToWorkList(SETCC.Val); 4930 return DAG.getNode(ISD::SELECT, SCC.getValueType(), SCC.getOperand(2), 4931 SCC.getOperand(3), SETCC); 4932 } 4933 return SCC; 4934 } 4935 return SDOperand(); 4936} 4937 4938/// SimplifySelectOps - Given a SELECT or a SELECT_CC node, where LHS and RHS 4939/// are the two values being selected between, see if we can simplify the 4940/// select. Callers of this should assume that TheSelect is deleted if this 4941/// returns true. As such, they should return the appropriate thing (e.g. the 4942/// node) back to the top-level of the DAG combiner loop to avoid it being 4943/// looked at. 4944/// 4945bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDOperand LHS, 4946 SDOperand RHS) { 4947 4948 // If this is a select from two identical things, try to pull the operation 4949 // through the select. 4950 if (LHS.getOpcode() == RHS.getOpcode() && LHS.hasOneUse() && RHS.hasOneUse()){ 4951 // If this is a load and the token chain is identical, replace the select 4952 // of two loads with a load through a select of the address to load from. 4953 // This triggers in things like "select bool X, 10.0, 123.0" after the FP 4954 // constants have been dropped into the constant pool. 4955 if (LHS.getOpcode() == ISD::LOAD && 4956 // Token chains must be identical. 4957 LHS.getOperand(0) == RHS.getOperand(0)) { 4958 LoadSDNode *LLD = cast<LoadSDNode>(LHS); 4959 LoadSDNode *RLD = cast<LoadSDNode>(RHS); 4960 4961 // If this is an EXTLOAD, the VT's must match. 4962 if (LLD->getMemoryVT() == RLD->getMemoryVT()) { 4963 // FIXME: this conflates two src values, discarding one. This is not 4964 // the right thing to do, but nothing uses srcvalues now. When they do, 4965 // turn SrcValue into a list of locations. 4966 SDOperand Addr; 4967 if (TheSelect->getOpcode() == ISD::SELECT) { 4968 // Check that the condition doesn't reach either load. If so, folding 4969 // this will induce a cycle into the DAG. 4970 if (!LLD->isPredecessor(TheSelect->getOperand(0).Val) && 4971 !RLD->isPredecessor(TheSelect->getOperand(0).Val)) { 4972 Addr = DAG.getNode(ISD::SELECT, LLD->getBasePtr().getValueType(), 4973 TheSelect->getOperand(0), LLD->getBasePtr(), 4974 RLD->getBasePtr()); 4975 } 4976 } else { 4977 // Check that the condition doesn't reach either load. If so, folding 4978 // this will induce a cycle into the DAG. 4979 if (!LLD->isPredecessor(TheSelect->getOperand(0).Val) && 4980 !RLD->isPredecessor(TheSelect->getOperand(0).Val) && 4981 !LLD->isPredecessor(TheSelect->getOperand(1).Val) && 4982 !RLD->isPredecessor(TheSelect->getOperand(1).Val)) { 4983 Addr = DAG.getNode(ISD::SELECT_CC, LLD->getBasePtr().getValueType(), 4984 TheSelect->getOperand(0), 4985 TheSelect->getOperand(1), 4986 LLD->getBasePtr(), RLD->getBasePtr(), 4987 TheSelect->getOperand(4)); 4988 } 4989 } 4990 4991 if (Addr.Val) { 4992 SDOperand Load; 4993 if (LLD->getExtensionType() == ISD::NON_EXTLOAD) 4994 Load = DAG.getLoad(TheSelect->getValueType(0), LLD->getChain(), 4995 Addr,LLD->getSrcValue(), 4996 LLD->getSrcValueOffset(), 4997 LLD->isVolatile(), 4998 LLD->getAlignment()); 4999 else { 5000 Load = DAG.getExtLoad(LLD->getExtensionType(), 5001 TheSelect->getValueType(0), 5002 LLD->getChain(), Addr, LLD->getSrcValue(), 5003 LLD->getSrcValueOffset(), 5004 LLD->getMemoryVT(), 5005 LLD->isVolatile(), 5006 LLD->getAlignment()); 5007 } 5008 // Users of the select now use the result of the load. 5009 CombineTo(TheSelect, Load); 5010 5011 // Users of the old loads now use the new load's chain. We know the 5012 // old-load value is dead now. 5013 CombineTo(LHS.Val, Load.getValue(0), Load.getValue(1)); 5014 CombineTo(RHS.Val, Load.getValue(0), Load.getValue(1)); 5015 return true; 5016 } 5017 } 5018 } 5019 } 5020 5021 return false; 5022} 5023 5024SDOperand DAGCombiner::SimplifySelectCC(SDOperand N0, SDOperand N1, 5025 SDOperand N2, SDOperand N3, 5026 ISD::CondCode CC, bool NotExtCompare) { 5027 5028 MVT::ValueType VT = N2.getValueType(); 5029 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.Val); 5030 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.Val); 5031 ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.Val); 5032 5033 // Determine if the condition we're dealing with is constant 5034 SDOperand SCC = SimplifySetCC(TLI.getSetCCResultTy(), N0, N1, CC, false); 5035 if (SCC.Val) AddToWorkList(SCC.Val); 5036 ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.Val); 5037 5038 // fold select_cc true, x, y -> x 5039 if (SCCC && SCCC->getValue()) 5040 return N2; 5041 // fold select_cc false, x, y -> y 5042 if (SCCC && SCCC->getValue() == 0) 5043 return N3; 5044 5045 // Check to see if we can simplify the select into an fabs node 5046 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N1)) { 5047 // Allow either -0.0 or 0.0 5048 if (CFP->getValueAPF().isZero()) { 5049 // select (setg[te] X, +/-0.0), X, fneg(X) -> fabs 5050 if ((CC == ISD::SETGE || CC == ISD::SETGT) && 5051 N0 == N2 && N3.getOpcode() == ISD::FNEG && 5052 N2 == N3.getOperand(0)) 5053 return DAG.getNode(ISD::FABS, VT, N0); 5054 5055 // select (setl[te] X, +/-0.0), fneg(X), X -> fabs 5056 if ((CC == ISD::SETLT || CC == ISD::SETLE) && 5057 N0 == N3 && N2.getOpcode() == ISD::FNEG && 5058 N2.getOperand(0) == N3) 5059 return DAG.getNode(ISD::FABS, VT, N3); 5060 } 5061 } 5062 5063 // Check to see if we can perform the "gzip trick", transforming 5064 // select_cc setlt X, 0, A, 0 -> and (sra X, size(X)-1), A 5065 if (N1C && N3C && N3C->isNullValue() && CC == ISD::SETLT && 5066 MVT::isInteger(N0.getValueType()) && 5067 MVT::isInteger(N2.getValueType()) && 5068 (N1C->isNullValue() || // (a < 0) ? b : 0 5069 (N1C->getValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0 5070 MVT::ValueType XType = N0.getValueType(); 5071 MVT::ValueType AType = N2.getValueType(); 5072 if (XType >= AType) { 5073 // and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a 5074 // single-bit constant. 5075 if (N2C && ((N2C->getValue() & (N2C->getValue()-1)) == 0)) { 5076 unsigned ShCtV = Log2_64(N2C->getValue()); 5077 ShCtV = MVT::getSizeInBits(XType)-ShCtV-1; 5078 SDOperand ShCt = DAG.getConstant(ShCtV, TLI.getShiftAmountTy()); 5079 SDOperand Shift = DAG.getNode(ISD::SRL, XType, N0, ShCt); 5080 AddToWorkList(Shift.Val); 5081 if (XType > AType) { 5082 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift); 5083 AddToWorkList(Shift.Val); 5084 } 5085 return DAG.getNode(ISD::AND, AType, Shift, N2); 5086 } 5087 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0, 5088 DAG.getConstant(MVT::getSizeInBits(XType)-1, 5089 TLI.getShiftAmountTy())); 5090 AddToWorkList(Shift.Val); 5091 if (XType > AType) { 5092 Shift = DAG.getNode(ISD::TRUNCATE, AType, Shift); 5093 AddToWorkList(Shift.Val); 5094 } 5095 return DAG.getNode(ISD::AND, AType, Shift, N2); 5096 } 5097 } 5098 5099 // fold select C, 16, 0 -> shl C, 4 5100 if (N2C && N3C && N3C->isNullValue() && isPowerOf2_64(N2C->getValue()) && 5101 TLI.getSetCCResultContents() == TargetLowering::ZeroOrOneSetCCResult) { 5102 5103 // If the caller doesn't want us to simplify this into a zext of a compare, 5104 // don't do it. 5105 if (NotExtCompare && N2C->getValue() == 1) 5106 return SDOperand(); 5107 5108 // Get a SetCC of the condition 5109 // FIXME: Should probably make sure that setcc is legal if we ever have a 5110 // target where it isn't. 5111 SDOperand Temp, SCC; 5112 // cast from setcc result type to select result type 5113 if (AfterLegalize) { 5114 SCC = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC); 5115 if (N2.getValueType() < SCC.getValueType()) 5116 Temp = DAG.getZeroExtendInReg(SCC, N2.getValueType()); 5117 else 5118 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC); 5119 } else { 5120 SCC = DAG.getSetCC(MVT::i1, N0, N1, CC); 5121 Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getValueType(), SCC); 5122 } 5123 AddToWorkList(SCC.Val); 5124 AddToWorkList(Temp.Val); 5125 5126 if (N2C->getValue() == 1) 5127 return Temp; 5128 // shl setcc result by log2 n2c 5129 return DAG.getNode(ISD::SHL, N2.getValueType(), Temp, 5130 DAG.getConstant(Log2_64(N2C->getValue()), 5131 TLI.getShiftAmountTy())); 5132 } 5133 5134 // Check to see if this is the equivalent of setcc 5135 // FIXME: Turn all of these into setcc if setcc if setcc is legal 5136 // otherwise, go ahead with the folds. 5137 if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getValue() == 1ULL)) { 5138 MVT::ValueType XType = N0.getValueType(); 5139 if (TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultTy())) { 5140 SDOperand Res = DAG.getSetCC(TLI.getSetCCResultTy(), N0, N1, CC); 5141 if (Res.getValueType() != VT) 5142 Res = DAG.getNode(ISD::ZERO_EXTEND, VT, Res); 5143 return Res; 5144 } 5145 5146 // seteq X, 0 -> srl (ctlz X, log2(size(X))) 5147 if (N1C && N1C->isNullValue() && CC == ISD::SETEQ && 5148 TLI.isOperationLegal(ISD::CTLZ, XType)) { 5149 SDOperand Ctlz = DAG.getNode(ISD::CTLZ, XType, N0); 5150 return DAG.getNode(ISD::SRL, XType, Ctlz, 5151 DAG.getConstant(Log2_32(MVT::getSizeInBits(XType)), 5152 TLI.getShiftAmountTy())); 5153 } 5154 // setgt X, 0 -> srl (and (-X, ~X), size(X)-1) 5155 if (N1C && N1C->isNullValue() && CC == ISD::SETGT) { 5156 SDOperand NegN0 = DAG.getNode(ISD::SUB, XType, DAG.getConstant(0, XType), 5157 N0); 5158 SDOperand NotN0 = DAG.getNode(ISD::XOR, XType, N0, 5159 DAG.getConstant(~0ULL, XType)); 5160 return DAG.getNode(ISD::SRL, XType, 5161 DAG.getNode(ISD::AND, XType, NegN0, NotN0), 5162 DAG.getConstant(MVT::getSizeInBits(XType)-1, 5163 TLI.getShiftAmountTy())); 5164 } 5165 // setgt X, -1 -> xor (srl (X, size(X)-1), 1) 5166 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT) { 5167 SDOperand Sign = DAG.getNode(ISD::SRL, XType, N0, 5168 DAG.getConstant(MVT::getSizeInBits(XType)-1, 5169 TLI.getShiftAmountTy())); 5170 return DAG.getNode(ISD::XOR, XType, Sign, DAG.getConstant(1, XType)); 5171 } 5172 } 5173 5174 // Check to see if this is an integer abs. select_cc setl[te] X, 0, -X, X -> 5175 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 5176 if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) && 5177 N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1) && 5178 N2.getOperand(0) == N1 && MVT::isInteger(N0.getValueType())) { 5179 MVT::ValueType XType = N0.getValueType(); 5180 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0, 5181 DAG.getConstant(MVT::getSizeInBits(XType)-1, 5182 TLI.getShiftAmountTy())); 5183 SDOperand Add = DAG.getNode(ISD::ADD, XType, N0, Shift); 5184 AddToWorkList(Shift.Val); 5185 AddToWorkList(Add.Val); 5186 return DAG.getNode(ISD::XOR, XType, Add, Shift); 5187 } 5188 // Check to see if this is an integer abs. select_cc setgt X, -1, X, -X -> 5189 // Y = sra (X, size(X)-1); xor (add (X, Y), Y) 5190 if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT && 5191 N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1)) { 5192 if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0))) { 5193 MVT::ValueType XType = N0.getValueType(); 5194 if (SubC->isNullValue() && MVT::isInteger(XType)) { 5195 SDOperand Shift = DAG.getNode(ISD::SRA, XType, N0, 5196 DAG.getConstant(MVT::getSizeInBits(XType)-1, 5197 TLI.getShiftAmountTy())); 5198 SDOperand Add = DAG.getNode(ISD::ADD, XType, N0, Shift); 5199 AddToWorkList(Shift.Val); 5200 AddToWorkList(Add.Val); 5201 return DAG.getNode(ISD::XOR, XType, Add, Shift); 5202 } 5203 } 5204 } 5205 5206 return SDOperand(); 5207} 5208 5209/// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC. 5210SDOperand DAGCombiner::SimplifySetCC(MVT::ValueType VT, SDOperand N0, 5211 SDOperand N1, ISD::CondCode Cond, 5212 bool foldBooleans) { 5213 TargetLowering::DAGCombinerInfo 5214 DagCombineInfo(DAG, !AfterLegalize, false, this); 5215 return TLI.SimplifySetCC(VT, N0, N1, Cond, foldBooleans, DagCombineInfo); 5216} 5217 5218/// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant, 5219/// return a DAG expression to select that will generate the same value by 5220/// multiplying by a magic number. See: 5221/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 5222SDOperand DAGCombiner::BuildSDIV(SDNode *N) { 5223 std::vector<SDNode*> Built; 5224 SDOperand S = TLI.BuildSDIV(N, DAG, &Built); 5225 5226 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 5227 ii != ee; ++ii) 5228 AddToWorkList(*ii); 5229 return S; 5230} 5231 5232/// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant, 5233/// return a DAG expression to select that will generate the same value by 5234/// multiplying by a magic number. See: 5235/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html> 5236SDOperand DAGCombiner::BuildUDIV(SDNode *N) { 5237 std::vector<SDNode*> Built; 5238 SDOperand S = TLI.BuildUDIV(N, DAG, &Built); 5239 5240 for (std::vector<SDNode*>::iterator ii = Built.begin(), ee = Built.end(); 5241 ii != ee; ++ii) 5242 AddToWorkList(*ii); 5243 return S; 5244} 5245 5246/// FindBaseOffset - Return true if base is known not to alias with anything 5247/// but itself. Provides base object and offset as results. 5248static bool FindBaseOffset(SDOperand Ptr, SDOperand &Base, int64_t &Offset) { 5249 // Assume it is a primitive operation. 5250 Base = Ptr; Offset = 0; 5251 5252 // If it's an adding a simple constant then integrate the offset. 5253 if (Base.getOpcode() == ISD::ADD) { 5254 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) { 5255 Base = Base.getOperand(0); 5256 Offset += C->getValue(); 5257 } 5258 } 5259 5260 // If it's any of the following then it can't alias with anything but itself. 5261 return isa<FrameIndexSDNode>(Base) || 5262 isa<ConstantPoolSDNode>(Base) || 5263 isa<GlobalAddressSDNode>(Base); 5264} 5265 5266/// isAlias - Return true if there is any possibility that the two addresses 5267/// overlap. 5268bool DAGCombiner::isAlias(SDOperand Ptr1, int64_t Size1, 5269 const Value *SrcValue1, int SrcValueOffset1, 5270 SDOperand Ptr2, int64_t Size2, 5271 const Value *SrcValue2, int SrcValueOffset2) 5272{ 5273 // If they are the same then they must be aliases. 5274 if (Ptr1 == Ptr2) return true; 5275 5276 // Gather base node and offset information. 5277 SDOperand Base1, Base2; 5278 int64_t Offset1, Offset2; 5279 bool KnownBase1 = FindBaseOffset(Ptr1, Base1, Offset1); 5280 bool KnownBase2 = FindBaseOffset(Ptr2, Base2, Offset2); 5281 5282 // If they have a same base address then... 5283 if (Base1 == Base2) { 5284 // Check to see if the addresses overlap. 5285 return!((Offset1 + Size1) <= Offset2 || (Offset2 + Size2) <= Offset1); 5286 } 5287 5288 // If we know both bases then they can't alias. 5289 if (KnownBase1 && KnownBase2) return false; 5290 5291 if (CombinerGlobalAA) { 5292 // Use alias analysis information. 5293 int64_t MinOffset = std::min(SrcValueOffset1, SrcValueOffset2); 5294 int64_t Overlap1 = Size1 + SrcValueOffset1 - MinOffset; 5295 int64_t Overlap2 = Size2 + SrcValueOffset2 - MinOffset; 5296 AliasAnalysis::AliasResult AAResult = 5297 AA.alias(SrcValue1, Overlap1, SrcValue2, Overlap2); 5298 if (AAResult == AliasAnalysis::NoAlias) 5299 return false; 5300 } 5301 5302 // Otherwise we have to assume they alias. 5303 return true; 5304} 5305 5306/// FindAliasInfo - Extracts the relevant alias information from the memory 5307/// node. Returns true if the operand was a load. 5308bool DAGCombiner::FindAliasInfo(SDNode *N, 5309 SDOperand &Ptr, int64_t &Size, 5310 const Value *&SrcValue, int &SrcValueOffset) { 5311 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { 5312 Ptr = LD->getBasePtr(); 5313 Size = MVT::getSizeInBits(LD->getMemoryVT()) >> 3; 5314 SrcValue = LD->getSrcValue(); 5315 SrcValueOffset = LD->getSrcValueOffset(); 5316 return true; 5317 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { 5318 Ptr = ST->getBasePtr(); 5319 Size = MVT::getSizeInBits(ST->getMemoryVT()) >> 3; 5320 SrcValue = ST->getSrcValue(); 5321 SrcValueOffset = ST->getSrcValueOffset(); 5322 } else { 5323 assert(0 && "FindAliasInfo expected a memory operand"); 5324 } 5325 5326 return false; 5327} 5328 5329/// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, 5330/// looking for aliasing nodes and adding them to the Aliases vector. 5331void DAGCombiner::GatherAllAliases(SDNode *N, SDOperand OriginalChain, 5332 SmallVector<SDOperand, 8> &Aliases) { 5333 SmallVector<SDOperand, 8> Chains; // List of chains to visit. 5334 std::set<SDNode *> Visited; // Visited node set. 5335 5336 // Get alias information for node. 5337 SDOperand Ptr; 5338 int64_t Size; 5339 const Value *SrcValue; 5340 int SrcValueOffset; 5341 bool IsLoad = FindAliasInfo(N, Ptr, Size, SrcValue, SrcValueOffset); 5342 5343 // Starting off. 5344 Chains.push_back(OriginalChain); 5345 5346 // Look at each chain and determine if it is an alias. If so, add it to the 5347 // aliases list. If not, then continue up the chain looking for the next 5348 // candidate. 5349 while (!Chains.empty()) { 5350 SDOperand Chain = Chains.back(); 5351 Chains.pop_back(); 5352 5353 // Don't bother if we've been before. 5354 if (Visited.find(Chain.Val) != Visited.end()) continue; 5355 Visited.insert(Chain.Val); 5356 5357 switch (Chain.getOpcode()) { 5358 case ISD::EntryToken: 5359 // Entry token is ideal chain operand, but handled in FindBetterChain. 5360 break; 5361 5362 case ISD::LOAD: 5363 case ISD::STORE: { 5364 // Get alias information for Chain. 5365 SDOperand OpPtr; 5366 int64_t OpSize; 5367 const Value *OpSrcValue; 5368 int OpSrcValueOffset; 5369 bool IsOpLoad = FindAliasInfo(Chain.Val, OpPtr, OpSize, 5370 OpSrcValue, OpSrcValueOffset); 5371 5372 // If chain is alias then stop here. 5373 if (!(IsLoad && IsOpLoad) && 5374 isAlias(Ptr, Size, SrcValue, SrcValueOffset, 5375 OpPtr, OpSize, OpSrcValue, OpSrcValueOffset)) { 5376 Aliases.push_back(Chain); 5377 } else { 5378 // Look further up the chain. 5379 Chains.push_back(Chain.getOperand(0)); 5380 // Clean up old chain. 5381 AddToWorkList(Chain.Val); 5382 } 5383 break; 5384 } 5385 5386 case ISD::TokenFactor: 5387 // We have to check each of the operands of the token factor, so we queue 5388 // then up. Adding the operands to the queue (stack) in reverse order 5389 // maintains the original order and increases the likelihood that getNode 5390 // will find a matching token factor (CSE.) 5391 for (unsigned n = Chain.getNumOperands(); n;) 5392 Chains.push_back(Chain.getOperand(--n)); 5393 // Eliminate the token factor if we can. 5394 AddToWorkList(Chain.Val); 5395 break; 5396 5397 default: 5398 // For all other instructions we will just have to take what we can get. 5399 Aliases.push_back(Chain); 5400 break; 5401 } 5402 } 5403} 5404 5405/// FindBetterChain - Walk up chain skipping non-aliasing memory nodes, looking 5406/// for a better chain (aliasing node.) 5407SDOperand DAGCombiner::FindBetterChain(SDNode *N, SDOperand OldChain) { 5408 SmallVector<SDOperand, 8> Aliases; // Ops for replacing token factor. 5409 5410 // Accumulate all the aliases to this node. 5411 GatherAllAliases(N, OldChain, Aliases); 5412 5413 if (Aliases.size() == 0) { 5414 // If no operands then chain to entry token. 5415 return DAG.getEntryNode(); 5416 } else if (Aliases.size() == 1) { 5417 // If a single operand then chain to it. We don't need to revisit it. 5418 return Aliases[0]; 5419 } 5420 5421 // Construct a custom tailored token factor. 5422 SDOperand NewChain = DAG.getNode(ISD::TokenFactor, MVT::Other, 5423 &Aliases[0], Aliases.size()); 5424 5425 // Make sure the old chain gets cleaned up. 5426 if (NewChain != OldChain) AddToWorkList(OldChain.Val); 5427 5428 return NewChain; 5429} 5430 5431// SelectionDAG::Combine - This is the entry point for the file. 5432// 5433void SelectionDAG::Combine(bool RunningAfterLegalize, AliasAnalysis &AA) { 5434 if (!RunningAfterLegalize && ViewDAGCombine1) 5435 viewGraph(); 5436 if (RunningAfterLegalize && ViewDAGCombine2) 5437 viewGraph(); 5438 /// run - This is the main entry point to this class. 5439 /// 5440 DAGCombiner(*this, AA).Run(RunningAfterLegalize); 5441} 5442