1f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard//===-- AMDGPURegisterInfo.h - AMDGPURegisterInfo Interface -*- C++ -*-----===//
2f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard//
3f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard//                     The LLVM Compiler Infrastructure
4f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard//
5f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard// This file is distributed under the University of Illinois Open Source
6f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard// License. See LICENSE.TXT for details.
7f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard//
8f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard//===----------------------------------------------------------------------===//
9f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard//
10f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard/// \file
11f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard/// \brief TargetRegisterInfo interface that is implemented by all hw codegen
12f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard/// targets.
13f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard//
14f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard//===----------------------------------------------------------------------===//
15f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard
16de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar#ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUREGISTERINFO_H
17de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar#define LLVM_LIB_TARGET_AMDGPU_AMDGPUREGISTERINFO_H
18f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard
19f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard#include "llvm/Target/TargetRegisterInfo.h"
20f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard
21f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard#define GET_REGINFO_HEADER
22f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard#define GET_REGINFO_ENUM
23f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard#include "AMDGPUGenRegisterInfo.inc"
24f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard
25f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellardnamespace llvm {
26f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard
27c6a4f5e819217e1e12c458aed8e7b122e23a3a58Stephen Hinesclass AMDGPUSubtarget;
28f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellardclass TargetInstrInfo;
29f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard
30f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellardstruct AMDGPURegisterInfo : public AMDGPUGenRegisterInfo {
314c5e43da7792f75567b693105cc53e3f1992ad98Pirama Arumuga Nainar  AMDGPURegisterInfo();
32f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard
3338d5e1c36d954f1ff6489f58efd1d4865217cf9bTom Stellard  /// \returns the sub reg enum value for the given \p Channel
3438d5e1c36d954f1ff6489f58efd1d4865217cf9bTom Stellard  /// (e.g. getSubRegFromChannel(0) -> AMDGPU::sub0)
3538d5e1c36d954f1ff6489f58efd1d4865217cf9bTom Stellard  unsigned getSubRegFromChannel(unsigned Channel) const;
3638d5e1c36d954f1ff6489f58efd1d4865217cf9bTom Stellard
37dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines  const MCPhysReg* getCalleeSavedRegs(const MachineFunction *MF) const override;
38dce4a407a24b04eebc6a376f8e62b41aaa7b071fStephen Hines  unsigned getFrameRegister(const MachineFunction &MF) const override;
39f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard};
40f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard
41f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard} // End namespace llvm
42f98f2ce29e6e2996fa58f38979143eceaa818335Tom Stellard
4337ed9c199ca639565f6ce88105f9e39e898d82d0Stephen Hines#endif
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