1//===-- Thumb2InstrInfo.h - Thumb-2 Instruction Information -----*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the Thumb-2 implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_LIB_TARGET_ARM_THUMB2INSTRINFO_H
15#define LLVM_LIB_TARGET_ARM_THUMB2INSTRINFO_H
16
17#include "ARMBaseInstrInfo.h"
18#include "ThumbRegisterInfo.h"
19
20namespace llvm {
21class ARMSubtarget;
22class ScheduleHazardRecognizer;
23
24class Thumb2InstrInfo : public ARMBaseInstrInfo {
25  ThumbRegisterInfo RI;
26public:
27  explicit Thumb2InstrInfo(const ARMSubtarget &STI);
28
29  /// getNoopForMachoTarget - Return the noop instruction to use for a noop.
30  void getNoopForMachoTarget(MCInst &NopInst) const override;
31
32  // Return the non-pre/post incrementing version of 'Opc'. Return 0
33  // if there is not such an opcode.
34  unsigned getUnindexedOpcode(unsigned Opc) const override;
35
36  void ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail,
37                               MachineBasicBlock *NewDest) const override;
38
39  bool isLegalToSplitMBBAt(MachineBasicBlock &MBB,
40                           MachineBasicBlock::iterator MBBI) const override;
41
42  void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
43                   const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
44                   bool KillSrc) const override;
45
46  void storeRegToStackSlot(MachineBasicBlock &MBB,
47                           MachineBasicBlock::iterator MBBI,
48                           unsigned SrcReg, bool isKill, int FrameIndex,
49                           const TargetRegisterClass *RC,
50                           const TargetRegisterInfo *TRI) const override;
51
52  void loadRegFromStackSlot(MachineBasicBlock &MBB,
53                            MachineBasicBlock::iterator MBBI,
54                            unsigned DestReg, int FrameIndex,
55                            const TargetRegisterClass *RC,
56                            const TargetRegisterInfo *TRI) const override;
57
58  /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info.  As
59  /// such, whenever a client has an instance of instruction info, it should
60  /// always be able to get register info as well (through this method).
61  ///
62  const ThumbRegisterInfo &getRegisterInfo() const override { return RI; }
63
64private:
65  void expandLoadStackGuard(MachineBasicBlock::iterator MI) const override;
66};
67
68/// getITInstrPredicate - Valid only in Thumb2 mode. This function is identical
69/// to llvm::getInstrPredicate except it returns AL for conditional branch
70/// instructions which are "predicated", but are not in IT blocks.
71ARMCC::CondCodes getITInstrPredicate(const MachineInstr &MI, unsigned &PredReg);
72}
73
74#endif
75