1f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar//===--- HexagonExpandCondsets.cpp ----------------------------------------===// 2f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar// 3f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar// The LLVM Compiler Infrastructure 4f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar// 5f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar// This file is distributed under the University of Illinois Open Source 6f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar// License. See LICENSE.TXT for details. 7f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar// 8f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar//===----------------------------------------------------------------------===// 9f3ef5332fa3f4d5ec72c178a2b19dac363a19383Pirama Arumuga Nainar 100c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar// Replace mux instructions with the corresponding legal instructions. 110c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar// It is meant to work post-SSA, but still on virtual registers. It was 120c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar// originally placed between register coalescing and machine instruction 130c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar// scheduler. 140c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar// In this place in the optimization sequence, live interval analysis had 150c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar// been performed, and the live intervals should be preserved. A large part 160c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar// of the code deals with preserving the liveness information. 170c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar// 180c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar// Liveness tracking aside, the main functionality of this pass is divided 190c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar// into two steps. The first step is to replace an instruction 20de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar// vreg0 = C2_mux vreg1, vreg2, vreg3 210c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar// with a pair of conditional transfers 22de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar// vreg0 = A2_tfrt vreg1, vreg2 23de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar// vreg0 = A2_tfrf vreg1, vreg3 240c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar// It is the intention that the execution of this pass could be terminated 250c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar// after this step, and the code generated would be functionally correct. 260c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar// 270c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar// If the uses of the source values vreg1 and vreg2 are kills, and their 280c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar// definitions are predicable, then in the second step, the conditional 290c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar// transfers will then be rewritten as predicated instructions. E.g. 300c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar// vreg0 = A2_or vreg1, vreg2 310c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar// vreg3 = A2_tfrt vreg99, vreg0<kill> 320c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar// will be rewritten as 330c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar// vreg3 = A2_port vreg99, vreg1, vreg2 340c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar// 350c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar// This replacement has two variants: "up" and "down". Consider this case: 360c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar// vreg0 = A2_or vreg1, vreg2 370c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar// ... [intervening instructions] ... 380c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar// vreg3 = A2_tfrt vreg99, vreg0<kill> 390c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar// variant "up": 400c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar// vreg3 = A2_port vreg99, vreg1, vreg2 410c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar// ... [intervening instructions, vreg0->vreg3] ... 420c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar// [deleted] 430c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar// variant "down": 440c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar// [deleted] 450c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar// ... [intervening instructions] ... 460c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar// vreg3 = A2_port vreg99, vreg1, vreg2 470c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar// 480c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar// Both, one or none of these variants may be valid, and checks are made 490c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar// to rule out inapplicable variants. 500c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar// 510c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar// As an additional optimization, before either of the two steps above is 520c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar// executed, the pass attempts to coalesce the target register with one of 530c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar// the source registers, e.g. given an instruction 540c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar// vreg3 = C2_mux vreg0, vreg1, vreg2 550c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar// vreg3 will be coalesced with either vreg1 or vreg2. If this succeeds, 560c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar// the instruction would then be (for example) 570c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar// vreg3 = C2_mux vreg0, vreg3, vreg2 580c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar// and, under certain circumstances, this could result in only one predicated 590c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar// instruction: 600c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar// vreg3 = A2_tfrf vreg0, vreg2 610c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar// 620c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 63de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar// Splitting a definition of a register into two predicated transfers 64de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar// creates a complication in liveness tracking. Live interval computation 65de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar// will see both instructions as actual definitions, and will mark the 66de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar// first one as dead. The definition is not actually dead, and this 67de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar// situation will need to be fixed. For example: 68de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar// vreg1<def,dead> = A2_tfrt ... ; marked as dead 69de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar// vreg1<def> = A2_tfrf ... 70de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar// 71de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar// Since any of the individual predicated transfers may end up getting 72de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar// removed (in case it is an identity copy), some pre-existing def may 73de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar// be marked as dead after live interval recomputation: 74de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar// vreg1<def,dead> = ... ; marked as dead 75de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar// ... 76de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar// vreg1<def> = A2_tfrf ... ; if A2_tfrt is removed 77de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar// This case happens if vreg1 was used as a source in A2_tfrt, which means 78de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar// that is it actually live at the A2_tfrf, and so the now dead definition 79de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar// of vreg1 will need to be updated to non-dead at some point. 80de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar// 81de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar// This issue could be remedied by adding implicit uses to the predicated 82de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar// transfers, but this will create a problem with subsequent predication, 83de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar// since the transfers will no longer be possible to reorder. To avoid 84de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar// that, the initial splitting will not add any implicit uses. These 85de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar// implicit uses will be added later, after predication. The extra price, 86de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar// however, is that finding the locations where the implicit uses need 87de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar// to be added, and updating the live ranges will be more involved. 88de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar// 89de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar// An additional problem appears when subregister liveness tracking is 90de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar// enabled. In such a scenario, the live interval for the super-register 91de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar// will have live ranges for each subregister (i.e. subranges). This sub- 92de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar// range contains all liveness information about the subregister, except 93de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar// for one case: a "read-undef" flag from another subregister will not 94de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar// be reflected: given 95de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar// vreg1:subreg_hireg<def,read-undef> = ... ; "undefines" subreg_loreg 96de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar// the subrange for subreg_loreg will not have any indication that it is 97de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar// undefined at this point. Calculating subregister liveness based only 98de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar// on the information from the subrange may create a segment which spans 99de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar// over such a "read-undef" flag. This would create inconsistencies in 100de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar// the liveness data, resulting in assertions or incorrect code. 101de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar// Example: 102de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar// vreg1:subreg_loreg<def> = ... 103de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar// vreg1:subreg_hireg<def, read-undef> = ... ; "undefines" subreg_loreg 104de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar// ... 105de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar// vreg1:subreg_loreg<def> = A2_tfrt ... ; may end up with imp-use 106de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar// ; of subreg_loreg 107de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar// The remedy takes advantage of the fact, that at this point we have 108de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar// an unconditional definition of the subregister. What this means is 109de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar// that any preceding value in this subregister will be overwritten, 110de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar// or in other words, the last use before this def is a kill. This also 111de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar// implies that the first of the predicated transfers at this location 112de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar// should not have any implicit uses. 113de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar// Assume for a moment that no part of the corresponding super-register 114de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar// is used as a source. In such case, the entire super-register can be 115de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar// considered undefined immediately before this instruction. Because of 116de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar// that, we can insert an IMPLICIT_DEF of the super-register at this 117de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar// location, which will cause it to be reflected in all the associated 118de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar// subranges. What is important here is that if an IMPLICIT_DEF of 119de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar// subreg_loreg was used, we would lose the indication that subreg_hireg 120de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar// is also considered undefined. This could lead to having implicit uses 121de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar// incorrectly added. 122de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar// 123de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar// What is left is the two cases when the super-register is used as a 124de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar// source. 125de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar// * Case 1: the used part is the same as the one that is defined: 126de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar// vreg1<def> = ... 127de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar// ... 128de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar// vreg1:subreg_loreg<def,read-undef> = C2_mux ..., vreg1:subreg_loreg 129de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar// In the end, the subreg_loreg should be marked as live at the point of 130de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar// the splitting: 131de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar// vreg1:subreg_loreg<def,read-undef> = A2_tfrt ; should have imp-use 132de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar// vreg1:subreg_loreg<def,read-undef> = A2_tfrf ; should have imp-use 133de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar// Hence, an IMPLICIT_DEF of only vreg1:subreg_hireg would be sufficient. 134de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar// * Case 2: the used part does not overlap the part being defined: 135de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar// vreg1<def> = ... 136de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar// ... 137de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar// vreg1:subreg_loreg<def,read-undef> = C2_mux ..., vreg1:subreg_hireg 138de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar// For this case, we insert an IMPLICIT_DEF of vreg1:subreg_hireg after 139de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar// the C2_mux. 140de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar 1410c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar#define DEBUG_TYPE "expand-condsets" 1420c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 143de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar#include "HexagonTargetMachine.h" 144de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar#include "llvm/ADT/SetVector.h" 1450c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar#include "llvm/CodeGen/Passes.h" 1460c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar#include "llvm/CodeGen/LiveInterval.h" 1470c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar#include "llvm/CodeGen/LiveIntervalAnalysis.h" 148de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar#include "llvm/CodeGen/MachineDominators.h" 1490c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar#include "llvm/CodeGen/MachineFunction.h" 1500c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar#include "llvm/CodeGen/MachineInstrBuilder.h" 1510c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar#include "llvm/CodeGen/MachineRegisterInfo.h" 1520c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar#include "llvm/Target/TargetInstrInfo.h" 1530c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar#include "llvm/Target/TargetMachine.h" 1540c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar#include "llvm/Target/TargetRegisterInfo.h" 1550c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar#include "llvm/Support/CommandLine.h" 1560c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar#include "llvm/Support/Debug.h" 1570c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar#include "llvm/Support/raw_ostream.h" 1580c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 159de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar#include <algorithm> 160de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar#include <iterator> 161de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar#include <set> 162de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar#include <utility> 163de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar 1640c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainarusing namespace llvm; 1650c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 1660c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainarstatic cl::opt<unsigned> OptTfrLimit("expand-condsets-tfr-limit", 1670c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar cl::init(~0U), cl::Hidden, cl::desc("Max number of mux expansions")); 1680c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainarstatic cl::opt<unsigned> OptCoaLimit("expand-condsets-coa-limit", 1690c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar cl::init(~0U), cl::Hidden, cl::desc("Max number of segment coalescings")); 1700c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 1710c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainarnamespace llvm { 1720c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar void initializeHexagonExpandCondsetsPass(PassRegistry&); 1730c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar FunctionPass *createHexagonExpandCondsets(); 1740c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar} 1750c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 1760c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainarnamespace { 1770c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar class HexagonExpandCondsets : public MachineFunctionPass { 1780c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar public: 1790c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar static char ID; 1800c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar HexagonExpandCondsets() : 1810c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar MachineFunctionPass(ID), HII(0), TRI(0), MRI(0), 1820c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar LIS(0), CoaLimitActive(false), 1830c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar TfrLimitActive(false), CoaCounter(0), TfrCounter(0) { 1840c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (OptCoaLimit.getPosition()) 1850c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar CoaLimitActive = true, CoaLimit = OptCoaLimit; 1860c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (OptTfrLimit.getPosition()) 1870c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar TfrLimitActive = true, TfrLimit = OptTfrLimit; 1880c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar initializeHexagonExpandCondsetsPass(*PassRegistry::getPassRegistry()); 1890c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar } 1900c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 191de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar const char *getPassName() const override { 1920c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar return "Hexagon Expand Condsets"; 1930c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar } 194de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar void getAnalysisUsage(AnalysisUsage &AU) const override { 1950c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar AU.addRequired<LiveIntervals>(); 1960c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar AU.addPreserved<LiveIntervals>(); 1970c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar AU.addPreserved<SlotIndexes>(); 198de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar AU.addRequired<MachineDominatorTree>(); 199de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar AU.addPreserved<MachineDominatorTree>(); 2000c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar MachineFunctionPass::getAnalysisUsage(AU); 2010c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar } 202de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar bool runOnMachineFunction(MachineFunction &MF) override; 2030c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 2040c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar private: 2050c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar const HexagonInstrInfo *HII; 2060c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar const TargetRegisterInfo *TRI; 207de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar MachineDominatorTree *MDT; 2080c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar MachineRegisterInfo *MRI; 2090c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar LiveIntervals *LIS; 210de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar std::set<MachineInstr*> LocalImpDefs; 2110c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 2120c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar bool CoaLimitActive, TfrLimitActive; 2130c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar unsigned CoaLimit, TfrLimit, CoaCounter, TfrCounter; 2140c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 2150c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar struct RegisterRef { 2160c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar RegisterRef(const MachineOperand &Op) : Reg(Op.getReg()), 2170c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar Sub(Op.getSubReg()) {} 2180c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar RegisterRef(unsigned R = 0, unsigned S = 0) : Reg(R), Sub(S) {} 2190c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar bool operator== (RegisterRef RR) const { 2200c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar return Reg == RR.Reg && Sub == RR.Sub; 2210c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar } 2220c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar bool operator!= (RegisterRef RR) const { return !operator==(RR); } 223de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar bool operator< (RegisterRef RR) const { 224de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar return Reg < RR.Reg || (Reg == RR.Reg && Sub < RR.Sub); 225de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar } 2260c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar unsigned Reg, Sub; 2270c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar }; 2280c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 2290c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar typedef DenseMap<unsigned,unsigned> ReferenceMap; 2300c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar enum { Sub_Low = 0x1, Sub_High = 0x2, Sub_None = (Sub_Low | Sub_High) }; 2310c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar enum { Exec_Then = 0x10, Exec_Else = 0x20 }; 2320c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar unsigned getMaskForSub(unsigned Sub); 233de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar bool isCondset(const MachineInstr &MI); 234de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar LaneBitmask getLaneMask(unsigned Reg, unsigned Sub); 2350c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 2360c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar void addRefToMap(RegisterRef RR, ReferenceMap &Map, unsigned Exec); 2370c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar bool isRefInMap(RegisterRef, ReferenceMap &Map, unsigned Exec); 2380c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 239de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar void removeImpDefSegments(LiveRange &Range); 240de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar void updateDeadsInRange(unsigned Reg, LaneBitmask LM, LiveRange &Range); 241de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar void updateKillFlags(unsigned Reg); 242de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar void updateDeadFlags(unsigned Reg); 243de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar void recalculateLiveInterval(unsigned Reg); 244de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar void removeInstr(MachineInstr &MI); 245de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar void updateLiveness(std::set<unsigned> &RegSet, bool Recalc, 246de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar bool UpdateKills, bool UpdateDeads); 2470c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 2480c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar unsigned getCondTfrOpcode(const MachineOperand &SO, bool Cond); 249de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar MachineInstr *genCondTfrFor(MachineOperand &SrcOp, 250de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar MachineBasicBlock::iterator At, unsigned DstR, 251de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar unsigned DstSR, const MachineOperand &PredOp, bool PredSense, 252de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar bool ReadUndef, bool ImpUse); 253de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar bool split(MachineInstr &MI, std::set<unsigned> &UpdRegs); 254de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar bool splitInBlock(MachineBasicBlock &B, std::set<unsigned> &UpdRegs); 2550c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 2560c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar bool isPredicable(MachineInstr *MI); 2570c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar MachineInstr *getReachingDefForPred(RegisterRef RD, 2580c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar MachineBasicBlock::iterator UseIt, unsigned PredR, bool Cond); 259de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar bool canMoveOver(MachineInstr &MI, ReferenceMap &Defs, ReferenceMap &Uses); 260de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar bool canMoveMemTo(MachineInstr &MI, MachineInstr &ToI, bool IsDown); 261de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar void predicateAt(const MachineOperand &DefOp, MachineInstr &MI, 262de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar MachineBasicBlock::iterator Where, 263de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar const MachineOperand &PredOp, bool Cond, 264de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar std::set<unsigned> &UpdRegs); 2650c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar void renameInRange(RegisterRef RO, RegisterRef RN, unsigned PredR, 2660c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar bool Cond, MachineBasicBlock::iterator First, 2670c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar MachineBasicBlock::iterator Last); 268de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar bool predicate(MachineInstr &TfrI, bool Cond, std::set<unsigned> &UpdRegs); 269de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar bool predicateInBlock(MachineBasicBlock &B, 270de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar std::set<unsigned> &UpdRegs); 2710c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 2720c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar bool isIntReg(RegisterRef RR, unsigned &BW); 2730c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar bool isIntraBlocks(LiveInterval &LI); 2740c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar bool coalesceRegisters(RegisterRef R1, RegisterRef R2); 2750c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar bool coalesceSegments(MachineFunction &MF); 2760c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar }; 2770c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar} 2780c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 2790c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainarchar HexagonExpandCondsets::ID = 0; 2800c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 281de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga NainarINITIALIZE_PASS_BEGIN(HexagonExpandCondsets, "expand-condsets", 282de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar "Hexagon Expand Condsets", false, false) 283de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga NainarINITIALIZE_PASS_DEPENDENCY(MachineDominatorTree) 284de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga NainarINITIALIZE_PASS_DEPENDENCY(SlotIndexes) 285de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga NainarINITIALIZE_PASS_DEPENDENCY(LiveIntervals) 286de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga NainarINITIALIZE_PASS_END(HexagonExpandCondsets, "expand-condsets", 287de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar "Hexagon Expand Condsets", false, false) 2880c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 2890c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainarunsigned HexagonExpandCondsets::getMaskForSub(unsigned Sub) { 2900c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar switch (Sub) { 2910c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar case Hexagon::subreg_loreg: 2920c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar return Sub_Low; 2930c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar case Hexagon::subreg_hireg: 2940c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar return Sub_High; 2950c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar case Hexagon::NoSubRegister: 2960c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar return Sub_None; 2970c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar } 2980c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar llvm_unreachable("Invalid subregister"); 2990c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar} 3000c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 301de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainarbool HexagonExpandCondsets::isCondset(const MachineInstr &MI) { 302de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar unsigned Opc = MI.getOpcode(); 3030c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar switch (Opc) { 3040c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar case Hexagon::C2_mux: 3050c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar case Hexagon::C2_muxii: 3060c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar case Hexagon::C2_muxir: 3070c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar case Hexagon::C2_muxri: 3080c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar case Hexagon::MUX64_rr: 3090c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar return true; 3100c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar break; 3110c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar } 3120c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar return false; 3130c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar} 3140c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 3150c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 316de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga NainarLaneBitmask HexagonExpandCondsets::getLaneMask(unsigned Reg, unsigned Sub) { 317de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar assert(TargetRegisterInfo::isVirtualRegister(Reg)); 318de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar return Sub != 0 ? TRI->getSubRegIndexLaneMask(Sub) 319de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar : MRI->getMaxLaneMaskForVReg(Reg); 320de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar} 321de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar 322de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar 3230c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainarvoid HexagonExpandCondsets::addRefToMap(RegisterRef RR, ReferenceMap &Map, 3240c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar unsigned Exec) { 3250c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar unsigned Mask = getMaskForSub(RR.Sub) | Exec; 3260c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar ReferenceMap::iterator F = Map.find(RR.Reg); 3270c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (F == Map.end()) 3280c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar Map.insert(std::make_pair(RR.Reg, Mask)); 3290c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar else 3300c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar F->second |= Mask; 3310c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar} 3320c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 3330c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 3340c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainarbool HexagonExpandCondsets::isRefInMap(RegisterRef RR, ReferenceMap &Map, 3350c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar unsigned Exec) { 3360c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar ReferenceMap::iterator F = Map.find(RR.Reg); 3370c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (F == Map.end()) 3380c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar return false; 3390c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar unsigned Mask = getMaskForSub(RR.Sub) | Exec; 3400c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (Mask & F->second) 3410c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar return true; 3420c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar return false; 3430c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar} 3440c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 3450c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 346de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainarvoid HexagonExpandCondsets::updateKillFlags(unsigned Reg) { 347de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar auto KillAt = [this,Reg] (SlotIndex K, LaneBitmask LM) -> void { 348de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // Set the <kill> flag on a use of Reg whose lane mask is contained in LM. 349de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar MachineInstr *MI = LIS->getInstructionFromIndex(K); 3500c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar for (auto &Op : MI->operands()) { 351de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar if (!Op.isReg() || !Op.isUse() || Op.getReg() != Reg) 3520c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar continue; 353de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar LaneBitmask SLM = getLaneMask(Reg, Op.getSubReg()); 354de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar if ((SLM & LM) == SLM) { 355de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // Only set the kill flag on the first encountered use of Reg in this 356de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // instruction. 357de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar Op.setIsKill(true); 358de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar break; 359de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar } 3600c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar } 361de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar }; 3620c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 363de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar LiveInterval &LI = LIS->getInterval(Reg); 364de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar for (auto I = LI.begin(), E = LI.end(); I != E; ++I) { 365de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar if (!I->end.isRegister()) 3660c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar continue; 367de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // Do not mark the end of the segment as <kill>, if the next segment 368de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // starts with a predicated instruction. 369de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar auto NextI = std::next(I); 370de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar if (NextI != E && NextI->start.isRegister()) { 371de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar MachineInstr *DefI = LIS->getInstructionFromIndex(NextI->start); 372de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar if (HII->isPredicated(*DefI)) 3730c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar continue; 3740c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar } 375de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar bool WholeReg = true; 376de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar if (LI.hasSubRanges()) { 377de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar auto EndsAtI = [I] (LiveInterval::SubRange &S) -> bool { 378de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar LiveRange::iterator F = S.find(I->end); 379de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar return F != S.end() && I->end == F->end; 380de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar }; 381de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // Check if all subranges end at I->end. If so, make sure to kill 382de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // the whole register. 383de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar for (LiveInterval::SubRange &S : LI.subranges()) { 384de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar if (EndsAtI(S)) 385de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar KillAt(I->end, S.LaneMask); 386de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar else 387de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar WholeReg = false; 388de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar } 389de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar } 390de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar if (WholeReg) 391de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar KillAt(I->end, MRI->getMaxLaneMaskForVReg(Reg)); 3920c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar } 3930c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar} 3940c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 3950c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 396de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainarvoid HexagonExpandCondsets::removeImpDefSegments(LiveRange &Range) { 397de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar auto StartImpDef = [this] (LiveRange::Segment &S) -> bool { 398de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar return S.start.isRegister() && 399de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar LocalImpDefs.count(LIS->getInstructionFromIndex(S.start)); 400de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar }; 401de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar Range.segments.erase(std::remove_if(Range.begin(), Range.end(), StartImpDef), 402de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar Range.end()); 403de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar} 4040c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 405de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainarvoid HexagonExpandCondsets::updateDeadsInRange(unsigned Reg, LaneBitmask LM, 406de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar LiveRange &Range) { 407de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar assert(TargetRegisterInfo::isVirtualRegister(Reg)); 408de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar if (Range.empty()) 4090c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar return; 4100c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 411de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar auto IsRegDef = [this,Reg,LM] (MachineOperand &Op) -> bool { 412de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar if (!Op.isReg() || !Op.isDef()) 413de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar return false; 414de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar unsigned DR = Op.getReg(), DSR = Op.getSubReg(); 415de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar if (!TargetRegisterInfo::isVirtualRegister(DR) || DR != Reg) 416de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar return false; 417de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar LaneBitmask SLM = getLaneMask(DR, DSR); 418de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar return (SLM & LM) != 0; 419de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar }; 4200c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 421de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // The splitting step will create pairs of predicated definitions without 422de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // any implicit uses (since implicit uses would interfere with predication). 423de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // This can cause the reaching defs to become dead after live range 424de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // recomputation, even though they are not really dead. 425de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // We need to identify predicated defs that need implicit uses, and 426de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // dead defs that are not really dead, and correct both problems. 427de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar 428de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar SetVector<MachineBasicBlock*> Defs; 429de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar auto Dominate = [this] (SetVector<MachineBasicBlock*> &Defs, 430de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar MachineBasicBlock *Dest) -> bool { 431de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar for (MachineBasicBlock *D : Defs) 432de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar if (D != Dest && MDT->dominates(D, Dest)) 433de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar return true; 4340c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 435de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar MachineBasicBlock *Entry = &Dest->getParent()->front(); 436de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar SetVector<MachineBasicBlock*> Work(Dest->pred_begin(), Dest->pred_end()); 437de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar for (unsigned i = 0; i < Work.size(); ++i) { 438de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar MachineBasicBlock *B = Work[i]; 439de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar if (Defs.count(B)) 440de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar continue; 441de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar if (B == Entry) 442de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar return false; 443de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar for (auto *P : B->predecessors()) 444de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar Work.insert(P); 4450c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar } 446de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar return true; 447de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar }; 4480c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 449de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // First, try to extend live range within individual basic blocks. This 450de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // will leave us only with dead defs that do not reach any predicated 451de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // defs in the same block. 452de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar SmallVector<SlotIndex,4> PredDefs; 453de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar for (auto &Seg : Range) { 454de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar if (!Seg.start.isRegister()) 455de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar continue; 456de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar MachineInstr *DefI = LIS->getInstructionFromIndex(Seg.start); 457de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar if (LocalImpDefs.count(DefI)) 458de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar continue; 459de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar Defs.insert(DefI->getParent()); 460de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar if (HII->isPredicated(*DefI)) 461de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar PredDefs.push_back(Seg.start); 462de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar } 463de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar for (auto &SI : PredDefs) { 464de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar MachineBasicBlock *BB = LIS->getMBBFromIndex(SI); 465de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar if (Range.extendInBlock(LIS->getMBBStartIdx(BB), SI)) 466de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar SI = SlotIndex(); 4670c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar } 4680c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 469de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // Calculate reachability for those predicated defs that were not handled 470de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // by the in-block extension. 471de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar SmallVector<SlotIndex,4> ExtTo; 472de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar for (auto &SI : PredDefs) { 473de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar if (!SI.isValid()) 474de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar continue; 475de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar MachineBasicBlock *BB = LIS->getMBBFromIndex(SI); 476de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar if (BB->pred_empty()) 477de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar continue; 478de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // If the defs from this range reach SI via all predecessors, it is live. 479de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar if (Dominate(Defs, BB)) 480de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar ExtTo.push_back(SI); 481de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar } 482de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar LIS->extendToIndices(Range, ExtTo); 483de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar 484de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // Remove <dead> flags from all defs that are not dead after live range 485de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // extension, and collect all def operands. They will be used to generate 486de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // the necessary implicit uses. 487de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar std::set<RegisterRef> DefRegs; 488de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar for (auto &Seg : Range) { 489de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar if (!Seg.start.isRegister()) 4900c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar continue; 491de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar MachineInstr *DefI = LIS->getInstructionFromIndex(Seg.start); 492de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar if (LocalImpDefs.count(DefI)) 4930c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar continue; 494de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar for (auto &Op : DefI->operands()) { 495de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar if (Seg.start.isDead() || !IsRegDef(Op)) 496de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar continue; 497de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar DefRegs.insert(Op); 498de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar Op.setIsDead(false); 4990c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar } 5000c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar } 5010c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 5020c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 503de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // Finally, add implicit uses to each predicated def that is reached 504de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // by other defs. Remove segments started by implicit-defs first, since 505de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // they do not define registers. 506de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar removeImpDefSegments(Range); 5070c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 508de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar for (auto &Seg : Range) { 509de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar if (!Seg.start.isRegister() || !Range.liveAt(Seg.start.getPrevSlot())) 5100c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar continue; 511de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar MachineInstr *DefI = LIS->getInstructionFromIndex(Seg.start); 512de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar if (!HII->isPredicated(*DefI)) 5130c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar continue; 514de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar MachineFunction &MF = *DefI->getParent()->getParent(); 515de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // Construct the set of all necessary implicit uses, based on the def 516de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // operands in the instruction. 517de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar std::set<RegisterRef> ImpUses; 518de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar for (auto &Op : DefI->operands()) 519de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar if (Op.isReg() && Op.isDef() && DefRegs.count(Op)) 520de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar ImpUses.insert(Op); 521de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar for (RegisterRef R : ImpUses) 522de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar MachineInstrBuilder(MF, DefI).addReg(R.Reg, RegState::Implicit, R.Sub); 523de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar } 524de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar} 5250c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 5260c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 527de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainarvoid HexagonExpandCondsets::updateDeadFlags(unsigned Reg) { 528de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar LiveInterval &LI = LIS->getInterval(Reg); 529de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar if (LI.hasSubRanges()) { 530de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar for (LiveInterval::SubRange &S : LI.subranges()) { 531de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar updateDeadsInRange(Reg, S.LaneMask, S); 532de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar LIS->shrinkToUses(S, Reg); 533de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // LI::shrinkToUses will add segments started by implicit-defs. 534de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // Remove them again. 535de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar removeImpDefSegments(S); 5360c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar } 537de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar LI.clear(); 538de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar LIS->constructMainRangeFromSubranges(LI); 539de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar } else { 540de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar updateDeadsInRange(Reg, MRI->getMaxLaneMaskForVReg(Reg), LI); 5410c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar } 542de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar} 5430c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 544de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar 545de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainarvoid HexagonExpandCondsets::recalculateLiveInterval(unsigned Reg) { 546de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar LIS->removeInterval(Reg); 547de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar LIS->createAndComputeVirtRegInterval(Reg); 548de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar} 549de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar 550de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainarvoid HexagonExpandCondsets::removeInstr(MachineInstr &MI) { 5510c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar LIS->RemoveMachineInstrFromMaps(MI); 552de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar MI.eraseFromParent(); 553de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar} 554de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar 555de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar 556de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainarvoid HexagonExpandCondsets::updateLiveness(std::set<unsigned> &RegSet, 557de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar bool Recalc, bool UpdateKills, bool UpdateDeads) { 558de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar UpdateKills |= UpdateDeads; 559de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar for (auto R : RegSet) { 560de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar if (Recalc) 561de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar recalculateLiveInterval(R); 562de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar if (UpdateKills) 563de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar MRI->clearKillFlags(R); 564de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar if (UpdateDeads) 565de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar updateDeadFlags(R); 566de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // Fixing <dead> flags may extend live ranges, so reset <kill> flags 567de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // after that. 568de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar if (UpdateKills) 569de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar updateKillFlags(R); 570de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar LIS->getInterval(R).verify(); 5710c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar } 5720c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar} 5730c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 5740c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 5750c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar/// Get the opcode for a conditional transfer of the value in SO (source 5760c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar/// operand). The condition (true/false) is given in Cond. 5770c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainarunsigned HexagonExpandCondsets::getCondTfrOpcode(const MachineOperand &SO, 578de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar bool IfTrue) { 5790c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar using namespace Hexagon; 5800c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (SO.isReg()) { 5810c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar unsigned PhysR; 5820c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar RegisterRef RS = SO; 5830c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (TargetRegisterInfo::isVirtualRegister(RS.Reg)) { 5840c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar const TargetRegisterClass *VC = MRI->getRegClass(RS.Reg); 5850c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar assert(VC->begin() != VC->end() && "Empty register class"); 5860c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar PhysR = *VC->begin(); 5870c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar } else { 5880c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar assert(TargetRegisterInfo::isPhysicalRegister(RS.Reg)); 5890c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar PhysR = RS.Reg; 5900c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar } 5910c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar unsigned PhysS = (RS.Sub == 0) ? PhysR : TRI->getSubReg(PhysR, RS.Sub); 5920c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(PhysS); 5930c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar switch (RC->getSize()) { 5940c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar case 4: 595de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar return IfTrue ? A2_tfrt : A2_tfrf; 5960c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar case 8: 597de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar return IfTrue ? A2_tfrpt : A2_tfrpf; 5980c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar } 5990c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar llvm_unreachable("Invalid register operand"); 6000c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar } 6010c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (SO.isImm() || SO.isFPImm()) 602de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar return IfTrue ? C2_cmoveit : C2_cmoveif; 6030c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar llvm_unreachable("Unexpected source operand"); 6040c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar} 6050c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 6060c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 6070c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar/// Generate a conditional transfer, copying the value SrcOp to the 6080c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar/// destination register DstR:DstSR, and using the predicate register from 6090c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar/// PredOp. The Cond argument specifies whether the predicate is to be 6100c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar/// if(PredOp), or if(!PredOp). 611de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga NainarMachineInstr *HexagonExpandCondsets::genCondTfrFor(MachineOperand &SrcOp, 612de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar MachineBasicBlock::iterator At, 613de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar unsigned DstR, unsigned DstSR, const MachineOperand &PredOp, 614de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar bool PredSense, bool ReadUndef, bool ImpUse) { 6150c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar MachineInstr *MI = SrcOp.getParent(); 616de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar MachineBasicBlock &B = *At->getParent(); 617de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar const DebugLoc &DL = MI->getDebugLoc(); 6180c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 6190c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // Don't avoid identity copies here (i.e. if the source and the destination 6200c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // are the same registers). It is actually better to generate them here, 6210c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // since this would cause the copy to potentially be predicated in the next 6220c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // step. The predication will remove such a copy if it is unable to 6230c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar /// predicate. 6240c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 625de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar unsigned Opc = getCondTfrOpcode(SrcOp, PredSense); 626de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar unsigned State = RegState::Define | (ReadUndef ? RegState::Undef : 0); 627de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar MachineInstrBuilder MIB = BuildMI(B, At, DL, HII->get(Opc)) 628de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar .addReg(DstR, State, DstSR) 6290c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar .addOperand(PredOp) 6300c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar .addOperand(SrcOp); 631de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar 6320c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // We don't want any kills yet. 633de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar MIB->clearKillInfo(); 634de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar DEBUG(dbgs() << "created an initial copy: " << *MIB); 635de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar return &*MIB; 6360c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar} 6370c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 6380c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 6390c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar/// Replace a MUX instruction MI with a pair A2_tfrt/A2_tfrf. This function 6400c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar/// performs all necessary changes to complete the replacement. 641de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainarbool HexagonExpandCondsets::split(MachineInstr &MI, 642de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar std::set<unsigned> &UpdRegs) { 6430c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (TfrLimitActive) { 6440c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (TfrCounter >= TfrLimit) 6450c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar return false; 6460c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar TfrCounter++; 6470c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar } 648de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar DEBUG(dbgs() << "\nsplitting BB#" << MI.getParent()->getNumber() << ": " 649de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar << MI); 650de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar MachineOperand &MD = MI.getOperand(0); // Definition 651de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar MachineOperand &MP = MI.getOperand(1); // Predicate register 652de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar MachineOperand &MS1 = MI.getOperand(2); // Source value #1 653de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar MachineOperand &MS2 = MI.getOperand(3); // Source value #2 6540c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar assert(MD.isDef()); 6550c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar unsigned DR = MD.getReg(), DSR = MD.getSubReg(); 656de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar bool ReadUndef = MD.isUndef(); 657de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar MachineBasicBlock::iterator At = MI; 658de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar 659de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar if (ReadUndef && DSR != 0 && MRI->shouldTrackSubRegLiveness(DR)) { 660de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar unsigned NewSR = 0; 661de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar MachineBasicBlock::iterator DefAt = At; 662de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar bool SameReg = (MS1.isReg() && DR == MS1.getReg()) || 663de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar (MS2.isReg() && DR == MS2.getReg()); 664de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar if (SameReg) { 665de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar NewSR = (DSR == Hexagon::subreg_loreg) ? Hexagon::subreg_hireg 666de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar : Hexagon::subreg_loreg; 667de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // Advance the insertion point if the subregisters differ between 668de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // the source and the target (with the same super-register). 669de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // Note: this case has never occured during tests. 670de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar if ((MS1.isReg() && NewSR == MS1.getSubReg()) || 671de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar (MS2.isReg() && NewSR == MS2.getSubReg())) 672de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar ++DefAt; 673de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar } 674de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // Use "At", since "DefAt" may be end(). 675de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar MachineBasicBlock &B = *At->getParent(); 676de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar DebugLoc DL = At->getDebugLoc(); 677de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar auto ImpD = BuildMI(B, DefAt, DL, HII->get(TargetOpcode::IMPLICIT_DEF)) 678de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar .addReg(DR, RegState::Define, NewSR); 679de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar LIS->InsertMachineInstrInMaps(*ImpD); 680de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar LocalImpDefs.insert(&*ImpD); 681de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar } 6820c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 6830c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // First, create the two invididual conditional transfers, and add each 6840c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // of them to the live intervals information. Do that first and then remove 6850c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // the old instruction from live intervals. 686de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar MachineInstr *TfrT = 687de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar genCondTfrFor(MI.getOperand(2), At, DR, DSR, MP, true, ReadUndef, false); 688de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar MachineInstr *TfrF = 689de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar genCondTfrFor(MI.getOperand(3), At, DR, DSR, MP, false, ReadUndef, true); 690de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar LIS->InsertMachineInstrInMaps(*TfrT); 691de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar LIS->InsertMachineInstrInMaps(*TfrF); 692de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar 693de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // Will need to recalculate live intervals for all registers in MI. 694de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar for (auto &Op : MI.operands()) 695de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar if (Op.isReg()) 696de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar UpdRegs.insert(Op.getReg()); 697de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar 698de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar removeInstr(MI); 6990c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar return true; 7000c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar} 7010c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 7020c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 703de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar/// Split all MUX instructions in the given block into pairs of conditional 7040c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar/// transfers. 705de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainarbool HexagonExpandCondsets::splitInBlock(MachineBasicBlock &B, 706de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar std::set<unsigned> &UpdRegs) { 7070c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar bool Changed = false; 7080c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar MachineBasicBlock::iterator I, E, NextI; 7090c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar for (I = B.begin(), E = B.end(); I != E; I = NextI) { 7100c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar NextI = std::next(I); 711de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar if (isCondset(*I)) 712de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar Changed |= split(*I, UpdRegs); 7130c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar } 7140c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar return Changed; 7150c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar} 7160c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 7170c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 7180c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainarbool HexagonExpandCondsets::isPredicable(MachineInstr *MI) { 719de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar if (HII->isPredicated(*MI) || !HII->isPredicable(*MI)) 7200c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar return false; 7210c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (MI->hasUnmodeledSideEffects() || MI->mayStore()) 7220c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar return false; 7230c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // Reject instructions with multiple defs (e.g. post-increment loads). 7240c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar bool HasDef = false; 7250c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar for (auto &Op : MI->operands()) { 7260c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (!Op.isReg() || !Op.isDef()) 7270c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar continue; 7280c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (HasDef) 7290c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar return false; 7300c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar HasDef = true; 7310c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar } 7320c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar for (auto &Mo : MI->memoperands()) 7330c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (Mo->isVolatile()) 7340c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar return false; 7350c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar return true; 7360c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar} 7370c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 7380c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 7390c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar/// Find the reaching definition for a predicated use of RD. The RD is used 7400c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar/// under the conditions given by PredR and Cond, and this function will ignore 7410c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar/// definitions that set RD under the opposite conditions. 7420c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga NainarMachineInstr *HexagonExpandCondsets::getReachingDefForPred(RegisterRef RD, 7430c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar MachineBasicBlock::iterator UseIt, unsigned PredR, bool Cond) { 7440c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar MachineBasicBlock &B = *UseIt->getParent(); 7450c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar MachineBasicBlock::iterator I = UseIt, S = B.begin(); 7460c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (I == S) 7470c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar return 0; 7480c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 7490c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar bool PredValid = true; 7500c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar do { 7510c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar --I; 7520c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar MachineInstr *MI = &*I; 7530c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // Check if this instruction can be ignored, i.e. if it is predicated 7540c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // on the complementary condition. 755de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar if (PredValid && HII->isPredicated(*MI)) { 756de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar if (MI->readsRegister(PredR) && (Cond != HII->isPredicatedTrue(*MI))) 7570c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar continue; 7580c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar } 7590c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 7600c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // Check the defs. If the PredR is defined, invalidate it. If RD is 7610c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // defined, return the instruction or 0, depending on the circumstances. 7620c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar for (auto &Op : MI->operands()) { 7630c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (!Op.isReg() || !Op.isDef()) 7640c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar continue; 7650c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar RegisterRef RR = Op; 7660c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (RR.Reg == PredR) { 7670c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar PredValid = false; 7680c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar continue; 7690c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar } 7700c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (RR.Reg != RD.Reg) 7710c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar continue; 7720c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // If the "Reg" part agrees, there is still the subregister to check. 7730c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // If we are looking for vreg1:loreg, we can skip vreg1:hireg, but 7740c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // not vreg1 (w/o subregisters). 7750c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (RR.Sub == RD.Sub) 7760c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar return MI; 7770c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (RR.Sub == 0 || RD.Sub == 0) 7780c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar return 0; 7790c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // We have different subregisters, so we can continue looking. 7800c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar } 7810c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar } while (I != S); 7820c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 7830c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar return 0; 7840c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar} 7850c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 7860c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 7870c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar/// Check if the instruction MI can be safely moved over a set of instructions 7880c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar/// whose side-effects (in terms of register defs and uses) are expressed in 7890c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar/// the maps Defs and Uses. These maps reflect the conditional defs and uses 7900c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar/// that depend on the same predicate register to allow moving instructions 7910c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar/// over instructions predicated on the opposite condition. 792de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainarbool HexagonExpandCondsets::canMoveOver(MachineInstr &MI, ReferenceMap &Defs, 793de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar ReferenceMap &Uses) { 7940c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // In order to be able to safely move MI over instructions that define 7950c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // "Defs" and use "Uses", no def operand from MI can be defined or used 7960c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // and no use operand can be defined. 797de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar for (auto &Op : MI.operands()) { 7980c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (!Op.isReg()) 7990c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar continue; 8000c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar RegisterRef RR = Op; 8010c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // For physical register we would need to check register aliases, etc. 8020c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // and we don't want to bother with that. It would be of little value 8030c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // before the actual register rewriting (from virtual to physical). 8040c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (!TargetRegisterInfo::isVirtualRegister(RR.Reg)) 8050c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar return false; 8060c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // No redefs for any operand. 8070c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (isRefInMap(RR, Defs, Exec_Then)) 8080c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar return false; 8090c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // For defs, there cannot be uses. 8100c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (Op.isDef() && isRefInMap(RR, Uses, Exec_Then)) 8110c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar return false; 8120c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar } 8130c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar return true; 8140c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar} 8150c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 8160c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 8170c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar/// Check if the instruction accessing memory (TheI) can be moved to the 8180c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar/// location ToI. 819de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainarbool HexagonExpandCondsets::canMoveMemTo(MachineInstr &TheI, MachineInstr &ToI, 820de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar bool IsDown) { 821de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar bool IsLoad = TheI.mayLoad(), IsStore = TheI.mayStore(); 8220c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (!IsLoad && !IsStore) 8230c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar return true; 8240c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (HII->areMemAccessesTriviallyDisjoint(TheI, ToI)) 8250c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar return true; 826de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar if (TheI.hasUnmodeledSideEffects()) 8270c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar return false; 8280c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 8290c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar MachineBasicBlock::iterator StartI = IsDown ? TheI : ToI; 8300c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar MachineBasicBlock::iterator EndI = IsDown ? ToI : TheI; 831de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar bool Ordered = TheI.hasOrderedMemoryRef(); 8320c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 8330c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // Search for aliased memory reference in (StartI, EndI). 8340c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar for (MachineBasicBlock::iterator I = std::next(StartI); I != EndI; ++I) { 8350c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar MachineInstr *MI = &*I; 8360c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (MI->hasUnmodeledSideEffects()) 8370c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar return false; 8380c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar bool L = MI->mayLoad(), S = MI->mayStore(); 8390c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (!L && !S) 8400c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar continue; 8410c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (Ordered && MI->hasOrderedMemoryRef()) 8420c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar return false; 8430c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 8440c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar bool Conflict = (L && IsStore) || S; 8450c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (Conflict) 8460c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar return false; 8470c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar } 8480c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar return true; 8490c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar} 8500c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 8510c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 8520c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar/// Generate a predicated version of MI (where the condition is given via 8530c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar/// PredR and Cond) at the point indicated by Where. 854de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainarvoid HexagonExpandCondsets::predicateAt(const MachineOperand &DefOp, 855de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar MachineInstr &MI, 856de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar MachineBasicBlock::iterator Where, 857de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar const MachineOperand &PredOp, bool Cond, 858de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar std::set<unsigned> &UpdRegs) { 8590c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // The problem with updating live intervals is that we can move one def 8600c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // past another def. In particular, this can happen when moving an A2_tfrt 8610c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // over an A2_tfrf defining the same register. From the point of view of 8620c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // live intervals, these two instructions are two separate definitions, 8630c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // and each one starts another live segment. LiveIntervals's "handleMove" 8640c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // does not allow such moves, so we need to handle it ourselves. To avoid 8650c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // invalidating liveness data while we are using it, the move will be 8660c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // implemented in 4 steps: (1) add a clone of the instruction MI at the 8670c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // target location, (2) update liveness, (3) delete the old instruction, 8680c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // and (4) update liveness again. 8690c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 870de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar MachineBasicBlock &B = *MI.getParent(); 8710c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar DebugLoc DL = Where->getDebugLoc(); // "Where" points to an instruction. 872de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar unsigned Opc = MI.getOpcode(); 8730c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar unsigned PredOpc = HII->getCondOpcode(Opc, !Cond); 8740c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar MachineInstrBuilder MB = BuildMI(B, Where, DL, HII->get(PredOpc)); 875de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar unsigned Ox = 0, NP = MI.getNumOperands(); 8760c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // Skip all defs from MI first. 8770c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar while (Ox < NP) { 878de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar MachineOperand &MO = MI.getOperand(Ox); 8790c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (!MO.isReg() || !MO.isDef()) 8800c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar break; 8810c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar Ox++; 8820c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar } 8830c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // Add the new def, then the predicate register, then the rest of the 8840c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // operands. 885de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar MB.addReg(DefOp.getReg(), getRegState(DefOp), DefOp.getSubReg()); 886de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar MB.addReg(PredOp.getReg(), PredOp.isUndef() ? RegState::Undef : 0, 887de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar PredOp.getSubReg()); 8880c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar while (Ox < NP) { 889de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar MachineOperand &MO = MI.getOperand(Ox); 8900c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (!MO.isReg() || !MO.isImplicit()) 8910c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar MB.addOperand(MO); 8920c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar Ox++; 8930c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar } 8940c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 8950c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar MachineFunction &MF = *B.getParent(); 896de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar MachineInstr::mmo_iterator I = MI.memoperands_begin(); 897de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar unsigned NR = std::distance(I, MI.memoperands_end()); 8980c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar MachineInstr::mmo_iterator MemRefs = MF.allocateMemRefsArray(NR); 8990c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar for (unsigned i = 0; i < NR; ++i) 9000c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar MemRefs[i] = *I++; 9010c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar MB.setMemRefs(MemRefs, MemRefs+NR); 9020c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 9030c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar MachineInstr *NewI = MB; 9040c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar NewI->clearKillInfo(); 905de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar LIS->InsertMachineInstrInMaps(*NewI); 906de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar 907de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar for (auto &Op : NewI->operands()) 908de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar if (Op.isReg()) 909de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar UpdRegs.insert(Op.getReg()); 9100c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar} 9110c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 9120c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 9130c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar/// In the range [First, Last], rename all references to the "old" register RO 9140c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar/// to the "new" register RN, but only in instructions predicated on the given 9150c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar/// condition. 9160c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainarvoid HexagonExpandCondsets::renameInRange(RegisterRef RO, RegisterRef RN, 9170c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar unsigned PredR, bool Cond, MachineBasicBlock::iterator First, 9180c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar MachineBasicBlock::iterator Last) { 9190c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar MachineBasicBlock::iterator End = std::next(Last); 9200c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar for (MachineBasicBlock::iterator I = First; I != End; ++I) { 9210c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar MachineInstr *MI = &*I; 9220c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // Do not touch instructions that are not predicated, or are predicated 9230c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // on the opposite condition. 924de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar if (!HII->isPredicated(*MI)) 9250c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar continue; 926de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar if (!MI->readsRegister(PredR) || (Cond != HII->isPredicatedTrue(*MI))) 9270c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar continue; 9280c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 9290c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar for (auto &Op : MI->operands()) { 9300c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (!Op.isReg() || RO != RegisterRef(Op)) 9310c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar continue; 9320c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar Op.setReg(RN.Reg); 9330c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar Op.setSubReg(RN.Sub); 9340c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // In practice, this isn't supposed to see any defs. 9350c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar assert(!Op.isDef() && "Not expecting a def"); 9360c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar } 9370c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar } 9380c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar} 9390c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 9400c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 9410c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar/// For a given conditional copy, predicate the definition of the source of 9420c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar/// the copy under the given condition (using the same predicate register as 9430c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar/// the copy). 944de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainarbool HexagonExpandCondsets::predicate(MachineInstr &TfrI, bool Cond, 945de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar std::set<unsigned> &UpdRegs) { 9460c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // TfrI - A2_tfr[tf] Instruction (not A2_tfrsi). 947de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar unsigned Opc = TfrI.getOpcode(); 9480c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar (void)Opc; 9490c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar assert(Opc == Hexagon::A2_tfrt || Opc == Hexagon::A2_tfrf); 9500c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar DEBUG(dbgs() << "\nattempt to predicate if-" << (Cond ? "true" : "false") 951de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar << ": " << TfrI); 9520c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 953de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar MachineOperand &MD = TfrI.getOperand(0); 954de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar MachineOperand &MP = TfrI.getOperand(1); 955de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar MachineOperand &MS = TfrI.getOperand(2); 9560c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // The source operand should be a <kill>. This is not strictly necessary, 9570c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // but it makes things a lot simpler. Otherwise, we would need to rename 9580c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // some registers, which would complicate the transformation considerably. 9590c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (!MS.isKill()) 9600c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar return false; 961de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // Avoid predicating instructions that define a subregister if subregister 962de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // liveness tracking is not enabled. 963de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar if (MD.getSubReg() && !MRI->shouldTrackSubRegLiveness(MD.getReg())) 964de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar return false; 9650c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 9660c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar RegisterRef RT(MS); 9670c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar unsigned PredR = MP.getReg(); 9680c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar MachineInstr *DefI = getReachingDefForPred(RT, TfrI, PredR, Cond); 9690c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (!DefI || !isPredicable(DefI)) 9700c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar return false; 9710c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 9720c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar DEBUG(dbgs() << "Source def: " << *DefI); 9730c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 9740c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // Collect the information about registers defined and used between the 9750c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // DefI and the TfrI. 9760c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // Map: reg -> bitmask of subregs 9770c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar ReferenceMap Uses, Defs; 9780c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar MachineBasicBlock::iterator DefIt = DefI, TfrIt = TfrI; 9790c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 9800c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // Check if the predicate register is valid between DefI and TfrI. 9810c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // If it is, we can then ignore instructions predicated on the negated 9820c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // conditions when collecting def and use information. 9830c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar bool PredValid = true; 9840c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar for (MachineBasicBlock::iterator I = std::next(DefIt); I != TfrIt; ++I) { 9850c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (!I->modifiesRegister(PredR, 0)) 9860c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar continue; 9870c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar PredValid = false; 9880c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar break; 9890c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar } 9900c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 9910c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar for (MachineBasicBlock::iterator I = std::next(DefIt); I != TfrIt; ++I) { 9920c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar MachineInstr *MI = &*I; 9930c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // If this instruction is predicated on the same register, it could 9940c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // potentially be ignored. 9950c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // By default assume that the instruction executes on the same condition 9960c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // as TfrI (Exec_Then), and also on the opposite one (Exec_Else). 9970c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar unsigned Exec = Exec_Then | Exec_Else; 998de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar if (PredValid && HII->isPredicated(*MI) && MI->readsRegister(PredR)) 999de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar Exec = (Cond == HII->isPredicatedTrue(*MI)) ? Exec_Then : Exec_Else; 10000c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 10010c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar for (auto &Op : MI->operands()) { 10020c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (!Op.isReg()) 10030c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar continue; 10040c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // We don't want to deal with physical registers. The reason is that 10050c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // they can be aliased with other physical registers. Aliased virtual 10060c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // registers must share the same register number, and can only differ 10070c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // in the subregisters, which we are keeping track of. Physical 10080c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // registers ters no longer have subregisters---their super- and 10090c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // subregisters are other physical registers, and we are not checking 10100c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // that. 10110c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar RegisterRef RR = Op; 10120c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (!TargetRegisterInfo::isVirtualRegister(RR.Reg)) 10130c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar return false; 10140c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 10150c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar ReferenceMap &Map = Op.isDef() ? Defs : Uses; 10160c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar addRefToMap(RR, Map, Exec); 10170c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar } 10180c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar } 10190c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 10200c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // The situation: 10210c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // RT = DefI 10220c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // ... 10230c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // RD = TfrI ..., RT 10240c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 10250c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // If the register-in-the-middle (RT) is used or redefined between 10260c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // DefI and TfrI, we may not be able proceed with this transformation. 10270c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // We can ignore a def that will not execute together with TfrI, and a 10280c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // use that will. If there is such a use (that does execute together with 10290c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // TfrI), we will not be able to move DefI down. If there is a use that 10300c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // executed if TfrI's condition is false, then RT must be available 10310c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // unconditionally (cannot be predicated). 10320c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // Essentially, we need to be able to rename RT to RD in this segment. 10330c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (isRefInMap(RT, Defs, Exec_Then) || isRefInMap(RT, Uses, Exec_Else)) 10340c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar return false; 10350c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar RegisterRef RD = MD; 10360c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // If the predicate register is defined between DefI and TfrI, the only 10370c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // potential thing to do would be to move the DefI down to TfrI, and then 10380c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // predicate. The reaching def (DefI) must be movable down to the location 10390c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // of the TfrI. 10400c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // If the target register of the TfrI (RD) is not used or defined between 10410c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // DefI and TfrI, consider moving TfrI up to DefI. 10420c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar bool CanUp = canMoveOver(TfrI, Defs, Uses); 1043de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar bool CanDown = canMoveOver(*DefI, Defs, Uses); 10440c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // The TfrI does not access memory, but DefI could. Check if it's safe 10450c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // to move DefI down to TfrI. 10460c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (DefI->mayLoad() || DefI->mayStore()) 1047de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar if (!canMoveMemTo(*DefI, TfrI, true)) 10480c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar CanDown = false; 10490c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 10500c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar DEBUG(dbgs() << "Can move up: " << (CanUp ? "yes" : "no") 10510c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar << ", can move down: " << (CanDown ? "yes\n" : "no\n")); 10520c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar MachineBasicBlock::iterator PastDefIt = std::next(DefIt); 10530c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (CanUp) 1054de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar predicateAt(MD, *DefI, PastDefIt, MP, Cond, UpdRegs); 10550c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar else if (CanDown) 1056de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar predicateAt(MD, *DefI, TfrIt, MP, Cond, UpdRegs); 10570c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar else 10580c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar return false; 10590c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 1060de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar if (RT != RD) { 10610c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar renameInRange(RT, RD, PredR, Cond, PastDefIt, TfrIt); 1062de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar UpdRegs.insert(RT.Reg); 1063de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar } 10640c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 1065de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar removeInstr(TfrI); 1066de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar removeInstr(*DefI); 10670c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar return true; 10680c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar} 10690c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 10700c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 10710c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar/// Predicate all cases of conditional copies in the specified block. 1072de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainarbool HexagonExpandCondsets::predicateInBlock(MachineBasicBlock &B, 1073de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar std::set<unsigned> &UpdRegs) { 10740c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar bool Changed = false; 10750c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar MachineBasicBlock::iterator I, E, NextI; 10760c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar for (I = B.begin(), E = B.end(); I != E; I = NextI) { 10770c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar NextI = std::next(I); 10780c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar unsigned Opc = I->getOpcode(); 10790c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (Opc == Hexagon::A2_tfrt || Opc == Hexagon::A2_tfrf) { 1080de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar bool Done = predicate(*I, (Opc == Hexagon::A2_tfrt), UpdRegs); 10810c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (!Done) { 10820c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // If we didn't predicate I, we may need to remove it in case it is 10830c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // an "identity" copy, e.g. vreg1 = A2_tfrt vreg2, vreg1. 1084de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar if (RegisterRef(I->getOperand(0)) == RegisterRef(I->getOperand(2))) { 1085de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar for (auto &Op : I->operands()) 1086de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar if (Op.isReg()) 1087de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar UpdRegs.insert(Op.getReg()); 1088de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar removeInstr(*I); 1089de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar } 10900c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar } 10910c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar Changed |= Done; 10920c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar } 10930c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar } 10940c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar return Changed; 10950c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar} 10960c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 10970c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 10980c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainarbool HexagonExpandCondsets::isIntReg(RegisterRef RR, unsigned &BW) { 10990c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (!TargetRegisterInfo::isVirtualRegister(RR.Reg)) 11000c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar return false; 11010c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar const TargetRegisterClass *RC = MRI->getRegClass(RR.Reg); 11020c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (RC == &Hexagon::IntRegsRegClass) { 11030c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar BW = 32; 11040c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar return true; 11050c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar } 11060c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (RC == &Hexagon::DoubleRegsRegClass) { 11070c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar BW = (RR.Sub != 0) ? 32 : 64; 11080c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar return true; 11090c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar } 11100c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar return false; 11110c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar} 11120c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 11130c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 11140c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainarbool HexagonExpandCondsets::isIntraBlocks(LiveInterval &LI) { 11150c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar for (LiveInterval::iterator I = LI.begin(), E = LI.end(); I != E; ++I) { 11160c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar LiveRange::Segment &LR = *I; 11170c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // Range must start at a register... 11180c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (!LR.start.isRegister()) 11190c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar return false; 11200c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // ...and end in a register or in a dead slot. 11210c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (!LR.end.isRegister() && !LR.end.isDead()) 11220c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar return false; 11230c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar } 11240c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar return true; 11250c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar} 11260c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 11270c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 11280c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainarbool HexagonExpandCondsets::coalesceRegisters(RegisterRef R1, RegisterRef R2) { 11290c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (CoaLimitActive) { 11300c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (CoaCounter >= CoaLimit) 11310c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar return false; 11320c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar CoaCounter++; 11330c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar } 11340c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar unsigned BW1, BW2; 11350c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (!isIntReg(R1, BW1) || !isIntReg(R2, BW2) || BW1 != BW2) 11360c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar return false; 11370c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (MRI->isLiveIn(R1.Reg)) 11380c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar return false; 11390c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (MRI->isLiveIn(R2.Reg)) 11400c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar return false; 11410c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 11420c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar LiveInterval &L1 = LIS->getInterval(R1.Reg); 11430c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar LiveInterval &L2 = LIS->getInterval(R2.Reg); 11440c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar bool Overlap = L1.overlaps(L2); 11450c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 11460c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar DEBUG(dbgs() << "compatible registers: (" 11470c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar << (Overlap ? "overlap" : "disjoint") << ")\n " 11480c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar << PrintReg(R1.Reg, TRI, R1.Sub) << " " << L1 << "\n " 11490c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar << PrintReg(R2.Reg, TRI, R2.Sub) << " " << L2 << "\n"); 11500c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (R1.Sub || R2.Sub) 11510c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar return false; 11520c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (Overlap) 11530c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar return false; 11540c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 11550c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // Coalescing could have a negative impact on scheduling, so try to limit 11560c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // to some reasonable extent. Only consider coalescing segments, when one 11570c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // of them does not cross basic block boundaries. 11580c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (!isIntraBlocks(L1) && !isIntraBlocks(L2)) 11590c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar return false; 11600c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 11610c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar MRI->replaceRegWith(R2.Reg, R1.Reg); 11620c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 11630c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // Move all live segments from L2 to L1. 11640c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar typedef DenseMap<VNInfo*,VNInfo*> ValueInfoMap; 11650c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar ValueInfoMap VM; 11660c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar for (LiveInterval::iterator I = L2.begin(), E = L2.end(); I != E; ++I) { 11670c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar VNInfo *NewVN, *OldVN = I->valno; 11680c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar ValueInfoMap::iterator F = VM.find(OldVN); 11690c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (F == VM.end()) { 11700c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar NewVN = L1.getNextValue(I->valno->def, LIS->getVNInfoAllocator()); 11710c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar VM.insert(std::make_pair(OldVN, NewVN)); 11720c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar } else { 11730c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar NewVN = F->second; 11740c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar } 11750c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar L1.addSegment(LiveRange::Segment(I->start, I->end, NewVN)); 11760c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar } 11770c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar while (L2.begin() != L2.end()) 11780c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar L2.removeSegment(*L2.begin()); 11790c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 1180de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar updateKillFlags(R1.Reg); 11810c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar DEBUG(dbgs() << "coalesced: " << L1 << "\n"); 11820c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar L1.verify(); 11830c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 11840c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar return true; 11850c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar} 11860c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 11870c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 11880c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar/// Attempt to coalesce one of the source registers to a MUX intruction with 11890c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar/// the destination register. This could lead to having only one predicated 11900c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar/// instruction in the end instead of two. 11910c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainarbool HexagonExpandCondsets::coalesceSegments(MachineFunction &MF) { 11920c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar SmallVector<MachineInstr*,16> Condsets; 11930c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I) { 11940c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar MachineBasicBlock &B = *I; 11950c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar for (MachineBasicBlock::iterator J = B.begin(), F = B.end(); J != F; ++J) { 11960c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar MachineInstr *MI = &*J; 1197de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar if (!isCondset(*MI)) 11980c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar continue; 11990c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar MachineOperand &S1 = MI->getOperand(2), &S2 = MI->getOperand(3); 12000c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (!S1.isReg() && !S2.isReg()) 12010c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar continue; 12020c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar Condsets.push_back(MI); 12030c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar } 12040c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar } 12050c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 12060c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar bool Changed = false; 12070c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar for (unsigned i = 0, n = Condsets.size(); i < n; ++i) { 12080c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar MachineInstr *CI = Condsets[i]; 12090c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar RegisterRef RD = CI->getOperand(0); 12100c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar RegisterRef RP = CI->getOperand(1); 12110c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar MachineOperand &S1 = CI->getOperand(2), &S2 = CI->getOperand(3); 12120c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar bool Done = false; 12130c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // Consider this case: 12140c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // vreg1 = instr1 ... 12150c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // vreg2 = instr2 ... 12160c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // vreg0 = C2_mux ..., vreg1, vreg2 12170c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // If vreg0 was coalesced with vreg1, we could end up with the following 12180c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // code: 12190c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // vreg0 = instr1 ... 12200c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // vreg2 = instr2 ... 12210c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // vreg0 = A2_tfrf ..., vreg2 12220c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // which will later become: 12230c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // vreg0 = instr1 ... 12240c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // vreg0 = instr2_cNotPt ... 12250c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // i.e. there will be an unconditional definition (instr1) of vreg0 12260c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // followed by a conditional one. The output dependency was there before 12270c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // and it unavoidable, but if instr1 is predicable, we will no longer be 12280c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // able to predicate it here. 12290c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // To avoid this scenario, don't coalesce the destination register with 12300c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // a source register that is defined by a predicable instruction. 12310c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (S1.isReg()) { 12320c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar RegisterRef RS = S1; 12330c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar MachineInstr *RDef = getReachingDefForPred(RS, CI, RP.Reg, true); 1234de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar if (!RDef || !HII->isPredicable(*RDef)) 12350c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar Done = coalesceRegisters(RD, RegisterRef(S1)); 12360c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar } 12370c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar if (!Done && S2.isReg()) { 12380c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar RegisterRef RS = S2; 12390c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar MachineInstr *RDef = getReachingDefForPred(RS, CI, RP.Reg, false); 1240de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar if (!RDef || !HII->isPredicable(*RDef)) 12410c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar Done = coalesceRegisters(RD, RegisterRef(S2)); 12420c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar } 12430c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar Changed |= Done; 12440c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar } 12450c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar return Changed; 12460c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar} 12470c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 12480c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 12490c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainarbool HexagonExpandCondsets::runOnMachineFunction(MachineFunction &MF) { 1250de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar if (skipFunction(*MF.getFunction())) 1251de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar return false; 1252de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar 12530c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar HII = static_cast<const HexagonInstrInfo*>(MF.getSubtarget().getInstrInfo()); 12540c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar TRI = MF.getSubtarget().getRegisterInfo(); 1255de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar MDT = &getAnalysis<MachineDominatorTree>(); 12560c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar LIS = &getAnalysis<LiveIntervals>(); 12570c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar MRI = &MF.getRegInfo(); 1258de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar LocalImpDefs.clear(); 1259de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar 1260de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar DEBUG(LIS->print(dbgs() << "Before expand-condsets\n", 1261de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar MF.getFunction()->getParent())); 12620c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 12630c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar bool Changed = false; 1264de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar std::set<unsigned> SplitUpd, PredUpd; 12650c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 12660c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // Try to coalesce the target of a mux with one of its sources. 12670c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar // This could eliminate a register copy in some circumstances. 12680c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar Changed |= coalesceSegments(MF); 12690c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 1270de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // First, simply split all muxes into a pair of conditional transfers 1271de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // and update the live intervals to reflect the new arrangement. The 1272de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // goal is to update the kill flags, since predication will rely on 1273de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // them. 1274de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar for (auto &B : MF) 1275de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar Changed |= splitInBlock(B, SplitUpd); 1276de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar updateLiveness(SplitUpd, true, true, false); 1277de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar 1278de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // Traverse all blocks and collapse predicable instructions feeding 1279de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // conditional transfers into predicated instructions. 1280de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // Walk over all the instructions again, so we may catch pre-existing 1281de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // cases that were not created in the previous step. 1282de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar for (auto &B : MF) 1283de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar Changed |= predicateInBlock(B, PredUpd); 1284de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar 1285de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar updateLiveness(PredUpd, true, true, true); 1286de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // Remove from SplitUpd all registers contained in PredUpd to avoid 1287de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar // unnecessary liveness recalculation. 1288de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar std::set<unsigned> Diff; 1289de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar std::set_difference(SplitUpd.begin(), SplitUpd.end(), 1290de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar PredUpd.begin(), PredUpd.end(), 1291de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar std::inserter(Diff, Diff.begin())); 1292de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar updateLiveness(Diff, false, false, true); 1293de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar 1294de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar for (auto *ImpD : LocalImpDefs) 1295de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar removeInstr(*ImpD); 1296de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar 1297de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar DEBUG({ 1298de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar if (Changed) 1299de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar LIS->print(dbgs() << "After expand-condsets\n", 1300de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar MF.getFunction()->getParent()); 1301de2d8694e25a814696358e95141f4b1aa4d8847ePirama Arumuga Nainar }); 13020c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 13030c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar return Changed; 13040c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar} 13050c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 13060c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 13070c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar//===----------------------------------------------------------------------===// 13080c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar// Public Constructor Functions 13090c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar//===----------------------------------------------------------------------===// 13100c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar 13110c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga NainarFunctionPass *llvm::createHexagonExpandCondsets() { 13120c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar return new HexagonExpandCondsets(); 13130c7f116bb6950ef819323d855415b2f2b0aad987Pirama Arumuga Nainar} 1314