MipsTargetMachine.cpp revision aeef83c6afa1e18d1cf9d359cc678ca0ad556175
1//===-- MipsTargetMachine.cpp - Define TargetMachine for Mips -------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// Implements the info about Mips target spec. 11// 12//===----------------------------------------------------------------------===// 13 14#include "MipsTargetMachine.h" 15#include "Mips.h" 16#include "MipsFrameLowering.h" 17#include "MipsInstrInfo.h" 18#include "llvm/CodeGen/Passes.h" 19#include "llvm/PassManager.h" 20#include "llvm/Support/TargetRegistry.h" 21using namespace llvm; 22 23extern "C" void LLVMInitializeMipsTarget() { 24 // Register the target. 25 RegisterTargetMachine<MipsebTargetMachine> X(TheMipsTarget); 26 RegisterTargetMachine<MipselTargetMachine> Y(TheMipselTarget); 27 RegisterTargetMachine<MipsebTargetMachine> A(TheMips64Target); 28 RegisterTargetMachine<MipselTargetMachine> B(TheMips64elTarget); 29} 30 31// DataLayout --> Big-endian, 32-bit pointer/ABI/alignment 32// The stack is always 8 byte aligned 33// On function prologue, the stack is created by decrementing 34// its pointer. Once decremented, all references are done with positive 35// offset from the stack/frame pointer, using StackGrowsUp enables 36// an easier handling. 37// Using CodeModel::Large enables different CALL behavior. 38MipsTargetMachine:: 39MipsTargetMachine(const Target &T, StringRef TT, 40 StringRef CPU, StringRef FS, const TargetOptions &Options, 41 Reloc::Model RM, CodeModel::Model CM, 42 CodeGenOpt::Level OL, 43 bool isLittle) 44 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL), 45 Subtarget(TT, CPU, FS, isLittle, RM), 46 DL(isLittle ? 47 (Subtarget.isABI_N64() ? 48 "e-p:64:64:64-i8:8:32-i16:16:32-i64:64:64-f128:128:128-" 49 "n32:64-S128" : 50 "e-p:32:32:32-i8:8:32-i16:16:32-i64:64:64-n32-S64") : 51 (Subtarget.isABI_N64() ? 52 "E-p:64:64:64-i8:8:32-i16:16:32-i64:64:64-f128:128:128-" 53 "n32:64-S128" : 54 "E-p:32:32:32-i8:8:32-i16:16:32-i64:64:64-n32-S64")), 55 InstrInfo(MipsInstrInfo::create(*this)), 56 FrameLowering(MipsFrameLowering::create(*this, Subtarget)), 57 TLInfo(*this), TSInfo(*this), JITInfo() { 58} 59 60void MipsebTargetMachine::anchor() { } 61 62MipsebTargetMachine:: 63MipsebTargetMachine(const Target &T, StringRef TT, 64 StringRef CPU, StringRef FS, const TargetOptions &Options, 65 Reloc::Model RM, CodeModel::Model CM, 66 CodeGenOpt::Level OL) 67 : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {} 68 69void MipselTargetMachine::anchor() { } 70 71MipselTargetMachine:: 72MipselTargetMachine(const Target &T, StringRef TT, 73 StringRef CPU, StringRef FS, const TargetOptions &Options, 74 Reloc::Model RM, CodeModel::Model CM, 75 CodeGenOpt::Level OL) 76 : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {} 77 78namespace { 79/// Mips Code Generator Pass Configuration Options. 80class MipsPassConfig : public TargetPassConfig { 81public: 82 MipsPassConfig(MipsTargetMachine *TM, PassManagerBase &PM) 83 : TargetPassConfig(TM, PM) {} 84 85 MipsTargetMachine &getMipsTargetMachine() const { 86 return getTM<MipsTargetMachine>(); 87 } 88 89 const MipsSubtarget &getMipsSubtarget() const { 90 return *getMipsTargetMachine().getSubtargetImpl(); 91 } 92 93 virtual bool addInstSelector(); 94 virtual bool addPreEmitPass(); 95}; 96} // namespace 97 98TargetPassConfig *MipsTargetMachine::createPassConfig(PassManagerBase &PM) { 99 return new MipsPassConfig(this, PM); 100} 101 102// Install an instruction selector pass using 103// the ISelDag to gen Mips code. 104bool MipsPassConfig::addInstSelector() { 105 addPass(createMipsISelDag(getMipsTargetMachine())); 106 return false; 107} 108 109// Implemented by targets that want to run passes immediately before 110// machine code is emitted. return true if -print-machineinstrs should 111// print out the code after the passes. 112bool MipsPassConfig::addPreEmitPass() { 113 MipsTargetMachine &TM = getMipsTargetMachine(); 114 addPass(createMipsDelaySlotFillerPass(TM)); 115 116 // NOTE: long branch has not been implemented for mips16. 117 if (TM.getSubtarget<MipsSubtarget>().hasStandardEncoding()) 118 addPass(createMipsLongBranchPass(TM)); 119 120 return true; 121} 122 123bool MipsTargetMachine::addCodeEmitter(PassManagerBase &PM, 124 JITCodeEmitter &JCE) { 125 // Machine code emitter pass for Mips. 126 PM.add(createMipsJITCodeEmitterPass(*this, JCE)); 127 return false; 128} 129