NVPTX.h revision 0ff4287fe2245f417ed78fa535fce360b8b8df23 
1//===-- NVPTX.h - Top-level interface for NVPTX representation --*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the entry points for global functions defined in
11// the LLVM NVPTX back-end.
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef LLVM_TARGET_NVPTX_H
16#define LLVM_TARGET_NVPTX_H
17
18#include "MCTargetDesc/NVPTXBaseInfo.h"
19#include "llvm/ADT/StringMap.h"
20#include "llvm/IR/Module.h"
21#include "llvm/IR/Value.h"
22#include "llvm/Support/ErrorHandling.h"
23#include "llvm/Target/TargetMachine.h"
24#include <cassert>
25#include <iosfwd>
26
27namespace llvm {
28class NVPTXTargetMachine;
29class FunctionPass;
30class MachineFunctionPass;
31class formatted_raw_ostream;
32
33namespace NVPTXCC {
34enum CondCodes {
35  EQ,
36  NE,
37  LT,
38  LE,
39  GT,
40  GE
41};
42}
43
44inline static const char *NVPTXCondCodeToString(NVPTXCC::CondCodes CC) {
45  switch (CC) {
46  case NVPTXCC::NE:
47    return "ne";
48  case NVPTXCC::EQ:
49    return "eq";
50  case NVPTXCC::LT:
51    return "lt";
52  case NVPTXCC::LE:
53    return "le";
54  case NVPTXCC::GT:
55    return "gt";
56  case NVPTXCC::GE:
57    return "ge";
58  }
59  llvm_unreachable("Unknown condition code");
60}
61
62FunctionPass *
63createNVPTXISelDag(NVPTXTargetMachine &TM, llvm::CodeGenOpt::Level OptLevel);
64FunctionPass *createLowerStructArgsPass(NVPTXTargetMachine &);
65FunctionPass *createNVPTXReMatPass(NVPTXTargetMachine &);
66FunctionPass *createNVPTXReMatBlockPass(NVPTXTargetMachine &);
67ModulePass *createGenericToNVVMPass();
68ModulePass *createNVVMReflectPass();
69ModulePass *createNVVMReflectPass(const StringMap<int>& Mapping);
70MachineFunctionPass *createNVPTXPrologEpilogPass();
71
72bool isImageOrSamplerVal(const Value *, const Module *);
73
74extern Target TheNVPTXTarget32;
75extern Target TheNVPTXTarget64;
76
77namespace NVPTX {
78enum DrvInterface {
79  NVCL,
80  CUDA
81};
82
83// A field inside TSFlags needs a shift and a mask. The usage is
84// always as follows :
85// ((TSFlags & fieldMask) >> fieldShift)
86// The enum keeps the mask, the shift, and all valid values of the
87// field in one place.
88enum VecInstType {
89  VecInstTypeShift = 0,
90  VecInstTypeMask = 0xF,
91
92  VecNOP = 0,
93  VecLoad = 1,
94  VecStore = 2,
95  VecBuild = 3,
96  VecShuffle = 4,
97  VecExtract = 5,
98  VecInsert = 6,
99  VecDest = 7,
100  VecOther = 15
101};
102
103enum SimpleMove {
104  SimpleMoveMask = 0x10,
105  SimpleMoveShift = 4
106};
107enum LoadStore {
108  isLoadMask = 0x20,
109  isLoadShift = 5,
110  isStoreMask = 0x40,
111  isStoreShift = 6
112};
113
114namespace PTXLdStInstCode {
115enum AddressSpace {
116  GENERIC = 0,
117  GLOBAL = 1,
118  CONSTANT = 2,
119  SHARED = 3,
120  PARAM = 4,
121  LOCAL = 5
122};
123enum FromType {
124  Unsigned = 0,
125  Signed,
126  Float
127};
128enum VecType {
129  Scalar = 1,
130  V2 = 2,
131  V4 = 4
132};
133}
134}
135} // end namespace llvm;
136
137// Defines symbolic names for NVPTX registers.  This defines a mapping from
138// register name to register number.
139#define GET_REGINFO_ENUM
140#include "NVPTXGenRegisterInfo.inc"
141
142// Defines symbolic names for the NVPTX instructions.
143#define GET_INSTRINFO_ENUM
144#include "NVPTXGenInstrInfo.inc"
145
146#endif
147