1//===-- PPCSubtarget.h - Define Subtarget for the PPC ----------*- C++ -*--===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file declares the PowerPC specific subclass of TargetSubtargetInfo.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_LIB_TARGET_POWERPC_PPCSUBTARGET_H
15#define LLVM_LIB_TARGET_POWERPC_PPCSUBTARGET_H
16
17#include "PPCFrameLowering.h"
18#include "PPCISelLowering.h"
19#include "PPCInstrInfo.h"
20#include "llvm/ADT/Triple.h"
21#include "llvm/CodeGen/SelectionDAGTargetInfo.h"
22#include "llvm/IR/DataLayout.h"
23#include "llvm/MC/MCInstrItineraries.h"
24#include "llvm/Target/TargetSubtargetInfo.h"
25#include <string>
26
27#define GET_SUBTARGETINFO_HEADER
28#include "PPCGenSubtargetInfo.inc"
29
30// GCC #defines PPC on Linux but we use it as our namespace name
31#undef PPC
32
33namespace llvm {
34class StringRef;
35
36namespace PPC {
37  // -m directive values.
38  enum {
39    DIR_NONE,
40    DIR_32,
41    DIR_440,
42    DIR_601,
43    DIR_602,
44    DIR_603,
45    DIR_7400,
46    DIR_750,
47    DIR_970,
48    DIR_A2,
49    DIR_E500mc,
50    DIR_E5500,
51    DIR_PWR3,
52    DIR_PWR4,
53    DIR_PWR5,
54    DIR_PWR5X,
55    DIR_PWR6,
56    DIR_PWR6X,
57    DIR_PWR7,
58    DIR_PWR8,
59    DIR_PWR9,
60    DIR_64
61  };
62}
63
64class GlobalValue;
65class TargetMachine;
66
67class PPCSubtarget : public PPCGenSubtargetInfo {
68public:
69  enum POPCNTDKind {
70    POPCNTD_Unavailable,
71    POPCNTD_Slow,
72    POPCNTD_Fast
73  };
74
75protected:
76  /// TargetTriple - What processor and OS we're targeting.
77  Triple TargetTriple;
78
79  /// stackAlignment - The minimum alignment known to hold of the stack frame on
80  /// entry to the function and which must be maintained by every function.
81  unsigned StackAlignment;
82
83  /// Selected instruction itineraries (one entry per itinerary class.)
84  InstrItineraryData InstrItins;
85
86  /// Which cpu directive was used.
87  unsigned DarwinDirective;
88
89  /// Used by the ISel to turn in optimizations for POWER4-derived architectures
90  bool HasMFOCRF;
91  bool Has64BitSupport;
92  bool Use64BitRegs;
93  bool UseCRBits;
94  bool UseSoftFloat;
95  bool IsPPC64;
96  bool HasAltivec;
97  bool HasSPE;
98  bool HasQPX;
99  bool HasVSX;
100  bool HasP8Vector;
101  bool HasP8Altivec;
102  bool HasP8Crypto;
103  bool HasP9Vector;
104  bool HasP9Altivec;
105  bool HasFCPSGN;
106  bool HasFSQRT;
107  bool HasFRE, HasFRES, HasFRSQRTE, HasFRSQRTES;
108  bool HasRecipPrec;
109  bool HasSTFIWX;
110  bool HasLFIWAX;
111  bool HasFPRND;
112  bool HasFPCVT;
113  bool HasISEL;
114  bool HasBPERMD;
115  bool HasExtDiv;
116  bool HasCMPB;
117  bool HasLDBRX;
118  bool IsBookE;
119  bool HasOnlyMSYNC;
120  bool IsE500;
121  bool IsPPC4xx;
122  bool IsPPC6xx;
123  bool FeatureMFTB;
124  bool DeprecatedDST;
125  bool HasLazyResolverStubs;
126  bool IsLittleEndian;
127  bool HasICBT;
128  bool HasInvariantFunctionDescriptors;
129  bool HasPartwordAtomics;
130  bool HasDirectMove;
131  bool HasHTM;
132  bool HasFusion;
133  bool HasFloat128;
134  bool IsISA3_0;
135
136  POPCNTDKind HasPOPCNTD;
137
138  /// When targeting QPX running a stock PPC64 Linux kernel where the stack
139  /// alignment has not been changed, we need to keep the 16-byte alignment
140  /// of the stack.
141  bool IsQPXStackUnaligned;
142
143  const PPCTargetMachine &TM;
144  PPCFrameLowering FrameLowering;
145  PPCInstrInfo InstrInfo;
146  PPCTargetLowering TLInfo;
147  SelectionDAGTargetInfo TSInfo;
148
149public:
150  /// This constructor initializes the data members to match that
151  /// of the specified triple.
152  ///
153  PPCSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS,
154               const PPCTargetMachine &TM);
155
156  /// ParseSubtargetFeatures - Parses features string setting specified
157  /// subtarget options.  Definition of function is auto generated by tblgen.
158  void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
159
160  /// getStackAlignment - Returns the minimum alignment known to hold of the
161  /// stack frame on entry to the function and which must be maintained by every
162  /// function for this subtarget.
163  unsigned getStackAlignment() const { return StackAlignment; }
164
165  /// getDarwinDirective - Returns the -m directive specified for the cpu.
166  ///
167  unsigned getDarwinDirective() const { return DarwinDirective; }
168
169  /// getInstrItins - Return the instruction itineraries based on subtarget
170  /// selection.
171  const InstrItineraryData *getInstrItineraryData() const override {
172    return &InstrItins;
173  }
174
175  const PPCFrameLowering *getFrameLowering() const override {
176    return &FrameLowering;
177  }
178  const PPCInstrInfo *getInstrInfo() const override { return &InstrInfo; }
179  const PPCTargetLowering *getTargetLowering() const override {
180    return &TLInfo;
181  }
182  const SelectionDAGTargetInfo *getSelectionDAGInfo() const override {
183    return &TSInfo;
184  }
185  const PPCRegisterInfo *getRegisterInfo() const override {
186    return &getInstrInfo()->getRegisterInfo();
187  }
188  const PPCTargetMachine &getTargetMachine() const { return TM; }
189
190  /// initializeSubtargetDependencies - Initializes using a CPU and feature string
191  /// so that we can use initializer lists for subtarget initialization.
192  PPCSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS);
193
194private:
195  void initializeEnvironment();
196  void initSubtargetFeatures(StringRef CPU, StringRef FS);
197
198public:
199  /// isPPC64 - Return true if we are generating code for 64-bit pointer mode.
200  ///
201  bool isPPC64() const;
202
203  /// has64BitSupport - Return true if the selected CPU supports 64-bit
204  /// instructions, regardless of whether we are in 32-bit or 64-bit mode.
205  bool has64BitSupport() const { return Has64BitSupport; }
206  // useSoftFloat - Return true if soft-float option is turned on.
207  bool useSoftFloat() const { return UseSoftFloat; }
208
209  /// use64BitRegs - Return true if in 64-bit mode or if we should use 64-bit
210  /// registers in 32-bit mode when possible.  This can only true if
211  /// has64BitSupport() returns true.
212  bool use64BitRegs() const { return Use64BitRegs; }
213
214  /// useCRBits - Return true if we should store and manipulate i1 values in
215  /// the individual condition register bits.
216  bool useCRBits() const { return UseCRBits; }
217
218  /// hasLazyResolverStub - Return true if accesses to the specified global have
219  /// to go through a dyld lazy resolution stub.  This means that an extra load
220  /// is required to get the address of the global.
221  bool hasLazyResolverStub(const GlobalValue *GV) const;
222
223  // isLittleEndian - True if generating little-endian code
224  bool isLittleEndian() const { return IsLittleEndian; }
225
226  // Specific obvious features.
227  bool hasFCPSGN() const { return HasFCPSGN; }
228  bool hasFSQRT() const { return HasFSQRT; }
229  bool hasFRE() const { return HasFRE; }
230  bool hasFRES() const { return HasFRES; }
231  bool hasFRSQRTE() const { return HasFRSQRTE; }
232  bool hasFRSQRTES() const { return HasFRSQRTES; }
233  bool hasRecipPrec() const { return HasRecipPrec; }
234  bool hasSTFIWX() const { return HasSTFIWX; }
235  bool hasLFIWAX() const { return HasLFIWAX; }
236  bool hasFPRND() const { return HasFPRND; }
237  bool hasFPCVT() const { return HasFPCVT; }
238  bool hasAltivec() const { return HasAltivec; }
239  bool hasSPE() const { return HasSPE; }
240  bool hasQPX() const { return HasQPX; }
241  bool hasVSX() const { return HasVSX; }
242  bool hasP8Vector() const { return HasP8Vector; }
243  bool hasP8Altivec() const { return HasP8Altivec; }
244  bool hasP8Crypto() const { return HasP8Crypto; }
245  bool hasP9Vector() const { return HasP9Vector; }
246  bool hasP9Altivec() const { return HasP9Altivec; }
247  bool hasMFOCRF() const { return HasMFOCRF; }
248  bool hasISEL() const { return HasISEL; }
249  bool hasBPERMD() const { return HasBPERMD; }
250  bool hasExtDiv() const { return HasExtDiv; }
251  bool hasCMPB() const { return HasCMPB; }
252  bool hasLDBRX() const { return HasLDBRX; }
253  bool isBookE() const { return IsBookE; }
254  bool hasOnlyMSYNC() const { return HasOnlyMSYNC; }
255  bool isPPC4xx() const { return IsPPC4xx; }
256  bool isPPC6xx() const { return IsPPC6xx; }
257  bool isE500() const { return IsE500; }
258  bool isFeatureMFTB() const { return FeatureMFTB; }
259  bool isDeprecatedDST() const { return DeprecatedDST; }
260  bool hasICBT() const { return HasICBT; }
261  bool hasInvariantFunctionDescriptors() const {
262    return HasInvariantFunctionDescriptors;
263  }
264  bool hasPartwordAtomics() const { return HasPartwordAtomics; }
265  bool hasDirectMove() const { return HasDirectMove; }
266
267  bool isQPXStackUnaligned() const { return IsQPXStackUnaligned; }
268  unsigned getPlatformStackAlignment() const {
269    if ((hasQPX() || isBGQ()) && !isQPXStackUnaligned())
270      return 32;
271
272    return 16;
273  }
274  bool hasHTM() const { return HasHTM; }
275  bool hasFusion() const { return HasFusion; }
276  bool hasFloat128() const { return HasFloat128; }
277  bool isISA3_0() const { return IsISA3_0; }
278
279  POPCNTDKind hasPOPCNTD() const { return HasPOPCNTD; }
280
281  const Triple &getTargetTriple() const { return TargetTriple; }
282
283  /// isDarwin - True if this is any darwin platform.
284  bool isDarwin() const { return TargetTriple.isMacOSX(); }
285  /// isBGQ - True if this is a BG/Q platform.
286  bool isBGQ() const { return TargetTriple.getVendor() == Triple::BGQ; }
287
288  bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
289  bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
290  bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
291
292  bool isDarwinABI() const { return isTargetMachO() || isDarwin(); }
293  bool isSVR4ABI() const { return !isDarwinABI(); }
294  bool isELFv2ABI() const;
295
296  bool enableEarlyIfConversion() const override { return hasISEL(); }
297
298  // Scheduling customization.
299  bool enableMachineScheduler() const override;
300  // This overrides the PostRAScheduler bit in the SchedModel for each CPU.
301  bool enablePostRAScheduler() const override;
302  AntiDepBreakMode getAntiDepBreakMode() const override;
303  void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const override;
304
305  void overrideSchedPolicy(MachineSchedPolicy &Policy,
306                           unsigned NumRegionInstrs) const override;
307  bool useAA() const override;
308
309  bool enableSubRegLiveness() const override;
310
311  /// classifyGlobalReference - Classify a global variable reference for the
312  /// current subtarget accourding to how we should reference it.
313  unsigned char classifyGlobalReference(const GlobalValue *GV) const;
314};
315} // End llvm namespace
316
317#endif
318