1//===-- X86InstrBuilder.h - Functions to aid building x86 insts -*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file exposes functions that may be used with BuildMI from the
11// MachineInstrBuilder.h file to handle X86'isms in a clean way.
12//
13// The BuildMem function may be used with the BuildMI function to add entire
14// memory references in a single, typed, function call.  X86 memory references
15// can be very complex expressions (described in the README), so wrapping them
16// up behind an easier to use interface makes sense.  Descriptions of the
17// functions are included below.
18//
19// For reference, the order of operands for memory references is:
20// (Operand), Base, Scale, Index, Displacement.
21//
22//===----------------------------------------------------------------------===//
23
24#ifndef LLVM_LIB_TARGET_X86_X86INSTRBUILDER_H
25#define LLVM_LIB_TARGET_X86_X86INSTRBUILDER_H
26
27#include "llvm/CodeGen/MachineFrameInfo.h"
28#include "llvm/CodeGen/MachineInstrBuilder.h"
29#include "llvm/CodeGen/MachineMemOperand.h"
30
31namespace llvm {
32
33/// X86AddressMode - This struct holds a generalized full x86 address mode.
34/// The base register can be a frame index, which will eventually be replaced
35/// with BP or SP and Disp being offsetted accordingly.  The displacement may
36/// also include the offset of a global value.
37struct X86AddressMode {
38  enum {
39    RegBase,
40    FrameIndexBase
41  } BaseType;
42
43  union {
44    unsigned Reg;
45    int FrameIndex;
46  } Base;
47
48  unsigned Scale;
49  unsigned IndexReg;
50  int Disp;
51  const GlobalValue *GV;
52  unsigned GVOpFlags;
53
54  X86AddressMode()
55    : BaseType(RegBase), Scale(1), IndexReg(0), Disp(0), GV(nullptr),
56      GVOpFlags(0) {
57    Base.Reg = 0;
58  }
59
60
61  void getFullAddress(SmallVectorImpl<MachineOperand> &MO) {
62    assert(Scale == 1 || Scale == 2 || Scale == 4 || Scale == 8);
63
64    if (BaseType == X86AddressMode::RegBase)
65      MO.push_back(MachineOperand::CreateReg(Base.Reg, false, false,
66                                             false, false, false, 0, false));
67    else {
68      assert(BaseType == X86AddressMode::FrameIndexBase);
69      MO.push_back(MachineOperand::CreateFI(Base.FrameIndex));
70    }
71
72    MO.push_back(MachineOperand::CreateImm(Scale));
73    MO.push_back(MachineOperand::CreateReg(IndexReg, false, false,
74                                           false, false, false, 0, false));
75
76    if (GV)
77      MO.push_back(MachineOperand::CreateGA(GV, Disp, GVOpFlags));
78    else
79      MO.push_back(MachineOperand::CreateImm(Disp));
80
81    MO.push_back(MachineOperand::CreateReg(0, false, false,
82                                           false, false, false, 0, false));
83  }
84};
85
86/// Compute the addressing mode from an machine instruction starting with the
87/// given operand.
88static inline X86AddressMode getAddressFromInstr(MachineInstr *MI,
89                                                 unsigned Operand) {
90  X86AddressMode AM;
91  MachineOperand &Op = MI->getOperand(Operand);
92  if (Op.isReg()) {
93    AM.BaseType = X86AddressMode::RegBase;
94    AM.Base.Reg = Op.getReg();
95  } else {
96    AM.BaseType = X86AddressMode::FrameIndexBase;
97    AM.Base.FrameIndex = Op.getIndex();
98  }
99  Op = MI->getOperand(Operand + 1);
100  if (Op.isImm())
101    AM.Scale = Op.getImm();
102  Op = MI->getOperand(Operand + 2);
103  if (Op.isImm())
104    AM.IndexReg = Op.getImm();
105  Op = MI->getOperand(Operand + 3);
106  if (Op.isGlobal()) {
107    AM.GV = Op.getGlobal();
108  } else {
109    AM.Disp = Op.getImm();
110  }
111  return AM;
112}
113
114/// addDirectMem - This function is used to add a direct memory reference to the
115/// current instruction -- that is, a dereference of an address in a register,
116/// with no scale, index or displacement. An example is: DWORD PTR [EAX].
117///
118static inline const MachineInstrBuilder &
119addDirectMem(const MachineInstrBuilder &MIB, unsigned Reg) {
120  // Because memory references are always represented with five
121  // values, this adds: Reg, 1, NoReg, 0, NoReg to the instruction.
122  return MIB.addReg(Reg).addImm(1).addReg(0).addImm(0).addReg(0);
123}
124
125
126static inline const MachineInstrBuilder &
127addOffset(const MachineInstrBuilder &MIB, int Offset) {
128  return MIB.addImm(1).addReg(0).addImm(Offset).addReg(0);
129}
130
131/// addRegOffset - This function is used to add a memory reference of the form
132/// [Reg + Offset], i.e., one with no scale or index, but with a
133/// displacement. An example is: DWORD PTR [EAX + 4].
134///
135static inline const MachineInstrBuilder &
136addRegOffset(const MachineInstrBuilder &MIB,
137             unsigned Reg, bool isKill, int Offset) {
138  return addOffset(MIB.addReg(Reg, getKillRegState(isKill)), Offset);
139}
140
141/// addRegReg - This function is used to add a memory reference of the form:
142/// [Reg + Reg].
143static inline const MachineInstrBuilder &addRegReg(const MachineInstrBuilder &MIB,
144                                            unsigned Reg1, bool isKill1,
145                                            unsigned Reg2, bool isKill2) {
146  return MIB.addReg(Reg1, getKillRegState(isKill1)).addImm(1)
147    .addReg(Reg2, getKillRegState(isKill2)).addImm(0).addReg(0);
148}
149
150static inline const MachineInstrBuilder &
151addFullAddress(const MachineInstrBuilder &MIB,
152               const X86AddressMode &AM) {
153  assert(AM.Scale == 1 || AM.Scale == 2 || AM.Scale == 4 || AM.Scale == 8);
154
155  if (AM.BaseType == X86AddressMode::RegBase)
156    MIB.addReg(AM.Base.Reg);
157  else {
158    assert(AM.BaseType == X86AddressMode::FrameIndexBase);
159    MIB.addFrameIndex(AM.Base.FrameIndex);
160  }
161
162  MIB.addImm(AM.Scale).addReg(AM.IndexReg);
163  if (AM.GV)
164    MIB.addGlobalAddress(AM.GV, AM.Disp, AM.GVOpFlags);
165  else
166    MIB.addImm(AM.Disp);
167
168  return MIB.addReg(0);
169}
170
171/// addFrameReference - This function is used to add a reference to the base of
172/// an abstract object on the stack frame of the current function.  This
173/// reference has base register as the FrameIndex offset until it is resolved.
174/// This allows a constant offset to be specified as well...
175///
176static inline const MachineInstrBuilder &
177addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset = 0) {
178  MachineInstr *MI = MIB;
179  MachineFunction &MF = *MI->getParent()->getParent();
180  MachineFrameInfo &MFI = *MF.getFrameInfo();
181  const MCInstrDesc &MCID = MI->getDesc();
182  unsigned Flags = 0;
183  if (MCID.mayLoad())
184    Flags |= MachineMemOperand::MOLoad;
185  if (MCID.mayStore())
186    Flags |= MachineMemOperand::MOStore;
187  MachineMemOperand *MMO = MF.getMachineMemOperand(
188      MachinePointerInfo::getFixedStack(MF, FI, Offset), Flags,
189      MFI.getObjectSize(FI), MFI.getObjectAlignment(FI));
190  return addOffset(MIB.addFrameIndex(FI), Offset)
191            .addMemOperand(MMO);
192}
193
194/// addConstantPoolReference - This function is used to add a reference to the
195/// base of a constant value spilled to the per-function constant pool.  The
196/// reference uses the abstract ConstantPoolIndex which is retained until
197/// either machine code emission or assembly output. In PIC mode on x86-32,
198/// the GlobalBaseReg parameter can be used to make this a
199/// GlobalBaseReg-relative reference.
200///
201static inline const MachineInstrBuilder &
202addConstantPoolReference(const MachineInstrBuilder &MIB, unsigned CPI,
203                         unsigned GlobalBaseReg, unsigned char OpFlags) {
204  //FIXME: factor this
205  return MIB.addReg(GlobalBaseReg).addImm(1).addReg(0)
206    .addConstantPoolIndex(CPI, 0, OpFlags).addReg(0);
207}
208
209} // End llvm namespace
210
211#endif
212