X86InstrInfo.cpp revision 126f17a17625876adb63f06d043fc1b1e4f0361c
1//===- X86InstrInfo.cpp - X86 Instruction Information -----------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the X86 implementation of the TargetInstrInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "X86InstrInfo.h" 15#include "X86.h" 16#include "X86GenInstrInfo.inc" 17#include "X86InstrBuilder.h" 18#include "X86Subtarget.h" 19#include "X86TargetMachine.h" 20#include "llvm/CodeGen/MachineInstrBuilder.h" 21#include "llvm/CodeGen/LiveVariables.h" 22using namespace llvm; 23 24X86InstrInfo::X86InstrInfo(X86TargetMachine &tm) 25 : TargetInstrInfo(X86Insts, sizeof(X86Insts)/sizeof(X86Insts[0])), 26 TM(tm), RI(tm, *this) { 27} 28 29bool X86InstrInfo::isMoveInstr(const MachineInstr& MI, 30 unsigned& sourceReg, 31 unsigned& destReg) const { 32 MachineOpCode oc = MI.getOpcode(); 33 if (oc == X86::MOV8rr || oc == X86::MOV16rr || 34 oc == X86::MOV32rr || oc == X86::MOV64rr || 35 oc == X86::MOV16to16_ || oc == X86::MOV32to32_ || 36 oc == X86::FpMOV || oc == X86::MOVSSrr || oc == X86::MOVSDrr || 37 oc == X86::FsMOVAPSrr || oc == X86::FsMOVAPDrr || 38 oc == X86::MOVAPSrr || oc == X86::MOVAPDrr || 39 oc == X86::MOVSS2PSrr || oc == X86::MOVSD2PDrr || 40 oc == X86::MOVPS2SSrr || oc == X86::MOVPD2SDrr || 41 oc == X86::MMX_MOVD64rr || oc == X86::MMX_MOVQ64rr) { 42 assert(MI.getNumOperands() >= 2 && 43 MI.getOperand(0).isRegister() && 44 MI.getOperand(1).isRegister() && 45 "invalid register-register move instruction"); 46 sourceReg = MI.getOperand(1).getReg(); 47 destReg = MI.getOperand(0).getReg(); 48 return true; 49 } 50 return false; 51} 52 53unsigned X86InstrInfo::isLoadFromStackSlot(MachineInstr *MI, 54 int &FrameIndex) const { 55 switch (MI->getOpcode()) { 56 default: break; 57 case X86::MOV8rm: 58 case X86::MOV16rm: 59 case X86::MOV16_rm: 60 case X86::MOV32rm: 61 case X86::MOV32_rm: 62 case X86::MOV64rm: 63 case X86::FpLD64m: 64 case X86::MOVSSrm: 65 case X86::MOVSDrm: 66 case X86::MOVAPSrm: 67 case X86::MOVAPDrm: 68 case X86::MMX_MOVD64rm: 69 case X86::MMX_MOVQ64rm: 70 if (MI->getOperand(1).isFrameIndex() && MI->getOperand(2).isImmediate() && 71 MI->getOperand(3).isRegister() && MI->getOperand(4).isImmediate() && 72 MI->getOperand(2).getImmedValue() == 1 && 73 MI->getOperand(3).getReg() == 0 && 74 MI->getOperand(4).getImmedValue() == 0) { 75 FrameIndex = MI->getOperand(1).getFrameIndex(); 76 return MI->getOperand(0).getReg(); 77 } 78 break; 79 } 80 return 0; 81} 82 83unsigned X86InstrInfo::isStoreToStackSlot(MachineInstr *MI, 84 int &FrameIndex) const { 85 switch (MI->getOpcode()) { 86 default: break; 87 case X86::MOV8mr: 88 case X86::MOV16mr: 89 case X86::MOV16_mr: 90 case X86::MOV32mr: 91 case X86::MOV32_mr: 92 case X86::MOV64mr: 93 case X86::FpSTP64m: 94 case X86::MOVSSmr: 95 case X86::MOVSDmr: 96 case X86::MOVAPSmr: 97 case X86::MOVAPDmr: 98 case X86::MMX_MOVD64mr: 99 case X86::MMX_MOVQ64mr: 100 case X86::MMX_MOVNTQmr: 101 if (MI->getOperand(0).isFrameIndex() && MI->getOperand(1).isImmediate() && 102 MI->getOperand(2).isRegister() && MI->getOperand(3).isImmediate() && 103 MI->getOperand(1).getImmedValue() == 1 && 104 MI->getOperand(2).getReg() == 0 && 105 MI->getOperand(3).getImmedValue() == 0) { 106 FrameIndex = MI->getOperand(0).getFrameIndex(); 107 return MI->getOperand(4).getReg(); 108 } 109 break; 110 } 111 return 0; 112} 113 114 115/// convertToThreeAddress - This method must be implemented by targets that 116/// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target 117/// may be able to convert a two-address instruction into a true 118/// three-address instruction on demand. This allows the X86 target (for 119/// example) to convert ADD and SHL instructions into LEA instructions if they 120/// would require register copies due to two-addressness. 121/// 122/// This method returns a null pointer if the transformation cannot be 123/// performed, otherwise it returns the new instruction. 124/// 125MachineInstr * 126X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI, 127 MachineBasicBlock::iterator &MBBI, 128 LiveVariables &LV) const { 129 MachineInstr *MI = MBBI; 130 // All instructions input are two-addr instructions. Get the known operands. 131 unsigned Dest = MI->getOperand(0).getReg(); 132 unsigned Src = MI->getOperand(1).getReg(); 133 134 MachineInstr *NewMI = NULL; 135 // FIXME: 16-bit LEA's are really slow on Athlons, but not bad on P4's. When 136 // we have better subtarget support, enable the 16-bit LEA generation here. 137 bool DisableLEA16 = true; 138 139 switch (MI->getOpcode()) { 140 default: return 0; 141 case X86::SHUFPSrri: { 142 assert(MI->getNumOperands() == 4 && "Unknown shufps instruction!"); 143 if (!TM.getSubtarget<X86Subtarget>().hasSSE2()) return 0; 144 145 unsigned A = MI->getOperand(0).getReg(); 146 unsigned B = MI->getOperand(1).getReg(); 147 unsigned C = MI->getOperand(2).getReg(); 148 unsigned M = MI->getOperand(3).getImm(); 149 if (B != C) return 0; 150 NewMI = BuildMI(get(X86::PSHUFDri), A).addReg(B).addImm(M); 151 break; 152 } 153 case X86::SHL64ri: { 154 assert(MI->getNumOperands() == 3 && "Unknown shift instruction!"); 155 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses 156 // the flags produced by a shift yet, so this is safe. 157 unsigned Dest = MI->getOperand(0).getReg(); 158 unsigned Src = MI->getOperand(1).getReg(); 159 unsigned ShAmt = MI->getOperand(2).getImm(); 160 if (ShAmt == 0 || ShAmt >= 4) return 0; 161 162 NewMI = BuildMI(get(X86::LEA64r), Dest) 163 .addReg(0).addImm(1 << ShAmt).addReg(Src).addImm(0); 164 break; 165 } 166 case X86::SHL32ri: { 167 assert(MI->getNumOperands() == 3 && "Unknown shift instruction!"); 168 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses 169 // the flags produced by a shift yet, so this is safe. 170 unsigned Dest = MI->getOperand(0).getReg(); 171 unsigned Src = MI->getOperand(1).getReg(); 172 unsigned ShAmt = MI->getOperand(2).getImm(); 173 if (ShAmt == 0 || ShAmt >= 4) return 0; 174 175 unsigned Opc = TM.getSubtarget<X86Subtarget>().is64Bit() ? 176 X86::LEA64_32r : X86::LEA32r; 177 NewMI = BuildMI(get(Opc), Dest) 178 .addReg(0).addImm(1 << ShAmt).addReg(Src).addImm(0); 179 break; 180 } 181 case X86::SHL16ri: { 182 assert(MI->getNumOperands() == 3 && "Unknown shift instruction!"); 183 if (DisableLEA16) return 0; 184 185 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses 186 // the flags produced by a shift yet, so this is safe. 187 unsigned Dest = MI->getOperand(0).getReg(); 188 unsigned Src = MI->getOperand(1).getReg(); 189 unsigned ShAmt = MI->getOperand(2).getImm(); 190 if (ShAmt == 0 || ShAmt >= 4) return 0; 191 192 NewMI = BuildMI(get(X86::LEA16r), Dest) 193 .addReg(0).addImm(1 << ShAmt).addReg(Src).addImm(0); 194 break; 195 } 196 } 197 198 // FIXME: None of these instructions are promotable to LEAs without 199 // additional information. In particular, LEA doesn't set the flags that 200 // add and inc do. :( 201 if (0) 202 switch (MI->getOpcode()) { 203 case X86::INC32r: 204 case X86::INC64_32r: 205 assert(MI->getNumOperands() == 2 && "Unknown inc instruction!"); 206 NewMI = addRegOffset(BuildMI(get(X86::LEA32r), Dest), Src, 1); 207 break; 208 case X86::INC16r: 209 case X86::INC64_16r: 210 if (DisableLEA16) return 0; 211 assert(MI->getNumOperands() == 2 && "Unknown inc instruction!"); 212 NewMI = addRegOffset(BuildMI(get(X86::LEA16r), Dest), Src, 1); 213 break; 214 case X86::DEC32r: 215 case X86::DEC64_32r: 216 assert(MI->getNumOperands() == 2 && "Unknown dec instruction!"); 217 NewMI = addRegOffset(BuildMI(get(X86::LEA32r), Dest), Src, -1); 218 break; 219 case X86::DEC16r: 220 case X86::DEC64_16r: 221 if (DisableLEA16) return 0; 222 assert(MI->getNumOperands() == 2 && "Unknown dec instruction!"); 223 NewMI = addRegOffset(BuildMI(get(X86::LEA16r), Dest), Src, -1); 224 break; 225 case X86::ADD32rr: 226 assert(MI->getNumOperands() == 3 && "Unknown add instruction!"); 227 NewMI = addRegReg(BuildMI(get(X86::LEA32r), Dest), Src, 228 MI->getOperand(2).getReg()); 229 break; 230 case X86::ADD16rr: 231 if (DisableLEA16) return 0; 232 assert(MI->getNumOperands() == 3 && "Unknown add instruction!"); 233 NewMI = addRegReg(BuildMI(get(X86::LEA16r), Dest), Src, 234 MI->getOperand(2).getReg()); 235 break; 236 case X86::ADD32ri: 237 case X86::ADD32ri8: 238 assert(MI->getNumOperands() == 3 && "Unknown add instruction!"); 239 if (MI->getOperand(2).isImmediate()) 240 NewMI = addRegOffset(BuildMI(get(X86::LEA32r), Dest), Src, 241 MI->getOperand(2).getImmedValue()); 242 break; 243 case X86::ADD16ri: 244 case X86::ADD16ri8: 245 if (DisableLEA16) return 0; 246 assert(MI->getNumOperands() == 3 && "Unknown add instruction!"); 247 if (MI->getOperand(2).isImmediate()) 248 NewMI = addRegOffset(BuildMI(get(X86::LEA16r), Dest), Src, 249 MI->getOperand(2).getImmedValue()); 250 break; 251 case X86::SHL16ri: 252 if (DisableLEA16) return 0; 253 case X86::SHL32ri: 254 assert(MI->getNumOperands() == 3 && MI->getOperand(2).isImmediate() && 255 "Unknown shl instruction!"); 256 unsigned ShAmt = MI->getOperand(2).getImmedValue(); 257 if (ShAmt == 1 || ShAmt == 2 || ShAmt == 3) { 258 X86AddressMode AM; 259 AM.Scale = 1 << ShAmt; 260 AM.IndexReg = Src; 261 unsigned Opc = MI->getOpcode() == X86::SHL32ri ? X86::LEA32r :X86::LEA16r; 262 NewMI = addFullAddress(BuildMI(get(Opc), Dest), AM); 263 } 264 break; 265 } 266 267 if (NewMI) { 268 NewMI->copyKillDeadInfo(MI); 269 LV.instructionChanged(MI, NewMI); // Update live variables 270 MFI->insert(MBBI, NewMI); // Insert the new inst 271 } 272 return NewMI; 273} 274 275/// commuteInstruction - We have a few instructions that must be hacked on to 276/// commute them. 277/// 278MachineInstr *X86InstrInfo::commuteInstruction(MachineInstr *MI) const { 279 // FIXME: Can commute cmoves by changing the condition! 280 switch (MI->getOpcode()) { 281 case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I) 282 case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I) 283 case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I) 284 case X86::SHLD32rri8:{// A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I) 285 unsigned Opc; 286 unsigned Size; 287 switch (MI->getOpcode()) { 288 default: assert(0 && "Unreachable!"); 289 case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break; 290 case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break; 291 case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break; 292 case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break; 293 } 294 unsigned Amt = MI->getOperand(3).getImmedValue(); 295 unsigned A = MI->getOperand(0).getReg(); 296 unsigned B = MI->getOperand(1).getReg(); 297 unsigned C = MI->getOperand(2).getReg(); 298 bool BisKill = MI->getOperand(1).isKill(); 299 bool CisKill = MI->getOperand(2).isKill(); 300 return BuildMI(get(Opc), A).addReg(C, false, false, CisKill) 301 .addReg(B, false, false, BisKill).addImm(Size-Amt); 302 } 303 default: 304 return TargetInstrInfo::commuteInstruction(MI); 305 } 306} 307 308static X86::CondCode GetCondFromBranchOpc(unsigned BrOpc) { 309 switch (BrOpc) { 310 default: return X86::COND_INVALID; 311 case X86::JE: return X86::COND_E; 312 case X86::JNE: return X86::COND_NE; 313 case X86::JL: return X86::COND_L; 314 case X86::JLE: return X86::COND_LE; 315 case X86::JG: return X86::COND_G; 316 case X86::JGE: return X86::COND_GE; 317 case X86::JB: return X86::COND_B; 318 case X86::JBE: return X86::COND_BE; 319 case X86::JA: return X86::COND_A; 320 case X86::JAE: return X86::COND_AE; 321 case X86::JS: return X86::COND_S; 322 case X86::JNS: return X86::COND_NS; 323 case X86::JP: return X86::COND_P; 324 case X86::JNP: return X86::COND_NP; 325 case X86::JO: return X86::COND_O; 326 case X86::JNO: return X86::COND_NO; 327 } 328} 329 330unsigned X86::GetCondBranchFromCond(X86::CondCode CC) { 331 switch (CC) { 332 default: assert(0 && "Illegal condition code!"); 333 case X86::COND_E: return X86::JE; 334 case X86::COND_NE: return X86::JNE; 335 case X86::COND_L: return X86::JL; 336 case X86::COND_LE: return X86::JLE; 337 case X86::COND_G: return X86::JG; 338 case X86::COND_GE: return X86::JGE; 339 case X86::COND_B: return X86::JB; 340 case X86::COND_BE: return X86::JBE; 341 case X86::COND_A: return X86::JA; 342 case X86::COND_AE: return X86::JAE; 343 case X86::COND_S: return X86::JS; 344 case X86::COND_NS: return X86::JNS; 345 case X86::COND_P: return X86::JP; 346 case X86::COND_NP: return X86::JNP; 347 case X86::COND_O: return X86::JO; 348 case X86::COND_NO: return X86::JNO; 349 } 350} 351 352/// GetOppositeBranchCondition - Return the inverse of the specified condition, 353/// e.g. turning COND_E to COND_NE. 354X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) { 355 switch (CC) { 356 default: assert(0 && "Illegal condition code!"); 357 case X86::COND_E: return X86::COND_NE; 358 case X86::COND_NE: return X86::COND_E; 359 case X86::COND_L: return X86::COND_GE; 360 case X86::COND_LE: return X86::COND_G; 361 case X86::COND_G: return X86::COND_LE; 362 case X86::COND_GE: return X86::COND_L; 363 case X86::COND_B: return X86::COND_AE; 364 case X86::COND_BE: return X86::COND_A; 365 case X86::COND_A: return X86::COND_BE; 366 case X86::COND_AE: return X86::COND_B; 367 case X86::COND_S: return X86::COND_NS; 368 case X86::COND_NS: return X86::COND_S; 369 case X86::COND_P: return X86::COND_NP; 370 case X86::COND_NP: return X86::COND_P; 371 case X86::COND_O: return X86::COND_NO; 372 case X86::COND_NO: return X86::COND_O; 373 } 374} 375 376 377bool X86InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, 378 MachineBasicBlock *&TBB, 379 MachineBasicBlock *&FBB, 380 std::vector<MachineOperand> &Cond) const { 381 // TODO: If FP_REG_KILL is around, ignore it. 382 383 // If the block has no terminators, it just falls into the block after it. 384 MachineBasicBlock::iterator I = MBB.end(); 385 if (I == MBB.begin() || !isTerminatorInstr((--I)->getOpcode())) 386 return false; 387 388 // Get the last instruction in the block. 389 MachineInstr *LastInst = I; 390 391 // If there is only one terminator instruction, process it. 392 if (I == MBB.begin() || !isTerminatorInstr((--I)->getOpcode())) { 393 if (!isBranch(LastInst->getOpcode())) 394 return true; 395 396 // If the block ends with a branch there are 3 possibilities: 397 // it's an unconditional, conditional, or indirect branch. 398 399 if (LastInst->getOpcode() == X86::JMP) { 400 TBB = LastInst->getOperand(0).getMachineBasicBlock(); 401 return false; 402 } 403 X86::CondCode BranchCode = GetCondFromBranchOpc(LastInst->getOpcode()); 404 if (BranchCode == X86::COND_INVALID) 405 return true; // Can't handle indirect branch. 406 407 // Otherwise, block ends with fall-through condbranch. 408 TBB = LastInst->getOperand(0).getMachineBasicBlock(); 409 Cond.push_back(MachineOperand::CreateImm(BranchCode)); 410 return false; 411 } 412 413 // Get the instruction before it if it's a terminator. 414 MachineInstr *SecondLastInst = I; 415 416 // If there are three terminators, we don't know what sort of block this is. 417 if (SecondLastInst && I != MBB.begin() && 418 isTerminatorInstr((--I)->getOpcode())) 419 return true; 420 421 // If the block ends with X86::JMP and a conditional branch, handle it. 422 X86::CondCode BranchCode = GetCondFromBranchOpc(SecondLastInst->getOpcode()); 423 if (BranchCode != X86::COND_INVALID && LastInst->getOpcode() == X86::JMP) { 424 TBB = SecondLastInst->getOperand(0).getMachineBasicBlock(); 425 Cond.push_back(MachineOperand::CreateImm(BranchCode)); 426 FBB = LastInst->getOperand(0).getMachineBasicBlock(); 427 return false; 428 } 429 430 // Otherwise, can't handle this. 431 return true; 432} 433 434unsigned X86InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const { 435 MachineBasicBlock::iterator I = MBB.end(); 436 if (I == MBB.begin()) return 0; 437 --I; 438 if (I->getOpcode() != X86::JMP && 439 GetCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID) 440 return 0; 441 442 // Remove the branch. 443 I->eraseFromParent(); 444 445 I = MBB.end(); 446 447 if (I == MBB.begin()) return 1; 448 --I; 449 if (GetCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID) 450 return 1; 451 452 // Remove the branch. 453 I->eraseFromParent(); 454 return 2; 455} 456 457unsigned 458X86InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 459 MachineBasicBlock *FBB, 460 const std::vector<MachineOperand> &Cond) const { 461 // Shouldn't be a fall through. 462 assert(TBB && "InsertBranch must not be told to insert a fallthrough"); 463 assert((Cond.size() == 1 || Cond.size() == 0) && 464 "X86 branch conditions have one component!"); 465 466 if (FBB == 0) { // One way branch. 467 if (Cond.empty()) { 468 // Unconditional branch? 469 BuildMI(&MBB, get(X86::JMP)).addMBB(TBB); 470 } else { 471 // Conditional branch. 472 unsigned Opc = GetCondBranchFromCond((X86::CondCode)Cond[0].getImm()); 473 BuildMI(&MBB, get(Opc)).addMBB(TBB); 474 } 475 return 1; 476 } 477 478 // Two-way Conditional branch. 479 unsigned Opc = GetCondBranchFromCond((X86::CondCode)Cond[0].getImm()); 480 BuildMI(&MBB, get(Opc)).addMBB(TBB); 481 BuildMI(&MBB, get(X86::JMP)).addMBB(FBB); 482 return 2; 483} 484 485bool X86InstrInfo::BlockHasNoFallThrough(MachineBasicBlock &MBB) const { 486 if (MBB.empty()) return false; 487 488 switch (MBB.back().getOpcode()) { 489 case X86::RET: // Return. 490 case X86::RETI: 491 case X86::TAILJMPd: 492 case X86::TAILJMPr: 493 case X86::TAILJMPm: 494 case X86::JMP: // Uncond branch. 495 case X86::JMP32r: // Indirect branch. 496 case X86::JMP32m: // Indirect branch through mem. 497 return true; 498 default: return false; 499 } 500} 501 502bool X86InstrInfo:: 503ReverseBranchCondition(std::vector<MachineOperand> &Cond) const { 504 assert(Cond.size() == 1 && "Invalid X86 branch condition!"); 505 Cond[0].setImm(GetOppositeBranchCondition((X86::CondCode)Cond[0].getImm())); 506 return false; 507} 508 509const TargetRegisterClass *X86InstrInfo::getPointerRegClass() const { 510 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>(); 511 if (Subtarget->is64Bit()) 512 return &X86::GR64RegClass; 513 else 514 return &X86::GR32RegClass; 515} 516