X86InstrInfo.cpp revision 5c00e077952d14899c3fc26709c7b2dfd36d0209
1cc49f813b0d7bf6664102b30b5513fd21c362e0dNeil Fuller//===- X86InstrInfo.cpp - X86 Instruction Information -----------*- C++ -*-===// 2cc49f813b0d7bf6664102b30b5513fd21c362e0dNeil Fuller// 3cc49f813b0d7bf6664102b30b5513fd21c362e0dNeil Fuller// The LLVM Compiler Infrastructure 4cc49f813b0d7bf6664102b30b5513fd21c362e0dNeil Fuller// 5cc49f813b0d7bf6664102b30b5513fd21c362e0dNeil Fuller// This file is distributed under the University of Illinois Open Source 6cc49f813b0d7bf6664102b30b5513fd21c362e0dNeil Fuller// License. See LICENSE.TXT for details. 7cc49f813b0d7bf6664102b30b5513fd21c362e0dNeil Fuller// 8cc49f813b0d7bf6664102b30b5513fd21c362e0dNeil Fuller//===----------------------------------------------------------------------===// 9cc49f813b0d7bf6664102b30b5513fd21c362e0dNeil Fuller// 10cc49f813b0d7bf6664102b30b5513fd21c362e0dNeil Fuller// This file contains the X86 implementation of the TargetInstrInfo class. 11cc49f813b0d7bf6664102b30b5513fd21c362e0dNeil Fuller// 12cc49f813b0d7bf6664102b30b5513fd21c362e0dNeil Fuller//===----------------------------------------------------------------------===// 13cc49f813b0d7bf6664102b30b5513fd21c362e0dNeil Fuller 14cc49f813b0d7bf6664102b30b5513fd21c362e0dNeil Fuller#include "X86InstrInfo.h" 15cc49f813b0d7bf6664102b30b5513fd21c362e0dNeil Fuller#include "X86.h" 16cc49f813b0d7bf6664102b30b5513fd21c362e0dNeil Fuller#include "X86GenInstrInfo.inc" 17cc49f813b0d7bf6664102b30b5513fd21c362e0dNeil Fuller#include "X86InstrBuilder.h" 18cc49f813b0d7bf6664102b30b5513fd21c362e0dNeil Fuller#include "X86MachineFunctionInfo.h" 19cc49f813b0d7bf6664102b30b5513fd21c362e0dNeil Fuller#include "X86Subtarget.h" 20cc49f813b0d7bf6664102b30b5513fd21c362e0dNeil Fuller#include "X86TargetMachine.h" 21ac1c676b1256aaa85c5cc22494ea56bd2d276b9fNeil Fuller#include "llvm/DerivedTypes.h" 22cc49f813b0d7bf6664102b30b5513fd21c362e0dNeil Fuller#include "llvm/LLVMContext.h" 23cc49f813b0d7bf6664102b30b5513fd21c362e0dNeil Fuller#include "llvm/ADT/STLExtras.h" 24ac1c676b1256aaa85c5cc22494ea56bd2d276b9fNeil Fuller#include "llvm/CodeGen/MachineConstantPool.h" 25ac1c676b1256aaa85c5cc22494ea56bd2d276b9fNeil Fuller#include "llvm/CodeGen/MachineFrameInfo.h" 26cc49f813b0d7bf6664102b30b5513fd21c362e0dNeil Fuller#include "llvm/CodeGen/MachineInstrBuilder.h" 27cc49f813b0d7bf6664102b30b5513fd21c362e0dNeil Fuller#include "llvm/CodeGen/MachineRegisterInfo.h" 28cc49f813b0d7bf6664102b30b5513fd21c362e0dNeil Fuller#include "llvm/CodeGen/LiveVariables.h" 29cc49f813b0d7bf6664102b30b5513fd21c362e0dNeil Fuller#include "llvm/CodeGen/PseudoSourceValue.h" 30cc49f813b0d7bf6664102b30b5513fd21c362e0dNeil Fuller#include "llvm/MC/MCInst.h" 31cc49f813b0d7bf6664102b30b5513fd21c362e0dNeil Fuller#include "llvm/Support/CommandLine.h" 32cc49f813b0d7bf6664102b30b5513fd21c362e0dNeil Fuller#include "llvm/Support/Debug.h" 33cc49f813b0d7bf6664102b30b5513fd21c362e0dNeil Fuller#include "llvm/Support/ErrorHandling.h" 346a016ebfcb5009b380a656ed29d81c16f382c379Neil Fuller#include "llvm/Support/raw_ostream.h" 35cc49f813b0d7bf6664102b30b5513fd21c362e0dNeil Fuller#include "llvm/Target/TargetOptions.h" 36cc49f813b0d7bf6664102b30b5513fd21c362e0dNeil Fuller#include "llvm/MC/MCAsmInfo.h" 376a016ebfcb5009b380a656ed29d81c16f382c379Neil Fuller 3893cf604e9dd0525f15bc0a7450b2a35f3884c298Neil Fuller#include <limits> 3993cf604e9dd0525f15bc0a7450b2a35f3884c298Neil Fuller 4093cf604e9dd0525f15bc0a7450b2a35f3884c298Neil Fullerusing namespace llvm; 41cc49f813b0d7bf6664102b30b5513fd21c362e0dNeil Fuller 42cc49f813b0d7bf6664102b30b5513fd21c362e0dNeil Fullerstatic cl::opt<bool> 43cc49f813b0d7bf6664102b30b5513fd21c362e0dNeil FullerNoFusing("disable-spill-fusing", 44cc49f813b0d7bf6664102b30b5513fd21c362e0dNeil Fuller cl::desc("Disable fusing of spill code into instructions")); 45cc49f813b0d7bf6664102b30b5513fd21c362e0dNeil Fullerstatic cl::opt<bool> 46cc49f813b0d7bf6664102b30b5513fd21c362e0dNeil FullerPrintFailedFusing("print-failed-fuse-candidates", 47cc49f813b0d7bf6664102b30b5513fd21c362e0dNeil Fuller cl::desc("Print instructions that the allocator wants to" 48cc49f813b0d7bf6664102b30b5513fd21c362e0dNeil Fuller " fuse, but the X86 backend currently can't"), 49cc49f813b0d7bf6664102b30b5513fd21c362e0dNeil Fuller cl::Hidden); 50cc49f813b0d7bf6664102b30b5513fd21c362e0dNeil Fullerstatic cl::opt<bool> 51cc49f813b0d7bf6664102b30b5513fd21c362e0dNeil FullerReMatPICStubLoad("remat-pic-stub-load", 52cc49f813b0d7bf6664102b30b5513fd21c362e0dNeil Fuller cl::desc("Re-materialize load from stub in PIC mode"), 53cc49f813b0d7bf6664102b30b5513fd21c362e0dNeil Fuller cl::init(false), cl::Hidden); 546a016ebfcb5009b380a656ed29d81c16f382c379Neil Fuller 55cc49f813b0d7bf6664102b30b5513fd21c362e0dNeil FullerX86InstrInfo::X86InstrInfo(X86TargetMachine &tm) 56cc49f813b0d7bf6664102b30b5513fd21c362e0dNeil Fuller : TargetInstrInfoImpl(X86Insts, array_lengthof(X86Insts)), 57cc49f813b0d7bf6664102b30b5513fd21c362e0dNeil Fuller TM(tm), RI(tm, *this) { 58cc49f813b0d7bf6664102b30b5513fd21c362e0dNeil Fuller SmallVector<unsigned,16> AmbEntries; 59cc49f813b0d7bf6664102b30b5513fd21c362e0dNeil Fuller static const unsigned OpTbl2Addr[][2] = { 60cc49f813b0d7bf6664102b30b5513fd21c362e0dNeil Fuller { X86::ADC32ri, X86::ADC32mi }, 61cc49f813b0d7bf6664102b30b5513fd21c362e0dNeil Fuller { X86::ADC32ri8, X86::ADC32mi8 }, 626a016ebfcb5009b380a656ed29d81c16f382c379Neil Fuller { X86::ADC32rr, X86::ADC32mr }, 63ac1c676b1256aaa85c5cc22494ea56bd2d276b9fNeil Fuller { X86::ADC64ri32, X86::ADC64mi32 }, 64cc49f813b0d7bf6664102b30b5513fd21c362e0dNeil Fuller { X86::ADC64ri8, X86::ADC64mi8 }, 65cc49f813b0d7bf6664102b30b5513fd21c362e0dNeil Fuller { X86::ADC64rr, X86::ADC64mr }, 666a016ebfcb5009b380a656ed29d81c16f382c379Neil Fuller { X86::ADD16ri, X86::ADD16mi }, 67ac1c676b1256aaa85c5cc22494ea56bd2d276b9fNeil Fuller { X86::ADD16ri8, X86::ADD16mi8 }, 68cc49f813b0d7bf6664102b30b5513fd21c362e0dNeil Fuller { X86::ADD16rr, X86::ADD16mr }, 69cc49f813b0d7bf6664102b30b5513fd21c362e0dNeil Fuller { X86::ADD32ri, X86::ADD32mi }, 70cc49f813b0d7bf6664102b30b5513fd21c362e0dNeil Fuller { X86::ADD32ri8, X86::ADD32mi8 }, 71cc49f813b0d7bf6664102b30b5513fd21c362e0dNeil Fuller { X86::ADD32rr, X86::ADD32mr }, 72cc49f813b0d7bf6664102b30b5513fd21c362e0dNeil Fuller { X86::ADD64ri32, X86::ADD64mi32 }, 73cc49f813b0d7bf6664102b30b5513fd21c362e0dNeil Fuller { X86::ADD64ri8, X86::ADD64mi8 }, 74cc49f813b0d7bf6664102b30b5513fd21c362e0dNeil Fuller { X86::ADD64rr, X86::ADD64mr }, 75cc49f813b0d7bf6664102b30b5513fd21c362e0dNeil Fuller { X86::ADD8ri, X86::ADD8mi }, 76cc49f813b0d7bf6664102b30b5513fd21c362e0dNeil Fuller { X86::ADD8rr, X86::ADD8mr }, 77cc49f813b0d7bf6664102b30b5513fd21c362e0dNeil Fuller { X86::AND16ri, X86::AND16mi }, 78cc49f813b0d7bf6664102b30b5513fd21c362e0dNeil Fuller { X86::AND16ri8, X86::AND16mi8 }, 79 { X86::AND16rr, X86::AND16mr }, 80 { X86::AND32ri, X86::AND32mi }, 81 { X86::AND32ri8, X86::AND32mi8 }, 82 { X86::AND32rr, X86::AND32mr }, 83 { X86::AND64ri32, X86::AND64mi32 }, 84 { X86::AND64ri8, X86::AND64mi8 }, 85 { X86::AND64rr, X86::AND64mr }, 86 { X86::AND8ri, X86::AND8mi }, 87 { X86::AND8rr, X86::AND8mr }, 88 { X86::DEC16r, X86::DEC16m }, 89 { X86::DEC32r, X86::DEC32m }, 90 { X86::DEC64_16r, X86::DEC64_16m }, 91 { X86::DEC64_32r, X86::DEC64_32m }, 92 { X86::DEC64r, X86::DEC64m }, 93 { X86::DEC8r, X86::DEC8m }, 94 { X86::INC16r, X86::INC16m }, 95 { X86::INC32r, X86::INC32m }, 96 { X86::INC64_16r, X86::INC64_16m }, 97 { X86::INC64_32r, X86::INC64_32m }, 98 { X86::INC64r, X86::INC64m }, 99 { X86::INC8r, X86::INC8m }, 100 { X86::NEG16r, X86::NEG16m }, 101 { X86::NEG32r, X86::NEG32m }, 102 { X86::NEG64r, X86::NEG64m }, 103 { X86::NEG8r, X86::NEG8m }, 104 { X86::NOT16r, X86::NOT16m }, 105 { X86::NOT32r, X86::NOT32m }, 106 { X86::NOT64r, X86::NOT64m }, 107 { X86::NOT8r, X86::NOT8m }, 108 { X86::OR16ri, X86::OR16mi }, 109 { X86::OR16ri8, X86::OR16mi8 }, 110 { X86::OR16rr, X86::OR16mr }, 111 { X86::OR32ri, X86::OR32mi }, 112 { X86::OR32ri8, X86::OR32mi8 }, 113 { X86::OR32rr, X86::OR32mr }, 114 { X86::OR64ri32, X86::OR64mi32 }, 115 { X86::OR64ri8, X86::OR64mi8 }, 116 { X86::OR64rr, X86::OR64mr }, 117 { X86::OR8ri, X86::OR8mi }, 118 { X86::OR8rr, X86::OR8mr }, 119 { X86::ROL16r1, X86::ROL16m1 }, 120 { X86::ROL16rCL, X86::ROL16mCL }, 121 { X86::ROL16ri, X86::ROL16mi }, 122 { X86::ROL32r1, X86::ROL32m1 }, 123 { X86::ROL32rCL, X86::ROL32mCL }, 124 { X86::ROL32ri, X86::ROL32mi }, 125 { X86::ROL64r1, X86::ROL64m1 }, 126 { X86::ROL64rCL, X86::ROL64mCL }, 127 { X86::ROL64ri, X86::ROL64mi }, 128 { X86::ROL8r1, X86::ROL8m1 }, 129 { X86::ROL8rCL, X86::ROL8mCL }, 130 { X86::ROL8ri, X86::ROL8mi }, 131 { X86::ROR16r1, X86::ROR16m1 }, 132 { X86::ROR16rCL, X86::ROR16mCL }, 133 { X86::ROR16ri, X86::ROR16mi }, 134 { X86::ROR32r1, X86::ROR32m1 }, 135 { X86::ROR32rCL, X86::ROR32mCL }, 136 { X86::ROR32ri, X86::ROR32mi }, 137 { X86::ROR64r1, X86::ROR64m1 }, 138 { X86::ROR64rCL, X86::ROR64mCL }, 139 { X86::ROR64ri, X86::ROR64mi }, 140 { X86::ROR8r1, X86::ROR8m1 }, 141 { X86::ROR8rCL, X86::ROR8mCL }, 142 { X86::ROR8ri, X86::ROR8mi }, 143 { X86::SAR16r1, X86::SAR16m1 }, 144 { X86::SAR16rCL, X86::SAR16mCL }, 145 { X86::SAR16ri, X86::SAR16mi }, 146 { X86::SAR32r1, X86::SAR32m1 }, 147 { X86::SAR32rCL, X86::SAR32mCL }, 148 { X86::SAR32ri, X86::SAR32mi }, 149 { X86::SAR64r1, X86::SAR64m1 }, 150 { X86::SAR64rCL, X86::SAR64mCL }, 151 { X86::SAR64ri, X86::SAR64mi }, 152 { X86::SAR8r1, X86::SAR8m1 }, 153 { X86::SAR8rCL, X86::SAR8mCL }, 154 { X86::SAR8ri, X86::SAR8mi }, 155 { X86::SBB32ri, X86::SBB32mi }, 156 { X86::SBB32ri8, X86::SBB32mi8 }, 157 { X86::SBB32rr, X86::SBB32mr }, 158 { X86::SBB64ri32, X86::SBB64mi32 }, 159 { X86::SBB64ri8, X86::SBB64mi8 }, 160 { X86::SBB64rr, X86::SBB64mr }, 161 { X86::SHL16rCL, X86::SHL16mCL }, 162 { X86::SHL16ri, X86::SHL16mi }, 163 { X86::SHL32rCL, X86::SHL32mCL }, 164 { X86::SHL32ri, X86::SHL32mi }, 165 { X86::SHL64rCL, X86::SHL64mCL }, 166 { X86::SHL64ri, X86::SHL64mi }, 167 { X86::SHL8rCL, X86::SHL8mCL }, 168 { X86::SHL8ri, X86::SHL8mi }, 169 { X86::SHLD16rrCL, X86::SHLD16mrCL }, 170 { X86::SHLD16rri8, X86::SHLD16mri8 }, 171 { X86::SHLD32rrCL, X86::SHLD32mrCL }, 172 { X86::SHLD32rri8, X86::SHLD32mri8 }, 173 { X86::SHLD64rrCL, X86::SHLD64mrCL }, 174 { X86::SHLD64rri8, X86::SHLD64mri8 }, 175 { X86::SHR16r1, X86::SHR16m1 }, 176 { X86::SHR16rCL, X86::SHR16mCL }, 177 { X86::SHR16ri, X86::SHR16mi }, 178 { X86::SHR32r1, X86::SHR32m1 }, 179 { X86::SHR32rCL, X86::SHR32mCL }, 180 { X86::SHR32ri, X86::SHR32mi }, 181 { X86::SHR64r1, X86::SHR64m1 }, 182 { X86::SHR64rCL, X86::SHR64mCL }, 183 { X86::SHR64ri, X86::SHR64mi }, 184 { X86::SHR8r1, X86::SHR8m1 }, 185 { X86::SHR8rCL, X86::SHR8mCL }, 186 { X86::SHR8ri, X86::SHR8mi }, 187 { X86::SHRD16rrCL, X86::SHRD16mrCL }, 188 { X86::SHRD16rri8, X86::SHRD16mri8 }, 189 { X86::SHRD32rrCL, X86::SHRD32mrCL }, 190 { X86::SHRD32rri8, X86::SHRD32mri8 }, 191 { X86::SHRD64rrCL, X86::SHRD64mrCL }, 192 { X86::SHRD64rri8, X86::SHRD64mri8 }, 193 { X86::SUB16ri, X86::SUB16mi }, 194 { X86::SUB16ri8, X86::SUB16mi8 }, 195 { X86::SUB16rr, X86::SUB16mr }, 196 { X86::SUB32ri, X86::SUB32mi }, 197 { X86::SUB32ri8, X86::SUB32mi8 }, 198 { X86::SUB32rr, X86::SUB32mr }, 199 { X86::SUB64ri32, X86::SUB64mi32 }, 200 { X86::SUB64ri8, X86::SUB64mi8 }, 201 { X86::SUB64rr, X86::SUB64mr }, 202 { X86::SUB8ri, X86::SUB8mi }, 203 { X86::SUB8rr, X86::SUB8mr }, 204 { X86::XOR16ri, X86::XOR16mi }, 205 { X86::XOR16ri8, X86::XOR16mi8 }, 206 { X86::XOR16rr, X86::XOR16mr }, 207 { X86::XOR32ri, X86::XOR32mi }, 208 { X86::XOR32ri8, X86::XOR32mi8 }, 209 { X86::XOR32rr, X86::XOR32mr }, 210 { X86::XOR64ri32, X86::XOR64mi32 }, 211 { X86::XOR64ri8, X86::XOR64mi8 }, 212 { X86::XOR64rr, X86::XOR64mr }, 213 { X86::XOR8ri, X86::XOR8mi }, 214 { X86::XOR8rr, X86::XOR8mr } 215 }; 216 217 for (unsigned i = 0, e = array_lengthof(OpTbl2Addr); i != e; ++i) { 218 unsigned RegOp = OpTbl2Addr[i][0]; 219 unsigned MemOp = OpTbl2Addr[i][1]; 220 if (!RegOp2MemOpTable2Addr.insert(std::make_pair((unsigned*)RegOp, 221 std::make_pair(MemOp,0))).second) 222 assert(false && "Duplicated entries?"); 223 // Index 0, folded load and store, no alignment requirement. 224 unsigned AuxInfo = 0 | (1 << 4) | (1 << 5); 225 if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp, 226 std::make_pair(RegOp, 227 AuxInfo))).second) 228 AmbEntries.push_back(MemOp); 229 } 230 231 // If the third value is 1, then it's folding either a load or a store. 232 static const unsigned OpTbl0[][4] = { 233 { X86::BT16ri8, X86::BT16mi8, 1, 0 }, 234 { X86::BT32ri8, X86::BT32mi8, 1, 0 }, 235 { X86::BT64ri8, X86::BT64mi8, 1, 0 }, 236 { X86::CALL32r, X86::CALL32m, 1, 0 }, 237 { X86::CALL64r, X86::CALL64m, 1, 0 }, 238 { X86::CMP16ri, X86::CMP16mi, 1, 0 }, 239 { X86::CMP16ri8, X86::CMP16mi8, 1, 0 }, 240 { X86::CMP16rr, X86::CMP16mr, 1, 0 }, 241 { X86::CMP32ri, X86::CMP32mi, 1, 0 }, 242 { X86::CMP32ri8, X86::CMP32mi8, 1, 0 }, 243 { X86::CMP32rr, X86::CMP32mr, 1, 0 }, 244 { X86::CMP64ri32, X86::CMP64mi32, 1, 0 }, 245 { X86::CMP64ri8, X86::CMP64mi8, 1, 0 }, 246 { X86::CMP64rr, X86::CMP64mr, 1, 0 }, 247 { X86::CMP8ri, X86::CMP8mi, 1, 0 }, 248 { X86::CMP8rr, X86::CMP8mr, 1, 0 }, 249 { X86::DIV16r, X86::DIV16m, 1, 0 }, 250 { X86::DIV32r, X86::DIV32m, 1, 0 }, 251 { X86::DIV64r, X86::DIV64m, 1, 0 }, 252 { X86::DIV8r, X86::DIV8m, 1, 0 }, 253 { X86::EXTRACTPSrr, X86::EXTRACTPSmr, 0, 16 }, 254 { X86::FsMOVAPDrr, X86::MOVSDmr, 0, 0 }, 255 { X86::FsMOVAPSrr, X86::MOVSSmr, 0, 0 }, 256 { X86::IDIV16r, X86::IDIV16m, 1, 0 }, 257 { X86::IDIV32r, X86::IDIV32m, 1, 0 }, 258 { X86::IDIV64r, X86::IDIV64m, 1, 0 }, 259 { X86::IDIV8r, X86::IDIV8m, 1, 0 }, 260 { X86::IMUL16r, X86::IMUL16m, 1, 0 }, 261 { X86::IMUL32r, X86::IMUL32m, 1, 0 }, 262 { X86::IMUL64r, X86::IMUL64m, 1, 0 }, 263 { X86::IMUL8r, X86::IMUL8m, 1, 0 }, 264 { X86::JMP32r, X86::JMP32m, 1, 0 }, 265 { X86::JMP64r, X86::JMP64m, 1, 0 }, 266 { X86::MOV16ri, X86::MOV16mi, 0, 0 }, 267 { X86::MOV16rr, X86::MOV16mr, 0, 0 }, 268 { X86::MOV32ri, X86::MOV32mi, 0, 0 }, 269 { X86::MOV32rr, X86::MOV32mr, 0, 0 }, 270 { X86::MOV32rr_TC, X86::MOV32mr_TC, 0, 0 }, 271 { X86::MOV64ri32, X86::MOV64mi32, 0, 0 }, 272 { X86::MOV64rr, X86::MOV64mr, 0, 0 }, 273 { X86::MOV8ri, X86::MOV8mi, 0, 0 }, 274 { X86::MOV8rr, X86::MOV8mr, 0, 0 }, 275 { X86::MOV8rr_NOREX, X86::MOV8mr_NOREX, 0, 0 }, 276 { X86::MOVAPDrr, X86::MOVAPDmr, 0, 16 }, 277 { X86::MOVAPSrr, X86::MOVAPSmr, 0, 16 }, 278 { X86::MOVDQArr, X86::MOVDQAmr, 0, 16 }, 279 { X86::MOVPDI2DIrr, X86::MOVPDI2DImr, 0, 0 }, 280 { X86::MOVPQIto64rr,X86::MOVPQI2QImr, 0, 0 }, 281 { X86::MOVSDto64rr, X86::MOVSDto64mr, 0, 0 }, 282 { X86::MOVSS2DIrr, X86::MOVSS2DImr, 0, 0 }, 283 { X86::MOVUPDrr, X86::MOVUPDmr, 0, 0 }, 284 { X86::MOVUPSrr, X86::MOVUPSmr, 0, 0 }, 285 { X86::MUL16r, X86::MUL16m, 1, 0 }, 286 { X86::MUL32r, X86::MUL32m, 1, 0 }, 287 { X86::MUL64r, X86::MUL64m, 1, 0 }, 288 { X86::MUL8r, X86::MUL8m, 1, 0 }, 289 { X86::SETAEr, X86::SETAEm, 0, 0 }, 290 { X86::SETAr, X86::SETAm, 0, 0 }, 291 { X86::SETBEr, X86::SETBEm, 0, 0 }, 292 { X86::SETBr, X86::SETBm, 0, 0 }, 293 { X86::SETEr, X86::SETEm, 0, 0 }, 294 { X86::SETGEr, X86::SETGEm, 0, 0 }, 295 { X86::SETGr, X86::SETGm, 0, 0 }, 296 { X86::SETLEr, X86::SETLEm, 0, 0 }, 297 { X86::SETLr, X86::SETLm, 0, 0 }, 298 { X86::SETNEr, X86::SETNEm, 0, 0 }, 299 { X86::SETNOr, X86::SETNOm, 0, 0 }, 300 { X86::SETNPr, X86::SETNPm, 0, 0 }, 301 { X86::SETNSr, X86::SETNSm, 0, 0 }, 302 { X86::SETOr, X86::SETOm, 0, 0 }, 303 { X86::SETPr, X86::SETPm, 0, 0 }, 304 { X86::SETSr, X86::SETSm, 0, 0 }, 305 { X86::TAILJMPr, X86::TAILJMPm, 1, 0 }, 306 { X86::TAILJMPr64, X86::TAILJMPm64, 1, 0 }, 307 { X86::TEST16ri, X86::TEST16mi, 1, 0 }, 308 { X86::TEST32ri, X86::TEST32mi, 1, 0 }, 309 { X86::TEST64ri32, X86::TEST64mi32, 1, 0 }, 310 { X86::TEST8ri, X86::TEST8mi, 1, 0 } 311 }; 312 313 for (unsigned i = 0, e = array_lengthof(OpTbl0); i != e; ++i) { 314 unsigned RegOp = OpTbl0[i][0]; 315 unsigned MemOp = OpTbl0[i][1]; 316 unsigned Align = OpTbl0[i][3]; 317 if (!RegOp2MemOpTable0.insert(std::make_pair((unsigned*)RegOp, 318 std::make_pair(MemOp,Align))).second) 319 assert(false && "Duplicated entries?"); 320 unsigned FoldedLoad = OpTbl0[i][2]; 321 // Index 0, folded load or store. 322 unsigned AuxInfo = 0 | (FoldedLoad << 4) | ((FoldedLoad^1) << 5); 323 if (RegOp != X86::FsMOVAPDrr && RegOp != X86::FsMOVAPSrr) 324 if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp, 325 std::make_pair(RegOp, AuxInfo))).second) 326 AmbEntries.push_back(MemOp); 327 } 328 329 static const unsigned OpTbl1[][3] = { 330 { X86::CMP16rr, X86::CMP16rm, 0 }, 331 { X86::CMP32rr, X86::CMP32rm, 0 }, 332 { X86::CMP64rr, X86::CMP64rm, 0 }, 333 { X86::CMP8rr, X86::CMP8rm, 0 }, 334 { X86::CVTSD2SSrr, X86::CVTSD2SSrm, 0 }, 335 { X86::CVTSI2SD64rr, X86::CVTSI2SD64rm, 0 }, 336 { X86::CVTSI2SDrr, X86::CVTSI2SDrm, 0 }, 337 { X86::CVTSI2SS64rr, X86::CVTSI2SS64rm, 0 }, 338 { X86::CVTSI2SSrr, X86::CVTSI2SSrm, 0 }, 339 { X86::CVTSS2SDrr, X86::CVTSS2SDrm, 0 }, 340 { X86::CVTTSD2SI64rr, X86::CVTTSD2SI64rm, 0 }, 341 { X86::CVTTSD2SIrr, X86::CVTTSD2SIrm, 0 }, 342 { X86::CVTTSS2SI64rr, X86::CVTTSS2SI64rm, 0 }, 343 { X86::CVTTSS2SIrr, X86::CVTTSS2SIrm, 0 }, 344 { X86::FsMOVAPDrr, X86::MOVSDrm, 0 }, 345 { X86::FsMOVAPSrr, X86::MOVSSrm, 0 }, 346 { X86::IMUL16rri, X86::IMUL16rmi, 0 }, 347 { X86::IMUL16rri8, X86::IMUL16rmi8, 0 }, 348 { X86::IMUL32rri, X86::IMUL32rmi, 0 }, 349 { X86::IMUL32rri8, X86::IMUL32rmi8, 0 }, 350 { X86::IMUL64rri32, X86::IMUL64rmi32, 0 }, 351 { X86::IMUL64rri8, X86::IMUL64rmi8, 0 }, 352 { X86::Int_CMPSDrr, X86::Int_CMPSDrm, 0 }, 353 { X86::Int_CMPSSrr, X86::Int_CMPSSrm, 0 }, 354 { X86::Int_COMISDrr, X86::Int_COMISDrm, 0 }, 355 { X86::Int_COMISSrr, X86::Int_COMISSrm, 0 }, 356 { X86::Int_CVTDQ2PDrr, X86::Int_CVTDQ2PDrm, 16 }, 357 { X86::Int_CVTDQ2PSrr, X86::Int_CVTDQ2PSrm, 16 }, 358 { X86::Int_CVTPD2DQrr, X86::Int_CVTPD2DQrm, 16 }, 359 { X86::Int_CVTPD2PSrr, X86::Int_CVTPD2PSrm, 16 }, 360 { X86::Int_CVTPS2DQrr, X86::Int_CVTPS2DQrm, 16 }, 361 { X86::Int_CVTPS2PDrr, X86::Int_CVTPS2PDrm, 0 }, 362 { X86::Int_CVTSD2SI64rr,X86::Int_CVTSD2SI64rm, 0 }, 363 { X86::Int_CVTSD2SIrr, X86::Int_CVTSD2SIrm, 0 }, 364 { X86::Int_CVTSD2SSrr, X86::Int_CVTSD2SSrm, 0 }, 365 { X86::Int_CVTSI2SD64rr,X86::Int_CVTSI2SD64rm, 0 }, 366 { X86::Int_CVTSI2SDrr, X86::Int_CVTSI2SDrm, 0 }, 367 { X86::Int_CVTSI2SS64rr,X86::Int_CVTSI2SS64rm, 0 }, 368 { X86::Int_CVTSI2SSrr, X86::Int_CVTSI2SSrm, 0 }, 369 { X86::Int_CVTSS2SDrr, X86::Int_CVTSS2SDrm, 0 }, 370 { X86::Int_CVTSS2SI64rr,X86::Int_CVTSS2SI64rm, 0 }, 371 { X86::Int_CVTSS2SIrr, X86::Int_CVTSS2SIrm, 0 }, 372 { X86::Int_CVTTPD2DQrr, X86::Int_CVTTPD2DQrm, 16 }, 373 { X86::Int_CVTTPS2DQrr, X86::Int_CVTTPS2DQrm, 16 }, 374 { X86::Int_CVTTSD2SI64rr,X86::Int_CVTTSD2SI64rm, 0 }, 375 { X86::Int_CVTTSD2SIrr, X86::Int_CVTTSD2SIrm, 0 }, 376 { X86::Int_CVTTSS2SI64rr,X86::Int_CVTTSS2SI64rm, 0 }, 377 { X86::Int_CVTTSS2SIrr, X86::Int_CVTTSS2SIrm, 0 }, 378 { X86::Int_UCOMISDrr, X86::Int_UCOMISDrm, 0 }, 379 { X86::Int_UCOMISSrr, X86::Int_UCOMISSrm, 0 }, 380 { X86::MOV16rr, X86::MOV16rm, 0 }, 381 { X86::MOV32rr, X86::MOV32rm, 0 }, 382 { X86::MOV32rr_TC, X86::MOV32rm_TC, 0 }, 383 { X86::MOV64rr, X86::MOV64rm, 0 }, 384 { X86::MOV64toPQIrr, X86::MOVQI2PQIrm, 0 }, 385 { X86::MOV64toSDrr, X86::MOV64toSDrm, 0 }, 386 { X86::MOV8rr, X86::MOV8rm, 0 }, 387 { X86::MOVAPDrr, X86::MOVAPDrm, 16 }, 388 { X86::MOVAPSrr, X86::MOVAPSrm, 16 }, 389 { X86::MOVDDUPrr, X86::MOVDDUPrm, 0 }, 390 { X86::MOVDI2PDIrr, X86::MOVDI2PDIrm, 0 }, 391 { X86::MOVDI2SSrr, X86::MOVDI2SSrm, 0 }, 392 { X86::MOVDQArr, X86::MOVDQArm, 16 }, 393 { X86::MOVSHDUPrr, X86::MOVSHDUPrm, 16 }, 394 { X86::MOVSLDUPrr, X86::MOVSLDUPrm, 16 }, 395 { X86::MOVSX16rr8, X86::MOVSX16rm8, 0 }, 396 { X86::MOVSX32rr16, X86::MOVSX32rm16, 0 }, 397 { X86::MOVSX32rr8, X86::MOVSX32rm8, 0 }, 398 { X86::MOVSX64rr16, X86::MOVSX64rm16, 0 }, 399 { X86::MOVSX64rr32, X86::MOVSX64rm32, 0 }, 400 { X86::MOVSX64rr8, X86::MOVSX64rm8, 0 }, 401 { X86::MOVUPDrr, X86::MOVUPDrm, 16 }, 402 { X86::MOVUPSrr, X86::MOVUPSrm, 0 }, 403 { X86::MOVZDI2PDIrr, X86::MOVZDI2PDIrm, 0 }, 404 { X86::MOVZQI2PQIrr, X86::MOVZQI2PQIrm, 0 }, 405 { X86::MOVZPQILo2PQIrr, X86::MOVZPQILo2PQIrm, 16 }, 406 { X86::MOVZX16rr8, X86::MOVZX16rm8, 0 }, 407 { X86::MOVZX32rr16, X86::MOVZX32rm16, 0 }, 408 { X86::MOVZX32_NOREXrr8, X86::MOVZX32_NOREXrm8, 0 }, 409 { X86::MOVZX32rr8, X86::MOVZX32rm8, 0 }, 410 { X86::MOVZX64rr16, X86::MOVZX64rm16, 0 }, 411 { X86::MOVZX64rr32, X86::MOVZX64rm32, 0 }, 412 { X86::MOVZX64rr8, X86::MOVZX64rm8, 0 }, 413 { X86::PSHUFDri, X86::PSHUFDmi, 16 }, 414 { X86::PSHUFHWri, X86::PSHUFHWmi, 16 }, 415 { X86::PSHUFLWri, X86::PSHUFLWmi, 16 }, 416 { X86::RCPPSr, X86::RCPPSm, 16 }, 417 { X86::RCPPSr_Int, X86::RCPPSm_Int, 16 }, 418 { X86::RSQRTPSr, X86::RSQRTPSm, 16 }, 419 { X86::RSQRTPSr_Int, X86::RSQRTPSm_Int, 16 }, 420 { X86::RSQRTSSr, X86::RSQRTSSm, 0 }, 421 { X86::RSQRTSSr_Int, X86::RSQRTSSm_Int, 0 }, 422 { X86::SQRTPDr, X86::SQRTPDm, 16 }, 423 { X86::SQRTPDr_Int, X86::SQRTPDm_Int, 16 }, 424 { X86::SQRTPSr, X86::SQRTPSm, 16 }, 425 { X86::SQRTPSr_Int, X86::SQRTPSm_Int, 16 }, 426 { X86::SQRTSDr, X86::SQRTSDm, 0 }, 427 { X86::SQRTSDr_Int, X86::SQRTSDm_Int, 0 }, 428 { X86::SQRTSSr, X86::SQRTSSm, 0 }, 429 { X86::SQRTSSr_Int, X86::SQRTSSm_Int, 0 }, 430 { X86::TEST16rr, X86::TEST16rm, 0 }, 431 { X86::TEST32rr, X86::TEST32rm, 0 }, 432 { X86::TEST64rr, X86::TEST64rm, 0 }, 433 { X86::TEST8rr, X86::TEST8rm, 0 }, 434 // FIXME: TEST*rr EAX,EAX ---> CMP [mem], 0 435 { X86::UCOMISDrr, X86::UCOMISDrm, 0 }, 436 { X86::UCOMISSrr, X86::UCOMISSrm, 0 } 437 }; 438 439 for (unsigned i = 0, e = array_lengthof(OpTbl1); i != e; ++i) { 440 unsigned RegOp = OpTbl1[i][0]; 441 unsigned MemOp = OpTbl1[i][1]; 442 unsigned Align = OpTbl1[i][2]; 443 if (!RegOp2MemOpTable1.insert(std::make_pair((unsigned*)RegOp, 444 std::make_pair(MemOp,Align))).second) 445 assert(false && "Duplicated entries?"); 446 // Index 1, folded load 447 unsigned AuxInfo = 1 | (1 << 4); 448 if (RegOp != X86::FsMOVAPDrr && RegOp != X86::FsMOVAPSrr) 449 if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp, 450 std::make_pair(RegOp, AuxInfo))).second) 451 AmbEntries.push_back(MemOp); 452 } 453 454 static const unsigned OpTbl2[][3] = { 455 { X86::ADC32rr, X86::ADC32rm, 0 }, 456 { X86::ADC64rr, X86::ADC64rm, 0 }, 457 { X86::ADD16rr, X86::ADD16rm, 0 }, 458 { X86::ADD32rr, X86::ADD32rm, 0 }, 459 { X86::ADD64rr, X86::ADD64rm, 0 }, 460 { X86::ADD8rr, X86::ADD8rm, 0 }, 461 { X86::ADDPDrr, X86::ADDPDrm, 16 }, 462 { X86::ADDPSrr, X86::ADDPSrm, 16 }, 463 { X86::ADDSDrr, X86::ADDSDrm, 0 }, 464 { X86::ADDSSrr, X86::ADDSSrm, 0 }, 465 { X86::ADDSUBPDrr, X86::ADDSUBPDrm, 16 }, 466 { X86::ADDSUBPSrr, X86::ADDSUBPSrm, 16 }, 467 { X86::AND16rr, X86::AND16rm, 0 }, 468 { X86::AND32rr, X86::AND32rm, 0 }, 469 { X86::AND64rr, X86::AND64rm, 0 }, 470 { X86::AND8rr, X86::AND8rm, 0 }, 471 { X86::ANDNPDrr, X86::ANDNPDrm, 16 }, 472 { X86::ANDNPSrr, X86::ANDNPSrm, 16 }, 473 { X86::ANDPDrr, X86::ANDPDrm, 16 }, 474 { X86::ANDPSrr, X86::ANDPSrm, 16 }, 475 { X86::CMOVA16rr, X86::CMOVA16rm, 0 }, 476 { X86::CMOVA32rr, X86::CMOVA32rm, 0 }, 477 { X86::CMOVA64rr, X86::CMOVA64rm, 0 }, 478 { X86::CMOVAE16rr, X86::CMOVAE16rm, 0 }, 479 { X86::CMOVAE32rr, X86::CMOVAE32rm, 0 }, 480 { X86::CMOVAE64rr, X86::CMOVAE64rm, 0 }, 481 { X86::CMOVB16rr, X86::CMOVB16rm, 0 }, 482 { X86::CMOVB32rr, X86::CMOVB32rm, 0 }, 483 { X86::CMOVB64rr, X86::CMOVB64rm, 0 }, 484 { X86::CMOVBE16rr, X86::CMOVBE16rm, 0 }, 485 { X86::CMOVBE32rr, X86::CMOVBE32rm, 0 }, 486 { X86::CMOVBE64rr, X86::CMOVBE64rm, 0 }, 487 { X86::CMOVE16rr, X86::CMOVE16rm, 0 }, 488 { X86::CMOVE32rr, X86::CMOVE32rm, 0 }, 489 { X86::CMOVE64rr, X86::CMOVE64rm, 0 }, 490 { X86::CMOVG16rr, X86::CMOVG16rm, 0 }, 491 { X86::CMOVG32rr, X86::CMOVG32rm, 0 }, 492 { X86::CMOVG64rr, X86::CMOVG64rm, 0 }, 493 { X86::CMOVGE16rr, X86::CMOVGE16rm, 0 }, 494 { X86::CMOVGE32rr, X86::CMOVGE32rm, 0 }, 495 { X86::CMOVGE64rr, X86::CMOVGE64rm, 0 }, 496 { X86::CMOVL16rr, X86::CMOVL16rm, 0 }, 497 { X86::CMOVL32rr, X86::CMOVL32rm, 0 }, 498 { X86::CMOVL64rr, X86::CMOVL64rm, 0 }, 499 { X86::CMOVLE16rr, X86::CMOVLE16rm, 0 }, 500 { X86::CMOVLE32rr, X86::CMOVLE32rm, 0 }, 501 { X86::CMOVLE64rr, X86::CMOVLE64rm, 0 }, 502 { X86::CMOVNE16rr, X86::CMOVNE16rm, 0 }, 503 { X86::CMOVNE32rr, X86::CMOVNE32rm, 0 }, 504 { X86::CMOVNE64rr, X86::CMOVNE64rm, 0 }, 505 { X86::CMOVNO16rr, X86::CMOVNO16rm, 0 }, 506 { X86::CMOVNO32rr, X86::CMOVNO32rm, 0 }, 507 { X86::CMOVNO64rr, X86::CMOVNO64rm, 0 }, 508 { X86::CMOVNP16rr, X86::CMOVNP16rm, 0 }, 509 { X86::CMOVNP32rr, X86::CMOVNP32rm, 0 }, 510 { X86::CMOVNP64rr, X86::CMOVNP64rm, 0 }, 511 { X86::CMOVNS16rr, X86::CMOVNS16rm, 0 }, 512 { X86::CMOVNS32rr, X86::CMOVNS32rm, 0 }, 513 { X86::CMOVNS64rr, X86::CMOVNS64rm, 0 }, 514 { X86::CMOVO16rr, X86::CMOVO16rm, 0 }, 515 { X86::CMOVO32rr, X86::CMOVO32rm, 0 }, 516 { X86::CMOVO64rr, X86::CMOVO64rm, 0 }, 517 { X86::CMOVP16rr, X86::CMOVP16rm, 0 }, 518 { X86::CMOVP32rr, X86::CMOVP32rm, 0 }, 519 { X86::CMOVP64rr, X86::CMOVP64rm, 0 }, 520 { X86::CMOVS16rr, X86::CMOVS16rm, 0 }, 521 { X86::CMOVS32rr, X86::CMOVS32rm, 0 }, 522 { X86::CMOVS64rr, X86::CMOVS64rm, 0 }, 523 { X86::CMPPDrri, X86::CMPPDrmi, 16 }, 524 { X86::CMPPSrri, X86::CMPPSrmi, 16 }, 525 { X86::CMPSDrr, X86::CMPSDrm, 0 }, 526 { X86::CMPSSrr, X86::CMPSSrm, 0 }, 527 { X86::DIVPDrr, X86::DIVPDrm, 16 }, 528 { X86::DIVPSrr, X86::DIVPSrm, 16 }, 529 { X86::DIVSDrr, X86::DIVSDrm, 0 }, 530 { X86::DIVSSrr, X86::DIVSSrm, 0 }, 531 { X86::FsANDNPDrr, X86::FsANDNPDrm, 16 }, 532 { X86::FsANDNPSrr, X86::FsANDNPSrm, 16 }, 533 { X86::FsANDPDrr, X86::FsANDPDrm, 16 }, 534 { X86::FsANDPSrr, X86::FsANDPSrm, 16 }, 535 { X86::FsORPDrr, X86::FsORPDrm, 16 }, 536 { X86::FsORPSrr, X86::FsORPSrm, 16 }, 537 { X86::FsXORPDrr, X86::FsXORPDrm, 16 }, 538 { X86::FsXORPSrr, X86::FsXORPSrm, 16 }, 539 { X86::HADDPDrr, X86::HADDPDrm, 16 }, 540 { X86::HADDPSrr, X86::HADDPSrm, 16 }, 541 { X86::HSUBPDrr, X86::HSUBPDrm, 16 }, 542 { X86::HSUBPSrr, X86::HSUBPSrm, 16 }, 543 { X86::IMUL16rr, X86::IMUL16rm, 0 }, 544 { X86::IMUL32rr, X86::IMUL32rm, 0 }, 545 { X86::IMUL64rr, X86::IMUL64rm, 0 }, 546 { X86::MAXPDrr, X86::MAXPDrm, 16 }, 547 { X86::MAXPDrr_Int, X86::MAXPDrm_Int, 16 }, 548 { X86::MAXPSrr, X86::MAXPSrm, 16 }, 549 { X86::MAXPSrr_Int, X86::MAXPSrm_Int, 16 }, 550 { X86::MAXSDrr, X86::MAXSDrm, 0 }, 551 { X86::MAXSDrr_Int, X86::MAXSDrm_Int, 0 }, 552 { X86::MAXSSrr, X86::MAXSSrm, 0 }, 553 { X86::MAXSSrr_Int, X86::MAXSSrm_Int, 0 }, 554 { X86::MINPDrr, X86::MINPDrm, 16 }, 555 { X86::MINPDrr_Int, X86::MINPDrm_Int, 16 }, 556 { X86::MINPSrr, X86::MINPSrm, 16 }, 557 { X86::MINPSrr_Int, X86::MINPSrm_Int, 16 }, 558 { X86::MINSDrr, X86::MINSDrm, 0 }, 559 { X86::MINSDrr_Int, X86::MINSDrm_Int, 0 }, 560 { X86::MINSSrr, X86::MINSSrm, 0 }, 561 { X86::MINSSrr_Int, X86::MINSSrm_Int, 0 }, 562 { X86::MULPDrr, X86::MULPDrm, 16 }, 563 { X86::MULPSrr, X86::MULPSrm, 16 }, 564 { X86::MULSDrr, X86::MULSDrm, 0 }, 565 { X86::MULSSrr, X86::MULSSrm, 0 }, 566 { X86::OR16rr, X86::OR16rm, 0 }, 567 { X86::OR32rr, X86::OR32rm, 0 }, 568 { X86::OR64rr, X86::OR64rm, 0 }, 569 { X86::OR8rr, X86::OR8rm, 0 }, 570 { X86::ORPDrr, X86::ORPDrm, 16 }, 571 { X86::ORPSrr, X86::ORPSrm, 16 }, 572 { X86::PACKSSDWrr, X86::PACKSSDWrm, 16 }, 573 { X86::PACKSSWBrr, X86::PACKSSWBrm, 16 }, 574 { X86::PACKUSWBrr, X86::PACKUSWBrm, 16 }, 575 { X86::PADDBrr, X86::PADDBrm, 16 }, 576 { X86::PADDDrr, X86::PADDDrm, 16 }, 577 { X86::PADDQrr, X86::PADDQrm, 16 }, 578 { X86::PADDSBrr, X86::PADDSBrm, 16 }, 579 { X86::PADDSWrr, X86::PADDSWrm, 16 }, 580 { X86::PADDWrr, X86::PADDWrm, 16 }, 581 { X86::PANDNrr, X86::PANDNrm, 16 }, 582 { X86::PANDrr, X86::PANDrm, 16 }, 583 { X86::PAVGBrr, X86::PAVGBrm, 16 }, 584 { X86::PAVGWrr, X86::PAVGWrm, 16 }, 585 { X86::PCMPEQBrr, X86::PCMPEQBrm, 16 }, 586 { X86::PCMPEQDrr, X86::PCMPEQDrm, 16 }, 587 { X86::PCMPEQWrr, X86::PCMPEQWrm, 16 }, 588 { X86::PCMPGTBrr, X86::PCMPGTBrm, 16 }, 589 { X86::PCMPGTDrr, X86::PCMPGTDrm, 16 }, 590 { X86::PCMPGTWrr, X86::PCMPGTWrm, 16 }, 591 { X86::PINSRWrri, X86::PINSRWrmi, 16 }, 592 { X86::PMADDWDrr, X86::PMADDWDrm, 16 }, 593 { X86::PMAXSWrr, X86::PMAXSWrm, 16 }, 594 { X86::PMAXUBrr, X86::PMAXUBrm, 16 }, 595 { X86::PMINSWrr, X86::PMINSWrm, 16 }, 596 { X86::PMINUBrr, X86::PMINUBrm, 16 }, 597 { X86::PMULDQrr, X86::PMULDQrm, 16 }, 598 { X86::PMULHUWrr, X86::PMULHUWrm, 16 }, 599 { X86::PMULHWrr, X86::PMULHWrm, 16 }, 600 { X86::PMULLDrr, X86::PMULLDrm, 16 }, 601 { X86::PMULLWrr, X86::PMULLWrm, 16 }, 602 { X86::PMULUDQrr, X86::PMULUDQrm, 16 }, 603 { X86::PORrr, X86::PORrm, 16 }, 604 { X86::PSADBWrr, X86::PSADBWrm, 16 }, 605 { X86::PSLLDrr, X86::PSLLDrm, 16 }, 606 { X86::PSLLQrr, X86::PSLLQrm, 16 }, 607 { X86::PSLLWrr, X86::PSLLWrm, 16 }, 608 { X86::PSRADrr, X86::PSRADrm, 16 }, 609 { X86::PSRAWrr, X86::PSRAWrm, 16 }, 610 { X86::PSRLDrr, X86::PSRLDrm, 16 }, 611 { X86::PSRLQrr, X86::PSRLQrm, 16 }, 612 { X86::PSRLWrr, X86::PSRLWrm, 16 }, 613 { X86::PSUBBrr, X86::PSUBBrm, 16 }, 614 { X86::PSUBDrr, X86::PSUBDrm, 16 }, 615 { X86::PSUBSBrr, X86::PSUBSBrm, 16 }, 616 { X86::PSUBSWrr, X86::PSUBSWrm, 16 }, 617 { X86::PSUBWrr, X86::PSUBWrm, 16 }, 618 { X86::PUNPCKHBWrr, X86::PUNPCKHBWrm, 16 }, 619 { X86::PUNPCKHDQrr, X86::PUNPCKHDQrm, 16 }, 620 { X86::PUNPCKHQDQrr, X86::PUNPCKHQDQrm, 16 }, 621 { X86::PUNPCKHWDrr, X86::PUNPCKHWDrm, 16 }, 622 { X86::PUNPCKLBWrr, X86::PUNPCKLBWrm, 16 }, 623 { X86::PUNPCKLDQrr, X86::PUNPCKLDQrm, 16 }, 624 { X86::PUNPCKLQDQrr, X86::PUNPCKLQDQrm, 16 }, 625 { X86::PUNPCKLWDrr, X86::PUNPCKLWDrm, 16 }, 626 { X86::PXORrr, X86::PXORrm, 16 }, 627 { X86::SBB32rr, X86::SBB32rm, 0 }, 628 { X86::SBB64rr, X86::SBB64rm, 0 }, 629 { X86::SHUFPDrri, X86::SHUFPDrmi, 16 }, 630 { X86::SHUFPSrri, X86::SHUFPSrmi, 16 }, 631 { X86::SUB16rr, X86::SUB16rm, 0 }, 632 { X86::SUB32rr, X86::SUB32rm, 0 }, 633 { X86::SUB64rr, X86::SUB64rm, 0 }, 634 { X86::SUB8rr, X86::SUB8rm, 0 }, 635 { X86::SUBPDrr, X86::SUBPDrm, 16 }, 636 { X86::SUBPSrr, X86::SUBPSrm, 16 }, 637 { X86::SUBSDrr, X86::SUBSDrm, 0 }, 638 { X86::SUBSSrr, X86::SUBSSrm, 0 }, 639 // FIXME: TEST*rr -> swapped operand of TEST*mr. 640 { X86::UNPCKHPDrr, X86::UNPCKHPDrm, 16 }, 641 { X86::UNPCKHPSrr, X86::UNPCKHPSrm, 16 }, 642 { X86::UNPCKLPDrr, X86::UNPCKLPDrm, 16 }, 643 { X86::UNPCKLPSrr, X86::UNPCKLPSrm, 16 }, 644 { X86::XOR16rr, X86::XOR16rm, 0 }, 645 { X86::XOR32rr, X86::XOR32rm, 0 }, 646 { X86::XOR64rr, X86::XOR64rm, 0 }, 647 { X86::XOR8rr, X86::XOR8rm, 0 }, 648 { X86::XORPDrr, X86::XORPDrm, 16 }, 649 { X86::XORPSrr, X86::XORPSrm, 16 } 650 }; 651 652 for (unsigned i = 0, e = array_lengthof(OpTbl2); i != e; ++i) { 653 unsigned RegOp = OpTbl2[i][0]; 654 unsigned MemOp = OpTbl2[i][1]; 655 unsigned Align = OpTbl2[i][2]; 656 if (!RegOp2MemOpTable2.insert(std::make_pair((unsigned*)RegOp, 657 std::make_pair(MemOp,Align))).second) 658 assert(false && "Duplicated entries?"); 659 // Index 2, folded load 660 unsigned AuxInfo = 2 | (1 << 4); 661 if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp, 662 std::make_pair(RegOp, AuxInfo))).second) 663 AmbEntries.push_back(MemOp); 664 } 665 666 // Remove ambiguous entries. 667 assert(AmbEntries.empty() && "Duplicated entries in unfolding maps?"); 668} 669 670bool X86InstrInfo::isMoveInstr(const MachineInstr& MI, 671 unsigned &SrcReg, unsigned &DstReg, 672 unsigned &SrcSubIdx, unsigned &DstSubIdx) const { 673 switch (MI.getOpcode()) { 674 default: 675 return false; 676 case X86::MOV8rr: 677 case X86::MOV8rr_NOREX: 678 case X86::MOV16rr: 679 case X86::MOV32rr: 680 case X86::MOV64rr: 681 case X86::MOV32rr_TC: 682 case X86::MOV64rr_TC: 683 684 // FP Stack register class copies 685 case X86::MOV_Fp3232: case X86::MOV_Fp6464: case X86::MOV_Fp8080: 686 case X86::MOV_Fp3264: case X86::MOV_Fp3280: 687 case X86::MOV_Fp6432: case X86::MOV_Fp8032: 688 689 // Note that MOVSSrr and MOVSDrr are not considered copies. FR32 and FR64 690 // copies are done with FsMOVAPSrr and FsMOVAPDrr. 691 692 case X86::FsMOVAPSrr: 693 case X86::FsMOVAPDrr: 694 case X86::MOVAPSrr: 695 case X86::MOVAPDrr: 696 case X86::MOVDQArr: 697 case X86::MMX_MOVQ64rr: 698 assert(MI.getNumOperands() >= 2 && 699 MI.getOperand(0).isReg() && 700 MI.getOperand(1).isReg() && 701 "invalid register-register move instruction"); 702 SrcReg = MI.getOperand(1).getReg(); 703 DstReg = MI.getOperand(0).getReg(); 704 SrcSubIdx = MI.getOperand(1).getSubReg(); 705 DstSubIdx = MI.getOperand(0).getSubReg(); 706 return true; 707 } 708} 709 710bool 711X86InstrInfo::isCoalescableExtInstr(const MachineInstr &MI, 712 unsigned &SrcReg, unsigned &DstReg, 713 unsigned &SubIdx) const { 714 switch (MI.getOpcode()) { 715 default: break; 716 case X86::MOVSX16rr8: 717 case X86::MOVZX16rr8: 718 case X86::MOVSX32rr8: 719 case X86::MOVZX32rr8: 720 case X86::MOVSX64rr8: 721 case X86::MOVZX64rr8: 722 if (!TM.getSubtarget<X86Subtarget>().is64Bit()) 723 // It's not always legal to reference the low 8-bit of the larger 724 // register in 32-bit mode. 725 return false; 726 case X86::MOVSX32rr16: 727 case X86::MOVZX32rr16: 728 case X86::MOVSX64rr16: 729 case X86::MOVZX64rr16: 730 case X86::MOVSX64rr32: 731 case X86::MOVZX64rr32: { 732 if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg()) 733 // Be conservative. 734 return false; 735 SrcReg = MI.getOperand(1).getReg(); 736 DstReg = MI.getOperand(0).getReg(); 737 switch (MI.getOpcode()) { 738 default: 739 llvm_unreachable(0); 740 break; 741 case X86::MOVSX16rr8: 742 case X86::MOVZX16rr8: 743 case X86::MOVSX32rr8: 744 case X86::MOVZX32rr8: 745 case X86::MOVSX64rr8: 746 case X86::MOVZX64rr8: 747 SubIdx = X86::sub_8bit; 748 break; 749 case X86::MOVSX32rr16: 750 case X86::MOVZX32rr16: 751 case X86::MOVSX64rr16: 752 case X86::MOVZX64rr16: 753 SubIdx = X86::sub_16bit; 754 break; 755 case X86::MOVSX64rr32: 756 case X86::MOVZX64rr32: 757 SubIdx = X86::sub_32bit; 758 break; 759 } 760 return true; 761 } 762 } 763 return false; 764} 765 766/// isFrameOperand - Return true and the FrameIndex if the specified 767/// operand and follow operands form a reference to the stack frame. 768bool X86InstrInfo::isFrameOperand(const MachineInstr *MI, unsigned int Op, 769 int &FrameIndex) const { 770 if (MI->getOperand(Op).isFI() && MI->getOperand(Op+1).isImm() && 771 MI->getOperand(Op+2).isReg() && MI->getOperand(Op+3).isImm() && 772 MI->getOperand(Op+1).getImm() == 1 && 773 MI->getOperand(Op+2).getReg() == 0 && 774 MI->getOperand(Op+3).getImm() == 0) { 775 FrameIndex = MI->getOperand(Op).getIndex(); 776 return true; 777 } 778 return false; 779} 780 781static bool isFrameLoadOpcode(int Opcode) { 782 switch (Opcode) { 783 default: break; 784 case X86::MOV8rm: 785 case X86::MOV16rm: 786 case X86::MOV32rm: 787 case X86::MOV64rm: 788 case X86::LD_Fp64m: 789 case X86::MOVSSrm: 790 case X86::MOVSDrm: 791 case X86::MOVAPSrm: 792 case X86::MOVAPDrm: 793 case X86::MOVDQArm: 794 case X86::MMX_MOVD64rm: 795 case X86::MMX_MOVQ64rm: 796 return true; 797 break; 798 } 799 return false; 800} 801 802static bool isFrameStoreOpcode(int Opcode) { 803 switch (Opcode) { 804 default: break; 805 case X86::MOV8mr: 806 case X86::MOV16mr: 807 case X86::MOV32mr: 808 case X86::MOV64mr: 809 case X86::ST_FpP64m: 810 case X86::MOVSSmr: 811 case X86::MOVSDmr: 812 case X86::MOVAPSmr: 813 case X86::MOVAPDmr: 814 case X86::MOVDQAmr: 815 case X86::MMX_MOVD64mr: 816 case X86::MMX_MOVQ64mr: 817 case X86::MMX_MOVNTQmr: 818 return true; 819 } 820 return false; 821} 822 823unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr *MI, 824 int &FrameIndex) const { 825 if (isFrameLoadOpcode(MI->getOpcode())) 826 if (isFrameOperand(MI, 1, FrameIndex)) 827 return MI->getOperand(0).getReg(); 828 return 0; 829} 830 831unsigned X86InstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI, 832 int &FrameIndex) const { 833 if (isFrameLoadOpcode(MI->getOpcode())) { 834 unsigned Reg; 835 if ((Reg = isLoadFromStackSlot(MI, FrameIndex))) 836 return Reg; 837 // Check for post-frame index elimination operations 838 const MachineMemOperand *Dummy; 839 return hasLoadFromStackSlot(MI, Dummy, FrameIndex); 840 } 841 return 0; 842} 843 844bool X86InstrInfo::hasLoadFromStackSlot(const MachineInstr *MI, 845 const MachineMemOperand *&MMO, 846 int &FrameIndex) const { 847 for (MachineInstr::mmo_iterator o = MI->memoperands_begin(), 848 oe = MI->memoperands_end(); 849 o != oe; 850 ++o) { 851 if ((*o)->isLoad() && (*o)->getValue()) 852 if (const FixedStackPseudoSourceValue *Value = 853 dyn_cast<const FixedStackPseudoSourceValue>((*o)->getValue())) { 854 FrameIndex = Value->getFrameIndex(); 855 MMO = *o; 856 return true; 857 } 858 } 859 return false; 860} 861 862unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr *MI, 863 int &FrameIndex) const { 864 if (isFrameStoreOpcode(MI->getOpcode())) 865 if (isFrameOperand(MI, 0, FrameIndex)) 866 return MI->getOperand(X86AddrNumOperands).getReg(); 867 return 0; 868} 869 870unsigned X86InstrInfo::isStoreToStackSlotPostFE(const MachineInstr *MI, 871 int &FrameIndex) const { 872 if (isFrameStoreOpcode(MI->getOpcode())) { 873 unsigned Reg; 874 if ((Reg = isStoreToStackSlot(MI, FrameIndex))) 875 return Reg; 876 // Check for post-frame index elimination operations 877 const MachineMemOperand *Dummy; 878 return hasStoreToStackSlot(MI, Dummy, FrameIndex); 879 } 880 return 0; 881} 882 883bool X86InstrInfo::hasStoreToStackSlot(const MachineInstr *MI, 884 const MachineMemOperand *&MMO, 885 int &FrameIndex) const { 886 for (MachineInstr::mmo_iterator o = MI->memoperands_begin(), 887 oe = MI->memoperands_end(); 888 o != oe; 889 ++o) { 890 if ((*o)->isStore() && (*o)->getValue()) 891 if (const FixedStackPseudoSourceValue *Value = 892 dyn_cast<const FixedStackPseudoSourceValue>((*o)->getValue())) { 893 FrameIndex = Value->getFrameIndex(); 894 MMO = *o; 895 return true; 896 } 897 } 898 return false; 899} 900 901/// regIsPICBase - Return true if register is PIC base (i.e.g defined by 902/// X86::MOVPC32r. 903static bool regIsPICBase(unsigned BaseReg, const MachineRegisterInfo &MRI) { 904 bool isPICBase = false; 905 for (MachineRegisterInfo::def_iterator I = MRI.def_begin(BaseReg), 906 E = MRI.def_end(); I != E; ++I) { 907 MachineInstr *DefMI = I.getOperand().getParent(); 908 if (DefMI->getOpcode() != X86::MOVPC32r) 909 return false; 910 assert(!isPICBase && "More than one PIC base?"); 911 isPICBase = true; 912 } 913 return isPICBase; 914} 915 916bool 917X86InstrInfo::isReallyTriviallyReMaterializable(const MachineInstr *MI, 918 AliasAnalysis *AA) const { 919 switch (MI->getOpcode()) { 920 default: break; 921 case X86::MOV8rm: 922 case X86::MOV16rm: 923 case X86::MOV32rm: 924 case X86::MOV64rm: 925 case X86::LD_Fp64m: 926 case X86::MOVSSrm: 927 case X86::MOVSDrm: 928 case X86::MOVAPSrm: 929 case X86::MOVUPSrm: 930 case X86::MOVUPSrm_Int: 931 case X86::MOVAPDrm: 932 case X86::MOVDQArm: 933 case X86::MMX_MOVD64rm: 934 case X86::MMX_MOVQ64rm: 935 case X86::FsMOVAPSrm: 936 case X86::FsMOVAPDrm: { 937 // Loads from constant pools are trivially rematerializable. 938 if (MI->getOperand(1).isReg() && 939 MI->getOperand(2).isImm() && 940 MI->getOperand(3).isReg() && MI->getOperand(3).getReg() == 0 && 941 MI->isInvariantLoad(AA)) { 942 unsigned BaseReg = MI->getOperand(1).getReg(); 943 if (BaseReg == 0 || BaseReg == X86::RIP) 944 return true; 945 // Allow re-materialization of PIC load. 946 if (!ReMatPICStubLoad && MI->getOperand(4).isGlobal()) 947 return false; 948 const MachineFunction &MF = *MI->getParent()->getParent(); 949 const MachineRegisterInfo &MRI = MF.getRegInfo(); 950 bool isPICBase = false; 951 for (MachineRegisterInfo::def_iterator I = MRI.def_begin(BaseReg), 952 E = MRI.def_end(); I != E; ++I) { 953 MachineInstr *DefMI = I.getOperand().getParent(); 954 if (DefMI->getOpcode() != X86::MOVPC32r) 955 return false; 956 assert(!isPICBase && "More than one PIC base?"); 957 isPICBase = true; 958 } 959 return isPICBase; 960 } 961 return false; 962 } 963 964 case X86::LEA32r: 965 case X86::LEA64r: { 966 if (MI->getOperand(2).isImm() && 967 MI->getOperand(3).isReg() && MI->getOperand(3).getReg() == 0 && 968 !MI->getOperand(4).isReg()) { 969 // lea fi#, lea GV, etc. are all rematerializable. 970 if (!MI->getOperand(1).isReg()) 971 return true; 972 unsigned BaseReg = MI->getOperand(1).getReg(); 973 if (BaseReg == 0) 974 return true; 975 // Allow re-materialization of lea PICBase + x. 976 const MachineFunction &MF = *MI->getParent()->getParent(); 977 const MachineRegisterInfo &MRI = MF.getRegInfo(); 978 return regIsPICBase(BaseReg, MRI); 979 } 980 return false; 981 } 982 } 983 984 // All other instructions marked M_REMATERIALIZABLE are always trivially 985 // rematerializable. 986 return true; 987} 988 989/// isSafeToClobberEFLAGS - Return true if it's safe insert an instruction that 990/// would clobber the EFLAGS condition register. Note the result may be 991/// conservative. If it cannot definitely determine the safety after visiting 992/// a few instructions in each direction it assumes it's not safe. 993static bool isSafeToClobberEFLAGS(MachineBasicBlock &MBB, 994 MachineBasicBlock::iterator I) { 995 MachineBasicBlock::iterator E = MBB.end(); 996 997 // It's always safe to clobber EFLAGS at the end of a block. 998 if (I == E) 999 return true; 1000 1001 // For compile time consideration, if we are not able to determine the 1002 // safety after visiting 4 instructions in each direction, we will assume 1003 // it's not safe. 1004 MachineBasicBlock::iterator Iter = I; 1005 for (unsigned i = 0; i < 4; ++i) { 1006 bool SeenDef = false; 1007 for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) { 1008 MachineOperand &MO = Iter->getOperand(j); 1009 if (!MO.isReg()) 1010 continue; 1011 if (MO.getReg() == X86::EFLAGS) { 1012 if (MO.isUse()) 1013 return false; 1014 SeenDef = true; 1015 } 1016 } 1017 1018 if (SeenDef) 1019 // This instruction defines EFLAGS, no need to look any further. 1020 return true; 1021 ++Iter; 1022 // Skip over DBG_VALUE. 1023 while (Iter != E && Iter->isDebugValue()) 1024 ++Iter; 1025 1026 // If we make it to the end of the block, it's safe to clobber EFLAGS. 1027 if (Iter == E) 1028 return true; 1029 } 1030 1031 MachineBasicBlock::iterator B = MBB.begin(); 1032 Iter = I; 1033 for (unsigned i = 0; i < 4; ++i) { 1034 // If we make it to the beginning of the block, it's safe to clobber 1035 // EFLAGS iff EFLAGS is not live-in. 1036 if (Iter == B) 1037 return !MBB.isLiveIn(X86::EFLAGS); 1038 1039 --Iter; 1040 // Skip over DBG_VALUE. 1041 while (Iter != B && Iter->isDebugValue()) 1042 --Iter; 1043 1044 bool SawKill = false; 1045 for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) { 1046 MachineOperand &MO = Iter->getOperand(j); 1047 if (MO.isReg() && MO.getReg() == X86::EFLAGS) { 1048 if (MO.isDef()) return MO.isDead(); 1049 if (MO.isKill()) SawKill = true; 1050 } 1051 } 1052 1053 if (SawKill) 1054 // This instruction kills EFLAGS and doesn't redefine it, so 1055 // there's no need to look further. 1056 return true; 1057 } 1058 1059 // Conservative answer. 1060 return false; 1061} 1062 1063void X86InstrInfo::reMaterialize(MachineBasicBlock &MBB, 1064 MachineBasicBlock::iterator I, 1065 unsigned DestReg, unsigned SubIdx, 1066 const MachineInstr *Orig, 1067 const TargetRegisterInfo &TRI) const { 1068 DebugLoc DL = Orig->getDebugLoc(); 1069 1070 // MOV32r0 etc. are implemented with xor which clobbers condition code. 1071 // Re-materialize them as movri instructions to avoid side effects. 1072 bool Clone = true; 1073 unsigned Opc = Orig->getOpcode(); 1074 switch (Opc) { 1075 default: break; 1076 case X86::MOV8r0: 1077 case X86::MOV16r0: 1078 case X86::MOV32r0: 1079 case X86::MOV64r0: { 1080 if (!isSafeToClobberEFLAGS(MBB, I)) { 1081 switch (Opc) { 1082 default: break; 1083 case X86::MOV8r0: Opc = X86::MOV8ri; break; 1084 case X86::MOV16r0: Opc = X86::MOV16ri; break; 1085 case X86::MOV32r0: Opc = X86::MOV32ri; break; 1086 case X86::MOV64r0: Opc = X86::MOV64ri64i32; break; 1087 } 1088 Clone = false; 1089 } 1090 break; 1091 } 1092 } 1093 1094 if (Clone) { 1095 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig); 1096 MBB.insert(I, MI); 1097 } else { 1098 BuildMI(MBB, I, DL, get(Opc)).addOperand(Orig->getOperand(0)).addImm(0); 1099 } 1100 1101 MachineInstr *NewMI = prior(I); 1102 NewMI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI); 1103} 1104 1105/// hasLiveCondCodeDef - True if MI has a condition code def, e.g. EFLAGS, that 1106/// is not marked dead. 1107static bool hasLiveCondCodeDef(MachineInstr *MI) { 1108 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 1109 MachineOperand &MO = MI->getOperand(i); 1110 if (MO.isReg() && MO.isDef() && 1111 MO.getReg() == X86::EFLAGS && !MO.isDead()) { 1112 return true; 1113 } 1114 } 1115 return false; 1116} 1117 1118/// convertToThreeAddressWithLEA - Helper for convertToThreeAddress when 1119/// 16-bit LEA is disabled, use 32-bit LEA to form 3-address code by promoting 1120/// to a 32-bit superregister and then truncating back down to a 16-bit 1121/// subregister. 1122MachineInstr * 1123X86InstrInfo::convertToThreeAddressWithLEA(unsigned MIOpc, 1124 MachineFunction::iterator &MFI, 1125 MachineBasicBlock::iterator &MBBI, 1126 LiveVariables *LV) const { 1127 MachineInstr *MI = MBBI; 1128 unsigned Dest = MI->getOperand(0).getReg(); 1129 unsigned Src = MI->getOperand(1).getReg(); 1130 bool isDead = MI->getOperand(0).isDead(); 1131 bool isKill = MI->getOperand(1).isKill(); 1132 1133 unsigned Opc = TM.getSubtarget<X86Subtarget>().is64Bit() 1134 ? X86::LEA64_32r : X86::LEA32r; 1135 MachineRegisterInfo &RegInfo = MFI->getParent()->getRegInfo(); 1136 unsigned leaInReg = RegInfo.createVirtualRegister(&X86::GR32RegClass); 1137 unsigned leaOutReg = RegInfo.createVirtualRegister(&X86::GR32RegClass); 1138 1139 // Build and insert into an implicit UNDEF value. This is OK because 1140 // well be shifting and then extracting the lower 16-bits. 1141 // This has the potential to cause partial register stall. e.g. 1142 // movw (%rbp,%rcx,2), %dx 1143 // leal -65(%rdx), %esi 1144 // But testing has shown this *does* help performance in 64-bit mode (at 1145 // least on modern x86 machines). 1146 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg); 1147 MachineInstr *InsMI = 1148 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(TargetOpcode::COPY)) 1149 .addReg(leaInReg, RegState::Define, X86::sub_16bit) 1150 .addReg(Src, getKillRegState(isKill)); 1151 1152 MachineInstrBuilder MIB = BuildMI(*MFI, MBBI, MI->getDebugLoc(), 1153 get(Opc), leaOutReg); 1154 switch (MIOpc) { 1155 default: 1156 llvm_unreachable(0); 1157 break; 1158 case X86::SHL16ri: { 1159 unsigned ShAmt = MI->getOperand(2).getImm(); 1160 MIB.addReg(0).addImm(1 << ShAmt) 1161 .addReg(leaInReg, RegState::Kill).addImm(0); 1162 break; 1163 } 1164 case X86::INC16r: 1165 case X86::INC64_16r: 1166 addLeaRegOffset(MIB, leaInReg, true, 1); 1167 break; 1168 case X86::DEC16r: 1169 case X86::DEC64_16r: 1170 addLeaRegOffset(MIB, leaInReg, true, -1); 1171 break; 1172 case X86::ADD16ri: 1173 case X86::ADD16ri8: 1174 addLeaRegOffset(MIB, leaInReg, true, MI->getOperand(2).getImm()); 1175 break; 1176 case X86::ADD16rr: { 1177 unsigned Src2 = MI->getOperand(2).getReg(); 1178 bool isKill2 = MI->getOperand(2).isKill(); 1179 unsigned leaInReg2 = 0; 1180 MachineInstr *InsMI2 = 0; 1181 if (Src == Src2) { 1182 // ADD16rr %reg1028<kill>, %reg1028 1183 // just a single insert_subreg. 1184 addRegReg(MIB, leaInReg, true, leaInReg, false); 1185 } else { 1186 leaInReg2 = RegInfo.createVirtualRegister(&X86::GR32RegClass); 1187 // Build and insert into an implicit UNDEF value. This is OK because 1188 // well be shifting and then extracting the lower 16-bits. 1189 BuildMI(*MFI, MIB, MI->getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg2); 1190 InsMI2 = 1191 BuildMI(*MFI, MIB, MI->getDebugLoc(), get(TargetOpcode::COPY)) 1192 .addReg(leaInReg2, RegState::Define, X86::sub_16bit) 1193 .addReg(Src2, getKillRegState(isKill2)); 1194 addRegReg(MIB, leaInReg, true, leaInReg2, true); 1195 } 1196 if (LV && isKill2 && InsMI2) 1197 LV->replaceKillInstruction(Src2, MI, InsMI2); 1198 break; 1199 } 1200 } 1201 1202 MachineInstr *NewMI = MIB; 1203 MachineInstr *ExtMI = 1204 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::EXTRACT_SUBREG)) 1205 .addReg(Dest, RegState::Define | getDeadRegState(isDead)) 1206 .addReg(leaOutReg, RegState::Kill) 1207 .addImm(X86::sub_16bit); 1208 1209 if (LV) { 1210 // Update live variables 1211 LV->getVarInfo(leaInReg).Kills.push_back(NewMI); 1212 LV->getVarInfo(leaOutReg).Kills.push_back(ExtMI); 1213 if (isKill) 1214 LV->replaceKillInstruction(Src, MI, InsMI); 1215 if (isDead) 1216 LV->replaceKillInstruction(Dest, MI, ExtMI); 1217 } 1218 1219 return ExtMI; 1220} 1221 1222/// convertToThreeAddress - This method must be implemented by targets that 1223/// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target 1224/// may be able to convert a two-address instruction into a true 1225/// three-address instruction on demand. This allows the X86 target (for 1226/// example) to convert ADD and SHL instructions into LEA instructions if they 1227/// would require register copies due to two-addressness. 1228/// 1229/// This method returns a null pointer if the transformation cannot be 1230/// performed, otherwise it returns the new instruction. 1231/// 1232MachineInstr * 1233X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI, 1234 MachineBasicBlock::iterator &MBBI, 1235 LiveVariables *LV) const { 1236 MachineInstr *MI = MBBI; 1237 MachineFunction &MF = *MI->getParent()->getParent(); 1238 // All instructions input are two-addr instructions. Get the known operands. 1239 unsigned Dest = MI->getOperand(0).getReg(); 1240 unsigned Src = MI->getOperand(1).getReg(); 1241 bool isDead = MI->getOperand(0).isDead(); 1242 bool isKill = MI->getOperand(1).isKill(); 1243 1244 MachineInstr *NewMI = NULL; 1245 // FIXME: 16-bit LEA's are really slow on Athlons, but not bad on P4's. When 1246 // we have better subtarget support, enable the 16-bit LEA generation here. 1247 // 16-bit LEA is also slow on Core2. 1248 bool DisableLEA16 = true; 1249 bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit(); 1250 1251 unsigned MIOpc = MI->getOpcode(); 1252 switch (MIOpc) { 1253 case X86::SHUFPSrri: { 1254 assert(MI->getNumOperands() == 4 && "Unknown shufps instruction!"); 1255 if (!TM.getSubtarget<X86Subtarget>().hasSSE2()) return 0; 1256 1257 unsigned B = MI->getOperand(1).getReg(); 1258 unsigned C = MI->getOperand(2).getReg(); 1259 if (B != C) return 0; 1260 unsigned A = MI->getOperand(0).getReg(); 1261 unsigned M = MI->getOperand(3).getImm(); 1262 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::PSHUFDri)) 1263 .addReg(A, RegState::Define | getDeadRegState(isDead)) 1264 .addReg(B, getKillRegState(isKill)).addImm(M); 1265 break; 1266 } 1267 case X86::SHL64ri: { 1268 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!"); 1269 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses 1270 // the flags produced by a shift yet, so this is safe. 1271 unsigned ShAmt = MI->getOperand(2).getImm(); 1272 if (ShAmt == 0 || ShAmt >= 4) return 0; 1273 1274 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r)) 1275 .addReg(Dest, RegState::Define | getDeadRegState(isDead)) 1276 .addReg(0).addImm(1 << ShAmt) 1277 .addReg(Src, getKillRegState(isKill)) 1278 .addImm(0); 1279 break; 1280 } 1281 case X86::SHL32ri: { 1282 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!"); 1283 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses 1284 // the flags produced by a shift yet, so this is safe. 1285 unsigned ShAmt = MI->getOperand(2).getImm(); 1286 if (ShAmt == 0 || ShAmt >= 4) return 0; 1287 1288 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r; 1289 NewMI = BuildMI(MF, MI->getDebugLoc(), get(Opc)) 1290 .addReg(Dest, RegState::Define | getDeadRegState(isDead)) 1291 .addReg(0).addImm(1 << ShAmt) 1292 .addReg(Src, getKillRegState(isKill)).addImm(0); 1293 break; 1294 } 1295 case X86::SHL16ri: { 1296 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!"); 1297 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses 1298 // the flags produced by a shift yet, so this is safe. 1299 unsigned ShAmt = MI->getOperand(2).getImm(); 1300 if (ShAmt == 0 || ShAmt >= 4) return 0; 1301 1302 if (DisableLEA16) 1303 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0; 1304 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r)) 1305 .addReg(Dest, RegState::Define | getDeadRegState(isDead)) 1306 .addReg(0).addImm(1 << ShAmt) 1307 .addReg(Src, getKillRegState(isKill)) 1308 .addImm(0); 1309 break; 1310 } 1311 default: { 1312 // The following opcodes also sets the condition code register(s). Only 1313 // convert them to equivalent lea if the condition code register def's 1314 // are dead! 1315 if (hasLiveCondCodeDef(MI)) 1316 return 0; 1317 1318 switch (MIOpc) { 1319 default: return 0; 1320 case X86::INC64r: 1321 case X86::INC32r: 1322 case X86::INC64_32r: { 1323 assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!"); 1324 unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r 1325 : (is64Bit ? X86::LEA64_32r : X86::LEA32r); 1326 NewMI = addLeaRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc)) 1327 .addReg(Dest, RegState::Define | 1328 getDeadRegState(isDead)), 1329 Src, isKill, 1); 1330 break; 1331 } 1332 case X86::INC16r: 1333 case X86::INC64_16r: 1334 if (DisableLEA16) 1335 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0; 1336 assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!"); 1337 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r)) 1338 .addReg(Dest, RegState::Define | 1339 getDeadRegState(isDead)), 1340 Src, isKill, 1); 1341 break; 1342 case X86::DEC64r: 1343 case X86::DEC32r: 1344 case X86::DEC64_32r: { 1345 assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!"); 1346 unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r 1347 : (is64Bit ? X86::LEA64_32r : X86::LEA32r); 1348 NewMI = addLeaRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc)) 1349 .addReg(Dest, RegState::Define | 1350 getDeadRegState(isDead)), 1351 Src, isKill, -1); 1352 break; 1353 } 1354 case X86::DEC16r: 1355 case X86::DEC64_16r: 1356 if (DisableLEA16) 1357 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0; 1358 assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!"); 1359 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r)) 1360 .addReg(Dest, RegState::Define | 1361 getDeadRegState(isDead)), 1362 Src, isKill, -1); 1363 break; 1364 case X86::ADD64rr: 1365 case X86::ADD32rr: { 1366 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!"); 1367 unsigned Opc = MIOpc == X86::ADD64rr ? X86::LEA64r 1368 : (is64Bit ? X86::LEA64_32r : X86::LEA32r); 1369 unsigned Src2 = MI->getOperand(2).getReg(); 1370 bool isKill2 = MI->getOperand(2).isKill(); 1371 NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(Opc)) 1372 .addReg(Dest, RegState::Define | 1373 getDeadRegState(isDead)), 1374 Src, isKill, Src2, isKill2); 1375 if (LV && isKill2) 1376 LV->replaceKillInstruction(Src2, MI, NewMI); 1377 break; 1378 } 1379 case X86::ADD16rr: { 1380 if (DisableLEA16) 1381 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0; 1382 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!"); 1383 unsigned Src2 = MI->getOperand(2).getReg(); 1384 bool isKill2 = MI->getOperand(2).isKill(); 1385 NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r)) 1386 .addReg(Dest, RegState::Define | 1387 getDeadRegState(isDead)), 1388 Src, isKill, Src2, isKill2); 1389 if (LV && isKill2) 1390 LV->replaceKillInstruction(Src2, MI, NewMI); 1391 break; 1392 } 1393 case X86::ADD64ri32: 1394 case X86::ADD64ri8: 1395 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!"); 1396 NewMI = addLeaRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r)) 1397 .addReg(Dest, RegState::Define | 1398 getDeadRegState(isDead)), 1399 Src, isKill, MI->getOperand(2).getImm()); 1400 break; 1401 case X86::ADD32ri: 1402 case X86::ADD32ri8: { 1403 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!"); 1404 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r; 1405 NewMI = addLeaRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc)) 1406 .addReg(Dest, RegState::Define | 1407 getDeadRegState(isDead)), 1408 Src, isKill, MI->getOperand(2).getImm()); 1409 break; 1410 } 1411 case X86::ADD16ri: 1412 case X86::ADD16ri8: 1413 if (DisableLEA16) 1414 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0; 1415 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!"); 1416 NewMI = addLeaRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r)) 1417 .addReg(Dest, RegState::Define | 1418 getDeadRegState(isDead)), 1419 Src, isKill, MI->getOperand(2).getImm()); 1420 break; 1421 } 1422 } 1423 } 1424 1425 if (!NewMI) return 0; 1426 1427 if (LV) { // Update live variables 1428 if (isKill) 1429 LV->replaceKillInstruction(Src, MI, NewMI); 1430 if (isDead) 1431 LV->replaceKillInstruction(Dest, MI, NewMI); 1432 } 1433 1434 MFI->insert(MBBI, NewMI); // Insert the new inst 1435 return NewMI; 1436} 1437 1438/// commuteInstruction - We have a few instructions that must be hacked on to 1439/// commute them. 1440/// 1441MachineInstr * 1442X86InstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const { 1443 switch (MI->getOpcode()) { 1444 case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I) 1445 case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I) 1446 case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I) 1447 case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I) 1448 case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I -> A = SHLD64rri8 C, B, (64-I) 1449 case X86::SHLD64rri8:{// A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, (64-I) 1450 unsigned Opc; 1451 unsigned Size; 1452 switch (MI->getOpcode()) { 1453 default: llvm_unreachable("Unreachable!"); 1454 case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break; 1455 case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break; 1456 case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break; 1457 case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break; 1458 case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break; 1459 case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break; 1460 } 1461 unsigned Amt = MI->getOperand(3).getImm(); 1462 if (NewMI) { 1463 MachineFunction &MF = *MI->getParent()->getParent(); 1464 MI = MF.CloneMachineInstr(MI); 1465 NewMI = false; 1466 } 1467 MI->setDesc(get(Opc)); 1468 MI->getOperand(3).setImm(Size-Amt); 1469 return TargetInstrInfoImpl::commuteInstruction(MI, NewMI); 1470 } 1471 case X86::CMOVB16rr: 1472 case X86::CMOVB32rr: 1473 case X86::CMOVB64rr: 1474 case X86::CMOVAE16rr: 1475 case X86::CMOVAE32rr: 1476 case X86::CMOVAE64rr: 1477 case X86::CMOVE16rr: 1478 case X86::CMOVE32rr: 1479 case X86::CMOVE64rr: 1480 case X86::CMOVNE16rr: 1481 case X86::CMOVNE32rr: 1482 case X86::CMOVNE64rr: 1483 case X86::CMOVBE16rr: 1484 case X86::CMOVBE32rr: 1485 case X86::CMOVBE64rr: 1486 case X86::CMOVA16rr: 1487 case X86::CMOVA32rr: 1488 case X86::CMOVA64rr: 1489 case X86::CMOVL16rr: 1490 case X86::CMOVL32rr: 1491 case X86::CMOVL64rr: 1492 case X86::CMOVGE16rr: 1493 case X86::CMOVGE32rr: 1494 case X86::CMOVGE64rr: 1495 case X86::CMOVLE16rr: 1496 case X86::CMOVLE32rr: 1497 case X86::CMOVLE64rr: 1498 case X86::CMOVG16rr: 1499 case X86::CMOVG32rr: 1500 case X86::CMOVG64rr: 1501 case X86::CMOVS16rr: 1502 case X86::CMOVS32rr: 1503 case X86::CMOVS64rr: 1504 case X86::CMOVNS16rr: 1505 case X86::CMOVNS32rr: 1506 case X86::CMOVNS64rr: 1507 case X86::CMOVP16rr: 1508 case X86::CMOVP32rr: 1509 case X86::CMOVP64rr: 1510 case X86::CMOVNP16rr: 1511 case X86::CMOVNP32rr: 1512 case X86::CMOVNP64rr: 1513 case X86::CMOVO16rr: 1514 case X86::CMOVO32rr: 1515 case X86::CMOVO64rr: 1516 case X86::CMOVNO16rr: 1517 case X86::CMOVNO32rr: 1518 case X86::CMOVNO64rr: { 1519 unsigned Opc = 0; 1520 switch (MI->getOpcode()) { 1521 default: break; 1522 case X86::CMOVB16rr: Opc = X86::CMOVAE16rr; break; 1523 case X86::CMOVB32rr: Opc = X86::CMOVAE32rr; break; 1524 case X86::CMOVB64rr: Opc = X86::CMOVAE64rr; break; 1525 case X86::CMOVAE16rr: Opc = X86::CMOVB16rr; break; 1526 case X86::CMOVAE32rr: Opc = X86::CMOVB32rr; break; 1527 case X86::CMOVAE64rr: Opc = X86::CMOVB64rr; break; 1528 case X86::CMOVE16rr: Opc = X86::CMOVNE16rr; break; 1529 case X86::CMOVE32rr: Opc = X86::CMOVNE32rr; break; 1530 case X86::CMOVE64rr: Opc = X86::CMOVNE64rr; break; 1531 case X86::CMOVNE16rr: Opc = X86::CMOVE16rr; break; 1532 case X86::CMOVNE32rr: Opc = X86::CMOVE32rr; break; 1533 case X86::CMOVNE64rr: Opc = X86::CMOVE64rr; break; 1534 case X86::CMOVBE16rr: Opc = X86::CMOVA16rr; break; 1535 case X86::CMOVBE32rr: Opc = X86::CMOVA32rr; break; 1536 case X86::CMOVBE64rr: Opc = X86::CMOVA64rr; break; 1537 case X86::CMOVA16rr: Opc = X86::CMOVBE16rr; break; 1538 case X86::CMOVA32rr: Opc = X86::CMOVBE32rr; break; 1539 case X86::CMOVA64rr: Opc = X86::CMOVBE64rr; break; 1540 case X86::CMOVL16rr: Opc = X86::CMOVGE16rr; break; 1541 case X86::CMOVL32rr: Opc = X86::CMOVGE32rr; break; 1542 case X86::CMOVL64rr: Opc = X86::CMOVGE64rr; break; 1543 case X86::CMOVGE16rr: Opc = X86::CMOVL16rr; break; 1544 case X86::CMOVGE32rr: Opc = X86::CMOVL32rr; break; 1545 case X86::CMOVGE64rr: Opc = X86::CMOVL64rr; break; 1546 case X86::CMOVLE16rr: Opc = X86::CMOVG16rr; break; 1547 case X86::CMOVLE32rr: Opc = X86::CMOVG32rr; break; 1548 case X86::CMOVLE64rr: Opc = X86::CMOVG64rr; break; 1549 case X86::CMOVG16rr: Opc = X86::CMOVLE16rr; break; 1550 case X86::CMOVG32rr: Opc = X86::CMOVLE32rr; break; 1551 case X86::CMOVG64rr: Opc = X86::CMOVLE64rr; break; 1552 case X86::CMOVS16rr: Opc = X86::CMOVNS16rr; break; 1553 case X86::CMOVS32rr: Opc = X86::CMOVNS32rr; break; 1554 case X86::CMOVS64rr: Opc = X86::CMOVNS64rr; break; 1555 case X86::CMOVNS16rr: Opc = X86::CMOVS16rr; break; 1556 case X86::CMOVNS32rr: Opc = X86::CMOVS32rr; break; 1557 case X86::CMOVNS64rr: Opc = X86::CMOVS64rr; break; 1558 case X86::CMOVP16rr: Opc = X86::CMOVNP16rr; break; 1559 case X86::CMOVP32rr: Opc = X86::CMOVNP32rr; break; 1560 case X86::CMOVP64rr: Opc = X86::CMOVNP64rr; break; 1561 case X86::CMOVNP16rr: Opc = X86::CMOVP16rr; break; 1562 case X86::CMOVNP32rr: Opc = X86::CMOVP32rr; break; 1563 case X86::CMOVNP64rr: Opc = X86::CMOVP64rr; break; 1564 case X86::CMOVO16rr: Opc = X86::CMOVNO16rr; break; 1565 case X86::CMOVO32rr: Opc = X86::CMOVNO32rr; break; 1566 case X86::CMOVO64rr: Opc = X86::CMOVNO64rr; break; 1567 case X86::CMOVNO16rr: Opc = X86::CMOVO16rr; break; 1568 case X86::CMOVNO32rr: Opc = X86::CMOVO32rr; break; 1569 case X86::CMOVNO64rr: Opc = X86::CMOVO64rr; break; 1570 } 1571 if (NewMI) { 1572 MachineFunction &MF = *MI->getParent()->getParent(); 1573 MI = MF.CloneMachineInstr(MI); 1574 NewMI = false; 1575 } 1576 MI->setDesc(get(Opc)); 1577 // Fallthrough intended. 1578 } 1579 default: 1580 return TargetInstrInfoImpl::commuteInstruction(MI, NewMI); 1581 } 1582} 1583 1584static X86::CondCode GetCondFromBranchOpc(unsigned BrOpc) { 1585 switch (BrOpc) { 1586 default: return X86::COND_INVALID; 1587 case X86::JE_4: return X86::COND_E; 1588 case X86::JNE_4: return X86::COND_NE; 1589 case X86::JL_4: return X86::COND_L; 1590 case X86::JLE_4: return X86::COND_LE; 1591 case X86::JG_4: return X86::COND_G; 1592 case X86::JGE_4: return X86::COND_GE; 1593 case X86::JB_4: return X86::COND_B; 1594 case X86::JBE_4: return X86::COND_BE; 1595 case X86::JA_4: return X86::COND_A; 1596 case X86::JAE_4: return X86::COND_AE; 1597 case X86::JS_4: return X86::COND_S; 1598 case X86::JNS_4: return X86::COND_NS; 1599 case X86::JP_4: return X86::COND_P; 1600 case X86::JNP_4: return X86::COND_NP; 1601 case X86::JO_4: return X86::COND_O; 1602 case X86::JNO_4: return X86::COND_NO; 1603 } 1604} 1605 1606unsigned X86::GetCondBranchFromCond(X86::CondCode CC) { 1607 switch (CC) { 1608 default: llvm_unreachable("Illegal condition code!"); 1609 case X86::COND_E: return X86::JE_4; 1610 case X86::COND_NE: return X86::JNE_4; 1611 case X86::COND_L: return X86::JL_4; 1612 case X86::COND_LE: return X86::JLE_4; 1613 case X86::COND_G: return X86::JG_4; 1614 case X86::COND_GE: return X86::JGE_4; 1615 case X86::COND_B: return X86::JB_4; 1616 case X86::COND_BE: return X86::JBE_4; 1617 case X86::COND_A: return X86::JA_4; 1618 case X86::COND_AE: return X86::JAE_4; 1619 case X86::COND_S: return X86::JS_4; 1620 case X86::COND_NS: return X86::JNS_4; 1621 case X86::COND_P: return X86::JP_4; 1622 case X86::COND_NP: return X86::JNP_4; 1623 case X86::COND_O: return X86::JO_4; 1624 case X86::COND_NO: return X86::JNO_4; 1625 } 1626} 1627 1628/// GetOppositeBranchCondition - Return the inverse of the specified condition, 1629/// e.g. turning COND_E to COND_NE. 1630X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) { 1631 switch (CC) { 1632 default: llvm_unreachable("Illegal condition code!"); 1633 case X86::COND_E: return X86::COND_NE; 1634 case X86::COND_NE: return X86::COND_E; 1635 case X86::COND_L: return X86::COND_GE; 1636 case X86::COND_LE: return X86::COND_G; 1637 case X86::COND_G: return X86::COND_LE; 1638 case X86::COND_GE: return X86::COND_L; 1639 case X86::COND_B: return X86::COND_AE; 1640 case X86::COND_BE: return X86::COND_A; 1641 case X86::COND_A: return X86::COND_BE; 1642 case X86::COND_AE: return X86::COND_B; 1643 case X86::COND_S: return X86::COND_NS; 1644 case X86::COND_NS: return X86::COND_S; 1645 case X86::COND_P: return X86::COND_NP; 1646 case X86::COND_NP: return X86::COND_P; 1647 case X86::COND_O: return X86::COND_NO; 1648 case X86::COND_NO: return X86::COND_O; 1649 } 1650} 1651 1652bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const { 1653 const TargetInstrDesc &TID = MI->getDesc(); 1654 if (!TID.isTerminator()) return false; 1655 1656 // Conditional branch is a special case. 1657 if (TID.isBranch() && !TID.isBarrier()) 1658 return true; 1659 if (!TID.isPredicable()) 1660 return true; 1661 return !isPredicated(MI); 1662} 1663 1664// For purposes of branch analysis do not count FP_REG_KILL as a terminator. 1665static bool isBrAnalysisUnpredicatedTerminator(const MachineInstr *MI, 1666 const X86InstrInfo &TII) { 1667 if (MI->getOpcode() == X86::FP_REG_KILL) 1668 return false; 1669 return TII.isUnpredicatedTerminator(MI); 1670} 1671 1672bool X86InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, 1673 MachineBasicBlock *&TBB, 1674 MachineBasicBlock *&FBB, 1675 SmallVectorImpl<MachineOperand> &Cond, 1676 bool AllowModify) const { 1677 // Start from the bottom of the block and work up, examining the 1678 // terminator instructions. 1679 MachineBasicBlock::iterator I = MBB.end(); 1680 MachineBasicBlock::iterator UnCondBrIter = MBB.end(); 1681 while (I != MBB.begin()) { 1682 --I; 1683 if (I->isDebugValue()) 1684 continue; 1685 1686 // Working from the bottom, when we see a non-terminator instruction, we're 1687 // done. 1688 if (!isBrAnalysisUnpredicatedTerminator(I, *this)) 1689 break; 1690 1691 // A terminator that isn't a branch can't easily be handled by this 1692 // analysis. 1693 if (!I->getDesc().isBranch()) 1694 return true; 1695 1696 // Handle unconditional branches. 1697 if (I->getOpcode() == X86::JMP_4) { 1698 UnCondBrIter = I; 1699 1700 if (!AllowModify) { 1701 TBB = I->getOperand(0).getMBB(); 1702 continue; 1703 } 1704 1705 // If the block has any instructions after a JMP, delete them. 1706 while (llvm::next(I) != MBB.end()) 1707 llvm::next(I)->eraseFromParent(); 1708 1709 Cond.clear(); 1710 FBB = 0; 1711 1712 // Delete the JMP if it's equivalent to a fall-through. 1713 if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) { 1714 TBB = 0; 1715 I->eraseFromParent(); 1716 I = MBB.end(); 1717 UnCondBrIter = MBB.end(); 1718 continue; 1719 } 1720 1721 // TBB is used to indicate the unconditional destination. 1722 TBB = I->getOperand(0).getMBB(); 1723 continue; 1724 } 1725 1726 // Handle conditional branches. 1727 X86::CondCode BranchCode = GetCondFromBranchOpc(I->getOpcode()); 1728 if (BranchCode == X86::COND_INVALID) 1729 return true; // Can't handle indirect branch. 1730 1731 // Working from the bottom, handle the first conditional branch. 1732 if (Cond.empty()) { 1733 MachineBasicBlock *TargetBB = I->getOperand(0).getMBB(); 1734 if (AllowModify && UnCondBrIter != MBB.end() && 1735 MBB.isLayoutSuccessor(TargetBB)) { 1736 // If we can modify the code and it ends in something like: 1737 // 1738 // jCC L1 1739 // jmp L2 1740 // L1: 1741 // ... 1742 // L2: 1743 // 1744 // Then we can change this to: 1745 // 1746 // jnCC L2 1747 // L1: 1748 // ... 1749 // L2: 1750 // 1751 // Which is a bit more efficient. 1752 // We conditionally jump to the fall-through block. 1753 BranchCode = GetOppositeBranchCondition(BranchCode); 1754 unsigned JNCC = GetCondBranchFromCond(BranchCode); 1755 MachineBasicBlock::iterator OldInst = I; 1756 1757 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(JNCC)) 1758 .addMBB(UnCondBrIter->getOperand(0).getMBB()); 1759 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(X86::JMP_4)) 1760 .addMBB(TargetBB); 1761 MBB.addSuccessor(TargetBB); 1762 1763 OldInst->eraseFromParent(); 1764 UnCondBrIter->eraseFromParent(); 1765 1766 // Restart the analysis. 1767 UnCondBrIter = MBB.end(); 1768 I = MBB.end(); 1769 continue; 1770 } 1771 1772 FBB = TBB; 1773 TBB = I->getOperand(0).getMBB(); 1774 Cond.push_back(MachineOperand::CreateImm(BranchCode)); 1775 continue; 1776 } 1777 1778 // Handle subsequent conditional branches. Only handle the case where all 1779 // conditional branches branch to the same destination and their condition 1780 // opcodes fit one of the special multi-branch idioms. 1781 assert(Cond.size() == 1); 1782 assert(TBB); 1783 1784 // Only handle the case where all conditional branches branch to the same 1785 // destination. 1786 if (TBB != I->getOperand(0).getMBB()) 1787 return true; 1788 1789 // If the conditions are the same, we can leave them alone. 1790 X86::CondCode OldBranchCode = (X86::CondCode)Cond[0].getImm(); 1791 if (OldBranchCode == BranchCode) 1792 continue; 1793 1794 // If they differ, see if they fit one of the known patterns. Theoretically, 1795 // we could handle more patterns here, but we shouldn't expect to see them 1796 // if instruction selection has done a reasonable job. 1797 if ((OldBranchCode == X86::COND_NP && 1798 BranchCode == X86::COND_E) || 1799 (OldBranchCode == X86::COND_E && 1800 BranchCode == X86::COND_NP)) 1801 BranchCode = X86::COND_NP_OR_E; 1802 else if ((OldBranchCode == X86::COND_P && 1803 BranchCode == X86::COND_NE) || 1804 (OldBranchCode == X86::COND_NE && 1805 BranchCode == X86::COND_P)) 1806 BranchCode = X86::COND_NE_OR_P; 1807 else 1808 return true; 1809 1810 // Update the MachineOperand. 1811 Cond[0].setImm(BranchCode); 1812 } 1813 1814 return false; 1815} 1816 1817unsigned X86InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const { 1818 MachineBasicBlock::iterator I = MBB.end(); 1819 unsigned Count = 0; 1820 1821 while (I != MBB.begin()) { 1822 --I; 1823 if (I->isDebugValue()) 1824 continue; 1825 if (I->getOpcode() != X86::JMP_4 && 1826 GetCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID) 1827 break; 1828 // Remove the branch. 1829 I->eraseFromParent(); 1830 I = MBB.end(); 1831 ++Count; 1832 } 1833 1834 return Count; 1835} 1836 1837unsigned 1838X86InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 1839 MachineBasicBlock *FBB, 1840 const SmallVectorImpl<MachineOperand> &Cond, 1841 DebugLoc DL) const { 1842 // Shouldn't be a fall through. 1843 assert(TBB && "InsertBranch must not be told to insert a fallthrough"); 1844 assert((Cond.size() == 1 || Cond.size() == 0) && 1845 "X86 branch conditions have one component!"); 1846 1847 if (Cond.empty()) { 1848 // Unconditional branch? 1849 assert(!FBB && "Unconditional branch with multiple successors!"); 1850 BuildMI(&MBB, DL, get(X86::JMP_4)).addMBB(TBB); 1851 return 1; 1852 } 1853 1854 // Conditional branch. 1855 unsigned Count = 0; 1856 X86::CondCode CC = (X86::CondCode)Cond[0].getImm(); 1857 switch (CC) { 1858 case X86::COND_NP_OR_E: 1859 // Synthesize NP_OR_E with two branches. 1860 BuildMI(&MBB, DL, get(X86::JNP_4)).addMBB(TBB); 1861 ++Count; 1862 BuildMI(&MBB, DL, get(X86::JE_4)).addMBB(TBB); 1863 ++Count; 1864 break; 1865 case X86::COND_NE_OR_P: 1866 // Synthesize NE_OR_P with two branches. 1867 BuildMI(&MBB, DL, get(X86::JNE_4)).addMBB(TBB); 1868 ++Count; 1869 BuildMI(&MBB, DL, get(X86::JP_4)).addMBB(TBB); 1870 ++Count; 1871 break; 1872 default: { 1873 unsigned Opc = GetCondBranchFromCond(CC); 1874 BuildMI(&MBB, DL, get(Opc)).addMBB(TBB); 1875 ++Count; 1876 } 1877 } 1878 if (FBB) { 1879 // Two-way Conditional branch. Insert the second branch. 1880 BuildMI(&MBB, DL, get(X86::JMP_4)).addMBB(FBB); 1881 ++Count; 1882 } 1883 return Count; 1884} 1885 1886/// isHReg - Test if the given register is a physical h register. 1887static bool isHReg(unsigned Reg) { 1888 return X86::GR8_ABCD_HRegClass.contains(Reg); 1889} 1890 1891bool X86InstrInfo::copyRegToReg(MachineBasicBlock &MBB, 1892 MachineBasicBlock::iterator MI, 1893 unsigned DestReg, unsigned SrcReg, 1894 const TargetRegisterClass *DestRC, 1895 const TargetRegisterClass *SrcRC, 1896 DebugLoc DL) const { 1897 1898 // Determine if DstRC and SrcRC have a common superclass in common. 1899 const TargetRegisterClass *CommonRC = DestRC; 1900 if (DestRC == SrcRC) 1901 /* Source and destination have the same register class. */; 1902 else if (CommonRC->hasSuperClass(SrcRC)) 1903 CommonRC = SrcRC; 1904 else if (!DestRC->hasSubClass(SrcRC)) { 1905 // Neither of GR64_NOREX or GR64_NOSP is a superclass of the other, 1906 // but we want to copy them as GR64. Similarly, for GR32_NOREX and 1907 // GR32_NOSP, copy as GR32. 1908 if (SrcRC->hasSuperClass(&X86::GR64RegClass) && 1909 DestRC->hasSuperClass(&X86::GR64RegClass)) 1910 CommonRC = &X86::GR64RegClass; 1911 else if (SrcRC->hasSuperClass(&X86::GR32RegClass) && 1912 DestRC->hasSuperClass(&X86::GR32RegClass)) 1913 CommonRC = &X86::GR32RegClass; 1914 else if (SrcRC->hasSuperClass(&X86::GR8RegClass) && 1915 DestRC->hasSuperClass(&X86::GR8RegClass)) 1916 CommonRC = &X86::GR8RegClass; 1917 else 1918 CommonRC = 0; 1919 } 1920 1921 if (CommonRC) { 1922 unsigned Opc; 1923 if (CommonRC == &X86::GR64RegClass || CommonRC == &X86::GR64_NOSPRegClass) { 1924 Opc = X86::MOV64rr; 1925 } else if (CommonRC == &X86::GR32RegClass || 1926 CommonRC == &X86::GR32_NOSPRegClass) { 1927 Opc = X86::MOV32rr; 1928 } else if (CommonRC == &X86::GR16RegClass) { 1929 Opc = X86::MOV16rr; 1930 } else if (CommonRC == &X86::GR8RegClass) { 1931 // Copying to or from a physical H register on x86-64 requires a NOREX 1932 // move. Otherwise use a normal move. 1933 if ((isHReg(DestReg) || isHReg(SrcReg) || 1934 SrcRC == &X86::GR8_ABCD_HRegClass || 1935 DestRC == &X86::GR8_ABCD_HRegClass) && 1936 TM.getSubtarget<X86Subtarget>().is64Bit()) 1937 Opc = X86::MOV8rr_NOREX; 1938 else 1939 Opc = X86::MOV8rr; 1940 } else if (CommonRC == &X86::GR64_ABCDRegClass) { 1941 Opc = X86::MOV64rr; 1942 } else if (CommonRC == &X86::GR32_ABCDRegClass) { 1943 Opc = X86::MOV32rr; 1944 } else if (CommonRC == &X86::GR16_ABCDRegClass) { 1945 Opc = X86::MOV16rr; 1946 } else if (CommonRC == &X86::GR8_ABCD_LRegClass) { 1947 Opc = X86::MOV8rr; 1948 } else if (CommonRC == &X86::GR8_ABCD_HRegClass) { 1949 if (TM.getSubtarget<X86Subtarget>().is64Bit()) 1950 Opc = X86::MOV8rr_NOREX; 1951 else 1952 Opc = X86::MOV8rr; 1953 } else if (CommonRC == &X86::GR64_NOREXRegClass || 1954 CommonRC == &X86::GR64_NOREX_NOSPRegClass) { 1955 Opc = X86::MOV64rr; 1956 } else if (CommonRC == &X86::GR32_NOREXRegClass) { 1957 Opc = X86::MOV32rr; 1958 } else if (CommonRC == &X86::GR16_NOREXRegClass) { 1959 Opc = X86::MOV16rr; 1960 } else if (CommonRC == &X86::GR8_NOREXRegClass) { 1961 Opc = X86::MOV8rr; 1962 } else if (CommonRC == &X86::GR64_TCRegClass) { 1963 Opc = X86::MOV64rr_TC; 1964 } else if (CommonRC == &X86::GR32_TCRegClass) { 1965 Opc = X86::MOV32rr_TC; 1966 } else if (CommonRC == &X86::RFP32RegClass) { 1967 Opc = X86::MOV_Fp3232; 1968 } else if (CommonRC == &X86::RFP64RegClass || CommonRC == &X86::RSTRegClass) { 1969 Opc = X86::MOV_Fp6464; 1970 } else if (CommonRC == &X86::RFP80RegClass) { 1971 Opc = X86::MOV_Fp8080; 1972 } else if (CommonRC == &X86::FR32RegClass) { 1973 Opc = X86::FsMOVAPSrr; 1974 } else if (CommonRC == &X86::FR64RegClass) { 1975 Opc = X86::FsMOVAPDrr; 1976 } else if (CommonRC == &X86::VR128RegClass) { 1977 Opc = X86::MOVAPSrr; 1978 } else if (CommonRC == &X86::VR64RegClass) { 1979 Opc = X86::MMX_MOVQ64rr; 1980 } else { 1981 return false; 1982 } 1983 BuildMI(MBB, MI, DL, get(Opc), DestReg).addReg(SrcReg); 1984 return true; 1985 } 1986 1987 // Moving EFLAGS to / from another register requires a push and a pop. 1988 if (SrcRC == &X86::CCRRegClass) { 1989 if (SrcReg != X86::EFLAGS) 1990 return false; 1991 if (DestRC == &X86::GR64RegClass || DestRC == &X86::GR64_NOSPRegClass) { 1992 BuildMI(MBB, MI, DL, get(X86::PUSHF64)); 1993 BuildMI(MBB, MI, DL, get(X86::POP64r), DestReg); 1994 return true; 1995 } else if (DestRC == &X86::GR32RegClass || 1996 DestRC == &X86::GR32_NOSPRegClass) { 1997 BuildMI(MBB, MI, DL, get(X86::PUSHF32)); 1998 BuildMI(MBB, MI, DL, get(X86::POP32r), DestReg); 1999 return true; 2000 } 2001 } else if (DestRC == &X86::CCRRegClass) { 2002 if (DestReg != X86::EFLAGS) 2003 return false; 2004 if (SrcRC == &X86::GR64RegClass || DestRC == &X86::GR64_NOSPRegClass) { 2005 BuildMI(MBB, MI, DL, get(X86::PUSH64r)).addReg(SrcReg); 2006 BuildMI(MBB, MI, DL, get(X86::POPF64)); 2007 return true; 2008 } else if (SrcRC == &X86::GR32RegClass || 2009 DestRC == &X86::GR32_NOSPRegClass) { 2010 BuildMI(MBB, MI, DL, get(X86::PUSH32r)).addReg(SrcReg); 2011 BuildMI(MBB, MI, DL, get(X86::POPF32)); 2012 return true; 2013 } 2014 } 2015 2016 // Moving from ST(0) turns into FpGET_ST0_32 etc. 2017 if (SrcRC == &X86::RSTRegClass) { 2018 // Copying from ST(0)/ST(1). 2019 if (SrcReg != X86::ST0 && SrcReg != X86::ST1) 2020 // Can only copy from ST(0)/ST(1) right now 2021 return false; 2022 bool isST0 = SrcReg == X86::ST0; 2023 unsigned Opc; 2024 if (DestRC == &X86::RFP32RegClass) 2025 Opc = isST0 ? X86::FpGET_ST0_32 : X86::FpGET_ST1_32; 2026 else if (DestRC == &X86::RFP64RegClass) 2027 Opc = isST0 ? X86::FpGET_ST0_64 : X86::FpGET_ST1_64; 2028 else { 2029 if (DestRC != &X86::RFP80RegClass) 2030 return false; 2031 Opc = isST0 ? X86::FpGET_ST0_80 : X86::FpGET_ST1_80; 2032 } 2033 BuildMI(MBB, MI, DL, get(Opc), DestReg); 2034 return true; 2035 } 2036 2037 // Moving to ST(0) turns into FpSET_ST0_32 etc. 2038 if (DestRC == &X86::RSTRegClass) { 2039 // Copying to ST(0) / ST(1). 2040 if (DestReg != X86::ST0 && DestReg != X86::ST1) 2041 // Can only copy to TOS right now 2042 return false; 2043 bool isST0 = DestReg == X86::ST0; 2044 unsigned Opc; 2045 if (SrcRC == &X86::RFP32RegClass) 2046 Opc = isST0 ? X86::FpSET_ST0_32 : X86::FpSET_ST1_32; 2047 else if (SrcRC == &X86::RFP64RegClass) 2048 Opc = isST0 ? X86::FpSET_ST0_64 : X86::FpSET_ST1_64; 2049 else { 2050 if (SrcRC != &X86::RFP80RegClass) 2051 return false; 2052 Opc = isST0 ? X86::FpSET_ST0_80 : X86::FpSET_ST1_80; 2053 } 2054 BuildMI(MBB, MI, DL, get(Opc)).addReg(SrcReg); 2055 return true; 2056 } 2057 2058 // Not yet supported! 2059 return false; 2060} 2061 2062static unsigned getLoadStoreRegOpcode(unsigned Reg, 2063 const TargetRegisterClass *RC, 2064 bool isStackAligned, 2065 const TargetMachine &TM, 2066 bool load) { 2067 if (RC == &X86::GR64RegClass || RC == &X86::GR64_NOSPRegClass) { 2068 return load ? X86::MOV64rm : X86::MOV64mr; 2069 } else if (RC == &X86::GR32RegClass || RC == &X86::GR32_NOSPRegClass) { 2070 return load ? X86::MOV32rm : X86::MOV32mr; 2071 } else if (RC == &X86::GR16RegClass) { 2072 return load ? X86::MOV16rm : X86::MOV16mr; 2073 } else if (RC == &X86::GR8RegClass) { 2074 // Copying to or from a physical H register on x86-64 requires a NOREX 2075 // move. Otherwise use a normal move. 2076 if (isHReg(Reg) && 2077 TM.getSubtarget<X86Subtarget>().is64Bit()) 2078 return load ? X86::MOV8rm_NOREX : X86::MOV8mr_NOREX; 2079 else 2080 return load ? X86::MOV8rm : X86::MOV8mr; 2081 } else if (RC == &X86::GR64_ABCDRegClass) { 2082 return load ? X86::MOV64rm : X86::MOV64mr; 2083 } else if (RC == &X86::GR32_ABCDRegClass) { 2084 return load ? X86::MOV32rm : X86::MOV32mr; 2085 } else if (RC == &X86::GR16_ABCDRegClass) { 2086 return load ? X86::MOV16rm : X86::MOV16mr; 2087 } else if (RC == &X86::GR8_ABCD_LRegClass) { 2088 return load ? X86::MOV8rm :X86::MOV8mr; 2089 } else if (RC == &X86::GR8_ABCD_HRegClass) { 2090 if (TM.getSubtarget<X86Subtarget>().is64Bit()) 2091 return load ? X86::MOV8rm_NOREX : X86::MOV8mr_NOREX; 2092 else 2093 return load ? X86::MOV8rm : X86::MOV8mr; 2094 } else if (RC == &X86::GR64_NOREXRegClass || 2095 RC == &X86::GR64_NOREX_NOSPRegClass) { 2096 return load ? X86::MOV64rm : X86::MOV64mr; 2097 } else if (RC == &X86::GR32_NOREXRegClass) { 2098 return load ? X86::MOV32rm : X86::MOV32mr; 2099 } else if (RC == &X86::GR16_NOREXRegClass) { 2100 return load ? X86::MOV16rm : X86::MOV16mr; 2101 } else if (RC == &X86::GR8_NOREXRegClass) { 2102 return load ? X86::MOV8rm : X86::MOV8mr; 2103 } else if (RC == &X86::GR64_TCRegClass) { 2104 return load ? X86::MOV64rm_TC : X86::MOV64mr_TC; 2105 } else if (RC == &X86::GR32_TCRegClass) { 2106 return load ? X86::MOV32rm_TC : X86::MOV32mr_TC; 2107 } else if (RC == &X86::RFP80RegClass) { 2108 return load ? X86::LD_Fp80m : X86::ST_FpP80m; 2109 } else if (RC == &X86::RFP64RegClass) { 2110 return load ? X86::LD_Fp64m : X86::ST_Fp64m; 2111 } else if (RC == &X86::RFP32RegClass) { 2112 return load ? X86::LD_Fp32m : X86::ST_Fp32m; 2113 } else if (RC == &X86::FR32RegClass) { 2114 return load ? X86::MOVSSrm : X86::MOVSSmr; 2115 } else if (RC == &X86::FR64RegClass) { 2116 return load ? X86::MOVSDrm : X86::MOVSDmr; 2117 } else if (RC == &X86::VR128RegClass) { 2118 // If stack is realigned we can use aligned stores. 2119 if (isStackAligned) 2120 return load ? X86::MOVAPSrm : X86::MOVAPSmr; 2121 else 2122 return load ? X86::MOVUPSrm : X86::MOVUPSmr; 2123 } else if (RC == &X86::VR64RegClass) { 2124 return load ? X86::MMX_MOVQ64rm : X86::MMX_MOVQ64mr; 2125 } else { 2126 llvm_unreachable("Unknown regclass"); 2127 } 2128} 2129 2130static unsigned getStoreRegOpcode(unsigned SrcReg, 2131 const TargetRegisterClass *RC, 2132 bool isStackAligned, 2133 TargetMachine &TM) { 2134 return getLoadStoreRegOpcode(SrcReg, RC, isStackAligned, TM, false); 2135} 2136 2137 2138static unsigned getLoadRegOpcode(unsigned DestReg, 2139 const TargetRegisterClass *RC, 2140 bool isStackAligned, 2141 const TargetMachine &TM) { 2142 return getLoadStoreRegOpcode(DestReg, RC, isStackAligned, TM, true); 2143} 2144 2145void X86InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, 2146 MachineBasicBlock::iterator MI, 2147 unsigned SrcReg, bool isKill, int FrameIdx, 2148 const TargetRegisterClass *RC, 2149 const TargetRegisterInfo *TRI) const { 2150 const MachineFunction &MF = *MBB.getParent(); 2151 bool isAligned = (RI.getStackAlignment() >= 16) || RI.canRealignStack(MF); 2152 unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, TM); 2153 DebugLoc DL = MBB.findDebugLoc(MI); 2154 addFrameReference(BuildMI(MBB, MI, DL, get(Opc)), FrameIdx) 2155 .addReg(SrcReg, getKillRegState(isKill)); 2156} 2157 2158void X86InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, 2159 bool isKill, 2160 SmallVectorImpl<MachineOperand> &Addr, 2161 const TargetRegisterClass *RC, 2162 MachineInstr::mmo_iterator MMOBegin, 2163 MachineInstr::mmo_iterator MMOEnd, 2164 SmallVectorImpl<MachineInstr*> &NewMIs) const { 2165 bool isAligned = *MMOBegin && (*MMOBegin)->getAlignment() >= 16; 2166 unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, TM); 2167 DebugLoc DL; 2168 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc)); 2169 for (unsigned i = 0, e = Addr.size(); i != e; ++i) 2170 MIB.addOperand(Addr[i]); 2171 MIB.addReg(SrcReg, getKillRegState(isKill)); 2172 (*MIB).setMemRefs(MMOBegin, MMOEnd); 2173 NewMIs.push_back(MIB); 2174} 2175 2176 2177void X86InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, 2178 MachineBasicBlock::iterator MI, 2179 unsigned DestReg, int FrameIdx, 2180 const TargetRegisterClass *RC, 2181 const TargetRegisterInfo *TRI) const { 2182 const MachineFunction &MF = *MBB.getParent(); 2183 bool isAligned = (RI.getStackAlignment() >= 16) || RI.canRealignStack(MF); 2184 unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, TM); 2185 DebugLoc DL = MBB.findDebugLoc(MI); 2186 addFrameReference(BuildMI(MBB, MI, DL, get(Opc), DestReg), FrameIdx); 2187} 2188 2189void X86InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg, 2190 SmallVectorImpl<MachineOperand> &Addr, 2191 const TargetRegisterClass *RC, 2192 MachineInstr::mmo_iterator MMOBegin, 2193 MachineInstr::mmo_iterator MMOEnd, 2194 SmallVectorImpl<MachineInstr*> &NewMIs) const { 2195 bool isAligned = *MMOBegin && (*MMOBegin)->getAlignment() >= 16; 2196 unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, TM); 2197 DebugLoc DL; 2198 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg); 2199 for (unsigned i = 0, e = Addr.size(); i != e; ++i) 2200 MIB.addOperand(Addr[i]); 2201 (*MIB).setMemRefs(MMOBegin, MMOEnd); 2202 NewMIs.push_back(MIB); 2203} 2204 2205bool X86InstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB, 2206 MachineBasicBlock::iterator MI, 2207 const std::vector<CalleeSavedInfo> &CSI, 2208 const TargetRegisterInfo *TRI) const { 2209 if (CSI.empty()) 2210 return false; 2211 2212 DebugLoc DL = MBB.findDebugLoc(MI); 2213 2214 bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit(); 2215 bool isWin64 = TM.getSubtarget<X86Subtarget>().isTargetWin64(); 2216 unsigned SlotSize = is64Bit ? 8 : 4; 2217 2218 MachineFunction &MF = *MBB.getParent(); 2219 unsigned FPReg = RI.getFrameRegister(MF); 2220 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>(); 2221 unsigned CalleeFrameSize = 0; 2222 2223 unsigned Opc = is64Bit ? X86::PUSH64r : X86::PUSH32r; 2224 for (unsigned i = CSI.size(); i != 0; --i) { 2225 unsigned Reg = CSI[i-1].getReg(); 2226 // Add the callee-saved register as live-in. It's killed at the spill. 2227 MBB.addLiveIn(Reg); 2228 if (Reg == FPReg) 2229 // X86RegisterInfo::emitPrologue will handle spilling of frame register. 2230 continue; 2231 if (!X86::VR128RegClass.contains(Reg) && !isWin64) { 2232 CalleeFrameSize += SlotSize; 2233 BuildMI(MBB, MI, DL, get(Opc)).addReg(Reg, RegState::Kill); 2234 } else { 2235 storeRegToStackSlot(MBB, MI, Reg, true, CSI[i-1].getFrameIdx(), 2236 &X86::VR128RegClass, &RI); 2237 } 2238 } 2239 2240 X86FI->setCalleeSavedFrameSize(CalleeFrameSize); 2241 return true; 2242} 2243 2244bool X86InstrInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB, 2245 MachineBasicBlock::iterator MI, 2246 const std::vector<CalleeSavedInfo> &CSI, 2247 const TargetRegisterInfo *TRI) const { 2248 if (CSI.empty()) 2249 return false; 2250 2251 DebugLoc DL = MBB.findDebugLoc(MI); 2252 2253 MachineFunction &MF = *MBB.getParent(); 2254 unsigned FPReg = RI.getFrameRegister(MF); 2255 bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit(); 2256 bool isWin64 = TM.getSubtarget<X86Subtarget>().isTargetWin64(); 2257 unsigned Opc = is64Bit ? X86::POP64r : X86::POP32r; 2258 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 2259 unsigned Reg = CSI[i].getReg(); 2260 if (Reg == FPReg) 2261 // X86RegisterInfo::emitEpilogue will handle restoring of frame register. 2262 continue; 2263 if (!X86::VR128RegClass.contains(Reg) && !isWin64) { 2264 BuildMI(MBB, MI, DL, get(Opc), Reg); 2265 } else { 2266 loadRegFromStackSlot(MBB, MI, Reg, CSI[i].getFrameIdx(), 2267 &X86::VR128RegClass, &RI); 2268 } 2269 } 2270 return true; 2271} 2272 2273MachineInstr* 2274X86InstrInfo::emitFrameIndexDebugValue(MachineFunction &MF, 2275 int FrameIx, uint64_t Offset, 2276 const MDNode *MDPtr, 2277 DebugLoc DL) const { 2278 X86AddressMode AM; 2279 AM.BaseType = X86AddressMode::FrameIndexBase; 2280 AM.Base.FrameIndex = FrameIx; 2281 MachineInstrBuilder MIB = BuildMI(MF, DL, get(X86::DBG_VALUE)); 2282 addFullAddress(MIB, AM).addImm(Offset).addMetadata(MDPtr); 2283 return &*MIB; 2284} 2285 2286static MachineInstr *FuseTwoAddrInst(MachineFunction &MF, unsigned Opcode, 2287 const SmallVectorImpl<MachineOperand> &MOs, 2288 MachineInstr *MI, 2289 const TargetInstrInfo &TII) { 2290 // Create the base instruction with the memory operand as the first part. 2291 MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode), 2292 MI->getDebugLoc(), true); 2293 MachineInstrBuilder MIB(NewMI); 2294 unsigned NumAddrOps = MOs.size(); 2295 for (unsigned i = 0; i != NumAddrOps; ++i) 2296 MIB.addOperand(MOs[i]); 2297 if (NumAddrOps < 4) // FrameIndex only 2298 addOffset(MIB, 0); 2299 2300 // Loop over the rest of the ri operands, converting them over. 2301 unsigned NumOps = MI->getDesc().getNumOperands()-2; 2302 for (unsigned i = 0; i != NumOps; ++i) { 2303 MachineOperand &MO = MI->getOperand(i+2); 2304 MIB.addOperand(MO); 2305 } 2306 for (unsigned i = NumOps+2, e = MI->getNumOperands(); i != e; ++i) { 2307 MachineOperand &MO = MI->getOperand(i); 2308 MIB.addOperand(MO); 2309 } 2310 return MIB; 2311} 2312 2313static MachineInstr *FuseInst(MachineFunction &MF, 2314 unsigned Opcode, unsigned OpNo, 2315 const SmallVectorImpl<MachineOperand> &MOs, 2316 MachineInstr *MI, const TargetInstrInfo &TII) { 2317 MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode), 2318 MI->getDebugLoc(), true); 2319 MachineInstrBuilder MIB(NewMI); 2320 2321 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 2322 MachineOperand &MO = MI->getOperand(i); 2323 if (i == OpNo) { 2324 assert(MO.isReg() && "Expected to fold into reg operand!"); 2325 unsigned NumAddrOps = MOs.size(); 2326 for (unsigned i = 0; i != NumAddrOps; ++i) 2327 MIB.addOperand(MOs[i]); 2328 if (NumAddrOps < 4) // FrameIndex only 2329 addOffset(MIB, 0); 2330 } else { 2331 MIB.addOperand(MO); 2332 } 2333 } 2334 return MIB; 2335} 2336 2337static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode, 2338 const SmallVectorImpl<MachineOperand> &MOs, 2339 MachineInstr *MI) { 2340 MachineFunction &MF = *MI->getParent()->getParent(); 2341 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), TII.get(Opcode)); 2342 2343 unsigned NumAddrOps = MOs.size(); 2344 for (unsigned i = 0; i != NumAddrOps; ++i) 2345 MIB.addOperand(MOs[i]); 2346 if (NumAddrOps < 4) // FrameIndex only 2347 addOffset(MIB, 0); 2348 return MIB.addImm(0); 2349} 2350 2351MachineInstr* 2352X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF, 2353 MachineInstr *MI, unsigned i, 2354 const SmallVectorImpl<MachineOperand> &MOs, 2355 unsigned Size, unsigned Align) const { 2356 const DenseMap<unsigned*, std::pair<unsigned,unsigned> > *OpcodeTablePtr=NULL; 2357 bool isTwoAddrFold = false; 2358 unsigned NumOps = MI->getDesc().getNumOperands(); 2359 bool isTwoAddr = NumOps > 1 && 2360 MI->getDesc().getOperandConstraint(1, TOI::TIED_TO) != -1; 2361 2362 MachineInstr *NewMI = NULL; 2363 // Folding a memory location into the two-address part of a two-address 2364 // instruction is different than folding it other places. It requires 2365 // replacing the *two* registers with the memory location. 2366 if (isTwoAddr && NumOps >= 2 && i < 2 && 2367 MI->getOperand(0).isReg() && 2368 MI->getOperand(1).isReg() && 2369 MI->getOperand(0).getReg() == MI->getOperand(1).getReg()) { 2370 OpcodeTablePtr = &RegOp2MemOpTable2Addr; 2371 isTwoAddrFold = true; 2372 } else if (i == 0) { // If operand 0 2373 if (MI->getOpcode() == X86::MOV64r0) 2374 NewMI = MakeM0Inst(*this, X86::MOV64mi32, MOs, MI); 2375 else if (MI->getOpcode() == X86::MOV32r0) 2376 NewMI = MakeM0Inst(*this, X86::MOV32mi, MOs, MI); 2377 else if (MI->getOpcode() == X86::MOV16r0) 2378 NewMI = MakeM0Inst(*this, X86::MOV16mi, MOs, MI); 2379 else if (MI->getOpcode() == X86::MOV8r0) 2380 NewMI = MakeM0Inst(*this, X86::MOV8mi, MOs, MI); 2381 if (NewMI) 2382 return NewMI; 2383 2384 OpcodeTablePtr = &RegOp2MemOpTable0; 2385 } else if (i == 1) { 2386 OpcodeTablePtr = &RegOp2MemOpTable1; 2387 } else if (i == 2) { 2388 OpcodeTablePtr = &RegOp2MemOpTable2; 2389 } 2390 2391 // If table selected... 2392 if (OpcodeTablePtr) { 2393 // Find the Opcode to fuse 2394 DenseMap<unsigned*, std::pair<unsigned,unsigned> >::const_iterator I = 2395 OpcodeTablePtr->find((unsigned*)MI->getOpcode()); 2396 if (I != OpcodeTablePtr->end()) { 2397 unsigned Opcode = I->second.first; 2398 unsigned MinAlign = I->second.second; 2399 if (Align < MinAlign) 2400 return NULL; 2401 bool NarrowToMOV32rm = false; 2402 if (Size) { 2403 unsigned RCSize = MI->getDesc().OpInfo[i].getRegClass(&RI)->getSize(); 2404 if (Size < RCSize) { 2405 // Check if it's safe to fold the load. If the size of the object is 2406 // narrower than the load width, then it's not. 2407 if (Opcode != X86::MOV64rm || RCSize != 8 || Size != 4) 2408 return NULL; 2409 // If this is a 64-bit load, but the spill slot is 32, then we can do 2410 // a 32-bit load which is implicitly zero-extended. This likely is due 2411 // to liveintervalanalysis remat'ing a load from stack slot. 2412 if (MI->getOperand(0).getSubReg() || MI->getOperand(1).getSubReg()) 2413 return NULL; 2414 Opcode = X86::MOV32rm; 2415 NarrowToMOV32rm = true; 2416 } 2417 } 2418 2419 if (isTwoAddrFold) 2420 NewMI = FuseTwoAddrInst(MF, Opcode, MOs, MI, *this); 2421 else 2422 NewMI = FuseInst(MF, Opcode, i, MOs, MI, *this); 2423 2424 if (NarrowToMOV32rm) { 2425 // If this is the special case where we use a MOV32rm to load a 32-bit 2426 // value and zero-extend the top bits. Change the destination register 2427 // to a 32-bit one. 2428 unsigned DstReg = NewMI->getOperand(0).getReg(); 2429 if (TargetRegisterInfo::isPhysicalRegister(DstReg)) 2430 NewMI->getOperand(0).setReg(RI.getSubReg(DstReg, 2431 X86::sub_32bit)); 2432 else 2433 NewMI->getOperand(0).setSubReg(X86::sub_32bit); 2434 } 2435 return NewMI; 2436 } 2437 } 2438 2439 // No fusion 2440 if (PrintFailedFusing) 2441 dbgs() << "We failed to fuse operand " << i << " in " << *MI; 2442 return NULL; 2443} 2444 2445 2446MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF, 2447 MachineInstr *MI, 2448 const SmallVectorImpl<unsigned> &Ops, 2449 int FrameIndex) const { 2450 // Check switch flag 2451 if (NoFusing) return NULL; 2452 2453 if (!MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize)) 2454 switch (MI->getOpcode()) { 2455 case X86::CVTSD2SSrr: 2456 case X86::Int_CVTSD2SSrr: 2457 case X86::CVTSS2SDrr: 2458 case X86::Int_CVTSS2SDrr: 2459 case X86::RCPSSr: 2460 case X86::RCPSSr_Int: 2461 case X86::ROUNDSDr_Int: 2462 case X86::ROUNDSSr_Int: 2463 case X86::RSQRTSSr: 2464 case X86::RSQRTSSr_Int: 2465 case X86::SQRTSSr: 2466 case X86::SQRTSSr_Int: 2467 return 0; 2468 } 2469 2470 const MachineFrameInfo *MFI = MF.getFrameInfo(); 2471 unsigned Size = MFI->getObjectSize(FrameIndex); 2472 unsigned Alignment = MFI->getObjectAlignment(FrameIndex); 2473 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) { 2474 unsigned NewOpc = 0; 2475 unsigned RCSize = 0; 2476 switch (MI->getOpcode()) { 2477 default: return NULL; 2478 case X86::TEST8rr: NewOpc = X86::CMP8ri; RCSize = 1; break; 2479 case X86::TEST16rr: NewOpc = X86::CMP16ri8; RCSize = 2; break; 2480 case X86::TEST32rr: NewOpc = X86::CMP32ri8; RCSize = 4; break; 2481 case X86::TEST64rr: NewOpc = X86::CMP64ri8; RCSize = 8; break; 2482 } 2483 // Check if it's safe to fold the load. If the size of the object is 2484 // narrower than the load width, then it's not. 2485 if (Size < RCSize) 2486 return NULL; 2487 // Change to CMPXXri r, 0 first. 2488 MI->setDesc(get(NewOpc)); 2489 MI->getOperand(1).ChangeToImmediate(0); 2490 } else if (Ops.size() != 1) 2491 return NULL; 2492 2493 SmallVector<MachineOperand,4> MOs; 2494 MOs.push_back(MachineOperand::CreateFI(FrameIndex)); 2495 return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, Size, Alignment); 2496} 2497 2498MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF, 2499 MachineInstr *MI, 2500 const SmallVectorImpl<unsigned> &Ops, 2501 MachineInstr *LoadMI) const { 2502 // Check switch flag 2503 if (NoFusing) return NULL; 2504 2505 if (!MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize)) 2506 switch (MI->getOpcode()) { 2507 case X86::CVTSD2SSrr: 2508 case X86::Int_CVTSD2SSrr: 2509 case X86::CVTSS2SDrr: 2510 case X86::Int_CVTSS2SDrr: 2511 case X86::RCPSSr: 2512 case X86::RCPSSr_Int: 2513 case X86::ROUNDSDr_Int: 2514 case X86::ROUNDSSr_Int: 2515 case X86::RSQRTSSr: 2516 case X86::RSQRTSSr_Int: 2517 case X86::SQRTSSr: 2518 case X86::SQRTSSr_Int: 2519 return 0; 2520 } 2521 2522 // Determine the alignment of the load. 2523 unsigned Alignment = 0; 2524 if (LoadMI->hasOneMemOperand()) 2525 Alignment = (*LoadMI->memoperands_begin())->getAlignment(); 2526 else 2527 switch (LoadMI->getOpcode()) { 2528 case X86::V_SET0PS: 2529 case X86::V_SET0PD: 2530 case X86::V_SET0PI: 2531 case X86::V_SETALLONES: 2532 Alignment = 16; 2533 break; 2534 case X86::FsFLD0SD: 2535 Alignment = 8; 2536 break; 2537 case X86::FsFLD0SS: 2538 Alignment = 4; 2539 break; 2540 default: 2541 llvm_unreachable("Don't know how to fold this instruction!"); 2542 } 2543 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) { 2544 unsigned NewOpc = 0; 2545 switch (MI->getOpcode()) { 2546 default: return NULL; 2547 case X86::TEST8rr: NewOpc = X86::CMP8ri; break; 2548 case X86::TEST16rr: NewOpc = X86::CMP16ri8; break; 2549 case X86::TEST32rr: NewOpc = X86::CMP32ri8; break; 2550 case X86::TEST64rr: NewOpc = X86::CMP64ri8; break; 2551 } 2552 // Change to CMPXXri r, 0 first. 2553 MI->setDesc(get(NewOpc)); 2554 MI->getOperand(1).ChangeToImmediate(0); 2555 } else if (Ops.size() != 1) 2556 return NULL; 2557 2558 SmallVector<MachineOperand,X86AddrNumOperands> MOs; 2559 switch (LoadMI->getOpcode()) { 2560 case X86::V_SET0PS: 2561 case X86::V_SET0PD: 2562 case X86::V_SET0PI: 2563 case X86::V_SETALLONES: 2564 case X86::FsFLD0SD: 2565 case X86::FsFLD0SS: { 2566 // Folding a V_SET0P? or V_SETALLONES as a load, to ease register pressure. 2567 // Create a constant-pool entry and operands to load from it. 2568 2569 // Medium and large mode can't fold loads this way. 2570 if (TM.getCodeModel() != CodeModel::Small && 2571 TM.getCodeModel() != CodeModel::Kernel) 2572 return NULL; 2573 2574 // x86-32 PIC requires a PIC base register for constant pools. 2575 unsigned PICBase = 0; 2576 if (TM.getRelocationModel() == Reloc::PIC_) { 2577 if (TM.getSubtarget<X86Subtarget>().is64Bit()) 2578 PICBase = X86::RIP; 2579 else 2580 // FIXME: PICBase = TM.getInstrInfo()->getGlobalBaseReg(&MF); 2581 // This doesn't work for several reasons. 2582 // 1. GlobalBaseReg may have been spilled. 2583 // 2. It may not be live at MI. 2584 return NULL; 2585 } 2586 2587 // Create a constant-pool entry. 2588 MachineConstantPool &MCP = *MF.getConstantPool(); 2589 const Type *Ty; 2590 if (LoadMI->getOpcode() == X86::FsFLD0SS) 2591 Ty = Type::getFloatTy(MF.getFunction()->getContext()); 2592 else if (LoadMI->getOpcode() == X86::FsFLD0SD) 2593 Ty = Type::getDoubleTy(MF.getFunction()->getContext()); 2594 else 2595 Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 4); 2596 const Constant *C = LoadMI->getOpcode() == X86::V_SETALLONES ? 2597 Constant::getAllOnesValue(Ty) : 2598 Constant::getNullValue(Ty); 2599 unsigned CPI = MCP.getConstantPoolIndex(C, Alignment); 2600 2601 // Create operands to load from the constant pool entry. 2602 MOs.push_back(MachineOperand::CreateReg(PICBase, false)); 2603 MOs.push_back(MachineOperand::CreateImm(1)); 2604 MOs.push_back(MachineOperand::CreateReg(0, false)); 2605 MOs.push_back(MachineOperand::CreateCPI(CPI, 0)); 2606 MOs.push_back(MachineOperand::CreateReg(0, false)); 2607 break; 2608 } 2609 default: { 2610 // Folding a normal load. Just copy the load's address operands. 2611 unsigned NumOps = LoadMI->getDesc().getNumOperands(); 2612 for (unsigned i = NumOps - X86AddrNumOperands; i != NumOps; ++i) 2613 MOs.push_back(LoadMI->getOperand(i)); 2614 break; 2615 } 2616 } 2617 return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, 0, Alignment); 2618} 2619 2620 2621bool X86InstrInfo::canFoldMemoryOperand(const MachineInstr *MI, 2622 const SmallVectorImpl<unsigned> &Ops) const { 2623 // Check switch flag 2624 if (NoFusing) return 0; 2625 2626 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) { 2627 switch (MI->getOpcode()) { 2628 default: return false; 2629 case X86::TEST8rr: 2630 case X86::TEST16rr: 2631 case X86::TEST32rr: 2632 case X86::TEST64rr: 2633 return true; 2634 } 2635 } 2636 2637 if (Ops.size() != 1) 2638 return false; 2639 2640 unsigned OpNum = Ops[0]; 2641 unsigned Opc = MI->getOpcode(); 2642 unsigned NumOps = MI->getDesc().getNumOperands(); 2643 bool isTwoAddr = NumOps > 1 && 2644 MI->getDesc().getOperandConstraint(1, TOI::TIED_TO) != -1; 2645 2646 // Folding a memory location into the two-address part of a two-address 2647 // instruction is different than folding it other places. It requires 2648 // replacing the *two* registers with the memory location. 2649 const DenseMap<unsigned*, std::pair<unsigned,unsigned> > *OpcodeTablePtr=NULL; 2650 if (isTwoAddr && NumOps >= 2 && OpNum < 2) { 2651 OpcodeTablePtr = &RegOp2MemOpTable2Addr; 2652 } else if (OpNum == 0) { // If operand 0 2653 switch (Opc) { 2654 case X86::MOV8r0: 2655 case X86::MOV16r0: 2656 case X86::MOV32r0: 2657 case X86::MOV64r0: 2658 return true; 2659 default: break; 2660 } 2661 OpcodeTablePtr = &RegOp2MemOpTable0; 2662 } else if (OpNum == 1) { 2663 OpcodeTablePtr = &RegOp2MemOpTable1; 2664 } else if (OpNum == 2) { 2665 OpcodeTablePtr = &RegOp2MemOpTable2; 2666 } 2667 2668 if (OpcodeTablePtr) { 2669 // Find the Opcode to fuse 2670 DenseMap<unsigned*, std::pair<unsigned,unsigned> >::const_iterator I = 2671 OpcodeTablePtr->find((unsigned*)Opc); 2672 if (I != OpcodeTablePtr->end()) 2673 return true; 2674 } 2675 return false; 2676} 2677 2678bool X86InstrInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, 2679 unsigned Reg, bool UnfoldLoad, bool UnfoldStore, 2680 SmallVectorImpl<MachineInstr*> &NewMIs) const { 2681 DenseMap<unsigned*, std::pair<unsigned,unsigned> >::const_iterator I = 2682 MemOp2RegOpTable.find((unsigned*)MI->getOpcode()); 2683 if (I == MemOp2RegOpTable.end()) 2684 return false; 2685 unsigned Opc = I->second.first; 2686 unsigned Index = I->second.second & 0xf; 2687 bool FoldedLoad = I->second.second & (1 << 4); 2688 bool FoldedStore = I->second.second & (1 << 5); 2689 if (UnfoldLoad && !FoldedLoad) 2690 return false; 2691 UnfoldLoad &= FoldedLoad; 2692 if (UnfoldStore && !FoldedStore) 2693 return false; 2694 UnfoldStore &= FoldedStore; 2695 2696 const TargetInstrDesc &TID = get(Opc); 2697 const TargetOperandInfo &TOI = TID.OpInfo[Index]; 2698 const TargetRegisterClass *RC = TOI.getRegClass(&RI); 2699 if (!MI->hasOneMemOperand() && 2700 RC == &X86::VR128RegClass && 2701 !TM.getSubtarget<X86Subtarget>().isUnalignedMemAccessFast()) 2702 // Without memoperands, loadRegFromAddr and storeRegToStackSlot will 2703 // conservatively assume the address is unaligned. That's bad for 2704 // performance. 2705 return false; 2706 SmallVector<MachineOperand, X86AddrNumOperands> AddrOps; 2707 SmallVector<MachineOperand,2> BeforeOps; 2708 SmallVector<MachineOperand,2> AfterOps; 2709 SmallVector<MachineOperand,4> ImpOps; 2710 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 2711 MachineOperand &Op = MI->getOperand(i); 2712 if (i >= Index && i < Index + X86AddrNumOperands) 2713 AddrOps.push_back(Op); 2714 else if (Op.isReg() && Op.isImplicit()) 2715 ImpOps.push_back(Op); 2716 else if (i < Index) 2717 BeforeOps.push_back(Op); 2718 else if (i > Index) 2719 AfterOps.push_back(Op); 2720 } 2721 2722 // Emit the load instruction. 2723 if (UnfoldLoad) { 2724 std::pair<MachineInstr::mmo_iterator, 2725 MachineInstr::mmo_iterator> MMOs = 2726 MF.extractLoadMemRefs(MI->memoperands_begin(), 2727 MI->memoperands_end()); 2728 loadRegFromAddr(MF, Reg, AddrOps, RC, MMOs.first, MMOs.second, NewMIs); 2729 if (UnfoldStore) { 2730 // Address operands cannot be marked isKill. 2731 for (unsigned i = 1; i != 1 + X86AddrNumOperands; ++i) { 2732 MachineOperand &MO = NewMIs[0]->getOperand(i); 2733 if (MO.isReg()) 2734 MO.setIsKill(false); 2735 } 2736 } 2737 } 2738 2739 // Emit the data processing instruction. 2740 MachineInstr *DataMI = MF.CreateMachineInstr(TID, MI->getDebugLoc(), true); 2741 MachineInstrBuilder MIB(DataMI); 2742 2743 if (FoldedStore) 2744 MIB.addReg(Reg, RegState::Define); 2745 for (unsigned i = 0, e = BeforeOps.size(); i != e; ++i) 2746 MIB.addOperand(BeforeOps[i]); 2747 if (FoldedLoad) 2748 MIB.addReg(Reg); 2749 for (unsigned i = 0, e = AfterOps.size(); i != e; ++i) 2750 MIB.addOperand(AfterOps[i]); 2751 for (unsigned i = 0, e = ImpOps.size(); i != e; ++i) { 2752 MachineOperand &MO = ImpOps[i]; 2753 MIB.addReg(MO.getReg(), 2754 getDefRegState(MO.isDef()) | 2755 RegState::Implicit | 2756 getKillRegState(MO.isKill()) | 2757 getDeadRegState(MO.isDead()) | 2758 getUndefRegState(MO.isUndef())); 2759 } 2760 // Change CMP32ri r, 0 back to TEST32rr r, r, etc. 2761 unsigned NewOpc = 0; 2762 switch (DataMI->getOpcode()) { 2763 default: break; 2764 case X86::CMP64ri32: 2765 case X86::CMP64ri8: 2766 case X86::CMP32ri: 2767 case X86::CMP32ri8: 2768 case X86::CMP16ri: 2769 case X86::CMP16ri8: 2770 case X86::CMP8ri: { 2771 MachineOperand &MO0 = DataMI->getOperand(0); 2772 MachineOperand &MO1 = DataMI->getOperand(1); 2773 if (MO1.getImm() == 0) { 2774 switch (DataMI->getOpcode()) { 2775 default: break; 2776 case X86::CMP64ri8: 2777 case X86::CMP64ri32: NewOpc = X86::TEST64rr; break; 2778 case X86::CMP32ri8: 2779 case X86::CMP32ri: NewOpc = X86::TEST32rr; break; 2780 case X86::CMP16ri8: 2781 case X86::CMP16ri: NewOpc = X86::TEST16rr; break; 2782 case X86::CMP8ri: NewOpc = X86::TEST8rr; break; 2783 } 2784 DataMI->setDesc(get(NewOpc)); 2785 MO1.ChangeToRegister(MO0.getReg(), false); 2786 } 2787 } 2788 } 2789 NewMIs.push_back(DataMI); 2790 2791 // Emit the store instruction. 2792 if (UnfoldStore) { 2793 const TargetRegisterClass *DstRC = TID.OpInfo[0].getRegClass(&RI); 2794 std::pair<MachineInstr::mmo_iterator, 2795 MachineInstr::mmo_iterator> MMOs = 2796 MF.extractStoreMemRefs(MI->memoperands_begin(), 2797 MI->memoperands_end()); 2798 storeRegToAddr(MF, Reg, true, AddrOps, DstRC, MMOs.first, MMOs.second, NewMIs); 2799 } 2800 2801 return true; 2802} 2803 2804bool 2805X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, 2806 SmallVectorImpl<SDNode*> &NewNodes) const { 2807 if (!N->isMachineOpcode()) 2808 return false; 2809 2810 DenseMap<unsigned*, std::pair<unsigned,unsigned> >::const_iterator I = 2811 MemOp2RegOpTable.find((unsigned*)N->getMachineOpcode()); 2812 if (I == MemOp2RegOpTable.end()) 2813 return false; 2814 unsigned Opc = I->second.first; 2815 unsigned Index = I->second.second & 0xf; 2816 bool FoldedLoad = I->second.second & (1 << 4); 2817 bool FoldedStore = I->second.second & (1 << 5); 2818 const TargetInstrDesc &TID = get(Opc); 2819 const TargetRegisterClass *RC = TID.OpInfo[Index].getRegClass(&RI); 2820 unsigned NumDefs = TID.NumDefs; 2821 std::vector<SDValue> AddrOps; 2822 std::vector<SDValue> BeforeOps; 2823 std::vector<SDValue> AfterOps; 2824 DebugLoc dl = N->getDebugLoc(); 2825 unsigned NumOps = N->getNumOperands(); 2826 for (unsigned i = 0; i != NumOps-1; ++i) { 2827 SDValue Op = N->getOperand(i); 2828 if (i >= Index-NumDefs && i < Index-NumDefs + X86AddrNumOperands) 2829 AddrOps.push_back(Op); 2830 else if (i < Index-NumDefs) 2831 BeforeOps.push_back(Op); 2832 else if (i > Index-NumDefs) 2833 AfterOps.push_back(Op); 2834 } 2835 SDValue Chain = N->getOperand(NumOps-1); 2836 AddrOps.push_back(Chain); 2837 2838 // Emit the load instruction. 2839 SDNode *Load = 0; 2840 MachineFunction &MF = DAG.getMachineFunction(); 2841 if (FoldedLoad) { 2842 EVT VT = *RC->vt_begin(); 2843 std::pair<MachineInstr::mmo_iterator, 2844 MachineInstr::mmo_iterator> MMOs = 2845 MF.extractLoadMemRefs(cast<MachineSDNode>(N)->memoperands_begin(), 2846 cast<MachineSDNode>(N)->memoperands_end()); 2847 if (!(*MMOs.first) && 2848 RC == &X86::VR128RegClass && 2849 !TM.getSubtarget<X86Subtarget>().isUnalignedMemAccessFast()) 2850 // Do not introduce a slow unaligned load. 2851 return false; 2852 bool isAligned = (*MMOs.first) && (*MMOs.first)->getAlignment() >= 16; 2853 Load = DAG.getMachineNode(getLoadRegOpcode(0, RC, isAligned, TM), dl, 2854 VT, MVT::Other, &AddrOps[0], AddrOps.size()); 2855 NewNodes.push_back(Load); 2856 2857 // Preserve memory reference information. 2858 cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second); 2859 } 2860 2861 // Emit the data processing instruction. 2862 std::vector<EVT> VTs; 2863 const TargetRegisterClass *DstRC = 0; 2864 if (TID.getNumDefs() > 0) { 2865 DstRC = TID.OpInfo[0].getRegClass(&RI); 2866 VTs.push_back(*DstRC->vt_begin()); 2867 } 2868 for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) { 2869 EVT VT = N->getValueType(i); 2870 if (VT != MVT::Other && i >= (unsigned)TID.getNumDefs()) 2871 VTs.push_back(VT); 2872 } 2873 if (Load) 2874 BeforeOps.push_back(SDValue(Load, 0)); 2875 std::copy(AfterOps.begin(), AfterOps.end(), std::back_inserter(BeforeOps)); 2876 SDNode *NewNode= DAG.getMachineNode(Opc, dl, VTs, &BeforeOps[0], 2877 BeforeOps.size()); 2878 NewNodes.push_back(NewNode); 2879 2880 // Emit the store instruction. 2881 if (FoldedStore) { 2882 AddrOps.pop_back(); 2883 AddrOps.push_back(SDValue(NewNode, 0)); 2884 AddrOps.push_back(Chain); 2885 std::pair<MachineInstr::mmo_iterator, 2886 MachineInstr::mmo_iterator> MMOs = 2887 MF.extractStoreMemRefs(cast<MachineSDNode>(N)->memoperands_begin(), 2888 cast<MachineSDNode>(N)->memoperands_end()); 2889 if (!(*MMOs.first) && 2890 RC == &X86::VR128RegClass && 2891 !TM.getSubtarget<X86Subtarget>().isUnalignedMemAccessFast()) 2892 // Do not introduce a slow unaligned store. 2893 return false; 2894 bool isAligned = (*MMOs.first) && (*MMOs.first)->getAlignment() >= 16; 2895 SDNode *Store = DAG.getMachineNode(getStoreRegOpcode(0, DstRC, 2896 isAligned, TM), 2897 dl, MVT::Other, 2898 &AddrOps[0], AddrOps.size()); 2899 NewNodes.push_back(Store); 2900 2901 // Preserve memory reference information. 2902 cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second); 2903 } 2904 2905 return true; 2906} 2907 2908unsigned X86InstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc, 2909 bool UnfoldLoad, bool UnfoldStore, 2910 unsigned *LoadRegIndex) const { 2911 DenseMap<unsigned*, std::pair<unsigned,unsigned> >::const_iterator I = 2912 MemOp2RegOpTable.find((unsigned*)Opc); 2913 if (I == MemOp2RegOpTable.end()) 2914 return 0; 2915 bool FoldedLoad = I->second.second & (1 << 4); 2916 bool FoldedStore = I->second.second & (1 << 5); 2917 if (UnfoldLoad && !FoldedLoad) 2918 return 0; 2919 if (UnfoldStore && !FoldedStore) 2920 return 0; 2921 if (LoadRegIndex) 2922 *LoadRegIndex = I->second.second & 0xf; 2923 return I->second.first; 2924} 2925 2926bool 2927X86InstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, 2928 int64_t &Offset1, int64_t &Offset2) const { 2929 if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode()) 2930 return false; 2931 unsigned Opc1 = Load1->getMachineOpcode(); 2932 unsigned Opc2 = Load2->getMachineOpcode(); 2933 switch (Opc1) { 2934 default: return false; 2935 case X86::MOV8rm: 2936 case X86::MOV16rm: 2937 case X86::MOV32rm: 2938 case X86::MOV64rm: 2939 case X86::LD_Fp32m: 2940 case X86::LD_Fp64m: 2941 case X86::LD_Fp80m: 2942 case X86::MOVSSrm: 2943 case X86::MOVSDrm: 2944 case X86::MMX_MOVD64rm: 2945 case X86::MMX_MOVQ64rm: 2946 case X86::FsMOVAPSrm: 2947 case X86::FsMOVAPDrm: 2948 case X86::MOVAPSrm: 2949 case X86::MOVUPSrm: 2950 case X86::MOVUPSrm_Int: 2951 case X86::MOVAPDrm: 2952 case X86::MOVDQArm: 2953 case X86::MOVDQUrm: 2954 case X86::MOVDQUrm_Int: 2955 break; 2956 } 2957 switch (Opc2) { 2958 default: return false; 2959 case X86::MOV8rm: 2960 case X86::MOV16rm: 2961 case X86::MOV32rm: 2962 case X86::MOV64rm: 2963 case X86::LD_Fp32m: 2964 case X86::LD_Fp64m: 2965 case X86::LD_Fp80m: 2966 case X86::MOVSSrm: 2967 case X86::MOVSDrm: 2968 case X86::MMX_MOVD64rm: 2969 case X86::MMX_MOVQ64rm: 2970 case X86::FsMOVAPSrm: 2971 case X86::FsMOVAPDrm: 2972 case X86::MOVAPSrm: 2973 case X86::MOVUPSrm: 2974 case X86::MOVUPSrm_Int: 2975 case X86::MOVAPDrm: 2976 case X86::MOVDQArm: 2977 case X86::MOVDQUrm: 2978 case X86::MOVDQUrm_Int: 2979 break; 2980 } 2981 2982 // Check if chain operands and base addresses match. 2983 if (Load1->getOperand(0) != Load2->getOperand(0) || 2984 Load1->getOperand(5) != Load2->getOperand(5)) 2985 return false; 2986 // Segment operands should match as well. 2987 if (Load1->getOperand(4) != Load2->getOperand(4)) 2988 return false; 2989 // Scale should be 1, Index should be Reg0. 2990 if (Load1->getOperand(1) == Load2->getOperand(1) && 2991 Load1->getOperand(2) == Load2->getOperand(2)) { 2992 if (cast<ConstantSDNode>(Load1->getOperand(1))->getZExtValue() != 1) 2993 return false; 2994 2995 // Now let's examine the displacements. 2996 if (isa<ConstantSDNode>(Load1->getOperand(3)) && 2997 isa<ConstantSDNode>(Load2->getOperand(3))) { 2998 Offset1 = cast<ConstantSDNode>(Load1->getOperand(3))->getSExtValue(); 2999 Offset2 = cast<ConstantSDNode>(Load2->getOperand(3))->getSExtValue(); 3000 return true; 3001 } 3002 } 3003 return false; 3004} 3005 3006bool X86InstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, 3007 int64_t Offset1, int64_t Offset2, 3008 unsigned NumLoads) const { 3009 assert(Offset2 > Offset1); 3010 if ((Offset2 - Offset1) / 8 > 64) 3011 return false; 3012 3013 unsigned Opc1 = Load1->getMachineOpcode(); 3014 unsigned Opc2 = Load2->getMachineOpcode(); 3015 if (Opc1 != Opc2) 3016 return false; // FIXME: overly conservative? 3017 3018 switch (Opc1) { 3019 default: break; 3020 case X86::LD_Fp32m: 3021 case X86::LD_Fp64m: 3022 case X86::LD_Fp80m: 3023 case X86::MMX_MOVD64rm: 3024 case X86::MMX_MOVQ64rm: 3025 return false; 3026 } 3027 3028 EVT VT = Load1->getValueType(0); 3029 switch (VT.getSimpleVT().SimpleTy) { 3030 default: 3031 // XMM registers. In 64-bit mode we can be a bit more aggressive since we 3032 // have 16 of them to play with. 3033 if (TM.getSubtargetImpl()->is64Bit()) { 3034 if (NumLoads >= 3) 3035 return false; 3036 } else if (NumLoads) { 3037 return false; 3038 } 3039 break; 3040 case MVT::i8: 3041 case MVT::i16: 3042 case MVT::i32: 3043 case MVT::i64: 3044 case MVT::f32: 3045 case MVT::f64: 3046 if (NumLoads) 3047 return false; 3048 break; 3049 } 3050 3051 return true; 3052} 3053 3054 3055bool X86InstrInfo:: 3056ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { 3057 assert(Cond.size() == 1 && "Invalid X86 branch condition!"); 3058 X86::CondCode CC = static_cast<X86::CondCode>(Cond[0].getImm()); 3059 if (CC == X86::COND_NE_OR_P || CC == X86::COND_NP_OR_E) 3060 return true; 3061 Cond[0].setImm(GetOppositeBranchCondition(CC)); 3062 return false; 3063} 3064 3065bool X86InstrInfo:: 3066isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const { 3067 // FIXME: Return false for x87 stack register classes for now. We can't 3068 // allow any loads of these registers before FpGet_ST0_80. 3069 return !(RC == &X86::CCRRegClass || RC == &X86::RFP32RegClass || 3070 RC == &X86::RFP64RegClass || RC == &X86::RFP80RegClass); 3071} 3072 3073 3074/// isX86_64ExtendedReg - Is the MachineOperand a x86-64 extended (r8 or higher) 3075/// register? e.g. r8, xmm8, xmm13, etc. 3076bool X86InstrInfo::isX86_64ExtendedReg(unsigned RegNo) { 3077 switch (RegNo) { 3078 default: break; 3079 case X86::R8: case X86::R9: case X86::R10: case X86::R11: 3080 case X86::R12: case X86::R13: case X86::R14: case X86::R15: 3081 case X86::R8D: case X86::R9D: case X86::R10D: case X86::R11D: 3082 case X86::R12D: case X86::R13D: case X86::R14D: case X86::R15D: 3083 case X86::R8W: case X86::R9W: case X86::R10W: case X86::R11W: 3084 case X86::R12W: case X86::R13W: case X86::R14W: case X86::R15W: 3085 case X86::R8B: case X86::R9B: case X86::R10B: case X86::R11B: 3086 case X86::R12B: case X86::R13B: case X86::R14B: case X86::R15B: 3087 case X86::XMM8: case X86::XMM9: case X86::XMM10: case X86::XMM11: 3088 case X86::XMM12: case X86::XMM13: case X86::XMM14: case X86::XMM15: 3089 return true; 3090 } 3091 return false; 3092} 3093 3094 3095/// determineREX - Determine if the MachineInstr has to be encoded with a X86-64 3096/// REX prefix which specifies 1) 64-bit instructions, 2) non-default operand 3097/// size, and 3) use of X86-64 extended registers. 3098unsigned X86InstrInfo::determineREX(const MachineInstr &MI) { 3099 unsigned REX = 0; 3100 const TargetInstrDesc &Desc = MI.getDesc(); 3101 3102 // Pseudo instructions do not need REX prefix byte. 3103 if ((Desc.TSFlags & X86II::FormMask) == X86II::Pseudo) 3104 return 0; 3105 if (Desc.TSFlags & X86II::REX_W) 3106 REX |= 1 << 3; 3107 3108 unsigned NumOps = Desc.getNumOperands(); 3109 if (NumOps) { 3110 bool isTwoAddr = NumOps > 1 && 3111 Desc.getOperandConstraint(1, TOI::TIED_TO) != -1; 3112 3113 // If it accesses SPL, BPL, SIL, or DIL, then it requires a 0x40 REX prefix. 3114 unsigned i = isTwoAddr ? 1 : 0; 3115 for (unsigned e = NumOps; i != e; ++i) { 3116 const MachineOperand& MO = MI.getOperand(i); 3117 if (MO.isReg()) { 3118 unsigned Reg = MO.getReg(); 3119 if (isX86_64NonExtLowByteReg(Reg)) 3120 REX |= 0x40; 3121 } 3122 } 3123 3124 switch (Desc.TSFlags & X86II::FormMask) { 3125 case X86II::MRMInitReg: 3126 if (isX86_64ExtendedReg(MI.getOperand(0))) 3127 REX |= (1 << 0) | (1 << 2); 3128 break; 3129 case X86II::MRMSrcReg: { 3130 if (isX86_64ExtendedReg(MI.getOperand(0))) 3131 REX |= 1 << 2; 3132 i = isTwoAddr ? 2 : 1; 3133 for (unsigned e = NumOps; i != e; ++i) { 3134 const MachineOperand& MO = MI.getOperand(i); 3135 if (isX86_64ExtendedReg(MO)) 3136 REX |= 1 << 0; 3137 } 3138 break; 3139 } 3140 case X86II::MRMSrcMem: { 3141 if (isX86_64ExtendedReg(MI.getOperand(0))) 3142 REX |= 1 << 2; 3143 unsigned Bit = 0; 3144 i = isTwoAddr ? 2 : 1; 3145 for (; i != NumOps; ++i) { 3146 const MachineOperand& MO = MI.getOperand(i); 3147 if (MO.isReg()) { 3148 if (isX86_64ExtendedReg(MO)) 3149 REX |= 1 << Bit; 3150 Bit++; 3151 } 3152 } 3153 break; 3154 } 3155 case X86II::MRM0m: case X86II::MRM1m: 3156 case X86II::MRM2m: case X86II::MRM3m: 3157 case X86II::MRM4m: case X86II::MRM5m: 3158 case X86II::MRM6m: case X86II::MRM7m: 3159 case X86II::MRMDestMem: { 3160 unsigned e = (isTwoAddr ? X86AddrNumOperands+1 : X86AddrNumOperands); 3161 i = isTwoAddr ? 1 : 0; 3162 if (NumOps > e && isX86_64ExtendedReg(MI.getOperand(e))) 3163 REX |= 1 << 2; 3164 unsigned Bit = 0; 3165 for (; i != e; ++i) { 3166 const MachineOperand& MO = MI.getOperand(i); 3167 if (MO.isReg()) { 3168 if (isX86_64ExtendedReg(MO)) 3169 REX |= 1 << Bit; 3170 Bit++; 3171 } 3172 } 3173 break; 3174 } 3175 default: { 3176 if (isX86_64ExtendedReg(MI.getOperand(0))) 3177 REX |= 1 << 0; 3178 i = isTwoAddr ? 2 : 1; 3179 for (unsigned e = NumOps; i != e; ++i) { 3180 const MachineOperand& MO = MI.getOperand(i); 3181 if (isX86_64ExtendedReg(MO)) 3182 REX |= 1 << 2; 3183 } 3184 break; 3185 } 3186 } 3187 } 3188 return REX; 3189} 3190 3191/// sizePCRelativeBlockAddress - This method returns the size of a PC 3192/// relative block address instruction 3193/// 3194static unsigned sizePCRelativeBlockAddress() { 3195 return 4; 3196} 3197 3198/// sizeGlobalAddress - Give the size of the emission of this global address 3199/// 3200static unsigned sizeGlobalAddress(bool dword) { 3201 return dword ? 8 : 4; 3202} 3203 3204/// sizeConstPoolAddress - Give the size of the emission of this constant 3205/// pool address 3206/// 3207static unsigned sizeConstPoolAddress(bool dword) { 3208 return dword ? 8 : 4; 3209} 3210 3211/// sizeExternalSymbolAddress - Give the size of the emission of this external 3212/// symbol 3213/// 3214static unsigned sizeExternalSymbolAddress(bool dword) { 3215 return dword ? 8 : 4; 3216} 3217 3218/// sizeJumpTableAddress - Give the size of the emission of this jump 3219/// table address 3220/// 3221static unsigned sizeJumpTableAddress(bool dword) { 3222 return dword ? 8 : 4; 3223} 3224 3225static unsigned sizeConstant(unsigned Size) { 3226 return Size; 3227} 3228 3229static unsigned sizeRegModRMByte(){ 3230 return 1; 3231} 3232 3233static unsigned sizeSIBByte(){ 3234 return 1; 3235} 3236 3237static unsigned getDisplacementFieldSize(const MachineOperand *RelocOp) { 3238 unsigned FinalSize = 0; 3239 // If this is a simple integer displacement that doesn't require a relocation. 3240 if (!RelocOp) { 3241 FinalSize += sizeConstant(4); 3242 return FinalSize; 3243 } 3244 3245 // Otherwise, this is something that requires a relocation. 3246 if (RelocOp->isGlobal()) { 3247 FinalSize += sizeGlobalAddress(false); 3248 } else if (RelocOp->isCPI()) { 3249 FinalSize += sizeConstPoolAddress(false); 3250 } else if (RelocOp->isJTI()) { 3251 FinalSize += sizeJumpTableAddress(false); 3252 } else { 3253 llvm_unreachable("Unknown value to relocate!"); 3254 } 3255 return FinalSize; 3256} 3257 3258static unsigned getMemModRMByteSize(const MachineInstr &MI, unsigned Op, 3259 bool IsPIC, bool Is64BitMode) { 3260 const MachineOperand &Op3 = MI.getOperand(Op+3); 3261 int DispVal = 0; 3262 const MachineOperand *DispForReloc = 0; 3263 unsigned FinalSize = 0; 3264 3265 // Figure out what sort of displacement we have to handle here. 3266 if (Op3.isGlobal()) { 3267 DispForReloc = &Op3; 3268 } else if (Op3.isCPI()) { 3269 if (Is64BitMode || IsPIC) { 3270 DispForReloc = &Op3; 3271 } else { 3272 DispVal = 1; 3273 } 3274 } else if (Op3.isJTI()) { 3275 if (Is64BitMode || IsPIC) { 3276 DispForReloc = &Op3; 3277 } else { 3278 DispVal = 1; 3279 } 3280 } else { 3281 DispVal = 1; 3282 } 3283 3284 const MachineOperand &Base = MI.getOperand(Op); 3285 const MachineOperand &IndexReg = MI.getOperand(Op+2); 3286 3287 unsigned BaseReg = Base.getReg(); 3288 3289 // Is a SIB byte needed? 3290 if ((!Is64BitMode || DispForReloc || BaseReg != 0) && 3291 IndexReg.getReg() == 0 && 3292 (BaseReg == 0 || X86RegisterInfo::getX86RegNum(BaseReg) != N86::ESP)) { 3293 if (BaseReg == 0) { // Just a displacement? 3294 // Emit special case [disp32] encoding 3295 ++FinalSize; 3296 FinalSize += getDisplacementFieldSize(DispForReloc); 3297 } else { 3298 unsigned BaseRegNo = X86RegisterInfo::getX86RegNum(BaseReg); 3299 if (!DispForReloc && DispVal == 0 && BaseRegNo != N86::EBP) { 3300 // Emit simple indirect register encoding... [EAX] f.e. 3301 ++FinalSize; 3302 // Be pessimistic and assume it's a disp32, not a disp8 3303 } else { 3304 // Emit the most general non-SIB encoding: [REG+disp32] 3305 ++FinalSize; 3306 FinalSize += getDisplacementFieldSize(DispForReloc); 3307 } 3308 } 3309 3310 } else { // We need a SIB byte, so start by outputting the ModR/M byte first 3311 assert(IndexReg.getReg() != X86::ESP && 3312 IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!"); 3313 3314 bool ForceDisp32 = false; 3315 if (BaseReg == 0 || DispForReloc) { 3316 // Emit the normal disp32 encoding. 3317 ++FinalSize; 3318 ForceDisp32 = true; 3319 } else { 3320 ++FinalSize; 3321 } 3322 3323 FinalSize += sizeSIBByte(); 3324 3325 // Do we need to output a displacement? 3326 if (DispVal != 0 || ForceDisp32) { 3327 FinalSize += getDisplacementFieldSize(DispForReloc); 3328 } 3329 } 3330 return FinalSize; 3331} 3332 3333 3334static unsigned GetInstSizeWithDesc(const MachineInstr &MI, 3335 const TargetInstrDesc *Desc, 3336 bool IsPIC, bool Is64BitMode) { 3337 3338 unsigned Opcode = Desc->Opcode; 3339 unsigned FinalSize = 0; 3340 3341 // Emit the lock opcode prefix as needed. 3342 if (Desc->TSFlags & X86II::LOCK) ++FinalSize; 3343 3344 // Emit segment override opcode prefix as needed. 3345 switch (Desc->TSFlags & X86II::SegOvrMask) { 3346 case X86II::FS: 3347 case X86II::GS: 3348 ++FinalSize; 3349 break; 3350 default: llvm_unreachable("Invalid segment!"); 3351 case 0: break; // No segment override! 3352 } 3353 3354 // Emit the repeat opcode prefix as needed. 3355 if ((Desc->TSFlags & X86II::Op0Mask) == X86II::REP) ++FinalSize; 3356 3357 // Emit the operand size opcode prefix as needed. 3358 if (Desc->TSFlags & X86II::OpSize) ++FinalSize; 3359 3360 // Emit the address size opcode prefix as needed. 3361 if (Desc->TSFlags & X86II::AdSize) ++FinalSize; 3362 3363 bool Need0FPrefix = false; 3364 switch (Desc->TSFlags & X86II::Op0Mask) { 3365 case X86II::TB: // Two-byte opcode prefix 3366 case X86II::T8: // 0F 38 3367 case X86II::TA: // 0F 3A 3368 Need0FPrefix = true; 3369 break; 3370 case X86II::TF: // F2 0F 38 3371 ++FinalSize; 3372 Need0FPrefix = true; 3373 break; 3374 case X86II::REP: break; // already handled. 3375 case X86II::XS: // F3 0F 3376 ++FinalSize; 3377 Need0FPrefix = true; 3378 break; 3379 case X86II::XD: // F2 0F 3380 ++FinalSize; 3381 Need0FPrefix = true; 3382 break; 3383 case X86II::D8: case X86II::D9: case X86II::DA: case X86II::DB: 3384 case X86II::DC: case X86II::DD: case X86II::DE: case X86II::DF: 3385 ++FinalSize; 3386 break; // Two-byte opcode prefix 3387 default: llvm_unreachable("Invalid prefix!"); 3388 case 0: break; // No prefix! 3389 } 3390 3391 if (Is64BitMode) { 3392 // REX prefix 3393 unsigned REX = X86InstrInfo::determineREX(MI); 3394 if (REX) 3395 ++FinalSize; 3396 } 3397 3398 // 0x0F escape code must be emitted just before the opcode. 3399 if (Need0FPrefix) 3400 ++FinalSize; 3401 3402 switch (Desc->TSFlags & X86II::Op0Mask) { 3403 case X86II::T8: // 0F 38 3404 ++FinalSize; 3405 break; 3406 case X86II::TA: // 0F 3A 3407 ++FinalSize; 3408 break; 3409 case X86II::TF: // F2 0F 38 3410 ++FinalSize; 3411 break; 3412 } 3413 3414 // If this is a two-address instruction, skip one of the register operands. 3415 unsigned NumOps = Desc->getNumOperands(); 3416 unsigned CurOp = 0; 3417 if (NumOps > 1 && Desc->getOperandConstraint(1, TOI::TIED_TO) != -1) 3418 CurOp++; 3419 else if (NumOps > 2 && Desc->getOperandConstraint(NumOps-1, TOI::TIED_TO)== 0) 3420 // Skip the last source operand that is tied_to the dest reg. e.g. LXADD32 3421 --NumOps; 3422 3423 switch (Desc->TSFlags & X86II::FormMask) { 3424 default: llvm_unreachable("Unknown FormMask value in X86 MachineCodeEmitter!"); 3425 case X86II::Pseudo: 3426 // Remember the current PC offset, this is the PIC relocation 3427 // base address. 3428 switch (Opcode) { 3429 default: 3430 break; 3431 case TargetOpcode::INLINEASM: { 3432 const MachineFunction *MF = MI.getParent()->getParent(); 3433 const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo(); 3434 FinalSize += TII.getInlineAsmLength(MI.getOperand(0).getSymbolName(), 3435 *MF->getTarget().getMCAsmInfo()); 3436 break; 3437 } 3438 case TargetOpcode::DBG_LABEL: 3439 case TargetOpcode::EH_LABEL: 3440 case TargetOpcode::DBG_VALUE: 3441 break; 3442 case TargetOpcode::IMPLICIT_DEF: 3443 case TargetOpcode::KILL: 3444 case X86::FP_REG_KILL: 3445 break; 3446 case X86::MOVPC32r: { 3447 // This emits the "call" portion of this pseudo instruction. 3448 ++FinalSize; 3449 FinalSize += sizeConstant(X86II::getSizeOfImm(Desc->TSFlags)); 3450 break; 3451 } 3452 } 3453 CurOp = NumOps; 3454 break; 3455 case X86II::RawFrm: 3456 ++FinalSize; 3457 3458 if (CurOp != NumOps) { 3459 const MachineOperand &MO = MI.getOperand(CurOp++); 3460 if (MO.isMBB()) { 3461 FinalSize += sizePCRelativeBlockAddress(); 3462 } else if (MO.isGlobal()) { 3463 FinalSize += sizeGlobalAddress(false); 3464 } else if (MO.isSymbol()) { 3465 FinalSize += sizeExternalSymbolAddress(false); 3466 } else if (MO.isImm()) { 3467 FinalSize += sizeConstant(X86II::getSizeOfImm(Desc->TSFlags)); 3468 } else { 3469 llvm_unreachable("Unknown RawFrm operand!"); 3470 } 3471 } 3472 break; 3473 3474 case X86II::AddRegFrm: 3475 ++FinalSize; 3476 ++CurOp; 3477 3478 if (CurOp != NumOps) { 3479 const MachineOperand &MO1 = MI.getOperand(CurOp++); 3480 unsigned Size = X86II::getSizeOfImm(Desc->TSFlags); 3481 if (MO1.isImm()) 3482 FinalSize += sizeConstant(Size); 3483 else { 3484 bool dword = false; 3485 if (Opcode == X86::MOV64ri) 3486 dword = true; 3487 if (MO1.isGlobal()) { 3488 FinalSize += sizeGlobalAddress(dword); 3489 } else if (MO1.isSymbol()) 3490 FinalSize += sizeExternalSymbolAddress(dword); 3491 else if (MO1.isCPI()) 3492 FinalSize += sizeConstPoolAddress(dword); 3493 else if (MO1.isJTI()) 3494 FinalSize += sizeJumpTableAddress(dword); 3495 } 3496 } 3497 break; 3498 3499 case X86II::MRMDestReg: { 3500 ++FinalSize; 3501 FinalSize += sizeRegModRMByte(); 3502 CurOp += 2; 3503 if (CurOp != NumOps) { 3504 ++CurOp; 3505 FinalSize += sizeConstant(X86II::getSizeOfImm(Desc->TSFlags)); 3506 } 3507 break; 3508 } 3509 case X86II::MRMDestMem: { 3510 ++FinalSize; 3511 FinalSize += getMemModRMByteSize(MI, CurOp, IsPIC, Is64BitMode); 3512 CurOp += X86AddrNumOperands + 1; 3513 if (CurOp != NumOps) { 3514 ++CurOp; 3515 FinalSize += sizeConstant(X86II::getSizeOfImm(Desc->TSFlags)); 3516 } 3517 break; 3518 } 3519 3520 case X86II::MRMSrcReg: 3521 ++FinalSize; 3522 FinalSize += sizeRegModRMByte(); 3523 CurOp += 2; 3524 if (CurOp != NumOps) { 3525 ++CurOp; 3526 FinalSize += sizeConstant(X86II::getSizeOfImm(Desc->TSFlags)); 3527 } 3528 break; 3529 3530 case X86II::MRMSrcMem: { 3531 int AddrOperands; 3532 if (Opcode == X86::LEA64r || Opcode == X86::LEA64_32r || 3533 Opcode == X86::LEA16r || Opcode == X86::LEA32r) 3534 AddrOperands = X86AddrNumOperands - 1; // No segment register 3535 else 3536 AddrOperands = X86AddrNumOperands; 3537 3538 ++FinalSize; 3539 FinalSize += getMemModRMByteSize(MI, CurOp+1, IsPIC, Is64BitMode); 3540 CurOp += AddrOperands + 1; 3541 if (CurOp != NumOps) { 3542 ++CurOp; 3543 FinalSize += sizeConstant(X86II::getSizeOfImm(Desc->TSFlags)); 3544 } 3545 break; 3546 } 3547 3548 case X86II::MRM0r: case X86II::MRM1r: 3549 case X86II::MRM2r: case X86II::MRM3r: 3550 case X86II::MRM4r: case X86II::MRM5r: 3551 case X86II::MRM6r: case X86II::MRM7r: 3552 ++FinalSize; 3553 if (Desc->getOpcode() == X86::LFENCE || 3554 Desc->getOpcode() == X86::MFENCE) { 3555 // Special handling of lfence and mfence; 3556 FinalSize += sizeRegModRMByte(); 3557 } else if (Desc->getOpcode() == X86::MONITOR || 3558 Desc->getOpcode() == X86::MWAIT) { 3559 // Special handling of monitor and mwait. 3560 FinalSize += sizeRegModRMByte() + 1; // +1 for the opcode. 3561 } else { 3562 ++CurOp; 3563 FinalSize += sizeRegModRMByte(); 3564 } 3565 3566 if (CurOp != NumOps) { 3567 const MachineOperand &MO1 = MI.getOperand(CurOp++); 3568 unsigned Size = X86II::getSizeOfImm(Desc->TSFlags); 3569 if (MO1.isImm()) 3570 FinalSize += sizeConstant(Size); 3571 else { 3572 bool dword = false; 3573 if (Opcode == X86::MOV64ri32) 3574 dword = true; 3575 if (MO1.isGlobal()) { 3576 FinalSize += sizeGlobalAddress(dword); 3577 } else if (MO1.isSymbol()) 3578 FinalSize += sizeExternalSymbolAddress(dword); 3579 else if (MO1.isCPI()) 3580 FinalSize += sizeConstPoolAddress(dword); 3581 else if (MO1.isJTI()) 3582 FinalSize += sizeJumpTableAddress(dword); 3583 } 3584 } 3585 break; 3586 3587 case X86II::MRM0m: case X86II::MRM1m: 3588 case X86II::MRM2m: case X86II::MRM3m: 3589 case X86II::MRM4m: case X86II::MRM5m: 3590 case X86II::MRM6m: case X86II::MRM7m: { 3591 3592 ++FinalSize; 3593 FinalSize += getMemModRMByteSize(MI, CurOp, IsPIC, Is64BitMode); 3594 CurOp += X86AddrNumOperands; 3595 3596 if (CurOp != NumOps) { 3597 const MachineOperand &MO = MI.getOperand(CurOp++); 3598 unsigned Size = X86II::getSizeOfImm(Desc->TSFlags); 3599 if (MO.isImm()) 3600 FinalSize += sizeConstant(Size); 3601 else { 3602 bool dword = false; 3603 if (Opcode == X86::MOV64mi32) 3604 dword = true; 3605 if (MO.isGlobal()) { 3606 FinalSize += sizeGlobalAddress(dword); 3607 } else if (MO.isSymbol()) 3608 FinalSize += sizeExternalSymbolAddress(dword); 3609 else if (MO.isCPI()) 3610 FinalSize += sizeConstPoolAddress(dword); 3611 else if (MO.isJTI()) 3612 FinalSize += sizeJumpTableAddress(dword); 3613 } 3614 } 3615 break; 3616 3617 case X86II::MRM_C1: 3618 case X86II::MRM_C8: 3619 case X86II::MRM_C9: 3620 case X86II::MRM_E8: 3621 case X86II::MRM_F0: 3622 FinalSize += 2; 3623 break; 3624 } 3625 3626 case X86II::MRMInitReg: 3627 ++FinalSize; 3628 // Duplicate register, used by things like MOV8r0 (aka xor reg,reg). 3629 FinalSize += sizeRegModRMByte(); 3630 ++CurOp; 3631 break; 3632 } 3633 3634 if (!Desc->isVariadic() && CurOp != NumOps) { 3635 std::string msg; 3636 raw_string_ostream Msg(msg); 3637 Msg << "Cannot determine size: " << MI; 3638 report_fatal_error(Msg.str()); 3639 } 3640 3641 3642 return FinalSize; 3643} 3644 3645 3646unsigned X86InstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const { 3647 const TargetInstrDesc &Desc = MI->getDesc(); 3648 bool IsPIC = TM.getRelocationModel() == Reloc::PIC_; 3649 bool Is64BitMode = TM.getSubtargetImpl()->is64Bit(); 3650 unsigned Size = GetInstSizeWithDesc(*MI, &Desc, IsPIC, Is64BitMode); 3651 if (Desc.getOpcode() == X86::MOVPC32r) 3652 Size += GetInstSizeWithDesc(*MI, &get(X86::POP32r), IsPIC, Is64BitMode); 3653 return Size; 3654} 3655 3656/// getGlobalBaseReg - Return a virtual register initialized with the 3657/// the global base register value. Output instructions required to 3658/// initialize the register in the function entry block, if necessary. 3659/// 3660unsigned X86InstrInfo::getGlobalBaseReg(MachineFunction *MF) const { 3661 assert(!TM.getSubtarget<X86Subtarget>().is64Bit() && 3662 "X86-64 PIC uses RIP relative addressing"); 3663 3664 X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>(); 3665 unsigned GlobalBaseReg = X86FI->getGlobalBaseReg(); 3666 if (GlobalBaseReg != 0) 3667 return GlobalBaseReg; 3668 3669 // Insert the set of GlobalBaseReg into the first MBB of the function 3670 MachineBasicBlock &FirstMBB = MF->front(); 3671 MachineBasicBlock::iterator MBBI = FirstMBB.begin(); 3672 DebugLoc DL = FirstMBB.findDebugLoc(MBBI); 3673 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 3674 unsigned PC = RegInfo.createVirtualRegister(X86::GR32RegisterClass); 3675 3676 const TargetInstrInfo *TII = TM.getInstrInfo(); 3677 // Operand of MovePCtoStack is completely ignored by asm printer. It's 3678 // only used in JIT code emission as displacement to pc. 3679 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOVPC32r), PC).addImm(0); 3680 3681 // If we're using vanilla 'GOT' PIC style, we should use relative addressing 3682 // not to pc, but to _GLOBAL_OFFSET_TABLE_ external. 3683 if (TM.getSubtarget<X86Subtarget>().isPICStyleGOT()) { 3684 GlobalBaseReg = RegInfo.createVirtualRegister(X86::GR32RegisterClass); 3685 // Generate addl $__GLOBAL_OFFSET_TABLE_ + [.-piclabel], %some_register 3686 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD32ri), GlobalBaseReg) 3687 .addReg(PC).addExternalSymbol("_GLOBAL_OFFSET_TABLE_", 3688 X86II::MO_GOT_ABSOLUTE_ADDRESS); 3689 } else { 3690 GlobalBaseReg = PC; 3691 } 3692 3693 X86FI->setGlobalBaseReg(GlobalBaseReg); 3694 return GlobalBaseReg; 3695} 3696 3697// These are the replaceable SSE instructions. Some of these have Int variants 3698// that we don't include here. We don't want to replace instructions selected 3699// by intrinsics. 3700static const unsigned ReplaceableInstrs[][3] = { 3701 //PackedInt PackedSingle PackedDouble 3702 { X86::MOVAPSmr, X86::MOVAPDmr, X86::MOVDQAmr }, 3703 { X86::MOVAPSrm, X86::MOVAPDrm, X86::MOVDQArm }, 3704 { X86::MOVAPSrr, X86::MOVAPDrr, X86::MOVDQArr }, 3705 { X86::MOVUPSmr, X86::MOVUPDmr, X86::MOVDQUmr }, 3706 { X86::MOVUPSrm, X86::MOVUPDrm, X86::MOVDQUrm }, 3707 { X86::MOVNTPSmr, X86::MOVNTPDmr, X86::MOVNTDQmr }, 3708 { X86::ANDNPSrm, X86::ANDNPDrm, X86::PANDNrm }, 3709 { X86::ANDNPSrr, X86::ANDNPDrr, X86::PANDNrr }, 3710 { X86::ANDPSrm, X86::ANDPDrm, X86::PANDrm }, 3711 { X86::ANDPSrr, X86::ANDPDrr, X86::PANDrr }, 3712 { X86::ORPSrm, X86::ORPDrm, X86::PORrm }, 3713 { X86::ORPSrr, X86::ORPDrr, X86::PORrr }, 3714 { X86::V_SET0PS, X86::V_SET0PD, X86::V_SET0PI }, 3715 { X86::XORPSrm, X86::XORPDrm, X86::PXORrm }, 3716 { X86::XORPSrr, X86::XORPDrr, X86::PXORrr }, 3717}; 3718 3719// FIXME: Some shuffle and unpack instructions have equivalents in different 3720// domains, but they require a bit more work than just switching opcodes. 3721 3722static const unsigned *lookup(unsigned opcode, unsigned domain) { 3723 for (unsigned i = 0, e = array_lengthof(ReplaceableInstrs); i != e; ++i) 3724 if (ReplaceableInstrs[i][domain-1] == opcode) 3725 return ReplaceableInstrs[i]; 3726 return 0; 3727} 3728 3729std::pair<uint16_t, uint16_t> 3730X86InstrInfo::GetSSEDomain(const MachineInstr *MI) const { 3731 uint16_t domain = (MI->getDesc().TSFlags >> X86II::SSEDomainShift) & 3; 3732 return std::make_pair(domain, 3733 domain && lookup(MI->getOpcode(), domain) ? 0xe : 0); 3734} 3735 3736void X86InstrInfo::SetSSEDomain(MachineInstr *MI, unsigned Domain) const { 3737 assert(Domain>0 && Domain<4 && "Invalid execution domain"); 3738 uint16_t dom = (MI->getDesc().TSFlags >> X86II::SSEDomainShift) & 3; 3739 assert(dom && "Not an SSE instruction"); 3740 const unsigned *table = lookup(MI->getOpcode(), dom); 3741 assert(table && "Cannot change domain"); 3742 MI->setDesc(get(table[Domain-1])); 3743} 3744 3745/// getNoopForMachoTarget - Return the noop instruction to use for a noop. 3746void X86InstrInfo::getNoopForMachoTarget(MCInst &NopInst) const { 3747 NopInst.setOpcode(X86::NOOP); 3748} 3749