X86InstrInfo.cpp revision 739c7a83e16e7daaf22cfa4ae84e8d1cc0260941 
1//===-- X86InstrInfo.cpp - X86 Instruction Information --------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the X86 implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "X86InstrInfo.h"
15#include "X86.h"
16#include "X86InstrBuilder.h"
17#include "X86MachineFunctionInfo.h"
18#include "X86Subtarget.h"
19#include "X86TargetMachine.h"
20#include "llvm/ADT/STLExtras.h"
21#include "llvm/CodeGen/LiveVariables.h"
22#include "llvm/CodeGen/MachineConstantPool.h"
23#include "llvm/CodeGen/MachineDominators.h"
24#include "llvm/CodeGen/MachineFrameInfo.h"
25#include "llvm/CodeGen/MachineInstrBuilder.h"
26#include "llvm/CodeGen/MachineRegisterInfo.h"
27#include "llvm/DerivedTypes.h"
28#include "llvm/LLVMContext.h"
29#include "llvm/MC/MCAsmInfo.h"
30#include "llvm/MC/MCInst.h"
31#include "llvm/Support/CommandLine.h"
32#include "llvm/Support/Debug.h"
33#include "llvm/Support/ErrorHandling.h"
34#include "llvm/Support/raw_ostream.h"
35#include "llvm/Target/TargetOptions.h"
36#include <limits>
37
38#define GET_INSTRINFO_CTOR
39#include "X86GenInstrInfo.inc"
40
41using namespace llvm;
42
43static cl::opt<bool>
44NoFusing("disable-spill-fusing",
45         cl::desc("Disable fusing of spill code into instructions"));
46static cl::opt<bool>
47PrintFailedFusing("print-failed-fuse-candidates",
48                  cl::desc("Print instructions that the allocator wants to"
49                           " fuse, but the X86 backend currently can't"),
50                  cl::Hidden);
51static cl::opt<bool>
52ReMatPICStubLoad("remat-pic-stub-load",
53                 cl::desc("Re-materialize load from stub in PIC mode"),
54                 cl::init(false), cl::Hidden);
55
56enum {
57  // Select which memory operand is being unfolded.
58  // (stored in bits 0 - 3)
59  TB_INDEX_0    = 0,
60  TB_INDEX_1    = 1,
61  TB_INDEX_2    = 2,
62  TB_INDEX_3    = 3,
63  TB_INDEX_MASK = 0xf,
64
65  // Do not insert the reverse map (MemOp -> RegOp) into the table.
66  // This may be needed because there is a many -> one mapping.
67  TB_NO_REVERSE   = 1 << 4,
68
69  // Do not insert the forward map (RegOp -> MemOp) into the table.
70  // This is needed for Native Client, which prohibits branch
71  // instructions from using a memory operand.
72  TB_NO_FORWARD   = 1 << 5,
73
74  TB_FOLDED_LOAD  = 1 << 6,
75  TB_FOLDED_STORE = 1 << 7,
76
77  // Minimum alignment required for load/store.
78  // Used for RegOp->MemOp conversion.
79  // (stored in bits 8 - 15)
80  TB_ALIGN_SHIFT = 8,
81  TB_ALIGN_NONE  =    0 << TB_ALIGN_SHIFT,
82  TB_ALIGN_16    =   16 << TB_ALIGN_SHIFT,
83  TB_ALIGN_32    =   32 << TB_ALIGN_SHIFT,
84  TB_ALIGN_MASK  = 0xff << TB_ALIGN_SHIFT
85};
86
87struct X86OpTblEntry {
88  uint16_t RegOp;
89  uint16_t MemOp;
90  uint16_t Flags;
91};
92
93X86InstrInfo::X86InstrInfo(X86TargetMachine &tm)
94  : X86GenInstrInfo((tm.getSubtarget<X86Subtarget>().is64Bit()
95                     ? X86::ADJCALLSTACKDOWN64
96                     : X86::ADJCALLSTACKDOWN32),
97                    (tm.getSubtarget<X86Subtarget>().is64Bit()
98                     ? X86::ADJCALLSTACKUP64
99                     : X86::ADJCALLSTACKUP32)),
100    TM(tm), RI(tm, *this) {
101
102  static const X86OpTblEntry OpTbl2Addr[] = {
103    { X86::ADC32ri,     X86::ADC32mi,    0 },
104    { X86::ADC32ri8,    X86::ADC32mi8,   0 },
105    { X86::ADC32rr,     X86::ADC32mr,    0 },
106    { X86::ADC64ri32,   X86::ADC64mi32,  0 },
107    { X86::ADC64ri8,    X86::ADC64mi8,   0 },
108    { X86::ADC64rr,     X86::ADC64mr,    0 },
109    { X86::ADD16ri,     X86::ADD16mi,    0 },
110    { X86::ADD16ri8,    X86::ADD16mi8,   0 },
111    { X86::ADD16ri_DB,  X86::ADD16mi,    TB_NO_REVERSE },
112    { X86::ADD16ri8_DB, X86::ADD16mi8,   TB_NO_REVERSE },
113    { X86::ADD16rr,     X86::ADD16mr,    0 },
114    { X86::ADD16rr_DB,  X86::ADD16mr,    TB_NO_REVERSE },
115    { X86::ADD32ri,     X86::ADD32mi,    0 },
116    { X86::ADD32ri8,    X86::ADD32mi8,   0 },
117    { X86::ADD32ri_DB,  X86::ADD32mi,    TB_NO_REVERSE },
118    { X86::ADD32ri8_DB, X86::ADD32mi8,   TB_NO_REVERSE },
119    { X86::ADD32rr,     X86::ADD32mr,    0 },
120    { X86::ADD32rr_DB,  X86::ADD32mr,    TB_NO_REVERSE },
121    { X86::ADD64ri32,   X86::ADD64mi32,  0 },
122    { X86::ADD64ri8,    X86::ADD64mi8,   0 },
123    { X86::ADD64ri32_DB,X86::ADD64mi32,  TB_NO_REVERSE },
124    { X86::ADD64ri8_DB, X86::ADD64mi8,   TB_NO_REVERSE },
125    { X86::ADD64rr,     X86::ADD64mr,    0 },
126    { X86::ADD64rr_DB,  X86::ADD64mr,    TB_NO_REVERSE },
127    { X86::ADD8ri,      X86::ADD8mi,     0 },
128    { X86::ADD8rr,      X86::ADD8mr,     0 },
129    { X86::AND16ri,     X86::AND16mi,    0 },
130    { X86::AND16ri8,    X86::AND16mi8,   0 },
131    { X86::AND16rr,     X86::AND16mr,    0 },
132    { X86::AND32ri,     X86::AND32mi,    0 },
133    { X86::AND32ri8,    X86::AND32mi8,   0 },
134    { X86::AND32rr,     X86::AND32mr,    0 },
135    { X86::AND64ri32,   X86::AND64mi32,  0 },
136    { X86::AND64ri8,    X86::AND64mi8,   0 },
137    { X86::AND64rr,     X86::AND64mr,    0 },
138    { X86::AND8ri,      X86::AND8mi,     0 },
139    { X86::AND8rr,      X86::AND8mr,     0 },
140    { X86::DEC16r,      X86::DEC16m,     0 },
141    { X86::DEC32r,      X86::DEC32m,     0 },
142    { X86::DEC64_16r,   X86::DEC64_16m,  0 },
143    { X86::DEC64_32r,   X86::DEC64_32m,  0 },
144    { X86::DEC64r,      X86::DEC64m,     0 },
145    { X86::DEC8r,       X86::DEC8m,      0 },
146    { X86::INC16r,      X86::INC16m,     0 },
147    { X86::INC32r,      X86::INC32m,     0 },
148    { X86::INC64_16r,   X86::INC64_16m,  0 },
149    { X86::INC64_32r,   X86::INC64_32m,  0 },
150    { X86::INC64r,      X86::INC64m,     0 },
151    { X86::INC8r,       X86::INC8m,      0 },
152    { X86::NEG16r,      X86::NEG16m,     0 },
153    { X86::NEG32r,      X86::NEG32m,     0 },
154    { X86::NEG64r,      X86::NEG64m,     0 },
155    { X86::NEG8r,       X86::NEG8m,      0 },
156    { X86::NOT16r,      X86::NOT16m,     0 },
157    { X86::NOT32r,      X86::NOT32m,     0 },
158    { X86::NOT64r,      X86::NOT64m,     0 },
159    { X86::NOT8r,       X86::NOT8m,      0 },
160    { X86::OR16ri,      X86::OR16mi,     0 },
161    { X86::OR16ri8,     X86::OR16mi8,    0 },
162    { X86::OR16rr,      X86::OR16mr,     0 },
163    { X86::OR32ri,      X86::OR32mi,     0 },
164    { X86::OR32ri8,     X86::OR32mi8,    0 },
165    { X86::OR32rr,      X86::OR32mr,     0 },
166    { X86::OR64ri32,    X86::OR64mi32,   0 },
167    { X86::OR64ri8,     X86::OR64mi8,    0 },
168    { X86::OR64rr,      X86::OR64mr,     0 },
169    { X86::OR8ri,       X86::OR8mi,      0 },
170    { X86::OR8rr,       X86::OR8mr,      0 },
171    { X86::ROL16r1,     X86::ROL16m1,    0 },
172    { X86::ROL16rCL,    X86::ROL16mCL,   0 },
173    { X86::ROL16ri,     X86::ROL16mi,    0 },
174    { X86::ROL32r1,     X86::ROL32m1,    0 },
175    { X86::ROL32rCL,    X86::ROL32mCL,   0 },
176    { X86::ROL32ri,     X86::ROL32mi,    0 },
177    { X86::ROL64r1,     X86::ROL64m1,    0 },
178    { X86::ROL64rCL,    X86::ROL64mCL,   0 },
179    { X86::ROL64ri,     X86::ROL64mi,    0 },
180    { X86::ROL8r1,      X86::ROL8m1,     0 },
181    { X86::ROL8rCL,     X86::ROL8mCL,    0 },
182    { X86::ROL8ri,      X86::ROL8mi,     0 },
183    { X86::ROR16r1,     X86::ROR16m1,    0 },
184    { X86::ROR16rCL,    X86::ROR16mCL,   0 },
185    { X86::ROR16ri,     X86::ROR16mi,    0 },
186    { X86::ROR32r1,     X86::ROR32m1,    0 },
187    { X86::ROR32rCL,    X86::ROR32mCL,   0 },
188    { X86::ROR32ri,     X86::ROR32mi,    0 },
189    { X86::ROR64r1,     X86::ROR64m1,    0 },
190    { X86::ROR64rCL,    X86::ROR64mCL,   0 },
191    { X86::ROR64ri,     X86::ROR64mi,    0 },
192    { X86::ROR8r1,      X86::ROR8m1,     0 },
193    { X86::ROR8rCL,     X86::ROR8mCL,    0 },
194    { X86::ROR8ri,      X86::ROR8mi,     0 },
195    { X86::SAR16r1,     X86::SAR16m1,    0 },
196    { X86::SAR16rCL,    X86::SAR16mCL,   0 },
197    { X86::SAR16ri,     X86::SAR16mi,    0 },
198    { X86::SAR32r1,     X86::SAR32m1,    0 },
199    { X86::SAR32rCL,    X86::SAR32mCL,   0 },
200    { X86::SAR32ri,     X86::SAR32mi,    0 },
201    { X86::SAR64r1,     X86::SAR64m1,    0 },
202    { X86::SAR64rCL,    X86::SAR64mCL,   0 },
203    { X86::SAR64ri,     X86::SAR64mi,    0 },
204    { X86::SAR8r1,      X86::SAR8m1,     0 },
205    { X86::SAR8rCL,     X86::SAR8mCL,    0 },
206    { X86::SAR8ri,      X86::SAR8mi,     0 },
207    { X86::SBB32ri,     X86::SBB32mi,    0 },
208    { X86::SBB32ri8,    X86::SBB32mi8,   0 },
209    { X86::SBB32rr,     X86::SBB32mr,    0 },
210    { X86::SBB64ri32,   X86::SBB64mi32,  0 },
211    { X86::SBB64ri8,    X86::SBB64mi8,   0 },
212    { X86::SBB64rr,     X86::SBB64mr,    0 },
213    { X86::SHL16rCL,    X86::SHL16mCL,   0 },
214    { X86::SHL16ri,     X86::SHL16mi,    0 },
215    { X86::SHL32rCL,    X86::SHL32mCL,   0 },
216    { X86::SHL32ri,     X86::SHL32mi,    0 },
217    { X86::SHL64rCL,    X86::SHL64mCL,   0 },
218    { X86::SHL64ri,     X86::SHL64mi,    0 },
219    { X86::SHL8rCL,     X86::SHL8mCL,    0 },
220    { X86::SHL8ri,      X86::SHL8mi,     0 },
221    { X86::SHLD16rrCL,  X86::SHLD16mrCL, 0 },
222    { X86::SHLD16rri8,  X86::SHLD16mri8, 0 },
223    { X86::SHLD32rrCL,  X86::SHLD32mrCL, 0 },
224    { X86::SHLD32rri8,  X86::SHLD32mri8, 0 },
225    { X86::SHLD64rrCL,  X86::SHLD64mrCL, 0 },
226    { X86::SHLD64rri8,  X86::SHLD64mri8, 0 },
227    { X86::SHR16r1,     X86::SHR16m1,    0 },
228    { X86::SHR16rCL,    X86::SHR16mCL,   0 },
229    { X86::SHR16ri,     X86::SHR16mi,    0 },
230    { X86::SHR32r1,     X86::SHR32m1,    0 },
231    { X86::SHR32rCL,    X86::SHR32mCL,   0 },
232    { X86::SHR32ri,     X86::SHR32mi,    0 },
233    { X86::SHR64r1,     X86::SHR64m1,    0 },
234    { X86::SHR64rCL,    X86::SHR64mCL,   0 },
235    { X86::SHR64ri,     X86::SHR64mi,    0 },
236    { X86::SHR8r1,      X86::SHR8m1,     0 },
237    { X86::SHR8rCL,     X86::SHR8mCL,    0 },
238    { X86::SHR8ri,      X86::SHR8mi,     0 },
239    { X86::SHRD16rrCL,  X86::SHRD16mrCL, 0 },
240    { X86::SHRD16rri8,  X86::SHRD16mri8, 0 },
241    { X86::SHRD32rrCL,  X86::SHRD32mrCL, 0 },
242    { X86::SHRD32rri8,  X86::SHRD32mri8, 0 },
243    { X86::SHRD64rrCL,  X86::SHRD64mrCL, 0 },
244    { X86::SHRD64rri8,  X86::SHRD64mri8, 0 },
245    { X86::SUB16ri,     X86::SUB16mi,    0 },
246    { X86::SUB16ri8,    X86::SUB16mi8,   0 },
247    { X86::SUB16rr,     X86::SUB16mr,    0 },
248    { X86::SUB32ri,     X86::SUB32mi,    0 },
249    { X86::SUB32ri8,    X86::SUB32mi8,   0 },
250    { X86::SUB32rr,     X86::SUB32mr,    0 },
251    { X86::SUB64ri32,   X86::SUB64mi32,  0 },
252    { X86::SUB64ri8,    X86::SUB64mi8,   0 },
253    { X86::SUB64rr,     X86::SUB64mr,    0 },
254    { X86::SUB8ri,      X86::SUB8mi,     0 },
255    { X86::SUB8rr,      X86::SUB8mr,     0 },
256    { X86::XOR16ri,     X86::XOR16mi,    0 },
257    { X86::XOR16ri8,    X86::XOR16mi8,   0 },
258    { X86::XOR16rr,     X86::XOR16mr,    0 },
259    { X86::XOR32ri,     X86::XOR32mi,    0 },
260    { X86::XOR32ri8,    X86::XOR32mi8,   0 },
261    { X86::XOR32rr,     X86::XOR32mr,    0 },
262    { X86::XOR64ri32,   X86::XOR64mi32,  0 },
263    { X86::XOR64ri8,    X86::XOR64mi8,   0 },
264    { X86::XOR64rr,     X86::XOR64mr,    0 },
265    { X86::XOR8ri,      X86::XOR8mi,     0 },
266    { X86::XOR8rr,      X86::XOR8mr,     0 }
267  };
268
269  for (unsigned i = 0, e = array_lengthof(OpTbl2Addr); i != e; ++i) {
270    unsigned RegOp = OpTbl2Addr[i].RegOp;
271    unsigned MemOp = OpTbl2Addr[i].MemOp;
272    unsigned Flags = OpTbl2Addr[i].Flags;
273    AddTableEntry(RegOp2MemOpTable2Addr, MemOp2RegOpTable,
274                  RegOp, MemOp,
275                  // Index 0, folded load and store, no alignment requirement.
276                  Flags | TB_INDEX_0 | TB_FOLDED_LOAD | TB_FOLDED_STORE);
277  }
278
279  static const X86OpTblEntry OpTbl0[] = {
280    { X86::BT16ri8,     X86::BT16mi8,       TB_FOLDED_LOAD },
281    { X86::BT32ri8,     X86::BT32mi8,       TB_FOLDED_LOAD },
282    { X86::BT64ri8,     X86::BT64mi8,       TB_FOLDED_LOAD },
283    { X86::CALL32r,     X86::CALL32m,       TB_FOLDED_LOAD },
284    { X86::CALL64r,     X86::CALL64m,       TB_FOLDED_LOAD },
285    { X86::CMP16ri,     X86::CMP16mi,       TB_FOLDED_LOAD },
286    { X86::CMP16ri8,    X86::CMP16mi8,      TB_FOLDED_LOAD },
287    { X86::CMP16rr,     X86::CMP16mr,       TB_FOLDED_LOAD },
288    { X86::CMP32ri,     X86::CMP32mi,       TB_FOLDED_LOAD },
289    { X86::CMP32ri8,    X86::CMP32mi8,      TB_FOLDED_LOAD },
290    { X86::CMP32rr,     X86::CMP32mr,       TB_FOLDED_LOAD },
291    { X86::CMP64ri32,   X86::CMP64mi32,     TB_FOLDED_LOAD },
292    { X86::CMP64ri8,    X86::CMP64mi8,      TB_FOLDED_LOAD },
293    { X86::CMP64rr,     X86::CMP64mr,       TB_FOLDED_LOAD },
294    { X86::CMP8ri,      X86::CMP8mi,        TB_FOLDED_LOAD },
295    { X86::CMP8rr,      X86::CMP8mr,        TB_FOLDED_LOAD },
296    { X86::DIV16r,      X86::DIV16m,        TB_FOLDED_LOAD },
297    { X86::DIV32r,      X86::DIV32m,        TB_FOLDED_LOAD },
298    { X86::DIV64r,      X86::DIV64m,        TB_FOLDED_LOAD },
299    { X86::DIV8r,       X86::DIV8m,         TB_FOLDED_LOAD },
300    { X86::EXTRACTPSrr, X86::EXTRACTPSmr,   TB_FOLDED_STORE | TB_ALIGN_16 },
301    { X86::FsMOVAPDrr,  X86::MOVSDmr,       TB_FOLDED_STORE | TB_NO_REVERSE },
302    { X86::FsMOVAPSrr,  X86::MOVSSmr,       TB_FOLDED_STORE | TB_NO_REVERSE },
303    { X86::IDIV16r,     X86::IDIV16m,       TB_FOLDED_LOAD },
304    { X86::IDIV32r,     X86::IDIV32m,       TB_FOLDED_LOAD },
305    { X86::IDIV64r,     X86::IDIV64m,       TB_FOLDED_LOAD },
306    { X86::IDIV8r,      X86::IDIV8m,        TB_FOLDED_LOAD },
307    { X86::IMUL16r,     X86::IMUL16m,       TB_FOLDED_LOAD },
308    { X86::IMUL32r,     X86::IMUL32m,       TB_FOLDED_LOAD },
309    { X86::IMUL64r,     X86::IMUL64m,       TB_FOLDED_LOAD },
310    { X86::IMUL8r,      X86::IMUL8m,        TB_FOLDED_LOAD },
311    { X86::JMP32r,      X86::JMP32m,        TB_FOLDED_LOAD },
312    { X86::JMP64r,      X86::JMP64m,        TB_FOLDED_LOAD },
313    { X86::MOV16ri,     X86::MOV16mi,       TB_FOLDED_STORE },
314    { X86::MOV16rr,     X86::MOV16mr,       TB_FOLDED_STORE },
315    { X86::MOV32ri,     X86::MOV32mi,       TB_FOLDED_STORE },
316    { X86::MOV32rr,     X86::MOV32mr,       TB_FOLDED_STORE },
317    { X86::MOV64ri32,   X86::MOV64mi32,     TB_FOLDED_STORE },
318    { X86::MOV64rr,     X86::MOV64mr,       TB_FOLDED_STORE },
319    { X86::MOV8ri,      X86::MOV8mi,        TB_FOLDED_STORE },
320    { X86::MOV8rr,      X86::MOV8mr,        TB_FOLDED_STORE },
321    { X86::MOV8rr_NOREX, X86::MOV8mr_NOREX, TB_FOLDED_STORE },
322    { X86::MOVAPDrr,    X86::MOVAPDmr,      TB_FOLDED_STORE | TB_ALIGN_16 },
323    { X86::MOVAPSrr,    X86::MOVAPSmr,      TB_FOLDED_STORE | TB_ALIGN_16 },
324    { X86::MOVDQArr,    X86::MOVDQAmr,      TB_FOLDED_STORE | TB_ALIGN_16 },
325    { X86::MOVPDI2DIrr, X86::MOVPDI2DImr,   TB_FOLDED_STORE },
326    { X86::MOVPQIto64rr,X86::MOVPQI2QImr,   TB_FOLDED_STORE },
327    { X86::MOVSDto64rr, X86::MOVSDto64mr,   TB_FOLDED_STORE },
328    { X86::MOVSS2DIrr,  X86::MOVSS2DImr,    TB_FOLDED_STORE },
329    { X86::MOVUPDrr,    X86::MOVUPDmr,      TB_FOLDED_STORE },
330    { X86::MOVUPSrr,    X86::MOVUPSmr,      TB_FOLDED_STORE },
331    { X86::MUL16r,      X86::MUL16m,        TB_FOLDED_LOAD },
332    { X86::MUL32r,      X86::MUL32m,        TB_FOLDED_LOAD },
333    { X86::MUL64r,      X86::MUL64m,        TB_FOLDED_LOAD },
334    { X86::MUL8r,       X86::MUL8m,         TB_FOLDED_LOAD },
335    { X86::SETAEr,      X86::SETAEm,        TB_FOLDED_STORE },
336    { X86::SETAr,       X86::SETAm,         TB_FOLDED_STORE },
337    { X86::SETBEr,      X86::SETBEm,        TB_FOLDED_STORE },
338    { X86::SETBr,       X86::SETBm,         TB_FOLDED_STORE },
339    { X86::SETEr,       X86::SETEm,         TB_FOLDED_STORE },
340    { X86::SETGEr,      X86::SETGEm,        TB_FOLDED_STORE },
341    { X86::SETGr,       X86::SETGm,         TB_FOLDED_STORE },
342    { X86::SETLEr,      X86::SETLEm,        TB_FOLDED_STORE },
343    { X86::SETLr,       X86::SETLm,         TB_FOLDED_STORE },
344    { X86::SETNEr,      X86::SETNEm,        TB_FOLDED_STORE },
345    { X86::SETNOr,      X86::SETNOm,        TB_FOLDED_STORE },
346    { X86::SETNPr,      X86::SETNPm,        TB_FOLDED_STORE },
347    { X86::SETNSr,      X86::SETNSm,        TB_FOLDED_STORE },
348    { X86::SETOr,       X86::SETOm,         TB_FOLDED_STORE },
349    { X86::SETPr,       X86::SETPm,         TB_FOLDED_STORE },
350    { X86::SETSr,       X86::SETSm,         TB_FOLDED_STORE },
351    { X86::TAILJMPr,    X86::TAILJMPm,      TB_FOLDED_LOAD },
352    { X86::TAILJMPr64,  X86::TAILJMPm64,    TB_FOLDED_LOAD },
353    { X86::TEST16ri,    X86::TEST16mi,      TB_FOLDED_LOAD },
354    { X86::TEST32ri,    X86::TEST32mi,      TB_FOLDED_LOAD },
355    { X86::TEST64ri32,  X86::TEST64mi32,    TB_FOLDED_LOAD },
356    { X86::TEST8ri,     X86::TEST8mi,       TB_FOLDED_LOAD },
357    // AVX 128-bit versions of foldable instructions
358    { X86::VEXTRACTPSrr,X86::VEXTRACTPSmr,  TB_FOLDED_STORE | TB_ALIGN_16 },
359    { X86::FsVMOVAPDrr, X86::VMOVSDmr,      TB_FOLDED_STORE | TB_NO_REVERSE },
360    { X86::FsVMOVAPSrr, X86::VMOVSSmr,      TB_FOLDED_STORE | TB_NO_REVERSE },
361    { X86::VEXTRACTF128rr, X86::VEXTRACTF128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
362    { X86::VMOVAPDrr,   X86::VMOVAPDmr,     TB_FOLDED_STORE | TB_ALIGN_16 },
363    { X86::VMOVAPSrr,   X86::VMOVAPSmr,     TB_FOLDED_STORE | TB_ALIGN_16 },
364    { X86::VMOVDQArr,   X86::VMOVDQAmr,     TB_FOLDED_STORE | TB_ALIGN_16 },
365    { X86::VMOVPDI2DIrr,X86::VMOVPDI2DImr,  TB_FOLDED_STORE },
366    { X86::VMOVPQIto64rr, X86::VMOVPQI2QImr,TB_FOLDED_STORE },
367    { X86::VMOVSDto64rr,X86::VMOVSDto64mr,  TB_FOLDED_STORE },
368    { X86::VMOVSS2DIrr, X86::VMOVSS2DImr,   TB_FOLDED_STORE },
369    { X86::VMOVUPDrr,   X86::VMOVUPDmr,     TB_FOLDED_STORE },
370    { X86::VMOVUPSrr,   X86::VMOVUPSmr,     TB_FOLDED_STORE },
371    // AVX 256-bit foldable instructions
372    { X86::VEXTRACTI128rr, X86::VEXTRACTI128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
373    { X86::VMOVAPDYrr,  X86::VMOVAPDYmr,    TB_FOLDED_STORE | TB_ALIGN_32 },
374    { X86::VMOVAPSYrr,  X86::VMOVAPSYmr,    TB_FOLDED_STORE | TB_ALIGN_32 },
375    { X86::VMOVDQAYrr,  X86::VMOVDQAYmr,    TB_FOLDED_STORE | TB_ALIGN_32 },
376    { X86::VMOVUPDYrr,  X86::VMOVUPDYmr,    TB_FOLDED_STORE },
377    { X86::VMOVUPSYrr,  X86::VMOVUPSYmr,    TB_FOLDED_STORE }
378  };
379
380  for (unsigned i = 0, e = array_lengthof(OpTbl0); i != e; ++i) {
381    unsigned RegOp      = OpTbl0[i].RegOp;
382    unsigned MemOp      = OpTbl0[i].MemOp;
383    unsigned Flags      = OpTbl0[i].Flags;
384    AddTableEntry(RegOp2MemOpTable0, MemOp2RegOpTable,
385                  RegOp, MemOp, TB_INDEX_0 | Flags);
386  }
387
388  static const X86OpTblEntry OpTbl1[] = {
389    { X86::CMP16rr,         X86::CMP16rm,             0 },
390    { X86::CMP32rr,         X86::CMP32rm,             0 },
391    { X86::CMP64rr,         X86::CMP64rm,             0 },
392    { X86::CMP8rr,          X86::CMP8rm,              0 },
393    { X86::CVTSD2SSrr,      X86::CVTSD2SSrm,          0 },
394    { X86::CVTSI2SD64rr,    X86::CVTSI2SD64rm,        0 },
395    { X86::CVTSI2SDrr,      X86::CVTSI2SDrm,          0 },
396    { X86::CVTSI2SS64rr,    X86::CVTSI2SS64rm,        0 },
397    { X86::CVTSI2SSrr,      X86::CVTSI2SSrm,          0 },
398    { X86::CVTSS2SDrr,      X86::CVTSS2SDrm,          0 },
399    { X86::CVTTSD2SI64rr,   X86::CVTTSD2SI64rm,       0 },
400    { X86::CVTTSD2SIrr,     X86::CVTTSD2SIrm,         0 },
401    { X86::CVTTSS2SI64rr,   X86::CVTTSS2SI64rm,       0 },
402    { X86::CVTTSS2SIrr,     X86::CVTTSS2SIrm,         0 },
403    { X86::FsMOVAPDrr,      X86::MOVSDrm,             TB_NO_REVERSE },
404    { X86::FsMOVAPSrr,      X86::MOVSSrm,             TB_NO_REVERSE },
405    { X86::IMUL16rri,       X86::IMUL16rmi,           0 },
406    { X86::IMUL16rri8,      X86::IMUL16rmi8,          0 },
407    { X86::IMUL32rri,       X86::IMUL32rmi,           0 },
408    { X86::IMUL32rri8,      X86::IMUL32rmi8,          0 },
409    { X86::IMUL64rri32,     X86::IMUL64rmi32,         0 },
410    { X86::IMUL64rri8,      X86::IMUL64rmi8,          0 },
411    { X86::Int_COMISDrr,    X86::Int_COMISDrm,        0 },
412    { X86::Int_COMISSrr,    X86::Int_COMISSrm,        0 },
413    { X86::CVTSD2SI64rr,    X86::CVTSD2SI64rm,        0 },
414    { X86::CVTSD2SIrr,      X86::CVTSD2SIrm,          0 },
415    { X86::CVTSS2SI64rr,    X86::CVTSS2SI64rm,        0 },
416    { X86::CVTSS2SIrr,      X86::CVTSS2SIrm,          0 },
417    { X86::CVTTPD2DQrr,     X86::CVTTPD2DQrm,         TB_ALIGN_16 },
418    { X86::CVTTPS2DQrr,     X86::CVTTPS2DQrm,         TB_ALIGN_16 },
419    { X86::Int_CVTTSD2SI64rr,X86::Int_CVTTSD2SI64rm,  0 },
420    { X86::Int_CVTTSD2SIrr, X86::Int_CVTTSD2SIrm,     0 },
421    { X86::Int_CVTTSS2SI64rr,X86::Int_CVTTSS2SI64rm,  0 },
422    { X86::Int_CVTTSS2SIrr, X86::Int_CVTTSS2SIrm,     0 },
423    { X86::Int_UCOMISDrr,   X86::Int_UCOMISDrm,       0 },
424    { X86::Int_UCOMISSrr,   X86::Int_UCOMISSrm,       0 },
425    { X86::MOV16rr,         X86::MOV16rm,             0 },
426    { X86::MOV32rr,         X86::MOV32rm,             0 },
427    { X86::MOV64rr,         X86::MOV64rm,             0 },
428    { X86::MOV64toPQIrr,    X86::MOVQI2PQIrm,         0 },
429    { X86::MOV64toSDrr,     X86::MOV64toSDrm,         0 },
430    { X86::MOV8rr,          X86::MOV8rm,              0 },
431    { X86::MOVAPDrr,        X86::MOVAPDrm,            TB_ALIGN_16 },
432    { X86::MOVAPSrr,        X86::MOVAPSrm,            TB_ALIGN_16 },
433    { X86::MOVDDUPrr,       X86::MOVDDUPrm,           0 },
434    { X86::MOVDI2PDIrr,     X86::MOVDI2PDIrm,         0 },
435    { X86::MOVDI2SSrr,      X86::MOVDI2SSrm,          0 },
436    { X86::MOVDQArr,        X86::MOVDQArm,            TB_ALIGN_16 },
437    { X86::MOVSHDUPrr,      X86::MOVSHDUPrm,          TB_ALIGN_16 },
438    { X86::MOVSLDUPrr,      X86::MOVSLDUPrm,          TB_ALIGN_16 },
439    { X86::MOVSX16rr8,      X86::MOVSX16rm8,          0 },
440    { X86::MOVSX32rr16,     X86::MOVSX32rm16,         0 },
441    { X86::MOVSX32rr8,      X86::MOVSX32rm8,          0 },
442    { X86::MOVSX64rr16,     X86::MOVSX64rm16,         0 },
443    { X86::MOVSX64rr32,     X86::MOVSX64rm32,         0 },
444    { X86::MOVSX64rr8,      X86::MOVSX64rm8,          0 },
445    { X86::MOVUPDrr,        X86::MOVUPDrm,            TB_ALIGN_16 },
446    { X86::MOVUPSrr,        X86::MOVUPSrm,            0 },
447    { X86::MOVZDI2PDIrr,    X86::MOVZDI2PDIrm,        0 },
448    { X86::MOVZQI2PQIrr,    X86::MOVZQI2PQIrm,        0 },
449    { X86::MOVZPQILo2PQIrr, X86::MOVZPQILo2PQIrm,     TB_ALIGN_16 },
450    { X86::MOVZX16rr8,      X86::MOVZX16rm8,          0 },
451    { X86::MOVZX32rr16,     X86::MOVZX32rm16,         0 },
452    { X86::MOVZX32_NOREXrr8, X86::MOVZX32_NOREXrm8,   0 },
453    { X86::MOVZX32rr8,      X86::MOVZX32rm8,          0 },
454    { X86::MOVZX64rr16,     X86::MOVZX64rm16,         0 },
455    { X86::MOVZX64rr32,     X86::MOVZX64rm32,         0 },
456    { X86::MOVZX64rr8,      X86::MOVZX64rm8,          0 },
457    { X86::PABSBrr128,      X86::PABSBrm128,          TB_ALIGN_16 },
458    { X86::PABSDrr128,      X86::PABSDrm128,          TB_ALIGN_16 },
459    { X86::PABSWrr128,      X86::PABSWrm128,          TB_ALIGN_16 },
460    { X86::PSHUFDri,        X86::PSHUFDmi,            TB_ALIGN_16 },
461    { X86::PSHUFHWri,       X86::PSHUFHWmi,           TB_ALIGN_16 },
462    { X86::PSHUFLWri,       X86::PSHUFLWmi,           TB_ALIGN_16 },
463    { X86::RCPPSr,          X86::RCPPSm,              TB_ALIGN_16 },
464    { X86::RCPPSr_Int,      X86::RCPPSm_Int,          TB_ALIGN_16 },
465    { X86::RSQRTPSr,        X86::RSQRTPSm,            TB_ALIGN_16 },
466    { X86::RSQRTPSr_Int,    X86::RSQRTPSm_Int,        TB_ALIGN_16 },
467    { X86::RSQRTSSr,        X86::RSQRTSSm,            0 },
468    { X86::RSQRTSSr_Int,    X86::RSQRTSSm_Int,        0 },
469    { X86::SQRTPDr,         X86::SQRTPDm,             TB_ALIGN_16 },
470    { X86::SQRTPDr_Int,     X86::SQRTPDm_Int,         TB_ALIGN_16 },
471    { X86::SQRTPSr,         X86::SQRTPSm,             TB_ALIGN_16 },
472    { X86::SQRTPSr_Int,     X86::SQRTPSm_Int,         TB_ALIGN_16 },
473    { X86::SQRTSDr,         X86::SQRTSDm,             0 },
474    { X86::SQRTSDr_Int,     X86::SQRTSDm_Int,         0 },
475    { X86::SQRTSSr,         X86::SQRTSSm,             0 },
476    { X86::SQRTSSr_Int,     X86::SQRTSSm_Int,         0 },
477    { X86::TEST16rr,        X86::TEST16rm,            0 },
478    { X86::TEST32rr,        X86::TEST32rm,            0 },
479    { X86::TEST64rr,        X86::TEST64rm,            0 },
480    { X86::TEST8rr,         X86::TEST8rm,             0 },
481    // FIXME: TEST*rr EAX,EAX ---> CMP [mem], 0
482    { X86::UCOMISDrr,       X86::UCOMISDrm,           0 },
483    { X86::UCOMISSrr,       X86::UCOMISSrm,           0 },
484    // AVX 128-bit versions of foldable instructions
485    { X86::Int_VCOMISDrr,   X86::Int_VCOMISDrm,       0 },
486    { X86::Int_VCOMISSrr,   X86::Int_VCOMISSrm,       0 },
487    { X86::Int_VUCOMISDrr,  X86::Int_VUCOMISDrm,      0 },
488    { X86::Int_VUCOMISSrr,  X86::Int_VUCOMISSrm,      0 },
489    { X86::VCVTTSD2SI64rr,  X86::VCVTTSD2SI64rm,      0 },
490    { X86::Int_VCVTTSD2SI64rr,X86::Int_VCVTTSD2SI64rm,0 },
491    { X86::VCVTTSD2SIrr,    X86::VCVTTSD2SIrm,        0 },
492    { X86::Int_VCVTTSD2SIrr,X86::Int_VCVTTSD2SIrm,    0 },
493    { X86::VCVTTSS2SI64rr,  X86::VCVTTSS2SI64rm,      0 },
494    { X86::Int_VCVTTSS2SI64rr,X86::Int_VCVTTSS2SI64rm,0 },
495    { X86::VCVTTSS2SIrr,    X86::VCVTTSS2SIrm,        0 },
496    { X86::Int_VCVTTSS2SIrr,X86::Int_VCVTTSS2SIrm,    0 },
497    { X86::VCVTSD2SI64rr,   X86::VCVTSD2SI64rm,       0 },
498    { X86::VCVTSD2SIrr,     X86::VCVTSD2SIrm,         0 },
499    { X86::VCVTSS2SI64rr,   X86::VCVTSS2SI64rm,       0 },
500    { X86::VCVTSS2SIrr,     X86::VCVTSS2SIrm,         0 },
501    { X86::FsVMOVAPDrr,     X86::VMOVSDrm,            TB_NO_REVERSE },
502    { X86::FsVMOVAPSrr,     X86::VMOVSSrm,            TB_NO_REVERSE },
503    { X86::VMOV64toPQIrr,   X86::VMOVQI2PQIrm,        0 },
504    { X86::VMOV64toSDrr,    X86::VMOV64toSDrm,        0 },
505    { X86::VMOVAPDrr,       X86::VMOVAPDrm,           TB_ALIGN_16 },
506    { X86::VMOVAPSrr,       X86::VMOVAPSrm,           TB_ALIGN_16 },
507    { X86::VMOVDDUPrr,      X86::VMOVDDUPrm,          0 },
508    { X86::VMOVDI2PDIrr,    X86::VMOVDI2PDIrm,        0 },
509    { X86::VMOVDI2SSrr,     X86::VMOVDI2SSrm,         0 },
510    { X86::VMOVDQArr,       X86::VMOVDQArm,           TB_ALIGN_16 },
511    { X86::VMOVSLDUPrr,     X86::VMOVSLDUPrm,         TB_ALIGN_16 },
512    { X86::VMOVSHDUPrr,     X86::VMOVSHDUPrm,         TB_ALIGN_16 },
513    { X86::VMOVUPDrr,       X86::VMOVUPDrm,           TB_ALIGN_16 },
514    { X86::VMOVUPSrr,       X86::VMOVUPSrm,           0 },
515    { X86::VMOVZDI2PDIrr,   X86::VMOVZDI2PDIrm,       0 },
516    { X86::VMOVZQI2PQIrr,   X86::VMOVZQI2PQIrm,       0 },
517    { X86::VMOVZPQILo2PQIrr,X86::VMOVZPQILo2PQIrm,    TB_ALIGN_16 },
518    { X86::VPABSBrr128,     X86::VPABSBrm128,         TB_ALIGN_16 },
519    { X86::VPABSDrr128,     X86::VPABSDrm128,         TB_ALIGN_16 },
520    { X86::VPABSWrr128,     X86::VPABSWrm128,         TB_ALIGN_16 },
521    { X86::VPERMILPDri,     X86::VPERMILPDmi,         TB_ALIGN_16 },
522    { X86::VPERMILPSri,     X86::VPERMILPSmi,         TB_ALIGN_16 },
523    { X86::VPSHUFDri,       X86::VPSHUFDmi,           TB_ALIGN_16 },
524    { X86::VPSHUFHWri,      X86::VPSHUFHWmi,          TB_ALIGN_16 },
525    { X86::VPSHUFLWri,      X86::VPSHUFLWmi,          TB_ALIGN_16 },
526    { X86::VRCPPSr,         X86::VRCPPSm,             TB_ALIGN_16 },
527    { X86::VRCPPSr_Int,     X86::VRCPPSm_Int,         TB_ALIGN_16 },
528    { X86::VRSQRTPSr,       X86::VRSQRTPSm,           TB_ALIGN_16 },
529    { X86::VRSQRTPSr_Int,   X86::VRSQRTPSm_Int,       TB_ALIGN_16 },
530    { X86::VSQRTPDr,        X86::VSQRTPDm,            TB_ALIGN_16 },
531    { X86::VSQRTPDr_Int,    X86::VSQRTPDm_Int,        TB_ALIGN_16 },
532    { X86::VSQRTPSr,        X86::VSQRTPSm,            TB_ALIGN_16 },
533    { X86::VSQRTPSr_Int,    X86::VSQRTPSm_Int,        TB_ALIGN_16 },
534    { X86::VUCOMISDrr,      X86::VUCOMISDrm,          0 },
535    { X86::VUCOMISSrr,      X86::VUCOMISSrm,          0 },
536    { X86::VBROADCASTSSrr,  X86::VBROADCASTSSrm,      TB_NO_REVERSE },
537
538    // AVX 256-bit foldable instructions
539    { X86::VMOVAPDYrr,      X86::VMOVAPDYrm,          TB_ALIGN_32 },
540    { X86::VMOVAPSYrr,      X86::VMOVAPSYrm,          TB_ALIGN_32 },
541    { X86::VMOVDQAYrr,      X86::VMOVDQAYrm,          TB_ALIGN_32 },
542    { X86::VMOVUPDYrr,      X86::VMOVUPDYrm,          0 },
543    { X86::VMOVUPSYrr,      X86::VMOVUPSYrm,          0 },
544    { X86::VPERMILPDYri,    X86::VPERMILPDYmi,        TB_ALIGN_32 },
545    { X86::VPERMILPSYri,    X86::VPERMILPSYmi,        TB_ALIGN_32 },
546
547    // AVX2 foldable instructions
548    { X86::VPABSBrr256,     X86::VPABSBrm256,         TB_ALIGN_32 },
549    { X86::VPABSDrr256,     X86::VPABSDrm256,         TB_ALIGN_32 },
550    { X86::VPABSWrr256,     X86::VPABSWrm256,         TB_ALIGN_32 },
551    { X86::VPSHUFDYri,      X86::VPSHUFDYmi,          TB_ALIGN_32 },
552    { X86::VPSHUFHWYri,     X86::VPSHUFHWYmi,         TB_ALIGN_32 },
553    { X86::VPSHUFLWYri,     X86::VPSHUFLWYmi,         TB_ALIGN_32 },
554    { X86::VRCPPSYr,        X86::VRCPPSYm,            TB_ALIGN_32 },
555    { X86::VRCPPSYr_Int,    X86::VRCPPSYm_Int,        TB_ALIGN_32 },
556    { X86::VRSQRTPSYr,      X86::VRSQRTPSYm,          TB_ALIGN_32 },
557    { X86::VRSQRTPSYr_Int,  X86::VRSQRTPSYm_Int,      TB_ALIGN_32 },
558    { X86::VSQRTPDYr,       X86::VSQRTPDYm,           TB_ALIGN_32 },
559    { X86::VSQRTPDYr_Int,   X86::VSQRTPDYm_Int,       TB_ALIGN_32 },
560    { X86::VSQRTPSYr,       X86::VSQRTPSYm,           TB_ALIGN_32 },
561    { X86::VSQRTPSYr_Int,   X86::VSQRTPSYm_Int,       TB_ALIGN_32 },
562    { X86::VBROADCASTSSYrr, X86::VBROADCASTSSYrm,     TB_NO_REVERSE },
563    { X86::VBROADCASTSDYrr, X86::VBROADCASTSDYrm,     TB_NO_REVERSE },
564
565    // BMI/BMI2/LZCNT/POPCNT foldable instructions
566    { X86::BEXTR32rr,       X86::BEXTR32rm,           0 },
567    { X86::BEXTR64rr,       X86::BEXTR64rm,           0 },
568    { X86::BLSI32rr,        X86::BLSI32rm,            0 },
569    { X86::BLSI64rr,        X86::BLSI64rm,            0 },
570    { X86::BLSMSK32rr,      X86::BLSMSK32rm,          0 },
571    { X86::BLSMSK64rr,      X86::BLSMSK64rm,          0 },
572    { X86::BLSR32rr,        X86::BLSR32rm,            0 },
573    { X86::BLSR64rr,        X86::BLSR64rm,            0 },
574    { X86::BZHI32rr,        X86::BZHI32rm,            0 },
575    { X86::BZHI64rr,        X86::BZHI64rm,            0 },
576    { X86::LZCNT16rr,       X86::LZCNT16rm,           0 },
577    { X86::LZCNT32rr,       X86::LZCNT32rm,           0 },
578    { X86::LZCNT64rr,       X86::LZCNT64rm,           0 },
579    { X86::POPCNT16rr,      X86::POPCNT16rm,          0 },
580    { X86::POPCNT32rr,      X86::POPCNT32rm,          0 },
581    { X86::POPCNT64rr,      X86::POPCNT64rm,          0 },
582    { X86::RORX32ri,        X86::RORX32mi,            0 },
583    { X86::RORX64ri,        X86::RORX64mi,            0 },
584    { X86::SARX32rr,        X86::SARX32rm,            0 },
585    { X86::SARX64rr,        X86::SARX64rm,            0 },
586    { X86::SHRX32rr,        X86::SHRX32rm,            0 },
587    { X86::SHRX64rr,        X86::SHRX64rm,            0 },
588    { X86::SHLX32rr,        X86::SHLX32rm,            0 },
589    { X86::SHLX64rr,        X86::SHLX64rm,            0 },
590    { X86::TZCNT16rr,       X86::TZCNT16rm,           0 },
591    { X86::TZCNT32rr,       X86::TZCNT32rm,           0 },
592    { X86::TZCNT64rr,       X86::TZCNT64rm,           0 },
593  };
594
595  for (unsigned i = 0, e = array_lengthof(OpTbl1); i != e; ++i) {
596    unsigned RegOp = OpTbl1[i].RegOp;
597    unsigned MemOp = OpTbl1[i].MemOp;
598    unsigned Flags = OpTbl1[i].Flags;
599    AddTableEntry(RegOp2MemOpTable1, MemOp2RegOpTable,
600                  RegOp, MemOp,
601                  // Index 1, folded load
602                  Flags | TB_INDEX_1 | TB_FOLDED_LOAD);
603  }
604
605  static const X86OpTblEntry OpTbl2[] = {
606    { X86::ADC32rr,         X86::ADC32rm,       0 },
607    { X86::ADC64rr,         X86::ADC64rm,       0 },
608    { X86::ADD16rr,         X86::ADD16rm,       0 },
609    { X86::ADD16rr_DB,      X86::ADD16rm,       TB_NO_REVERSE },
610    { X86::ADD32rr,         X86::ADD32rm,       0 },
611    { X86::ADD32rr_DB,      X86::ADD32rm,       TB_NO_REVERSE },
612    { X86::ADD64rr,         X86::ADD64rm,       0 },
613    { X86::ADD64rr_DB,      X86::ADD64rm,       TB_NO_REVERSE },
614    { X86::ADD8rr,          X86::ADD8rm,        0 },
615    { X86::ADDPDrr,         X86::ADDPDrm,       TB_ALIGN_16 },
616    { X86::ADDPSrr,         X86::ADDPSrm,       TB_ALIGN_16 },
617    { X86::ADDSDrr,         X86::ADDSDrm,       0 },
618    { X86::ADDSSrr,         X86::ADDSSrm,       0 },
619    { X86::ADDSUBPDrr,      X86::ADDSUBPDrm,    TB_ALIGN_16 },
620    { X86::ADDSUBPSrr,      X86::ADDSUBPSrm,    TB_ALIGN_16 },
621    { X86::AND16rr,         X86::AND16rm,       0 },
622    { X86::AND32rr,         X86::AND32rm,       0 },
623    { X86::AND64rr,         X86::AND64rm,       0 },
624    { X86::AND8rr,          X86::AND8rm,        0 },
625    { X86::ANDNPDrr,        X86::ANDNPDrm,      TB_ALIGN_16 },
626    { X86::ANDNPSrr,        X86::ANDNPSrm,      TB_ALIGN_16 },
627    { X86::ANDPDrr,         X86::ANDPDrm,       TB_ALIGN_16 },
628    { X86::ANDPSrr,         X86::ANDPSrm,       TB_ALIGN_16 },
629    { X86::BLENDPDrri,      X86::BLENDPDrmi,    TB_ALIGN_16 },
630    { X86::BLENDPSrri,      X86::BLENDPSrmi,    TB_ALIGN_16 },
631    { X86::BLENDVPDrr0,     X86::BLENDVPDrm0,   TB_ALIGN_16 },
632    { X86::BLENDVPSrr0,     X86::BLENDVPSrm0,   TB_ALIGN_16 },
633    { X86::CMOVA16rr,       X86::CMOVA16rm,     0 },
634    { X86::CMOVA32rr,       X86::CMOVA32rm,     0 },
635    { X86::CMOVA64rr,       X86::CMOVA64rm,     0 },
636    { X86::CMOVAE16rr,      X86::CMOVAE16rm,    0 },
637    { X86::CMOVAE32rr,      X86::CMOVAE32rm,    0 },
638    { X86::CMOVAE64rr,      X86::CMOVAE64rm,    0 },
639    { X86::CMOVB16rr,       X86::CMOVB16rm,     0 },
640    { X86::CMOVB32rr,       X86::CMOVB32rm,     0 },
641    { X86::CMOVB64rr,       X86::CMOVB64rm,     0 },
642    { X86::CMOVBE16rr,      X86::CMOVBE16rm,    0 },
643    { X86::CMOVBE32rr,      X86::CMOVBE32rm,    0 },
644    { X86::CMOVBE64rr,      X86::CMOVBE64rm,    0 },
645    { X86::CMOVE16rr,       X86::CMOVE16rm,     0 },
646    { X86::CMOVE32rr,       X86::CMOVE32rm,     0 },
647    { X86::CMOVE64rr,       X86::CMOVE64rm,     0 },
648    { X86::CMOVG16rr,       X86::CMOVG16rm,     0 },
649    { X86::CMOVG32rr,       X86::CMOVG32rm,     0 },
650    { X86::CMOVG64rr,       X86::CMOVG64rm,     0 },
651    { X86::CMOVGE16rr,      X86::CMOVGE16rm,    0 },
652    { X86::CMOVGE32rr,      X86::CMOVGE32rm,    0 },
653    { X86::CMOVGE64rr,      X86::CMOVGE64rm,    0 },
654    { X86::CMOVL16rr,       X86::CMOVL16rm,     0 },
655    { X86::CMOVL32rr,       X86::CMOVL32rm,     0 },
656    { X86::CMOVL64rr,       X86::CMOVL64rm,     0 },
657    { X86::CMOVLE16rr,      X86::CMOVLE16rm,    0 },
658    { X86::CMOVLE32rr,      X86::CMOVLE32rm,    0 },
659    { X86::CMOVLE64rr,      X86::CMOVLE64rm,    0 },
660    { X86::CMOVNE16rr,      X86::CMOVNE16rm,    0 },
661    { X86::CMOVNE32rr,      X86::CMOVNE32rm,    0 },
662    { X86::CMOVNE64rr,      X86::CMOVNE64rm,    0 },
663    { X86::CMOVNO16rr,      X86::CMOVNO16rm,    0 },
664    { X86::CMOVNO32rr,      X86::CMOVNO32rm,    0 },
665    { X86::CMOVNO64rr,      X86::CMOVNO64rm,    0 },
666    { X86::CMOVNP16rr,      X86::CMOVNP16rm,    0 },
667    { X86::CMOVNP32rr,      X86::CMOVNP32rm,    0 },
668    { X86::CMOVNP64rr,      X86::CMOVNP64rm,    0 },
669    { X86::CMOVNS16rr,      X86::CMOVNS16rm,    0 },
670    { X86::CMOVNS32rr,      X86::CMOVNS32rm,    0 },
671    { X86::CMOVNS64rr,      X86::CMOVNS64rm,    0 },
672    { X86::CMOVO16rr,       X86::CMOVO16rm,     0 },
673    { X86::CMOVO32rr,       X86::CMOVO32rm,     0 },
674    { X86::CMOVO64rr,       X86::CMOVO64rm,     0 },
675    { X86::CMOVP16rr,       X86::CMOVP16rm,     0 },
676    { X86::CMOVP32rr,       X86::CMOVP32rm,     0 },
677    { X86::CMOVP64rr,       X86::CMOVP64rm,     0 },
678    { X86::CMOVS16rr,       X86::CMOVS16rm,     0 },
679    { X86::CMOVS32rr,       X86::CMOVS32rm,     0 },
680    { X86::CMOVS64rr,       X86::CMOVS64rm,     0 },
681    { X86::CMPPDrri,        X86::CMPPDrmi,      TB_ALIGN_16 },
682    { X86::CMPPSrri,        X86::CMPPSrmi,      TB_ALIGN_16 },
683    { X86::CMPSDrr,         X86::CMPSDrm,       0 },
684    { X86::CMPSSrr,         X86::CMPSSrm,       0 },
685    { X86::DIVPDrr,         X86::DIVPDrm,       TB_ALIGN_16 },
686    { X86::DIVPSrr,         X86::DIVPSrm,       TB_ALIGN_16 },
687    { X86::DIVSDrr,         X86::DIVSDrm,       0 },
688    { X86::DIVSSrr,         X86::DIVSSrm,       0 },
689    { X86::FsANDNPDrr,      X86::FsANDNPDrm,    TB_ALIGN_16 },
690    { X86::FsANDNPSrr,      X86::FsANDNPSrm,    TB_ALIGN_16 },
691    { X86::FsANDPDrr,       X86::FsANDPDrm,     TB_ALIGN_16 },
692    { X86::FsANDPSrr,       X86::FsANDPSrm,     TB_ALIGN_16 },
693    { X86::FsORPDrr,        X86::FsORPDrm,      TB_ALIGN_16 },
694    { X86::FsORPSrr,        X86::FsORPSrm,      TB_ALIGN_16 },
695    { X86::FsXORPDrr,       X86::FsXORPDrm,     TB_ALIGN_16 },
696    { X86::FsXORPSrr,       X86::FsXORPSrm,     TB_ALIGN_16 },
697    { X86::HADDPDrr,        X86::HADDPDrm,      TB_ALIGN_16 },
698    { X86::HADDPSrr,        X86::HADDPSrm,      TB_ALIGN_16 },
699    { X86::HSUBPDrr,        X86::HSUBPDrm,      TB_ALIGN_16 },
700    { X86::HSUBPSrr,        X86::HSUBPSrm,      TB_ALIGN_16 },
701    { X86::IMUL16rr,        X86::IMUL16rm,      0 },
702    { X86::IMUL32rr,        X86::IMUL32rm,      0 },
703    { X86::IMUL64rr,        X86::IMUL64rm,      0 },
704    { X86::Int_CMPSDrr,     X86::Int_CMPSDrm,   0 },
705    { X86::Int_CMPSSrr,     X86::Int_CMPSSrm,   0 },
706    { X86::Int_CVTSD2SSrr,  X86::Int_CVTSD2SSrm,      0 },
707    { X86::Int_CVTSI2SD64rr,X86::Int_CVTSI2SD64rm,    0 },
708    { X86::Int_CVTSI2SDrr,  X86::Int_CVTSI2SDrm,      0 },
709    { X86::Int_CVTSI2SS64rr,X86::Int_CVTSI2SS64rm,    0 },
710    { X86::Int_CVTSI2SSrr,  X86::Int_CVTSI2SSrm,      0 },
711    { X86::Int_CVTSS2SDrr,  X86::Int_CVTSS2SDrm,      0 },
712    { X86::MAXPDrr,         X86::MAXPDrm,       TB_ALIGN_16 },
713    { X86::MAXPDrr_Int,     X86::MAXPDrm_Int,   TB_ALIGN_16 },
714    { X86::MAXPSrr,         X86::MAXPSrm,       TB_ALIGN_16 },
715    { X86::MAXPSrr_Int,     X86::MAXPSrm_Int,   TB_ALIGN_16 },
716    { X86::MAXSDrr,         X86::MAXSDrm,       0 },
717    { X86::MAXSDrr_Int,     X86::MAXSDrm_Int,   0 },
718    { X86::MAXSSrr,         X86::MAXSSrm,       0 },
719    { X86::MAXSSrr_Int,     X86::MAXSSrm_Int,   0 },
720    { X86::MINPDrr,         X86::MINPDrm,       TB_ALIGN_16 },
721    { X86::MINPDrr_Int,     X86::MINPDrm_Int,   TB_ALIGN_16 },
722    { X86::MINPSrr,         X86::MINPSrm,       TB_ALIGN_16 },
723    { X86::MINPSrr_Int,     X86::MINPSrm_Int,   TB_ALIGN_16 },
724    { X86::MINSDrr,         X86::MINSDrm,       0 },
725    { X86::MINSDrr_Int,     X86::MINSDrm_Int,   0 },
726    { X86::MINSSrr,         X86::MINSSrm,       0 },
727    { X86::MINSSrr_Int,     X86::MINSSrm_Int,   0 },
728    { X86::MPSADBWrri,      X86::MPSADBWrmi,    TB_ALIGN_16 },
729    { X86::MULPDrr,         X86::MULPDrm,       TB_ALIGN_16 },
730    { X86::MULPSrr,         X86::MULPSrm,       TB_ALIGN_16 },
731    { X86::MULSDrr,         X86::MULSDrm,       0 },
732    { X86::MULSSrr,         X86::MULSSrm,       0 },
733    { X86::OR16rr,          X86::OR16rm,        0 },
734    { X86::OR32rr,          X86::OR32rm,        0 },
735    { X86::OR64rr,          X86::OR64rm,        0 },
736    { X86::OR8rr,           X86::OR8rm,         0 },
737    { X86::ORPDrr,          X86::ORPDrm,        TB_ALIGN_16 },
738    { X86::ORPSrr,          X86::ORPSrm,        TB_ALIGN_16 },
739    { X86::PACKSSDWrr,      X86::PACKSSDWrm,    TB_ALIGN_16 },
740    { X86::PACKSSWBrr,      X86::PACKSSWBrm,    TB_ALIGN_16 },
741    { X86::PACKUSDWrr,      X86::PACKUSDWrm,    TB_ALIGN_16 },
742    { X86::PACKUSWBrr,      X86::PACKUSWBrm,    TB_ALIGN_16 },
743    { X86::PADDBrr,         X86::PADDBrm,       TB_ALIGN_16 },
744    { X86::PADDDrr,         X86::PADDDrm,       TB_ALIGN_16 },
745    { X86::PADDQrr,         X86::PADDQrm,       TB_ALIGN_16 },
746    { X86::PADDSBrr,        X86::PADDSBrm,      TB_ALIGN_16 },
747    { X86::PADDSWrr,        X86::PADDSWrm,      TB_ALIGN_16 },
748    { X86::PADDUSBrr,       X86::PADDUSBrm,     TB_ALIGN_16 },
749    { X86::PADDUSWrr,       X86::PADDUSWrm,     TB_ALIGN_16 },
750    { X86::PADDWrr,         X86::PADDWrm,       TB_ALIGN_16 },
751    { X86::PALIGNR128rr,    X86::PALIGNR128rm,  TB_ALIGN_16 },
752    { X86::PANDNrr,         X86::PANDNrm,       TB_ALIGN_16 },
753    { X86::PANDrr,          X86::PANDrm,        TB_ALIGN_16 },
754    { X86::PAVGBrr,         X86::PAVGBrm,       TB_ALIGN_16 },
755    { X86::PAVGWrr,         X86::PAVGWrm,       TB_ALIGN_16 },
756    { X86::PBLENDWrri,      X86::PBLENDWrmi,    TB_ALIGN_16 },
757    { X86::PCMPEQBrr,       X86::PCMPEQBrm,     TB_ALIGN_16 },
758    { X86::PCMPEQDrr,       X86::PCMPEQDrm,     TB_ALIGN_16 },
759    { X86::PCMPEQQrr,       X86::PCMPEQQrm,     TB_ALIGN_16 },
760    { X86::PCMPEQWrr,       X86::PCMPEQWrm,     TB_ALIGN_16 },
761    { X86::PCMPGTBrr,       X86::PCMPGTBrm,     TB_ALIGN_16 },
762    { X86::PCMPGTDrr,       X86::PCMPGTDrm,     TB_ALIGN_16 },
763    { X86::PCMPGTQrr,       X86::PCMPGTQrm,     TB_ALIGN_16 },
764    { X86::PCMPGTWrr,       X86::PCMPGTWrm,     TB_ALIGN_16 },
765    { X86::PHADDDrr,        X86::PHADDDrm,      TB_ALIGN_16 },
766    { X86::PHADDWrr,        X86::PHADDWrm,      TB_ALIGN_16 },
767    { X86::PHADDSWrr128,    X86::PHADDSWrm128,  TB_ALIGN_16 },
768    { X86::PHSUBDrr,        X86::PHSUBDrm,      TB_ALIGN_16 },
769    { X86::PHSUBSWrr128,    X86::PHSUBSWrm128,  TB_ALIGN_16 },
770    { X86::PHSUBWrr,        X86::PHSUBWrm,      TB_ALIGN_16 },
771    { X86::PINSRWrri,       X86::PINSRWrmi,     TB_ALIGN_16 },
772    { X86::PMADDUBSWrr128,  X86::PMADDUBSWrm128, TB_ALIGN_16 },
773    { X86::PMADDWDrr,       X86::PMADDWDrm,     TB_ALIGN_16 },
774    { X86::PMAXSWrr,        X86::PMAXSWrm,      TB_ALIGN_16 },
775    { X86::PMAXUBrr,        X86::PMAXUBrm,      TB_ALIGN_16 },
776    { X86::PMINSWrr,        X86::PMINSWrm,      TB_ALIGN_16 },
777    { X86::PMINUBrr,        X86::PMINUBrm,      TB_ALIGN_16 },
778    { X86::PMINSBrr,        X86::PMINSBrm,      TB_ALIGN_16 },
779    { X86::PMINSDrr,        X86::PMINSDrm,      TB_ALIGN_16 },
780    { X86::PMINUDrr,        X86::PMINUDrm,      TB_ALIGN_16 },
781    { X86::PMINUWrr,        X86::PMINUWrm,      TB_ALIGN_16 },
782    { X86::PMAXSBrr,        X86::PMAXSBrm,      TB_ALIGN_16 },
783    { X86::PMAXSDrr,        X86::PMAXSDrm,      TB_ALIGN_16 },
784    { X86::PMAXUDrr,        X86::PMAXUDrm,      TB_ALIGN_16 },
785    { X86::PMAXUWrr,        X86::PMAXUWrm,      TB_ALIGN_16 },
786    { X86::PMULDQrr,        X86::PMULDQrm,      TB_ALIGN_16 },
787    { X86::PMULHRSWrr128,   X86::PMULHRSWrm128, TB_ALIGN_16 },
788    { X86::PMULHUWrr,       X86::PMULHUWrm,     TB_ALIGN_16 },
789    { X86::PMULHWrr,        X86::PMULHWrm,      TB_ALIGN_16 },
790    { X86::PMULLDrr,        X86::PMULLDrm,      TB_ALIGN_16 },
791    { X86::PMULLWrr,        X86::PMULLWrm,      TB_ALIGN_16 },
792    { X86::PMULUDQrr,       X86::PMULUDQrm,     TB_ALIGN_16 },
793    { X86::PORrr,           X86::PORrm,         TB_ALIGN_16 },
794    { X86::PSADBWrr,        X86::PSADBWrm,      TB_ALIGN_16 },
795    { X86::PSHUFBrr,        X86::PSHUFBrm,      TB_ALIGN_16 },
796    { X86::PSIGNBrr,        X86::PSIGNBrm,      TB_ALIGN_16 },
797    { X86::PSIGNWrr,        X86::PSIGNWrm,      TB_ALIGN_16 },
798    { X86::PSIGNDrr,        X86::PSIGNDrm,      TB_ALIGN_16 },
799    { X86::PSLLDrr,         X86::PSLLDrm,       TB_ALIGN_16 },
800    { X86::PSLLQrr,         X86::PSLLQrm,       TB_ALIGN_16 },
801    { X86::PSLLWrr,         X86::PSLLWrm,       TB_ALIGN_16 },
802    { X86::PSRADrr,         X86::PSRADrm,       TB_ALIGN_16 },
803    { X86::PSRAWrr,         X86::PSRAWrm,       TB_ALIGN_16 },
804    { X86::PSRLDrr,         X86::PSRLDrm,       TB_ALIGN_16 },
805    { X86::PSRLQrr,         X86::PSRLQrm,       TB_ALIGN_16 },
806    { X86::PSRLWrr,         X86::PSRLWrm,       TB_ALIGN_16 },
807    { X86::PSUBBrr,         X86::PSUBBrm,       TB_ALIGN_16 },
808    { X86::PSUBDrr,         X86::PSUBDrm,       TB_ALIGN_16 },
809    { X86::PSUBSBrr,        X86::PSUBSBrm,      TB_ALIGN_16 },
810    { X86::PSUBSWrr,        X86::PSUBSWrm,      TB_ALIGN_16 },
811    { X86::PSUBWrr,         X86::PSUBWrm,       TB_ALIGN_16 },
812    { X86::PUNPCKHBWrr,     X86::PUNPCKHBWrm,   TB_ALIGN_16 },
813    { X86::PUNPCKHDQrr,     X86::PUNPCKHDQrm,   TB_ALIGN_16 },
814    { X86::PUNPCKHQDQrr,    X86::PUNPCKHQDQrm,  TB_ALIGN_16 },
815    { X86::PUNPCKHWDrr,     X86::PUNPCKHWDrm,   TB_ALIGN_16 },
816    { X86::PUNPCKLBWrr,     X86::PUNPCKLBWrm,   TB_ALIGN_16 },
817    { X86::PUNPCKLDQrr,     X86::PUNPCKLDQrm,   TB_ALIGN_16 },
818    { X86::PUNPCKLQDQrr,    X86::PUNPCKLQDQrm,  TB_ALIGN_16 },
819    { X86::PUNPCKLWDrr,     X86::PUNPCKLWDrm,   TB_ALIGN_16 },
820    { X86::PXORrr,          X86::PXORrm,        TB_ALIGN_16 },
821    { X86::SBB32rr,         X86::SBB32rm,       0 },
822    { X86::SBB64rr,         X86::SBB64rm,       0 },
823    { X86::SHUFPDrri,       X86::SHUFPDrmi,     TB_ALIGN_16 },
824    { X86::SHUFPSrri,       X86::SHUFPSrmi,     TB_ALIGN_16 },
825    { X86::SUB16rr,         X86::SUB16rm,       0 },
826    { X86::SUB32rr,         X86::SUB32rm,       0 },
827    { X86::SUB64rr,         X86::SUB64rm,       0 },
828    { X86::SUB8rr,          X86::SUB8rm,        0 },
829    { X86::SUBPDrr,         X86::SUBPDrm,       TB_ALIGN_16 },
830    { X86::SUBPSrr,         X86::SUBPSrm,       TB_ALIGN_16 },
831    { X86::SUBSDrr,         X86::SUBSDrm,       0 },
832    { X86::SUBSSrr,         X86::SUBSSrm,       0 },
833    // FIXME: TEST*rr -> swapped operand of TEST*mr.
834    { X86::UNPCKHPDrr,      X86::UNPCKHPDrm,    TB_ALIGN_16 },
835    { X86::UNPCKHPSrr,      X86::UNPCKHPSrm,    TB_ALIGN_16 },
836    { X86::UNPCKLPDrr,      X86::UNPCKLPDrm,    TB_ALIGN_16 },
837    { X86::UNPCKLPSrr,      X86::UNPCKLPSrm,    TB_ALIGN_16 },
838    { X86::XOR16rr,         X86::XOR16rm,       0 },
839    { X86::XOR32rr,         X86::XOR32rm,       0 },
840    { X86::XOR64rr,         X86::XOR64rm,       0 },
841    { X86::XOR8rr,          X86::XOR8rm,        0 },
842    { X86::XORPDrr,         X86::XORPDrm,       TB_ALIGN_16 },
843    { X86::XORPSrr,         X86::XORPSrm,       TB_ALIGN_16 },
844    // AVX 128-bit versions of foldable instructions
845    { X86::VCVTSD2SSrr,       X86::VCVTSD2SSrm,        0 },
846    { X86::Int_VCVTSD2SSrr,   X86::Int_VCVTSD2SSrm,    0 },
847    { X86::VCVTSI2SD64rr,     X86::VCVTSI2SD64rm,      0 },
848    { X86::Int_VCVTSI2SD64rr, X86::Int_VCVTSI2SD64rm,  0 },
849    { X86::VCVTSI2SDrr,       X86::VCVTSI2SDrm,        0 },
850    { X86::Int_VCVTSI2SDrr,   X86::Int_VCVTSI2SDrm,    0 },
851    { X86::VCVTSI2SS64rr,     X86::VCVTSI2SS64rm,      0 },
852    { X86::Int_VCVTSI2SS64rr, X86::Int_VCVTSI2SS64rm,  0 },
853    { X86::VCVTSI2SSrr,       X86::VCVTSI2SSrm,        0 },
854    { X86::Int_VCVTSI2SSrr,   X86::Int_VCVTSI2SSrm,    0 },
855    { X86::VCVTSS2SDrr,       X86::VCVTSS2SDrm,        0 },
856    { X86::Int_VCVTSS2SDrr,   X86::Int_VCVTSS2SDrm,    0 },
857    { X86::VCVTTPD2DQrr,      X86::VCVTTPD2DQXrm,      TB_ALIGN_16 },
858    { X86::VCVTTPS2DQrr,      X86::VCVTTPS2DQrm,       TB_ALIGN_16 },
859    { X86::VRSQRTSSr,         X86::VRSQRTSSm,          0 },
860    { X86::VSQRTSDr,          X86::VSQRTSDm,           0 },
861    { X86::VSQRTSSr,          X86::VSQRTSSm,           0 },
862    { X86::VADDPDrr,          X86::VADDPDrm,           TB_ALIGN_16 },
863    { X86::VADDPSrr,          X86::VADDPSrm,           TB_ALIGN_16 },
864    { X86::VADDSDrr,          X86::VADDSDrm,           0 },
865    { X86::VADDSSrr,          X86::VADDSSrm,           0 },
866    { X86::VADDSUBPDrr,       X86::VADDSUBPDrm,        TB_ALIGN_16 },
867    { X86::VADDSUBPSrr,       X86::VADDSUBPSrm,        TB_ALIGN_16 },
868    { X86::VANDNPDrr,         X86::VANDNPDrm,          TB_ALIGN_16 },
869    { X86::VANDNPSrr,         X86::VANDNPSrm,          TB_ALIGN_16 },
870    { X86::VANDPDrr,          X86::VANDPDrm,           TB_ALIGN_16 },
871    { X86::VANDPSrr,          X86::VANDPSrm,           TB_ALIGN_16 },
872    { X86::VBLENDPDrri,       X86::VBLENDPDrmi,        TB_ALIGN_16 },
873    { X86::VBLENDPSrri,       X86::VBLENDPSrmi,        TB_ALIGN_16 },
874    { X86::VBLENDVPDrr,       X86::VBLENDVPDrm,        TB_ALIGN_16 },
875    { X86::VBLENDVPSrr,       X86::VBLENDVPSrm,        TB_ALIGN_16 },
876    { X86::VCMPPDrri,         X86::VCMPPDrmi,          TB_ALIGN_16 },
877    { X86::VCMPPSrri,         X86::VCMPPSrmi,          TB_ALIGN_16 },
878    { X86::VCMPSDrr,          X86::VCMPSDrm,           0 },
879    { X86::VCMPSSrr,          X86::VCMPSSrm,           0 },
880    { X86::VDIVPDrr,          X86::VDIVPDrm,           TB_ALIGN_16 },
881    { X86::VDIVPSrr,          X86::VDIVPSrm,           TB_ALIGN_16 },
882    { X86::VDIVSDrr,          X86::VDIVSDrm,           0 },
883    { X86::VDIVSSrr,          X86::VDIVSSrm,           0 },
884    { X86::VFsANDNPDrr,       X86::VFsANDNPDrm,        TB_ALIGN_16 },
885    { X86::VFsANDNPSrr,       X86::VFsANDNPSrm,        TB_ALIGN_16 },
886    { X86::VFsANDPDrr,        X86::VFsANDPDrm,         TB_ALIGN_16 },
887    { X86::VFsANDPSrr,        X86::VFsANDPSrm,         TB_ALIGN_16 },
888    { X86::VFsORPDrr,         X86::VFsORPDrm,          TB_ALIGN_16 },
889    { X86::VFsORPSrr,         X86::VFsORPSrm,          TB_ALIGN_16 },
890    { X86::VFsXORPDrr,        X86::VFsXORPDrm,         TB_ALIGN_16 },
891    { X86::VFsXORPSrr,        X86::VFsXORPSrm,         TB_ALIGN_16 },
892    { X86::VHADDPDrr,         X86::VHADDPDrm,          TB_ALIGN_16 },
893    { X86::VHADDPSrr,         X86::VHADDPSrm,          TB_ALIGN_16 },
894    { X86::VHSUBPDrr,         X86::VHSUBPDrm,          TB_ALIGN_16 },
895    { X86::VHSUBPSrr,         X86::VHSUBPSrm,          TB_ALIGN_16 },
896    { X86::Int_VCMPSDrr,      X86::Int_VCMPSDrm,       0 },
897    { X86::Int_VCMPSSrr,      X86::Int_VCMPSSrm,       0 },
898    { X86::VMAXPDrr,          X86::VMAXPDrm,           TB_ALIGN_16 },
899    { X86::VMAXPDrr_Int,      X86::VMAXPDrm_Int,       TB_ALIGN_16 },
900    { X86::VMAXPSrr,          X86::VMAXPSrm,           TB_ALIGN_16 },
901    { X86::VMAXPSrr_Int,      X86::VMAXPSrm_Int,       TB_ALIGN_16 },
902    { X86::VMAXSDrr,          X86::VMAXSDrm,           0 },
903    { X86::VMAXSDrr_Int,      X86::VMAXSDrm_Int,       0 },
904    { X86::VMAXSSrr,          X86::VMAXSSrm,           0 },
905    { X86::VMAXSSrr_Int,      X86::VMAXSSrm_Int,       0 },
906    { X86::VMINPDrr,          X86::VMINPDrm,           TB_ALIGN_16 },
907    { X86::VMINPDrr_Int,      X86::VMINPDrm_Int,       TB_ALIGN_16 },
908    { X86::VMINPSrr,          X86::VMINPSrm,           TB_ALIGN_16 },
909    { X86::VMINPSrr_Int,      X86::VMINPSrm_Int,       TB_ALIGN_16 },
910    { X86::VMINSDrr,          X86::VMINSDrm,           0 },
911    { X86::VMINSDrr_Int,      X86::VMINSDrm_Int,       0 },
912    { X86::VMINSSrr,          X86::VMINSSrm,           0 },
913    { X86::VMINSSrr_Int,      X86::VMINSSrm_Int,       0 },
914    { X86::VMPSADBWrri,       X86::VMPSADBWrmi,        TB_ALIGN_16 },
915    { X86::VMULPDrr,          X86::VMULPDrm,           TB_ALIGN_16 },
916    { X86::VMULPSrr,          X86::VMULPSrm,           TB_ALIGN_16 },
917    { X86::VMULSDrr,          X86::VMULSDrm,           0 },
918    { X86::VMULSSrr,          X86::VMULSSrm,           0 },
919    { X86::VORPDrr,           X86::VORPDrm,            TB_ALIGN_16 },
920    { X86::VORPSrr,           X86::VORPSrm,            TB_ALIGN_16 },
921    { X86::VPACKSSDWrr,       X86::VPACKSSDWrm,        TB_ALIGN_16 },
922    { X86::VPACKSSWBrr,       X86::VPACKSSWBrm,        TB_ALIGN_16 },
923    { X86::VPACKUSDWrr,       X86::VPACKUSDWrm,        TB_ALIGN_16 },
924    { X86::VPACKUSWBrr,       X86::VPACKUSWBrm,        TB_ALIGN_16 },
925    { X86::VPADDBrr,          X86::VPADDBrm,           TB_ALIGN_16 },
926    { X86::VPADDDrr,          X86::VPADDDrm,           TB_ALIGN_16 },
927    { X86::VPADDQrr,          X86::VPADDQrm,           TB_ALIGN_16 },
928    { X86::VPADDSBrr,         X86::VPADDSBrm,          TB_ALIGN_16 },
929    { X86::VPADDSWrr,         X86::VPADDSWrm,          TB_ALIGN_16 },
930    { X86::VPADDUSBrr,        X86::VPADDUSBrm,         TB_ALIGN_16 },
931    { X86::VPADDUSWrr,        X86::VPADDUSWrm,         TB_ALIGN_16 },
932    { X86::VPADDWrr,          X86::VPADDWrm,           TB_ALIGN_16 },
933    { X86::VPALIGNR128rr,     X86::VPALIGNR128rm,      TB_ALIGN_16 },
934    { X86::VPANDNrr,          X86::VPANDNrm,           TB_ALIGN_16 },
935    { X86::VPANDrr,           X86::VPANDrm,            TB_ALIGN_16 },
936    { X86::VPAVGBrr,          X86::VPAVGBrm,           TB_ALIGN_16 },
937    { X86::VPAVGWrr,          X86::VPAVGWrm,           TB_ALIGN_16 },
938    { X86::VPBLENDWrri,       X86::VPBLENDWrmi,        TB_ALIGN_16 },
939    { X86::VPCMPEQBrr,        X86::VPCMPEQBrm,         TB_ALIGN_16 },
940    { X86::VPCMPEQDrr,        X86::VPCMPEQDrm,         TB_ALIGN_16 },
941    { X86::VPCMPEQQrr,        X86::VPCMPEQQrm,         TB_ALIGN_16 },
942    { X86::VPCMPEQWrr,        X86::VPCMPEQWrm,         TB_ALIGN_16 },
943    { X86::VPCMPGTBrr,        X86::VPCMPGTBrm,         TB_ALIGN_16 },
944    { X86::VPCMPGTDrr,        X86::VPCMPGTDrm,         TB_ALIGN_16 },
945    { X86::VPCMPGTQrr,        X86::VPCMPGTQrm,         TB_ALIGN_16 },
946    { X86::VPCMPGTWrr,        X86::VPCMPGTWrm,         TB_ALIGN_16 },
947    { X86::VPHADDDrr,         X86::VPHADDDrm,          TB_ALIGN_16 },
948    { X86::VPHADDSWrr128,     X86::VPHADDSWrm128,      TB_ALIGN_16 },
949    { X86::VPHADDWrr,         X86::VPHADDWrm,          TB_ALIGN_16 },
950    { X86::VPHSUBDrr,         X86::VPHSUBDrm,          TB_ALIGN_16 },
951    { X86::VPHSUBSWrr128,     X86::VPHSUBSWrm128,      TB_ALIGN_16 },
952    { X86::VPHSUBWrr,         X86::VPHSUBWrm,          TB_ALIGN_16 },
953    { X86::VPERMILPDrr,       X86::VPERMILPDrm,        TB_ALIGN_16 },
954    { X86::VPERMILPSrr,       X86::VPERMILPSrm,        TB_ALIGN_16 },
955    { X86::VPINSRWrri,        X86::VPINSRWrmi,         TB_ALIGN_16 },
956    { X86::VPMADDUBSWrr128,   X86::VPMADDUBSWrm128,    TB_ALIGN_16 },
957    { X86::VPMADDWDrr,        X86::VPMADDWDrm,         TB_ALIGN_16 },
958    { X86::VPMAXSWrr,         X86::VPMAXSWrm,          TB_ALIGN_16 },
959    { X86::VPMAXUBrr,         X86::VPMAXUBrm,          TB_ALIGN_16 },
960    { X86::VPMINSWrr,         X86::VPMINSWrm,          TB_ALIGN_16 },
961    { X86::VPMINUBrr,         X86::VPMINUBrm,          TB_ALIGN_16 },
962    { X86::VPMINSBrr,         X86::VPMINSBrm,          TB_ALIGN_16 },
963    { X86::VPMINSDrr,         X86::VPMINSDrm,          TB_ALIGN_16 },
964    { X86::VPMINUDrr,         X86::VPMINUDrm,          TB_ALIGN_16 },
965    { X86::VPMINUWrr,         X86::VPMINUWrm,          TB_ALIGN_16 },
966    { X86::VPMAXSBrr,         X86::VPMAXSBrm,          TB_ALIGN_16 },
967    { X86::VPMAXSDrr,         X86::VPMAXSDrm,          TB_ALIGN_16 },
968    { X86::VPMAXUDrr,         X86::VPMAXUDrm,          TB_ALIGN_16 },
969    { X86::VPMAXUWrr,         X86::VPMAXUWrm,          TB_ALIGN_16 },
970    { X86::VPMULDQrr,         X86::VPMULDQrm,          TB_ALIGN_16 },
971    { X86::VPMULHRSWrr128,    X86::VPMULHRSWrm128,     TB_ALIGN_16 },
972    { X86::VPMULHUWrr,        X86::VPMULHUWrm,         TB_ALIGN_16 },
973    { X86::VPMULHWrr,         X86::VPMULHWrm,          TB_ALIGN_16 },
974    { X86::VPMULLDrr,         X86::VPMULLDrm,          TB_ALIGN_16 },
975    { X86::VPMULLWrr,         X86::VPMULLWrm,          TB_ALIGN_16 },
976    { X86::VPMULUDQrr,        X86::VPMULUDQrm,         TB_ALIGN_16 },
977    { X86::VPORrr,            X86::VPORrm,             TB_ALIGN_16 },
978    { X86::VPSADBWrr,         X86::VPSADBWrm,          TB_ALIGN_16 },
979    { X86::VPSHUFBrr,         X86::VPSHUFBrm,          TB_ALIGN_16 },
980    { X86::VPSIGNBrr,         X86::VPSIGNBrm,          TB_ALIGN_16 },
981    { X86::VPSIGNWrr,         X86::VPSIGNWrm,          TB_ALIGN_16 },
982    { X86::VPSIGNDrr,         X86::VPSIGNDrm,          TB_ALIGN_16 },
983    { X86::VPSLLDrr,          X86::VPSLLDrm,           TB_ALIGN_16 },
984    { X86::VPSLLQrr,          X86::VPSLLQrm,           TB_ALIGN_16 },
985    { X86::VPSLLWrr,          X86::VPSLLWrm,           TB_ALIGN_16 },
986    { X86::VPSRADrr,          X86::VPSRADrm,           TB_ALIGN_16 },
987    { X86::VPSRAWrr,          X86::VPSRAWrm,           TB_ALIGN_16 },
988    { X86::VPSRLDrr,          X86::VPSRLDrm,           TB_ALIGN_16 },
989    { X86::VPSRLQrr,          X86::VPSRLQrm,           TB_ALIGN_16 },
990    { X86::VPSRLWrr,          X86::VPSRLWrm,           TB_ALIGN_16 },
991    { X86::VPSUBBrr,          X86::VPSUBBrm,           TB_ALIGN_16 },
992    { X86::VPSUBDrr,          X86::VPSUBDrm,           TB_ALIGN_16 },
993    { X86::VPSUBSBrr,         X86::VPSUBSBrm,          TB_ALIGN_16 },
994    { X86::VPSUBSWrr,         X86::VPSUBSWrm,          TB_ALIGN_16 },
995    { X86::VPSUBWrr,          X86::VPSUBWrm,           TB_ALIGN_16 },
996    { X86::VPUNPCKHBWrr,      X86::VPUNPCKHBWrm,       TB_ALIGN_16 },
997    { X86::VPUNPCKHDQrr,      X86::VPUNPCKHDQrm,       TB_ALIGN_16 },
998    { X86::VPUNPCKHQDQrr,     X86::VPUNPCKHQDQrm,      TB_ALIGN_16 },
999    { X86::VPUNPCKHWDrr,      X86::VPUNPCKHWDrm,       TB_ALIGN_16 },
1000    { X86::VPUNPCKLBWrr,      X86::VPUNPCKLBWrm,       TB_ALIGN_16 },
1001    { X86::VPUNPCKLDQrr,      X86::VPUNPCKLDQrm,       TB_ALIGN_16 },
1002    { X86::VPUNPCKLQDQrr,     X86::VPUNPCKLQDQrm,      TB_ALIGN_16 },
1003    { X86::VPUNPCKLWDrr,      X86::VPUNPCKLWDrm,       TB_ALIGN_16 },
1004    { X86::VPXORrr,           X86::VPXORrm,            TB_ALIGN_16 },
1005    { X86::VSHUFPDrri,        X86::VSHUFPDrmi,         TB_ALIGN_16 },
1006    { X86::VSHUFPSrri,        X86::VSHUFPSrmi,         TB_ALIGN_16 },
1007    { X86::VSUBPDrr,          X86::VSUBPDrm,           TB_ALIGN_16 },
1008    { X86::VSUBPSrr,          X86::VSUBPSrm,           TB_ALIGN_16 },
1009    { X86::VSUBSDrr,          X86::VSUBSDrm,           0 },
1010    { X86::VSUBSSrr,          X86::VSUBSSrm,           0 },
1011    { X86::VUNPCKHPDrr,       X86::VUNPCKHPDrm,        TB_ALIGN_16 },
1012    { X86::VUNPCKHPSrr,       X86::VUNPCKHPSrm,        TB_ALIGN_16 },
1013    { X86::VUNPCKLPDrr,       X86::VUNPCKLPDrm,        TB_ALIGN_16 },
1014    { X86::VUNPCKLPSrr,       X86::VUNPCKLPSrm,        TB_ALIGN_16 },
1015    { X86::VXORPDrr,          X86::VXORPDrm,           TB_ALIGN_16 },
1016    { X86::VXORPSrr,          X86::VXORPSrm,           TB_ALIGN_16 },
1017    // AVX 256-bit foldable instructions
1018    { X86::VADDPDYrr,         X86::VADDPDYrm,          TB_ALIGN_32 },
1019    { X86::VADDPSYrr,         X86::VADDPSYrm,          TB_ALIGN_32 },
1020    { X86::VADDSUBPDYrr,      X86::VADDSUBPDYrm,       TB_ALIGN_32 },
1021    { X86::VADDSUBPSYrr,      X86::VADDSUBPSYrm,       TB_ALIGN_32 },
1022    { X86::VANDNPDYrr,        X86::VANDNPDYrm,         TB_ALIGN_32 },
1023    { X86::VANDNPSYrr,        X86::VANDNPSYrm,         TB_ALIGN_32 },
1024    { X86::VANDPDYrr,         X86::VANDPDYrm,          TB_ALIGN_32 },
1025    { X86::VANDPSYrr,         X86::VANDPSYrm,          TB_ALIGN_32 },
1026    { X86::VBLENDPDYrri,      X86::VBLENDPDYrmi,       TB_ALIGN_32 },
1027    { X86::VBLENDPSYrri,      X86::VBLENDPSYrmi,       TB_ALIGN_32 },
1028    { X86::VBLENDVPDYrr,      X86::VBLENDVPDYrm,       TB_ALIGN_32 },
1029    { X86::VBLENDVPSYrr,      X86::VBLENDVPSYrm,       TB_ALIGN_32 },
1030    { X86::VCMPPDYrri,        X86::VCMPPDYrmi,         TB_ALIGN_32 },
1031    { X86::VCMPPSYrri,        X86::VCMPPSYrmi,         TB_ALIGN_32 },
1032    { X86::VDIVPDYrr,         X86::VDIVPDYrm,          TB_ALIGN_32 },
1033    { X86::VDIVPSYrr,         X86::VDIVPSYrm,          TB_ALIGN_32 },
1034    { X86::VHADDPDYrr,        X86::VHADDPDYrm,         TB_ALIGN_32 },
1035    { X86::VHADDPSYrr,        X86::VHADDPSYrm,         TB_ALIGN_32 },
1036    { X86::VHSUBPDYrr,        X86::VHSUBPDYrm,         TB_ALIGN_32 },
1037    { X86::VHSUBPSYrr,        X86::VHSUBPSYrm,         TB_ALIGN_32 },
1038    { X86::VINSERTF128rr,     X86::VINSERTF128rm,      TB_ALIGN_32 },
1039    { X86::VMAXPDYrr,         X86::VMAXPDYrm,          TB_ALIGN_32 },
1040    { X86::VMAXPDYrr_Int,     X86::VMAXPDYrm_Int,      TB_ALIGN_32 },
1041    { X86::VMAXPSYrr,         X86::VMAXPSYrm,          TB_ALIGN_32 },
1042    { X86::VMAXPSYrr_Int,     X86::VMAXPSYrm_Int,      TB_ALIGN_32 },
1043    { X86::VMINPDYrr,         X86::VMINPDYrm,          TB_ALIGN_32 },
1044    { X86::VMINPDYrr_Int,     X86::VMINPDYrm_Int,      TB_ALIGN_32 },
1045    { X86::VMINPSYrr,         X86::VMINPSYrm,          TB_ALIGN_32 },
1046    { X86::VMINPSYrr_Int,     X86::VMINPSYrm_Int,      TB_ALIGN_32 },
1047    { X86::VMULPDYrr,         X86::VMULPDYrm,          TB_ALIGN_32 },
1048    { X86::VMULPSYrr,         X86::VMULPSYrm,          TB_ALIGN_32 },
1049    { X86::VORPDYrr,          X86::VORPDYrm,           TB_ALIGN_32 },
1050    { X86::VORPSYrr,          X86::VORPSYrm,           TB_ALIGN_32 },
1051    { X86::VPERM2F128rr,      X86::VPERM2F128rm,       TB_ALIGN_32 },
1052    { X86::VPERMILPDYrr,      X86::VPERMILPDYrm,       TB_ALIGN_32 },
1053    { X86::VPERMILPSYrr,      X86::VPERMILPSYrm,       TB_ALIGN_32 },
1054    { X86::VSHUFPDYrri,       X86::VSHUFPDYrmi,        TB_ALIGN_32 },
1055    { X86::VSHUFPSYrri,       X86::VSHUFPSYrmi,        TB_ALIGN_32 },
1056    { X86::VSUBPDYrr,         X86::VSUBPDYrm,          TB_ALIGN_32 },
1057    { X86::VSUBPSYrr,         X86::VSUBPSYrm,          TB_ALIGN_32 },
1058    { X86::VUNPCKHPDYrr,      X86::VUNPCKHPDYrm,       TB_ALIGN_32 },
1059    { X86::VUNPCKHPSYrr,      X86::VUNPCKHPSYrm,       TB_ALIGN_32 },
1060    { X86::VUNPCKLPDYrr,      X86::VUNPCKLPDYrm,       TB_ALIGN_32 },
1061    { X86::VUNPCKLPSYrr,      X86::VUNPCKLPSYrm,       TB_ALIGN_32 },
1062    { X86::VXORPDYrr,         X86::VXORPDYrm,          TB_ALIGN_32 },
1063    { X86::VXORPSYrr,         X86::VXORPSYrm,          TB_ALIGN_32 },
1064    // AVX2 foldable instructions
1065    { X86::VINSERTI128rr,     X86::VINSERTI128rm,      TB_ALIGN_16 },
1066    { X86::VPACKSSDWYrr,      X86::VPACKSSDWYrm,       TB_ALIGN_32 },
1067    { X86::VPACKSSWBYrr,      X86::VPACKSSWBYrm,       TB_ALIGN_32 },
1068    { X86::VPACKUSDWYrr,      X86::VPACKUSDWYrm,       TB_ALIGN_32 },
1069    { X86::VPACKUSWBYrr,      X86::VPACKUSWBYrm,       TB_ALIGN_32 },
1070    { X86::VPADDBYrr,         X86::VPADDBYrm,          TB_ALIGN_32 },
1071    { X86::VPADDDYrr,         X86::VPADDDYrm,          TB_ALIGN_32 },
1072    { X86::VPADDQYrr,         X86::VPADDQYrm,          TB_ALIGN_32 },
1073    { X86::VPADDSBYrr,        X86::VPADDSBYrm,         TB_ALIGN_32 },
1074    { X86::VPADDSWYrr,        X86::VPADDSWYrm,         TB_ALIGN_32 },
1075    { X86::VPADDUSBYrr,       X86::VPADDUSBYrm,        TB_ALIGN_32 },
1076    { X86::VPADDUSWYrr,       X86::VPADDUSWYrm,        TB_ALIGN_32 },
1077    { X86::VPADDWYrr,         X86::VPADDWYrm,          TB_ALIGN_32 },
1078    { X86::VPALIGNR256rr,     X86::VPALIGNR256rm,      TB_ALIGN_32 },
1079    { X86::VPANDNYrr,         X86::VPANDNYrm,          TB_ALIGN_32 },
1080    { X86::VPANDYrr,          X86::VPANDYrm,           TB_ALIGN_32 },
1081    { X86::VPAVGBYrr,         X86::VPAVGBYrm,          TB_ALIGN_32 },
1082    { X86::VPAVGWYrr,         X86::VPAVGWYrm,          TB_ALIGN_32 },
1083    { X86::VPBLENDDrri,       X86::VPBLENDDrmi,        TB_ALIGN_32 },
1084    { X86::VPBLENDDYrri,      X86::VPBLENDDYrmi,       TB_ALIGN_32 },
1085    { X86::VPBLENDWYrri,      X86::VPBLENDWYrmi,       TB_ALIGN_32 },
1086    { X86::VPCMPEQBYrr,       X86::VPCMPEQBYrm,        TB_ALIGN_32 },
1087    { X86::VPCMPEQDYrr,       X86::VPCMPEQDYrm,        TB_ALIGN_32 },
1088    { X86::VPCMPEQQYrr,       X86::VPCMPEQQYrm,        TB_ALIGN_32 },
1089    { X86::VPCMPEQWYrr,       X86::VPCMPEQWYrm,        TB_ALIGN_32 },
1090    { X86::VPCMPGTBYrr,       X86::VPCMPGTBYrm,        TB_ALIGN_32 },
1091    { X86::VPCMPGTDYrr,       X86::VPCMPGTDYrm,        TB_ALIGN_32 },
1092    { X86::VPCMPGTQYrr,       X86::VPCMPGTQYrm,        TB_ALIGN_32 },
1093    { X86::VPCMPGTWYrr,       X86::VPCMPGTWYrm,        TB_ALIGN_32 },
1094    { X86::VPERM2I128rr,      X86::VPERM2I128rm,       TB_ALIGN_32 },
1095    { X86::VPERMDYrr,         X86::VPERMDYrm,          TB_ALIGN_32 },
1096    { X86::VPERMPDYri,        X86::VPERMPDYmi,         TB_ALIGN_32 },
1097    { X86::VPERMPSYrr,        X86::VPERMPSYrm,         TB_ALIGN_32 },
1098    { X86::VPERMQYri,         X86::VPERMQYmi,          TB_ALIGN_32 },
1099    { X86::VPHADDDYrr,        X86::VPHADDDYrm,         TB_ALIGN_32 },
1100    { X86::VPHADDSWrr256,     X86::VPHADDSWrm256,      TB_ALIGN_32 },
1101    { X86::VPHADDWYrr,        X86::VPHADDWYrm,         TB_ALIGN_32 },
1102    { X86::VPHSUBDYrr,        X86::VPHSUBDYrm,         TB_ALIGN_32 },
1103    { X86::VPHSUBSWrr256,     X86::VPHSUBSWrm256,      TB_ALIGN_32 },
1104    { X86::VPHSUBWYrr,        X86::VPHSUBWYrm,         TB_ALIGN_32 },
1105    { X86::VPMADDUBSWrr256,   X86::VPMADDUBSWrm256,    TB_ALIGN_32 },
1106    { X86::VPMADDWDYrr,       X86::VPMADDWDYrm,        TB_ALIGN_32 },
1107    { X86::VPMAXSWYrr,        X86::VPMAXSWYrm,         TB_ALIGN_32 },
1108    { X86::VPMAXUBYrr,        X86::VPMAXUBYrm,         TB_ALIGN_32 },
1109    { X86::VPMINSWYrr,        X86::VPMINSWYrm,         TB_ALIGN_32 },
1110    { X86::VPMINUBYrr,        X86::VPMINUBYrm,         TB_ALIGN_32 },
1111    { X86::VPMINSBYrr,        X86::VPMINSBYrm,         TB_ALIGN_32 },
1112    { X86::VPMINSDYrr,        X86::VPMINSDYrm,         TB_ALIGN_32 },
1113    { X86::VPMINUDYrr,        X86::VPMINUDYrm,         TB_ALIGN_32 },
1114    { X86::VPMINUWYrr,        X86::VPMINUWYrm,         TB_ALIGN_32 },
1115    { X86::VPMAXSBYrr,        X86::VPMAXSBYrm,         TB_ALIGN_32 },
1116    { X86::VPMAXSDYrr,        X86::VPMAXSDYrm,         TB_ALIGN_32 },
1117    { X86::VPMAXUDYrr,        X86::VPMAXUDYrm,         TB_ALIGN_32 },
1118    { X86::VPMAXUWYrr,        X86::VPMAXUWYrm,         TB_ALIGN_32 },
1119    { X86::VMPSADBWYrri,      X86::VMPSADBWYrmi,       TB_ALIGN_32 },
1120    { X86::VPMULDQYrr,        X86::VPMULDQYrm,         TB_ALIGN_32 },
1121    { X86::VPMULHRSWrr256,    X86::VPMULHRSWrm256,     TB_ALIGN_32 },
1122    { X86::VPMULHUWYrr,       X86::VPMULHUWYrm,        TB_ALIGN_32 },
1123    { X86::VPMULHWYrr,        X86::VPMULHWYrm,         TB_ALIGN_32 },
1124    { X86::VPMULLDYrr,        X86::VPMULLDYrm,         TB_ALIGN_32 },
1125    { X86::VPMULLWYrr,        X86::VPMULLWYrm,         TB_ALIGN_32 },
1126    { X86::VPMULUDQYrr,       X86::VPMULUDQYrm,        TB_ALIGN_32 },
1127    { X86::VPORYrr,           X86::VPORYrm,            TB_ALIGN_32 },
1128    { X86::VPSADBWYrr,        X86::VPSADBWYrm,         TB_ALIGN_32 },
1129    { X86::VPSHUFBYrr,        X86::VPSHUFBYrm,         TB_ALIGN_32 },
1130    { X86::VPSIGNBYrr,        X86::VPSIGNBYrm,         TB_ALIGN_32 },
1131    { X86::VPSIGNWYrr,        X86::VPSIGNWYrm,         TB_ALIGN_32 },
1132    { X86::VPSIGNDYrr,        X86::VPSIGNDYrm,         TB_ALIGN_32 },
1133    { X86::VPSLLDYrr,         X86::VPSLLDYrm,          TB_ALIGN_16 },
1134    { X86::VPSLLQYrr,         X86::VPSLLQYrm,          TB_ALIGN_16 },
1135    { X86::VPSLLWYrr,         X86::VPSLLWYrm,          TB_ALIGN_16 },
1136    { X86::VPSLLVDrr,         X86::VPSLLVDrm,          TB_ALIGN_16 },
1137    { X86::VPSLLVDYrr,        X86::VPSLLVDYrm,         TB_ALIGN_32 },
1138    { X86::VPSLLVQrr,         X86::VPSLLVQrm,          TB_ALIGN_16 },
1139    { X86::VPSLLVQYrr,        X86::VPSLLVQYrm,         TB_ALIGN_32 },
1140    { X86::VPSRADYrr,         X86::VPSRADYrm,          TB_ALIGN_16 },
1141    { X86::VPSRAWYrr,         X86::VPSRAWYrm,          TB_ALIGN_16 },
1142    { X86::VPSRAVDrr,         X86::VPSRAVDrm,          TB_ALIGN_16 },
1143    { X86::VPSRAVDYrr,        X86::VPSRAVDYrm,         TB_ALIGN_32 },
1144    { X86::VPSRLDYrr,         X86::VPSRLDYrm,          TB_ALIGN_16 },
1145    { X86::VPSRLQYrr,         X86::VPSRLQYrm,          TB_ALIGN_16 },
1146    { X86::VPSRLWYrr,         X86::VPSRLWYrm,          TB_ALIGN_16 },
1147    { X86::VPSRLVDrr,         X86::VPSRLVDrm,          TB_ALIGN_16 },
1148    { X86::VPSRLVDYrr,        X86::VPSRLVDYrm,         TB_ALIGN_32 },
1149    { X86::VPSRLVQrr,         X86::VPSRLVQrm,          TB_ALIGN_16 },
1150    { X86::VPSRLVQYrr,        X86::VPSRLVQYrm,         TB_ALIGN_32 },
1151    { X86::VPSUBBYrr,         X86::VPSUBBYrm,          TB_ALIGN_32 },
1152    { X86::VPSUBDYrr,         X86::VPSUBDYrm,          TB_ALIGN_32 },
1153    { X86::VPSUBSBYrr,        X86::VPSUBSBYrm,         TB_ALIGN_32 },
1154    { X86::VPSUBSWYrr,        X86::VPSUBSWYrm,         TB_ALIGN_32 },
1155    { X86::VPSUBWYrr,         X86::VPSUBWYrm,          TB_ALIGN_32 },
1156    { X86::VPUNPCKHBWYrr,     X86::VPUNPCKHBWYrm,      TB_ALIGN_32 },
1157    { X86::VPUNPCKHDQYrr,     X86::VPUNPCKHDQYrm,      TB_ALIGN_32 },
1158    { X86::VPUNPCKHQDQYrr,    X86::VPUNPCKHQDQYrm,     TB_ALIGN_16 },
1159    { X86::VPUNPCKHWDYrr,     X86::VPUNPCKHWDYrm,      TB_ALIGN_32 },
1160    { X86::VPUNPCKLBWYrr,     X86::VPUNPCKLBWYrm,      TB_ALIGN_32 },
1161    { X86::VPUNPCKLDQYrr,     X86::VPUNPCKLDQYrm,      TB_ALIGN_32 },
1162    { X86::VPUNPCKLQDQYrr,    X86::VPUNPCKLQDQYrm,     TB_ALIGN_32 },
1163    { X86::VPUNPCKLWDYrr,     X86::VPUNPCKLWDYrm,      TB_ALIGN_32 },
1164    { X86::VPXORYrr,          X86::VPXORYrm,           TB_ALIGN_32 },
1165    // FIXME: add AVX 256-bit foldable instructions
1166
1167    // FMA4 foldable patterns
1168    { X86::VFMADDSS4rr,       X86::VFMADDSS4mr,        0           },
1169    { X86::VFMADDSD4rr,       X86::VFMADDSD4mr,        0           },
1170    { X86::VFMADDPS4rr,       X86::VFMADDPS4mr,        TB_ALIGN_16 },
1171    { X86::VFMADDPD4rr,       X86::VFMADDPD4mr,        TB_ALIGN_16 },
1172    { X86::VFMADDPS4rrY,      X86::VFMADDPS4mrY,       TB_ALIGN_32 },
1173    { X86::VFMADDPD4rrY,      X86::VFMADDPD4mrY,       TB_ALIGN_32 },
1174    { X86::VFNMADDSS4rr,      X86::VFNMADDSS4mr,       0           },
1175    { X86::VFNMADDSD4rr,      X86::VFNMADDSD4mr,       0           },
1176    { X86::VFNMADDPS4rr,      X86::VFNMADDPS4mr,       TB_ALIGN_16 },
1177    { X86::VFNMADDPD4rr,      X86::VFNMADDPD4mr,       TB_ALIGN_16 },
1178    { X86::VFNMADDPS4rrY,     X86::VFNMADDPS4mrY,      TB_ALIGN_32 },
1179    { X86::VFNMADDPD4rrY,     X86::VFNMADDPD4mrY,      TB_ALIGN_32 },
1180    { X86::VFMSUBSS4rr,       X86::VFMSUBSS4mr,        0           },
1181    { X86::VFMSUBSD4rr,       X86::VFMSUBSD4mr,        0           },
1182    { X86::VFMSUBPS4rr,       X86::VFMSUBPS4mr,        TB_ALIGN_16 },
1183    { X86::VFMSUBPD4rr,       X86::VFMSUBPD4mr,        TB_ALIGN_16 },
1184    { X86::VFMSUBPS4rrY,      X86::VFMSUBPS4mrY,       TB_ALIGN_32 },
1185    { X86::VFMSUBPD4rrY,      X86::VFMSUBPD4mrY,       TB_ALIGN_32 },
1186    { X86::VFNMSUBSS4rr,      X86::VFNMSUBSS4mr,       0           },
1187    { X86::VFNMSUBSD4rr,      X86::VFNMSUBSD4mr,       0           },
1188    { X86::VFNMSUBPS4rr,      X86::VFNMSUBPS4mr,       TB_ALIGN_16 },
1189    { X86::VFNMSUBPD4rr,      X86::VFNMSUBPD4mr,       TB_ALIGN_16 },
1190    { X86::VFNMSUBPS4rrY,     X86::VFNMSUBPS4mrY,      TB_ALIGN_32 },
1191    { X86::VFNMSUBPD4rrY,     X86::VFNMSUBPD4mrY,      TB_ALIGN_32 },
1192    { X86::VFMADDSUBPS4rr,    X86::VFMADDSUBPS4mr,     TB_ALIGN_16 },
1193    { X86::VFMADDSUBPD4rr,    X86::VFMADDSUBPD4mr,     TB_ALIGN_16 },
1194    { X86::VFMADDSUBPS4rrY,   X86::VFMADDSUBPS4mrY,    TB_ALIGN_32 },
1195    { X86::VFMADDSUBPD4rrY,   X86::VFMADDSUBPD4mrY,    TB_ALIGN_32 },
1196    { X86::VFMSUBADDPS4rr,    X86::VFMSUBADDPS4mr,     TB_ALIGN_16 },
1197    { X86::VFMSUBADDPD4rr,    X86::VFMSUBADDPD4mr,     TB_ALIGN_16 },
1198    { X86::VFMSUBADDPS4rrY,   X86::VFMSUBADDPS4mrY,    TB_ALIGN_32 },
1199    { X86::VFMSUBADDPD4rrY,   X86::VFMSUBADDPD4mrY,    TB_ALIGN_32 },
1200
1201    // BMI/BMI2 foldable instructions
1202    { X86::ANDN32rr,          X86::ANDN32rm,            0 },
1203    { X86::ANDN64rr,          X86::ANDN64rm,            0 },
1204    { X86::MULX32rr,          X86::MULX32rm,            0 },
1205    { X86::MULX64rr,          X86::MULX64rm,            0 },
1206    { X86::PDEP32rr,          X86::PDEP32rm,            0 },
1207    { X86::PDEP64rr,          X86::PDEP64rm,            0 },
1208    { X86::PEXT32rr,          X86::PEXT32rm,            0 },
1209    { X86::PEXT64rr,          X86::PEXT64rm,            0 },
1210  };
1211
1212  for (unsigned i = 0, e = array_lengthof(OpTbl2); i != e; ++i) {
1213    unsigned RegOp = OpTbl2[i].RegOp;
1214    unsigned MemOp = OpTbl2[i].MemOp;
1215    unsigned Flags = OpTbl2[i].Flags;
1216    AddTableEntry(RegOp2MemOpTable2, MemOp2RegOpTable,
1217                  RegOp, MemOp,
1218                  // Index 2, folded load
1219                  Flags | TB_INDEX_2 | TB_FOLDED_LOAD);
1220  }
1221
1222  static const X86OpTblEntry OpTbl3[] = {
1223    // FMA foldable instructions
1224    { X86::VFMADDSSr231r,         X86::VFMADDSSr231m,         0 },
1225    { X86::VFMADDSDr231r,         X86::VFMADDSDr231m,         0 },
1226    { X86::VFMADDSSr132r,         X86::VFMADDSSr132m,         0 },
1227    { X86::VFMADDSDr132r,         X86::VFMADDSDr132m,         0 },
1228    { X86::VFMADDSSr213r,         X86::VFMADDSSr213m,         0 },
1229    { X86::VFMADDSDr213r,         X86::VFMADDSDr213m,         0 },
1230    { X86::VFMADDSSr213r_Int,     X86::VFMADDSSr213m_Int,     0 },
1231    { X86::VFMADDSDr213r_Int,     X86::VFMADDSDr213m_Int,     0 },
1232
1233    { X86::VFMADDPSr231r,         X86::VFMADDPSr231m,         TB_ALIGN_16 },
1234    { X86::VFMADDPDr231r,         X86::VFMADDPDr231m,         TB_ALIGN_16 },
1235    { X86::VFMADDPSr132r,         X86::VFMADDPSr132m,         TB_ALIGN_16 },
1236    { X86::VFMADDPDr132r,         X86::VFMADDPDr132m,         TB_ALIGN_16 },
1237    { X86::VFMADDPSr213r,         X86::VFMADDPSr213m,         TB_ALIGN_16 },
1238    { X86::VFMADDPDr213r,         X86::VFMADDPDr213m,         TB_ALIGN_16 },
1239    { X86::VFMADDPSr231rY,        X86::VFMADDPSr231mY,        TB_ALIGN_32 },
1240    { X86::VFMADDPDr231rY,        X86::VFMADDPDr231mY,        TB_ALIGN_32 },
1241    { X86::VFMADDPSr132rY,        X86::VFMADDPSr132mY,        TB_ALIGN_32 },
1242    { X86::VFMADDPDr132rY,        X86::VFMADDPDr132mY,        TB_ALIGN_32 },
1243    { X86::VFMADDPSr213rY,        X86::VFMADDPSr213mY,        TB_ALIGN_32 },
1244    { X86::VFMADDPDr213rY,        X86::VFMADDPDr213mY,        TB_ALIGN_32 },
1245
1246    { X86::VFNMADDSSr231r,        X86::VFNMADDSSr231m,        0 },
1247    { X86::VFNMADDSDr231r,        X86::VFNMADDSDr231m,        0 },
1248    { X86::VFNMADDSSr132r,        X86::VFNMADDSSr132m,        0 },
1249    { X86::VFNMADDSDr132r,        X86::VFNMADDSDr132m,        0 },
1250    { X86::VFNMADDSSr213r,        X86::VFNMADDSSr213m,        0 },
1251    { X86::VFNMADDSDr213r,        X86::VFNMADDSDr213m,        0 },
1252    { X86::VFNMADDSSr213r_Int,    X86::VFNMADDSSr213m_Int,    0 },
1253    { X86::VFNMADDSDr213r_Int,    X86::VFNMADDSDr213m_Int,    0 },
1254
1255    { X86::VFNMADDPSr231r,        X86::VFNMADDPSr231m,        TB_ALIGN_16 },
1256    { X86::VFNMADDPDr231r,        X86::VFNMADDPDr231m,        TB_ALIGN_16 },
1257    { X86::VFNMADDPSr132r,        X86::VFNMADDPSr132m,        TB_ALIGN_16 },
1258    { X86::VFNMADDPDr132r,        X86::VFNMADDPDr132m,        TB_ALIGN_16 },
1259    { X86::VFNMADDPSr213r,        X86::VFNMADDPSr213m,        TB_ALIGN_16 },
1260    { X86::VFNMADDPDr213r,        X86::VFNMADDPDr213m,        TB_ALIGN_16 },
1261    { X86::VFNMADDPSr231rY,       X86::VFNMADDPSr231mY,       TB_ALIGN_32 },
1262    { X86::VFNMADDPDr231rY,       X86::VFNMADDPDr231mY,       TB_ALIGN_32 },
1263    { X86::VFNMADDPSr132rY,       X86::VFNMADDPSr132mY,       TB_ALIGN_32 },
1264    { X86::VFNMADDPDr132rY,       X86::VFNMADDPDr132mY,       TB_ALIGN_32 },
1265    { X86::VFNMADDPSr213rY,       X86::VFNMADDPSr213mY,       TB_ALIGN_32 },
1266    { X86::VFNMADDPDr213rY,       X86::VFNMADDPDr213mY,       TB_ALIGN_32 },
1267
1268    { X86::VFMSUBSSr231r,         X86::VFMSUBSSr231m,         0 },
1269    { X86::VFMSUBSDr231r,         X86::VFMSUBSDr231m,         0 },
1270    { X86::VFMSUBSSr132r,         X86::VFMSUBSSr132m,         0 },
1271    { X86::VFMSUBSDr132r,         X86::VFMSUBSDr132m,         0 },
1272    { X86::VFMSUBSSr213r,         X86::VFMSUBSSr213m,         0 },
1273    { X86::VFMSUBSDr213r,         X86::VFMSUBSDr213m,         0 },
1274    { X86::VFMSUBSSr213r_Int,     X86::VFMSUBSSr213m_Int,     0 },
1275    { X86::VFMSUBSDr213r_Int,     X86::VFMSUBSDr213m_Int,     0 },
1276
1277    { X86::VFMSUBPSr231r,         X86::VFMSUBPSr231m,         TB_ALIGN_16 },
1278    { X86::VFMSUBPDr231r,         X86::VFMSUBPDr231m,         TB_ALIGN_16 },
1279    { X86::VFMSUBPSr132r,         X86::VFMSUBPSr132m,         TB_ALIGN_16 },
1280    { X86::VFMSUBPDr132r,         X86::VFMSUBPDr132m,         TB_ALIGN_16 },
1281    { X86::VFMSUBPSr213r,         X86::VFMSUBPSr213m,         TB_ALIGN_16 },
1282    { X86::VFMSUBPDr213r,         X86::VFMSUBPDr213m,         TB_ALIGN_16 },
1283    { X86::VFMSUBPSr231rY,        X86::VFMSUBPSr231mY,        TB_ALIGN_32 },
1284    { X86::VFMSUBPDr231rY,        X86::VFMSUBPDr231mY,        TB_ALIGN_32 },
1285    { X86::VFMSUBPSr132rY,        X86::VFMSUBPSr132mY,        TB_ALIGN_32 },
1286    { X86::VFMSUBPDr132rY,        X86::VFMSUBPDr132mY,        TB_ALIGN_32 },
1287    { X86::VFMSUBPSr213rY,        X86::VFMSUBPSr213mY,        TB_ALIGN_32 },
1288    { X86::VFMSUBPDr213rY,        X86::VFMSUBPDr213mY,        TB_ALIGN_32 },
1289
1290    { X86::VFNMSUBSSr231r,        X86::VFNMSUBSSr231m,        0 },
1291    { X86::VFNMSUBSDr231r,        X86::VFNMSUBSDr231m,        0 },
1292    { X86::VFNMSUBSSr132r,        X86::VFNMSUBSSr132m,        0 },
1293    { X86::VFNMSUBSDr132r,        X86::VFNMSUBSDr132m,        0 },
1294    { X86::VFNMSUBSSr213r,        X86::VFNMSUBSSr213m,        0 },
1295    { X86::VFNMSUBSDr213r,        X86::VFNMSUBSDr213m,        0 },
1296    { X86::VFNMSUBSSr213r_Int,    X86::VFNMSUBSSr213m_Int,    0 },
1297    { X86::VFNMSUBSDr213r_Int,    X86::VFNMSUBSDr213m_Int,    0 },
1298
1299    { X86::VFNMSUBPSr231r,        X86::VFNMSUBPSr231m,        TB_ALIGN_16 },
1300    { X86::VFNMSUBPDr231r,        X86::VFNMSUBPDr231m,        TB_ALIGN_16 },
1301    { X86::VFNMSUBPSr132r,        X86::VFNMSUBPSr132m,        TB_ALIGN_16 },
1302    { X86::VFNMSUBPDr132r,        X86::VFNMSUBPDr132m,        TB_ALIGN_16 },
1303    { X86::VFNMSUBPSr213r,        X86::VFNMSUBPSr213m,        TB_ALIGN_16 },
1304    { X86::VFNMSUBPDr213r,        X86::VFNMSUBPDr213m,        TB_ALIGN_16 },
1305    { X86::VFNMSUBPSr231rY,       X86::VFNMSUBPSr231mY,       TB_ALIGN_32 },
1306    { X86::VFNMSUBPDr231rY,       X86::VFNMSUBPDr231mY,       TB_ALIGN_32 },
1307    { X86::VFNMSUBPSr132rY,       X86::VFNMSUBPSr132mY,       TB_ALIGN_32 },
1308    { X86::VFNMSUBPDr132rY,       X86::VFNMSUBPDr132mY,       TB_ALIGN_32 },
1309    { X86::VFNMSUBPSr213rY,       X86::VFNMSUBPSr213mY,       TB_ALIGN_32 },
1310    { X86::VFNMSUBPDr213rY,       X86::VFNMSUBPDr213mY,       TB_ALIGN_32 },
1311
1312    { X86::VFMADDSUBPSr231r,      X86::VFMADDSUBPSr231m,      TB_ALIGN_16 },
1313    { X86::VFMADDSUBPDr231r,      X86::VFMADDSUBPDr231m,      TB_ALIGN_16 },
1314    { X86::VFMADDSUBPSr132r,      X86::VFMADDSUBPSr132m,      TB_ALIGN_16 },
1315    { X86::VFMADDSUBPDr132r,      X86::VFMADDSUBPDr132m,      TB_ALIGN_16 },
1316    { X86::VFMADDSUBPSr213r,      X86::VFMADDSUBPSr213m,      TB_ALIGN_16 },
1317    { X86::VFMADDSUBPDr213r,      X86::VFMADDSUBPDr213m,      TB_ALIGN_16 },
1318    { X86::VFMADDSUBPSr231rY,     X86::VFMADDSUBPSr231mY,     TB_ALIGN_32 },
1319    { X86::VFMADDSUBPDr231rY,     X86::VFMADDSUBPDr231mY,     TB_ALIGN_32 },
1320    { X86::VFMADDSUBPSr132rY,     X86::VFMADDSUBPSr132mY,     TB_ALIGN_32 },
1321    { X86::VFMADDSUBPDr132rY,     X86::VFMADDSUBPDr132mY,     TB_ALIGN_32 },
1322    { X86::VFMADDSUBPSr213rY,     X86::VFMADDSUBPSr213mY,     TB_ALIGN_32 },
1323    { X86::VFMADDSUBPDr213rY,     X86::VFMADDSUBPDr213mY,     TB_ALIGN_32 },
1324
1325    { X86::VFMSUBADDPSr231r,      X86::VFMSUBADDPSr231m,      TB_ALIGN_16 },
1326    { X86::VFMSUBADDPDr231r,      X86::VFMSUBADDPDr231m,      TB_ALIGN_16 },
1327    { X86::VFMSUBADDPSr132r,      X86::VFMSUBADDPSr132m,      TB_ALIGN_16 },
1328    { X86::VFMSUBADDPDr132r,      X86::VFMSUBADDPDr132m,      TB_ALIGN_16 },
1329    { X86::VFMSUBADDPSr213r,      X86::VFMSUBADDPSr213m,      TB_ALIGN_16 },
1330    { X86::VFMSUBADDPDr213r,      X86::VFMSUBADDPDr213m,      TB_ALIGN_16 },
1331    { X86::VFMSUBADDPSr231rY,     X86::VFMSUBADDPSr231mY,     TB_ALIGN_32 },
1332    { X86::VFMSUBADDPDr231rY,     X86::VFMSUBADDPDr231mY,     TB_ALIGN_32 },
1333    { X86::VFMSUBADDPSr132rY,     X86::VFMSUBADDPSr132mY,     TB_ALIGN_32 },
1334    { X86::VFMSUBADDPDr132rY,     X86::VFMSUBADDPDr132mY,     TB_ALIGN_32 },
1335    { X86::VFMSUBADDPSr213rY,     X86::VFMSUBADDPSr213mY,     TB_ALIGN_32 },
1336    { X86::VFMSUBADDPDr213rY,     X86::VFMSUBADDPDr213mY,     TB_ALIGN_32 },
1337
1338    // FMA4 foldable patterns
1339    { X86::VFMADDSS4rr,           X86::VFMADDSS4rm,           0           },
1340    { X86::VFMADDSD4rr,           X86::VFMADDSD4rm,           0           },
1341    { X86::VFMADDPS4rr,           X86::VFMADDPS4rm,           TB_ALIGN_16 },
1342    { X86::VFMADDPD4rr,           X86::VFMADDPD4rm,           TB_ALIGN_16 },
1343    { X86::VFMADDPS4rrY,          X86::VFMADDPS4rmY,          TB_ALIGN_32 },
1344    { X86::VFMADDPD4rrY,          X86::VFMADDPD4rmY,          TB_ALIGN_32 },
1345    { X86::VFNMADDSS4rr,          X86::VFNMADDSS4rm,          0           },
1346    { X86::VFNMADDSD4rr,          X86::VFNMADDSD4rm,          0           },
1347    { X86::VFNMADDPS4rr,          X86::VFNMADDPS4rm,          TB_ALIGN_16 },
1348    { X86::VFNMADDPD4rr,          X86::VFNMADDPD4rm,          TB_ALIGN_16 },
1349    { X86::VFNMADDPS4rrY,         X86::VFNMADDPS4rmY,         TB_ALIGN_32 },
1350    { X86::VFNMADDPD4rrY,         X86::VFNMADDPD4rmY,         TB_ALIGN_32 },
1351    { X86::VFMSUBSS4rr,           X86::VFMSUBSS4rm,           0           },
1352    { X86::VFMSUBSD4rr,           X86::VFMSUBSD4rm,           0           },
1353    { X86::VFMSUBPS4rr,           X86::VFMSUBPS4rm,           TB_ALIGN_16 },
1354    { X86::VFMSUBPD4rr,           X86::VFMSUBPD4rm,           TB_ALIGN_16 },
1355    { X86::VFMSUBPS4rrY,          X86::VFMSUBPS4rmY,          TB_ALIGN_32 },
1356    { X86::VFMSUBPD4rrY,          X86::VFMSUBPD4rmY,          TB_ALIGN_32 },
1357    { X86::VFNMSUBSS4rr,          X86::VFNMSUBSS4rm,          0           },
1358    { X86::VFNMSUBSD4rr,          X86::VFNMSUBSD4rm,          0           },
1359    { X86::VFNMSUBPS4rr,          X86::VFNMSUBPS4rm,          TB_ALIGN_16 },
1360    { X86::VFNMSUBPD4rr,          X86::VFNMSUBPD4rm,          TB_ALIGN_16 },
1361    { X86::VFNMSUBPS4rrY,         X86::VFNMSUBPS4rmY,         TB_ALIGN_32 },
1362    { X86::VFNMSUBPD4rrY,         X86::VFNMSUBPD4rmY,         TB_ALIGN_32 },
1363    { X86::VFMADDSUBPS4rr,        X86::VFMADDSUBPS4rm,        TB_ALIGN_16 },
1364    { X86::VFMADDSUBPD4rr,        X86::VFMADDSUBPD4rm,        TB_ALIGN_16 },
1365    { X86::VFMADDSUBPS4rrY,       X86::VFMADDSUBPS4rmY,       TB_ALIGN_32 },
1366    { X86::VFMADDSUBPD4rrY,       X86::VFMADDSUBPD4rmY,       TB_ALIGN_32 },
1367    { X86::VFMSUBADDPS4rr,        X86::VFMSUBADDPS4rm,        TB_ALIGN_16 },
1368    { X86::VFMSUBADDPD4rr,        X86::VFMSUBADDPD4rm,        TB_ALIGN_16 },
1369    { X86::VFMSUBADDPS4rrY,       X86::VFMSUBADDPS4rmY,       TB_ALIGN_32 },
1370    { X86::VFMSUBADDPD4rrY,       X86::VFMSUBADDPD4rmY,       TB_ALIGN_32 },
1371  };
1372
1373  for (unsigned i = 0, e = array_lengthof(OpTbl3); i != e; ++i) {
1374    unsigned RegOp = OpTbl3[i].RegOp;
1375    unsigned MemOp = OpTbl3[i].MemOp;
1376    unsigned Flags = OpTbl3[i].Flags;
1377    AddTableEntry(RegOp2MemOpTable3, MemOp2RegOpTable,
1378                  RegOp, MemOp,
1379                  // Index 3, folded load
1380                  Flags | TB_INDEX_3 | TB_FOLDED_LOAD);
1381  }
1382
1383}
1384
1385void
1386X86InstrInfo::AddTableEntry(RegOp2MemOpTableType &R2MTable,
1387                            MemOp2RegOpTableType &M2RTable,
1388                            unsigned RegOp, unsigned MemOp, unsigned Flags) {
1389    if ((Flags & TB_NO_FORWARD) == 0) {
1390      assert(!R2MTable.count(RegOp) && "Duplicate entry!");
1391      R2MTable[RegOp] = std::make_pair(MemOp, Flags);
1392    }
1393    if ((Flags & TB_NO_REVERSE) == 0) {
1394      assert(!M2RTable.count(MemOp) &&
1395           "Duplicated entries in unfolding maps?");
1396      M2RTable[MemOp] = std::make_pair(RegOp, Flags);
1397    }
1398}
1399
1400bool
1401X86InstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
1402                                    unsigned &SrcReg, unsigned &DstReg,
1403                                    unsigned &SubIdx) const {
1404  switch (MI.getOpcode()) {
1405  default: break;
1406  case X86::MOVSX16rr8:
1407  case X86::MOVZX16rr8:
1408  case X86::MOVSX32rr8:
1409  case X86::MOVZX32rr8:
1410  case X86::MOVSX64rr8:
1411  case X86::MOVZX64rr8:
1412    if (!TM.getSubtarget<X86Subtarget>().is64Bit())
1413      // It's not always legal to reference the low 8-bit of the larger
1414      // register in 32-bit mode.
1415      return false;
1416  case X86::MOVSX32rr16:
1417  case X86::MOVZX32rr16:
1418  case X86::MOVSX64rr16:
1419  case X86::MOVZX64rr16:
1420  case X86::MOVSX64rr32:
1421  case X86::MOVZX64rr32: {
1422    if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg())
1423      // Be conservative.
1424      return false;
1425    SrcReg = MI.getOperand(1).getReg();
1426    DstReg = MI.getOperand(0).getReg();
1427    switch (MI.getOpcode()) {
1428    default: llvm_unreachable("Unreachable!");
1429    case X86::MOVSX16rr8:
1430    case X86::MOVZX16rr8:
1431    case X86::MOVSX32rr8:
1432    case X86::MOVZX32rr8:
1433    case X86::MOVSX64rr8:
1434    case X86::MOVZX64rr8:
1435      SubIdx = X86::sub_8bit;
1436      break;
1437    case X86::MOVSX32rr16:
1438    case X86::MOVZX32rr16:
1439    case X86::MOVSX64rr16:
1440    case X86::MOVZX64rr16:
1441      SubIdx = X86::sub_16bit;
1442      break;
1443    case X86::MOVSX64rr32:
1444    case X86::MOVZX64rr32:
1445      SubIdx = X86::sub_32bit;
1446      break;
1447    }
1448    return true;
1449  }
1450  }
1451  return false;
1452}
1453
1454/// isFrameOperand - Return true and the FrameIndex if the specified
1455/// operand and follow operands form a reference to the stack frame.
1456bool X86InstrInfo::isFrameOperand(const MachineInstr *MI, unsigned int Op,
1457                                  int &FrameIndex) const {
1458  if (MI->getOperand(Op).isFI() && MI->getOperand(Op+1).isImm() &&
1459      MI->getOperand(Op+2).isReg() && MI->getOperand(Op+3).isImm() &&
1460      MI->getOperand(Op+1).getImm() == 1 &&
1461      MI->getOperand(Op+2).getReg() == 0 &&
1462      MI->getOperand(Op+3).getImm() == 0) {
1463    FrameIndex = MI->getOperand(Op).getIndex();
1464    return true;
1465  }
1466  return false;
1467}
1468
1469static bool isFrameLoadOpcode(int Opcode) {
1470  switch (Opcode) {
1471  default:
1472    return false;
1473  case X86::MOV8rm:
1474  case X86::MOV16rm:
1475  case X86::MOV32rm:
1476  case X86::MOV64rm:
1477  case X86::LD_Fp64m:
1478  case X86::MOVSSrm:
1479  case X86::MOVSDrm:
1480  case X86::MOVAPSrm:
1481  case X86::MOVAPDrm:
1482  case X86::MOVDQArm:
1483  case X86::VMOVSSrm:
1484  case X86::VMOVSDrm:
1485  case X86::VMOVAPSrm:
1486  case X86::VMOVAPDrm:
1487  case X86::VMOVDQArm:
1488  case X86::VMOVAPSYrm:
1489  case X86::VMOVAPDYrm:
1490  case X86::VMOVDQAYrm:
1491  case X86::MMX_MOVD64rm:
1492  case X86::MMX_MOVQ64rm:
1493    return true;
1494  }
1495}
1496
1497static bool isFrameStoreOpcode(int Opcode) {
1498  switch (Opcode) {
1499  default: break;
1500  case X86::MOV8mr:
1501  case X86::MOV16mr:
1502  case X86::MOV32mr:
1503  case X86::MOV64mr:
1504  case X86::ST_FpP64m:
1505  case X86::MOVSSmr:
1506  case X86::MOVSDmr:
1507  case X86::MOVAPSmr:
1508  case X86::MOVAPDmr:
1509  case X86::MOVDQAmr:
1510  case X86::VMOVSSmr:
1511  case X86::VMOVSDmr:
1512  case X86::VMOVAPSmr:
1513  case X86::VMOVAPDmr:
1514  case X86::VMOVDQAmr:
1515  case X86::VMOVAPSYmr:
1516  case X86::VMOVAPDYmr:
1517  case X86::VMOVDQAYmr:
1518  case X86::MMX_MOVD64mr:
1519  case X86::MMX_MOVQ64mr:
1520  case X86::MMX_MOVNTQmr:
1521    return true;
1522  }
1523  return false;
1524}
1525
1526unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
1527                                           int &FrameIndex) const {
1528  if (isFrameLoadOpcode(MI->getOpcode()))
1529    if (MI->getOperand(0).getSubReg() == 0 && isFrameOperand(MI, 1, FrameIndex))
1530      return MI->getOperand(0).getReg();
1531  return 0;
1532}
1533
1534unsigned X86InstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI,
1535                                                 int &FrameIndex) const {
1536  if (isFrameLoadOpcode(MI->getOpcode())) {
1537    unsigned Reg;
1538    if ((Reg = isLoadFromStackSlot(MI, FrameIndex)))
1539      return Reg;
1540    // Check for post-frame index elimination operations
1541    const MachineMemOperand *Dummy;
1542    return hasLoadFromStackSlot(MI, Dummy, FrameIndex);
1543  }
1544  return 0;
1545}
1546
1547unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr *MI,
1548                                          int &FrameIndex) const {
1549  if (isFrameStoreOpcode(MI->getOpcode()))
1550    if (MI->getOperand(X86::AddrNumOperands).getSubReg() == 0 &&
1551        isFrameOperand(MI, 0, FrameIndex))
1552      return MI->getOperand(X86::AddrNumOperands).getReg();
1553  return 0;
1554}
1555
1556unsigned X86InstrInfo::isStoreToStackSlotPostFE(const MachineInstr *MI,
1557                                                int &FrameIndex) const {
1558  if (isFrameStoreOpcode(MI->getOpcode())) {
1559    unsigned Reg;
1560    if ((Reg = isStoreToStackSlot(MI, FrameIndex)))
1561      return Reg;
1562    // Check for post-frame index elimination operations
1563    const MachineMemOperand *Dummy;
1564    return hasStoreToStackSlot(MI, Dummy, FrameIndex);
1565  }
1566  return 0;
1567}
1568
1569/// regIsPICBase - Return true if register is PIC base (i.e.g defined by
1570/// X86::MOVPC32r.
1571static bool regIsPICBase(unsigned BaseReg, const MachineRegisterInfo &MRI) {
1572  // Don't waste compile time scanning use-def chains of physregs.
1573  if (!TargetRegisterInfo::isVirtualRegister(BaseReg))
1574    return false;
1575  bool isPICBase = false;
1576  for (MachineRegisterInfo::def_iterator I = MRI.def_begin(BaseReg),
1577         E = MRI.def_end(); I != E; ++I) {
1578    MachineInstr *DefMI = I.getOperand().getParent();
1579    if (DefMI->getOpcode() != X86::MOVPC32r)
1580      return false;
1581    assert(!isPICBase && "More than one PIC base?");
1582    isPICBase = true;
1583  }
1584  return isPICBase;
1585}
1586
1587bool
1588X86InstrInfo::isReallyTriviallyReMaterializable(const MachineInstr *MI,
1589                                                AliasAnalysis *AA) const {
1590  switch (MI->getOpcode()) {
1591  default: break;
1592  case X86::MOV8rm:
1593  case X86::MOV16rm:
1594  case X86::MOV32rm:
1595  case X86::MOV64rm:
1596  case X86::LD_Fp64m:
1597  case X86::MOVSSrm:
1598  case X86::MOVSDrm:
1599  case X86::MOVAPSrm:
1600  case X86::MOVUPSrm:
1601  case X86::MOVAPDrm:
1602  case X86::MOVDQArm:
1603  case X86::MOVDQUrm:
1604  case X86::VMOVSSrm:
1605  case X86::VMOVSDrm:
1606  case X86::VMOVAPSrm:
1607  case X86::VMOVUPSrm:
1608  case X86::VMOVAPDrm:
1609  case X86::VMOVDQArm:
1610  case X86::VMOVDQUrm:
1611  case X86::VMOVAPSYrm:
1612  case X86::VMOVUPSYrm:
1613  case X86::VMOVAPDYrm:
1614  case X86::VMOVDQAYrm:
1615  case X86::VMOVDQUYrm:
1616  case X86::MMX_MOVD64rm:
1617  case X86::MMX_MOVQ64rm:
1618  case X86::FsVMOVAPSrm:
1619  case X86::FsVMOVAPDrm:
1620  case X86::FsMOVAPSrm:
1621  case X86::FsMOVAPDrm: {
1622    // Loads from constant pools are trivially rematerializable.
1623    if (MI->getOperand(1).isReg() &&
1624        MI->getOperand(2).isImm() &&
1625        MI->getOperand(3).isReg() && MI->getOperand(3).getReg() == 0 &&
1626        MI->isInvariantLoad(AA)) {
1627      unsigned BaseReg = MI->getOperand(1).getReg();
1628      if (BaseReg == 0 || BaseReg == X86::RIP)
1629        return true;
1630      // Allow re-materialization of PIC load.
1631      if (!ReMatPICStubLoad && MI->getOperand(4).isGlobal())
1632        return false;
1633      const MachineFunction &MF = *MI->getParent()->getParent();
1634      const MachineRegisterInfo &MRI = MF.getRegInfo();
1635      return regIsPICBase(BaseReg, MRI);
1636    }
1637    return false;
1638  }
1639
1640  case X86::LEA32r:
1641  case X86::LEA64r: {
1642    if (MI->getOperand(2).isImm() &&
1643        MI->getOperand(3).isReg() && MI->getOperand(3).getReg() == 0 &&
1644        !MI->getOperand(4).isReg()) {
1645      // lea fi#, lea GV, etc. are all rematerializable.
1646      if (!MI->getOperand(1).isReg())
1647        return true;
1648      unsigned BaseReg = MI->getOperand(1).getReg();
1649      if (BaseReg == 0)
1650        return true;
1651      // Allow re-materialization of lea PICBase + x.
1652      const MachineFunction &MF = *MI->getParent()->getParent();
1653      const MachineRegisterInfo &MRI = MF.getRegInfo();
1654      return regIsPICBase(BaseReg, MRI);
1655    }
1656    return false;
1657  }
1658  }
1659
1660  // All other instructions marked M_REMATERIALIZABLE are always trivially
1661  // rematerializable.
1662  return true;
1663}
1664
1665/// isSafeToClobberEFLAGS - Return true if it's safe insert an instruction that
1666/// would clobber the EFLAGS condition register. Note the result may be
1667/// conservative. If it cannot definitely determine the safety after visiting
1668/// a few instructions in each direction it assumes it's not safe.
1669static bool isSafeToClobberEFLAGS(MachineBasicBlock &MBB,
1670                                  MachineBasicBlock::iterator I) {
1671  MachineBasicBlock::iterator E = MBB.end();
1672
1673  // For compile time consideration, if we are not able to determine the
1674  // safety after visiting 4 instructions in each direction, we will assume
1675  // it's not safe.
1676  MachineBasicBlock::iterator Iter = I;
1677  for (unsigned i = 0; Iter != E && i < 4; ++i) {
1678    bool SeenDef = false;
1679    for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
1680      MachineOperand &MO = Iter->getOperand(j);
1681      if (MO.isRegMask() && MO.clobbersPhysReg(X86::EFLAGS))
1682        SeenDef = true;
1683      if (!MO.isReg())
1684        continue;
1685      if (MO.getReg() == X86::EFLAGS) {
1686        if (MO.isUse())
1687          return false;
1688        SeenDef = true;
1689      }
1690    }
1691
1692    if (SeenDef)
1693      // This instruction defines EFLAGS, no need to look any further.
1694      return true;
1695    ++Iter;
1696    // Skip over DBG_VALUE.
1697    while (Iter != E && Iter->isDebugValue())
1698      ++Iter;
1699  }
1700
1701  // It is safe to clobber EFLAGS at the end of a block of no successor has it
1702  // live in.
1703  if (Iter == E) {
1704    for (MachineBasicBlock::succ_iterator SI = MBB.succ_begin(),
1705           SE = MBB.succ_end(); SI != SE; ++SI)
1706      if ((*SI)->isLiveIn(X86::EFLAGS))
1707        return false;
1708    return true;
1709  }
1710
1711  MachineBasicBlock::iterator B = MBB.begin();
1712  Iter = I;
1713  for (unsigned i = 0; i < 4; ++i) {
1714    // If we make it to the beginning of the block, it's safe to clobber
1715    // EFLAGS iff EFLAGS is not live-in.
1716    if (Iter == B)
1717      return !MBB.isLiveIn(X86::EFLAGS);
1718
1719    --Iter;
1720    // Skip over DBG_VALUE.
1721    while (Iter != B && Iter->isDebugValue())
1722      --Iter;
1723
1724    bool SawKill = false;
1725    for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
1726      MachineOperand &MO = Iter->getOperand(j);
1727      // A register mask may clobber EFLAGS, but we should still look for a
1728      // live EFLAGS def.
1729      if (MO.isRegMask() && MO.clobbersPhysReg(X86::EFLAGS))
1730        SawKill = true;
1731      if (MO.isReg() && MO.getReg() == X86::EFLAGS) {
1732        if (MO.isDef()) return MO.isDead();
1733        if (MO.isKill()) SawKill = true;
1734      }
1735    }
1736
1737    if (SawKill)
1738      // This instruction kills EFLAGS and doesn't redefine it, so
1739      // there's no need to look further.
1740      return true;
1741  }
1742
1743  // Conservative answer.
1744  return false;
1745}
1746
1747void X86InstrInfo::reMaterialize(MachineBasicBlock &MBB,
1748                                 MachineBasicBlock::iterator I,
1749                                 unsigned DestReg, unsigned SubIdx,
1750                                 const MachineInstr *Orig,
1751                                 const TargetRegisterInfo &TRI) const {
1752  DebugLoc DL = Orig->getDebugLoc();
1753
1754  // MOV32r0 etc. are implemented with xor which clobbers condition code.
1755  // Re-materialize them as movri instructions to avoid side effects.
1756  bool Clone = true;
1757  unsigned Opc = Orig->getOpcode();
1758  switch (Opc) {
1759  default: break;
1760  case X86::MOV8r0:
1761  case X86::MOV16r0:
1762  case X86::MOV32r0:
1763  case X86::MOV64r0: {
1764    if (!isSafeToClobberEFLAGS(MBB, I)) {
1765      switch (Opc) {
1766      default: llvm_unreachable("Unreachable!");
1767      case X86::MOV8r0:  Opc = X86::MOV8ri;  break;
1768      case X86::MOV16r0: Opc = X86::MOV16ri; break;
1769      case X86::MOV32r0: Opc = X86::MOV32ri; break;
1770      case X86::MOV64r0: Opc = X86::MOV64ri64i32; break;
1771      }
1772      Clone = false;
1773    }
1774    break;
1775  }
1776  }
1777
1778  if (Clone) {
1779    MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
1780    MBB.insert(I, MI);
1781  } else {
1782    BuildMI(MBB, I, DL, get(Opc)).addOperand(Orig->getOperand(0)).addImm(0);
1783  }
1784
1785  MachineInstr *NewMI = prior(I);
1786  NewMI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI);
1787}
1788
1789/// hasLiveCondCodeDef - True if MI has a condition code def, e.g. EFLAGS, that
1790/// is not marked dead.
1791static bool hasLiveCondCodeDef(MachineInstr *MI) {
1792  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1793    MachineOperand &MO = MI->getOperand(i);
1794    if (MO.isReg() && MO.isDef() &&
1795        MO.getReg() == X86::EFLAGS && !MO.isDead()) {
1796      return true;
1797    }
1798  }
1799  return false;
1800}
1801
1802/// convertToThreeAddressWithLEA - Helper for convertToThreeAddress when
1803/// 16-bit LEA is disabled, use 32-bit LEA to form 3-address code by promoting
1804/// to a 32-bit superregister and then truncating back down to a 16-bit
1805/// subregister.
1806MachineInstr *
1807X86InstrInfo::convertToThreeAddressWithLEA(unsigned MIOpc,
1808                                           MachineFunction::iterator &MFI,
1809                                           MachineBasicBlock::iterator &MBBI,
1810                                           LiveVariables *LV) const {
1811  MachineInstr *MI = MBBI;
1812  unsigned Dest = MI->getOperand(0).getReg();
1813  unsigned Src = MI->getOperand(1).getReg();
1814  bool isDead = MI->getOperand(0).isDead();
1815  bool isKill = MI->getOperand(1).isKill();
1816
1817  unsigned Opc = TM.getSubtarget<X86Subtarget>().is64Bit()
1818    ? X86::LEA64_32r : X86::LEA32r;
1819  MachineRegisterInfo &RegInfo = MFI->getParent()->getRegInfo();
1820  unsigned leaInReg = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
1821  unsigned leaOutReg = RegInfo.createVirtualRegister(&X86::GR32RegClass);
1822
1823  // Build and insert into an implicit UNDEF value. This is OK because
1824  // well be shifting and then extracting the lower 16-bits.
1825  // This has the potential to cause partial register stall. e.g.
1826  //   movw    (%rbp,%rcx,2), %dx
1827  //   leal    -65(%rdx), %esi
1828  // But testing has shown this *does* help performance in 64-bit mode (at
1829  // least on modern x86 machines).
1830  BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg);
1831  MachineInstr *InsMI =
1832    BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(TargetOpcode::COPY))
1833    .addReg(leaInReg, RegState::Define, X86::sub_16bit)
1834    .addReg(Src, getKillRegState(isKill));
1835
1836  MachineInstrBuilder MIB = BuildMI(*MFI, MBBI, MI->getDebugLoc(),
1837                                    get(Opc), leaOutReg);
1838  switch (MIOpc) {
1839  default: llvm_unreachable("Unreachable!");
1840  case X86::SHL16ri: {
1841    unsigned ShAmt = MI->getOperand(2).getImm();
1842    MIB.addReg(0).addImm(1 << ShAmt)
1843       .addReg(leaInReg, RegState::Kill).addImm(0).addReg(0);
1844    break;
1845  }
1846  case X86::INC16r:
1847  case X86::INC64_16r:
1848    addRegOffset(MIB, leaInReg, true, 1);
1849    break;
1850  case X86::DEC16r:
1851  case X86::DEC64_16r:
1852    addRegOffset(MIB, leaInReg, true, -1);
1853    break;
1854  case X86::ADD16ri:
1855  case X86::ADD16ri8:
1856  case X86::ADD16ri_DB:
1857  case X86::ADD16ri8_DB:
1858    addRegOffset(MIB, leaInReg, true, MI->getOperand(2).getImm());
1859    break;
1860  case X86::ADD16rr:
1861  case X86::ADD16rr_DB: {
1862    unsigned Src2 = MI->getOperand(2).getReg();
1863    bool isKill2 = MI->getOperand(2).isKill();
1864    unsigned leaInReg2 = 0;
1865    MachineInstr *InsMI2 = 0;
1866    if (Src == Src2) {
1867      // ADD16rr %reg1028<kill>, %reg1028
1868      // just a single insert_subreg.
1869      addRegReg(MIB, leaInReg, true, leaInReg, false);
1870    } else {
1871      leaInReg2 = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
1872      // Build and insert into an implicit UNDEF value. This is OK because
1873      // well be shifting and then extracting the lower 16-bits.
1874      BuildMI(*MFI, &*MIB, MI->getDebugLoc(), get(X86::IMPLICIT_DEF),leaInReg2);
1875      InsMI2 =
1876        BuildMI(*MFI, &*MIB, MI->getDebugLoc(), get(TargetOpcode::COPY))
1877        .addReg(leaInReg2, RegState::Define, X86::sub_16bit)
1878        .addReg(Src2, getKillRegState(isKill2));
1879      addRegReg(MIB, leaInReg, true, leaInReg2, true);
1880    }
1881    if (LV && isKill2 && InsMI2)
1882      LV->replaceKillInstruction(Src2, MI, InsMI2);
1883    break;
1884  }
1885  }
1886
1887  MachineInstr *NewMI = MIB;
1888  MachineInstr *ExtMI =
1889    BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(TargetOpcode::COPY))
1890    .addReg(Dest, RegState::Define | getDeadRegState(isDead))
1891    .addReg(leaOutReg, RegState::Kill, X86::sub_16bit);
1892
1893  if (LV) {
1894    // Update live variables
1895    LV->getVarInfo(leaInReg).Kills.push_back(NewMI);
1896    LV->getVarInfo(leaOutReg).Kills.push_back(ExtMI);
1897    if (isKill)
1898      LV->replaceKillInstruction(Src, MI, InsMI);
1899    if (isDead)
1900      LV->replaceKillInstruction(Dest, MI, ExtMI);
1901  }
1902
1903  return ExtMI;
1904}
1905
1906/// convertToThreeAddress - This method must be implemented by targets that
1907/// set the M_CONVERTIBLE_TO_3_ADDR flag.  When this flag is set, the target
1908/// may be able to convert a two-address instruction into a true
1909/// three-address instruction on demand.  This allows the X86 target (for
1910/// example) to convert ADD and SHL instructions into LEA instructions if they
1911/// would require register copies due to two-addressness.
1912///
1913/// This method returns a null pointer if the transformation cannot be
1914/// performed, otherwise it returns the new instruction.
1915///
1916MachineInstr *
1917X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
1918                                    MachineBasicBlock::iterator &MBBI,
1919                                    LiveVariables *LV) const {
1920  MachineInstr *MI = MBBI;
1921  MachineFunction &MF = *MI->getParent()->getParent();
1922  // All instructions input are two-addr instructions.  Get the known operands.
1923  const MachineOperand &Dest = MI->getOperand(0);
1924  const MachineOperand &Src = MI->getOperand(1);
1925
1926  MachineInstr *NewMI = NULL;
1927  // FIXME: 16-bit LEA's are really slow on Athlons, but not bad on P4's.  When
1928  // we have better subtarget support, enable the 16-bit LEA generation here.
1929  // 16-bit LEA is also slow on Core2.
1930  bool DisableLEA16 = true;
1931  bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit();
1932
1933  unsigned MIOpc = MI->getOpcode();
1934  switch (MIOpc) {
1935  case X86::SHUFPSrri: {
1936    assert(MI->getNumOperands() == 4 && "Unknown shufps instruction!");
1937    if (!TM.getSubtarget<X86Subtarget>().hasSSE2()) return 0;
1938
1939    unsigned B = MI->getOperand(1).getReg();
1940    unsigned C = MI->getOperand(2).getReg();
1941    if (B != C) return 0;
1942    unsigned M = MI->getOperand(3).getImm();
1943    NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::PSHUFDri))
1944      .addOperand(Dest).addOperand(Src).addImm(M);
1945    break;
1946  }
1947  case X86::SHUFPDrri: {
1948    assert(MI->getNumOperands() == 4 && "Unknown shufpd instruction!");
1949    if (!TM.getSubtarget<X86Subtarget>().hasSSE2()) return 0;
1950
1951    unsigned B = MI->getOperand(1).getReg();
1952    unsigned C = MI->getOperand(2).getReg();
1953    if (B != C) return 0;
1954    unsigned M = MI->getOperand(3).getImm();
1955
1956    // Convert to PSHUFD mask.
1957    M = ((M & 1) << 1) | ((M & 1) << 3) | ((M & 2) << 4) | ((M & 2) << 6)| 0x44;
1958
1959    NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::PSHUFDri))
1960      .addOperand(Dest).addOperand(Src).addImm(M);
1961    break;
1962  }
1963  case X86::SHL64ri: {
1964    assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
1965    // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
1966    // the flags produced by a shift yet, so this is safe.
1967    unsigned ShAmt = MI->getOperand(2).getImm();
1968    if (ShAmt == 0 || ShAmt >= 4) return 0;
1969
1970    // LEA can't handle RSP.
1971    if (TargetRegisterInfo::isVirtualRegister(Src.getReg()) &&
1972        !MF.getRegInfo().constrainRegClass(Src.getReg(),
1973                                           &X86::GR64_NOSPRegClass))
1974      return 0;
1975
1976    NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
1977      .addOperand(Dest)
1978      .addReg(0).addImm(1 << ShAmt).addOperand(Src).addImm(0).addReg(0);
1979    break;
1980  }
1981  case X86::SHL32ri: {
1982    assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
1983    // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
1984    // the flags produced by a shift yet, so this is safe.
1985    unsigned ShAmt = MI->getOperand(2).getImm();
1986    if (ShAmt == 0 || ShAmt >= 4) return 0;
1987
1988    // LEA can't handle ESP.
1989    if (TargetRegisterInfo::isVirtualRegister(Src.getReg()) &&
1990        !MF.getRegInfo().constrainRegClass(Src.getReg(),
1991                                           &X86::GR32_NOSPRegClass))
1992      return 0;
1993
1994    unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
1995    NewMI = BuildMI(MF, MI->getDebugLoc(), get(Opc))
1996      .addOperand(Dest)
1997      .addReg(0).addImm(1 << ShAmt).addOperand(Src).addImm(0).addReg(0);
1998    break;
1999  }
2000  case X86::SHL16ri: {
2001    assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
2002    // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
2003    // the flags produced by a shift yet, so this is safe.
2004    unsigned ShAmt = MI->getOperand(2).getImm();
2005    if (ShAmt == 0 || ShAmt >= 4) return 0;
2006
2007    if (DisableLEA16)
2008      return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
2009    NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2010      .addOperand(Dest)
2011      .addReg(0).addImm(1 << ShAmt).addOperand(Src).addImm(0).addReg(0);
2012    break;
2013  }
2014  default: {
2015    // The following opcodes also sets the condition code register(s). Only
2016    // convert them to equivalent lea if the condition code register def's
2017    // are dead!
2018    if (hasLiveCondCodeDef(MI))
2019      return 0;
2020
2021    switch (MIOpc) {
2022    default: return 0;
2023    case X86::INC64r:
2024    case X86::INC32r:
2025    case X86::INC64_32r: {
2026      assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
2027      unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r
2028        : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
2029      const TargetRegisterClass *RC = MIOpc == X86::INC64r ?
2030        (const TargetRegisterClass*)&X86::GR64_NOSPRegClass :
2031        (const TargetRegisterClass*)&X86::GR32_NOSPRegClass;
2032
2033      // LEA can't handle RSP.
2034      if (TargetRegisterInfo::isVirtualRegister(Src.getReg()) &&
2035          !MF.getRegInfo().constrainRegClass(Src.getReg(), RC))
2036        return 0;
2037
2038      NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
2039                        .addOperand(Dest).addOperand(Src), 1);
2040      break;
2041    }
2042    case X86::INC16r:
2043    case X86::INC64_16r:
2044      if (DisableLEA16)
2045        return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
2046      assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
2047      NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2048                        .addOperand(Dest).addOperand(Src), 1);
2049      break;
2050    case X86::DEC64r:
2051    case X86::DEC32r:
2052    case X86::DEC64_32r: {
2053      assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
2054      unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r
2055        : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
2056      const TargetRegisterClass *RC = MIOpc == X86::DEC64r ?
2057        (const TargetRegisterClass*)&X86::GR64_NOSPRegClass :
2058        (const TargetRegisterClass*)&X86::GR32_NOSPRegClass;
2059      // LEA can't handle RSP.
2060      if (TargetRegisterInfo::isVirtualRegister(Src.getReg()) &&
2061          !MF.getRegInfo().constrainRegClass(Src.getReg(), RC))
2062        return 0;
2063
2064      NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
2065                        .addOperand(Dest).addOperand(Src), -1);
2066      break;
2067    }
2068    case X86::DEC16r:
2069    case X86::DEC64_16r:
2070      if (DisableLEA16)
2071        return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
2072      assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
2073      NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2074                        .addOperand(Dest).addOperand(Src), -1);
2075      break;
2076    case X86::ADD64rr:
2077    case X86::ADD64rr_DB:
2078    case X86::ADD32rr:
2079    case X86::ADD32rr_DB: {
2080      assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2081      unsigned Opc;
2082      const TargetRegisterClass *RC;
2083      if (MIOpc == X86::ADD64rr || MIOpc == X86::ADD64rr_DB) {
2084        Opc = X86::LEA64r;
2085        RC = &X86::GR64_NOSPRegClass;
2086      } else {
2087        Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
2088        RC = &X86::GR32_NOSPRegClass;
2089      }
2090
2091
2092      unsigned Src2 = MI->getOperand(2).getReg();
2093      bool isKill2 = MI->getOperand(2).isKill();
2094
2095      // LEA can't handle RSP.
2096      if (TargetRegisterInfo::isVirtualRegister(Src2) &&
2097          !MF.getRegInfo().constrainRegClass(Src2, RC))
2098        return 0;
2099
2100      NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(Opc))
2101                        .addOperand(Dest),
2102                        Src.getReg(), Src.isKill(), Src2, isKill2);
2103
2104      // Preserve undefness of the operands.
2105      bool isUndef = MI->getOperand(1).isUndef();
2106      bool isUndef2 = MI->getOperand(2).isUndef();
2107      NewMI->getOperand(1).setIsUndef(isUndef);
2108      NewMI->getOperand(3).setIsUndef(isUndef2);
2109
2110      if (LV && isKill2)
2111        LV->replaceKillInstruction(Src2, MI, NewMI);
2112      break;
2113    }
2114    case X86::ADD16rr:
2115    case X86::ADD16rr_DB: {
2116      if (DisableLEA16)
2117        return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
2118      assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2119      unsigned Src2 = MI->getOperand(2).getReg();
2120      bool isKill2 = MI->getOperand(2).isKill();
2121      NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2122                        .addOperand(Dest),
2123                        Src.getReg(), Src.isKill(), Src2, isKill2);
2124
2125      // Preserve undefness of the operands.
2126      bool isUndef = MI->getOperand(1).isUndef();
2127      bool isUndef2 = MI->getOperand(2).isUndef();
2128      NewMI->getOperand(1).setIsUndef(isUndef);
2129      NewMI->getOperand(3).setIsUndef(isUndef2);
2130
2131      if (LV && isKill2)
2132        LV->replaceKillInstruction(Src2, MI, NewMI);
2133      break;
2134    }
2135    case X86::ADD64ri32:
2136    case X86::ADD64ri8:
2137    case X86::ADD64ri32_DB:
2138    case X86::ADD64ri8_DB:
2139      assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2140      NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
2141                        .addOperand(Dest).addOperand(Src),
2142                        MI->getOperand(2).getImm());
2143      break;
2144    case X86::ADD32ri:
2145    case X86::ADD32ri8:
2146    case X86::ADD32ri_DB:
2147    case X86::ADD32ri8_DB: {
2148      assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2149      unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
2150      NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
2151                        .addOperand(Dest).addOperand(Src),
2152                        MI->getOperand(2).getImm());
2153      break;
2154    }
2155    case X86::ADD16ri:
2156    case X86::ADD16ri8:
2157    case X86::ADD16ri_DB:
2158    case X86::ADD16ri8_DB:
2159      if (DisableLEA16)
2160        return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
2161      assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2162      NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2163                        .addOperand(Dest).addOperand(Src),
2164                        MI->getOperand(2).getImm());
2165      break;
2166    }
2167  }
2168  }
2169
2170  if (!NewMI) return 0;
2171
2172  if (LV) {  // Update live variables
2173    if (Src.isKill())
2174      LV->replaceKillInstruction(Src.getReg(), MI, NewMI);
2175    if (Dest.isDead())
2176      LV->replaceKillInstruction(Dest.getReg(), MI, NewMI);
2177  }
2178
2179  MFI->insert(MBBI, NewMI);          // Insert the new inst
2180  return NewMI;
2181}
2182
2183/// commuteInstruction - We have a few instructions that must be hacked on to
2184/// commute them.
2185///
2186MachineInstr *
2187X86InstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
2188  switch (MI->getOpcode()) {
2189  case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I)
2190  case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I)
2191  case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I)
2192  case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I)
2193  case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I -> A = SHLD64rri8 C, B, (64-I)
2194  case X86::SHLD64rri8:{// A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, (64-I)
2195    unsigned Opc;
2196    unsigned Size;
2197    switch (MI->getOpcode()) {
2198    default: llvm_unreachable("Unreachable!");
2199    case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break;
2200    case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break;
2201    case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break;
2202    case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break;
2203    case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break;
2204    case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break;
2205    }
2206    unsigned Amt = MI->getOperand(3).getImm();
2207    if (NewMI) {
2208      MachineFunction &MF = *MI->getParent()->getParent();
2209      MI = MF.CloneMachineInstr(MI);
2210      NewMI = false;
2211    }
2212    MI->setDesc(get(Opc));
2213    MI->getOperand(3).setImm(Size-Amt);
2214    return TargetInstrInfo::commuteInstruction(MI, NewMI);
2215  }
2216  case X86::CMOVB16rr:  case X86::CMOVB32rr:  case X86::CMOVB64rr:
2217  case X86::CMOVAE16rr: case X86::CMOVAE32rr: case X86::CMOVAE64rr:
2218  case X86::CMOVE16rr:  case X86::CMOVE32rr:  case X86::CMOVE64rr:
2219  case X86::CMOVNE16rr: case X86::CMOVNE32rr: case X86::CMOVNE64rr:
2220  case X86::CMOVBE16rr: case X86::CMOVBE32rr: case X86::CMOVBE64rr:
2221  case X86::CMOVA16rr:  case X86::CMOVA32rr:  case X86::CMOVA64rr:
2222  case X86::CMOVL16rr:  case X86::CMOVL32rr:  case X86::CMOVL64rr:
2223  case X86::CMOVGE16rr: case X86::CMOVGE32rr: case X86::CMOVGE64rr:
2224  case X86::CMOVLE16rr: case X86::CMOVLE32rr: case X86::CMOVLE64rr:
2225  case X86::CMOVG16rr:  case X86::CMOVG32rr:  case X86::CMOVG64rr:
2226  case X86::CMOVS16rr:  case X86::CMOVS32rr:  case X86::CMOVS64rr:
2227  case X86::CMOVNS16rr: case X86::CMOVNS32rr: case X86::CMOVNS64rr:
2228  case X86::CMOVP16rr:  case X86::CMOVP32rr:  case X86::CMOVP64rr:
2229  case X86::CMOVNP16rr: case X86::CMOVNP32rr: case X86::CMOVNP64rr:
2230  case X86::CMOVO16rr:  case X86::CMOVO32rr:  case X86::CMOVO64rr:
2231  case X86::CMOVNO16rr: case X86::CMOVNO32rr: case X86::CMOVNO64rr: {
2232    unsigned Opc;
2233    switch (MI->getOpcode()) {
2234    default: llvm_unreachable("Unreachable!");
2235    case X86::CMOVB16rr:  Opc = X86::CMOVAE16rr; break;
2236    case X86::CMOVB32rr:  Opc = X86::CMOVAE32rr; break;
2237    case X86::CMOVB64rr:  Opc = X86::CMOVAE64rr; break;
2238    case X86::CMOVAE16rr: Opc = X86::CMOVB16rr; break;
2239    case X86::CMOVAE32rr: Opc = X86::CMOVB32rr; break;
2240    case X86::CMOVAE64rr: Opc = X86::CMOVB64rr; break;
2241    case X86::CMOVE16rr:  Opc = X86::CMOVNE16rr; break;
2242    case X86::CMOVE32rr:  Opc = X86::CMOVNE32rr; break;
2243    case X86::CMOVE64rr:  Opc = X86::CMOVNE64rr; break;
2244    case X86::CMOVNE16rr: Opc = X86::CMOVE16rr; break;
2245    case X86::CMOVNE32rr: Opc = X86::CMOVE32rr; break;
2246    case X86::CMOVNE64rr: Opc = X86::CMOVE64rr; break;
2247    case X86::CMOVBE16rr: Opc = X86::CMOVA16rr; break;
2248    case X86::CMOVBE32rr: Opc = X86::CMOVA32rr; break;
2249    case X86::CMOVBE64rr: Opc = X86::CMOVA64rr; break;
2250    case X86::CMOVA16rr:  Opc = X86::CMOVBE16rr; break;
2251    case X86::CMOVA32rr:  Opc = X86::CMOVBE32rr; break;
2252    case X86::CMOVA64rr:  Opc = X86::CMOVBE64rr; break;
2253    case X86::CMOVL16rr:  Opc = X86::CMOVGE16rr; break;
2254    case X86::CMOVL32rr:  Opc = X86::CMOVGE32rr; break;
2255    case X86::CMOVL64rr:  Opc = X86::CMOVGE64rr; break;
2256    case X86::CMOVGE16rr: Opc = X86::CMOVL16rr; break;
2257    case X86::CMOVGE32rr: Opc = X86::CMOVL32rr; break;
2258    case X86::CMOVGE64rr: Opc = X86::CMOVL64rr; break;
2259    case X86::CMOVLE16rr: Opc = X86::CMOVG16rr; break;
2260    case X86::CMOVLE32rr: Opc = X86::CMOVG32rr; break;
2261    case X86::CMOVLE64rr: Opc = X86::CMOVG64rr; break;
2262    case X86::CMOVG16rr:  Opc = X86::CMOVLE16rr; break;
2263    case X86::CMOVG32rr:  Opc = X86::CMOVLE32rr; break;
2264    case X86::CMOVG64rr:  Opc = X86::CMOVLE64rr; break;
2265    case X86::CMOVS16rr:  Opc = X86::CMOVNS16rr; break;
2266    case X86::CMOVS32rr:  Opc = X86::CMOVNS32rr; break;
2267    case X86::CMOVS64rr:  Opc = X86::CMOVNS64rr; break;
2268    case X86::CMOVNS16rr: Opc = X86::CMOVS16rr; break;
2269    case X86::CMOVNS32rr: Opc = X86::CMOVS32rr; break;
2270    case X86::CMOVNS64rr: Opc = X86::CMOVS64rr; break;
2271    case X86::CMOVP16rr:  Opc = X86::CMOVNP16rr; break;
2272    case X86::CMOVP32rr:  Opc = X86::CMOVNP32rr; break;
2273    case X86::CMOVP64rr:  Opc = X86::CMOVNP64rr; break;
2274    case X86::CMOVNP16rr: Opc = X86::CMOVP16rr; break;
2275    case X86::CMOVNP32rr: Opc = X86::CMOVP32rr; break;
2276    case X86::CMOVNP64rr: Opc = X86::CMOVP64rr; break;
2277    case X86::CMOVO16rr:  Opc = X86::CMOVNO16rr; break;
2278    case X86::CMOVO32rr:  Opc = X86::CMOVNO32rr; break;
2279    case X86::CMOVO64rr:  Opc = X86::CMOVNO64rr; break;
2280    case X86::CMOVNO16rr: Opc = X86::CMOVO16rr; break;
2281    case X86::CMOVNO32rr: Opc = X86::CMOVO32rr; break;
2282    case X86::CMOVNO64rr: Opc = X86::CMOVO64rr; break;
2283    }
2284    if (NewMI) {
2285      MachineFunction &MF = *MI->getParent()->getParent();
2286      MI = MF.CloneMachineInstr(MI);
2287      NewMI = false;
2288    }
2289    MI->setDesc(get(Opc));
2290    // Fallthrough intended.
2291  }
2292  default:
2293    return TargetInstrInfo::commuteInstruction(MI, NewMI);
2294  }
2295}
2296
2297static X86::CondCode getCondFromBranchOpc(unsigned BrOpc) {
2298  switch (BrOpc) {
2299  default: return X86::COND_INVALID;
2300  case X86::JE_4:  return X86::COND_E;
2301  case X86::JNE_4: return X86::COND_NE;
2302  case X86::JL_4:  return X86::COND_L;
2303  case X86::JLE_4: return X86::COND_LE;
2304  case X86::JG_4:  return X86::COND_G;
2305  case X86::JGE_4: return X86::COND_GE;
2306  case X86::JB_4:  return X86::COND_B;
2307  case X86::JBE_4: return X86::COND_BE;
2308  case X86::JA_4:  return X86::COND_A;
2309  case X86::JAE_4: return X86::COND_AE;
2310  case X86::JS_4:  return X86::COND_S;
2311  case X86::JNS_4: return X86::COND_NS;
2312  case X86::JP_4:  return X86::COND_P;
2313  case X86::JNP_4: return X86::COND_NP;
2314  case X86::JO_4:  return X86::COND_O;
2315  case X86::JNO_4: return X86::COND_NO;
2316  }
2317}
2318
2319/// getCondFromSETOpc - return condition code of a SET opcode.
2320static X86::CondCode getCondFromSETOpc(unsigned Opc) {
2321  switch (Opc) {
2322  default: return X86::COND_INVALID;
2323  case X86::SETAr:  case X86::SETAm:  return X86::COND_A;
2324  case X86::SETAEr: case X86::SETAEm: return X86::COND_AE;
2325  case X86::SETBr:  case X86::SETBm:  return X86::COND_B;
2326  case X86::SETBEr: case X86::SETBEm: return X86::COND_BE;
2327  case X86::SETEr:  case X86::SETEm:  return X86::COND_E;
2328  case X86::SETGr:  case X86::SETGm:  return X86::COND_G;
2329  case X86::SETGEr: case X86::SETGEm: return X86::COND_GE;
2330  case X86::SETLr:  case X86::SETLm:  return X86::COND_L;
2331  case X86::SETLEr: case X86::SETLEm: return X86::COND_LE;
2332  case X86::SETNEr: case X86::SETNEm: return X86::COND_NE;
2333  case X86::SETNOr: case X86::SETNOm: return X86::COND_NO;
2334  case X86::SETNPr: case X86::SETNPm: return X86::COND_NP;
2335  case X86::SETNSr: case X86::SETNSm: return X86::COND_NS;
2336  case X86::SETOr:  case X86::SETOm:  return X86::COND_O;
2337  case X86::SETPr:  case X86::SETPm:  return X86::COND_P;
2338  case X86::SETSr:  case X86::SETSm:  return X86::COND_S;
2339  }
2340}
2341
2342/// getCondFromCmovOpc - return condition code of a CMov opcode.
2343X86::CondCode X86::getCondFromCMovOpc(unsigned Opc) {
2344  switch (Opc) {
2345  default: return X86::COND_INVALID;
2346  case X86::CMOVA16rm:  case X86::CMOVA16rr:  case X86::CMOVA32rm:
2347  case X86::CMOVA32rr:  case X86::CMOVA64rm:  case X86::CMOVA64rr:
2348    return X86::COND_A;
2349  case X86::CMOVAE16rm: case X86::CMOVAE16rr: case X86::CMOVAE32rm:
2350  case X86::CMOVAE32rr: case X86::CMOVAE64rm: case X86::CMOVAE64rr:
2351    return X86::COND_AE;
2352  case X86::CMOVB16rm:  case X86::CMOVB16rr:  case X86::CMOVB32rm:
2353  case X86::CMOVB32rr:  case X86::CMOVB64rm:  case X86::CMOVB64rr:
2354    return X86::COND_B;
2355  case X86::CMOVBE16rm: case X86::CMOVBE16rr: case X86::CMOVBE32rm:
2356  case X86::CMOVBE32rr: case X86::CMOVBE64rm: case X86::CMOVBE64rr:
2357    return X86::COND_BE;
2358  case X86::CMOVE16rm:  case X86::CMOVE16rr:  case X86::CMOVE32rm:
2359  case X86::CMOVE32rr:  case X86::CMOVE64rm:  case X86::CMOVE64rr:
2360    return X86::COND_E;
2361  case X86::CMOVG16rm:  case X86::CMOVG16rr:  case X86::CMOVG32rm:
2362  case X86::CMOVG32rr:  case X86::CMOVG64rm:  case X86::CMOVG64rr:
2363    return X86::COND_G;
2364  case X86::CMOVGE16rm: case X86::CMOVGE16rr: case X86::CMOVGE32rm:
2365  case X86::CMOVGE32rr: case X86::CMOVGE64rm: case X86::CMOVGE64rr:
2366    return X86::COND_GE;
2367  case X86::CMOVL16rm:  case X86::CMOVL16rr:  case X86::CMOVL32rm:
2368  case X86::CMOVL32rr:  case X86::CMOVL64rm:  case X86::CMOVL64rr:
2369    return X86::COND_L;
2370  case X86::CMOVLE16rm: case X86::CMOVLE16rr: case X86::CMOVLE32rm:
2371  case X86::CMOVLE32rr: case X86::CMOVLE64rm: case X86::CMOVLE64rr:
2372    return X86::COND_LE;
2373  case X86::CMOVNE16rm: case X86::CMOVNE16rr: case X86::CMOVNE32rm:
2374  case X86::CMOVNE32rr: case X86::CMOVNE64rm: case X86::CMOVNE64rr:
2375    return X86::COND_NE;
2376  case X86::CMOVNO16rm: case X86::CMOVNO16rr: case X86::CMOVNO32rm:
2377  case X86::CMOVNO32rr: case X86::CMOVNO64rm: case X86::CMOVNO64rr:
2378    return X86::COND_NO;
2379  case X86::CMOVNP16rm: case X86::CMOVNP16rr: case X86::CMOVNP32rm:
2380  case X86::CMOVNP32rr: case X86::CMOVNP64rm: case X86::CMOVNP64rr:
2381    return X86::COND_NP;
2382  case X86::CMOVNS16rm: case X86::CMOVNS16rr: case X86::CMOVNS32rm:
2383  case X86::CMOVNS32rr: case X86::CMOVNS64rm: case X86::CMOVNS64rr:
2384    return X86::COND_NS;
2385  case X86::CMOVO16rm:  case X86::CMOVO16rr:  case X86::CMOVO32rm:
2386  case X86::CMOVO32rr:  case X86::CMOVO64rm:  case X86::CMOVO64rr:
2387    return X86::COND_O;
2388  case X86::CMOVP16rm:  case X86::CMOVP16rr:  case X86::CMOVP32rm:
2389  case X86::CMOVP32rr:  case X86::CMOVP64rm:  case X86::CMOVP64rr:
2390    return X86::COND_P;
2391  case X86::CMOVS16rm:  case X86::CMOVS16rr:  case X86::CMOVS32rm:
2392  case X86::CMOVS32rr:  case X86::CMOVS64rm:  case X86::CMOVS64rr:
2393    return X86::COND_S;
2394  }
2395}
2396
2397unsigned X86::GetCondBranchFromCond(X86::CondCode CC) {
2398  switch (CC) {
2399  default: llvm_unreachable("Illegal condition code!");
2400  case X86::COND_E:  return X86::JE_4;
2401  case X86::COND_NE: return X86::JNE_4;
2402  case X86::COND_L:  return X86::JL_4;
2403  case X86::COND_LE: return X86::JLE_4;
2404  case X86::COND_G:  return X86::JG_4;
2405  case X86::COND_GE: return X86::JGE_4;
2406  case X86::COND_B:  return X86::JB_4;
2407  case X86::COND_BE: return X86::JBE_4;
2408  case X86::COND_A:  return X86::JA_4;
2409  case X86::COND_AE: return X86::JAE_4;
2410  case X86::COND_S:  return X86::JS_4;
2411  case X86::COND_NS: return X86::JNS_4;
2412  case X86::COND_P:  return X86::JP_4;
2413  case X86::COND_NP: return X86::JNP_4;
2414  case X86::COND_O:  return X86::JO_4;
2415  case X86::COND_NO: return X86::JNO_4;
2416  }
2417}
2418
2419/// GetOppositeBranchCondition - Return the inverse of the specified condition,
2420/// e.g. turning COND_E to COND_NE.
2421X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) {
2422  switch (CC) {
2423  default: llvm_unreachable("Illegal condition code!");
2424  case X86::COND_E:  return X86::COND_NE;
2425  case X86::COND_NE: return X86::COND_E;
2426  case X86::COND_L:  return X86::COND_GE;
2427  case X86::COND_LE: return X86::COND_G;
2428  case X86::COND_G:  return X86::COND_LE;
2429  case X86::COND_GE: return X86::COND_L;
2430  case X86::COND_B:  return X86::COND_AE;
2431  case X86::COND_BE: return X86::COND_A;
2432  case X86::COND_A:  return X86::COND_BE;
2433  case X86::COND_AE: return X86::COND_B;
2434  case X86::COND_S:  return X86::COND_NS;
2435  case X86::COND_NS: return X86::COND_S;
2436  case X86::COND_P:  return X86::COND_NP;
2437  case X86::COND_NP: return X86::COND_P;
2438  case X86::COND_O:  return X86::COND_NO;
2439  case X86::COND_NO: return X86::COND_O;
2440  }
2441}
2442
2443/// getSwappedCondition - assume the flags are set by MI(a,b), return
2444/// the condition code if we modify the instructions such that flags are
2445/// set by MI(b,a).
2446static X86::CondCode getSwappedCondition(X86::CondCode CC) {
2447  switch (CC) {
2448  default: return X86::COND_INVALID;
2449  case X86::COND_E:  return X86::COND_E;
2450  case X86::COND_NE: return X86::COND_NE;
2451  case X86::COND_L:  return X86::COND_G;
2452  case X86::COND_LE: return X86::COND_GE;
2453  case X86::COND_G:  return X86::COND_L;
2454  case X86::COND_GE: return X86::COND_LE;
2455  case X86::COND_B:  return X86::COND_A;
2456  case X86::COND_BE: return X86::COND_AE;
2457  case X86::COND_A:  return X86::COND_B;
2458  case X86::COND_AE: return X86::COND_BE;
2459  }
2460}
2461
2462/// getSETFromCond - Return a set opcode for the given condition and
2463/// whether it has memory operand.
2464static unsigned getSETFromCond(X86::CondCode CC,
2465                               bool HasMemoryOperand) {
2466  static const uint16_t Opc[16][2] = {
2467    { X86::SETAr,  X86::SETAm  },
2468    { X86::SETAEr, X86::SETAEm },
2469    { X86::SETBr,  X86::SETBm  },
2470    { X86::SETBEr, X86::SETBEm },
2471    { X86::SETEr,  X86::SETEm  },
2472    { X86::SETGr,  X86::SETGm  },
2473    { X86::SETGEr, X86::SETGEm },
2474    { X86::SETLr,  X86::SETLm  },
2475    { X86::SETLEr, X86::SETLEm },
2476    { X86::SETNEr, X86::SETNEm },
2477    { X86::SETNOr, X86::SETNOm },
2478    { X86::SETNPr, X86::SETNPm },
2479    { X86::SETNSr, X86::SETNSm },
2480    { X86::SETOr,  X86::SETOm  },
2481    { X86::SETPr,  X86::SETPm  },
2482    { X86::SETSr,  X86::SETSm  }
2483  };
2484
2485  assert(CC < 16 && "Can only handle standard cond codes");
2486  return Opc[CC][HasMemoryOperand ? 1 : 0];
2487}
2488
2489/// getCMovFromCond - Return a cmov opcode for the given condition,
2490/// register size in bytes, and operand type.
2491static unsigned getCMovFromCond(X86::CondCode CC, unsigned RegBytes,
2492                                bool HasMemoryOperand) {
2493  static const uint16_t Opc[32][3] = {
2494    { X86::CMOVA16rr,  X86::CMOVA32rr,  X86::CMOVA64rr  },
2495    { X86::CMOVAE16rr, X86::CMOVAE32rr, X86::CMOVAE64rr },
2496    { X86::CMOVB16rr,  X86::CMOVB32rr,  X86::CMOVB64rr  },
2497    { X86::CMOVBE16rr, X86::CMOVBE32rr, X86::CMOVBE64rr },
2498    { X86::CMOVE16rr,  X86::CMOVE32rr,  X86::CMOVE64rr  },
2499    { X86::CMOVG16rr,  X86::CMOVG32rr,  X86::CMOVG64rr  },
2500    { X86::CMOVGE16rr, X86::CMOVGE32rr, X86::CMOVGE64rr },
2501    { X86::CMOVL16rr,  X86::CMOVL32rr,  X86::CMOVL64rr  },
2502    { X86::CMOVLE16rr, X86::CMOVLE32rr, X86::CMOVLE64rr },
2503    { X86::CMOVNE16rr, X86::CMOVNE32rr, X86::CMOVNE64rr },
2504    { X86::CMOVNO16rr, X86::CMOVNO32rr, X86::CMOVNO64rr },
2505    { X86::CMOVNP16rr, X86::CMOVNP32rr, X86::CMOVNP64rr },
2506    { X86::CMOVNS16rr, X86::CMOVNS32rr, X86::CMOVNS64rr },
2507    { X86::CMOVO16rr,  X86::CMOVO32rr,  X86::CMOVO64rr  },
2508    { X86::CMOVP16rr,  X86::CMOVP32rr,  X86::CMOVP64rr  },
2509    { X86::CMOVS16rr,  X86::CMOVS32rr,  X86::CMOVS64rr  },
2510    { X86::CMOVA16rm,  X86::CMOVA32rm,  X86::CMOVA64rm  },
2511    { X86::CMOVAE16rm, X86::CMOVAE32rm, X86::CMOVAE64rm },
2512    { X86::CMOVB16rm,  X86::CMOVB32rm,  X86::CMOVB64rm  },
2513    { X86::CMOVBE16rm, X86::CMOVBE32rm, X86::CMOVBE64rm },
2514    { X86::CMOVE16rm,  X86::CMOVE32rm,  X86::CMOVE64rm  },
2515    { X86::CMOVG16rm,  X86::CMOVG32rm,  X86::CMOVG64rm  },
2516    { X86::CMOVGE16rm, X86::CMOVGE32rm, X86::CMOVGE64rm },
2517    { X86::CMOVL16rm,  X86::CMOVL32rm,  X86::CMOVL64rm  },
2518    { X86::CMOVLE16rm, X86::CMOVLE32rm, X86::CMOVLE64rm },
2519    { X86::CMOVNE16rm, X86::CMOVNE32rm, X86::CMOVNE64rm },
2520    { X86::CMOVNO16rm, X86::CMOVNO32rm, X86::CMOVNO64rm },
2521    { X86::CMOVNP16rm, X86::CMOVNP32rm, X86::CMOVNP64rm },
2522    { X86::CMOVNS16rm, X86::CMOVNS32rm, X86::CMOVNS64rm },
2523    { X86::CMOVO16rm,  X86::CMOVO32rm,  X86::CMOVO64rm  },
2524    { X86::CMOVP16rm,  X86::CMOVP32rm,  X86::CMOVP64rm  },
2525    { X86::CMOVS16rm,  X86::CMOVS32rm,  X86::CMOVS64rm  }
2526  };
2527
2528  assert(CC < 16 && "Can only handle standard cond codes");
2529  unsigned Idx = HasMemoryOperand ? 16+CC : CC;
2530  switch(RegBytes) {
2531  default: llvm_unreachable("Illegal register size!");
2532  case 2: return Opc[Idx][0];
2533  case 4: return Opc[Idx][1];
2534  case 8: return Opc[Idx][2];
2535  }
2536}
2537
2538bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
2539  if (!MI->isTerminator()) return false;
2540
2541  // Conditional branch is a special case.
2542  if (MI->isBranch() && !MI->isBarrier())
2543    return true;
2544  if (!MI->isPredicable())
2545    return true;
2546  return !isPredicated(MI);
2547}
2548
2549bool X86InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
2550                                 MachineBasicBlock *&TBB,
2551                                 MachineBasicBlock *&FBB,
2552                                 SmallVectorImpl<MachineOperand> &Cond,
2553                                 bool AllowModify) const {
2554  // Start from the bottom of the block and work up, examining the
2555  // terminator instructions.
2556  MachineBasicBlock::iterator I = MBB.end();
2557  MachineBasicBlock::iterator UnCondBrIter = MBB.end();
2558  while (I != MBB.begin()) {
2559    --I;
2560    if (I->isDebugValue())
2561      continue;
2562
2563    // Working from the bottom, when we see a non-terminator instruction, we're
2564    // done.
2565    if (!isUnpredicatedTerminator(I))
2566      break;
2567
2568    // A terminator that isn't a branch can't easily be handled by this
2569    // analysis.
2570    if (!I->isBranch())
2571      return true;
2572
2573    // Handle unconditional branches.
2574    if (I->getOpcode() == X86::JMP_4) {
2575      UnCondBrIter = I;
2576
2577      if (!AllowModify) {
2578        TBB = I->getOperand(0).getMBB();
2579        continue;
2580      }
2581
2582      // If the block has any instructions after a JMP, delete them.
2583      while (llvm::next(I) != MBB.end())
2584        llvm::next(I)->eraseFromParent();
2585
2586      Cond.clear();
2587      FBB = 0;
2588
2589      // Delete the JMP if it's equivalent to a fall-through.
2590      if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
2591        TBB = 0;
2592        I->eraseFromParent();
2593        I = MBB.end();
2594        UnCondBrIter = MBB.end();
2595        continue;
2596      }
2597
2598      // TBB is used to indicate the unconditional destination.
2599      TBB = I->getOperand(0).getMBB();
2600      continue;
2601    }
2602
2603    // Handle conditional branches.
2604    X86::CondCode BranchCode = getCondFromBranchOpc(I->getOpcode());
2605    if (BranchCode == X86::COND_INVALID)
2606      return true;  // Can't handle indirect branch.
2607
2608    // Working from the bottom, handle the first conditional branch.
2609    if (Cond.empty()) {
2610      MachineBasicBlock *TargetBB = I->getOperand(0).getMBB();
2611      if (AllowModify && UnCondBrIter != MBB.end() &&
2612          MBB.isLayoutSuccessor(TargetBB)) {
2613        // If we can modify the code and it ends in something like:
2614        //
2615        //     jCC L1
2616        //     jmp L2
2617        //   L1:
2618        //     ...
2619        //   L2:
2620        //
2621        // Then we can change this to:
2622        //
2623        //     jnCC L2
2624        //   L1:
2625        //     ...
2626        //   L2:
2627        //
2628        // Which is a bit more efficient.
2629        // We conditionally jump to the fall-through block.
2630        BranchCode = GetOppositeBranchCondition(BranchCode);
2631        unsigned JNCC = GetCondBranchFromCond(BranchCode);
2632        MachineBasicBlock::iterator OldInst = I;
2633
2634        BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(JNCC))
2635          .addMBB(UnCondBrIter->getOperand(0).getMBB());
2636        BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(X86::JMP_4))
2637          .addMBB(TargetBB);
2638
2639        OldInst->eraseFromParent();
2640        UnCondBrIter->eraseFromParent();
2641
2642        // Restart the analysis.
2643        UnCondBrIter = MBB.end();
2644        I = MBB.end();
2645        continue;
2646      }
2647
2648      FBB = TBB;
2649      TBB = I->getOperand(0).getMBB();
2650      Cond.push_back(MachineOperand::CreateImm(BranchCode));
2651      continue;
2652    }
2653
2654    // Handle subsequent conditional branches. Only handle the case where all
2655    // conditional branches branch to the same destination and their condition
2656    // opcodes fit one of the special multi-branch idioms.
2657    assert(Cond.size() == 1);
2658    assert(TBB);
2659
2660    // Only handle the case where all conditional branches branch to the same
2661    // destination.
2662    if (TBB != I->getOperand(0).getMBB())
2663      return true;
2664
2665    // If the conditions are the same, we can leave them alone.
2666    X86::CondCode OldBranchCode = (X86::CondCode)Cond[0].getImm();
2667    if (OldBranchCode == BranchCode)
2668      continue;
2669
2670    // If they differ, see if they fit one of the known patterns. Theoretically,
2671    // we could handle more patterns here, but we shouldn't expect to see them
2672    // if instruction selection has done a reasonable job.
2673    if ((OldBranchCode == X86::COND_NP &&
2674         BranchCode == X86::COND_E) ||
2675        (OldBranchCode == X86::COND_E &&
2676         BranchCode == X86::COND_NP))
2677      BranchCode = X86::COND_NP_OR_E;
2678    else if ((OldBranchCode == X86::COND_P &&
2679              BranchCode == X86::COND_NE) ||
2680             (OldBranchCode == X86::COND_NE &&
2681              BranchCode == X86::COND_P))
2682      BranchCode = X86::COND_NE_OR_P;
2683    else
2684      return true;
2685
2686    // Update the MachineOperand.
2687    Cond[0].setImm(BranchCode);
2688  }
2689
2690  return false;
2691}
2692
2693unsigned X86InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
2694  MachineBasicBlock::iterator I = MBB.end();
2695  unsigned Count = 0;
2696
2697  while (I != MBB.begin()) {
2698    --I;
2699    if (I->isDebugValue())
2700      continue;
2701    if (I->getOpcode() != X86::JMP_4 &&
2702        getCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID)
2703      break;
2704    // Remove the branch.
2705    I->eraseFromParent();
2706    I = MBB.end();
2707    ++Count;
2708  }
2709
2710  return Count;
2711}
2712
2713unsigned
2714X86InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
2715                           MachineBasicBlock *FBB,
2716                           const SmallVectorImpl<MachineOperand> &Cond,
2717                           DebugLoc DL) const {
2718  // Shouldn't be a fall through.
2719  assert(TBB && "InsertBranch must not be told to insert a fallthrough");
2720  assert((Cond.size() == 1 || Cond.size() == 0) &&
2721         "X86 branch conditions have one component!");
2722
2723  if (Cond.empty()) {
2724    // Unconditional branch?
2725    assert(!FBB && "Unconditional branch with multiple successors!");
2726    BuildMI(&MBB, DL, get(X86::JMP_4)).addMBB(TBB);
2727    return 1;
2728  }
2729
2730  // Conditional branch.
2731  unsigned Count = 0;
2732  X86::CondCode CC = (X86::CondCode)Cond[0].getImm();
2733  switch (CC) {
2734  case X86::COND_NP_OR_E:
2735    // Synthesize NP_OR_E with two branches.
2736    BuildMI(&MBB, DL, get(X86::JNP_4)).addMBB(TBB);
2737    ++Count;
2738    BuildMI(&MBB, DL, get(X86::JE_4)).addMBB(TBB);
2739    ++Count;
2740    break;
2741  case X86::COND_NE_OR_P:
2742    // Synthesize NE_OR_P with two branches.
2743    BuildMI(&MBB, DL, get(X86::JNE_4)).addMBB(TBB);
2744    ++Count;
2745    BuildMI(&MBB, DL, get(X86::JP_4)).addMBB(TBB);
2746    ++Count;
2747    break;
2748  default: {
2749    unsigned Opc = GetCondBranchFromCond(CC);
2750    BuildMI(&MBB, DL, get(Opc)).addMBB(TBB);
2751    ++Count;
2752  }
2753  }
2754  if (FBB) {
2755    // Two-way Conditional branch. Insert the second branch.
2756    BuildMI(&MBB, DL, get(X86::JMP_4)).addMBB(FBB);
2757    ++Count;
2758  }
2759  return Count;
2760}
2761
2762bool X86InstrInfo::
2763canInsertSelect(const MachineBasicBlock &MBB,
2764                const SmallVectorImpl<MachineOperand> &Cond,
2765                unsigned TrueReg, unsigned FalseReg,
2766                int &CondCycles, int &TrueCycles, int &FalseCycles) const {
2767  // Not all subtargets have cmov instructions.
2768  if (!TM.getSubtarget<X86Subtarget>().hasCMov())
2769    return false;
2770  if (Cond.size() != 1)
2771    return false;
2772  // We cannot do the composite conditions, at least not in SSA form.
2773  if ((X86::CondCode)Cond[0].getImm() > X86::COND_S)
2774    return false;
2775
2776  // Check register classes.
2777  const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
2778  const TargetRegisterClass *RC =
2779    RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
2780  if (!RC)
2781    return false;
2782
2783  // We have cmov instructions for 16, 32, and 64 bit general purpose registers.
2784  if (X86::GR16RegClass.hasSubClassEq(RC) ||
2785      X86::GR32RegClass.hasSubClassEq(RC) ||
2786      X86::GR64RegClass.hasSubClassEq(RC)) {
2787    // This latency applies to Pentium M, Merom, Wolfdale, Nehalem, and Sandy
2788    // Bridge. Probably Ivy Bridge as well.
2789    CondCycles = 2;
2790    TrueCycles = 2;
2791    FalseCycles = 2;
2792    return true;
2793  }
2794
2795  // Can't do vectors.
2796  return false;
2797}
2798
2799void X86InstrInfo::insertSelect(MachineBasicBlock &MBB,
2800                                MachineBasicBlock::iterator I, DebugLoc DL,
2801                                unsigned DstReg,
2802                                const SmallVectorImpl<MachineOperand> &Cond,
2803                                unsigned TrueReg, unsigned FalseReg) const {
2804   MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
2805   assert(Cond.size() == 1 && "Invalid Cond array");
2806   unsigned Opc = getCMovFromCond((X86::CondCode)Cond[0].getImm(),
2807                                  MRI.getRegClass(DstReg)->getSize(),
2808                                  false/*HasMemoryOperand*/);
2809   BuildMI(MBB, I, DL, get(Opc), DstReg).addReg(FalseReg).addReg(TrueReg);
2810}
2811
2812/// isHReg - Test if the given register is a physical h register.
2813static bool isHReg(unsigned Reg) {
2814  return X86::GR8_ABCD_HRegClass.contains(Reg);
2815}
2816
2817// Try and copy between VR128/VR64 and GR64 registers.
2818static unsigned CopyToFromAsymmetricReg(unsigned DestReg, unsigned SrcReg,
2819                                        bool HasAVX) {
2820  // SrcReg(VR128) -> DestReg(GR64)
2821  // SrcReg(VR64)  -> DestReg(GR64)
2822  // SrcReg(GR64)  -> DestReg(VR128)
2823  // SrcReg(GR64)  -> DestReg(VR64)
2824
2825  if (X86::GR64RegClass.contains(DestReg)) {
2826    if (X86::VR128RegClass.contains(SrcReg))
2827      // Copy from a VR128 register to a GR64 register.
2828      return HasAVX ? X86::VMOVPQIto64rr : X86::MOVPQIto64rr;
2829    if (X86::VR64RegClass.contains(SrcReg))
2830      // Copy from a VR64 register to a GR64 register.
2831      return X86::MOVSDto64rr;
2832  } else if (X86::GR64RegClass.contains(SrcReg)) {
2833    // Copy from a GR64 register to a VR128 register.
2834    if (X86::VR128RegClass.contains(DestReg))
2835      return HasAVX ? X86::VMOV64toPQIrr : X86::MOV64toPQIrr;
2836    // Copy from a GR64 register to a VR64 register.
2837    if (X86::VR64RegClass.contains(DestReg))
2838      return X86::MOV64toSDrr;
2839  }
2840
2841  // SrcReg(FR32) -> DestReg(GR32)
2842  // SrcReg(GR32) -> DestReg(FR32)
2843
2844  if (X86::GR32RegClass.contains(DestReg) && X86::FR32RegClass.contains(SrcReg))
2845    // Copy from a FR32 register to a GR32 register.
2846    return HasAVX ? X86::VMOVSS2DIrr : X86::MOVSS2DIrr;
2847
2848  if (X86::FR32RegClass.contains(DestReg) && X86::GR32RegClass.contains(SrcReg))
2849    // Copy from a GR32 register to a FR32 register.
2850    return HasAVX ? X86::VMOVDI2SSrr : X86::MOVDI2SSrr;
2851
2852  return 0;
2853}
2854
2855void X86InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
2856                               MachineBasicBlock::iterator MI, DebugLoc DL,
2857                               unsigned DestReg, unsigned SrcReg,
2858                               bool KillSrc) const {
2859  // First deal with the normal symmetric copies.
2860  bool HasAVX = TM.getSubtarget<X86Subtarget>().hasAVX();
2861  unsigned Opc;
2862  if (X86::GR64RegClass.contains(DestReg, SrcReg))
2863    Opc = X86::MOV64rr;
2864  else if (X86::GR32RegClass.contains(DestReg, SrcReg))
2865    Opc = X86::MOV32rr;
2866  else if (X86::GR16RegClass.contains(DestReg, SrcReg))
2867    Opc = X86::MOV16rr;
2868  else if (X86::GR8RegClass.contains(DestReg, SrcReg)) {
2869    // Copying to or from a physical H register on x86-64 requires a NOREX
2870    // move.  Otherwise use a normal move.
2871    if ((isHReg(DestReg) || isHReg(SrcReg)) &&
2872        TM.getSubtarget<X86Subtarget>().is64Bit()) {
2873      Opc = X86::MOV8rr_NOREX;
2874      // Both operands must be encodable without an REX prefix.
2875      assert(X86::GR8_NOREXRegClass.contains(SrcReg, DestReg) &&
2876             "8-bit H register can not be copied outside GR8_NOREX");
2877    } else
2878      Opc = X86::MOV8rr;
2879  } else if (X86::VR128RegClass.contains(DestReg, SrcReg))
2880    Opc = HasAVX ? X86::VMOVAPSrr : X86::MOVAPSrr;
2881  else if (X86::VR256RegClass.contains(DestReg, SrcReg))
2882    Opc = X86::VMOVAPSYrr;
2883  else if (X86::VR64RegClass.contains(DestReg, SrcReg))
2884    Opc = X86::MMX_MOVQ64rr;
2885  else
2886    Opc = CopyToFromAsymmetricReg(DestReg, SrcReg, HasAVX);
2887
2888  if (Opc) {
2889    BuildMI(MBB, MI, DL, get(Opc), DestReg)
2890      .addReg(SrcReg, getKillRegState(KillSrc));
2891    return;
2892  }
2893
2894  // Moving EFLAGS to / from another register requires a push and a pop.
2895  if (SrcReg == X86::EFLAGS) {
2896    if (X86::GR64RegClass.contains(DestReg)) {
2897      BuildMI(MBB, MI, DL, get(X86::PUSHF64));
2898      BuildMI(MBB, MI, DL, get(X86::POP64r), DestReg);
2899      return;
2900    }
2901    if (X86::GR32RegClass.contains(DestReg)) {
2902      BuildMI(MBB, MI, DL, get(X86::PUSHF32));
2903      BuildMI(MBB, MI, DL, get(X86::POP32r), DestReg);
2904      return;
2905    }
2906  }
2907  if (DestReg == X86::EFLAGS) {
2908    if (X86::GR64RegClass.contains(SrcReg)) {
2909      BuildMI(MBB, MI, DL, get(X86::PUSH64r))
2910        .addReg(SrcReg, getKillRegState(KillSrc));
2911      BuildMI(MBB, MI, DL, get(X86::POPF64));
2912      return;
2913    }
2914    if (X86::GR32RegClass.contains(SrcReg)) {
2915      BuildMI(MBB, MI, DL, get(X86::PUSH32r))
2916        .addReg(SrcReg, getKillRegState(KillSrc));
2917      BuildMI(MBB, MI, DL, get(X86::POPF32));
2918      return;
2919    }
2920  }
2921
2922  DEBUG(dbgs() << "Cannot copy " << RI.getName(SrcReg)
2923               << " to " << RI.getName(DestReg) << '\n');
2924  llvm_unreachable("Cannot emit physreg copy instruction");
2925}
2926
2927static unsigned getLoadStoreRegOpcode(unsigned Reg,
2928                                      const TargetRegisterClass *RC,
2929                                      bool isStackAligned,
2930                                      const TargetMachine &TM,
2931                                      bool load) {
2932  bool HasAVX = TM.getSubtarget<X86Subtarget>().hasAVX();
2933  switch (RC->getSize()) {
2934  default:
2935    llvm_unreachable("Unknown spill size");
2936  case 1:
2937    assert(X86::GR8RegClass.hasSubClassEq(RC) && "Unknown 1-byte regclass");
2938    if (TM.getSubtarget<X86Subtarget>().is64Bit())
2939      // Copying to or from a physical H register on x86-64 requires a NOREX
2940      // move.  Otherwise use a normal move.
2941      if (isHReg(Reg) || X86::GR8_ABCD_HRegClass.hasSubClassEq(RC))
2942        return load ? X86::MOV8rm_NOREX : X86::MOV8mr_NOREX;
2943    return load ? X86::MOV8rm : X86::MOV8mr;
2944  case 2:
2945    assert(X86::GR16RegClass.hasSubClassEq(RC) && "Unknown 2-byte regclass");
2946    return load ? X86::MOV16rm : X86::MOV16mr;
2947  case 4:
2948    if (X86::GR32RegClass.hasSubClassEq(RC))
2949      return load ? X86::MOV32rm : X86::MOV32mr;
2950    if (X86::FR32RegClass.hasSubClassEq(RC))
2951      return load ?
2952        (HasAVX ? X86::VMOVSSrm : X86::MOVSSrm) :
2953        (HasAVX ? X86::VMOVSSmr : X86::MOVSSmr);
2954    if (X86::RFP32RegClass.hasSubClassEq(RC))
2955      return load ? X86::LD_Fp32m : X86::ST_Fp32m;
2956    llvm_unreachable("Unknown 4-byte regclass");
2957  case 8:
2958    if (X86::GR64RegClass.hasSubClassEq(RC))
2959      return load ? X86::MOV64rm : X86::MOV64mr;
2960    if (X86::FR64RegClass.hasSubClassEq(RC))
2961      return load ?
2962        (HasAVX ? X86::VMOVSDrm : X86::MOVSDrm) :
2963        (HasAVX ? X86::VMOVSDmr : X86::MOVSDmr);
2964    if (X86::VR64RegClass.hasSubClassEq(RC))
2965      return load ? X86::MMX_MOVQ64rm : X86::MMX_MOVQ64mr;
2966    if (X86::RFP64RegClass.hasSubClassEq(RC))
2967      return load ? X86::LD_Fp64m : X86::ST_Fp64m;
2968    llvm_unreachable("Unknown 8-byte regclass");
2969  case 10:
2970    assert(X86::RFP80RegClass.hasSubClassEq(RC) && "Unknown 10-byte regclass");
2971    return load ? X86::LD_Fp80m : X86::ST_FpP80m;
2972  case 16: {
2973    assert(X86::VR128RegClass.hasSubClassEq(RC) && "Unknown 16-byte regclass");
2974    // If stack is realigned we can use aligned stores.
2975    if (isStackAligned)
2976      return load ?
2977        (HasAVX ? X86::VMOVAPSrm : X86::MOVAPSrm) :
2978        (HasAVX ? X86::VMOVAPSmr : X86::MOVAPSmr);
2979    else
2980      return load ?
2981        (HasAVX ? X86::VMOVUPSrm : X86::MOVUPSrm) :
2982        (HasAVX ? X86::VMOVUPSmr : X86::MOVUPSmr);
2983  }
2984  case 32:
2985    assert(X86::VR256RegClass.hasSubClassEq(RC) && "Unknown 32-byte regclass");
2986    // If stack is realigned we can use aligned stores.
2987    if (isStackAligned)
2988      return load ? X86::VMOVAPSYrm : X86::VMOVAPSYmr;
2989    else
2990      return load ? X86::VMOVUPSYrm : X86::VMOVUPSYmr;
2991  }
2992}
2993
2994static unsigned getStoreRegOpcode(unsigned SrcReg,
2995                                  const TargetRegisterClass *RC,
2996                                  bool isStackAligned,
2997                                  TargetMachine &TM) {
2998  return getLoadStoreRegOpcode(SrcReg, RC, isStackAligned, TM, false);
2999}
3000
3001
3002static unsigned getLoadRegOpcode(unsigned DestReg,
3003                                 const TargetRegisterClass *RC,
3004                                 bool isStackAligned,
3005                                 const TargetMachine &TM) {
3006  return getLoadStoreRegOpcode(DestReg, RC, isStackAligned, TM, true);
3007}
3008
3009void X86InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
3010                                       MachineBasicBlock::iterator MI,
3011                                       unsigned SrcReg, bool isKill, int FrameIdx,
3012                                       const TargetRegisterClass *RC,
3013                                       const TargetRegisterInfo *TRI) const {
3014  const MachineFunction &MF = *MBB.getParent();
3015  assert(MF.getFrameInfo()->getObjectSize(FrameIdx) >= RC->getSize() &&
3016         "Stack slot too small for store");
3017  unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
3018  bool isAligned = (TM.getFrameLowering()->getStackAlignment() >= Alignment) ||
3019    RI.canRealignStack(MF);
3020  unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, TM);
3021  DebugLoc DL = MBB.findDebugLoc(MI);
3022  addFrameReference(BuildMI(MBB, MI, DL, get(Opc)), FrameIdx)
3023    .addReg(SrcReg, getKillRegState(isKill));
3024}
3025
3026void X86InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
3027                                  bool isKill,
3028                                  SmallVectorImpl<MachineOperand> &Addr,
3029                                  const TargetRegisterClass *RC,
3030                                  MachineInstr::mmo_iterator MMOBegin,
3031                                  MachineInstr::mmo_iterator MMOEnd,
3032                                  SmallVectorImpl<MachineInstr*> &NewMIs) const {
3033  unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
3034  bool isAligned = MMOBegin != MMOEnd &&
3035                   (*MMOBegin)->getAlignment() >= Alignment;
3036  unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, TM);
3037  DebugLoc DL;
3038  MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc));
3039  for (unsigned i = 0, e = Addr.size(); i != e; ++i)
3040    MIB.addOperand(Addr[i]);
3041  MIB.addReg(SrcReg, getKillRegState(isKill));
3042  (*MIB).setMemRefs(MMOBegin, MMOEnd);
3043  NewMIs.push_back(MIB);
3044}
3045
3046
3047void X86InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
3048                                        MachineBasicBlock::iterator MI,
3049                                        unsigned DestReg, int FrameIdx,
3050                                        const TargetRegisterClass *RC,
3051                                        const TargetRegisterInfo *TRI) const {
3052  const MachineFunction &MF = *MBB.getParent();
3053  unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
3054  bool isAligned = (TM.getFrameLowering()->getStackAlignment() >= Alignment) ||
3055    RI.canRealignStack(MF);
3056  unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, TM);
3057  DebugLoc DL = MBB.findDebugLoc(MI);
3058  addFrameReference(BuildMI(MBB, MI, DL, get(Opc), DestReg), FrameIdx);
3059}
3060
3061void X86InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
3062                                 SmallVectorImpl<MachineOperand> &Addr,
3063                                 const TargetRegisterClass *RC,
3064                                 MachineInstr::mmo_iterator MMOBegin,
3065                                 MachineInstr::mmo_iterator MMOEnd,
3066                                 SmallVectorImpl<MachineInstr*> &NewMIs) const {
3067  unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
3068  bool isAligned = MMOBegin != MMOEnd &&
3069                   (*MMOBegin)->getAlignment() >= Alignment;
3070  unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, TM);
3071  DebugLoc DL;
3072  MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
3073  for (unsigned i = 0, e = Addr.size(); i != e; ++i)
3074    MIB.addOperand(Addr[i]);
3075  (*MIB).setMemRefs(MMOBegin, MMOEnd);
3076  NewMIs.push_back(MIB);
3077}
3078
3079bool X86InstrInfo::
3080analyzeCompare(const MachineInstr *MI, unsigned &SrcReg, unsigned &SrcReg2,
3081               int &CmpMask, int &CmpValue) const {
3082  switch (MI->getOpcode()) {
3083  default: break;
3084  case X86::CMP64ri32:
3085  case X86::CMP64ri8:
3086  case X86::CMP32ri:
3087  case X86::CMP32ri8:
3088  case X86::CMP16ri:
3089  case X86::CMP16ri8:
3090  case X86::CMP8ri:
3091    SrcReg = MI->getOperand(0).getReg();
3092    SrcReg2 = 0;
3093    CmpMask = ~0;
3094    CmpValue = MI->getOperand(1).getImm();
3095    return true;
3096  // A SUB can be used to perform comparison.
3097  case X86::SUB64rm:
3098  case X86::SUB32rm:
3099  case X86::SUB16rm:
3100  case X86::SUB8rm:
3101    SrcReg = MI->getOperand(1).getReg();
3102    SrcReg2 = 0;
3103    CmpMask = ~0;
3104    CmpValue = 0;
3105    return true;
3106  case X86::SUB64rr:
3107  case X86::SUB32rr:
3108  case X86::SUB16rr:
3109  case X86::SUB8rr:
3110    SrcReg = MI->getOperand(1).getReg();
3111    SrcReg2 = MI->getOperand(2).getReg();
3112    CmpMask = ~0;
3113    CmpValue = 0;
3114    return true;
3115  case X86::SUB64ri32:
3116  case X86::SUB64ri8:
3117  case X86::SUB32ri:
3118  case X86::SUB32ri8:
3119  case X86::SUB16ri:
3120  case X86::SUB16ri8:
3121  case X86::SUB8ri:
3122    SrcReg = MI->getOperand(1).getReg();
3123    SrcReg2 = 0;
3124    CmpMask = ~0;
3125    CmpValue = MI->getOperand(2).getImm();
3126    return true;
3127  case X86::CMP64rr:
3128  case X86::CMP32rr:
3129  case X86::CMP16rr:
3130  case X86::CMP8rr:
3131    SrcReg = MI->getOperand(0).getReg();
3132    SrcReg2 = MI->getOperand(1).getReg();
3133    CmpMask = ~0;
3134    CmpValue = 0;
3135    return true;
3136  case X86::TEST8rr:
3137  case X86::TEST16rr:
3138  case X86::TEST32rr:
3139  case X86::TEST64rr:
3140    SrcReg = MI->getOperand(0).getReg();
3141    if (MI->getOperand(1).getReg() != SrcReg) return false;
3142    // Compare against zero.
3143    SrcReg2 = 0;
3144    CmpMask = ~0;
3145    CmpValue = 0;
3146    return true;
3147  }
3148  return false;
3149}
3150
3151/// isRedundantFlagInstr - check whether the first instruction, whose only
3152/// purpose is to update flags, can be made redundant.
3153/// CMPrr can be made redundant by SUBrr if the operands are the same.
3154/// This function can be extended later on.
3155/// SrcReg, SrcRegs: register operands for FlagI.
3156/// ImmValue: immediate for FlagI if it takes an immediate.
3157inline static bool isRedundantFlagInstr(MachineInstr *FlagI, unsigned SrcReg,
3158                                        unsigned SrcReg2, int ImmValue,
3159                                        MachineInstr *OI) {
3160  if (((FlagI->getOpcode() == X86::CMP64rr &&
3161        OI->getOpcode() == X86::SUB64rr) ||
3162       (FlagI->getOpcode() == X86::CMP32rr &&
3163        OI->getOpcode() == X86::SUB32rr)||
3164       (FlagI->getOpcode() == X86::CMP16rr &&
3165        OI->getOpcode() == X86::SUB16rr)||
3166       (FlagI->getOpcode() == X86::CMP8rr &&
3167        OI->getOpcode() == X86::SUB8rr)) &&
3168      ((OI->getOperand(1).getReg() == SrcReg &&
3169        OI->getOperand(2).getReg() == SrcReg2) ||
3170       (OI->getOperand(1).getReg() == SrcReg2 &&
3171        OI->getOperand(2).getReg() == SrcReg)))
3172    return true;
3173
3174  if (((FlagI->getOpcode() == X86::CMP64ri32 &&
3175        OI->getOpcode() == X86::SUB64ri32) ||
3176       (FlagI->getOpcode() == X86::CMP64ri8 &&
3177        OI->getOpcode() == X86::SUB64ri8) ||
3178       (FlagI->getOpcode() == X86::CMP32ri &&
3179        OI->getOpcode() == X86::SUB32ri) ||
3180       (FlagI->getOpcode() == X86::CMP32ri8 &&
3181        OI->getOpcode() == X86::SUB32ri8) ||
3182       (FlagI->getOpcode() == X86::CMP16ri &&
3183        OI->getOpcode() == X86::SUB16ri) ||
3184       (FlagI->getOpcode() == X86::CMP16ri8 &&
3185        OI->getOpcode() == X86::SUB16ri8) ||
3186       (FlagI->getOpcode() == X86::CMP8ri &&
3187        OI->getOpcode() == X86::SUB8ri)) &&
3188      OI->getOperand(1).getReg() == SrcReg &&
3189      OI->getOperand(2).getImm() == ImmValue)
3190    return true;
3191  return false;
3192}
3193
3194/// isDefConvertible - check whether the definition can be converted
3195/// to remove a comparison against zero.
3196inline static bool isDefConvertible(MachineInstr *MI) {
3197  switch (MI->getOpcode()) {
3198  default: return false;
3199  case X86::SUB64ri32: case X86::SUB64ri8: case X86::SUB32ri:
3200  case X86::SUB32ri8:  case X86::SUB16ri:  case X86::SUB16ri8:
3201  case X86::SUB8ri:    case X86::SUB64rr:  case X86::SUB32rr:
3202  case X86::SUB16rr:   case X86::SUB8rr:   case X86::SUB64rm:
3203  case X86::SUB32rm:   case X86::SUB16rm:  case X86::SUB8rm:
3204  case X86::DEC64r:    case X86::DEC32r:   case X86::DEC16r: case X86::DEC8r:
3205  case X86::DEC64_32r: case X86::DEC64_16r:
3206  case X86::ADD64ri32: case X86::ADD64ri8: case X86::ADD32ri:
3207  case X86::ADD32ri8:  case X86::ADD16ri:  case X86::ADD16ri8:
3208  case X86::ADD8ri:    case X86::ADD64rr:  case X86::ADD32rr:
3209  case X86::ADD16rr:   case X86::ADD8rr:   case X86::ADD64rm:
3210  case X86::ADD32rm:   case X86::ADD16rm:  case X86::ADD8rm:
3211  case X86::INC64r:    case X86::INC32r:   case X86::INC16r: case X86::INC8r:
3212  case X86::INC64_32r: case X86::INC64_16r:
3213  case X86::AND64ri32: case X86::AND64ri8: case X86::AND32ri:
3214  case X86::AND32ri8:  case X86::AND16ri:  case X86::AND16ri8:
3215  case X86::AND8ri:    case X86::AND64rr:  case X86::AND32rr:
3216  case X86::AND16rr:   case X86::AND8rr:   case X86::AND64rm:
3217  case X86::AND32rm:   case X86::AND16rm:  case X86::AND8rm:
3218  case X86::XOR64ri32: case X86::XOR64ri8: case X86::XOR32ri:
3219  case X86::XOR32ri8:  case X86::XOR16ri:  case X86::XOR16ri8:
3220  case X86::XOR8ri:    case X86::XOR64rr:  case X86::XOR32rr:
3221  case X86::XOR16rr:   case X86::XOR8rr:   case X86::XOR64rm:
3222  case X86::XOR32rm:   case X86::XOR16rm:  case X86::XOR8rm:
3223  case X86::OR64ri32:  case X86::OR64ri8:  case X86::OR32ri:
3224  case X86::OR32ri8:   case X86::OR16ri:   case X86::OR16ri8:
3225  case X86::OR8ri:     case X86::OR64rr:   case X86::OR32rr:
3226  case X86::OR16rr:    case X86::OR8rr:    case X86::OR64rm:
3227  case X86::OR32rm:    case X86::OR16rm:   case X86::OR8rm:
3228  case X86::ANDN32rr:  case X86::ANDN32rm:
3229  case X86::ANDN64rr:  case X86::ANDN64rm:
3230    return true;
3231  }
3232}
3233
3234/// optimizeCompareInstr - Check if there exists an earlier instruction that
3235/// operates on the same source operands and sets flags in the same way as
3236/// Compare; remove Compare if possible.
3237bool X86InstrInfo::
3238optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, unsigned SrcReg2,
3239                     int CmpMask, int CmpValue,
3240                     const MachineRegisterInfo *MRI) const {
3241  // Check whether we can replace SUB with CMP.
3242  unsigned NewOpcode = 0;
3243  switch (CmpInstr->getOpcode()) {
3244  default: break;
3245  case X86::SUB64ri32:
3246  case X86::SUB64ri8:
3247  case X86::SUB32ri:
3248  case X86::SUB32ri8:
3249  case X86::SUB16ri:
3250  case X86::SUB16ri8:
3251  case X86::SUB8ri:
3252  case X86::SUB64rm:
3253  case X86::SUB32rm:
3254  case X86::SUB16rm:
3255  case X86::SUB8rm:
3256  case X86::SUB64rr:
3257  case X86::SUB32rr:
3258  case X86::SUB16rr:
3259  case X86::SUB8rr: {
3260    if (!MRI->use_nodbg_empty(CmpInstr->getOperand(0).getReg()))
3261      return false;
3262    // There is no use of the destination register, we can replace SUB with CMP.
3263    switch (CmpInstr->getOpcode()) {
3264    default: llvm_unreachable("Unreachable!");
3265    case X86::SUB64rm:   NewOpcode = X86::CMP64rm;   break;
3266    case X86::SUB32rm:   NewOpcode = X86::CMP32rm;   break;
3267    case X86::SUB16rm:   NewOpcode = X86::CMP16rm;   break;
3268    case X86::SUB8rm:    NewOpcode = X86::CMP8rm;    break;
3269    case X86::SUB64rr:   NewOpcode = X86::CMP64rr;   break;
3270    case X86::SUB32rr:   NewOpcode = X86::CMP32rr;   break;
3271    case X86::SUB16rr:   NewOpcode = X86::CMP16rr;   break;
3272    case X86::SUB8rr:    NewOpcode = X86::CMP8rr;    break;
3273    case X86::SUB64ri32: NewOpcode = X86::CMP64ri32; break;
3274    case X86::SUB64ri8:  NewOpcode = X86::CMP64ri8;  break;
3275    case X86::SUB32ri:   NewOpcode = X86::CMP32ri;   break;
3276    case X86::SUB32ri8:  NewOpcode = X86::CMP32ri8;  break;
3277    case X86::SUB16ri:   NewOpcode = X86::CMP16ri;   break;
3278    case X86::SUB16ri8:  NewOpcode = X86::CMP16ri8;  break;
3279    case X86::SUB8ri:    NewOpcode = X86::CMP8ri;    break;
3280    }
3281    CmpInstr->setDesc(get(NewOpcode));
3282    CmpInstr->RemoveOperand(0);
3283    // Fall through to optimize Cmp if Cmp is CMPrr or CMPri.
3284    if (NewOpcode == X86::CMP64rm || NewOpcode == X86::CMP32rm ||
3285        NewOpcode == X86::CMP16rm || NewOpcode == X86::CMP8rm)
3286      return false;
3287  }
3288  }
3289
3290  // Get the unique definition of SrcReg.
3291  MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
3292  if (!MI) return false;
3293
3294  // CmpInstr is the first instruction of the BB.
3295  MachineBasicBlock::iterator I = CmpInstr, Def = MI;
3296
3297  // If we are comparing against zero, check whether we can use MI to update
3298  // EFLAGS. If MI is not in the same BB as CmpInstr, do not optimize.
3299  bool IsCmpZero = (SrcReg2 == 0 && CmpValue == 0);
3300  if (IsCmpZero && (MI->getParent() != CmpInstr->getParent() ||
3301      !isDefConvertible(MI)))
3302    return false;
3303
3304  // We are searching for an earlier instruction that can make CmpInstr
3305  // redundant and that instruction will be saved in Sub.
3306  MachineInstr *Sub = NULL;
3307  const TargetRegisterInfo *TRI = &getRegisterInfo();
3308
3309  // We iterate backward, starting from the instruction before CmpInstr and
3310  // stop when reaching the definition of a source register or done with the BB.
3311  // RI points to the instruction before CmpInstr.
3312  // If the definition is in this basic block, RE points to the definition;
3313  // otherwise, RE is the rend of the basic block.
3314  MachineBasicBlock::reverse_iterator
3315      RI = MachineBasicBlock::reverse_iterator(I),
3316      RE = CmpInstr->getParent() == MI->getParent() ?
3317           MachineBasicBlock::reverse_iterator(++Def) /* points to MI */ :
3318           CmpInstr->getParent()->rend();
3319  MachineInstr *Movr0Inst = 0;
3320  for (; RI != RE; ++RI) {
3321    MachineInstr *Instr = &*RI;
3322    // Check whether CmpInstr can be made redundant by the current instruction.
3323    if (!IsCmpZero &&
3324        isRedundantFlagInstr(CmpInstr, SrcReg, SrcReg2, CmpValue, Instr)) {
3325      Sub = Instr;
3326      break;
3327    }
3328
3329    if (Instr->modifiesRegister(X86::EFLAGS, TRI) ||
3330        Instr->readsRegister(X86::EFLAGS, TRI)) {
3331      // This instruction modifies or uses EFLAGS.
3332
3333      // MOV32r0 etc. are implemented with xor which clobbers condition code.
3334      // They are safe to move up, if the definition to EFLAGS is dead and
3335      // earlier instructions do not read or write EFLAGS.
3336      if (!Movr0Inst && (Instr->getOpcode() == X86::MOV8r0 ||
3337           Instr->getOpcode() == X86::MOV16r0 ||
3338           Instr->getOpcode() == X86::MOV32r0 ||
3339           Instr->getOpcode() == X86::MOV64r0) &&
3340          Instr->registerDefIsDead(X86::EFLAGS, TRI)) {
3341        Movr0Inst = Instr;
3342        continue;
3343      }
3344
3345      // We can't remove CmpInstr.
3346      return false;
3347    }
3348  }
3349
3350  // Return false if no candidates exist.
3351  if (!IsCmpZero && !Sub)
3352    return false;
3353
3354  bool IsSwapped = (SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 &&
3355                    Sub->getOperand(2).getReg() == SrcReg);
3356
3357  // Scan forward from the instruction after CmpInstr for uses of EFLAGS.
3358  // It is safe to remove CmpInstr if EFLAGS is redefined or killed.
3359  // If we are done with the basic block, we need to check whether EFLAGS is
3360  // live-out.
3361  bool IsSafe = false;
3362  SmallVector<std::pair<MachineInstr*, unsigned /*NewOpc*/>, 4> OpsToUpdate;
3363  MachineBasicBlock::iterator E = CmpInstr->getParent()->end();
3364  for (++I; I != E; ++I) {
3365    const MachineInstr &Instr = *I;
3366    bool ModifyEFLAGS = Instr.modifiesRegister(X86::EFLAGS, TRI);
3367    bool UseEFLAGS = Instr.readsRegister(X86::EFLAGS, TRI);
3368    // We should check the usage if this instruction uses and updates EFLAGS.
3369    if (!UseEFLAGS && ModifyEFLAGS) {
3370      // It is safe to remove CmpInstr if EFLAGS is updated again.
3371      IsSafe = true;
3372      break;
3373    }
3374    if (!UseEFLAGS && !ModifyEFLAGS)
3375      continue;
3376
3377    // EFLAGS is used by this instruction.
3378    X86::CondCode OldCC;
3379    bool OpcIsSET = false;
3380    if (IsCmpZero || IsSwapped) {
3381      // We decode the condition code from opcode.
3382      if (Instr.isBranch())
3383        OldCC = getCondFromBranchOpc(Instr.getOpcode());
3384      else {
3385        OldCC = getCondFromSETOpc(Instr.getOpcode());
3386        if (OldCC != X86::COND_INVALID)
3387          OpcIsSET = true;
3388        else
3389          OldCC = X86::getCondFromCMovOpc(Instr.getOpcode());
3390      }
3391      if (OldCC == X86::COND_INVALID) return false;
3392    }
3393    if (IsCmpZero) {
3394      switch (OldCC) {
3395      default: break;
3396      case X86::COND_A: case X86::COND_AE:
3397      case X86::COND_B: case X86::COND_BE:
3398      case X86::COND_G: case X86::COND_GE:
3399      case X86::COND_L: case X86::COND_LE:
3400      case X86::COND_O: case X86::COND_NO:
3401        // CF and OF are used, we can't perform this optimization.
3402        return false;
3403      }
3404    } else if (IsSwapped) {
3405      // If we have SUB(r1, r2) and CMP(r2, r1), the condition code needs
3406      // to be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc.
3407      // We swap the condition code and synthesize the new opcode.
3408      X86::CondCode NewCC = getSwappedCondition(OldCC);
3409      if (NewCC == X86::COND_INVALID) return false;
3410
3411      // Synthesize the new opcode.
3412      bool HasMemoryOperand = Instr.hasOneMemOperand();
3413      unsigned NewOpc;
3414      if (Instr.isBranch())
3415        NewOpc = GetCondBranchFromCond(NewCC);
3416      else if(OpcIsSET)
3417        NewOpc = getSETFromCond(NewCC, HasMemoryOperand);
3418      else {
3419        unsigned DstReg = Instr.getOperand(0).getReg();
3420        NewOpc = getCMovFromCond(NewCC, MRI->getRegClass(DstReg)->getSize(),
3421                                 HasMemoryOperand);
3422      }
3423
3424      // Push the MachineInstr to OpsToUpdate.
3425      // If it is safe to remove CmpInstr, the condition code of these
3426      // instructions will be modified.
3427      OpsToUpdate.push_back(std::make_pair(&*I, NewOpc));
3428    }
3429    if (ModifyEFLAGS || Instr.killsRegister(X86::EFLAGS, TRI)) {
3430      // It is safe to remove CmpInstr if EFLAGS is updated again or killed.
3431      IsSafe = true;
3432      break;
3433    }
3434  }
3435
3436  // If EFLAGS is not killed nor re-defined, we should check whether it is
3437  // live-out. If it is live-out, do not optimize.
3438  if ((IsCmpZero || IsSwapped) && !IsSafe) {
3439    MachineBasicBlock *MBB = CmpInstr->getParent();
3440    for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(),
3441             SE = MBB->succ_end(); SI != SE; ++SI)
3442      if ((*SI)->isLiveIn(X86::EFLAGS))
3443        return false;
3444  }
3445
3446  // The instruction to be updated is either Sub or MI.
3447  Sub = IsCmpZero ? MI : Sub;
3448  // Move Movr0Inst to the place right before Sub.
3449  if (Movr0Inst) {
3450    Sub->getParent()->remove(Movr0Inst);
3451    Sub->getParent()->insert(MachineBasicBlock::iterator(Sub), Movr0Inst);
3452  }
3453
3454  // Make sure Sub instruction defines EFLAGS and mark the def live.
3455  unsigned LastOperand = Sub->getNumOperands() - 1;
3456  assert(Sub->getNumOperands() >= 2 &&
3457         Sub->getOperand(LastOperand).isReg() &&
3458         Sub->getOperand(LastOperand).getReg() == X86::EFLAGS &&
3459         "EFLAGS should be the last operand of SUB, ADD, OR, XOR, AND");
3460  Sub->getOperand(LastOperand).setIsDef(true);
3461  Sub->getOperand(LastOperand).setIsDead(false);
3462  CmpInstr->eraseFromParent();
3463
3464  // Modify the condition code of instructions in OpsToUpdate.
3465  for (unsigned i = 0, e = OpsToUpdate.size(); i < e; i++)
3466    OpsToUpdate[i].first->setDesc(get(OpsToUpdate[i].second));
3467  return true;
3468}
3469
3470/// optimizeLoadInstr - Try to remove the load by folding it to a register
3471/// operand at the use. We fold the load instructions if load defines a virtual
3472/// register, the virtual register is used once in the same BB, and the
3473/// instructions in-between do not load or store, and have no side effects.
3474MachineInstr* X86InstrInfo::
3475optimizeLoadInstr(MachineInstr *MI, const MachineRegisterInfo *MRI,
3476                  unsigned &FoldAsLoadDefReg,
3477                  MachineInstr *&DefMI) const {
3478  if (FoldAsLoadDefReg == 0)
3479    return 0;
3480  // To be conservative, if there exists another load, clear the load candidate.
3481  if (MI->mayLoad()) {
3482    FoldAsLoadDefReg = 0;
3483    return 0;
3484  }
3485
3486  // Check whether we can move DefMI here.
3487  DefMI = MRI->getVRegDef(FoldAsLoadDefReg);
3488  assert(DefMI);
3489  bool SawStore = false;
3490  if (!DefMI->isSafeToMove(this, 0, SawStore))
3491    return 0;
3492
3493  // We try to commute MI if possible.
3494  unsigned IdxEnd = (MI->isCommutable()) ? 2 : 1;
3495  for (unsigned Idx = 0; Idx < IdxEnd; Idx++) {
3496    // Collect information about virtual register operands of MI.
3497    unsigned SrcOperandId = 0;
3498    bool FoundSrcOperand = false;
3499    for (unsigned i = 0, e = MI->getDesc().getNumOperands(); i != e; ++i) {
3500      MachineOperand &MO = MI->getOperand(i);
3501      if (!MO.isReg())
3502        continue;
3503      unsigned Reg = MO.getReg();
3504      if (Reg != FoldAsLoadDefReg)
3505        continue;
3506      // Do not fold if we have a subreg use or a def or multiple uses.
3507      if (MO.getSubReg() || MO.isDef() || FoundSrcOperand)
3508        return 0;
3509
3510      SrcOperandId = i;
3511      FoundSrcOperand = true;
3512    }
3513    if (!FoundSrcOperand) return 0;
3514
3515    // Check whether we can fold the def into SrcOperandId.
3516    SmallVector<unsigned, 8> Ops;
3517    Ops.push_back(SrcOperandId);
3518    MachineInstr *FoldMI = foldMemoryOperand(MI, Ops, DefMI);
3519    if (FoldMI) {
3520      FoldAsLoadDefReg = 0;
3521      return FoldMI;
3522    }
3523
3524    if (Idx == 1) {
3525      // MI was changed but it didn't help, commute it back!
3526      commuteInstruction(MI, false);
3527      return 0;
3528    }
3529
3530    // Check whether we can commute MI and enable folding.
3531    if (MI->isCommutable()) {
3532      MachineInstr *NewMI = commuteInstruction(MI, false);
3533      // Unable to commute.
3534      if (!NewMI) return 0;
3535      if (NewMI != MI) {
3536        // New instruction. It doesn't need to be kept.
3537        NewMI->eraseFromParent();
3538        return 0;
3539      }
3540    }
3541  }
3542  return 0;
3543}
3544
3545/// Expand2AddrUndef - Expand a single-def pseudo instruction to a two-addr
3546/// instruction with two undef reads of the register being defined.  This is
3547/// used for mapping:
3548///   %xmm4 = V_SET0
3549/// to:
3550///   %xmm4 = PXORrr %xmm4<undef>, %xmm4<undef>
3551///
3552static bool Expand2AddrUndef(MachineInstrBuilder &MIB,
3553                             const MCInstrDesc &Desc) {
3554  assert(Desc.getNumOperands() == 3 && "Expected two-addr instruction.");
3555  unsigned Reg = MIB->getOperand(0).getReg();
3556  MIB->setDesc(Desc);
3557
3558  // MachineInstr::addOperand() will insert explicit operands before any
3559  // implicit operands.
3560  MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
3561  // But we don't trust that.
3562  assert(MIB->getOperand(1).getReg() == Reg &&
3563         MIB->getOperand(2).getReg() == Reg && "Misplaced operand");
3564  return true;
3565}
3566
3567bool X86InstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
3568  bool HasAVX = TM.getSubtarget<X86Subtarget>().hasAVX();
3569  MachineInstrBuilder MIB(*MI->getParent()->getParent(), MI);
3570  switch (MI->getOpcode()) {
3571  case X86::SETB_C8r:
3572    return Expand2AddrUndef(MIB, get(X86::SBB8rr));
3573  case X86::SETB_C16r:
3574    return Expand2AddrUndef(MIB, get(X86::SBB16rr));
3575  case X86::SETB_C32r:
3576    return Expand2AddrUndef(MIB, get(X86::SBB32rr));
3577  case X86::SETB_C64r:
3578    return Expand2AddrUndef(MIB, get(X86::SBB64rr));
3579  case X86::V_SET0:
3580  case X86::FsFLD0SS:
3581  case X86::FsFLD0SD:
3582    return Expand2AddrUndef(MIB, get(HasAVX ? X86::VXORPSrr : X86::XORPSrr));
3583  case X86::AVX_SET0:
3584    assert(HasAVX && "AVX not supported");
3585    return Expand2AddrUndef(MIB, get(X86::VXORPSYrr));
3586  case X86::V_SETALLONES:
3587    return Expand2AddrUndef(MIB, get(HasAVX ? X86::VPCMPEQDrr : X86::PCMPEQDrr));
3588  case X86::AVX2_SETALLONES:
3589    return Expand2AddrUndef(MIB, get(X86::VPCMPEQDYrr));
3590  case X86::TEST8ri_NOREX:
3591    MI->setDesc(get(X86::TEST8ri));
3592    return true;
3593  }
3594  return false;
3595}
3596
3597MachineInstr*
3598X86InstrInfo::emitFrameIndexDebugValue(MachineFunction &MF,
3599                                       int FrameIx, uint64_t Offset,
3600                                       const MDNode *MDPtr,
3601                                       DebugLoc DL) const {
3602  X86AddressMode AM;
3603  AM.BaseType = X86AddressMode::FrameIndexBase;
3604  AM.Base.FrameIndex = FrameIx;
3605  MachineInstrBuilder MIB = BuildMI(MF, DL, get(X86::DBG_VALUE));
3606  addFullAddress(MIB, AM).addImm(Offset).addMetadata(MDPtr);
3607  return &*MIB;
3608}
3609
3610static MachineInstr *FuseTwoAddrInst(MachineFunction &MF, unsigned Opcode,
3611                                     const SmallVectorImpl<MachineOperand> &MOs,
3612                                     MachineInstr *MI,
3613                                     const TargetInstrInfo &TII) {
3614  // Create the base instruction with the memory operand as the first part.
3615  // Omit the implicit operands, something BuildMI can't do.
3616  MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode),
3617                                              MI->getDebugLoc(), true);
3618  MachineInstrBuilder MIB(MF, NewMI);
3619  unsigned NumAddrOps = MOs.size();
3620  for (unsigned i = 0; i != NumAddrOps; ++i)
3621    MIB.addOperand(MOs[i]);
3622  if (NumAddrOps < 4)  // FrameIndex only
3623    addOffset(MIB, 0);
3624
3625  // Loop over the rest of the ri operands, converting them over.
3626  unsigned NumOps = MI->getDesc().getNumOperands()-2;
3627  for (unsigned i = 0; i != NumOps; ++i) {
3628    MachineOperand &MO = MI->getOperand(i+2);
3629    MIB.addOperand(MO);
3630  }
3631  for (unsigned i = NumOps+2, e = MI->getNumOperands(); i != e; ++i) {
3632    MachineOperand &MO = MI->getOperand(i);
3633    MIB.addOperand(MO);
3634  }
3635  return MIB;
3636}
3637
3638static MachineInstr *FuseInst(MachineFunction &MF,
3639                              unsigned Opcode, unsigned OpNo,
3640                              const SmallVectorImpl<MachineOperand> &MOs,
3641                              MachineInstr *MI, const TargetInstrInfo &TII) {
3642  // Omit the implicit operands, something BuildMI can't do.
3643  MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode),
3644                                              MI->getDebugLoc(), true);
3645  MachineInstrBuilder MIB(MF, NewMI);
3646
3647  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
3648    MachineOperand &MO = MI->getOperand(i);
3649    if (i == OpNo) {
3650      assert(MO.isReg() && "Expected to fold into reg operand!");
3651      unsigned NumAddrOps = MOs.size();
3652      for (unsigned i = 0; i != NumAddrOps; ++i)
3653        MIB.addOperand(MOs[i]);
3654      if (NumAddrOps < 4)  // FrameIndex only
3655        addOffset(MIB, 0);
3656    } else {
3657      MIB.addOperand(MO);
3658    }
3659  }
3660  return MIB;
3661}
3662
3663static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode,
3664                                const SmallVectorImpl<MachineOperand> &MOs,
3665                                MachineInstr *MI) {
3666  MachineFunction &MF = *MI->getParent()->getParent();
3667  MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), TII.get(Opcode));
3668
3669  unsigned NumAddrOps = MOs.size();
3670  for (unsigned i = 0; i != NumAddrOps; ++i)
3671    MIB.addOperand(MOs[i]);
3672  if (NumAddrOps < 4)  // FrameIndex only
3673    addOffset(MIB, 0);
3674  return MIB.addImm(0);
3675}
3676
3677MachineInstr*
3678X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
3679                                    MachineInstr *MI, unsigned i,
3680                                    const SmallVectorImpl<MachineOperand> &MOs,
3681                                    unsigned Size, unsigned Align) const {
3682  const DenseMap<unsigned, std::pair<unsigned,unsigned> > *OpcodeTablePtr = 0;
3683  bool isTwoAddrFold = false;
3684  unsigned NumOps = MI->getDesc().getNumOperands();
3685  bool isTwoAddr = NumOps > 1 &&
3686    MI->getDesc().getOperandConstraint(1, MCOI::TIED_TO) != -1;
3687
3688  // FIXME: AsmPrinter doesn't know how to handle
3689  // X86II::MO_GOT_ABSOLUTE_ADDRESS after folding.
3690  if (MI->getOpcode() == X86::ADD32ri &&
3691      MI->getOperand(2).getTargetFlags() == X86II::MO_GOT_ABSOLUTE_ADDRESS)
3692    return NULL;
3693
3694  MachineInstr *NewMI = NULL;
3695  // Folding a memory location into the two-address part of a two-address
3696  // instruction is different than folding it other places.  It requires
3697  // replacing the *two* registers with the memory location.
3698  if (isTwoAddr && NumOps >= 2 && i < 2 &&
3699      MI->getOperand(0).isReg() &&
3700      MI->getOperand(1).isReg() &&
3701      MI->getOperand(0).getReg() == MI->getOperand(1).getReg()) {
3702    OpcodeTablePtr = &RegOp2MemOpTable2Addr;
3703    isTwoAddrFold = true;
3704  } else if (i == 0) { // If operand 0
3705    unsigned Opc = 0;
3706    switch (MI->getOpcode()) {
3707    default: break;
3708    case X86::MOV64r0: Opc = X86::MOV64mi32; break;
3709    case X86::MOV32r0: Opc = X86::MOV32mi;   break;
3710    case X86::MOV16r0: Opc = X86::MOV16mi;   break;
3711    case X86::MOV8r0:  Opc = X86::MOV8mi;    break;
3712    }
3713    if (Opc)
3714       NewMI = MakeM0Inst(*this, Opc, MOs, MI);
3715    if (NewMI)
3716      return NewMI;
3717
3718    OpcodeTablePtr = &RegOp2MemOpTable0;
3719  } else if (i == 1) {
3720    OpcodeTablePtr = &RegOp2MemOpTable1;
3721  } else if (i == 2) {
3722    OpcodeTablePtr = &RegOp2MemOpTable2;
3723  } else if (i == 3) {
3724    OpcodeTablePtr = &RegOp2MemOpTable3;
3725  }
3726
3727  // If table selected...
3728  if (OpcodeTablePtr) {
3729    // Find the Opcode to fuse
3730    DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
3731      OpcodeTablePtr->find(MI->getOpcode());
3732    if (I != OpcodeTablePtr->end()) {
3733      unsigned Opcode = I->second.first;
3734      unsigned MinAlign = (I->second.second & TB_ALIGN_MASK) >> TB_ALIGN_SHIFT;
3735      if (Align < MinAlign)
3736        return NULL;
3737      bool NarrowToMOV32rm = false;
3738      if (Size) {
3739        unsigned RCSize = getRegClass(MI->getDesc(), i, &RI, MF)->getSize();
3740        if (Size < RCSize) {
3741          // Check if it's safe to fold the load. If the size of the object is
3742          // narrower than the load width, then it's not.
3743          if (Opcode != X86::MOV64rm || RCSize != 8 || Size != 4)
3744            return NULL;
3745          // If this is a 64-bit load, but the spill slot is 32, then we can do
3746          // a 32-bit load which is implicitly zero-extended. This likely is due
3747          // to liveintervalanalysis remat'ing a load from stack slot.
3748          if (MI->getOperand(0).getSubReg() || MI->getOperand(1).getSubReg())
3749            return NULL;
3750          Opcode = X86::MOV32rm;
3751          NarrowToMOV32rm = true;
3752        }
3753      }
3754
3755      if (isTwoAddrFold)
3756        NewMI = FuseTwoAddrInst(MF, Opcode, MOs, MI, *this);
3757      else
3758        NewMI = FuseInst(MF, Opcode, i, MOs, MI, *this);
3759
3760      if (NarrowToMOV32rm) {
3761        // If this is the special case where we use a MOV32rm to load a 32-bit
3762        // value and zero-extend the top bits. Change the destination register
3763        // to a 32-bit one.
3764        unsigned DstReg = NewMI->getOperand(0).getReg();
3765        if (TargetRegisterInfo::isPhysicalRegister(DstReg))
3766          NewMI->getOperand(0).setReg(RI.getSubReg(DstReg,
3767                                                   X86::sub_32bit));
3768        else
3769          NewMI->getOperand(0).setSubReg(X86::sub_32bit);
3770      }
3771      return NewMI;
3772    }
3773  }
3774
3775  // No fusion
3776  if (PrintFailedFusing && !MI->isCopy())
3777    dbgs() << "We failed to fuse operand " << i << " in " << *MI;
3778  return NULL;
3779}
3780
3781/// hasPartialRegUpdate - Return true for all instructions that only update
3782/// the first 32 or 64-bits of the destination register and leave the rest
3783/// unmodified. This can be used to avoid folding loads if the instructions
3784/// only update part of the destination register, and the non-updated part is
3785/// not needed. e.g. cvtss2sd, sqrtss. Unfolding the load from these
3786/// instructions breaks the partial register dependency and it can improve
3787/// performance. e.g.:
3788///
3789///   movss (%rdi), %xmm0
3790///   cvtss2sd %xmm0, %xmm0
3791///
3792/// Instead of
3793///   cvtss2sd (%rdi), %xmm0
3794///
3795/// FIXME: This should be turned into a TSFlags.
3796///
3797static bool hasPartialRegUpdate(unsigned Opcode) {
3798  switch (Opcode) {
3799  case X86::CVTSI2SSrr:
3800  case X86::CVTSI2SS64rr:
3801  case X86::CVTSI2SDrr:
3802  case X86::CVTSI2SD64rr:
3803  case X86::CVTSD2SSrr:
3804  case X86::Int_CVTSD2SSrr:
3805  case X86::CVTSS2SDrr:
3806  case X86::Int_CVTSS2SDrr:
3807  case X86::RCPSSr:
3808  case X86::RCPSSr_Int:
3809  case X86::ROUNDSDr:
3810  case X86::ROUNDSDr_Int:
3811  case X86::ROUNDSSr:
3812  case X86::ROUNDSSr_Int:
3813  case X86::RSQRTSSr:
3814  case X86::RSQRTSSr_Int:
3815  case X86::SQRTSSr:
3816  case X86::SQRTSSr_Int:
3817  // AVX encoded versions
3818  case X86::VCVTSD2SSrr:
3819  case X86::Int_VCVTSD2SSrr:
3820  case X86::VCVTSS2SDrr:
3821  case X86::Int_VCVTSS2SDrr:
3822  case X86::VRCPSSr:
3823  case X86::VROUNDSDr:
3824  case X86::VROUNDSDr_Int:
3825  case X86::VROUNDSSr:
3826  case X86::VROUNDSSr_Int:
3827  case X86::VRSQRTSSr:
3828  case X86::VSQRTSSr:
3829    return true;
3830  }
3831
3832  return false;
3833}
3834
3835/// getPartialRegUpdateClearance - Inform the ExeDepsFix pass how many idle
3836/// instructions we would like before a partial register update.
3837unsigned X86InstrInfo::
3838getPartialRegUpdateClearance(const MachineInstr *MI, unsigned OpNum,
3839                             const TargetRegisterInfo *TRI) const {
3840  if (OpNum != 0 || !hasPartialRegUpdate(MI->getOpcode()))
3841    return 0;
3842
3843  // If MI is marked as reading Reg, the partial register update is wanted.
3844  const MachineOperand &MO = MI->getOperand(0);
3845  unsigned Reg = MO.getReg();
3846  if (TargetRegisterInfo::isVirtualRegister(Reg)) {
3847    if (MO.readsReg() || MI->readsVirtualRegister(Reg))
3848      return 0;
3849  } else {
3850    if (MI->readsRegister(Reg, TRI))
3851      return 0;
3852  }
3853
3854  // If any of the preceding 16 instructions are reading Reg, insert a
3855  // dependency breaking instruction.  The magic number is based on a few
3856  // Nehalem experiments.
3857  return 16;
3858}
3859
3860void X86InstrInfo::
3861breakPartialRegDependency(MachineBasicBlock::iterator MI, unsigned OpNum,
3862                          const TargetRegisterInfo *TRI) const {
3863  unsigned Reg = MI->getOperand(OpNum).getReg();
3864  if (X86::VR128RegClass.contains(Reg)) {
3865    // These instructions are all floating point domain, so xorps is the best
3866    // choice.
3867    bool HasAVX = TM.getSubtarget<X86Subtarget>().hasAVX();
3868    unsigned Opc = HasAVX ? X86::VXORPSrr : X86::XORPSrr;
3869    BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(Opc), Reg)
3870      .addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
3871  } else if (X86::VR256RegClass.contains(Reg)) {
3872    // Use vxorps to clear the full ymm register.
3873    // It wants to read and write the xmm sub-register.
3874    unsigned XReg = TRI->getSubReg(Reg, X86::sub_xmm);
3875    BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(X86::VXORPSrr), XReg)
3876      .addReg(XReg, RegState::Undef).addReg(XReg, RegState::Undef)
3877      .addReg(Reg, RegState::ImplicitDefine);
3878  } else
3879    return;
3880  MI->addRegisterKilled(Reg, TRI, true);
3881}
3882
3883MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
3884                                                  MachineInstr *MI,
3885                                           const SmallVectorImpl<unsigned> &Ops,
3886                                                  int FrameIndex) const {
3887  // Check switch flag
3888  if (NoFusing) return NULL;
3889
3890  // Unless optimizing for size, don't fold to avoid partial
3891  // register update stalls
3892  if (!MF.getFunction()->getFnAttributes().
3893        hasAttribute(Attribute::OptimizeForSize) &&
3894      hasPartialRegUpdate(MI->getOpcode()))
3895    return 0;
3896
3897  const MachineFrameInfo *MFI = MF.getFrameInfo();
3898  unsigned Size = MFI->getObjectSize(FrameIndex);
3899  unsigned Alignment = MFI->getObjectAlignment(FrameIndex);
3900  if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
3901    unsigned NewOpc = 0;
3902    unsigned RCSize = 0;
3903    switch (MI->getOpcode()) {
3904    default: return NULL;
3905    case X86::TEST8rr:  NewOpc = X86::CMP8ri; RCSize = 1; break;
3906    case X86::TEST16rr: NewOpc = X86::CMP16ri8; RCSize = 2; break;
3907    case X86::TEST32rr: NewOpc = X86::CMP32ri8; RCSize = 4; break;
3908    case X86::TEST64rr: NewOpc = X86::CMP64ri8; RCSize = 8; break;
3909    }
3910    // Check if it's safe to fold the load. If the size of the object is
3911    // narrower than the load width, then it's not.
3912    if (Size < RCSize)
3913      return NULL;
3914    // Change to CMPXXri r, 0 first.
3915    MI->setDesc(get(NewOpc));
3916    MI->getOperand(1).ChangeToImmediate(0);
3917  } else if (Ops.size() != 1)
3918    return NULL;
3919
3920  SmallVector<MachineOperand,4> MOs;
3921  MOs.push_back(MachineOperand::CreateFI(FrameIndex));
3922  return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, Size, Alignment);
3923}
3924
3925MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
3926                                                  MachineInstr *MI,
3927                                           const SmallVectorImpl<unsigned> &Ops,
3928                                                  MachineInstr *LoadMI) const {
3929  // Check switch flag
3930  if (NoFusing) return NULL;
3931
3932  // Unless optimizing for size, don't fold to avoid partial
3933  // register update stalls
3934  if (!MF.getFunction()->getFnAttributes().
3935        hasAttribute(Attribute::OptimizeForSize) &&
3936      hasPartialRegUpdate(MI->getOpcode()))
3937    return 0;
3938
3939  // Determine the alignment of the load.
3940  unsigned Alignment = 0;
3941  if (LoadMI->hasOneMemOperand())
3942    Alignment = (*LoadMI->memoperands_begin())->getAlignment();
3943  else
3944    switch (LoadMI->getOpcode()) {
3945    case X86::AVX2_SETALLONES:
3946    case X86::AVX_SET0:
3947      Alignment = 32;
3948      break;
3949    case X86::V_SET0:
3950    case X86::V_SETALLONES:
3951      Alignment = 16;
3952      break;
3953    case X86::FsFLD0SD:
3954      Alignment = 8;
3955      break;
3956    case X86::FsFLD0SS:
3957      Alignment = 4;
3958      break;
3959    default:
3960      return 0;
3961    }
3962  if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
3963    unsigned NewOpc = 0;
3964    switch (MI->getOpcode()) {
3965    default: return NULL;
3966    case X86::TEST8rr:  NewOpc = X86::CMP8ri; break;
3967    case X86::TEST16rr: NewOpc = X86::CMP16ri8; break;
3968    case X86::TEST32rr: NewOpc = X86::CMP32ri8; break;
3969    case X86::TEST64rr: NewOpc = X86::CMP64ri8; break;
3970    }
3971    // Change to CMPXXri r, 0 first.
3972    MI->setDesc(get(NewOpc));
3973    MI->getOperand(1).ChangeToImmediate(0);
3974  } else if (Ops.size() != 1)
3975    return NULL;
3976
3977  // Make sure the subregisters match.
3978  // Otherwise we risk changing the size of the load.
3979  if (LoadMI->getOperand(0).getSubReg() != MI->getOperand(Ops[0]).getSubReg())
3980    return NULL;
3981
3982  SmallVector<MachineOperand,X86::AddrNumOperands> MOs;
3983  switch (LoadMI->getOpcode()) {
3984  case X86::V_SET0:
3985  case X86::V_SETALLONES:
3986  case X86::AVX2_SETALLONES:
3987  case X86::AVX_SET0:
3988  case X86::FsFLD0SD:
3989  case X86::FsFLD0SS: {
3990    // Folding a V_SET0 or V_SETALLONES as a load, to ease register pressure.
3991    // Create a constant-pool entry and operands to load from it.
3992
3993    // Medium and large mode can't fold loads this way.
3994    if (TM.getCodeModel() != CodeModel::Small &&
3995        TM.getCodeModel() != CodeModel::Kernel)
3996      return NULL;
3997
3998    // x86-32 PIC requires a PIC base register for constant pools.
3999    unsigned PICBase = 0;
4000    if (TM.getRelocationModel() == Reloc::PIC_) {
4001      if (TM.getSubtarget<X86Subtarget>().is64Bit())
4002        PICBase = X86::RIP;
4003      else
4004        // FIXME: PICBase = getGlobalBaseReg(&MF);
4005        // This doesn't work for several reasons.
4006        // 1. GlobalBaseReg may have been spilled.
4007        // 2. It may not be live at MI.
4008        return NULL;
4009    }
4010
4011    // Create a constant-pool entry.
4012    MachineConstantPool &MCP = *MF.getConstantPool();
4013    Type *Ty;
4014    unsigned Opc = LoadMI->getOpcode();
4015    if (Opc == X86::FsFLD0SS)
4016      Ty = Type::getFloatTy(MF.getFunction()->getContext());
4017    else if (Opc == X86::FsFLD0SD)
4018      Ty = Type::getDoubleTy(MF.getFunction()->getContext());
4019    else if (Opc == X86::AVX2_SETALLONES || Opc == X86::AVX_SET0)
4020      Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 8);
4021    else
4022      Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 4);
4023
4024    bool IsAllOnes = (Opc == X86::V_SETALLONES || Opc == X86::AVX2_SETALLONES);
4025    const Constant *C = IsAllOnes ? Constant::getAllOnesValue(Ty) :
4026                                    Constant::getNullValue(Ty);
4027    unsigned CPI = MCP.getConstantPoolIndex(C, Alignment);
4028
4029    // Create operands to load from the constant pool entry.
4030    MOs.push_back(MachineOperand::CreateReg(PICBase, false));
4031    MOs.push_back(MachineOperand::CreateImm(1));
4032    MOs.push_back(MachineOperand::CreateReg(0, false));
4033    MOs.push_back(MachineOperand::CreateCPI(CPI, 0));
4034    MOs.push_back(MachineOperand::CreateReg(0, false));
4035    break;
4036  }
4037  default: {
4038    if ((LoadMI->getOpcode() == X86::MOVSSrm ||
4039         LoadMI->getOpcode() == X86::VMOVSSrm) &&
4040        MF.getRegInfo().getRegClass(LoadMI->getOperand(0).getReg())->getSize()
4041          > 4)
4042      // These instructions only load 32 bits, we can't fold them if the
4043      // destination register is wider than 32 bits (4 bytes).
4044      return NULL;
4045    if ((LoadMI->getOpcode() == X86::MOVSDrm ||
4046         LoadMI->getOpcode() == X86::VMOVSDrm) &&
4047        MF.getRegInfo().getRegClass(LoadMI->getOperand(0).getReg())->getSize()
4048          > 8)
4049      // These instructions only load 64 bits, we can't fold them if the
4050      // destination register is wider than 64 bits (8 bytes).
4051      return NULL;
4052
4053    // Folding a normal load. Just copy the load's address operands.
4054    unsigned NumOps = LoadMI->getDesc().getNumOperands();
4055    for (unsigned i = NumOps - X86::AddrNumOperands; i != NumOps; ++i)
4056      MOs.push_back(LoadMI->getOperand(i));
4057    break;
4058  }
4059  }
4060  return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, 0, Alignment);
4061}
4062
4063
4064bool X86InstrInfo::canFoldMemoryOperand(const MachineInstr *MI,
4065                                  const SmallVectorImpl<unsigned> &Ops) const {
4066  // Check switch flag
4067  if (NoFusing) return 0;
4068
4069  if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
4070    switch (MI->getOpcode()) {
4071    default: return false;
4072    case X86::TEST8rr:
4073    case X86::TEST16rr:
4074    case X86::TEST32rr:
4075    case X86::TEST64rr:
4076      return true;
4077    case X86::ADD32ri:
4078      // FIXME: AsmPrinter doesn't know how to handle
4079      // X86II::MO_GOT_ABSOLUTE_ADDRESS after folding.
4080      if (MI->getOperand(2).getTargetFlags() == X86II::MO_GOT_ABSOLUTE_ADDRESS)
4081        return false;
4082      break;
4083    }
4084  }
4085
4086  if (Ops.size() != 1)
4087    return false;
4088
4089  unsigned OpNum = Ops[0];
4090  unsigned Opc = MI->getOpcode();
4091  unsigned NumOps = MI->getDesc().getNumOperands();
4092  bool isTwoAddr = NumOps > 1 &&
4093    MI->getDesc().getOperandConstraint(1, MCOI::TIED_TO) != -1;
4094
4095  // Folding a memory location into the two-address part of a two-address
4096  // instruction is different than folding it other places.  It requires
4097  // replacing the *two* registers with the memory location.
4098  const DenseMap<unsigned, std::pair<unsigned,unsigned> > *OpcodeTablePtr = 0;
4099  if (isTwoAddr && NumOps >= 2 && OpNum < 2) {
4100    OpcodeTablePtr = &RegOp2MemOpTable2Addr;
4101  } else if (OpNum == 0) { // If operand 0
4102    switch (Opc) {
4103    case X86::MOV8r0:
4104    case X86::MOV16r0:
4105    case X86::MOV32r0:
4106    case X86::MOV64r0: return true;
4107    default: break;
4108    }
4109    OpcodeTablePtr = &RegOp2MemOpTable0;
4110  } else if (OpNum == 1) {
4111    OpcodeTablePtr = &RegOp2MemOpTable1;
4112  } else if (OpNum == 2) {
4113    OpcodeTablePtr = &RegOp2MemOpTable2;
4114  } else if (OpNum == 3) {
4115    OpcodeTablePtr = &RegOp2MemOpTable3;
4116  }
4117
4118  if (OpcodeTablePtr && OpcodeTablePtr->count(Opc))
4119    return true;
4120  return TargetInstrInfo::canFoldMemoryOperand(MI, Ops);
4121}
4122
4123bool X86InstrInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
4124                                unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
4125                                SmallVectorImpl<MachineInstr*> &NewMIs) const {
4126  DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
4127    MemOp2RegOpTable.find(MI->getOpcode());
4128  if (I == MemOp2RegOpTable.end())
4129    return false;
4130  unsigned Opc = I->second.first;
4131  unsigned Index = I->second.second & TB_INDEX_MASK;
4132  bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
4133  bool FoldedStore = I->second.second & TB_FOLDED_STORE;
4134  if (UnfoldLoad && !FoldedLoad)
4135    return false;
4136  UnfoldLoad &= FoldedLoad;
4137  if (UnfoldStore && !FoldedStore)
4138    return false;
4139  UnfoldStore &= FoldedStore;
4140
4141  const MCInstrDesc &MCID = get(Opc);
4142  const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF);
4143  if (!MI->hasOneMemOperand() &&
4144      RC == &X86::VR128RegClass &&
4145      !TM.getSubtarget<X86Subtarget>().isUnalignedMemAccessFast())
4146    // Without memoperands, loadRegFromAddr and storeRegToStackSlot will
4147    // conservatively assume the address is unaligned. That's bad for
4148    // performance.
4149    return false;
4150  SmallVector<MachineOperand, X86::AddrNumOperands> AddrOps;
4151  SmallVector<MachineOperand,2> BeforeOps;
4152  SmallVector<MachineOperand,2> AfterOps;
4153  SmallVector<MachineOperand,4> ImpOps;
4154  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
4155    MachineOperand &Op = MI->getOperand(i);
4156    if (i >= Index && i < Index + X86::AddrNumOperands)
4157      AddrOps.push_back(Op);
4158    else if (Op.isReg() && Op.isImplicit())
4159      ImpOps.push_back(Op);
4160    else if (i < Index)
4161      BeforeOps.push_back(Op);
4162    else if (i > Index)
4163      AfterOps.push_back(Op);
4164  }
4165
4166  // Emit the load instruction.
4167  if (UnfoldLoad) {
4168    std::pair<MachineInstr::mmo_iterator,
4169              MachineInstr::mmo_iterator> MMOs =
4170      MF.extractLoadMemRefs(MI->memoperands_begin(),
4171                            MI->memoperands_end());
4172    loadRegFromAddr(MF, Reg, AddrOps, RC, MMOs.first, MMOs.second, NewMIs);
4173    if (UnfoldStore) {
4174      // Address operands cannot be marked isKill.
4175      for (unsigned i = 1; i != 1 + X86::AddrNumOperands; ++i) {
4176        MachineOperand &MO = NewMIs[0]->getOperand(i);
4177        if (MO.isReg())
4178          MO.setIsKill(false);
4179      }
4180    }
4181  }
4182
4183  // Emit the data processing instruction.
4184  MachineInstr *DataMI = MF.CreateMachineInstr(MCID, MI->getDebugLoc(), true);
4185  MachineInstrBuilder MIB(MF, DataMI);
4186
4187  if (FoldedStore)
4188    MIB.addReg(Reg, RegState::Define);
4189  for (unsigned i = 0, e = BeforeOps.size(); i != e; ++i)
4190    MIB.addOperand(BeforeOps[i]);
4191  if (FoldedLoad)
4192    MIB.addReg(Reg);
4193  for (unsigned i = 0, e = AfterOps.size(); i != e; ++i)
4194    MIB.addOperand(AfterOps[i]);
4195  for (unsigned i = 0, e = ImpOps.size(); i != e; ++i) {
4196    MachineOperand &MO = ImpOps[i];
4197    MIB.addReg(MO.getReg(),
4198               getDefRegState(MO.isDef()) |
4199               RegState::Implicit |
4200               getKillRegState(MO.isKill()) |
4201               getDeadRegState(MO.isDead()) |
4202               getUndefRegState(MO.isUndef()));
4203  }
4204  // Change CMP32ri r, 0 back to TEST32rr r, r, etc.
4205  switch (DataMI->getOpcode()) {
4206  default: break;
4207  case X86::CMP64ri32:
4208  case X86::CMP64ri8:
4209  case X86::CMP32ri:
4210  case X86::CMP32ri8:
4211  case X86::CMP16ri:
4212  case X86::CMP16ri8:
4213  case X86::CMP8ri: {
4214    MachineOperand &MO0 = DataMI->getOperand(0);
4215    MachineOperand &MO1 = DataMI->getOperand(1);
4216    if (MO1.getImm() == 0) {
4217      unsigned NewOpc;
4218      switch (DataMI->getOpcode()) {
4219      default: llvm_unreachable("Unreachable!");
4220      case X86::CMP64ri8:
4221      case X86::CMP64ri32: NewOpc = X86::TEST64rr; break;
4222      case X86::CMP32ri8:
4223      case X86::CMP32ri:   NewOpc = X86::TEST32rr; break;
4224      case X86::CMP16ri8:
4225      case X86::CMP16ri:   NewOpc = X86::TEST16rr; break;
4226      case X86::CMP8ri:    NewOpc = X86::TEST8rr; break;
4227      }
4228      DataMI->setDesc(get(NewOpc));
4229      MO1.ChangeToRegister(MO0.getReg(), false);
4230    }
4231  }
4232  }
4233  NewMIs.push_back(DataMI);
4234
4235  // Emit the store instruction.
4236  if (UnfoldStore) {
4237    const TargetRegisterClass *DstRC = getRegClass(MCID, 0, &RI, MF);
4238    std::pair<MachineInstr::mmo_iterator,
4239              MachineInstr::mmo_iterator> MMOs =
4240      MF.extractStoreMemRefs(MI->memoperands_begin(),
4241                             MI->memoperands_end());
4242    storeRegToAddr(MF, Reg, true, AddrOps, DstRC, MMOs.first, MMOs.second, NewMIs);
4243  }
4244
4245  return true;
4246}
4247
4248bool
4249X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
4250                                  SmallVectorImpl<SDNode*> &NewNodes) const {
4251  if (!N->isMachineOpcode())
4252    return false;
4253
4254  DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
4255    MemOp2RegOpTable.find(N->getMachineOpcode());
4256  if (I == MemOp2RegOpTable.end())
4257    return false;
4258  unsigned Opc = I->second.first;
4259  unsigned Index = I->second.second & TB_INDEX_MASK;
4260  bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
4261  bool FoldedStore = I->second.second & TB_FOLDED_STORE;
4262  const MCInstrDesc &MCID = get(Opc);
4263  MachineFunction &MF = DAG.getMachineFunction();
4264  const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF);
4265  unsigned NumDefs = MCID.NumDefs;
4266  std::vector<SDValue> AddrOps;
4267  std::vector<SDValue> BeforeOps;
4268  std::vector<SDValue> AfterOps;
4269  DebugLoc dl = N->getDebugLoc();
4270  unsigned NumOps = N->getNumOperands();
4271  for (unsigned i = 0; i != NumOps-1; ++i) {
4272    SDValue Op = N->getOperand(i);
4273    if (i >= Index-NumDefs && i < Index-NumDefs + X86::AddrNumOperands)
4274      AddrOps.push_back(Op);
4275    else if (i < Index-NumDefs)
4276      BeforeOps.push_back(Op);
4277    else if (i > Index-NumDefs)
4278      AfterOps.push_back(Op);
4279  }
4280  SDValue Chain = N->getOperand(NumOps-1);
4281  AddrOps.push_back(Chain);
4282
4283  // Emit the load instruction.
4284  SDNode *Load = 0;
4285  if (FoldedLoad) {
4286    EVT VT = *RC->vt_begin();
4287    std::pair<MachineInstr::mmo_iterator,
4288              MachineInstr::mmo_iterator> MMOs =
4289      MF.extractLoadMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
4290                            cast<MachineSDNode>(N)->memoperands_end());
4291    if (!(*MMOs.first) &&
4292        RC == &X86::VR128RegClass &&
4293        !TM.getSubtarget<X86Subtarget>().isUnalignedMemAccessFast())
4294      // Do not introduce a slow unaligned load.
4295      return false;
4296    unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
4297    bool isAligned = (*MMOs.first) &&
4298                     (*MMOs.first)->getAlignment() >= Alignment;
4299    Load = DAG.getMachineNode(getLoadRegOpcode(0, RC, isAligned, TM), dl,
4300                              VT, MVT::Other, &AddrOps[0], AddrOps.size());
4301    NewNodes.push_back(Load);
4302
4303    // Preserve memory reference information.
4304    cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second);
4305  }
4306
4307  // Emit the data processing instruction.
4308  std::vector<EVT> VTs;
4309  const TargetRegisterClass *DstRC = 0;
4310  if (MCID.getNumDefs() > 0) {
4311    DstRC = getRegClass(MCID, 0, &RI, MF);
4312    VTs.push_back(*DstRC->vt_begin());
4313  }
4314  for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
4315    EVT VT = N->getValueType(i);
4316    if (VT != MVT::Other && i >= (unsigned)MCID.getNumDefs())
4317      VTs.push_back(VT);
4318  }
4319  if (Load)
4320    BeforeOps.push_back(SDValue(Load, 0));
4321  std::copy(AfterOps.begin(), AfterOps.end(), std::back_inserter(BeforeOps));
4322  SDNode *NewNode= DAG.getMachineNode(Opc, dl, VTs, &BeforeOps[0],
4323                                      BeforeOps.size());
4324  NewNodes.push_back(NewNode);
4325
4326  // Emit the store instruction.
4327  if (FoldedStore) {
4328    AddrOps.pop_back();
4329    AddrOps.push_back(SDValue(NewNode, 0));
4330    AddrOps.push_back(Chain);
4331    std::pair<MachineInstr::mmo_iterator,
4332              MachineInstr::mmo_iterator> MMOs =
4333      MF.extractStoreMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
4334                             cast<MachineSDNode>(N)->memoperands_end());
4335    if (!(*MMOs.first) &&
4336        RC == &X86::VR128RegClass &&
4337        !TM.getSubtarget<X86Subtarget>().isUnalignedMemAccessFast())
4338      // Do not introduce a slow unaligned store.
4339      return false;
4340    unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
4341    bool isAligned = (*MMOs.first) &&
4342                     (*MMOs.first)->getAlignment() >= Alignment;
4343    SDNode *Store = DAG.getMachineNode(getStoreRegOpcode(0, DstRC,
4344                                                         isAligned, TM),
4345                                       dl, MVT::Other,
4346                                       &AddrOps[0], AddrOps.size());
4347    NewNodes.push_back(Store);
4348
4349    // Preserve memory reference information.
4350    cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second);
4351  }
4352
4353  return true;
4354}
4355
4356unsigned X86InstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc,
4357                                      bool UnfoldLoad, bool UnfoldStore,
4358                                      unsigned *LoadRegIndex) const {
4359  DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
4360    MemOp2RegOpTable.find(Opc);
4361  if (I == MemOp2RegOpTable.end())
4362    return 0;
4363  bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
4364  bool FoldedStore = I->second.second & TB_FOLDED_STORE;
4365  if (UnfoldLoad && !FoldedLoad)
4366    return 0;
4367  if (UnfoldStore && !FoldedStore)
4368    return 0;
4369  if (LoadRegIndex)
4370    *LoadRegIndex = I->second.second & TB_INDEX_MASK;
4371  return I->second.first;
4372}
4373
4374bool
4375X86InstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
4376                                     int64_t &Offset1, int64_t &Offset2) const {
4377  if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode())
4378    return false;
4379  unsigned Opc1 = Load1->getMachineOpcode();
4380  unsigned Opc2 = Load2->getMachineOpcode();
4381  switch (Opc1) {
4382  default: return false;
4383  case X86::MOV8rm:
4384  case X86::MOV16rm:
4385  case X86::MOV32rm:
4386  case X86::MOV64rm:
4387  case X86::LD_Fp32m:
4388  case X86::LD_Fp64m:
4389  case X86::LD_Fp80m:
4390  case X86::MOVSSrm:
4391  case X86::MOVSDrm:
4392  case X86::MMX_MOVD64rm:
4393  case X86::MMX_MOVQ64rm:
4394  case X86::FsMOVAPSrm:
4395  case X86::FsMOVAPDrm:
4396  case X86::MOVAPSrm:
4397  case X86::MOVUPSrm:
4398  case X86::MOVAPDrm:
4399  case X86::MOVDQArm:
4400  case X86::MOVDQUrm:
4401  // AVX load instructions
4402  case X86::VMOVSSrm:
4403  case X86::VMOVSDrm:
4404  case X86::FsVMOVAPSrm:
4405  case X86::FsVMOVAPDrm:
4406  case X86::VMOVAPSrm:
4407  case X86::VMOVUPSrm:
4408  case X86::VMOVAPDrm:
4409  case X86::VMOVDQArm:
4410  case X86::VMOVDQUrm:
4411  case X86::VMOVAPSYrm:
4412  case X86::VMOVUPSYrm:
4413  case X86::VMOVAPDYrm:
4414  case X86::VMOVDQAYrm:
4415  case X86::VMOVDQUYrm:
4416    break;
4417  }
4418  switch (Opc2) {
4419  default: return false;
4420  case X86::MOV8rm:
4421  case X86::MOV16rm:
4422  case X86::MOV32rm:
4423  case X86::MOV64rm:
4424  case X86::LD_Fp32m:
4425  case X86::LD_Fp64m:
4426  case X86::LD_Fp80m:
4427  case X86::MOVSSrm:
4428  case X86::MOVSDrm:
4429  case X86::MMX_MOVD64rm:
4430  case X86::MMX_MOVQ64rm:
4431  case X86::FsMOVAPSrm:
4432  case X86::FsMOVAPDrm:
4433  case X86::MOVAPSrm:
4434  case X86::MOVUPSrm:
4435  case X86::MOVAPDrm:
4436  case X86::MOVDQArm:
4437  case X86::MOVDQUrm:
4438  // AVX load instructions
4439  case X86::VMOVSSrm:
4440  case X86::VMOVSDrm:
4441  case X86::FsVMOVAPSrm:
4442  case X86::FsVMOVAPDrm:
4443  case X86::VMOVAPSrm:
4444  case X86::VMOVUPSrm:
4445  case X86::VMOVAPDrm:
4446  case X86::VMOVDQArm:
4447  case X86::VMOVDQUrm:
4448  case X86::VMOVAPSYrm:
4449  case X86::VMOVUPSYrm:
4450  case X86::VMOVAPDYrm:
4451  case X86::VMOVDQAYrm:
4452  case X86::VMOVDQUYrm:
4453    break;
4454  }
4455
4456  // Check if chain operands and base addresses match.
4457  if (Load1->getOperand(0) != Load2->getOperand(0) ||
4458      Load1->getOperand(5) != Load2->getOperand(5))
4459    return false;
4460  // Segment operands should match as well.
4461  if (Load1->getOperand(4) != Load2->getOperand(4))
4462    return false;
4463  // Scale should be 1, Index should be Reg0.
4464  if (Load1->getOperand(1) == Load2->getOperand(1) &&
4465      Load1->getOperand(2) == Load2->getOperand(2)) {
4466    if (cast<ConstantSDNode>(Load1->getOperand(1))->getZExtValue() != 1)
4467      return false;
4468
4469    // Now let's examine the displacements.
4470    if (isa<ConstantSDNode>(Load1->getOperand(3)) &&
4471        isa<ConstantSDNode>(Load2->getOperand(3))) {
4472      Offset1 = cast<ConstantSDNode>(Load1->getOperand(3))->getSExtValue();
4473      Offset2 = cast<ConstantSDNode>(Load2->getOperand(3))->getSExtValue();
4474      return true;
4475    }
4476  }
4477  return false;
4478}
4479
4480bool X86InstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
4481                                           int64_t Offset1, int64_t Offset2,
4482                                           unsigned NumLoads) const {
4483  assert(Offset2 > Offset1);
4484  if ((Offset2 - Offset1) / 8 > 64)
4485    return false;
4486
4487  unsigned Opc1 = Load1->getMachineOpcode();
4488  unsigned Opc2 = Load2->getMachineOpcode();
4489  if (Opc1 != Opc2)
4490    return false;  // FIXME: overly conservative?
4491
4492  switch (Opc1) {
4493  default: break;
4494  case X86::LD_Fp32m:
4495  case X86::LD_Fp64m:
4496  case X86::LD_Fp80m:
4497  case X86::MMX_MOVD64rm:
4498  case X86::MMX_MOVQ64rm:
4499    return false;
4500  }
4501
4502  EVT VT = Load1->getValueType(0);
4503  switch (VT.getSimpleVT().SimpleTy) {
4504  default:
4505    // XMM registers. In 64-bit mode we can be a bit more aggressive since we
4506    // have 16 of them to play with.
4507    if (TM.getSubtargetImpl()->is64Bit()) {
4508      if (NumLoads >= 3)
4509        return false;
4510    } else if (NumLoads) {
4511      return false;
4512    }
4513    break;
4514  case MVT::i8:
4515  case MVT::i16:
4516  case MVT::i32:
4517  case MVT::i64:
4518  case MVT::f32:
4519  case MVT::f64:
4520    if (NumLoads)
4521      return false;
4522    break;
4523  }
4524
4525  return true;
4526}
4527
4528
4529bool X86InstrInfo::
4530ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
4531  assert(Cond.size() == 1 && "Invalid X86 branch condition!");
4532  X86::CondCode CC = static_cast<X86::CondCode>(Cond[0].getImm());
4533  if (CC == X86::COND_NE_OR_P || CC == X86::COND_NP_OR_E)
4534    return true;
4535  Cond[0].setImm(GetOppositeBranchCondition(CC));
4536  return false;
4537}
4538
4539bool X86InstrInfo::
4540isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
4541  // FIXME: Return false for x87 stack register classes for now. We can't
4542  // allow any loads of these registers before FpGet_ST0_80.
4543  return !(RC == &X86::CCRRegClass || RC == &X86::RFP32RegClass ||
4544           RC == &X86::RFP64RegClass || RC == &X86::RFP80RegClass);
4545}
4546
4547/// getGlobalBaseReg - Return a virtual register initialized with the
4548/// the global base register value. Output instructions required to
4549/// initialize the register in the function entry block, if necessary.
4550///
4551/// TODO: Eliminate this and move the code to X86MachineFunctionInfo.
4552///
4553unsigned X86InstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
4554  assert(!TM.getSubtarget<X86Subtarget>().is64Bit() &&
4555         "X86-64 PIC uses RIP relative addressing");
4556
4557  X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
4558  unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
4559  if (GlobalBaseReg != 0)
4560    return GlobalBaseReg;
4561
4562  // Create the register. The code to initialize it is inserted
4563  // later, by the CGBR pass (below).
4564  MachineRegisterInfo &RegInfo = MF->getRegInfo();
4565  GlobalBaseReg = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
4566  X86FI->setGlobalBaseReg(GlobalBaseReg);
4567  return GlobalBaseReg;
4568}
4569
4570// These are the replaceable SSE instructions. Some of these have Int variants
4571// that we don't include here. We don't want to replace instructions selected
4572// by intrinsics.
4573static const uint16_t ReplaceableInstrs[][3] = {
4574  //PackedSingle     PackedDouble    PackedInt
4575  { X86::MOVAPSmr,   X86::MOVAPDmr,  X86::MOVDQAmr  },
4576  { X86::MOVAPSrm,   X86::MOVAPDrm,  X86::MOVDQArm  },
4577  { X86::MOVAPSrr,   X86::MOVAPDrr,  X86::MOVDQArr  },
4578  { X86::MOVUPSmr,   X86::MOVUPDmr,  X86::MOVDQUmr  },
4579  { X86::MOVUPSrm,   X86::MOVUPDrm,  X86::MOVDQUrm  },
4580  { X86::MOVNTPSmr,  X86::MOVNTPDmr, X86::MOVNTDQmr },
4581  { X86::ANDNPSrm,   X86::ANDNPDrm,  X86::PANDNrm   },
4582  { X86::ANDNPSrr,   X86::ANDNPDrr,  X86::PANDNrr   },
4583  { X86::ANDPSrm,    X86::ANDPDrm,   X86::PANDrm    },
4584  { X86::ANDPSrr,    X86::ANDPDrr,   X86::PANDrr    },
4585  { X86::ORPSrm,     X86::ORPDrm,    X86::PORrm     },
4586  { X86::ORPSrr,     X86::ORPDrr,    X86::PORrr     },
4587  { X86::XORPSrm,    X86::XORPDrm,   X86::PXORrm    },
4588  { X86::XORPSrr,    X86::XORPDrr,   X86::PXORrr    },
4589  // AVX 128-bit support
4590  { X86::VMOVAPSmr,  X86::VMOVAPDmr,  X86::VMOVDQAmr  },
4591  { X86::VMOVAPSrm,  X86::VMOVAPDrm,  X86::VMOVDQArm  },
4592  { X86::VMOVAPSrr,  X86::VMOVAPDrr,  X86::VMOVDQArr  },
4593  { X86::VMOVUPSmr,  X86::VMOVUPDmr,  X86::VMOVDQUmr  },
4594  { X86::VMOVUPSrm,  X86::VMOVUPDrm,  X86::VMOVDQUrm  },
4595  { X86::VMOVNTPSmr, X86::VMOVNTPDmr, X86::VMOVNTDQmr },
4596  { X86::VANDNPSrm,  X86::VANDNPDrm,  X86::VPANDNrm   },
4597  { X86::VANDNPSrr,  X86::VANDNPDrr,  X86::VPANDNrr   },
4598  { X86::VANDPSrm,   X86::VANDPDrm,   X86::VPANDrm    },
4599  { X86::VANDPSrr,   X86::VANDPDrr,   X86::VPANDrr    },
4600  { X86::VORPSrm,    X86::VORPDrm,    X86::VPORrm     },
4601  { X86::VORPSrr,    X86::VORPDrr,    X86::VPORrr     },
4602  { X86::VXORPSrm,   X86::VXORPDrm,   X86::VPXORrm    },
4603  { X86::VXORPSrr,   X86::VXORPDrr,   X86::VPXORrr    },
4604  // AVX 256-bit support
4605  { X86::VMOVAPSYmr,   X86::VMOVAPDYmr,   X86::VMOVDQAYmr  },
4606  { X86::VMOVAPSYrm,   X86::VMOVAPDYrm,   X86::VMOVDQAYrm  },
4607  { X86::VMOVAPSYrr,   X86::VMOVAPDYrr,   X86::VMOVDQAYrr  },
4608  { X86::VMOVUPSYmr,   X86::VMOVUPDYmr,   X86::VMOVDQUYmr  },
4609  { X86::VMOVUPSYrm,   X86::VMOVUPDYrm,   X86::VMOVDQUYrm  },
4610  { X86::VMOVNTPSYmr,  X86::VMOVNTPDYmr,  X86::VMOVNTDQYmr }
4611};
4612
4613static const uint16_t ReplaceableInstrsAVX2[][3] = {
4614  //PackedSingle       PackedDouble       PackedInt
4615  { X86::VANDNPSYrm,   X86::VANDNPDYrm,   X86::VPANDNYrm   },
4616  { X86::VANDNPSYrr,   X86::VANDNPDYrr,   X86::VPANDNYrr   },
4617  { X86::VANDPSYrm,    X86::VANDPDYrm,    X86::VPANDYrm    },
4618  { X86::VANDPSYrr,    X86::VANDPDYrr,    X86::VPANDYrr    },
4619  { X86::VORPSYrm,     X86::VORPDYrm,     X86::VPORYrm     },
4620  { X86::VORPSYrr,     X86::VORPDYrr,     X86::VPORYrr     },
4621  { X86::VXORPSYrm,    X86::VXORPDYrm,    X86::VPXORYrm    },
4622  { X86::VXORPSYrr,    X86::VXORPDYrr,    X86::VPXORYrr    },
4623  { X86::VEXTRACTF128mr, X86::VEXTRACTF128mr, X86::VEXTRACTI128mr },
4624  { X86::VEXTRACTF128rr, X86::VEXTRACTF128rr, X86::VEXTRACTI128rr },
4625  { X86::VINSERTF128rm,  X86::VINSERTF128rm,  X86::VINSERTI128rm },
4626  { X86::VINSERTF128rr,  X86::VINSERTF128rr,  X86::VINSERTI128rr },
4627  { X86::VPERM2F128rm,   X86::VPERM2F128rm,   X86::VPERM2I128rm },
4628  { X86::VPERM2F128rr,   X86::VPERM2F128rr,   X86::VPERM2I128rr }
4629};
4630
4631// FIXME: Some shuffle and unpack instructions have equivalents in different
4632// domains, but they require a bit more work than just switching opcodes.
4633
4634static const uint16_t *lookup(unsigned opcode, unsigned domain) {
4635  for (unsigned i = 0, e = array_lengthof(ReplaceableInstrs); i != e; ++i)
4636    if (ReplaceableInstrs[i][domain-1] == opcode)
4637      return ReplaceableInstrs[i];
4638  return 0;
4639}
4640
4641static const uint16_t *lookupAVX2(unsigned opcode, unsigned domain) {
4642  for (unsigned i = 0, e = array_lengthof(ReplaceableInstrsAVX2); i != e; ++i)
4643    if (ReplaceableInstrsAVX2[i][domain-1] == opcode)
4644      return ReplaceableInstrsAVX2[i];
4645  return 0;
4646}
4647
4648std::pair<uint16_t, uint16_t>
4649X86InstrInfo::getExecutionDomain(const MachineInstr *MI) const {
4650  uint16_t domain = (MI->getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
4651  bool hasAVX2 = TM.getSubtarget<X86Subtarget>().hasAVX2();
4652  uint16_t validDomains = 0;
4653  if (domain && lookup(MI->getOpcode(), domain))
4654    validDomains = 0xe;
4655  else if (domain && lookupAVX2(MI->getOpcode(), domain))
4656    validDomains = hasAVX2 ? 0xe : 0x6;
4657  return std::make_pair(domain, validDomains);
4658}
4659
4660void X86InstrInfo::setExecutionDomain(MachineInstr *MI, unsigned Domain) const {
4661  assert(Domain>0 && Domain<4 && "Invalid execution domain");
4662  uint16_t dom = (MI->getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
4663  assert(dom && "Not an SSE instruction");
4664  const uint16_t *table = lookup(MI->getOpcode(), dom);
4665  if (!table) { // try the other table
4666    assert((TM.getSubtarget<X86Subtarget>().hasAVX2() || Domain < 3) &&
4667           "256-bit vector operations only available in AVX2");
4668    table = lookupAVX2(MI->getOpcode(), dom);
4669  }
4670  assert(table && "Cannot change domain");
4671  MI->setDesc(get(table[Domain-1]));
4672}
4673
4674/// getNoopForMachoTarget - Return the noop instruction to use for a noop.
4675void X86InstrInfo::getNoopForMachoTarget(MCInst &NopInst) const {
4676  NopInst.setOpcode(X86::NOOP);
4677}
4678
4679bool X86InstrInfo::isHighLatencyDef(int opc) const {
4680  switch (opc) {
4681  default: return false;
4682  case X86::DIVSDrm:
4683  case X86::DIVSDrm_Int:
4684  case X86::DIVSDrr:
4685  case X86::DIVSDrr_Int:
4686  case X86::DIVSSrm:
4687  case X86::DIVSSrm_Int:
4688  case X86::DIVSSrr:
4689  case X86::DIVSSrr_Int:
4690  case X86::SQRTPDm:
4691  case X86::SQRTPDm_Int:
4692  case X86::SQRTPDr:
4693  case X86::SQRTPDr_Int:
4694  case X86::SQRTPSm:
4695  case X86::SQRTPSm_Int:
4696  case X86::SQRTPSr:
4697  case X86::SQRTPSr_Int:
4698  case X86::SQRTSDm:
4699  case X86::SQRTSDm_Int:
4700  case X86::SQRTSDr:
4701  case X86::SQRTSDr_Int:
4702  case X86::SQRTSSm:
4703  case X86::SQRTSSm_Int:
4704  case X86::SQRTSSr:
4705  case X86::SQRTSSr_Int:
4706  // AVX instructions with high latency
4707  case X86::VDIVSDrm:
4708  case X86::VDIVSDrm_Int:
4709  case X86::VDIVSDrr:
4710  case X86::VDIVSDrr_Int:
4711  case X86::VDIVSSrm:
4712  case X86::VDIVSSrm_Int:
4713  case X86::VDIVSSrr:
4714  case X86::VDIVSSrr_Int:
4715  case X86::VSQRTPDm:
4716  case X86::VSQRTPDm_Int:
4717  case X86::VSQRTPDr:
4718  case X86::VSQRTPDr_Int:
4719  case X86::VSQRTPSm:
4720  case X86::VSQRTPSm_Int:
4721  case X86::VSQRTPSr:
4722  case X86::VSQRTPSr_Int:
4723  case X86::VSQRTSDm:
4724  case X86::VSQRTSDm_Int:
4725  case X86::VSQRTSDr:
4726  case X86::VSQRTSSm:
4727  case X86::VSQRTSSm_Int:
4728  case X86::VSQRTSSr:
4729    return true;
4730  }
4731}
4732
4733bool X86InstrInfo::
4734hasHighOperandLatency(const InstrItineraryData *ItinData,
4735                      const MachineRegisterInfo *MRI,
4736                      const MachineInstr *DefMI, unsigned DefIdx,
4737                      const MachineInstr *UseMI, unsigned UseIdx) const {
4738  return isHighLatencyDef(DefMI->getOpcode());
4739}
4740
4741namespace {
4742  /// CGBR - Create Global Base Reg pass. This initializes the PIC
4743  /// global base register for x86-32.
4744  struct CGBR : public MachineFunctionPass {
4745    static char ID;
4746    CGBR() : MachineFunctionPass(ID) {}
4747
4748    virtual bool runOnMachineFunction(MachineFunction &MF) {
4749      const X86TargetMachine *TM =
4750        static_cast<const X86TargetMachine *>(&MF.getTarget());
4751
4752      assert(!TM->getSubtarget<X86Subtarget>().is64Bit() &&
4753             "X86-64 PIC uses RIP relative addressing");
4754
4755      // Only emit a global base reg in PIC mode.
4756      if (TM->getRelocationModel() != Reloc::PIC_)
4757        return false;
4758
4759      X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
4760      unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
4761
4762      // If we didn't need a GlobalBaseReg, don't insert code.
4763      if (GlobalBaseReg == 0)
4764        return false;
4765
4766      // Insert the set of GlobalBaseReg into the first MBB of the function
4767      MachineBasicBlock &FirstMBB = MF.front();
4768      MachineBasicBlock::iterator MBBI = FirstMBB.begin();
4769      DebugLoc DL = FirstMBB.findDebugLoc(MBBI);
4770      MachineRegisterInfo &RegInfo = MF.getRegInfo();
4771      const X86InstrInfo *TII = TM->getInstrInfo();
4772
4773      unsigned PC;
4774      if (TM->getSubtarget<X86Subtarget>().isPICStyleGOT())
4775        PC = RegInfo.createVirtualRegister(&X86::GR32RegClass);
4776      else
4777        PC = GlobalBaseReg;
4778
4779      // Operand of MovePCtoStack is completely ignored by asm printer. It's
4780      // only used in JIT code emission as displacement to pc.
4781      BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOVPC32r), PC).addImm(0);
4782
4783      // If we're using vanilla 'GOT' PIC style, we should use relative addressing
4784      // not to pc, but to _GLOBAL_OFFSET_TABLE_ external.
4785      if (TM->getSubtarget<X86Subtarget>().isPICStyleGOT()) {
4786        // Generate addl $__GLOBAL_OFFSET_TABLE_ + [.-piclabel], %some_register
4787        BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD32ri), GlobalBaseReg)
4788          .addReg(PC).addExternalSymbol("_GLOBAL_OFFSET_TABLE_",
4789                                        X86II::MO_GOT_ABSOLUTE_ADDRESS);
4790      }
4791
4792      return true;
4793    }
4794
4795    virtual const char *getPassName() const {
4796      return "X86 PIC Global Base Reg Initialization";
4797    }
4798
4799    virtual void getAnalysisUsage(AnalysisUsage &AU) const {
4800      AU.setPreservesCFG();
4801      MachineFunctionPass::getAnalysisUsage(AU);
4802    }
4803  };
4804}
4805
4806char CGBR::ID = 0;
4807FunctionPass*
4808llvm::createGlobalBaseRegPass() { return new CGBR(); }
4809
4810namespace {
4811  struct LDTLSCleanup : public MachineFunctionPass {
4812    static char ID;
4813    LDTLSCleanup() : MachineFunctionPass(ID) {}
4814
4815    virtual bool runOnMachineFunction(MachineFunction &MF) {
4816      X86MachineFunctionInfo* MFI = MF.getInfo<X86MachineFunctionInfo>();
4817      if (MFI->getNumLocalDynamicTLSAccesses() < 2) {
4818        // No point folding accesses if there isn't at least two.
4819        return false;
4820      }
4821
4822      MachineDominatorTree *DT = &getAnalysis<MachineDominatorTree>();
4823      return VisitNode(DT->getRootNode(), 0);
4824    }
4825
4826    // Visit the dominator subtree rooted at Node in pre-order.
4827    // If TLSBaseAddrReg is non-null, then use that to replace any
4828    // TLS_base_addr instructions. Otherwise, create the register
4829    // when the first such instruction is seen, and then use it
4830    // as we encounter more instructions.
4831    bool VisitNode(MachineDomTreeNode *Node, unsigned TLSBaseAddrReg) {
4832      MachineBasicBlock *BB = Node->getBlock();
4833      bool Changed = false;
4834
4835      // Traverse the current block.
4836      for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end(); I != E;
4837           ++I) {
4838        switch (I->getOpcode()) {
4839          case X86::TLS_base_addr32:
4840          case X86::TLS_base_addr64:
4841            if (TLSBaseAddrReg)
4842              I = ReplaceTLSBaseAddrCall(I, TLSBaseAddrReg);
4843            else
4844              I = SetRegister(I, &TLSBaseAddrReg);
4845            Changed = true;
4846            break;
4847          default:
4848            break;
4849        }
4850      }
4851
4852      // Visit the children of this block in the dominator tree.
4853      for (MachineDomTreeNode::iterator I = Node->begin(), E = Node->end();
4854           I != E; ++I) {
4855        Changed |= VisitNode(*I, TLSBaseAddrReg);
4856      }
4857
4858      return Changed;
4859    }
4860
4861    // Replace the TLS_base_addr instruction I with a copy from
4862    // TLSBaseAddrReg, returning the new instruction.
4863    MachineInstr *ReplaceTLSBaseAddrCall(MachineInstr *I,
4864                                         unsigned TLSBaseAddrReg) {
4865      MachineFunction *MF = I->getParent()->getParent();
4866      const X86TargetMachine *TM =
4867          static_cast<const X86TargetMachine *>(&MF->getTarget());
4868      const bool is64Bit = TM->getSubtarget<X86Subtarget>().is64Bit();
4869      const X86InstrInfo *TII = TM->getInstrInfo();
4870
4871      // Insert a Copy from TLSBaseAddrReg to RAX/EAX.
4872      MachineInstr *Copy = BuildMI(*I->getParent(), I, I->getDebugLoc(),
4873                                   TII->get(TargetOpcode::COPY),
4874                                   is64Bit ? X86::RAX : X86::EAX)
4875                                   .addReg(TLSBaseAddrReg);
4876
4877      // Erase the TLS_base_addr instruction.
4878      I->eraseFromParent();
4879
4880      return Copy;
4881    }
4882
4883    // Create a virtal register in *TLSBaseAddrReg, and populate it by
4884    // inserting a copy instruction after I. Returns the new instruction.
4885    MachineInstr *SetRegister(MachineInstr *I, unsigned *TLSBaseAddrReg) {
4886      MachineFunction *MF = I->getParent()->getParent();
4887      const X86TargetMachine *TM =
4888          static_cast<const X86TargetMachine *>(&MF->getTarget());
4889      const bool is64Bit = TM->getSubtarget<X86Subtarget>().is64Bit();
4890      const X86InstrInfo *TII = TM->getInstrInfo();
4891
4892      // Create a virtual register for the TLS base address.
4893      MachineRegisterInfo &RegInfo = MF->getRegInfo();
4894      *TLSBaseAddrReg = RegInfo.createVirtualRegister(is64Bit
4895                                                      ? &X86::GR64RegClass
4896                                                      : &X86::GR32RegClass);
4897
4898      // Insert a copy from RAX/EAX to TLSBaseAddrReg.
4899      MachineInstr *Next = I->getNextNode();
4900      MachineInstr *Copy = BuildMI(*I->getParent(), Next, I->getDebugLoc(),
4901                                   TII->get(TargetOpcode::COPY),
4902                                   *TLSBaseAddrReg)
4903                                   .addReg(is64Bit ? X86::RAX : X86::EAX);
4904
4905      return Copy;
4906    }
4907
4908    virtual const char *getPassName() const {
4909      return "Local Dynamic TLS Access Clean-up";
4910    }
4911
4912    virtual void getAnalysisUsage(AnalysisUsage &AU) const {
4913      AU.setPreservesCFG();
4914      AU.addRequired<MachineDominatorTree>();
4915      MachineFunctionPass::getAnalysisUsage(AU);
4916    }
4917  };
4918}
4919
4920char LDTLSCleanup::ID = 0;
4921FunctionPass*
4922llvm::createCleanupLocalDynamicTLSPass() { return new LDTLSCleanup(); }
4923