X86InstrInfo.cpp revision 7ad42d9ec0af47807f069103a350efc1d5aef0a8
1//===- X86InstrInfo.cpp - X86 Instruction Information -----------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by the LLVM research group and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the X86 implementation of the TargetInstrInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "X86InstrInfo.h" 15#include "X86.h" 16#include "X86GenInstrInfo.inc" 17#include "X86InstrBuilder.h" 18#include "X86Subtarget.h" 19#include "X86TargetMachine.h" 20#include "llvm/ADT/STLExtras.h" 21#include "llvm/CodeGen/MachineInstrBuilder.h" 22#include "llvm/CodeGen/LiveVariables.h" 23#include "llvm/CodeGen/SSARegMap.h" 24#include "llvm/Target/TargetOptions.h" 25#include "llvm/Support/CommandLine.h" 26using namespace llvm; 27 28namespace { 29 cl::opt<bool> 30 EnableCommuteCMove("enable-x86-commute-cmove", 31 cl::desc("Commute conditional moves by inverting conditions")); 32} 33 34X86InstrInfo::X86InstrInfo(X86TargetMachine &tm) 35 : TargetInstrInfo(X86Insts, array_lengthof(X86Insts)), 36 TM(tm), RI(tm, *this) { 37} 38 39bool X86InstrInfo::isMoveInstr(const MachineInstr& MI, 40 unsigned& sourceReg, 41 unsigned& destReg) const { 42 MachineOpCode oc = MI.getOpcode(); 43 if (oc == X86::MOV8rr || oc == X86::MOV16rr || 44 oc == X86::MOV32rr || oc == X86::MOV64rr || 45 oc == X86::MOV16to16_ || oc == X86::MOV32to32_ || 46 oc == X86::MOV_Fp3232 || oc == X86::MOVSSrr || oc == X86::MOVSDrr || 47 oc == X86::MOV_Fp3264 || oc == X86::MOV_Fp6432 || oc == X86::MOV_Fp6464 || 48 oc == X86::FsMOVAPSrr || oc == X86::FsMOVAPDrr || 49 oc == X86::MOVAPSrr || oc == X86::MOVAPDrr || 50 oc == X86::MOVSS2PSrr || oc == X86::MOVSD2PDrr || 51 oc == X86::MOVPS2SSrr || oc == X86::MOVPD2SDrr || 52 oc == X86::MMX_MOVD64rr || oc == X86::MMX_MOVQ64rr) { 53 assert(MI.getNumOperands() >= 2 && 54 MI.getOperand(0).isRegister() && 55 MI.getOperand(1).isRegister() && 56 "invalid register-register move instruction"); 57 sourceReg = MI.getOperand(1).getReg(); 58 destReg = MI.getOperand(0).getReg(); 59 return true; 60 } 61 return false; 62} 63 64unsigned X86InstrInfo::isLoadFromStackSlot(MachineInstr *MI, 65 int &FrameIndex) const { 66 switch (MI->getOpcode()) { 67 default: break; 68 case X86::MOV8rm: 69 case X86::MOV16rm: 70 case X86::MOV16_rm: 71 case X86::MOV32rm: 72 case X86::MOV32_rm: 73 case X86::MOV64rm: 74 case X86::LD_Fp64m: 75 case X86::MOVSSrm: 76 case X86::MOVSDrm: 77 case X86::MOVAPSrm: 78 case X86::MOVAPDrm: 79 case X86::MMX_MOVD64rm: 80 case X86::MMX_MOVQ64rm: 81 if (MI->getOperand(1).isFrameIndex() && MI->getOperand(2).isImmediate() && 82 MI->getOperand(3).isRegister() && MI->getOperand(4).isImmediate() && 83 MI->getOperand(2).getImmedValue() == 1 && 84 MI->getOperand(3).getReg() == 0 && 85 MI->getOperand(4).getImmedValue() == 0) { 86 FrameIndex = MI->getOperand(1).getFrameIndex(); 87 return MI->getOperand(0).getReg(); 88 } 89 break; 90 } 91 return 0; 92} 93 94unsigned X86InstrInfo::isStoreToStackSlot(MachineInstr *MI, 95 int &FrameIndex) const { 96 switch (MI->getOpcode()) { 97 default: break; 98 case X86::MOV8mr: 99 case X86::MOV16mr: 100 case X86::MOV16_mr: 101 case X86::MOV32mr: 102 case X86::MOV32_mr: 103 case X86::MOV64mr: 104 case X86::ST_FpP64m: 105 case X86::MOVSSmr: 106 case X86::MOVSDmr: 107 case X86::MOVAPSmr: 108 case X86::MOVAPDmr: 109 case X86::MMX_MOVD64mr: 110 case X86::MMX_MOVQ64mr: 111 case X86::MMX_MOVNTQmr: 112 if (MI->getOperand(0).isFrameIndex() && MI->getOperand(1).isImmediate() && 113 MI->getOperand(2).isRegister() && MI->getOperand(3).isImmediate() && 114 MI->getOperand(1).getImmedValue() == 1 && 115 MI->getOperand(2).getReg() == 0 && 116 MI->getOperand(3).getImmedValue() == 0) { 117 FrameIndex = MI->getOperand(0).getFrameIndex(); 118 return MI->getOperand(4).getReg(); 119 } 120 break; 121 } 122 return 0; 123} 124 125 126bool X86InstrInfo::isReallyTriviallyReMaterializable(MachineInstr *MI) const { 127 switch (MI->getOpcode()) { 128 default: break; 129 case X86::MOV8rm: 130 case X86::MOV16rm: 131 case X86::MOV16_rm: 132 case X86::MOV32rm: 133 case X86::MOV32_rm: 134 case X86::MOV64rm: 135 case X86::LD_Fp64m: 136 case X86::MOVSSrm: 137 case X86::MOVSDrm: 138 case X86::MOVAPSrm: 139 case X86::MOVAPDrm: 140 case X86::MMX_MOVD64rm: 141 case X86::MMX_MOVQ64rm: 142 // Loads from constant pools are trivially rematerializable. 143 return MI->getOperand(1).isRegister() && MI->getOperand(2).isImmediate() && 144 MI->getOperand(3).isRegister() && MI->getOperand(4).isConstantPoolIndex() && 145 MI->getOperand(1).getReg() == 0 && 146 MI->getOperand(2).getImmedValue() == 1 && 147 MI->getOperand(3).getReg() == 0; 148 } 149 // All other instructions marked M_REMATERIALIZABLE are always trivially 150 // rematerializable. 151 return true; 152} 153 154/// hasLiveCondCodeDef - True if MI has a condition code def, e.g. EFLAGS, that 155/// is not marked dead. 156static bool hasLiveCondCodeDef(MachineInstr *MI) { 157 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 158 MachineOperand &MO = MI->getOperand(i); 159 if (MO.isRegister() && MO.isDef() && 160 MO.getReg() == X86::EFLAGS && !MO.isDead()) { 161 return true; 162 } 163 } 164 return false; 165} 166 167/// convertToThreeAddress - This method must be implemented by targets that 168/// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target 169/// may be able to convert a two-address instruction into a true 170/// three-address instruction on demand. This allows the X86 target (for 171/// example) to convert ADD and SHL instructions into LEA instructions if they 172/// would require register copies due to two-addressness. 173/// 174/// This method returns a null pointer if the transformation cannot be 175/// performed, otherwise it returns the new instruction. 176/// 177MachineInstr * 178X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI, 179 MachineBasicBlock::iterator &MBBI, 180 LiveVariables &LV) const { 181 MachineInstr *MI = MBBI; 182 // All instructions input are two-addr instructions. Get the known operands. 183 unsigned Dest = MI->getOperand(0).getReg(); 184 unsigned Src = MI->getOperand(1).getReg(); 185 186 MachineInstr *NewMI = NULL; 187 // FIXME: 16-bit LEA's are really slow on Athlons, but not bad on P4's. When 188 // we have better subtarget support, enable the 16-bit LEA generation here. 189 bool DisableLEA16 = true; 190 191 unsigned MIOpc = MI->getOpcode(); 192 switch (MIOpc) { 193 case X86::SHUFPSrri: { 194 assert(MI->getNumOperands() == 4 && "Unknown shufps instruction!"); 195 if (!TM.getSubtarget<X86Subtarget>().hasSSE2()) return 0; 196 197 unsigned A = MI->getOperand(0).getReg(); 198 unsigned B = MI->getOperand(1).getReg(); 199 unsigned C = MI->getOperand(2).getReg(); 200 unsigned M = MI->getOperand(3).getImm(); 201 if (B != C) return 0; 202 NewMI = BuildMI(get(X86::PSHUFDri), A).addReg(B).addImm(M); 203 break; 204 } 205 case X86::SHL64ri: { 206 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!"); 207 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses 208 // the flags produced by a shift yet, so this is safe. 209 unsigned Dest = MI->getOperand(0).getReg(); 210 unsigned Src = MI->getOperand(1).getReg(); 211 unsigned ShAmt = MI->getOperand(2).getImm(); 212 if (ShAmt == 0 || ShAmt >= 4) return 0; 213 214 NewMI = BuildMI(get(X86::LEA64r), Dest) 215 .addReg(0).addImm(1 << ShAmt).addReg(Src).addImm(0); 216 break; 217 } 218 case X86::SHL32ri: { 219 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!"); 220 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses 221 // the flags produced by a shift yet, so this is safe. 222 unsigned Dest = MI->getOperand(0).getReg(); 223 unsigned Src = MI->getOperand(1).getReg(); 224 unsigned ShAmt = MI->getOperand(2).getImm(); 225 if (ShAmt == 0 || ShAmt >= 4) return 0; 226 227 unsigned Opc = TM.getSubtarget<X86Subtarget>().is64Bit() ? 228 X86::LEA64_32r : X86::LEA32r; 229 NewMI = BuildMI(get(Opc), Dest) 230 .addReg(0).addImm(1 << ShAmt).addReg(Src).addImm(0); 231 break; 232 } 233 case X86::SHL16ri: { 234 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!"); 235 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses 236 // the flags produced by a shift yet, so this is safe. 237 unsigned Dest = MI->getOperand(0).getReg(); 238 unsigned Src = MI->getOperand(1).getReg(); 239 unsigned ShAmt = MI->getOperand(2).getImm(); 240 if (ShAmt == 0 || ShAmt >= 4) return 0; 241 242 if (DisableLEA16) { 243 // If 16-bit LEA is disabled, use 32-bit LEA via subregisters. 244 SSARegMap *RegMap = MFI->getParent()->getSSARegMap(); 245 unsigned Opc = TM.getSubtarget<X86Subtarget>().is64Bit() 246 ? X86::LEA64_32r : X86::LEA32r; 247 unsigned leaInReg = RegMap->createVirtualRegister(&X86::GR32RegClass); 248 unsigned leaOutReg = RegMap->createVirtualRegister(&X86::GR32RegClass); 249 250 MachineInstr *Ins = 251 BuildMI(get(X86::INSERT_SUBREG), leaInReg).addReg(Src).addImm(2); 252 Ins->copyKillDeadInfo(MI); 253 254 NewMI = BuildMI(get(Opc), leaOutReg) 255 .addReg(0).addImm(1 << ShAmt).addReg(leaInReg).addImm(0); 256 257 MachineInstr *Ext = 258 BuildMI(get(X86::EXTRACT_SUBREG), Dest).addReg(leaOutReg).addImm(2); 259 Ext->copyKillDeadInfo(MI); 260 261 MFI->insert(MBBI, Ins); // Insert the insert_subreg 262 LV.instructionChanged(MI, NewMI); // Update live variables 263 LV.addVirtualRegisterKilled(leaInReg, NewMI); 264 MFI->insert(MBBI, NewMI); // Insert the new inst 265 LV.addVirtualRegisterKilled(leaOutReg, Ext); 266 MFI->insert(MBBI, Ext); // Insert the extract_subreg 267 return Ext; 268 } else { 269 NewMI = BuildMI(get(X86::LEA16r), Dest) 270 .addReg(0).addImm(1 << ShAmt).addReg(Src).addImm(0); 271 } 272 break; 273 } 274 default: { 275 // The following opcodes also sets the condition code register(s). Only 276 // convert them to equivalent lea if the condition code register def's 277 // are dead! 278 if (hasLiveCondCodeDef(MI)) 279 return 0; 280 281 switch (MIOpc) { 282 default: return 0; 283 case X86::INC64r: 284 case X86::INC32r: { 285 assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!"); 286 unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r : X86::LEA32r; 287 NewMI = addRegOffset(BuildMI(get(Opc), Dest), Src, 1); 288 break; 289 } 290 case X86::INC16r: 291 case X86::INC64_16r: 292 if (DisableLEA16) return 0; 293 assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!"); 294 NewMI = addRegOffset(BuildMI(get(X86::LEA16r), Dest), Src, 1); 295 break; 296 case X86::DEC64r: 297 case X86::DEC32r: { 298 assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!"); 299 unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r : X86::LEA32r; 300 NewMI = addRegOffset(BuildMI(get(Opc), Dest), Src, -1); 301 break; 302 } 303 case X86::DEC16r: 304 case X86::DEC64_16r: 305 if (DisableLEA16) return 0; 306 assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!"); 307 NewMI = addRegOffset(BuildMI(get(X86::LEA16r), Dest), Src, -1); 308 break; 309 case X86::ADD64rr: 310 case X86::ADD32rr: { 311 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!"); 312 unsigned Opc = MIOpc == X86::ADD64rr ? X86::LEA64r : X86::LEA32r; 313 NewMI = addRegReg(BuildMI(get(Opc), Dest), Src, 314 MI->getOperand(2).getReg()); 315 break; 316 } 317 case X86::ADD16rr: 318 if (DisableLEA16) return 0; 319 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!"); 320 NewMI = addRegReg(BuildMI(get(X86::LEA16r), Dest), Src, 321 MI->getOperand(2).getReg()); 322 break; 323 case X86::ADD64ri32: 324 case X86::ADD64ri8: 325 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!"); 326 if (MI->getOperand(2).isImmediate()) 327 NewMI = addRegOffset(BuildMI(get(X86::LEA64r), Dest), Src, 328 MI->getOperand(2).getImmedValue()); 329 break; 330 case X86::ADD32ri: 331 case X86::ADD32ri8: 332 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!"); 333 if (MI->getOperand(2).isImmediate()) 334 NewMI = addRegOffset(BuildMI(get(X86::LEA32r), Dest), Src, 335 MI->getOperand(2).getImmedValue()); 336 break; 337 case X86::ADD16ri: 338 case X86::ADD16ri8: 339 if (DisableLEA16) return 0; 340 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!"); 341 if (MI->getOperand(2).isImmediate()) 342 NewMI = addRegOffset(BuildMI(get(X86::LEA16r), Dest), Src, 343 MI->getOperand(2).getImmedValue()); 344 break; 345 case X86::SHL16ri: 346 if (DisableLEA16) return 0; 347 case X86::SHL32ri: 348 case X86::SHL64ri: { 349 assert(MI->getNumOperands() >= 3 && MI->getOperand(2).isImmediate() && 350 "Unknown shl instruction!"); 351 unsigned ShAmt = MI->getOperand(2).getImmedValue(); 352 if (ShAmt == 1 || ShAmt == 2 || ShAmt == 3) { 353 X86AddressMode AM; 354 AM.Scale = 1 << ShAmt; 355 AM.IndexReg = Src; 356 unsigned Opc = MIOpc == X86::SHL64ri ? X86::LEA64r 357 : (MIOpc == X86::SHL32ri ? X86::LEA32r : X86::LEA16r); 358 NewMI = addFullAddress(BuildMI(get(Opc), Dest), AM); 359 } 360 break; 361 } 362 } 363 } 364 } 365 366 NewMI->copyKillDeadInfo(MI); 367 LV.instructionChanged(MI, NewMI); // Update live variables 368 MFI->insert(MBBI, NewMI); // Insert the new inst 369 return NewMI; 370} 371 372/// commuteInstruction - We have a few instructions that must be hacked on to 373/// commute them. 374/// 375MachineInstr *X86InstrInfo::commuteInstruction(MachineInstr *MI) const { 376 switch (MI->getOpcode()) { 377 case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I) 378 case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I) 379 case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I) 380 case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I) 381 case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I -> A = SHLD64rri8 C, B, (64-I) 382 case X86::SHLD64rri8:{// A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, (64-I) 383 unsigned Opc; 384 unsigned Size; 385 switch (MI->getOpcode()) { 386 default: assert(0 && "Unreachable!"); 387 case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break; 388 case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break; 389 case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break; 390 case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break; 391 case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break; 392 case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break; 393 } 394 unsigned Amt = MI->getOperand(3).getImmedValue(); 395 unsigned A = MI->getOperand(0).getReg(); 396 unsigned B = MI->getOperand(1).getReg(); 397 unsigned C = MI->getOperand(2).getReg(); 398 bool BisKill = MI->getOperand(1).isKill(); 399 bool CisKill = MI->getOperand(2).isKill(); 400 return BuildMI(get(Opc), A).addReg(C, false, false, CisKill) 401 .addReg(B, false, false, BisKill).addImm(Size-Amt); 402 } 403 case X86::CMOVB16rr: 404 case X86::CMOVB32rr: 405 case X86::CMOVB64rr: 406 case X86::CMOVAE16rr: 407 case X86::CMOVAE32rr: 408 case X86::CMOVAE64rr: 409 case X86::CMOVE16rr: 410 case X86::CMOVE32rr: 411 case X86::CMOVE64rr: 412 case X86::CMOVNE16rr: 413 case X86::CMOVNE32rr: 414 case X86::CMOVNE64rr: 415 case X86::CMOVBE16rr: 416 case X86::CMOVBE32rr: 417 case X86::CMOVBE64rr: 418 case X86::CMOVA16rr: 419 case X86::CMOVA32rr: 420 case X86::CMOVA64rr: 421 case X86::CMOVL16rr: 422 case X86::CMOVL32rr: 423 case X86::CMOVL64rr: 424 case X86::CMOVGE16rr: 425 case X86::CMOVGE32rr: 426 case X86::CMOVGE64rr: 427 case X86::CMOVLE16rr: 428 case X86::CMOVLE32rr: 429 case X86::CMOVLE64rr: 430 case X86::CMOVG16rr: 431 case X86::CMOVG32rr: 432 case X86::CMOVG64rr: 433 case X86::CMOVS16rr: 434 case X86::CMOVS32rr: 435 case X86::CMOVS64rr: 436 case X86::CMOVNS16rr: 437 case X86::CMOVNS32rr: 438 case X86::CMOVNS64rr: 439 case X86::CMOVP16rr: 440 case X86::CMOVP32rr: 441 case X86::CMOVP64rr: 442 case X86::CMOVNP16rr: 443 case X86::CMOVNP32rr: 444 case X86::CMOVNP64rr: { 445 if (!EnableCommuteCMove) 446 return 0; 447 unsigned Opc = 0; 448 switch (MI->getOpcode()) { 449 default: break; 450 case X86::CMOVB16rr: Opc = X86::CMOVAE16rr; break; 451 case X86::CMOVB32rr: Opc = X86::CMOVAE32rr; break; 452 case X86::CMOVB64rr: Opc = X86::CMOVAE64rr; break; 453 case X86::CMOVAE16rr: Opc = X86::CMOVB16rr; break; 454 case X86::CMOVAE32rr: Opc = X86::CMOVB32rr; break; 455 case X86::CMOVAE64rr: Opc = X86::CMOVB64rr; break; 456 case X86::CMOVE16rr: Opc = X86::CMOVNE16rr; break; 457 case X86::CMOVE32rr: Opc = X86::CMOVNE32rr; break; 458 case X86::CMOVE64rr: Opc = X86::CMOVNE64rr; break; 459 case X86::CMOVNE16rr: Opc = X86::CMOVE16rr; break; 460 case X86::CMOVNE32rr: Opc = X86::CMOVE32rr; break; 461 case X86::CMOVNE64rr: Opc = X86::CMOVE64rr; break; 462 case X86::CMOVBE16rr: Opc = X86::CMOVA16rr; break; 463 case X86::CMOVBE32rr: Opc = X86::CMOVA32rr; break; 464 case X86::CMOVBE64rr: Opc = X86::CMOVA64rr; break; 465 case X86::CMOVA16rr: Opc = X86::CMOVBE16rr; break; 466 case X86::CMOVA32rr: Opc = X86::CMOVBE32rr; break; 467 case X86::CMOVA64rr: Opc = X86::CMOVBE64rr; break; 468 case X86::CMOVL16rr: Opc = X86::CMOVGE16rr; break; 469 case X86::CMOVL32rr: Opc = X86::CMOVGE32rr; break; 470 case X86::CMOVL64rr: Opc = X86::CMOVGE64rr; break; 471 case X86::CMOVGE16rr: Opc = X86::CMOVL16rr; break; 472 case X86::CMOVGE32rr: Opc = X86::CMOVL32rr; break; 473 case X86::CMOVGE64rr: Opc = X86::CMOVL64rr; break; 474 case X86::CMOVLE16rr: Opc = X86::CMOVG16rr; break; 475 case X86::CMOVLE32rr: Opc = X86::CMOVG32rr; break; 476 case X86::CMOVLE64rr: Opc = X86::CMOVG64rr; break; 477 case X86::CMOVG16rr: Opc = X86::CMOVLE16rr; break; 478 case X86::CMOVG32rr: Opc = X86::CMOVLE32rr; break; 479 case X86::CMOVG64rr: Opc = X86::CMOVLE64rr; break; 480 case X86::CMOVS16rr: Opc = X86::CMOVNS16rr; break; 481 case X86::CMOVS32rr: Opc = X86::CMOVNS32rr; break; 482 case X86::CMOVS64rr: Opc = X86::CMOVNS32rr; break; 483 case X86::CMOVNS16rr: Opc = X86::CMOVS16rr; break; 484 case X86::CMOVNS32rr: Opc = X86::CMOVS32rr; break; 485 case X86::CMOVNS64rr: Opc = X86::CMOVS64rr; break; 486 case X86::CMOVP16rr: Opc = X86::CMOVNP16rr; break; 487 case X86::CMOVP32rr: Opc = X86::CMOVNP32rr; break; 488 case X86::CMOVP64rr: Opc = X86::CMOVNP32rr; break; 489 case X86::CMOVNP16rr: Opc = X86::CMOVP16rr; break; 490 case X86::CMOVNP32rr: Opc = X86::CMOVP32rr; break; 491 case X86::CMOVNP64rr: Opc = X86::CMOVP64rr; break; 492 } 493 494 MI->setInstrDescriptor(get(Opc)); 495 // Fallthrough intended. 496 } 497 default: 498 return TargetInstrInfo::commuteInstruction(MI); 499 } 500} 501 502static X86::CondCode GetCondFromBranchOpc(unsigned BrOpc) { 503 switch (BrOpc) { 504 default: return X86::COND_INVALID; 505 case X86::JE: return X86::COND_E; 506 case X86::JNE: return X86::COND_NE; 507 case X86::JL: return X86::COND_L; 508 case X86::JLE: return X86::COND_LE; 509 case X86::JG: return X86::COND_G; 510 case X86::JGE: return X86::COND_GE; 511 case X86::JB: return X86::COND_B; 512 case X86::JBE: return X86::COND_BE; 513 case X86::JA: return X86::COND_A; 514 case X86::JAE: return X86::COND_AE; 515 case X86::JS: return X86::COND_S; 516 case X86::JNS: return X86::COND_NS; 517 case X86::JP: return X86::COND_P; 518 case X86::JNP: return X86::COND_NP; 519 case X86::JO: return X86::COND_O; 520 case X86::JNO: return X86::COND_NO; 521 } 522} 523 524unsigned X86::GetCondBranchFromCond(X86::CondCode CC) { 525 switch (CC) { 526 default: assert(0 && "Illegal condition code!"); 527 case X86::COND_E: return X86::JE; 528 case X86::COND_NE: return X86::JNE; 529 case X86::COND_L: return X86::JL; 530 case X86::COND_LE: return X86::JLE; 531 case X86::COND_G: return X86::JG; 532 case X86::COND_GE: return X86::JGE; 533 case X86::COND_B: return X86::JB; 534 case X86::COND_BE: return X86::JBE; 535 case X86::COND_A: return X86::JA; 536 case X86::COND_AE: return X86::JAE; 537 case X86::COND_S: return X86::JS; 538 case X86::COND_NS: return X86::JNS; 539 case X86::COND_P: return X86::JP; 540 case X86::COND_NP: return X86::JNP; 541 case X86::COND_O: return X86::JO; 542 case X86::COND_NO: return X86::JNO; 543 } 544} 545 546/// GetOppositeBranchCondition - Return the inverse of the specified condition, 547/// e.g. turning COND_E to COND_NE. 548X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) { 549 switch (CC) { 550 default: assert(0 && "Illegal condition code!"); 551 case X86::COND_E: return X86::COND_NE; 552 case X86::COND_NE: return X86::COND_E; 553 case X86::COND_L: return X86::COND_GE; 554 case X86::COND_LE: return X86::COND_G; 555 case X86::COND_G: return X86::COND_LE; 556 case X86::COND_GE: return X86::COND_L; 557 case X86::COND_B: return X86::COND_AE; 558 case X86::COND_BE: return X86::COND_A; 559 case X86::COND_A: return X86::COND_BE; 560 case X86::COND_AE: return X86::COND_B; 561 case X86::COND_S: return X86::COND_NS; 562 case X86::COND_NS: return X86::COND_S; 563 case X86::COND_P: return X86::COND_NP; 564 case X86::COND_NP: return X86::COND_P; 565 case X86::COND_O: return X86::COND_NO; 566 case X86::COND_NO: return X86::COND_O; 567 } 568} 569 570bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const { 571 const TargetInstrDescriptor *TID = MI->getInstrDescriptor(); 572 if (TID->Flags & M_TERMINATOR_FLAG) { 573 // Conditional branch is a special case. 574 if ((TID->Flags & M_BRANCH_FLAG) != 0 && (TID->Flags & M_BARRIER_FLAG) == 0) 575 return true; 576 if ((TID->Flags & M_PREDICABLE) == 0) 577 return true; 578 return !isPredicated(MI); 579 } 580 return false; 581} 582 583// For purposes of branch analysis do not count FP_REG_KILL as a terminator. 584static bool isBrAnalysisUnpredicatedTerminator(const MachineInstr *MI, 585 const X86InstrInfo &TII) { 586 if (MI->getOpcode() == X86::FP_REG_KILL) 587 return false; 588 return TII.isUnpredicatedTerminator(MI); 589} 590 591bool X86InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, 592 MachineBasicBlock *&TBB, 593 MachineBasicBlock *&FBB, 594 std::vector<MachineOperand> &Cond) const { 595 // If the block has no terminators, it just falls into the block after it. 596 MachineBasicBlock::iterator I = MBB.end(); 597 if (I == MBB.begin() || !isBrAnalysisUnpredicatedTerminator(--I, *this)) 598 return false; 599 600 // Get the last instruction in the block. 601 MachineInstr *LastInst = I; 602 603 // If there is only one terminator instruction, process it. 604 if (I == MBB.begin() || !isBrAnalysisUnpredicatedTerminator(--I, *this)) { 605 if (!isBranch(LastInst->getOpcode())) 606 return true; 607 608 // If the block ends with a branch there are 3 possibilities: 609 // it's an unconditional, conditional, or indirect branch. 610 611 if (LastInst->getOpcode() == X86::JMP) { 612 TBB = LastInst->getOperand(0).getMachineBasicBlock(); 613 return false; 614 } 615 X86::CondCode BranchCode = GetCondFromBranchOpc(LastInst->getOpcode()); 616 if (BranchCode == X86::COND_INVALID) 617 return true; // Can't handle indirect branch. 618 619 // Otherwise, block ends with fall-through condbranch. 620 TBB = LastInst->getOperand(0).getMachineBasicBlock(); 621 Cond.push_back(MachineOperand::CreateImm(BranchCode)); 622 return false; 623 } 624 625 // Get the instruction before it if it's a terminator. 626 MachineInstr *SecondLastInst = I; 627 628 // If there are three terminators, we don't know what sort of block this is. 629 if (SecondLastInst && I != MBB.begin() && 630 isBrAnalysisUnpredicatedTerminator(--I, *this)) 631 return true; 632 633 // If the block ends with X86::JMP and a conditional branch, handle it. 634 X86::CondCode BranchCode = GetCondFromBranchOpc(SecondLastInst->getOpcode()); 635 if (BranchCode != X86::COND_INVALID && LastInst->getOpcode() == X86::JMP) { 636 TBB = SecondLastInst->getOperand(0).getMachineBasicBlock(); 637 Cond.push_back(MachineOperand::CreateImm(BranchCode)); 638 FBB = LastInst->getOperand(0).getMachineBasicBlock(); 639 return false; 640 } 641 642 // If the block ends with two X86::JMPs, handle it. The second one is not 643 // executed, so remove it. 644 if (SecondLastInst->getOpcode() == X86::JMP && 645 LastInst->getOpcode() == X86::JMP) { 646 TBB = SecondLastInst->getOperand(0).getMachineBasicBlock(); 647 I = LastInst; 648 I->eraseFromParent(); 649 return false; 650 } 651 652 // Otherwise, can't handle this. 653 return true; 654} 655 656unsigned X86InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const { 657 MachineBasicBlock::iterator I = MBB.end(); 658 if (I == MBB.begin()) return 0; 659 --I; 660 if (I->getOpcode() != X86::JMP && 661 GetCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID) 662 return 0; 663 664 // Remove the branch. 665 I->eraseFromParent(); 666 667 I = MBB.end(); 668 669 if (I == MBB.begin()) return 1; 670 --I; 671 if (GetCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID) 672 return 1; 673 674 // Remove the branch. 675 I->eraseFromParent(); 676 return 2; 677} 678 679unsigned 680X86InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 681 MachineBasicBlock *FBB, 682 const std::vector<MachineOperand> &Cond) const { 683 // Shouldn't be a fall through. 684 assert(TBB && "InsertBranch must not be told to insert a fallthrough"); 685 assert((Cond.size() == 1 || Cond.size() == 0) && 686 "X86 branch conditions have one component!"); 687 688 if (FBB == 0) { // One way branch. 689 if (Cond.empty()) { 690 // Unconditional branch? 691 BuildMI(&MBB, get(X86::JMP)).addMBB(TBB); 692 } else { 693 // Conditional branch. 694 unsigned Opc = GetCondBranchFromCond((X86::CondCode)Cond[0].getImm()); 695 BuildMI(&MBB, get(Opc)).addMBB(TBB); 696 } 697 return 1; 698 } 699 700 // Two-way Conditional branch. 701 unsigned Opc = GetCondBranchFromCond((X86::CondCode)Cond[0].getImm()); 702 BuildMI(&MBB, get(Opc)).addMBB(TBB); 703 BuildMI(&MBB, get(X86::JMP)).addMBB(FBB); 704 return 2; 705} 706 707bool X86InstrInfo::BlockHasNoFallThrough(MachineBasicBlock &MBB) const { 708 if (MBB.empty()) return false; 709 710 switch (MBB.back().getOpcode()) { 711 case X86::RET: // Return. 712 case X86::RETI: 713 case X86::TAILJMPd: 714 case X86::TAILJMPr: 715 case X86::TAILJMPm: 716 case X86::JMP: // Uncond branch. 717 case X86::JMP32r: // Indirect branch. 718 case X86::JMP64r: // Indirect branch (64-bit). 719 case X86::JMP32m: // Indirect branch through mem. 720 case X86::JMP64m: // Indirect branch through mem (64-bit). 721 return true; 722 default: return false; 723 } 724} 725 726bool X86InstrInfo:: 727ReverseBranchCondition(std::vector<MachineOperand> &Cond) const { 728 assert(Cond.size() == 1 && "Invalid X86 branch condition!"); 729 Cond[0].setImm(GetOppositeBranchCondition((X86::CondCode)Cond[0].getImm())); 730 return false; 731} 732 733const TargetRegisterClass *X86InstrInfo::getPointerRegClass() const { 734 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>(); 735 if (Subtarget->is64Bit()) 736 return &X86::GR64RegClass; 737 else 738 return &X86::GR32RegClass; 739} 740