X86InstrInfo.cpp revision 97e6992e3ecfd354a53142f0488769b399242295 
1//===- X86InstrInfo.cpp - X86 Instruction Information -----------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the X86 implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "X86InstrInfo.h"
15#include "X86.h"
16#include "X86GenInstrInfo.inc"
17#include "X86InstrBuilder.h"
18#include "X86MachineFunctionInfo.h"
19#include "X86Subtarget.h"
20#include "X86TargetMachine.h"
21#include "llvm/DerivedTypes.h"
22#include "llvm/LLVMContext.h"
23#include "llvm/ADT/STLExtras.h"
24#include "llvm/CodeGen/MachineConstantPool.h"
25#include "llvm/CodeGen/MachineFrameInfo.h"
26#include "llvm/CodeGen/MachineInstrBuilder.h"
27#include "llvm/CodeGen/MachineRegisterInfo.h"
28#include "llvm/CodeGen/LiveVariables.h"
29#include "llvm/CodeGen/PseudoSourceValue.h"
30#include "llvm/Support/CommandLine.h"
31#include "llvm/Support/Debug.h"
32#include "llvm/Support/ErrorHandling.h"
33#include "llvm/Support/raw_ostream.h"
34#include "llvm/Target/TargetOptions.h"
35#include "llvm/MC/MCAsmInfo.h"
36
37#include <limits>
38
39using namespace llvm;
40
41static cl::opt<bool>
42NoFusing("disable-spill-fusing",
43         cl::desc("Disable fusing of spill code into instructions"));
44static cl::opt<bool>
45PrintFailedFusing("print-failed-fuse-candidates",
46                  cl::desc("Print instructions that the allocator wants to"
47                           " fuse, but the X86 backend currently can't"),
48                  cl::Hidden);
49static cl::opt<bool>
50ReMatPICStubLoad("remat-pic-stub-load",
51                 cl::desc("Re-materialize load from stub in PIC mode"),
52                 cl::init(false), cl::Hidden);
53
54X86InstrInfo::X86InstrInfo(X86TargetMachine &tm)
55  : TargetInstrInfoImpl(X86Insts, array_lengthof(X86Insts)),
56    TM(tm), RI(tm, *this) {
57  SmallVector<unsigned,16> AmbEntries;
58  static const unsigned OpTbl2Addr[][2] = {
59    { X86::ADC32ri,     X86::ADC32mi },
60    { X86::ADC32ri8,    X86::ADC32mi8 },
61    { X86::ADC32rr,     X86::ADC32mr },
62    { X86::ADC64ri32,   X86::ADC64mi32 },
63    { X86::ADC64ri8,    X86::ADC64mi8 },
64    { X86::ADC64rr,     X86::ADC64mr },
65    { X86::ADD16ri,     X86::ADD16mi },
66    { X86::ADD16ri8,    X86::ADD16mi8 },
67    { X86::ADD16rr,     X86::ADD16mr },
68    { X86::ADD32ri,     X86::ADD32mi },
69    { X86::ADD32ri8,    X86::ADD32mi8 },
70    { X86::ADD32rr,     X86::ADD32mr },
71    { X86::ADD64ri32,   X86::ADD64mi32 },
72    { X86::ADD64ri8,    X86::ADD64mi8 },
73    { X86::ADD64rr,     X86::ADD64mr },
74    { X86::ADD8ri,      X86::ADD8mi },
75    { X86::ADD8rr,      X86::ADD8mr },
76    { X86::AND16ri,     X86::AND16mi },
77    { X86::AND16ri8,    X86::AND16mi8 },
78    { X86::AND16rr,     X86::AND16mr },
79    { X86::AND32ri,     X86::AND32mi },
80    { X86::AND32ri8,    X86::AND32mi8 },
81    { X86::AND32rr,     X86::AND32mr },
82    { X86::AND64ri32,   X86::AND64mi32 },
83    { X86::AND64ri8,    X86::AND64mi8 },
84    { X86::AND64rr,     X86::AND64mr },
85    { X86::AND8ri,      X86::AND8mi },
86    { X86::AND8rr,      X86::AND8mr },
87    { X86::DEC16r,      X86::DEC16m },
88    { X86::DEC32r,      X86::DEC32m },
89    { X86::DEC64_16r,   X86::DEC64_16m },
90    { X86::DEC64_32r,   X86::DEC64_32m },
91    { X86::DEC64r,      X86::DEC64m },
92    { X86::DEC8r,       X86::DEC8m },
93    { X86::INC16r,      X86::INC16m },
94    { X86::INC32r,      X86::INC32m },
95    { X86::INC64_16r,   X86::INC64_16m },
96    { X86::INC64_32r,   X86::INC64_32m },
97    { X86::INC64r,      X86::INC64m },
98    { X86::INC8r,       X86::INC8m },
99    { X86::NEG16r,      X86::NEG16m },
100    { X86::NEG32r,      X86::NEG32m },
101    { X86::NEG64r,      X86::NEG64m },
102    { X86::NEG8r,       X86::NEG8m },
103    { X86::NOT16r,      X86::NOT16m },
104    { X86::NOT32r,      X86::NOT32m },
105    { X86::NOT64r,      X86::NOT64m },
106    { X86::NOT8r,       X86::NOT8m },
107    { X86::OR16ri,      X86::OR16mi },
108    { X86::OR16ri8,     X86::OR16mi8 },
109    { X86::OR16rr,      X86::OR16mr },
110    { X86::OR32ri,      X86::OR32mi },
111    { X86::OR32ri8,     X86::OR32mi8 },
112    { X86::OR32rr,      X86::OR32mr },
113    { X86::OR64ri32,    X86::OR64mi32 },
114    { X86::OR64ri8,     X86::OR64mi8 },
115    { X86::OR64rr,      X86::OR64mr },
116    { X86::OR8ri,       X86::OR8mi },
117    { X86::OR8rr,       X86::OR8mr },
118    { X86::ROL16r1,     X86::ROL16m1 },
119    { X86::ROL16rCL,    X86::ROL16mCL },
120    { X86::ROL16ri,     X86::ROL16mi },
121    { X86::ROL32r1,     X86::ROL32m1 },
122    { X86::ROL32rCL,    X86::ROL32mCL },
123    { X86::ROL32ri,     X86::ROL32mi },
124    { X86::ROL64r1,     X86::ROL64m1 },
125    { X86::ROL64rCL,    X86::ROL64mCL },
126    { X86::ROL64ri,     X86::ROL64mi },
127    { X86::ROL8r1,      X86::ROL8m1 },
128    { X86::ROL8rCL,     X86::ROL8mCL },
129    { X86::ROL8ri,      X86::ROL8mi },
130    { X86::ROR16r1,     X86::ROR16m1 },
131    { X86::ROR16rCL,    X86::ROR16mCL },
132    { X86::ROR16ri,     X86::ROR16mi },
133    { X86::ROR32r1,     X86::ROR32m1 },
134    { X86::ROR32rCL,    X86::ROR32mCL },
135    { X86::ROR32ri,     X86::ROR32mi },
136    { X86::ROR64r1,     X86::ROR64m1 },
137    { X86::ROR64rCL,    X86::ROR64mCL },
138    { X86::ROR64ri,     X86::ROR64mi },
139    { X86::ROR8r1,      X86::ROR8m1 },
140    { X86::ROR8rCL,     X86::ROR8mCL },
141    { X86::ROR8ri,      X86::ROR8mi },
142    { X86::SAR16r1,     X86::SAR16m1 },
143    { X86::SAR16rCL,    X86::SAR16mCL },
144    { X86::SAR16ri,     X86::SAR16mi },
145    { X86::SAR32r1,     X86::SAR32m1 },
146    { X86::SAR32rCL,    X86::SAR32mCL },
147    { X86::SAR32ri,     X86::SAR32mi },
148    { X86::SAR64r1,     X86::SAR64m1 },
149    { X86::SAR64rCL,    X86::SAR64mCL },
150    { X86::SAR64ri,     X86::SAR64mi },
151    { X86::SAR8r1,      X86::SAR8m1 },
152    { X86::SAR8rCL,     X86::SAR8mCL },
153    { X86::SAR8ri,      X86::SAR8mi },
154    { X86::SBB32ri,     X86::SBB32mi },
155    { X86::SBB32ri8,    X86::SBB32mi8 },
156    { X86::SBB32rr,     X86::SBB32mr },
157    { X86::SBB64ri32,   X86::SBB64mi32 },
158    { X86::SBB64ri8,    X86::SBB64mi8 },
159    { X86::SBB64rr,     X86::SBB64mr },
160    { X86::SHL16rCL,    X86::SHL16mCL },
161    { X86::SHL16ri,     X86::SHL16mi },
162    { X86::SHL32rCL,    X86::SHL32mCL },
163    { X86::SHL32ri,     X86::SHL32mi },
164    { X86::SHL64rCL,    X86::SHL64mCL },
165    { X86::SHL64ri,     X86::SHL64mi },
166    { X86::SHL8rCL,     X86::SHL8mCL },
167    { X86::SHL8ri,      X86::SHL8mi },
168    { X86::SHLD16rrCL,  X86::SHLD16mrCL },
169    { X86::SHLD16rri8,  X86::SHLD16mri8 },
170    { X86::SHLD32rrCL,  X86::SHLD32mrCL },
171    { X86::SHLD32rri8,  X86::SHLD32mri8 },
172    { X86::SHLD64rrCL,  X86::SHLD64mrCL },
173    { X86::SHLD64rri8,  X86::SHLD64mri8 },
174    { X86::SHR16r1,     X86::SHR16m1 },
175    { X86::SHR16rCL,    X86::SHR16mCL },
176    { X86::SHR16ri,     X86::SHR16mi },
177    { X86::SHR32r1,     X86::SHR32m1 },
178    { X86::SHR32rCL,    X86::SHR32mCL },
179    { X86::SHR32ri,     X86::SHR32mi },
180    { X86::SHR64r1,     X86::SHR64m1 },
181    { X86::SHR64rCL,    X86::SHR64mCL },
182    { X86::SHR64ri,     X86::SHR64mi },
183    { X86::SHR8r1,      X86::SHR8m1 },
184    { X86::SHR8rCL,     X86::SHR8mCL },
185    { X86::SHR8ri,      X86::SHR8mi },
186    { X86::SHRD16rrCL,  X86::SHRD16mrCL },
187    { X86::SHRD16rri8,  X86::SHRD16mri8 },
188    { X86::SHRD32rrCL,  X86::SHRD32mrCL },
189    { X86::SHRD32rri8,  X86::SHRD32mri8 },
190    { X86::SHRD64rrCL,  X86::SHRD64mrCL },
191    { X86::SHRD64rri8,  X86::SHRD64mri8 },
192    { X86::SUB16ri,     X86::SUB16mi },
193    { X86::SUB16ri8,    X86::SUB16mi8 },
194    { X86::SUB16rr,     X86::SUB16mr },
195    { X86::SUB32ri,     X86::SUB32mi },
196    { X86::SUB32ri8,    X86::SUB32mi8 },
197    { X86::SUB32rr,     X86::SUB32mr },
198    { X86::SUB64ri32,   X86::SUB64mi32 },
199    { X86::SUB64ri8,    X86::SUB64mi8 },
200    { X86::SUB64rr,     X86::SUB64mr },
201    { X86::SUB8ri,      X86::SUB8mi },
202    { X86::SUB8rr,      X86::SUB8mr },
203    { X86::XOR16ri,     X86::XOR16mi },
204    { X86::XOR16ri8,    X86::XOR16mi8 },
205    { X86::XOR16rr,     X86::XOR16mr },
206    { X86::XOR32ri,     X86::XOR32mi },
207    { X86::XOR32ri8,    X86::XOR32mi8 },
208    { X86::XOR32rr,     X86::XOR32mr },
209    { X86::XOR64ri32,   X86::XOR64mi32 },
210    { X86::XOR64ri8,    X86::XOR64mi8 },
211    { X86::XOR64rr,     X86::XOR64mr },
212    { X86::XOR8ri,      X86::XOR8mi },
213    { X86::XOR8rr,      X86::XOR8mr }
214  };
215
216  for (unsigned i = 0, e = array_lengthof(OpTbl2Addr); i != e; ++i) {
217    unsigned RegOp = OpTbl2Addr[i][0];
218    unsigned MemOp = OpTbl2Addr[i][1];
219    if (!RegOp2MemOpTable2Addr.insert(std::make_pair((unsigned*)RegOp,
220                                               std::make_pair(MemOp,0))).second)
221      assert(false && "Duplicated entries?");
222    // Index 0, folded load and store, no alignment requirement.
223    unsigned AuxInfo = 0 | (1 << 4) | (1 << 5);
224    if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp,
225                                                std::make_pair(RegOp,
226                                                              AuxInfo))).second)
227      AmbEntries.push_back(MemOp);
228  }
229
230  // If the third value is 1, then it's folding either a load or a store.
231  static const unsigned OpTbl0[][4] = {
232    { X86::BT16ri8,     X86::BT16mi8, 1, 0 },
233    { X86::BT32ri8,     X86::BT32mi8, 1, 0 },
234    { X86::BT64ri8,     X86::BT64mi8, 1, 0 },
235    { X86::CALL32r,     X86::CALL32m, 1, 0 },
236    { X86::CALL64r,     X86::CALL64m, 1, 0 },
237    { X86::CMP16ri,     X86::CMP16mi, 1, 0 },
238    { X86::CMP16ri8,    X86::CMP16mi8, 1, 0 },
239    { X86::CMP16rr,     X86::CMP16mr, 1, 0 },
240    { X86::CMP32ri,     X86::CMP32mi, 1, 0 },
241    { X86::CMP32ri8,    X86::CMP32mi8, 1, 0 },
242    { X86::CMP32rr,     X86::CMP32mr, 1, 0 },
243    { X86::CMP64ri32,   X86::CMP64mi32, 1, 0 },
244    { X86::CMP64ri8,    X86::CMP64mi8, 1, 0 },
245    { X86::CMP64rr,     X86::CMP64mr, 1, 0 },
246    { X86::CMP8ri,      X86::CMP8mi, 1, 0 },
247    { X86::CMP8rr,      X86::CMP8mr, 1, 0 },
248    { X86::DIV16r,      X86::DIV16m, 1, 0 },
249    { X86::DIV32r,      X86::DIV32m, 1, 0 },
250    { X86::DIV64r,      X86::DIV64m, 1, 0 },
251    { X86::DIV8r,       X86::DIV8m, 1, 0 },
252    { X86::EXTRACTPSrr, X86::EXTRACTPSmr, 0, 16 },
253    { X86::FsMOVAPDrr,  X86::MOVSDmr, 0, 0 },
254    { X86::FsMOVAPSrr,  X86::MOVSSmr, 0, 0 },
255    { X86::IDIV16r,     X86::IDIV16m, 1, 0 },
256    { X86::IDIV32r,     X86::IDIV32m, 1, 0 },
257    { X86::IDIV64r,     X86::IDIV64m, 1, 0 },
258    { X86::IDIV8r,      X86::IDIV8m, 1, 0 },
259    { X86::IMUL16r,     X86::IMUL16m, 1, 0 },
260    { X86::IMUL32r,     X86::IMUL32m, 1, 0 },
261    { X86::IMUL64r,     X86::IMUL64m, 1, 0 },
262    { X86::IMUL8r,      X86::IMUL8m, 1, 0 },
263    { X86::JMP32r,      X86::JMP32m, 1, 0 },
264    { X86::JMP64r,      X86::JMP64m, 1, 0 },
265    { X86::MOV16ri,     X86::MOV16mi, 0, 0 },
266    { X86::MOV16rr,     X86::MOV16mr, 0, 0 },
267    { X86::MOV32ri,     X86::MOV32mi, 0, 0 },
268    { X86::MOV32rr,     X86::MOV32mr, 0, 0 },
269    { X86::MOV32rr_TC,  X86::MOV32mr_TC, 0, 0 },
270    { X86::MOV64ri32,   X86::MOV64mi32, 0, 0 },
271    { X86::MOV64rr,     X86::MOV64mr, 0, 0 },
272    { X86::MOV8ri,      X86::MOV8mi, 0, 0 },
273    { X86::MOV8rr,      X86::MOV8mr, 0, 0 },
274    { X86::MOV8rr_NOREX, X86::MOV8mr_NOREX, 0, 0 },
275    { X86::MOVAPDrr,    X86::MOVAPDmr, 0, 16 },
276    { X86::MOVAPSrr,    X86::MOVAPSmr, 0, 16 },
277    { X86::MOVDQArr,    X86::MOVDQAmr, 0, 16 },
278    { X86::MOVPDI2DIrr, X86::MOVPDI2DImr, 0, 0 },
279    { X86::MOVPQIto64rr,X86::MOVPQI2QImr, 0, 0 },
280    { X86::MOVSDto64rr, X86::MOVSDto64mr, 0, 0 },
281    { X86::MOVSS2DIrr,  X86::MOVSS2DImr, 0, 0 },
282    { X86::MOVUPDrr,    X86::MOVUPDmr, 0, 0 },
283    { X86::MOVUPSrr,    X86::MOVUPSmr, 0, 0 },
284    { X86::MUL16r,      X86::MUL16m, 1, 0 },
285    { X86::MUL32r,      X86::MUL32m, 1, 0 },
286    { X86::MUL64r,      X86::MUL64m, 1, 0 },
287    { X86::MUL8r,       X86::MUL8m, 1, 0 },
288    { X86::SETAEr,      X86::SETAEm, 0, 0 },
289    { X86::SETAr,       X86::SETAm, 0, 0 },
290    { X86::SETBEr,      X86::SETBEm, 0, 0 },
291    { X86::SETBr,       X86::SETBm, 0, 0 },
292    { X86::SETEr,       X86::SETEm, 0, 0 },
293    { X86::SETGEr,      X86::SETGEm, 0, 0 },
294    { X86::SETGr,       X86::SETGm, 0, 0 },
295    { X86::SETLEr,      X86::SETLEm, 0, 0 },
296    { X86::SETLr,       X86::SETLm, 0, 0 },
297    { X86::SETNEr,      X86::SETNEm, 0, 0 },
298    { X86::SETNOr,      X86::SETNOm, 0, 0 },
299    { X86::SETNPr,      X86::SETNPm, 0, 0 },
300    { X86::SETNSr,      X86::SETNSm, 0, 0 },
301    { X86::SETOr,       X86::SETOm, 0, 0 },
302    { X86::SETPr,       X86::SETPm, 0, 0 },
303    { X86::SETSr,       X86::SETSm, 0, 0 },
304    { X86::TAILJMPr,    X86::TAILJMPm, 1, 0 },
305    { X86::TAILJMPr64,  X86::TAILJMPm64, 1, 0 },
306    { X86::TEST16ri,    X86::TEST16mi, 1, 0 },
307    { X86::TEST32ri,    X86::TEST32mi, 1, 0 },
308    { X86::TEST64ri32,  X86::TEST64mi32, 1, 0 },
309    { X86::TEST8ri,     X86::TEST8mi, 1, 0 }
310  };
311
312  for (unsigned i = 0, e = array_lengthof(OpTbl0); i != e; ++i) {
313    unsigned RegOp = OpTbl0[i][0];
314    unsigned MemOp = OpTbl0[i][1];
315    unsigned Align = OpTbl0[i][3];
316    if (!RegOp2MemOpTable0.insert(std::make_pair((unsigned*)RegOp,
317                                           std::make_pair(MemOp,Align))).second)
318      assert(false && "Duplicated entries?");
319    unsigned FoldedLoad = OpTbl0[i][2];
320    // Index 0, folded load or store.
321    unsigned AuxInfo = 0 | (FoldedLoad << 4) | ((FoldedLoad^1) << 5);
322    if (RegOp != X86::FsMOVAPDrr && RegOp != X86::FsMOVAPSrr)
323      if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp,
324                                     std::make_pair(RegOp, AuxInfo))).second)
325        AmbEntries.push_back(MemOp);
326  }
327
328  static const unsigned OpTbl1[][3] = {
329    { X86::CMP16rr,         X86::CMP16rm, 0 },
330    { X86::CMP32rr,         X86::CMP32rm, 0 },
331    { X86::CMP64rr,         X86::CMP64rm, 0 },
332    { X86::CMP8rr,          X86::CMP8rm, 0 },
333    { X86::CVTSD2SSrr,      X86::CVTSD2SSrm, 0 },
334    { X86::CVTSI2SD64rr,    X86::CVTSI2SD64rm, 0 },
335    { X86::CVTSI2SDrr,      X86::CVTSI2SDrm, 0 },
336    { X86::CVTSI2SS64rr,    X86::CVTSI2SS64rm, 0 },
337    { X86::CVTSI2SSrr,      X86::CVTSI2SSrm, 0 },
338    { X86::CVTSS2SDrr,      X86::CVTSS2SDrm, 0 },
339    { X86::CVTTSD2SI64rr,   X86::CVTTSD2SI64rm, 0 },
340    { X86::CVTTSD2SIrr,     X86::CVTTSD2SIrm, 0 },
341    { X86::CVTTSS2SI64rr,   X86::CVTTSS2SI64rm, 0 },
342    { X86::CVTTSS2SIrr,     X86::CVTTSS2SIrm, 0 },
343    { X86::FsMOVAPDrr,      X86::MOVSDrm, 0 },
344    { X86::FsMOVAPSrr,      X86::MOVSSrm, 0 },
345    { X86::IMUL16rri,       X86::IMUL16rmi, 0 },
346    { X86::IMUL16rri8,      X86::IMUL16rmi8, 0 },
347    { X86::IMUL32rri,       X86::IMUL32rmi, 0 },
348    { X86::IMUL32rri8,      X86::IMUL32rmi8, 0 },
349    { X86::IMUL64rri32,     X86::IMUL64rmi32, 0 },
350    { X86::IMUL64rri8,      X86::IMUL64rmi8, 0 },
351    { X86::Int_CMPSDrr,     X86::Int_CMPSDrm, 0 },
352    { X86::Int_CMPSSrr,     X86::Int_CMPSSrm, 0 },
353    { X86::Int_COMISDrr,    X86::Int_COMISDrm, 0 },
354    { X86::Int_COMISSrr,    X86::Int_COMISSrm, 0 },
355    { X86::Int_CVTDQ2PDrr,  X86::Int_CVTDQ2PDrm, 16 },
356    { X86::Int_CVTDQ2PSrr,  X86::Int_CVTDQ2PSrm, 16 },
357    { X86::Int_CVTPD2DQrr,  X86::Int_CVTPD2DQrm, 16 },
358    { X86::Int_CVTPD2PSrr,  X86::Int_CVTPD2PSrm, 16 },
359    { X86::Int_CVTPS2DQrr,  X86::Int_CVTPS2DQrm, 16 },
360    { X86::Int_CVTPS2PDrr,  X86::Int_CVTPS2PDrm, 0 },
361    { X86::Int_CVTSD2SI64rr,X86::Int_CVTSD2SI64rm, 0 },
362    { X86::Int_CVTSD2SIrr,  X86::Int_CVTSD2SIrm, 0 },
363    { X86::Int_CVTSD2SSrr,  X86::Int_CVTSD2SSrm, 0 },
364    { X86::Int_CVTSI2SD64rr,X86::Int_CVTSI2SD64rm, 0 },
365    { X86::Int_CVTSI2SDrr,  X86::Int_CVTSI2SDrm, 0 },
366    { X86::Int_CVTSI2SS64rr,X86::Int_CVTSI2SS64rm, 0 },
367    { X86::Int_CVTSI2SSrr,  X86::Int_CVTSI2SSrm, 0 },
368    { X86::Int_CVTSS2SDrr,  X86::Int_CVTSS2SDrm, 0 },
369    { X86::Int_CVTSS2SI64rr,X86::Int_CVTSS2SI64rm, 0 },
370    { X86::Int_CVTSS2SIrr,  X86::Int_CVTSS2SIrm, 0 },
371    { X86::Int_CVTTPD2DQrr, X86::Int_CVTTPD2DQrm, 16 },
372    { X86::Int_CVTTPS2DQrr, X86::Int_CVTTPS2DQrm, 16 },
373    { X86::Int_CVTTSD2SI64rr,X86::Int_CVTTSD2SI64rm, 0 },
374    { X86::Int_CVTTSD2SIrr, X86::Int_CVTTSD2SIrm, 0 },
375    { X86::Int_CVTTSS2SI64rr,X86::Int_CVTTSS2SI64rm, 0 },
376    { X86::Int_CVTTSS2SIrr, X86::Int_CVTTSS2SIrm, 0 },
377    { X86::Int_UCOMISDrr,   X86::Int_UCOMISDrm, 0 },
378    { X86::Int_UCOMISSrr,   X86::Int_UCOMISSrm, 0 },
379    { X86::MOV16rr,         X86::MOV16rm, 0 },
380    { X86::MOV32rr,         X86::MOV32rm, 0 },
381    { X86::MOV32rr_TC,      X86::MOV32rm_TC, 0 },
382    { X86::MOV64rr,         X86::MOV64rm, 0 },
383    { X86::MOV64toPQIrr,    X86::MOVQI2PQIrm, 0 },
384    { X86::MOV64toSDrr,     X86::MOV64toSDrm, 0 },
385    { X86::MOV8rr,          X86::MOV8rm, 0 },
386    { X86::MOVAPDrr,        X86::MOVAPDrm, 16 },
387    { X86::MOVAPSrr,        X86::MOVAPSrm, 16 },
388    { X86::MOVDDUPrr,       X86::MOVDDUPrm, 0 },
389    { X86::MOVDI2PDIrr,     X86::MOVDI2PDIrm, 0 },
390    { X86::MOVDI2SSrr,      X86::MOVDI2SSrm, 0 },
391    { X86::MOVDQArr,        X86::MOVDQArm, 16 },
392    { X86::MOVSHDUPrr,      X86::MOVSHDUPrm, 16 },
393    { X86::MOVSLDUPrr,      X86::MOVSLDUPrm, 16 },
394    { X86::MOVSX16rr8,      X86::MOVSX16rm8, 0 },
395    { X86::MOVSX32rr16,     X86::MOVSX32rm16, 0 },
396    { X86::MOVSX32rr8,      X86::MOVSX32rm8, 0 },
397    { X86::MOVSX64rr16,     X86::MOVSX64rm16, 0 },
398    { X86::MOVSX64rr32,     X86::MOVSX64rm32, 0 },
399    { X86::MOVSX64rr8,      X86::MOVSX64rm8, 0 },
400    { X86::MOVUPDrr,        X86::MOVUPDrm, 16 },
401    { X86::MOVUPSrr,        X86::MOVUPSrm, 0 },
402    { X86::MOVZDI2PDIrr,    X86::MOVZDI2PDIrm, 0 },
403    { X86::MOVZQI2PQIrr,    X86::MOVZQI2PQIrm, 0 },
404    { X86::MOVZPQILo2PQIrr, X86::MOVZPQILo2PQIrm, 16 },
405    { X86::MOVZX16rr8,      X86::MOVZX16rm8, 0 },
406    { X86::MOVZX32rr16,     X86::MOVZX32rm16, 0 },
407    { X86::MOVZX32_NOREXrr8, X86::MOVZX32_NOREXrm8, 0 },
408    { X86::MOVZX32rr8,      X86::MOVZX32rm8, 0 },
409    { X86::MOVZX64rr16,     X86::MOVZX64rm16, 0 },
410    { X86::MOVZX64rr32,     X86::MOVZX64rm32, 0 },
411    { X86::MOVZX64rr8,      X86::MOVZX64rm8, 0 },
412    { X86::PSHUFDri,        X86::PSHUFDmi, 16 },
413    { X86::PSHUFHWri,       X86::PSHUFHWmi, 16 },
414    { X86::PSHUFLWri,       X86::PSHUFLWmi, 16 },
415    { X86::RCPPSr,          X86::RCPPSm, 16 },
416    { X86::RCPPSr_Int,      X86::RCPPSm_Int, 16 },
417    { X86::RSQRTPSr,        X86::RSQRTPSm, 16 },
418    { X86::RSQRTPSr_Int,    X86::RSQRTPSm_Int, 16 },
419    { X86::RSQRTSSr,        X86::RSQRTSSm, 0 },
420    { X86::RSQRTSSr_Int,    X86::RSQRTSSm_Int, 0 },
421    { X86::SQRTPDr,         X86::SQRTPDm, 16 },
422    { X86::SQRTPDr_Int,     X86::SQRTPDm_Int, 16 },
423    { X86::SQRTPSr,         X86::SQRTPSm, 16 },
424    { X86::SQRTPSr_Int,     X86::SQRTPSm_Int, 16 },
425    { X86::SQRTSDr,         X86::SQRTSDm, 0 },
426    { X86::SQRTSDr_Int,     X86::SQRTSDm_Int, 0 },
427    { X86::SQRTSSr,         X86::SQRTSSm, 0 },
428    { X86::SQRTSSr_Int,     X86::SQRTSSm_Int, 0 },
429    { X86::TEST16rr,        X86::TEST16rm, 0 },
430    { X86::TEST32rr,        X86::TEST32rm, 0 },
431    { X86::TEST64rr,        X86::TEST64rm, 0 },
432    { X86::TEST8rr,         X86::TEST8rm, 0 },
433    // FIXME: TEST*rr EAX,EAX ---> CMP [mem], 0
434    { X86::UCOMISDrr,       X86::UCOMISDrm, 0 },
435    { X86::UCOMISSrr,       X86::UCOMISSrm, 0 }
436  };
437
438  for (unsigned i = 0, e = array_lengthof(OpTbl1); i != e; ++i) {
439    unsigned RegOp = OpTbl1[i][0];
440    unsigned MemOp = OpTbl1[i][1];
441    unsigned Align = OpTbl1[i][2];
442    if (!RegOp2MemOpTable1.insert(std::make_pair((unsigned*)RegOp,
443                                           std::make_pair(MemOp,Align))).second)
444      assert(false && "Duplicated entries?");
445    // Index 1, folded load
446    unsigned AuxInfo = 1 | (1 << 4);
447    if (RegOp != X86::FsMOVAPDrr && RegOp != X86::FsMOVAPSrr)
448      if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp,
449                                     std::make_pair(RegOp, AuxInfo))).second)
450        AmbEntries.push_back(MemOp);
451  }
452
453  static const unsigned OpTbl2[][3] = {
454    { X86::ADC32rr,         X86::ADC32rm, 0 },
455    { X86::ADC64rr,         X86::ADC64rm, 0 },
456    { X86::ADD16rr,         X86::ADD16rm, 0 },
457    { X86::ADD32rr,         X86::ADD32rm, 0 },
458    { X86::ADD64rr,         X86::ADD64rm, 0 },
459    { X86::ADD8rr,          X86::ADD8rm, 0 },
460    { X86::ADDPDrr,         X86::ADDPDrm, 16 },
461    { X86::ADDPSrr,         X86::ADDPSrm, 16 },
462    { X86::ADDSDrr,         X86::ADDSDrm, 0 },
463    { X86::ADDSSrr,         X86::ADDSSrm, 0 },
464    { X86::ADDSUBPDrr,      X86::ADDSUBPDrm, 16 },
465    { X86::ADDSUBPSrr,      X86::ADDSUBPSrm, 16 },
466    { X86::AND16rr,         X86::AND16rm, 0 },
467    { X86::AND32rr,         X86::AND32rm, 0 },
468    { X86::AND64rr,         X86::AND64rm, 0 },
469    { X86::AND8rr,          X86::AND8rm, 0 },
470    { X86::ANDNPDrr,        X86::ANDNPDrm, 16 },
471    { X86::ANDNPSrr,        X86::ANDNPSrm, 16 },
472    { X86::ANDPDrr,         X86::ANDPDrm, 16 },
473    { X86::ANDPSrr,         X86::ANDPSrm, 16 },
474    { X86::CMOVA16rr,       X86::CMOVA16rm, 0 },
475    { X86::CMOVA32rr,       X86::CMOVA32rm, 0 },
476    { X86::CMOVA64rr,       X86::CMOVA64rm, 0 },
477    { X86::CMOVAE16rr,      X86::CMOVAE16rm, 0 },
478    { X86::CMOVAE32rr,      X86::CMOVAE32rm, 0 },
479    { X86::CMOVAE64rr,      X86::CMOVAE64rm, 0 },
480    { X86::CMOVB16rr,       X86::CMOVB16rm, 0 },
481    { X86::CMOVB32rr,       X86::CMOVB32rm, 0 },
482    { X86::CMOVB64rr,       X86::CMOVB64rm, 0 },
483    { X86::CMOVBE16rr,      X86::CMOVBE16rm, 0 },
484    { X86::CMOVBE32rr,      X86::CMOVBE32rm, 0 },
485    { X86::CMOVBE64rr,      X86::CMOVBE64rm, 0 },
486    { X86::CMOVE16rr,       X86::CMOVE16rm, 0 },
487    { X86::CMOVE32rr,       X86::CMOVE32rm, 0 },
488    { X86::CMOVE64rr,       X86::CMOVE64rm, 0 },
489    { X86::CMOVG16rr,       X86::CMOVG16rm, 0 },
490    { X86::CMOVG32rr,       X86::CMOVG32rm, 0 },
491    { X86::CMOVG64rr,       X86::CMOVG64rm, 0 },
492    { X86::CMOVGE16rr,      X86::CMOVGE16rm, 0 },
493    { X86::CMOVGE32rr,      X86::CMOVGE32rm, 0 },
494    { X86::CMOVGE64rr,      X86::CMOVGE64rm, 0 },
495    { X86::CMOVL16rr,       X86::CMOVL16rm, 0 },
496    { X86::CMOVL32rr,       X86::CMOVL32rm, 0 },
497    { X86::CMOVL64rr,       X86::CMOVL64rm, 0 },
498    { X86::CMOVLE16rr,      X86::CMOVLE16rm, 0 },
499    { X86::CMOVLE32rr,      X86::CMOVLE32rm, 0 },
500    { X86::CMOVLE64rr,      X86::CMOVLE64rm, 0 },
501    { X86::CMOVNE16rr,      X86::CMOVNE16rm, 0 },
502    { X86::CMOVNE32rr,      X86::CMOVNE32rm, 0 },
503    { X86::CMOVNE64rr,      X86::CMOVNE64rm, 0 },
504    { X86::CMOVNO16rr,      X86::CMOVNO16rm, 0 },
505    { X86::CMOVNO32rr,      X86::CMOVNO32rm, 0 },
506    { X86::CMOVNO64rr,      X86::CMOVNO64rm, 0 },
507    { X86::CMOVNP16rr,      X86::CMOVNP16rm, 0 },
508    { X86::CMOVNP32rr,      X86::CMOVNP32rm, 0 },
509    { X86::CMOVNP64rr,      X86::CMOVNP64rm, 0 },
510    { X86::CMOVNS16rr,      X86::CMOVNS16rm, 0 },
511    { X86::CMOVNS32rr,      X86::CMOVNS32rm, 0 },
512    { X86::CMOVNS64rr,      X86::CMOVNS64rm, 0 },
513    { X86::CMOVO16rr,       X86::CMOVO16rm, 0 },
514    { X86::CMOVO32rr,       X86::CMOVO32rm, 0 },
515    { X86::CMOVO64rr,       X86::CMOVO64rm, 0 },
516    { X86::CMOVP16rr,       X86::CMOVP16rm, 0 },
517    { X86::CMOVP32rr,       X86::CMOVP32rm, 0 },
518    { X86::CMOVP64rr,       X86::CMOVP64rm, 0 },
519    { X86::CMOVS16rr,       X86::CMOVS16rm, 0 },
520    { X86::CMOVS32rr,       X86::CMOVS32rm, 0 },
521    { X86::CMOVS64rr,       X86::CMOVS64rm, 0 },
522    { X86::CMPPDrri,        X86::CMPPDrmi, 16 },
523    { X86::CMPPSrri,        X86::CMPPSrmi, 16 },
524    { X86::CMPSDrr,         X86::CMPSDrm, 0 },
525    { X86::CMPSSrr,         X86::CMPSSrm, 0 },
526    { X86::DIVPDrr,         X86::DIVPDrm, 16 },
527    { X86::DIVPSrr,         X86::DIVPSrm, 16 },
528    { X86::DIVSDrr,         X86::DIVSDrm, 0 },
529    { X86::DIVSSrr,         X86::DIVSSrm, 0 },
530    { X86::FsANDNPDrr,      X86::FsANDNPDrm, 16 },
531    { X86::FsANDNPSrr,      X86::FsANDNPSrm, 16 },
532    { X86::FsANDPDrr,       X86::FsANDPDrm, 16 },
533    { X86::FsANDPSrr,       X86::FsANDPSrm, 16 },
534    { X86::FsORPDrr,        X86::FsORPDrm, 16 },
535    { X86::FsORPSrr,        X86::FsORPSrm, 16 },
536    { X86::FsXORPDrr,       X86::FsXORPDrm, 16 },
537    { X86::FsXORPSrr,       X86::FsXORPSrm, 16 },
538    { X86::HADDPDrr,        X86::HADDPDrm, 16 },
539    { X86::HADDPSrr,        X86::HADDPSrm, 16 },
540    { X86::HSUBPDrr,        X86::HSUBPDrm, 16 },
541    { X86::HSUBPSrr,        X86::HSUBPSrm, 16 },
542    { X86::IMUL16rr,        X86::IMUL16rm, 0 },
543    { X86::IMUL32rr,        X86::IMUL32rm, 0 },
544    { X86::IMUL64rr,        X86::IMUL64rm, 0 },
545    { X86::MAXPDrr,         X86::MAXPDrm, 16 },
546    { X86::MAXPDrr_Int,     X86::MAXPDrm_Int, 16 },
547    { X86::MAXPSrr,         X86::MAXPSrm, 16 },
548    { X86::MAXPSrr_Int,     X86::MAXPSrm_Int, 16 },
549    { X86::MAXSDrr,         X86::MAXSDrm, 0 },
550    { X86::MAXSDrr_Int,     X86::MAXSDrm_Int, 0 },
551    { X86::MAXSSrr,         X86::MAXSSrm, 0 },
552    { X86::MAXSSrr_Int,     X86::MAXSSrm_Int, 0 },
553    { X86::MINPDrr,         X86::MINPDrm, 16 },
554    { X86::MINPDrr_Int,     X86::MINPDrm_Int, 16 },
555    { X86::MINPSrr,         X86::MINPSrm, 16 },
556    { X86::MINPSrr_Int,     X86::MINPSrm_Int, 16 },
557    { X86::MINSDrr,         X86::MINSDrm, 0 },
558    { X86::MINSDrr_Int,     X86::MINSDrm_Int, 0 },
559    { X86::MINSSrr,         X86::MINSSrm, 0 },
560    { X86::MINSSrr_Int,     X86::MINSSrm_Int, 0 },
561    { X86::MULPDrr,         X86::MULPDrm, 16 },
562    { X86::MULPSrr,         X86::MULPSrm, 16 },
563    { X86::MULSDrr,         X86::MULSDrm, 0 },
564    { X86::MULSSrr,         X86::MULSSrm, 0 },
565    { X86::OR16rr,          X86::OR16rm, 0 },
566    { X86::OR32rr,          X86::OR32rm, 0 },
567    { X86::OR64rr,          X86::OR64rm, 0 },
568    { X86::OR8rr,           X86::OR8rm, 0 },
569    { X86::ORPDrr,          X86::ORPDrm, 16 },
570    { X86::ORPSrr,          X86::ORPSrm, 16 },
571    { X86::PACKSSDWrr,      X86::PACKSSDWrm, 16 },
572    { X86::PACKSSWBrr,      X86::PACKSSWBrm, 16 },
573    { X86::PACKUSWBrr,      X86::PACKUSWBrm, 16 },
574    { X86::PADDBrr,         X86::PADDBrm, 16 },
575    { X86::PADDDrr,         X86::PADDDrm, 16 },
576    { X86::PADDQrr,         X86::PADDQrm, 16 },
577    { X86::PADDSBrr,        X86::PADDSBrm, 16 },
578    { X86::PADDSWrr,        X86::PADDSWrm, 16 },
579    { X86::PADDWrr,         X86::PADDWrm, 16 },
580    { X86::PANDNrr,         X86::PANDNrm, 16 },
581    { X86::PANDrr,          X86::PANDrm, 16 },
582    { X86::PAVGBrr,         X86::PAVGBrm, 16 },
583    { X86::PAVGWrr,         X86::PAVGWrm, 16 },
584    { X86::PCMPEQBrr,       X86::PCMPEQBrm, 16 },
585    { X86::PCMPEQDrr,       X86::PCMPEQDrm, 16 },
586    { X86::PCMPEQWrr,       X86::PCMPEQWrm, 16 },
587    { X86::PCMPGTBrr,       X86::PCMPGTBrm, 16 },
588    { X86::PCMPGTDrr,       X86::PCMPGTDrm, 16 },
589    { X86::PCMPGTWrr,       X86::PCMPGTWrm, 16 },
590    { X86::PINSRWrri,       X86::PINSRWrmi, 16 },
591    { X86::PMADDWDrr,       X86::PMADDWDrm, 16 },
592    { X86::PMAXSWrr,        X86::PMAXSWrm, 16 },
593    { X86::PMAXUBrr,        X86::PMAXUBrm, 16 },
594    { X86::PMINSWrr,        X86::PMINSWrm, 16 },
595    { X86::PMINUBrr,        X86::PMINUBrm, 16 },
596    { X86::PMULDQrr,        X86::PMULDQrm, 16 },
597    { X86::PMULHUWrr,       X86::PMULHUWrm, 16 },
598    { X86::PMULHWrr,        X86::PMULHWrm, 16 },
599    { X86::PMULLDrr,        X86::PMULLDrm, 16 },
600    { X86::PMULLWrr,        X86::PMULLWrm, 16 },
601    { X86::PMULUDQrr,       X86::PMULUDQrm, 16 },
602    { X86::PORrr,           X86::PORrm, 16 },
603    { X86::PSADBWrr,        X86::PSADBWrm, 16 },
604    { X86::PSLLDrr,         X86::PSLLDrm, 16 },
605    { X86::PSLLQrr,         X86::PSLLQrm, 16 },
606    { X86::PSLLWrr,         X86::PSLLWrm, 16 },
607    { X86::PSRADrr,         X86::PSRADrm, 16 },
608    { X86::PSRAWrr,         X86::PSRAWrm, 16 },
609    { X86::PSRLDrr,         X86::PSRLDrm, 16 },
610    { X86::PSRLQrr,         X86::PSRLQrm, 16 },
611    { X86::PSRLWrr,         X86::PSRLWrm, 16 },
612    { X86::PSUBBrr,         X86::PSUBBrm, 16 },
613    { X86::PSUBDrr,         X86::PSUBDrm, 16 },
614    { X86::PSUBSBrr,        X86::PSUBSBrm, 16 },
615    { X86::PSUBSWrr,        X86::PSUBSWrm, 16 },
616    { X86::PSUBWrr,         X86::PSUBWrm, 16 },
617    { X86::PUNPCKHBWrr,     X86::PUNPCKHBWrm, 16 },
618    { X86::PUNPCKHDQrr,     X86::PUNPCKHDQrm, 16 },
619    { X86::PUNPCKHQDQrr,    X86::PUNPCKHQDQrm, 16 },
620    { X86::PUNPCKHWDrr,     X86::PUNPCKHWDrm, 16 },
621    { X86::PUNPCKLBWrr,     X86::PUNPCKLBWrm, 16 },
622    { X86::PUNPCKLDQrr,     X86::PUNPCKLDQrm, 16 },
623    { X86::PUNPCKLQDQrr,    X86::PUNPCKLQDQrm, 16 },
624    { X86::PUNPCKLWDrr,     X86::PUNPCKLWDrm, 16 },
625    { X86::PXORrr,          X86::PXORrm, 16 },
626    { X86::SBB32rr,         X86::SBB32rm, 0 },
627    { X86::SBB64rr,         X86::SBB64rm, 0 },
628    { X86::SHUFPDrri,       X86::SHUFPDrmi, 16 },
629    { X86::SHUFPSrri,       X86::SHUFPSrmi, 16 },
630    { X86::SUB16rr,         X86::SUB16rm, 0 },
631    { X86::SUB32rr,         X86::SUB32rm, 0 },
632    { X86::SUB64rr,         X86::SUB64rm, 0 },
633    { X86::SUB8rr,          X86::SUB8rm, 0 },
634    { X86::SUBPDrr,         X86::SUBPDrm, 16 },
635    { X86::SUBPSrr,         X86::SUBPSrm, 16 },
636    { X86::SUBSDrr,         X86::SUBSDrm, 0 },
637    { X86::SUBSSrr,         X86::SUBSSrm, 0 },
638    // FIXME: TEST*rr -> swapped operand of TEST*mr.
639    { X86::UNPCKHPDrr,      X86::UNPCKHPDrm, 16 },
640    { X86::UNPCKHPSrr,      X86::UNPCKHPSrm, 16 },
641    { X86::UNPCKLPDrr,      X86::UNPCKLPDrm, 16 },
642    { X86::UNPCKLPSrr,      X86::UNPCKLPSrm, 16 },
643    { X86::XOR16rr,         X86::XOR16rm, 0 },
644    { X86::XOR32rr,         X86::XOR32rm, 0 },
645    { X86::XOR64rr,         X86::XOR64rm, 0 },
646    { X86::XOR8rr,          X86::XOR8rm, 0 },
647    { X86::XORPDrr,         X86::XORPDrm, 16 },
648    { X86::XORPSrr,         X86::XORPSrm, 16 }
649  };
650
651  for (unsigned i = 0, e = array_lengthof(OpTbl2); i != e; ++i) {
652    unsigned RegOp = OpTbl2[i][0];
653    unsigned MemOp = OpTbl2[i][1];
654    unsigned Align = OpTbl2[i][2];
655    if (!RegOp2MemOpTable2.insert(std::make_pair((unsigned*)RegOp,
656                                           std::make_pair(MemOp,Align))).second)
657      assert(false && "Duplicated entries?");
658    // Index 2, folded load
659    unsigned AuxInfo = 2 | (1 << 4);
660    if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp,
661                                   std::make_pair(RegOp, AuxInfo))).second)
662      AmbEntries.push_back(MemOp);
663  }
664
665  // Remove ambiguous entries.
666  assert(AmbEntries.empty() && "Duplicated entries in unfolding maps?");
667}
668
669bool X86InstrInfo::isMoveInstr(const MachineInstr& MI,
670                               unsigned &SrcReg, unsigned &DstReg,
671                               unsigned &SrcSubIdx, unsigned &DstSubIdx) const {
672  switch (MI.getOpcode()) {
673  default:
674    return false;
675  case X86::MOV8rr:
676  case X86::MOV8rr_NOREX:
677  case X86::MOV16rr:
678  case X86::MOV32rr:
679  case X86::MOV64rr:
680  case X86::MOV32rr_TC:
681  case X86::MOV64rr_TC:
682
683  // FP Stack register class copies
684  case X86::MOV_Fp3232: case X86::MOV_Fp6464: case X86::MOV_Fp8080:
685  case X86::MOV_Fp3264: case X86::MOV_Fp3280:
686  case X86::MOV_Fp6432: case X86::MOV_Fp8032:
687
688  // Note that MOVSSrr and MOVSDrr are not considered copies. FR32 and FR64
689  // copies are done with FsMOVAPSrr and FsMOVAPDrr.
690
691  case X86::FsMOVAPSrr:
692  case X86::FsMOVAPDrr:
693  case X86::MOVAPSrr:
694  case X86::MOVAPDrr:
695  case X86::MOVDQArr:
696  case X86::MMX_MOVQ64rr:
697    assert(MI.getNumOperands() >= 2 &&
698           MI.getOperand(0).isReg() &&
699           MI.getOperand(1).isReg() &&
700           "invalid register-register move instruction");
701    SrcReg = MI.getOperand(1).getReg();
702    DstReg = MI.getOperand(0).getReg();
703    SrcSubIdx = MI.getOperand(1).getSubReg();
704    DstSubIdx = MI.getOperand(0).getSubReg();
705    return true;
706  }
707}
708
709bool
710X86InstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
711                                    unsigned &SrcReg, unsigned &DstReg,
712                                    unsigned &SubIdx) const {
713  switch (MI.getOpcode()) {
714  default: break;
715  case X86::MOVSX16rr8:
716  case X86::MOVZX16rr8:
717  case X86::MOVSX32rr8:
718  case X86::MOVZX32rr8:
719  case X86::MOVSX64rr8:
720  case X86::MOVZX64rr8:
721    if (!TM.getSubtarget<X86Subtarget>().is64Bit())
722      // It's not always legal to reference the low 8-bit of the larger
723      // register in 32-bit mode.
724      return false;
725  case X86::MOVSX32rr16:
726  case X86::MOVZX32rr16:
727  case X86::MOVSX64rr16:
728  case X86::MOVZX64rr16:
729  case X86::MOVSX64rr32:
730  case X86::MOVZX64rr32: {
731    if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg())
732      // Be conservative.
733      return false;
734    SrcReg = MI.getOperand(1).getReg();
735    DstReg = MI.getOperand(0).getReg();
736    switch (MI.getOpcode()) {
737    default:
738      llvm_unreachable(0);
739      break;
740    case X86::MOVSX16rr8:
741    case X86::MOVZX16rr8:
742    case X86::MOVSX32rr8:
743    case X86::MOVZX32rr8:
744    case X86::MOVSX64rr8:
745    case X86::MOVZX64rr8:
746      SubIdx = 1;
747      break;
748    case X86::MOVSX32rr16:
749    case X86::MOVZX32rr16:
750    case X86::MOVSX64rr16:
751    case X86::MOVZX64rr16:
752      SubIdx = 3;
753      break;
754    case X86::MOVSX64rr32:
755    case X86::MOVZX64rr32:
756      SubIdx = 4;
757      break;
758    }
759    return true;
760  }
761  }
762  return false;
763}
764
765/// isFrameOperand - Return true and the FrameIndex if the specified
766/// operand and follow operands form a reference to the stack frame.
767bool X86InstrInfo::isFrameOperand(const MachineInstr *MI, unsigned int Op,
768                                  int &FrameIndex) const {
769  if (MI->getOperand(Op).isFI() && MI->getOperand(Op+1).isImm() &&
770      MI->getOperand(Op+2).isReg() && MI->getOperand(Op+3).isImm() &&
771      MI->getOperand(Op+1).getImm() == 1 &&
772      MI->getOperand(Op+2).getReg() == 0 &&
773      MI->getOperand(Op+3).getImm() == 0) {
774    FrameIndex = MI->getOperand(Op).getIndex();
775    return true;
776  }
777  return false;
778}
779
780static bool isFrameLoadOpcode(int Opcode) {
781  switch (Opcode) {
782  default: break;
783  case X86::MOV8rm:
784  case X86::MOV16rm:
785  case X86::MOV32rm:
786  case X86::MOV64rm:
787  case X86::LD_Fp64m:
788  case X86::MOVSSrm:
789  case X86::MOVSDrm:
790  case X86::MOVAPSrm:
791  case X86::MOVAPDrm:
792  case X86::MOVDQArm:
793  case X86::MMX_MOVD64rm:
794  case X86::MMX_MOVQ64rm:
795    return true;
796    break;
797  }
798  return false;
799}
800
801static bool isFrameStoreOpcode(int Opcode) {
802  switch (Opcode) {
803  default: break;
804  case X86::MOV8mr:
805  case X86::MOV16mr:
806  case X86::MOV32mr:
807  case X86::MOV64mr:
808  case X86::ST_FpP64m:
809  case X86::MOVSSmr:
810  case X86::MOVSDmr:
811  case X86::MOVAPSmr:
812  case X86::MOVAPDmr:
813  case X86::MOVDQAmr:
814  case X86::MMX_MOVD64mr:
815  case X86::MMX_MOVQ64mr:
816  case X86::MMX_MOVNTQmr:
817    return true;
818  }
819  return false;
820}
821
822unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
823                                           int &FrameIndex) const {
824  if (isFrameLoadOpcode(MI->getOpcode()))
825    if (isFrameOperand(MI, 1, FrameIndex))
826      return MI->getOperand(0).getReg();
827  return 0;
828}
829
830unsigned X86InstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI,
831                                                 int &FrameIndex) const {
832  if (isFrameLoadOpcode(MI->getOpcode())) {
833    unsigned Reg;
834    if ((Reg = isLoadFromStackSlot(MI, FrameIndex)))
835      return Reg;
836    // Check for post-frame index elimination operations
837    const MachineMemOperand *Dummy;
838    return hasLoadFromStackSlot(MI, Dummy, FrameIndex);
839  }
840  return 0;
841}
842
843bool X86InstrInfo::hasLoadFromStackSlot(const MachineInstr *MI,
844                                        const MachineMemOperand *&MMO,
845                                        int &FrameIndex) const {
846  for (MachineInstr::mmo_iterator o = MI->memoperands_begin(),
847         oe = MI->memoperands_end();
848       o != oe;
849       ++o) {
850    if ((*o)->isLoad() && (*o)->getValue())
851      if (const FixedStackPseudoSourceValue *Value =
852          dyn_cast<const FixedStackPseudoSourceValue>((*o)->getValue())) {
853        FrameIndex = Value->getFrameIndex();
854        MMO = *o;
855        return true;
856      }
857  }
858  return false;
859}
860
861unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr *MI,
862                                          int &FrameIndex) const {
863  if (isFrameStoreOpcode(MI->getOpcode()))
864    if (isFrameOperand(MI, 0, FrameIndex))
865      return MI->getOperand(X86AddrNumOperands).getReg();
866  return 0;
867}
868
869unsigned X86InstrInfo::isStoreToStackSlotPostFE(const MachineInstr *MI,
870                                                int &FrameIndex) const {
871  if (isFrameStoreOpcode(MI->getOpcode())) {
872    unsigned Reg;
873    if ((Reg = isStoreToStackSlot(MI, FrameIndex)))
874      return Reg;
875    // Check for post-frame index elimination operations
876    const MachineMemOperand *Dummy;
877    return hasStoreToStackSlot(MI, Dummy, FrameIndex);
878  }
879  return 0;
880}
881
882bool X86InstrInfo::hasStoreToStackSlot(const MachineInstr *MI,
883                                       const MachineMemOperand *&MMO,
884                                       int &FrameIndex) const {
885  for (MachineInstr::mmo_iterator o = MI->memoperands_begin(),
886         oe = MI->memoperands_end();
887       o != oe;
888       ++o) {
889    if ((*o)->isStore() && (*o)->getValue())
890      if (const FixedStackPseudoSourceValue *Value =
891          dyn_cast<const FixedStackPseudoSourceValue>((*o)->getValue())) {
892        FrameIndex = Value->getFrameIndex();
893        MMO = *o;
894        return true;
895      }
896  }
897  return false;
898}
899
900/// regIsPICBase - Return true if register is PIC base (i.e.g defined by
901/// X86::MOVPC32r.
902static bool regIsPICBase(unsigned BaseReg, const MachineRegisterInfo &MRI) {
903  bool isPICBase = false;
904  for (MachineRegisterInfo::def_iterator I = MRI.def_begin(BaseReg),
905         E = MRI.def_end(); I != E; ++I) {
906    MachineInstr *DefMI = I.getOperand().getParent();
907    if (DefMI->getOpcode() != X86::MOVPC32r)
908      return false;
909    assert(!isPICBase && "More than one PIC base?");
910    isPICBase = true;
911  }
912  return isPICBase;
913}
914
915bool
916X86InstrInfo::isReallyTriviallyReMaterializable(const MachineInstr *MI,
917                                                AliasAnalysis *AA) const {
918  switch (MI->getOpcode()) {
919  default: break;
920    case X86::MOV8rm:
921    case X86::MOV16rm:
922    case X86::MOV32rm:
923    case X86::MOV64rm:
924    case X86::LD_Fp64m:
925    case X86::MOVSSrm:
926    case X86::MOVSDrm:
927    case X86::MOVAPSrm:
928    case X86::MOVUPSrm:
929    case X86::MOVUPSrm_Int:
930    case X86::MOVAPDrm:
931    case X86::MOVDQArm:
932    case X86::MMX_MOVD64rm:
933    case X86::MMX_MOVQ64rm:
934    case X86::FsMOVAPSrm:
935    case X86::FsMOVAPDrm: {
936      // Loads from constant pools are trivially rematerializable.
937      if (MI->getOperand(1).isReg() &&
938          MI->getOperand(2).isImm() &&
939          MI->getOperand(3).isReg() && MI->getOperand(3).getReg() == 0 &&
940          MI->isInvariantLoad(AA)) {
941        unsigned BaseReg = MI->getOperand(1).getReg();
942        if (BaseReg == 0 || BaseReg == X86::RIP)
943          return true;
944        // Allow re-materialization of PIC load.
945        if (!ReMatPICStubLoad && MI->getOperand(4).isGlobal())
946          return false;
947        const MachineFunction &MF = *MI->getParent()->getParent();
948        const MachineRegisterInfo &MRI = MF.getRegInfo();
949        bool isPICBase = false;
950        for (MachineRegisterInfo::def_iterator I = MRI.def_begin(BaseReg),
951               E = MRI.def_end(); I != E; ++I) {
952          MachineInstr *DefMI = I.getOperand().getParent();
953          if (DefMI->getOpcode() != X86::MOVPC32r)
954            return false;
955          assert(!isPICBase && "More than one PIC base?");
956          isPICBase = true;
957        }
958        return isPICBase;
959      }
960      return false;
961    }
962
963     case X86::LEA32r:
964     case X86::LEA64r: {
965       if (MI->getOperand(2).isImm() &&
966           MI->getOperand(3).isReg() && MI->getOperand(3).getReg() == 0 &&
967           !MI->getOperand(4).isReg()) {
968         // lea fi#, lea GV, etc. are all rematerializable.
969         if (!MI->getOperand(1).isReg())
970           return true;
971         unsigned BaseReg = MI->getOperand(1).getReg();
972         if (BaseReg == 0)
973           return true;
974         // Allow re-materialization of lea PICBase + x.
975         const MachineFunction &MF = *MI->getParent()->getParent();
976         const MachineRegisterInfo &MRI = MF.getRegInfo();
977         return regIsPICBase(BaseReg, MRI);
978       }
979       return false;
980     }
981  }
982
983  // All other instructions marked M_REMATERIALIZABLE are always trivially
984  // rematerializable.
985  return true;
986}
987
988/// isSafeToClobberEFLAGS - Return true if it's safe insert an instruction that
989/// would clobber the EFLAGS condition register. Note the result may be
990/// conservative. If it cannot definitely determine the safety after visiting
991/// a few instructions in each direction it assumes it's not safe.
992static bool isSafeToClobberEFLAGS(MachineBasicBlock &MBB,
993                                  MachineBasicBlock::iterator I) {
994  MachineBasicBlock::iterator E = MBB.end();
995
996  // It's always safe to clobber EFLAGS at the end of a block.
997  if (I == E)
998    return true;
999
1000  // For compile time consideration, if we are not able to determine the
1001  // safety after visiting 4 instructions in each direction, we will assume
1002  // it's not safe.
1003  MachineBasicBlock::iterator Iter = I;
1004  for (unsigned i = 0; i < 4; ++i) {
1005    bool SeenDef = false;
1006    for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
1007      MachineOperand &MO = Iter->getOperand(j);
1008      if (!MO.isReg())
1009        continue;
1010      if (MO.getReg() == X86::EFLAGS) {
1011        if (MO.isUse())
1012          return false;
1013        SeenDef = true;
1014      }
1015    }
1016
1017    if (SeenDef)
1018      // This instruction defines EFLAGS, no need to look any further.
1019      return true;
1020    ++Iter;
1021    // Skip over DBG_VALUE.
1022    while (Iter != E && Iter->isDebugValue())
1023      ++Iter;
1024
1025    // If we make it to the end of the block, it's safe to clobber EFLAGS.
1026    if (Iter == E)
1027      return true;
1028  }
1029
1030  MachineBasicBlock::iterator B = MBB.begin();
1031  Iter = I;
1032  for (unsigned i = 0; i < 4; ++i) {
1033    // If we make it to the beginning of the block, it's safe to clobber
1034    // EFLAGS iff EFLAGS is not live-in.
1035    if (Iter == B)
1036      return !MBB.isLiveIn(X86::EFLAGS);
1037
1038    --Iter;
1039    // Skip over DBG_VALUE.
1040    while (Iter != B && Iter->isDebugValue())
1041      --Iter;
1042
1043    bool SawKill = false;
1044    for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
1045      MachineOperand &MO = Iter->getOperand(j);
1046      if (MO.isReg() && MO.getReg() == X86::EFLAGS) {
1047        if (MO.isDef()) return MO.isDead();
1048        if (MO.isKill()) SawKill = true;
1049      }
1050    }
1051
1052    if (SawKill)
1053      // This instruction kills EFLAGS and doesn't redefine it, so
1054      // there's no need to look further.
1055      return true;
1056  }
1057
1058  // Conservative answer.
1059  return false;
1060}
1061
1062void X86InstrInfo::reMaterialize(MachineBasicBlock &MBB,
1063                                 MachineBasicBlock::iterator I,
1064                                 unsigned DestReg, unsigned SubIdx,
1065                                 const MachineInstr *Orig,
1066                                 const TargetRegisterInfo *TRI) const {
1067  DebugLoc DL = MBB.findDebugLoc(I);
1068
1069  if (SubIdx && TargetRegisterInfo::isPhysicalRegister(DestReg)) {
1070    DestReg = TRI->getSubReg(DestReg, SubIdx);
1071    SubIdx = 0;
1072  }
1073
1074  // MOV32r0 etc. are implemented with xor which clobbers condition code.
1075  // Re-materialize them as movri instructions to avoid side effects.
1076  bool Clone = true;
1077  unsigned Opc = Orig->getOpcode();
1078  switch (Opc) {
1079  default: break;
1080  case X86::MOV8r0:
1081  case X86::MOV16r0:
1082  case X86::MOV32r0:
1083  case X86::MOV64r0: {
1084    if (!isSafeToClobberEFLAGS(MBB, I)) {
1085      switch (Opc) {
1086      default: break;
1087      case X86::MOV8r0:  Opc = X86::MOV8ri;  break;
1088      case X86::MOV16r0: Opc = X86::MOV16ri; break;
1089      case X86::MOV32r0: Opc = X86::MOV32ri; break;
1090      case X86::MOV64r0: Opc = X86::MOV64ri64i32; break;
1091      }
1092      Clone = false;
1093    }
1094    break;
1095  }
1096  }
1097
1098  if (Clone) {
1099    MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
1100    MI->getOperand(0).setReg(DestReg);
1101    MBB.insert(I, MI);
1102  } else {
1103    BuildMI(MBB, I, DL, get(Opc), DestReg).addImm(0);
1104  }
1105
1106  MachineInstr *NewMI = prior(I);
1107  NewMI->getOperand(0).setSubReg(SubIdx);
1108}
1109
1110/// hasLiveCondCodeDef - True if MI has a condition code def, e.g. EFLAGS, that
1111/// is not marked dead.
1112static bool hasLiveCondCodeDef(MachineInstr *MI) {
1113  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
1114    MachineOperand &MO = MI->getOperand(i);
1115    if (MO.isReg() && MO.isDef() &&
1116        MO.getReg() == X86::EFLAGS && !MO.isDead()) {
1117      return true;
1118    }
1119  }
1120  return false;
1121}
1122
1123/// convertToThreeAddressWithLEA - Helper for convertToThreeAddress when
1124/// 16-bit LEA is disabled, use 32-bit LEA to form 3-address code by promoting
1125/// to a 32-bit superregister and then truncating back down to a 16-bit
1126/// subregister.
1127MachineInstr *
1128X86InstrInfo::convertToThreeAddressWithLEA(unsigned MIOpc,
1129                                           MachineFunction::iterator &MFI,
1130                                           MachineBasicBlock::iterator &MBBI,
1131                                           LiveVariables *LV) const {
1132  MachineInstr *MI = MBBI;
1133  unsigned Dest = MI->getOperand(0).getReg();
1134  unsigned Src = MI->getOperand(1).getReg();
1135  bool isDead = MI->getOperand(0).isDead();
1136  bool isKill = MI->getOperand(1).isKill();
1137
1138  unsigned Opc = TM.getSubtarget<X86Subtarget>().is64Bit()
1139    ? X86::LEA64_32r : X86::LEA32r;
1140  MachineRegisterInfo &RegInfo = MFI->getParent()->getRegInfo();
1141  unsigned leaInReg = RegInfo.createVirtualRegister(&X86::GR32RegClass);
1142  unsigned leaOutReg = RegInfo.createVirtualRegister(&X86::GR32RegClass);
1143
1144  // Build and insert into an implicit UNDEF value. This is OK because
1145  // well be shifting and then extracting the lower 16-bits.
1146  // This has the potential to cause partial register stall. e.g.
1147  //   movw    (%rbp,%rcx,2), %dx
1148  //   leal    -65(%rdx), %esi
1149  // But testing has shown this *does* help performance in 64-bit mode (at
1150  // least on modern x86 machines).
1151  BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg);
1152  MachineInstr *InsMI =
1153    BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::INSERT_SUBREG),leaInReg)
1154    .addReg(leaInReg)
1155    .addReg(Src, getKillRegState(isKill))
1156    .addImm(X86::SUBREG_16BIT);
1157
1158  MachineInstrBuilder MIB = BuildMI(*MFI, MBBI, MI->getDebugLoc(),
1159                                    get(Opc), leaOutReg);
1160  switch (MIOpc) {
1161  default:
1162    llvm_unreachable(0);
1163    break;
1164  case X86::SHL16ri: {
1165    unsigned ShAmt = MI->getOperand(2).getImm();
1166    MIB.addReg(0).addImm(1 << ShAmt)
1167       .addReg(leaInReg, RegState::Kill).addImm(0);
1168    break;
1169  }
1170  case X86::INC16r:
1171  case X86::INC64_16r:
1172    addLeaRegOffset(MIB, leaInReg, true, 1);
1173    break;
1174  case X86::DEC16r:
1175  case X86::DEC64_16r:
1176    addLeaRegOffset(MIB, leaInReg, true, -1);
1177    break;
1178  case X86::ADD16ri:
1179  case X86::ADD16ri8:
1180    addLeaRegOffset(MIB, leaInReg, true, MI->getOperand(2).getImm());
1181    break;
1182  case X86::ADD16rr: {
1183    unsigned Src2 = MI->getOperand(2).getReg();
1184    bool isKill2 = MI->getOperand(2).isKill();
1185    unsigned leaInReg2 = 0;
1186    MachineInstr *InsMI2 = 0;
1187    if (Src == Src2) {
1188      // ADD16rr %reg1028<kill>, %reg1028
1189      // just a single insert_subreg.
1190      addRegReg(MIB, leaInReg, true, leaInReg, false);
1191    } else {
1192      leaInReg2 = RegInfo.createVirtualRegister(&X86::GR32RegClass);
1193      // Build and insert into an implicit UNDEF value. This is OK because
1194      // well be shifting and then extracting the lower 16-bits.
1195      BuildMI(*MFI, MIB, MI->getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg2);
1196      InsMI2 =
1197        BuildMI(*MFI, MIB, MI->getDebugLoc(), get(X86::INSERT_SUBREG),leaInReg2)
1198        .addReg(leaInReg2)
1199        .addReg(Src2, getKillRegState(isKill2))
1200        .addImm(X86::SUBREG_16BIT);
1201      addRegReg(MIB, leaInReg, true, leaInReg2, true);
1202    }
1203    if (LV && isKill2 && InsMI2)
1204      LV->replaceKillInstruction(Src2, MI, InsMI2);
1205    break;
1206  }
1207  }
1208
1209  MachineInstr *NewMI = MIB;
1210  MachineInstr *ExtMI =
1211    BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::EXTRACT_SUBREG))
1212    .addReg(Dest, RegState::Define | getDeadRegState(isDead))
1213    .addReg(leaOutReg, RegState::Kill)
1214    .addImm(X86::SUBREG_16BIT);
1215
1216  if (LV) {
1217    // Update live variables
1218    LV->getVarInfo(leaInReg).Kills.push_back(NewMI);
1219    LV->getVarInfo(leaOutReg).Kills.push_back(ExtMI);
1220    if (isKill)
1221      LV->replaceKillInstruction(Src, MI, InsMI);
1222    if (isDead)
1223      LV->replaceKillInstruction(Dest, MI, ExtMI);
1224  }
1225
1226  return ExtMI;
1227}
1228
1229/// convertToThreeAddress - This method must be implemented by targets that
1230/// set the M_CONVERTIBLE_TO_3_ADDR flag.  When this flag is set, the target
1231/// may be able to convert a two-address instruction into a true
1232/// three-address instruction on demand.  This allows the X86 target (for
1233/// example) to convert ADD and SHL instructions into LEA instructions if they
1234/// would require register copies due to two-addressness.
1235///
1236/// This method returns a null pointer if the transformation cannot be
1237/// performed, otherwise it returns the new instruction.
1238///
1239MachineInstr *
1240X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
1241                                    MachineBasicBlock::iterator &MBBI,
1242                                    LiveVariables *LV) const {
1243  MachineInstr *MI = MBBI;
1244  MachineFunction &MF = *MI->getParent()->getParent();
1245  // All instructions input are two-addr instructions.  Get the known operands.
1246  unsigned Dest = MI->getOperand(0).getReg();
1247  unsigned Src = MI->getOperand(1).getReg();
1248  bool isDead = MI->getOperand(0).isDead();
1249  bool isKill = MI->getOperand(1).isKill();
1250
1251  MachineInstr *NewMI = NULL;
1252  // FIXME: 16-bit LEA's are really slow on Athlons, but not bad on P4's.  When
1253  // we have better subtarget support, enable the 16-bit LEA generation here.
1254  // 16-bit LEA is also slow on Core2.
1255  bool DisableLEA16 = true;
1256  bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit();
1257
1258  unsigned MIOpc = MI->getOpcode();
1259  switch (MIOpc) {
1260  case X86::SHUFPSrri: {
1261    assert(MI->getNumOperands() == 4 && "Unknown shufps instruction!");
1262    if (!TM.getSubtarget<X86Subtarget>().hasSSE2()) return 0;
1263
1264    unsigned B = MI->getOperand(1).getReg();
1265    unsigned C = MI->getOperand(2).getReg();
1266    if (B != C) return 0;
1267    unsigned A = MI->getOperand(0).getReg();
1268    unsigned M = MI->getOperand(3).getImm();
1269    NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::PSHUFDri))
1270      .addReg(A, RegState::Define | getDeadRegState(isDead))
1271      .addReg(B, getKillRegState(isKill)).addImm(M);
1272    break;
1273  }
1274  case X86::SHL64ri: {
1275    assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
1276    // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
1277    // the flags produced by a shift yet, so this is safe.
1278    unsigned ShAmt = MI->getOperand(2).getImm();
1279    if (ShAmt == 0 || ShAmt >= 4) return 0;
1280
1281    NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
1282      .addReg(Dest, RegState::Define | getDeadRegState(isDead))
1283      .addReg(0).addImm(1 << ShAmt)
1284      .addReg(Src, getKillRegState(isKill))
1285      .addImm(0);
1286    break;
1287  }
1288  case X86::SHL32ri: {
1289    assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
1290    // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
1291    // the flags produced by a shift yet, so this is safe.
1292    unsigned ShAmt = MI->getOperand(2).getImm();
1293    if (ShAmt == 0 || ShAmt >= 4) return 0;
1294
1295    unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
1296    NewMI = BuildMI(MF, MI->getDebugLoc(), get(Opc))
1297      .addReg(Dest, RegState::Define | getDeadRegState(isDead))
1298      .addReg(0).addImm(1 << ShAmt)
1299      .addReg(Src, getKillRegState(isKill)).addImm(0);
1300    break;
1301  }
1302  case X86::SHL16ri: {
1303    assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
1304    // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses
1305    // the flags produced by a shift yet, so this is safe.
1306    unsigned ShAmt = MI->getOperand(2).getImm();
1307    if (ShAmt == 0 || ShAmt >= 4) return 0;
1308
1309    if (DisableLEA16)
1310      return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
1311    NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1312      .addReg(Dest, RegState::Define | getDeadRegState(isDead))
1313      .addReg(0).addImm(1 << ShAmt)
1314      .addReg(Src, getKillRegState(isKill))
1315      .addImm(0);
1316    break;
1317  }
1318  default: {
1319    // The following opcodes also sets the condition code register(s). Only
1320    // convert them to equivalent lea if the condition code register def's
1321    // are dead!
1322    if (hasLiveCondCodeDef(MI))
1323      return 0;
1324
1325    switch (MIOpc) {
1326    default: return 0;
1327    case X86::INC64r:
1328    case X86::INC32r:
1329    case X86::INC64_32r: {
1330      assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
1331      unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r
1332        : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
1333      NewMI = addLeaRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
1334                              .addReg(Dest, RegState::Define |
1335                                      getDeadRegState(isDead)),
1336                              Src, isKill, 1);
1337      break;
1338    }
1339    case X86::INC16r:
1340    case X86::INC64_16r:
1341      if (DisableLEA16)
1342        return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
1343      assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
1344      NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1345                           .addReg(Dest, RegState::Define |
1346                                   getDeadRegState(isDead)),
1347                           Src, isKill, 1);
1348      break;
1349    case X86::DEC64r:
1350    case X86::DEC32r:
1351    case X86::DEC64_32r: {
1352      assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
1353      unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r
1354        : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
1355      NewMI = addLeaRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
1356                              .addReg(Dest, RegState::Define |
1357                                      getDeadRegState(isDead)),
1358                              Src, isKill, -1);
1359      break;
1360    }
1361    case X86::DEC16r:
1362    case X86::DEC64_16r:
1363      if (DisableLEA16)
1364        return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
1365      assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
1366      NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1367                           .addReg(Dest, RegState::Define |
1368                                   getDeadRegState(isDead)),
1369                           Src, isKill, -1);
1370      break;
1371    case X86::ADD64rr:
1372    case X86::ADD32rr: {
1373      assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1374      unsigned Opc = MIOpc == X86::ADD64rr ? X86::LEA64r
1375        : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
1376      unsigned Src2 = MI->getOperand(2).getReg();
1377      bool isKill2 = MI->getOperand(2).isKill();
1378      NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(Opc))
1379                        .addReg(Dest, RegState::Define |
1380                                getDeadRegState(isDead)),
1381                        Src, isKill, Src2, isKill2);
1382      if (LV && isKill2)
1383        LV->replaceKillInstruction(Src2, MI, NewMI);
1384      break;
1385    }
1386    case X86::ADD16rr: {
1387      if (DisableLEA16)
1388        return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
1389      assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1390      unsigned Src2 = MI->getOperand(2).getReg();
1391      bool isKill2 = MI->getOperand(2).isKill();
1392      NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1393                        .addReg(Dest, RegState::Define |
1394                                getDeadRegState(isDead)),
1395                        Src, isKill, Src2, isKill2);
1396      if (LV && isKill2)
1397        LV->replaceKillInstruction(Src2, MI, NewMI);
1398      break;
1399    }
1400    case X86::ADD64ri32:
1401    case X86::ADD64ri8:
1402      assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1403      NewMI = addLeaRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
1404                              .addReg(Dest, RegState::Define |
1405                                      getDeadRegState(isDead)),
1406                              Src, isKill, MI->getOperand(2).getImm());
1407      break;
1408    case X86::ADD32ri:
1409    case X86::ADD32ri8: {
1410      assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1411      unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
1412      NewMI = addLeaRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
1413                              .addReg(Dest, RegState::Define |
1414                                      getDeadRegState(isDead)),
1415                                Src, isKill, MI->getOperand(2).getImm());
1416      break;
1417    }
1418    case X86::ADD16ri:
1419    case X86::ADD16ri8:
1420      if (DisableLEA16)
1421        return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
1422      assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
1423      NewMI = addLeaRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
1424                              .addReg(Dest, RegState::Define |
1425                                      getDeadRegState(isDead)),
1426                              Src, isKill, MI->getOperand(2).getImm());
1427      break;
1428    }
1429  }
1430  }
1431
1432  if (!NewMI) return 0;
1433
1434  if (LV) {  // Update live variables
1435    if (isKill)
1436      LV->replaceKillInstruction(Src, MI, NewMI);
1437    if (isDead)
1438      LV->replaceKillInstruction(Dest, MI, NewMI);
1439  }
1440
1441  MFI->insert(MBBI, NewMI);          // Insert the new inst
1442  return NewMI;
1443}
1444
1445/// commuteInstruction - We have a few instructions that must be hacked on to
1446/// commute them.
1447///
1448MachineInstr *
1449X86InstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
1450  switch (MI->getOpcode()) {
1451  case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I)
1452  case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I)
1453  case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I)
1454  case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I)
1455  case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I -> A = SHLD64rri8 C, B, (64-I)
1456  case X86::SHLD64rri8:{// A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, (64-I)
1457    unsigned Opc;
1458    unsigned Size;
1459    switch (MI->getOpcode()) {
1460    default: llvm_unreachable("Unreachable!");
1461    case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break;
1462    case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break;
1463    case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break;
1464    case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break;
1465    case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break;
1466    case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break;
1467    }
1468    unsigned Amt = MI->getOperand(3).getImm();
1469    if (NewMI) {
1470      MachineFunction &MF = *MI->getParent()->getParent();
1471      MI = MF.CloneMachineInstr(MI);
1472      NewMI = false;
1473    }
1474    MI->setDesc(get(Opc));
1475    MI->getOperand(3).setImm(Size-Amt);
1476    return TargetInstrInfoImpl::commuteInstruction(MI, NewMI);
1477  }
1478  case X86::CMOVB16rr:
1479  case X86::CMOVB32rr:
1480  case X86::CMOVB64rr:
1481  case X86::CMOVAE16rr:
1482  case X86::CMOVAE32rr:
1483  case X86::CMOVAE64rr:
1484  case X86::CMOVE16rr:
1485  case X86::CMOVE32rr:
1486  case X86::CMOVE64rr:
1487  case X86::CMOVNE16rr:
1488  case X86::CMOVNE32rr:
1489  case X86::CMOVNE64rr:
1490  case X86::CMOVBE16rr:
1491  case X86::CMOVBE32rr:
1492  case X86::CMOVBE64rr:
1493  case X86::CMOVA16rr:
1494  case X86::CMOVA32rr:
1495  case X86::CMOVA64rr:
1496  case X86::CMOVL16rr:
1497  case X86::CMOVL32rr:
1498  case X86::CMOVL64rr:
1499  case X86::CMOVGE16rr:
1500  case X86::CMOVGE32rr:
1501  case X86::CMOVGE64rr:
1502  case X86::CMOVLE16rr:
1503  case X86::CMOVLE32rr:
1504  case X86::CMOVLE64rr:
1505  case X86::CMOVG16rr:
1506  case X86::CMOVG32rr:
1507  case X86::CMOVG64rr:
1508  case X86::CMOVS16rr:
1509  case X86::CMOVS32rr:
1510  case X86::CMOVS64rr:
1511  case X86::CMOVNS16rr:
1512  case X86::CMOVNS32rr:
1513  case X86::CMOVNS64rr:
1514  case X86::CMOVP16rr:
1515  case X86::CMOVP32rr:
1516  case X86::CMOVP64rr:
1517  case X86::CMOVNP16rr:
1518  case X86::CMOVNP32rr:
1519  case X86::CMOVNP64rr:
1520  case X86::CMOVO16rr:
1521  case X86::CMOVO32rr:
1522  case X86::CMOVO64rr:
1523  case X86::CMOVNO16rr:
1524  case X86::CMOVNO32rr:
1525  case X86::CMOVNO64rr: {
1526    unsigned Opc = 0;
1527    switch (MI->getOpcode()) {
1528    default: break;
1529    case X86::CMOVB16rr:  Opc = X86::CMOVAE16rr; break;
1530    case X86::CMOVB32rr:  Opc = X86::CMOVAE32rr; break;
1531    case X86::CMOVB64rr:  Opc = X86::CMOVAE64rr; break;
1532    case X86::CMOVAE16rr: Opc = X86::CMOVB16rr; break;
1533    case X86::CMOVAE32rr: Opc = X86::CMOVB32rr; break;
1534    case X86::CMOVAE64rr: Opc = X86::CMOVB64rr; break;
1535    case X86::CMOVE16rr:  Opc = X86::CMOVNE16rr; break;
1536    case X86::CMOVE32rr:  Opc = X86::CMOVNE32rr; break;
1537    case X86::CMOVE64rr:  Opc = X86::CMOVNE64rr; break;
1538    case X86::CMOVNE16rr: Opc = X86::CMOVE16rr; break;
1539    case X86::CMOVNE32rr: Opc = X86::CMOVE32rr; break;
1540    case X86::CMOVNE64rr: Opc = X86::CMOVE64rr; break;
1541    case X86::CMOVBE16rr: Opc = X86::CMOVA16rr; break;
1542    case X86::CMOVBE32rr: Opc = X86::CMOVA32rr; break;
1543    case X86::CMOVBE64rr: Opc = X86::CMOVA64rr; break;
1544    case X86::CMOVA16rr:  Opc = X86::CMOVBE16rr; break;
1545    case X86::CMOVA32rr:  Opc = X86::CMOVBE32rr; break;
1546    case X86::CMOVA64rr:  Opc = X86::CMOVBE64rr; break;
1547    case X86::CMOVL16rr:  Opc = X86::CMOVGE16rr; break;
1548    case X86::CMOVL32rr:  Opc = X86::CMOVGE32rr; break;
1549    case X86::CMOVL64rr:  Opc = X86::CMOVGE64rr; break;
1550    case X86::CMOVGE16rr: Opc = X86::CMOVL16rr; break;
1551    case X86::CMOVGE32rr: Opc = X86::CMOVL32rr; break;
1552    case X86::CMOVGE64rr: Opc = X86::CMOVL64rr; break;
1553    case X86::CMOVLE16rr: Opc = X86::CMOVG16rr; break;
1554    case X86::CMOVLE32rr: Opc = X86::CMOVG32rr; break;
1555    case X86::CMOVLE64rr: Opc = X86::CMOVG64rr; break;
1556    case X86::CMOVG16rr:  Opc = X86::CMOVLE16rr; break;
1557    case X86::CMOVG32rr:  Opc = X86::CMOVLE32rr; break;
1558    case X86::CMOVG64rr:  Opc = X86::CMOVLE64rr; break;
1559    case X86::CMOVS16rr:  Opc = X86::CMOVNS16rr; break;
1560    case X86::CMOVS32rr:  Opc = X86::CMOVNS32rr; break;
1561    case X86::CMOVS64rr:  Opc = X86::CMOVNS64rr; break;
1562    case X86::CMOVNS16rr: Opc = X86::CMOVS16rr; break;
1563    case X86::CMOVNS32rr: Opc = X86::CMOVS32rr; break;
1564    case X86::CMOVNS64rr: Opc = X86::CMOVS64rr; break;
1565    case X86::CMOVP16rr:  Opc = X86::CMOVNP16rr; break;
1566    case X86::CMOVP32rr:  Opc = X86::CMOVNP32rr; break;
1567    case X86::CMOVP64rr:  Opc = X86::CMOVNP64rr; break;
1568    case X86::CMOVNP16rr: Opc = X86::CMOVP16rr; break;
1569    case X86::CMOVNP32rr: Opc = X86::CMOVP32rr; break;
1570    case X86::CMOVNP64rr: Opc = X86::CMOVP64rr; break;
1571    case X86::CMOVO16rr:  Opc = X86::CMOVNO16rr; break;
1572    case X86::CMOVO32rr:  Opc = X86::CMOVNO32rr; break;
1573    case X86::CMOVO64rr:  Opc = X86::CMOVNO64rr; break;
1574    case X86::CMOVNO16rr: Opc = X86::CMOVO16rr; break;
1575    case X86::CMOVNO32rr: Opc = X86::CMOVO32rr; break;
1576    case X86::CMOVNO64rr: Opc = X86::CMOVO64rr; break;
1577    }
1578    if (NewMI) {
1579      MachineFunction &MF = *MI->getParent()->getParent();
1580      MI = MF.CloneMachineInstr(MI);
1581      NewMI = false;
1582    }
1583    MI->setDesc(get(Opc));
1584    // Fallthrough intended.
1585  }
1586  default:
1587    return TargetInstrInfoImpl::commuteInstruction(MI, NewMI);
1588  }
1589}
1590
1591static X86::CondCode GetCondFromBranchOpc(unsigned BrOpc) {
1592  switch (BrOpc) {
1593  default: return X86::COND_INVALID;
1594  case X86::JE_4:  return X86::COND_E;
1595  case X86::JNE_4: return X86::COND_NE;
1596  case X86::JL_4:  return X86::COND_L;
1597  case X86::JLE_4: return X86::COND_LE;
1598  case X86::JG_4:  return X86::COND_G;
1599  case X86::JGE_4: return X86::COND_GE;
1600  case X86::JB_4:  return X86::COND_B;
1601  case X86::JBE_4: return X86::COND_BE;
1602  case X86::JA_4:  return X86::COND_A;
1603  case X86::JAE_4: return X86::COND_AE;
1604  case X86::JS_4:  return X86::COND_S;
1605  case X86::JNS_4: return X86::COND_NS;
1606  case X86::JP_4:  return X86::COND_P;
1607  case X86::JNP_4: return X86::COND_NP;
1608  case X86::JO_4:  return X86::COND_O;
1609  case X86::JNO_4: return X86::COND_NO;
1610  }
1611}
1612
1613unsigned X86::GetCondBranchFromCond(X86::CondCode CC) {
1614  switch (CC) {
1615  default: llvm_unreachable("Illegal condition code!");
1616  case X86::COND_E:  return X86::JE_4;
1617  case X86::COND_NE: return X86::JNE_4;
1618  case X86::COND_L:  return X86::JL_4;
1619  case X86::COND_LE: return X86::JLE_4;
1620  case X86::COND_G:  return X86::JG_4;
1621  case X86::COND_GE: return X86::JGE_4;
1622  case X86::COND_B:  return X86::JB_4;
1623  case X86::COND_BE: return X86::JBE_4;
1624  case X86::COND_A:  return X86::JA_4;
1625  case X86::COND_AE: return X86::JAE_4;
1626  case X86::COND_S:  return X86::JS_4;
1627  case X86::COND_NS: return X86::JNS_4;
1628  case X86::COND_P:  return X86::JP_4;
1629  case X86::COND_NP: return X86::JNP_4;
1630  case X86::COND_O:  return X86::JO_4;
1631  case X86::COND_NO: return X86::JNO_4;
1632  }
1633}
1634
1635/// GetOppositeBranchCondition - Return the inverse of the specified condition,
1636/// e.g. turning COND_E to COND_NE.
1637X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) {
1638  switch (CC) {
1639  default: llvm_unreachable("Illegal condition code!");
1640  case X86::COND_E:  return X86::COND_NE;
1641  case X86::COND_NE: return X86::COND_E;
1642  case X86::COND_L:  return X86::COND_GE;
1643  case X86::COND_LE: return X86::COND_G;
1644  case X86::COND_G:  return X86::COND_LE;
1645  case X86::COND_GE: return X86::COND_L;
1646  case X86::COND_B:  return X86::COND_AE;
1647  case X86::COND_BE: return X86::COND_A;
1648  case X86::COND_A:  return X86::COND_BE;
1649  case X86::COND_AE: return X86::COND_B;
1650  case X86::COND_S:  return X86::COND_NS;
1651  case X86::COND_NS: return X86::COND_S;
1652  case X86::COND_P:  return X86::COND_NP;
1653  case X86::COND_NP: return X86::COND_P;
1654  case X86::COND_O:  return X86::COND_NO;
1655  case X86::COND_NO: return X86::COND_O;
1656  }
1657}
1658
1659bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
1660  const TargetInstrDesc &TID = MI->getDesc();
1661  if (!TID.isTerminator()) return false;
1662
1663  // Conditional branch is a special case.
1664  if (TID.isBranch() && !TID.isBarrier())
1665    return true;
1666  if (!TID.isPredicable())
1667    return true;
1668  return !isPredicated(MI);
1669}
1670
1671// For purposes of branch analysis do not count FP_REG_KILL as a terminator.
1672static bool isBrAnalysisUnpredicatedTerminator(const MachineInstr *MI,
1673                                               const X86InstrInfo &TII) {
1674  if (MI->getOpcode() == X86::FP_REG_KILL)
1675    return false;
1676  return TII.isUnpredicatedTerminator(MI);
1677}
1678
1679bool X86InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
1680                                 MachineBasicBlock *&TBB,
1681                                 MachineBasicBlock *&FBB,
1682                                 SmallVectorImpl<MachineOperand> &Cond,
1683                                 bool AllowModify) const {
1684  // Start from the bottom of the block and work up, examining the
1685  // terminator instructions.
1686  MachineBasicBlock::iterator I = MBB.end();
1687  while (I != MBB.begin()) {
1688    --I;
1689    if (I->isDebugValue())
1690      continue;
1691
1692    // Working from the bottom, when we see a non-terminator instruction, we're
1693    // done.
1694    if (!isBrAnalysisUnpredicatedTerminator(I, *this))
1695      break;
1696
1697    // A terminator that isn't a branch can't easily be handled by this
1698    // analysis.
1699    if (!I->getDesc().isBranch())
1700      return true;
1701
1702    // Handle unconditional branches.
1703    if (I->getOpcode() == X86::JMP_4) {
1704      if (!AllowModify) {
1705        TBB = I->getOperand(0).getMBB();
1706        continue;
1707      }
1708
1709      // If the block has any instructions after a JMP, delete them.
1710      while (llvm::next(I) != MBB.end())
1711        llvm::next(I)->eraseFromParent();
1712
1713      Cond.clear();
1714      FBB = 0;
1715
1716      // Delete the JMP if it's equivalent to a fall-through.
1717      if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
1718        TBB = 0;
1719        I->eraseFromParent();
1720        I = MBB.end();
1721        continue;
1722      }
1723
1724      // TBB is used to indicate the unconditinal destination.
1725      TBB = I->getOperand(0).getMBB();
1726      continue;
1727    }
1728
1729    // Handle conditional branches.
1730    X86::CondCode BranchCode = GetCondFromBranchOpc(I->getOpcode());
1731    if (BranchCode == X86::COND_INVALID)
1732      return true;  // Can't handle indirect branch.
1733
1734    // Working from the bottom, handle the first conditional branch.
1735    if (Cond.empty()) {
1736      FBB = TBB;
1737      TBB = I->getOperand(0).getMBB();
1738      Cond.push_back(MachineOperand::CreateImm(BranchCode));
1739      continue;
1740    }
1741
1742    // Handle subsequent conditional branches. Only handle the case where all
1743    // conditional branches branch to the same destination and their condition
1744    // opcodes fit one of the special multi-branch idioms.
1745    assert(Cond.size() == 1);
1746    assert(TBB);
1747
1748    // Only handle the case where all conditional branches branch to the same
1749    // destination.
1750    if (TBB != I->getOperand(0).getMBB())
1751      return true;
1752
1753    // If the conditions are the same, we can leave them alone.
1754    X86::CondCode OldBranchCode = (X86::CondCode)Cond[0].getImm();
1755    if (OldBranchCode == BranchCode)
1756      continue;
1757
1758    // If they differ, see if they fit one of the known patterns. Theoretically,
1759    // we could handle more patterns here, but we shouldn't expect to see them
1760    // if instruction selection has done a reasonable job.
1761    if ((OldBranchCode == X86::COND_NP &&
1762         BranchCode == X86::COND_E) ||
1763        (OldBranchCode == X86::COND_E &&
1764         BranchCode == X86::COND_NP))
1765      BranchCode = X86::COND_NP_OR_E;
1766    else if ((OldBranchCode == X86::COND_P &&
1767              BranchCode == X86::COND_NE) ||
1768             (OldBranchCode == X86::COND_NE &&
1769              BranchCode == X86::COND_P))
1770      BranchCode = X86::COND_NE_OR_P;
1771    else
1772      return true;
1773
1774    // Update the MachineOperand.
1775    Cond[0].setImm(BranchCode);
1776  }
1777
1778  return false;
1779}
1780
1781unsigned X86InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
1782  MachineBasicBlock::iterator I = MBB.end();
1783  unsigned Count = 0;
1784
1785  while (I != MBB.begin()) {
1786    --I;
1787    if (I->isDebugValue())
1788      continue;
1789    if (I->getOpcode() != X86::JMP_4 &&
1790        GetCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID)
1791      break;
1792    // Remove the branch.
1793    I->eraseFromParent();
1794    I = MBB.end();
1795    ++Count;
1796  }
1797
1798  return Count;
1799}
1800
1801unsigned
1802X86InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
1803                           MachineBasicBlock *FBB,
1804                           const SmallVectorImpl<MachineOperand> &Cond) const {
1805  // FIXME this should probably have a DebugLoc operand
1806  DebugLoc dl;
1807  // Shouldn't be a fall through.
1808  assert(TBB && "InsertBranch must not be told to insert a fallthrough");
1809  assert((Cond.size() == 1 || Cond.size() == 0) &&
1810         "X86 branch conditions have one component!");
1811
1812  if (Cond.empty()) {
1813    // Unconditional branch?
1814    assert(!FBB && "Unconditional branch with multiple successors!");
1815    BuildMI(&MBB, dl, get(X86::JMP_4)).addMBB(TBB);
1816    return 1;
1817  }
1818
1819  // Conditional branch.
1820  unsigned Count = 0;
1821  X86::CondCode CC = (X86::CondCode)Cond[0].getImm();
1822  switch (CC) {
1823  case X86::COND_NP_OR_E:
1824    // Synthesize NP_OR_E with two branches.
1825    BuildMI(&MBB, dl, get(X86::JNP_4)).addMBB(TBB);
1826    ++Count;
1827    BuildMI(&MBB, dl, get(X86::JE_4)).addMBB(TBB);
1828    ++Count;
1829    break;
1830  case X86::COND_NE_OR_P:
1831    // Synthesize NE_OR_P with two branches.
1832    BuildMI(&MBB, dl, get(X86::JNE_4)).addMBB(TBB);
1833    ++Count;
1834    BuildMI(&MBB, dl, get(X86::JP_4)).addMBB(TBB);
1835    ++Count;
1836    break;
1837  default: {
1838    unsigned Opc = GetCondBranchFromCond(CC);
1839    BuildMI(&MBB, dl, get(Opc)).addMBB(TBB);
1840    ++Count;
1841  }
1842  }
1843  if (FBB) {
1844    // Two-way Conditional branch. Insert the second branch.
1845    BuildMI(&MBB, dl, get(X86::JMP_4)).addMBB(FBB);
1846    ++Count;
1847  }
1848  return Count;
1849}
1850
1851/// isHReg - Test if the given register is a physical h register.
1852static bool isHReg(unsigned Reg) {
1853  return X86::GR8_ABCD_HRegClass.contains(Reg);
1854}
1855
1856bool X86InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
1857                                MachineBasicBlock::iterator MI,
1858                                unsigned DestReg, unsigned SrcReg,
1859                                const TargetRegisterClass *DestRC,
1860                                const TargetRegisterClass *SrcRC) const {
1861  DebugLoc DL = MBB.findDebugLoc(MI);
1862
1863  // Determine if DstRC and SrcRC have a common superclass in common.
1864  const TargetRegisterClass *CommonRC = DestRC;
1865  if (DestRC == SrcRC)
1866    /* Source and destination have the same register class. */;
1867  else if (CommonRC->hasSuperClass(SrcRC))
1868    CommonRC = SrcRC;
1869  else if (!DestRC->hasSubClass(SrcRC)) {
1870    // Neither of GR64_NOREX or GR64_NOSP is a superclass of the other,
1871    // but we want to copy them as GR64. Similarly, for GR32_NOREX and
1872    // GR32_NOSP, copy as GR32.
1873    if (SrcRC->hasSuperClass(&X86::GR64RegClass) &&
1874        DestRC->hasSuperClass(&X86::GR64RegClass))
1875      CommonRC = &X86::GR64RegClass;
1876    else if (SrcRC->hasSuperClass(&X86::GR32RegClass) &&
1877             DestRC->hasSuperClass(&X86::GR32RegClass))
1878      CommonRC = &X86::GR32RegClass;
1879    else
1880      CommonRC = 0;
1881  }
1882
1883  if (CommonRC) {
1884    unsigned Opc;
1885    if (CommonRC == &X86::GR64RegClass || CommonRC == &X86::GR64_NOSPRegClass) {
1886      Opc = X86::MOV64rr;
1887    } else if (CommonRC == &X86::GR32RegClass ||
1888               CommonRC == &X86::GR32_NOSPRegClass) {
1889      Opc = X86::MOV32rr;
1890    } else if (CommonRC == &X86::GR16RegClass) {
1891      Opc = X86::MOV16rr;
1892    } else if (CommonRC == &X86::GR8RegClass) {
1893      // Copying to or from a physical H register on x86-64 requires a NOREX
1894      // move.  Otherwise use a normal move.
1895      if ((isHReg(DestReg) || isHReg(SrcReg)) &&
1896          TM.getSubtarget<X86Subtarget>().is64Bit())
1897        Opc = X86::MOV8rr_NOREX;
1898      else
1899        Opc = X86::MOV8rr;
1900    } else if (CommonRC == &X86::GR64_ABCDRegClass) {
1901      Opc = X86::MOV64rr;
1902    } else if (CommonRC == &X86::GR32_ABCDRegClass) {
1903      Opc = X86::MOV32rr;
1904    } else if (CommonRC == &X86::GR16_ABCDRegClass) {
1905      Opc = X86::MOV16rr;
1906    } else if (CommonRC == &X86::GR8_ABCD_LRegClass) {
1907      Opc = X86::MOV8rr;
1908    } else if (CommonRC == &X86::GR8_ABCD_HRegClass) {
1909      if (TM.getSubtarget<X86Subtarget>().is64Bit())
1910        Opc = X86::MOV8rr_NOREX;
1911      else
1912        Opc = X86::MOV8rr;
1913    } else if (CommonRC == &X86::GR64_NOREXRegClass ||
1914               CommonRC == &X86::GR64_NOREX_NOSPRegClass) {
1915      Opc = X86::MOV64rr;
1916    } else if (CommonRC == &X86::GR32_NOREXRegClass) {
1917      Opc = X86::MOV32rr;
1918    } else if (CommonRC == &X86::GR16_NOREXRegClass) {
1919      Opc = X86::MOV16rr;
1920    } else if (CommonRC == &X86::GR8_NOREXRegClass) {
1921      Opc = X86::MOV8rr;
1922    } else if (CommonRC == &X86::GR64_TCRegClass) {
1923      Opc = X86::MOV64rr_TC;
1924    } else if (CommonRC == &X86::GR32_TCRegClass) {
1925      Opc = X86::MOV32rr_TC;
1926    } else if (CommonRC == &X86::RFP32RegClass) {
1927      Opc = X86::MOV_Fp3232;
1928    } else if (CommonRC == &X86::RFP64RegClass || CommonRC == &X86::RSTRegClass) {
1929      Opc = X86::MOV_Fp6464;
1930    } else if (CommonRC == &X86::RFP80RegClass) {
1931      Opc = X86::MOV_Fp8080;
1932    } else if (CommonRC == &X86::FR32RegClass) {
1933      Opc = X86::FsMOVAPSrr;
1934    } else if (CommonRC == &X86::FR64RegClass) {
1935      Opc = X86::FsMOVAPDrr;
1936    } else if (CommonRC == &X86::VR128RegClass) {
1937      Opc = X86::MOVAPSrr;
1938    } else if (CommonRC == &X86::VR64RegClass) {
1939      Opc = X86::MMX_MOVQ64rr;
1940    } else {
1941      return false;
1942    }
1943    BuildMI(MBB, MI, DL, get(Opc), DestReg).addReg(SrcReg);
1944    return true;
1945  }
1946
1947  // Moving EFLAGS to / from another register requires a push and a pop.
1948  if (SrcRC == &X86::CCRRegClass) {
1949    if (SrcReg != X86::EFLAGS)
1950      return false;
1951    if (DestRC == &X86::GR64RegClass || DestRC == &X86::GR64_NOSPRegClass) {
1952      BuildMI(MBB, MI, DL, get(X86::PUSHFQ64));
1953      BuildMI(MBB, MI, DL, get(X86::POP64r), DestReg);
1954      return true;
1955    } else if (DestRC == &X86::GR32RegClass ||
1956               DestRC == &X86::GR32_NOSPRegClass) {
1957      BuildMI(MBB, MI, DL, get(X86::PUSHFD));
1958      BuildMI(MBB, MI, DL, get(X86::POP32r), DestReg);
1959      return true;
1960    }
1961  } else if (DestRC == &X86::CCRRegClass) {
1962    if (DestReg != X86::EFLAGS)
1963      return false;
1964    if (SrcRC == &X86::GR64RegClass || DestRC == &X86::GR64_NOSPRegClass) {
1965      BuildMI(MBB, MI, DL, get(X86::PUSH64r)).addReg(SrcReg);
1966      BuildMI(MBB, MI, DL, get(X86::POPFQ));
1967      return true;
1968    } else if (SrcRC == &X86::GR32RegClass ||
1969               DestRC == &X86::GR32_NOSPRegClass) {
1970      BuildMI(MBB, MI, DL, get(X86::PUSH32r)).addReg(SrcReg);
1971      BuildMI(MBB, MI, DL, get(X86::POPFD));
1972      return true;
1973    }
1974  }
1975
1976  // Moving from ST(0) turns into FpGET_ST0_32 etc.
1977  if (SrcRC == &X86::RSTRegClass) {
1978    // Copying from ST(0)/ST(1).
1979    if (SrcReg != X86::ST0 && SrcReg != X86::ST1)
1980      // Can only copy from ST(0)/ST(1) right now
1981      return false;
1982    bool isST0 = SrcReg == X86::ST0;
1983    unsigned Opc;
1984    if (DestRC == &X86::RFP32RegClass)
1985      Opc = isST0 ? X86::FpGET_ST0_32 : X86::FpGET_ST1_32;
1986    else if (DestRC == &X86::RFP64RegClass)
1987      Opc = isST0 ? X86::FpGET_ST0_64 : X86::FpGET_ST1_64;
1988    else {
1989      if (DestRC != &X86::RFP80RegClass)
1990        return false;
1991      Opc = isST0 ? X86::FpGET_ST0_80 : X86::FpGET_ST1_80;
1992    }
1993    BuildMI(MBB, MI, DL, get(Opc), DestReg);
1994    return true;
1995  }
1996
1997  // Moving to ST(0) turns into FpSET_ST0_32 etc.
1998  if (DestRC == &X86::RSTRegClass) {
1999    // Copying to ST(0) / ST(1).
2000    if (DestReg != X86::ST0 && DestReg != X86::ST1)
2001      // Can only copy to TOS right now
2002      return false;
2003    bool isST0 = DestReg == X86::ST0;
2004    unsigned Opc;
2005    if (SrcRC == &X86::RFP32RegClass)
2006      Opc = isST0 ? X86::FpSET_ST0_32 : X86::FpSET_ST1_32;
2007    else if (SrcRC == &X86::RFP64RegClass)
2008      Opc = isST0 ? X86::FpSET_ST0_64 : X86::FpSET_ST1_64;
2009    else {
2010      if (SrcRC != &X86::RFP80RegClass)
2011        return false;
2012      Opc = isST0 ? X86::FpSET_ST0_80 : X86::FpSET_ST1_80;
2013    }
2014    BuildMI(MBB, MI, DL, get(Opc)).addReg(SrcReg);
2015    return true;
2016  }
2017
2018  // Not yet supported!
2019  return false;
2020}
2021
2022static unsigned getStoreRegOpcode(unsigned SrcReg,
2023                                  const TargetRegisterClass *RC,
2024                                  bool isStackAligned,
2025                                  TargetMachine &TM) {
2026  unsigned Opc = 0;
2027  if (RC == &X86::GR64RegClass || RC == &X86::GR64_NOSPRegClass) {
2028    Opc = X86::MOV64mr;
2029  } else if (RC == &X86::GR32RegClass || RC == &X86::GR32_NOSPRegClass) {
2030    Opc = X86::MOV32mr;
2031  } else if (RC == &X86::GR16RegClass) {
2032    Opc = X86::MOV16mr;
2033  } else if (RC == &X86::GR8RegClass) {
2034    // Copying to or from a physical H register on x86-64 requires a NOREX
2035    // move.  Otherwise use a normal move.
2036    if (isHReg(SrcReg) &&
2037        TM.getSubtarget<X86Subtarget>().is64Bit())
2038      Opc = X86::MOV8mr_NOREX;
2039    else
2040      Opc = X86::MOV8mr;
2041  } else if (RC == &X86::GR64_ABCDRegClass) {
2042    Opc = X86::MOV64mr;
2043  } else if (RC == &X86::GR32_ABCDRegClass) {
2044    Opc = X86::MOV32mr;
2045  } else if (RC == &X86::GR16_ABCDRegClass) {
2046    Opc = X86::MOV16mr;
2047  } else if (RC == &X86::GR8_ABCD_LRegClass) {
2048    Opc = X86::MOV8mr;
2049  } else if (RC == &X86::GR8_ABCD_HRegClass) {
2050    if (TM.getSubtarget<X86Subtarget>().is64Bit())
2051      Opc = X86::MOV8mr_NOREX;
2052    else
2053      Opc = X86::MOV8mr;
2054  } else if (RC == &X86::GR64_NOREXRegClass ||
2055             RC == &X86::GR64_NOREX_NOSPRegClass) {
2056    Opc = X86::MOV64mr;
2057  } else if (RC == &X86::GR32_NOREXRegClass) {
2058    Opc = X86::MOV32mr;
2059  } else if (RC == &X86::GR16_NOREXRegClass) {
2060    Opc = X86::MOV16mr;
2061  } else if (RC == &X86::GR8_NOREXRegClass) {
2062    Opc = X86::MOV8mr;
2063  } else if (RC == &X86::GR64_TCRegClass) {
2064    Opc = X86::MOV64mr_TC;
2065  } else if (RC == &X86::GR32_TCRegClass) {
2066    Opc = X86::MOV32mr_TC;
2067  } else if (RC == &X86::RFP80RegClass) {
2068    Opc = X86::ST_FpP80m;   // pops
2069  } else if (RC == &X86::RFP64RegClass) {
2070    Opc = X86::ST_Fp64m;
2071  } else if (RC == &X86::RFP32RegClass) {
2072    Opc = X86::ST_Fp32m;
2073  } else if (RC == &X86::FR32RegClass) {
2074    Opc = X86::MOVSSmr;
2075  } else if (RC == &X86::FR64RegClass) {
2076    Opc = X86::MOVSDmr;
2077  } else if (RC == &X86::VR128RegClass) {
2078    // If stack is realigned we can use aligned stores.
2079    Opc = isStackAligned ? X86::MOVAPSmr : X86::MOVUPSmr;
2080  } else if (RC == &X86::VR64RegClass) {
2081    Opc = X86::MMX_MOVQ64mr;
2082  } else {
2083    llvm_unreachable("Unknown regclass");
2084  }
2085
2086  return Opc;
2087}
2088
2089void X86InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
2090                                       MachineBasicBlock::iterator MI,
2091                                       unsigned SrcReg, bool isKill, int FrameIdx,
2092                                       const TargetRegisterClass *RC) const {
2093  const MachineFunction &MF = *MBB.getParent();
2094  bool isAligned = (RI.getStackAlignment() >= 16) || RI.canRealignStack(MF);
2095  unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, TM);
2096  DebugLoc DL = MBB.findDebugLoc(MI);
2097  addFrameReference(BuildMI(MBB, MI, DL, get(Opc)), FrameIdx)
2098    .addReg(SrcReg, getKillRegState(isKill));
2099}
2100
2101void X86InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
2102                                  bool isKill,
2103                                  SmallVectorImpl<MachineOperand> &Addr,
2104                                  const TargetRegisterClass *RC,
2105                                  MachineInstr::mmo_iterator MMOBegin,
2106                                  MachineInstr::mmo_iterator MMOEnd,
2107                                  SmallVectorImpl<MachineInstr*> &NewMIs) const {
2108  bool isAligned = (*MMOBegin)->getAlignment() >= 16;
2109  unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, TM);
2110  DebugLoc DL;
2111  MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc));
2112  for (unsigned i = 0, e = Addr.size(); i != e; ++i)
2113    MIB.addOperand(Addr[i]);
2114  MIB.addReg(SrcReg, getKillRegState(isKill));
2115  (*MIB).setMemRefs(MMOBegin, MMOEnd);
2116  NewMIs.push_back(MIB);
2117}
2118
2119static unsigned getLoadRegOpcode(unsigned DestReg,
2120                                 const TargetRegisterClass *RC,
2121                                 bool isStackAligned,
2122                                 const TargetMachine &TM) {
2123  unsigned Opc = 0;
2124  if (RC == &X86::GR64RegClass || RC == &X86::GR64_NOSPRegClass) {
2125    Opc = X86::MOV64rm;
2126  } else if (RC == &X86::GR32RegClass || RC == &X86::GR32_NOSPRegClass) {
2127    Opc = X86::MOV32rm;
2128  } else if (RC == &X86::GR16RegClass) {
2129    Opc = X86::MOV16rm;
2130  } else if (RC == &X86::GR8RegClass) {
2131    // Copying to or from a physical H register on x86-64 requires a NOREX
2132    // move.  Otherwise use a normal move.
2133    if (isHReg(DestReg) &&
2134        TM.getSubtarget<X86Subtarget>().is64Bit())
2135      Opc = X86::MOV8rm_NOREX;
2136    else
2137      Opc = X86::MOV8rm;
2138  } else if (RC == &X86::GR64_ABCDRegClass) {
2139    Opc = X86::MOV64rm;
2140  } else if (RC == &X86::GR32_ABCDRegClass) {
2141    Opc = X86::MOV32rm;
2142  } else if (RC == &X86::GR16_ABCDRegClass) {
2143    Opc = X86::MOV16rm;
2144  } else if (RC == &X86::GR8_ABCD_LRegClass) {
2145    Opc = X86::MOV8rm;
2146  } else if (RC == &X86::GR8_ABCD_HRegClass) {
2147    if (TM.getSubtarget<X86Subtarget>().is64Bit())
2148      Opc = X86::MOV8rm_NOREX;
2149    else
2150      Opc = X86::MOV8rm;
2151  } else if (RC == &X86::GR64_NOREXRegClass ||
2152             RC == &X86::GR64_NOREX_NOSPRegClass) {
2153    Opc = X86::MOV64rm;
2154  } else if (RC == &X86::GR32_NOREXRegClass) {
2155    Opc = X86::MOV32rm;
2156  } else if (RC == &X86::GR16_NOREXRegClass) {
2157    Opc = X86::MOV16rm;
2158  } else if (RC == &X86::GR8_NOREXRegClass) {
2159    Opc = X86::MOV8rm;
2160  } else if (RC == &X86::GR64_TCRegClass) {
2161    Opc = X86::MOV64rm_TC;
2162  } else if (RC == &X86::GR32_TCRegClass) {
2163    Opc = X86::MOV32rm_TC;
2164  } else if (RC == &X86::RFP80RegClass) {
2165    Opc = X86::LD_Fp80m;
2166  } else if (RC == &X86::RFP64RegClass) {
2167    Opc = X86::LD_Fp64m;
2168  } else if (RC == &X86::RFP32RegClass) {
2169    Opc = X86::LD_Fp32m;
2170  } else if (RC == &X86::FR32RegClass) {
2171    Opc = X86::MOVSSrm;
2172  } else if (RC == &X86::FR64RegClass) {
2173    Opc = X86::MOVSDrm;
2174  } else if (RC == &X86::VR128RegClass) {
2175    // If stack is realigned we can use aligned loads.
2176    Opc = isStackAligned ? X86::MOVAPSrm : X86::MOVUPSrm;
2177  } else if (RC == &X86::VR64RegClass) {
2178    Opc = X86::MMX_MOVQ64rm;
2179  } else {
2180    llvm_unreachable("Unknown regclass");
2181  }
2182
2183  return Opc;
2184}
2185
2186void X86InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
2187                                        MachineBasicBlock::iterator MI,
2188                                        unsigned DestReg, int FrameIdx,
2189                                        const TargetRegisterClass *RC) const{
2190  const MachineFunction &MF = *MBB.getParent();
2191  bool isAligned = (RI.getStackAlignment() >= 16) || RI.canRealignStack(MF);
2192  unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, TM);
2193  DebugLoc DL = MBB.findDebugLoc(MI);
2194  addFrameReference(BuildMI(MBB, MI, DL, get(Opc), DestReg), FrameIdx);
2195}
2196
2197void X86InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
2198                                 SmallVectorImpl<MachineOperand> &Addr,
2199                                 const TargetRegisterClass *RC,
2200                                 MachineInstr::mmo_iterator MMOBegin,
2201                                 MachineInstr::mmo_iterator MMOEnd,
2202                                 SmallVectorImpl<MachineInstr*> &NewMIs) const {
2203  bool isAligned = (*MMOBegin)->getAlignment() >= 16;
2204  unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, TM);
2205  DebugLoc DL;
2206  MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
2207  for (unsigned i = 0, e = Addr.size(); i != e; ++i)
2208    MIB.addOperand(Addr[i]);
2209  (*MIB).setMemRefs(MMOBegin, MMOEnd);
2210  NewMIs.push_back(MIB);
2211}
2212
2213bool X86InstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
2214                                             MachineBasicBlock::iterator MI,
2215                                const std::vector<CalleeSavedInfo> &CSI) const {
2216  if (CSI.empty())
2217    return false;
2218
2219  DebugLoc DL = MBB.findDebugLoc(MI);
2220
2221  bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit();
2222  bool isWin64 = TM.getSubtarget<X86Subtarget>().isTargetWin64();
2223  unsigned SlotSize = is64Bit ? 8 : 4;
2224
2225  MachineFunction &MF = *MBB.getParent();
2226  unsigned FPReg = RI.getFrameRegister(MF);
2227  X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
2228  unsigned CalleeFrameSize = 0;
2229
2230  unsigned Opc = is64Bit ? X86::PUSH64r : X86::PUSH32r;
2231  for (unsigned i = CSI.size(); i != 0; --i) {
2232    unsigned Reg = CSI[i-1].getReg();
2233    const TargetRegisterClass *RegClass = CSI[i-1].getRegClass();
2234    // Add the callee-saved register as live-in. It's killed at the spill.
2235    MBB.addLiveIn(Reg);
2236    if (Reg == FPReg)
2237      // X86RegisterInfo::emitPrologue will handle spilling of frame register.
2238      continue;
2239    if (RegClass != &X86::VR128RegClass && !isWin64) {
2240      CalleeFrameSize += SlotSize;
2241      BuildMI(MBB, MI, DL, get(Opc)).addReg(Reg, RegState::Kill);
2242    } else {
2243      storeRegToStackSlot(MBB, MI, Reg, true, CSI[i-1].getFrameIdx(), RegClass);
2244    }
2245  }
2246
2247  X86FI->setCalleeSavedFrameSize(CalleeFrameSize);
2248  return true;
2249}
2250
2251bool X86InstrInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
2252                                               MachineBasicBlock::iterator MI,
2253                                const std::vector<CalleeSavedInfo> &CSI) const {
2254  if (CSI.empty())
2255    return false;
2256
2257  DebugLoc DL = MBB.findDebugLoc(MI);
2258
2259  MachineFunction &MF = *MBB.getParent();
2260  unsigned FPReg = RI.getFrameRegister(MF);
2261  bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit();
2262  bool isWin64 = TM.getSubtarget<X86Subtarget>().isTargetWin64();
2263  unsigned Opc = is64Bit ? X86::POP64r : X86::POP32r;
2264  for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
2265    unsigned Reg = CSI[i].getReg();
2266    if (Reg == FPReg)
2267      // X86RegisterInfo::emitEpilogue will handle restoring of frame register.
2268      continue;
2269    const TargetRegisterClass *RegClass = CSI[i].getRegClass();
2270    if (RegClass != &X86::VR128RegClass && !isWin64) {
2271      BuildMI(MBB, MI, DL, get(Opc), Reg);
2272    } else {
2273      loadRegFromStackSlot(MBB, MI, Reg, CSI[i].getFrameIdx(), RegClass);
2274    }
2275  }
2276  return true;
2277}
2278
2279static MachineInstr *FuseTwoAddrInst(MachineFunction &MF, unsigned Opcode,
2280                                     const SmallVectorImpl<MachineOperand> &MOs,
2281                                     MachineInstr *MI,
2282                                     const TargetInstrInfo &TII) {
2283  // Create the base instruction with the memory operand as the first part.
2284  MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode),
2285                                              MI->getDebugLoc(), true);
2286  MachineInstrBuilder MIB(NewMI);
2287  unsigned NumAddrOps = MOs.size();
2288  for (unsigned i = 0; i != NumAddrOps; ++i)
2289    MIB.addOperand(MOs[i]);
2290  if (NumAddrOps < 4)  // FrameIndex only
2291    addOffset(MIB, 0);
2292
2293  // Loop over the rest of the ri operands, converting them over.
2294  unsigned NumOps = MI->getDesc().getNumOperands()-2;
2295  for (unsigned i = 0; i != NumOps; ++i) {
2296    MachineOperand &MO = MI->getOperand(i+2);
2297    MIB.addOperand(MO);
2298  }
2299  for (unsigned i = NumOps+2, e = MI->getNumOperands(); i != e; ++i) {
2300    MachineOperand &MO = MI->getOperand(i);
2301    MIB.addOperand(MO);
2302  }
2303  return MIB;
2304}
2305
2306static MachineInstr *FuseInst(MachineFunction &MF,
2307                              unsigned Opcode, unsigned OpNo,
2308                              const SmallVectorImpl<MachineOperand> &MOs,
2309                              MachineInstr *MI, const TargetInstrInfo &TII) {
2310  MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode),
2311                                              MI->getDebugLoc(), true);
2312  MachineInstrBuilder MIB(NewMI);
2313
2314  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
2315    MachineOperand &MO = MI->getOperand(i);
2316    if (i == OpNo) {
2317      assert(MO.isReg() && "Expected to fold into reg operand!");
2318      unsigned NumAddrOps = MOs.size();
2319      for (unsigned i = 0; i != NumAddrOps; ++i)
2320        MIB.addOperand(MOs[i]);
2321      if (NumAddrOps < 4)  // FrameIndex only
2322        addOffset(MIB, 0);
2323    } else {
2324      MIB.addOperand(MO);
2325    }
2326  }
2327  return MIB;
2328}
2329
2330static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode,
2331                                const SmallVectorImpl<MachineOperand> &MOs,
2332                                MachineInstr *MI) {
2333  MachineFunction &MF = *MI->getParent()->getParent();
2334  MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), TII.get(Opcode));
2335
2336  unsigned NumAddrOps = MOs.size();
2337  for (unsigned i = 0; i != NumAddrOps; ++i)
2338    MIB.addOperand(MOs[i]);
2339  if (NumAddrOps < 4)  // FrameIndex only
2340    addOffset(MIB, 0);
2341  return MIB.addImm(0);
2342}
2343
2344MachineInstr*
2345X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
2346                                    MachineInstr *MI, unsigned i,
2347                                    const SmallVectorImpl<MachineOperand> &MOs,
2348                                    unsigned Size, unsigned Align) const {
2349  const DenseMap<unsigned*, std::pair<unsigned,unsigned> > *OpcodeTablePtr=NULL;
2350  bool isTwoAddrFold = false;
2351  unsigned NumOps = MI->getDesc().getNumOperands();
2352  bool isTwoAddr = NumOps > 1 &&
2353    MI->getDesc().getOperandConstraint(1, TOI::TIED_TO) != -1;
2354
2355  MachineInstr *NewMI = NULL;
2356  // Folding a memory location into the two-address part of a two-address
2357  // instruction is different than folding it other places.  It requires
2358  // replacing the *two* registers with the memory location.
2359  if (isTwoAddr && NumOps >= 2 && i < 2 &&
2360      MI->getOperand(0).isReg() &&
2361      MI->getOperand(1).isReg() &&
2362      MI->getOperand(0).getReg() == MI->getOperand(1).getReg()) {
2363    OpcodeTablePtr = &RegOp2MemOpTable2Addr;
2364    isTwoAddrFold = true;
2365  } else if (i == 0) { // If operand 0
2366    if (MI->getOpcode() == X86::MOV64r0)
2367      NewMI = MakeM0Inst(*this, X86::MOV64mi32, MOs, MI);
2368    else if (MI->getOpcode() == X86::MOV32r0)
2369      NewMI = MakeM0Inst(*this, X86::MOV32mi, MOs, MI);
2370    else if (MI->getOpcode() == X86::MOV16r0)
2371      NewMI = MakeM0Inst(*this, X86::MOV16mi, MOs, MI);
2372    else if (MI->getOpcode() == X86::MOV8r0)
2373      NewMI = MakeM0Inst(*this, X86::MOV8mi, MOs, MI);
2374    if (NewMI)
2375      return NewMI;
2376
2377    OpcodeTablePtr = &RegOp2MemOpTable0;
2378  } else if (i == 1) {
2379    OpcodeTablePtr = &RegOp2MemOpTable1;
2380  } else if (i == 2) {
2381    OpcodeTablePtr = &RegOp2MemOpTable2;
2382  }
2383
2384  // If table selected...
2385  if (OpcodeTablePtr) {
2386    // Find the Opcode to fuse
2387    DenseMap<unsigned*, std::pair<unsigned,unsigned> >::const_iterator I =
2388      OpcodeTablePtr->find((unsigned*)MI->getOpcode());
2389    if (I != OpcodeTablePtr->end()) {
2390      unsigned Opcode = I->second.first;
2391      unsigned MinAlign = I->second.second;
2392      if (Align < MinAlign)
2393        return NULL;
2394      bool NarrowToMOV32rm = false;
2395      if (Size) {
2396        unsigned RCSize =  MI->getDesc().OpInfo[i].getRegClass(&RI)->getSize();
2397        if (Size < RCSize) {
2398          // Check if it's safe to fold the load. If the size of the object is
2399          // narrower than the load width, then it's not.
2400          if (Opcode != X86::MOV64rm || RCSize != 8 || Size != 4)
2401            return NULL;
2402          // If this is a 64-bit load, but the spill slot is 32, then we can do
2403          // a 32-bit load which is implicitly zero-extended. This likely is due
2404          // to liveintervalanalysis remat'ing a load from stack slot.
2405          if (MI->getOperand(0).getSubReg() || MI->getOperand(1).getSubReg())
2406            return NULL;
2407          Opcode = X86::MOV32rm;
2408          NarrowToMOV32rm = true;
2409        }
2410      }
2411
2412      if (isTwoAddrFold)
2413        NewMI = FuseTwoAddrInst(MF, Opcode, MOs, MI, *this);
2414      else
2415        NewMI = FuseInst(MF, Opcode, i, MOs, MI, *this);
2416
2417      if (NarrowToMOV32rm) {
2418        // If this is the special case where we use a MOV32rm to load a 32-bit
2419        // value and zero-extend the top bits. Change the destination register
2420        // to a 32-bit one.
2421        unsigned DstReg = NewMI->getOperand(0).getReg();
2422        if (TargetRegisterInfo::isPhysicalRegister(DstReg))
2423          NewMI->getOperand(0).setReg(RI.getSubReg(DstReg,
2424                                                   4/*x86_subreg_32bit*/));
2425        else
2426          NewMI->getOperand(0).setSubReg(4/*x86_subreg_32bit*/);
2427      }
2428      return NewMI;
2429    }
2430  }
2431
2432  // No fusion
2433  if (PrintFailedFusing)
2434    dbgs() << "We failed to fuse operand " << i << " in " << *MI;
2435  return NULL;
2436}
2437
2438
2439MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
2440                                                  MachineInstr *MI,
2441                                           const SmallVectorImpl<unsigned> &Ops,
2442                                                  int FrameIndex) const {
2443  // Check switch flag
2444  if (NoFusing) return NULL;
2445
2446  if (!MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize))
2447    switch (MI->getOpcode()) {
2448    case X86::CVTSD2SSrr:
2449    case X86::Int_CVTSD2SSrr:
2450    case X86::CVTSS2SDrr:
2451    case X86::Int_CVTSS2SDrr:
2452    case X86::RCPSSr:
2453    case X86::RCPSSr_Int:
2454    case X86::ROUNDSDr_Int:
2455    case X86::ROUNDSSr_Int:
2456    case X86::RSQRTSSr:
2457    case X86::RSQRTSSr_Int:
2458    case X86::SQRTSSr:
2459    case X86::SQRTSSr_Int:
2460      return 0;
2461    }
2462
2463  const MachineFrameInfo *MFI = MF.getFrameInfo();
2464  unsigned Size = MFI->getObjectSize(FrameIndex);
2465  unsigned Alignment = MFI->getObjectAlignment(FrameIndex);
2466  if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
2467    unsigned NewOpc = 0;
2468    unsigned RCSize = 0;
2469    switch (MI->getOpcode()) {
2470    default: return NULL;
2471    case X86::TEST8rr:  NewOpc = X86::CMP8ri; RCSize = 1; break;
2472    case X86::TEST16rr: NewOpc = X86::CMP16ri; RCSize = 2; break;
2473    case X86::TEST32rr: NewOpc = X86::CMP32ri; RCSize = 4; break;
2474    case X86::TEST64rr: NewOpc = X86::CMP64ri32; RCSize = 8; break;
2475    }
2476    // Check if it's safe to fold the load. If the size of the object is
2477    // narrower than the load width, then it's not.
2478    if (Size < RCSize)
2479      return NULL;
2480    // Change to CMPXXri r, 0 first.
2481    MI->setDesc(get(NewOpc));
2482    MI->getOperand(1).ChangeToImmediate(0);
2483  } else if (Ops.size() != 1)
2484    return NULL;
2485
2486  SmallVector<MachineOperand,4> MOs;
2487  MOs.push_back(MachineOperand::CreateFI(FrameIndex));
2488  return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, Size, Alignment);
2489}
2490
2491MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
2492                                                  MachineInstr *MI,
2493                                           const SmallVectorImpl<unsigned> &Ops,
2494                                                  MachineInstr *LoadMI) const {
2495  // Check switch flag
2496  if (NoFusing) return NULL;
2497
2498  if (!MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize))
2499    switch (MI->getOpcode()) {
2500    case X86::CVTSD2SSrr:
2501    case X86::Int_CVTSD2SSrr:
2502    case X86::CVTSS2SDrr:
2503    case X86::Int_CVTSS2SDrr:
2504    case X86::RCPSSr:
2505    case X86::RCPSSr_Int:
2506    case X86::ROUNDSDr_Int:
2507    case X86::ROUNDSSr_Int:
2508    case X86::RSQRTSSr:
2509    case X86::RSQRTSSr_Int:
2510    case X86::SQRTSSr:
2511    case X86::SQRTSSr_Int:
2512      return 0;
2513    }
2514
2515  // Determine the alignment of the load.
2516  unsigned Alignment = 0;
2517  if (LoadMI->hasOneMemOperand())
2518    Alignment = (*LoadMI->memoperands_begin())->getAlignment();
2519  else
2520    switch (LoadMI->getOpcode()) {
2521    case X86::V_SET0PS:
2522    case X86::V_SET0PD:
2523    case X86::V_SET0PI:
2524    case X86::V_SETALLONES:
2525      Alignment = 16;
2526      break;
2527    case X86::FsFLD0SD:
2528      Alignment = 8;
2529      break;
2530    case X86::FsFLD0SS:
2531      Alignment = 4;
2532      break;
2533    default:
2534      llvm_unreachable("Don't know how to fold this instruction!");
2535    }
2536  if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
2537    unsigned NewOpc = 0;
2538    switch (MI->getOpcode()) {
2539    default: return NULL;
2540    case X86::TEST8rr:  NewOpc = X86::CMP8ri; break;
2541    case X86::TEST16rr: NewOpc = X86::CMP16ri; break;
2542    case X86::TEST32rr: NewOpc = X86::CMP32ri; break;
2543    case X86::TEST64rr: NewOpc = X86::CMP64ri32; break;
2544    }
2545    // Change to CMPXXri r, 0 first.
2546    MI->setDesc(get(NewOpc));
2547    MI->getOperand(1).ChangeToImmediate(0);
2548  } else if (Ops.size() != 1)
2549    return NULL;
2550
2551  SmallVector<MachineOperand,X86AddrNumOperands> MOs;
2552  switch (LoadMI->getOpcode()) {
2553  case X86::V_SET0PS:
2554  case X86::V_SET0PD:
2555  case X86::V_SET0PI:
2556  case X86::V_SETALLONES:
2557  case X86::FsFLD0SD:
2558  case X86::FsFLD0SS: {
2559    // Folding a V_SET0P? or V_SETALLONES as a load, to ease register pressure.
2560    // Create a constant-pool entry and operands to load from it.
2561
2562    // Medium and large mode can't fold loads this way.
2563    if (TM.getCodeModel() != CodeModel::Small &&
2564        TM.getCodeModel() != CodeModel::Kernel)
2565      return NULL;
2566
2567    // x86-32 PIC requires a PIC base register for constant pools.
2568    unsigned PICBase = 0;
2569    if (TM.getRelocationModel() == Reloc::PIC_) {
2570      if (TM.getSubtarget<X86Subtarget>().is64Bit())
2571        PICBase = X86::RIP;
2572      else
2573        // FIXME: PICBase = TM.getInstrInfo()->getGlobalBaseReg(&MF);
2574        // This doesn't work for several reasons.
2575        // 1. GlobalBaseReg may have been spilled.
2576        // 2. It may not be live at MI.
2577        return NULL;
2578    }
2579
2580    // Create a constant-pool entry.
2581    MachineConstantPool &MCP = *MF.getConstantPool();
2582    const Type *Ty;
2583    if (LoadMI->getOpcode() == X86::FsFLD0SS)
2584      Ty = Type::getFloatTy(MF.getFunction()->getContext());
2585    else if (LoadMI->getOpcode() == X86::FsFLD0SD)
2586      Ty = Type::getDoubleTy(MF.getFunction()->getContext());
2587    else
2588      Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 4);
2589    Constant *C = LoadMI->getOpcode() == X86::V_SETALLONES ?
2590                    Constant::getAllOnesValue(Ty) :
2591                    Constant::getNullValue(Ty);
2592    unsigned CPI = MCP.getConstantPoolIndex(C, Alignment);
2593
2594    // Create operands to load from the constant pool entry.
2595    MOs.push_back(MachineOperand::CreateReg(PICBase, false));
2596    MOs.push_back(MachineOperand::CreateImm(1));
2597    MOs.push_back(MachineOperand::CreateReg(0, false));
2598    MOs.push_back(MachineOperand::CreateCPI(CPI, 0));
2599    MOs.push_back(MachineOperand::CreateReg(0, false));
2600    break;
2601  }
2602  default: {
2603    // Folding a normal load. Just copy the load's address operands.
2604    unsigned NumOps = LoadMI->getDesc().getNumOperands();
2605    for (unsigned i = NumOps - X86AddrNumOperands; i != NumOps; ++i)
2606      MOs.push_back(LoadMI->getOperand(i));
2607    break;
2608  }
2609  }
2610  return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, 0, Alignment);
2611}
2612
2613
2614bool X86InstrInfo::canFoldMemoryOperand(const MachineInstr *MI,
2615                                  const SmallVectorImpl<unsigned> &Ops) const {
2616  // Check switch flag
2617  if (NoFusing) return 0;
2618
2619  if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
2620    switch (MI->getOpcode()) {
2621    default: return false;
2622    case X86::TEST8rr:
2623    case X86::TEST16rr:
2624    case X86::TEST32rr:
2625    case X86::TEST64rr:
2626      return true;
2627    }
2628  }
2629
2630  if (Ops.size() != 1)
2631    return false;
2632
2633  unsigned OpNum = Ops[0];
2634  unsigned Opc = MI->getOpcode();
2635  unsigned NumOps = MI->getDesc().getNumOperands();
2636  bool isTwoAddr = NumOps > 1 &&
2637    MI->getDesc().getOperandConstraint(1, TOI::TIED_TO) != -1;
2638
2639  // Folding a memory location into the two-address part of a two-address
2640  // instruction is different than folding it other places.  It requires
2641  // replacing the *two* registers with the memory location.
2642  const DenseMap<unsigned*, std::pair<unsigned,unsigned> > *OpcodeTablePtr=NULL;
2643  if (isTwoAddr && NumOps >= 2 && OpNum < 2) {
2644    OpcodeTablePtr = &RegOp2MemOpTable2Addr;
2645  } else if (OpNum == 0) { // If operand 0
2646    switch (Opc) {
2647    case X86::MOV8r0:
2648    case X86::MOV16r0:
2649    case X86::MOV32r0:
2650    case X86::MOV64r0:
2651      return true;
2652    default: break;
2653    }
2654    OpcodeTablePtr = &RegOp2MemOpTable0;
2655  } else if (OpNum == 1) {
2656    OpcodeTablePtr = &RegOp2MemOpTable1;
2657  } else if (OpNum == 2) {
2658    OpcodeTablePtr = &RegOp2MemOpTable2;
2659  }
2660
2661  if (OpcodeTablePtr) {
2662    // Find the Opcode to fuse
2663    DenseMap<unsigned*, std::pair<unsigned,unsigned> >::const_iterator I =
2664      OpcodeTablePtr->find((unsigned*)Opc);
2665    if (I != OpcodeTablePtr->end())
2666      return true;
2667  }
2668  return false;
2669}
2670
2671bool X86InstrInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
2672                                unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
2673                                SmallVectorImpl<MachineInstr*> &NewMIs) const {
2674  DenseMap<unsigned*, std::pair<unsigned,unsigned> >::const_iterator I =
2675    MemOp2RegOpTable.find((unsigned*)MI->getOpcode());
2676  if (I == MemOp2RegOpTable.end())
2677    return false;
2678  unsigned Opc = I->second.first;
2679  unsigned Index = I->second.second & 0xf;
2680  bool FoldedLoad = I->second.second & (1 << 4);
2681  bool FoldedStore = I->second.second & (1 << 5);
2682  if (UnfoldLoad && !FoldedLoad)
2683    return false;
2684  UnfoldLoad &= FoldedLoad;
2685  if (UnfoldStore && !FoldedStore)
2686    return false;
2687  UnfoldStore &= FoldedStore;
2688
2689  const TargetInstrDesc &TID = get(Opc);
2690  const TargetOperandInfo &TOI = TID.OpInfo[Index];
2691  const TargetRegisterClass *RC = TOI.getRegClass(&RI);
2692  SmallVector<MachineOperand, X86AddrNumOperands> AddrOps;
2693  SmallVector<MachineOperand,2> BeforeOps;
2694  SmallVector<MachineOperand,2> AfterOps;
2695  SmallVector<MachineOperand,4> ImpOps;
2696  for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
2697    MachineOperand &Op = MI->getOperand(i);
2698    if (i >= Index && i < Index + X86AddrNumOperands)
2699      AddrOps.push_back(Op);
2700    else if (Op.isReg() && Op.isImplicit())
2701      ImpOps.push_back(Op);
2702    else if (i < Index)
2703      BeforeOps.push_back(Op);
2704    else if (i > Index)
2705      AfterOps.push_back(Op);
2706  }
2707
2708  // Emit the load instruction.
2709  if (UnfoldLoad) {
2710    std::pair<MachineInstr::mmo_iterator,
2711              MachineInstr::mmo_iterator> MMOs =
2712      MF.extractLoadMemRefs(MI->memoperands_begin(),
2713                            MI->memoperands_end());
2714    loadRegFromAddr(MF, Reg, AddrOps, RC, MMOs.first, MMOs.second, NewMIs);
2715    if (UnfoldStore) {
2716      // Address operands cannot be marked isKill.
2717      for (unsigned i = 1; i != 1 + X86AddrNumOperands; ++i) {
2718        MachineOperand &MO = NewMIs[0]->getOperand(i);
2719        if (MO.isReg())
2720          MO.setIsKill(false);
2721      }
2722    }
2723  }
2724
2725  // Emit the data processing instruction.
2726  MachineInstr *DataMI = MF.CreateMachineInstr(TID, MI->getDebugLoc(), true);
2727  MachineInstrBuilder MIB(DataMI);
2728
2729  if (FoldedStore)
2730    MIB.addReg(Reg, RegState::Define);
2731  for (unsigned i = 0, e = BeforeOps.size(); i != e; ++i)
2732    MIB.addOperand(BeforeOps[i]);
2733  if (FoldedLoad)
2734    MIB.addReg(Reg);
2735  for (unsigned i = 0, e = AfterOps.size(); i != e; ++i)
2736    MIB.addOperand(AfterOps[i]);
2737  for (unsigned i = 0, e = ImpOps.size(); i != e; ++i) {
2738    MachineOperand &MO = ImpOps[i];
2739    MIB.addReg(MO.getReg(),
2740               getDefRegState(MO.isDef()) |
2741               RegState::Implicit |
2742               getKillRegState(MO.isKill()) |
2743               getDeadRegState(MO.isDead()) |
2744               getUndefRegState(MO.isUndef()));
2745  }
2746  // Change CMP32ri r, 0 back to TEST32rr r, r, etc.
2747  unsigned NewOpc = 0;
2748  switch (DataMI->getOpcode()) {
2749  default: break;
2750  case X86::CMP64ri32:
2751  case X86::CMP32ri:
2752  case X86::CMP16ri:
2753  case X86::CMP8ri: {
2754    MachineOperand &MO0 = DataMI->getOperand(0);
2755    MachineOperand &MO1 = DataMI->getOperand(1);
2756    if (MO1.getImm() == 0) {
2757      switch (DataMI->getOpcode()) {
2758      default: break;
2759      case X86::CMP64ri32: NewOpc = X86::TEST64rr; break;
2760      case X86::CMP32ri:   NewOpc = X86::TEST32rr; break;
2761      case X86::CMP16ri:   NewOpc = X86::TEST16rr; break;
2762      case X86::CMP8ri:    NewOpc = X86::TEST8rr; break;
2763      }
2764      DataMI->setDesc(get(NewOpc));
2765      MO1.ChangeToRegister(MO0.getReg(), false);
2766    }
2767  }
2768  }
2769  NewMIs.push_back(DataMI);
2770
2771  // Emit the store instruction.
2772  if (UnfoldStore) {
2773    const TargetRegisterClass *DstRC = TID.OpInfo[0].getRegClass(&RI);
2774    std::pair<MachineInstr::mmo_iterator,
2775              MachineInstr::mmo_iterator> MMOs =
2776      MF.extractStoreMemRefs(MI->memoperands_begin(),
2777                             MI->memoperands_end());
2778    storeRegToAddr(MF, Reg, true, AddrOps, DstRC, MMOs.first, MMOs.second, NewMIs);
2779  }
2780
2781  return true;
2782}
2783
2784bool
2785X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
2786                                  SmallVectorImpl<SDNode*> &NewNodes) const {
2787  if (!N->isMachineOpcode())
2788    return false;
2789
2790  DenseMap<unsigned*, std::pair<unsigned,unsigned> >::const_iterator I =
2791    MemOp2RegOpTable.find((unsigned*)N->getMachineOpcode());
2792  if (I == MemOp2RegOpTable.end())
2793    return false;
2794  unsigned Opc = I->second.first;
2795  unsigned Index = I->second.second & 0xf;
2796  bool FoldedLoad = I->second.second & (1 << 4);
2797  bool FoldedStore = I->second.second & (1 << 5);
2798  const TargetInstrDesc &TID = get(Opc);
2799  const TargetRegisterClass *RC = TID.OpInfo[Index].getRegClass(&RI);
2800  unsigned NumDefs = TID.NumDefs;
2801  std::vector<SDValue> AddrOps;
2802  std::vector<SDValue> BeforeOps;
2803  std::vector<SDValue> AfterOps;
2804  DebugLoc dl = N->getDebugLoc();
2805  unsigned NumOps = N->getNumOperands();
2806  for (unsigned i = 0; i != NumOps-1; ++i) {
2807    SDValue Op = N->getOperand(i);
2808    if (i >= Index-NumDefs && i < Index-NumDefs + X86AddrNumOperands)
2809      AddrOps.push_back(Op);
2810    else if (i < Index-NumDefs)
2811      BeforeOps.push_back(Op);
2812    else if (i > Index-NumDefs)
2813      AfterOps.push_back(Op);
2814  }
2815  SDValue Chain = N->getOperand(NumOps-1);
2816  AddrOps.push_back(Chain);
2817
2818  // Emit the load instruction.
2819  SDNode *Load = 0;
2820  MachineFunction &MF = DAG.getMachineFunction();
2821  if (FoldedLoad) {
2822    EVT VT = *RC->vt_begin();
2823    std::pair<MachineInstr::mmo_iterator,
2824              MachineInstr::mmo_iterator> MMOs =
2825      MF.extractLoadMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
2826                            cast<MachineSDNode>(N)->memoperands_end());
2827    bool isAligned = (*MMOs.first)->getAlignment() >= 16;
2828    Load = DAG.getMachineNode(getLoadRegOpcode(0, RC, isAligned, TM), dl,
2829                              VT, MVT::Other, &AddrOps[0], AddrOps.size());
2830    NewNodes.push_back(Load);
2831
2832    // Preserve memory reference information.
2833    cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second);
2834  }
2835
2836  // Emit the data processing instruction.
2837  std::vector<EVT> VTs;
2838  const TargetRegisterClass *DstRC = 0;
2839  if (TID.getNumDefs() > 0) {
2840    DstRC = TID.OpInfo[0].getRegClass(&RI);
2841    VTs.push_back(*DstRC->vt_begin());
2842  }
2843  for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
2844    EVT VT = N->getValueType(i);
2845    if (VT != MVT::Other && i >= (unsigned)TID.getNumDefs())
2846      VTs.push_back(VT);
2847  }
2848  if (Load)
2849    BeforeOps.push_back(SDValue(Load, 0));
2850  std::copy(AfterOps.begin(), AfterOps.end(), std::back_inserter(BeforeOps));
2851  SDNode *NewNode= DAG.getMachineNode(Opc, dl, VTs, &BeforeOps[0],
2852                                      BeforeOps.size());
2853  NewNodes.push_back(NewNode);
2854
2855  // Emit the store instruction.
2856  if (FoldedStore) {
2857    AddrOps.pop_back();
2858    AddrOps.push_back(SDValue(NewNode, 0));
2859    AddrOps.push_back(Chain);
2860    std::pair<MachineInstr::mmo_iterator,
2861              MachineInstr::mmo_iterator> MMOs =
2862      MF.extractStoreMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
2863                             cast<MachineSDNode>(N)->memoperands_end());
2864    bool isAligned = (*MMOs.first)->getAlignment() >= 16;
2865    SDNode *Store = DAG.getMachineNode(getStoreRegOpcode(0, DstRC,
2866                                                         isAligned, TM),
2867                                       dl, MVT::Other,
2868                                       &AddrOps[0], AddrOps.size());
2869    NewNodes.push_back(Store);
2870
2871    // Preserve memory reference information.
2872    cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second);
2873  }
2874
2875  return true;
2876}
2877
2878unsigned X86InstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc,
2879                                      bool UnfoldLoad, bool UnfoldStore,
2880                                      unsigned *LoadRegIndex) const {
2881  DenseMap<unsigned*, std::pair<unsigned,unsigned> >::const_iterator I =
2882    MemOp2RegOpTable.find((unsigned*)Opc);
2883  if (I == MemOp2RegOpTable.end())
2884    return 0;
2885  bool FoldedLoad = I->second.second & (1 << 4);
2886  bool FoldedStore = I->second.second & (1 << 5);
2887  if (UnfoldLoad && !FoldedLoad)
2888    return 0;
2889  if (UnfoldStore && !FoldedStore)
2890    return 0;
2891  if (LoadRegIndex)
2892    *LoadRegIndex = I->second.second & 0xf;
2893  return I->second.first;
2894}
2895
2896bool
2897X86InstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
2898                                     int64_t &Offset1, int64_t &Offset2) const {
2899  if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode())
2900    return false;
2901  unsigned Opc1 = Load1->getMachineOpcode();
2902  unsigned Opc2 = Load2->getMachineOpcode();
2903  switch (Opc1) {
2904  default: return false;
2905  case X86::MOV8rm:
2906  case X86::MOV16rm:
2907  case X86::MOV32rm:
2908  case X86::MOV64rm:
2909  case X86::LD_Fp32m:
2910  case X86::LD_Fp64m:
2911  case X86::LD_Fp80m:
2912  case X86::MOVSSrm:
2913  case X86::MOVSDrm:
2914  case X86::MMX_MOVD64rm:
2915  case X86::MMX_MOVQ64rm:
2916  case X86::FsMOVAPSrm:
2917  case X86::FsMOVAPDrm:
2918  case X86::MOVAPSrm:
2919  case X86::MOVUPSrm:
2920  case X86::MOVUPSrm_Int:
2921  case X86::MOVAPDrm:
2922  case X86::MOVDQArm:
2923  case X86::MOVDQUrm:
2924  case X86::MOVDQUrm_Int:
2925    break;
2926  }
2927  switch (Opc2) {
2928  default: return false;
2929  case X86::MOV8rm:
2930  case X86::MOV16rm:
2931  case X86::MOV32rm:
2932  case X86::MOV64rm:
2933  case X86::LD_Fp32m:
2934  case X86::LD_Fp64m:
2935  case X86::LD_Fp80m:
2936  case X86::MOVSSrm:
2937  case X86::MOVSDrm:
2938  case X86::MMX_MOVD64rm:
2939  case X86::MMX_MOVQ64rm:
2940  case X86::FsMOVAPSrm:
2941  case X86::FsMOVAPDrm:
2942  case X86::MOVAPSrm:
2943  case X86::MOVUPSrm:
2944  case X86::MOVUPSrm_Int:
2945  case X86::MOVAPDrm:
2946  case X86::MOVDQArm:
2947  case X86::MOVDQUrm:
2948  case X86::MOVDQUrm_Int:
2949    break;
2950  }
2951
2952  // Check if chain operands and base addresses match.
2953  if (Load1->getOperand(0) != Load2->getOperand(0) ||
2954      Load1->getOperand(5) != Load2->getOperand(5))
2955    return false;
2956  // Segment operands should match as well.
2957  if (Load1->getOperand(4) != Load2->getOperand(4))
2958    return false;
2959  // Scale should be 1, Index should be Reg0.
2960  if (Load1->getOperand(1) == Load2->getOperand(1) &&
2961      Load1->getOperand(2) == Load2->getOperand(2)) {
2962    if (cast<ConstantSDNode>(Load1->getOperand(1))->getZExtValue() != 1)
2963      return false;
2964
2965    // Now let's examine the displacements.
2966    if (isa<ConstantSDNode>(Load1->getOperand(3)) &&
2967        isa<ConstantSDNode>(Load2->getOperand(3))) {
2968      Offset1 = cast<ConstantSDNode>(Load1->getOperand(3))->getSExtValue();
2969      Offset2 = cast<ConstantSDNode>(Load2->getOperand(3))->getSExtValue();
2970      return true;
2971    }
2972  }
2973  return false;
2974}
2975
2976bool X86InstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
2977                                           int64_t Offset1, int64_t Offset2,
2978                                           unsigned NumLoads) const {
2979  assert(Offset2 > Offset1);
2980  if ((Offset2 - Offset1) / 8 > 64)
2981    return false;
2982
2983  unsigned Opc1 = Load1->getMachineOpcode();
2984  unsigned Opc2 = Load2->getMachineOpcode();
2985  if (Opc1 != Opc2)
2986    return false;  // FIXME: overly conservative?
2987
2988  switch (Opc1) {
2989  default: break;
2990  case X86::LD_Fp32m:
2991  case X86::LD_Fp64m:
2992  case X86::LD_Fp80m:
2993  case X86::MMX_MOVD64rm:
2994  case X86::MMX_MOVQ64rm:
2995    return false;
2996  }
2997
2998  EVT VT = Load1->getValueType(0);
2999  switch (VT.getSimpleVT().SimpleTy) {
3000  default: {
3001    // XMM registers. In 64-bit mode we can be a bit more aggressive since we
3002    // have 16 of them to play with.
3003    if (TM.getSubtargetImpl()->is64Bit()) {
3004      if (NumLoads >= 3)
3005        return false;
3006    } else if (NumLoads)
3007      return false;
3008    break;
3009  }
3010  case MVT::i8:
3011  case MVT::i16:
3012  case MVT::i32:
3013  case MVT::i64:
3014  case MVT::f32:
3015  case MVT::f64:
3016    if (NumLoads)
3017      return false;
3018  }
3019
3020  return true;
3021}
3022
3023
3024bool X86InstrInfo::
3025ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
3026  assert(Cond.size() == 1 && "Invalid X86 branch condition!");
3027  X86::CondCode CC = static_cast<X86::CondCode>(Cond[0].getImm());
3028  if (CC == X86::COND_NE_OR_P || CC == X86::COND_NP_OR_E)
3029    return true;
3030  Cond[0].setImm(GetOppositeBranchCondition(CC));
3031  return false;
3032}
3033
3034bool X86InstrInfo::
3035isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
3036  // FIXME: Return false for x87 stack register classes for now. We can't
3037  // allow any loads of these registers before FpGet_ST0_80.
3038  return !(RC == &X86::CCRRegClass || RC == &X86::RFP32RegClass ||
3039           RC == &X86::RFP64RegClass || RC == &X86::RFP80RegClass);
3040}
3041
3042
3043/// isX86_64ExtendedReg - Is the MachineOperand a x86-64 extended (r8 or higher)
3044/// register?  e.g. r8, xmm8, xmm13, etc.
3045bool X86InstrInfo::isX86_64ExtendedReg(unsigned RegNo) {
3046  switch (RegNo) {
3047  default: break;
3048  case X86::R8:    case X86::R9:    case X86::R10:   case X86::R11:
3049  case X86::R12:   case X86::R13:   case X86::R14:   case X86::R15:
3050  case X86::R8D:   case X86::R9D:   case X86::R10D:  case X86::R11D:
3051  case X86::R12D:  case X86::R13D:  case X86::R14D:  case X86::R15D:
3052  case X86::R8W:   case X86::R9W:   case X86::R10W:  case X86::R11W:
3053  case X86::R12W:  case X86::R13W:  case X86::R14W:  case X86::R15W:
3054  case X86::R8B:   case X86::R9B:   case X86::R10B:  case X86::R11B:
3055  case X86::R12B:  case X86::R13B:  case X86::R14B:  case X86::R15B:
3056  case X86::XMM8:  case X86::XMM9:  case X86::XMM10: case X86::XMM11:
3057  case X86::XMM12: case X86::XMM13: case X86::XMM14: case X86::XMM15:
3058    return true;
3059  }
3060  return false;
3061}
3062
3063
3064/// determineREX - Determine if the MachineInstr has to be encoded with a X86-64
3065/// REX prefix which specifies 1) 64-bit instructions, 2) non-default operand
3066/// size, and 3) use of X86-64 extended registers.
3067unsigned X86InstrInfo::determineREX(const MachineInstr &MI) {
3068  unsigned REX = 0;
3069  const TargetInstrDesc &Desc = MI.getDesc();
3070
3071  // Pseudo instructions do not need REX prefix byte.
3072  if ((Desc.TSFlags & X86II::FormMask) == X86II::Pseudo)
3073    return 0;
3074  if (Desc.TSFlags & X86II::REX_W)
3075    REX |= 1 << 3;
3076
3077  unsigned NumOps = Desc.getNumOperands();
3078  if (NumOps) {
3079    bool isTwoAddr = NumOps > 1 &&
3080      Desc.getOperandConstraint(1, TOI::TIED_TO) != -1;
3081
3082    // If it accesses SPL, BPL, SIL, or DIL, then it requires a 0x40 REX prefix.
3083    unsigned i = isTwoAddr ? 1 : 0;
3084    for (unsigned e = NumOps; i != e; ++i) {
3085      const MachineOperand& MO = MI.getOperand(i);
3086      if (MO.isReg()) {
3087        unsigned Reg = MO.getReg();
3088        if (isX86_64NonExtLowByteReg(Reg))
3089          REX |= 0x40;
3090      }
3091    }
3092
3093    switch (Desc.TSFlags & X86II::FormMask) {
3094    case X86II::MRMInitReg:
3095      if (isX86_64ExtendedReg(MI.getOperand(0)))
3096        REX |= (1 << 0) | (1 << 2);
3097      break;
3098    case X86II::MRMSrcReg: {
3099      if (isX86_64ExtendedReg(MI.getOperand(0)))
3100        REX |= 1 << 2;
3101      i = isTwoAddr ? 2 : 1;
3102      for (unsigned e = NumOps; i != e; ++i) {
3103        const MachineOperand& MO = MI.getOperand(i);
3104        if (isX86_64ExtendedReg(MO))
3105          REX |= 1 << 0;
3106      }
3107      break;
3108    }
3109    case X86II::MRMSrcMem: {
3110      if (isX86_64ExtendedReg(MI.getOperand(0)))
3111        REX |= 1 << 2;
3112      unsigned Bit = 0;
3113      i = isTwoAddr ? 2 : 1;
3114      for (; i != NumOps; ++i) {
3115        const MachineOperand& MO = MI.getOperand(i);
3116        if (MO.isReg()) {
3117          if (isX86_64ExtendedReg(MO))
3118            REX |= 1 << Bit;
3119          Bit++;
3120        }
3121      }
3122      break;
3123    }
3124    case X86II::MRM0m: case X86II::MRM1m:
3125    case X86II::MRM2m: case X86II::MRM3m:
3126    case X86II::MRM4m: case X86II::MRM5m:
3127    case X86II::MRM6m: case X86II::MRM7m:
3128    case X86II::MRMDestMem: {
3129      unsigned e = (isTwoAddr ? X86AddrNumOperands+1 : X86AddrNumOperands);
3130      i = isTwoAddr ? 1 : 0;
3131      if (NumOps > e && isX86_64ExtendedReg(MI.getOperand(e)))
3132        REX |= 1 << 2;
3133      unsigned Bit = 0;
3134      for (; i != e; ++i) {
3135        const MachineOperand& MO = MI.getOperand(i);
3136        if (MO.isReg()) {
3137          if (isX86_64ExtendedReg(MO))
3138            REX |= 1 << Bit;
3139          Bit++;
3140        }
3141      }
3142      break;
3143    }
3144    default: {
3145      if (isX86_64ExtendedReg(MI.getOperand(0)))
3146        REX |= 1 << 0;
3147      i = isTwoAddr ? 2 : 1;
3148      for (unsigned e = NumOps; i != e; ++i) {
3149        const MachineOperand& MO = MI.getOperand(i);
3150        if (isX86_64ExtendedReg(MO))
3151          REX |= 1 << 2;
3152      }
3153      break;
3154    }
3155    }
3156  }
3157  return REX;
3158}
3159
3160/// sizePCRelativeBlockAddress - This method returns the size of a PC
3161/// relative block address instruction
3162///
3163static unsigned sizePCRelativeBlockAddress() {
3164  return 4;
3165}
3166
3167/// sizeGlobalAddress - Give the size of the emission of this global address
3168///
3169static unsigned sizeGlobalAddress(bool dword) {
3170  return dword ? 8 : 4;
3171}
3172
3173/// sizeConstPoolAddress - Give the size of the emission of this constant
3174/// pool address
3175///
3176static unsigned sizeConstPoolAddress(bool dword) {
3177  return dword ? 8 : 4;
3178}
3179
3180/// sizeExternalSymbolAddress - Give the size of the emission of this external
3181/// symbol
3182///
3183static unsigned sizeExternalSymbolAddress(bool dword) {
3184  return dword ? 8 : 4;
3185}
3186
3187/// sizeJumpTableAddress - Give the size of the emission of this jump
3188/// table address
3189///
3190static unsigned sizeJumpTableAddress(bool dword) {
3191  return dword ? 8 : 4;
3192}
3193
3194static unsigned sizeConstant(unsigned Size) {
3195  return Size;
3196}
3197
3198static unsigned sizeRegModRMByte(){
3199  return 1;
3200}
3201
3202static unsigned sizeSIBByte(){
3203  return 1;
3204}
3205
3206static unsigned getDisplacementFieldSize(const MachineOperand *RelocOp) {
3207  unsigned FinalSize = 0;
3208  // If this is a simple integer displacement that doesn't require a relocation.
3209  if (!RelocOp) {
3210    FinalSize += sizeConstant(4);
3211    return FinalSize;
3212  }
3213
3214  // Otherwise, this is something that requires a relocation.
3215  if (RelocOp->isGlobal()) {
3216    FinalSize += sizeGlobalAddress(false);
3217  } else if (RelocOp->isCPI()) {
3218    FinalSize += sizeConstPoolAddress(false);
3219  } else if (RelocOp->isJTI()) {
3220    FinalSize += sizeJumpTableAddress(false);
3221  } else {
3222    llvm_unreachable("Unknown value to relocate!");
3223  }
3224  return FinalSize;
3225}
3226
3227static unsigned getMemModRMByteSize(const MachineInstr &MI, unsigned Op,
3228                                    bool IsPIC, bool Is64BitMode) {
3229  const MachineOperand &Op3 = MI.getOperand(Op+3);
3230  int DispVal = 0;
3231  const MachineOperand *DispForReloc = 0;
3232  unsigned FinalSize = 0;
3233
3234  // Figure out what sort of displacement we have to handle here.
3235  if (Op3.isGlobal()) {
3236    DispForReloc = &Op3;
3237  } else if (Op3.isCPI()) {
3238    if (Is64BitMode || IsPIC) {
3239      DispForReloc = &Op3;
3240    } else {
3241      DispVal = 1;
3242    }
3243  } else if (Op3.isJTI()) {
3244    if (Is64BitMode || IsPIC) {
3245      DispForReloc = &Op3;
3246    } else {
3247      DispVal = 1;
3248    }
3249  } else {
3250    DispVal = 1;
3251  }
3252
3253  const MachineOperand &Base     = MI.getOperand(Op);
3254  const MachineOperand &IndexReg = MI.getOperand(Op+2);
3255
3256  unsigned BaseReg = Base.getReg();
3257
3258  // Is a SIB byte needed?
3259  if ((!Is64BitMode || DispForReloc || BaseReg != 0) &&
3260      IndexReg.getReg() == 0 &&
3261      (BaseReg == 0 || X86RegisterInfo::getX86RegNum(BaseReg) != N86::ESP)) {
3262    if (BaseReg == 0) {  // Just a displacement?
3263      // Emit special case [disp32] encoding
3264      ++FinalSize;
3265      FinalSize += getDisplacementFieldSize(DispForReloc);
3266    } else {
3267      unsigned BaseRegNo = X86RegisterInfo::getX86RegNum(BaseReg);
3268      if (!DispForReloc && DispVal == 0 && BaseRegNo != N86::EBP) {
3269        // Emit simple indirect register encoding... [EAX] f.e.
3270        ++FinalSize;
3271      // Be pessimistic and assume it's a disp32, not a disp8
3272      } else {
3273        // Emit the most general non-SIB encoding: [REG+disp32]
3274        ++FinalSize;
3275        FinalSize += getDisplacementFieldSize(DispForReloc);
3276      }
3277    }
3278
3279  } else {  // We need a SIB byte, so start by outputting the ModR/M byte first
3280    assert(IndexReg.getReg() != X86::ESP &&
3281           IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!");
3282
3283    bool ForceDisp32 = false;
3284    if (BaseReg == 0 || DispForReloc) {
3285      // Emit the normal disp32 encoding.
3286      ++FinalSize;
3287      ForceDisp32 = true;
3288    } else {
3289      ++FinalSize;
3290    }
3291
3292    FinalSize += sizeSIBByte();
3293
3294    // Do we need to output a displacement?
3295    if (DispVal != 0 || ForceDisp32) {
3296      FinalSize += getDisplacementFieldSize(DispForReloc);
3297    }
3298  }
3299  return FinalSize;
3300}
3301
3302
3303static unsigned GetInstSizeWithDesc(const MachineInstr &MI,
3304                                    const TargetInstrDesc *Desc,
3305                                    bool IsPIC, bool Is64BitMode) {
3306
3307  unsigned Opcode = Desc->Opcode;
3308  unsigned FinalSize = 0;
3309
3310  // Emit the lock opcode prefix as needed.
3311  if (Desc->TSFlags & X86II::LOCK) ++FinalSize;
3312
3313  // Emit segment override opcode prefix as needed.
3314  switch (Desc->TSFlags & X86II::SegOvrMask) {
3315  case X86II::FS:
3316  case X86II::GS:
3317   ++FinalSize;
3318   break;
3319  default: llvm_unreachable("Invalid segment!");
3320  case 0: break;  // No segment override!
3321  }
3322
3323  // Emit the repeat opcode prefix as needed.
3324  if ((Desc->TSFlags & X86II::Op0Mask) == X86II::REP) ++FinalSize;
3325
3326  // Emit the operand size opcode prefix as needed.
3327  if (Desc->TSFlags & X86II::OpSize) ++FinalSize;
3328
3329  // Emit the address size opcode prefix as needed.
3330  if (Desc->TSFlags & X86II::AdSize) ++FinalSize;
3331
3332  bool Need0FPrefix = false;
3333  switch (Desc->TSFlags & X86II::Op0Mask) {
3334  case X86II::TB:  // Two-byte opcode prefix
3335  case X86II::T8:  // 0F 38
3336  case X86II::TA:  // 0F 3A
3337    Need0FPrefix = true;
3338    break;
3339  case X86II::TF: // F2 0F 38
3340    ++FinalSize;
3341    Need0FPrefix = true;
3342    break;
3343  case X86II::REP: break; // already handled.
3344  case X86II::XS:   // F3 0F
3345    ++FinalSize;
3346    Need0FPrefix = true;
3347    break;
3348  case X86II::XD:   // F2 0F
3349    ++FinalSize;
3350    Need0FPrefix = true;
3351    break;
3352  case X86II::D8: case X86II::D9: case X86II::DA: case X86II::DB:
3353  case X86II::DC: case X86II::DD: case X86II::DE: case X86II::DF:
3354    ++FinalSize;
3355    break; // Two-byte opcode prefix
3356  default: llvm_unreachable("Invalid prefix!");
3357  case 0: break;  // No prefix!
3358  }
3359
3360  if (Is64BitMode) {
3361    // REX prefix
3362    unsigned REX = X86InstrInfo::determineREX(MI);
3363    if (REX)
3364      ++FinalSize;
3365  }
3366
3367  // 0x0F escape code must be emitted just before the opcode.
3368  if (Need0FPrefix)
3369    ++FinalSize;
3370
3371  switch (Desc->TSFlags & X86II::Op0Mask) {
3372  case X86II::T8:  // 0F 38
3373    ++FinalSize;
3374    break;
3375  case X86II::TA:  // 0F 3A
3376    ++FinalSize;
3377    break;
3378  case X86II::TF: // F2 0F 38
3379    ++FinalSize;
3380    break;
3381  }
3382
3383  // If this is a two-address instruction, skip one of the register operands.
3384  unsigned NumOps = Desc->getNumOperands();
3385  unsigned CurOp = 0;
3386  if (NumOps > 1 && Desc->getOperandConstraint(1, TOI::TIED_TO) != -1)
3387    CurOp++;
3388  else if (NumOps > 2 && Desc->getOperandConstraint(NumOps-1, TOI::TIED_TO)== 0)
3389    // Skip the last source operand that is tied_to the dest reg. e.g. LXADD32
3390    --NumOps;
3391
3392  switch (Desc->TSFlags & X86II::FormMask) {
3393  default: llvm_unreachable("Unknown FormMask value in X86 MachineCodeEmitter!");
3394  case X86II::Pseudo:
3395    // Remember the current PC offset, this is the PIC relocation
3396    // base address.
3397    switch (Opcode) {
3398    default:
3399      break;
3400    case TargetOpcode::INLINEASM: {
3401      const MachineFunction *MF = MI.getParent()->getParent();
3402      const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo();
3403      FinalSize += TII.getInlineAsmLength(MI.getOperand(0).getSymbolName(),
3404                                          *MF->getTarget().getMCAsmInfo());
3405      break;
3406    }
3407    case TargetOpcode::DBG_LABEL:
3408    case TargetOpcode::EH_LABEL:
3409    case TargetOpcode::DBG_VALUE:
3410      break;
3411    case TargetOpcode::IMPLICIT_DEF:
3412    case TargetOpcode::KILL:
3413    case X86::FP_REG_KILL:
3414      break;
3415    case X86::MOVPC32r: {
3416      // This emits the "call" portion of this pseudo instruction.
3417      ++FinalSize;
3418      FinalSize += sizeConstant(X86II::getSizeOfImm(Desc->TSFlags));
3419      break;
3420    }
3421    }
3422    CurOp = NumOps;
3423    break;
3424  case X86II::RawFrm:
3425    ++FinalSize;
3426
3427    if (CurOp != NumOps) {
3428      const MachineOperand &MO = MI.getOperand(CurOp++);
3429      if (MO.isMBB()) {
3430        FinalSize += sizePCRelativeBlockAddress();
3431      } else if (MO.isGlobal()) {
3432        FinalSize += sizeGlobalAddress(false);
3433      } else if (MO.isSymbol()) {
3434        FinalSize += sizeExternalSymbolAddress(false);
3435      } else if (MO.isImm()) {
3436        FinalSize += sizeConstant(X86II::getSizeOfImm(Desc->TSFlags));
3437      } else {
3438        llvm_unreachable("Unknown RawFrm operand!");
3439      }
3440    }
3441    break;
3442
3443  case X86II::AddRegFrm:
3444    ++FinalSize;
3445    ++CurOp;
3446
3447    if (CurOp != NumOps) {
3448      const MachineOperand &MO1 = MI.getOperand(CurOp++);
3449      unsigned Size = X86II::getSizeOfImm(Desc->TSFlags);
3450      if (MO1.isImm())
3451        FinalSize += sizeConstant(Size);
3452      else {
3453        bool dword = false;
3454        if (Opcode == X86::MOV64ri)
3455          dword = true;
3456        if (MO1.isGlobal()) {
3457          FinalSize += sizeGlobalAddress(dword);
3458        } else if (MO1.isSymbol())
3459          FinalSize += sizeExternalSymbolAddress(dword);
3460        else if (MO1.isCPI())
3461          FinalSize += sizeConstPoolAddress(dword);
3462        else if (MO1.isJTI())
3463          FinalSize += sizeJumpTableAddress(dword);
3464      }
3465    }
3466    break;
3467
3468  case X86II::MRMDestReg: {
3469    ++FinalSize;
3470    FinalSize += sizeRegModRMByte();
3471    CurOp += 2;
3472    if (CurOp != NumOps) {
3473      ++CurOp;
3474      FinalSize += sizeConstant(X86II::getSizeOfImm(Desc->TSFlags));
3475    }
3476    break;
3477  }
3478  case X86II::MRMDestMem: {
3479    ++FinalSize;
3480    FinalSize += getMemModRMByteSize(MI, CurOp, IsPIC, Is64BitMode);
3481    CurOp +=  X86AddrNumOperands + 1;
3482    if (CurOp != NumOps) {
3483      ++CurOp;
3484      FinalSize += sizeConstant(X86II::getSizeOfImm(Desc->TSFlags));
3485    }
3486    break;
3487  }
3488
3489  case X86II::MRMSrcReg:
3490    ++FinalSize;
3491    FinalSize += sizeRegModRMByte();
3492    CurOp += 2;
3493    if (CurOp != NumOps) {
3494      ++CurOp;
3495      FinalSize += sizeConstant(X86II::getSizeOfImm(Desc->TSFlags));
3496    }
3497    break;
3498
3499  case X86II::MRMSrcMem: {
3500    int AddrOperands;
3501    if (Opcode == X86::LEA64r || Opcode == X86::LEA64_32r ||
3502        Opcode == X86::LEA16r || Opcode == X86::LEA32r)
3503      AddrOperands = X86AddrNumOperands - 1; // No segment register
3504    else
3505      AddrOperands = X86AddrNumOperands;
3506
3507    ++FinalSize;
3508    FinalSize += getMemModRMByteSize(MI, CurOp+1, IsPIC, Is64BitMode);
3509    CurOp += AddrOperands + 1;
3510    if (CurOp != NumOps) {
3511      ++CurOp;
3512      FinalSize += sizeConstant(X86II::getSizeOfImm(Desc->TSFlags));
3513    }
3514    break;
3515  }
3516
3517  case X86II::MRM0r: case X86II::MRM1r:
3518  case X86II::MRM2r: case X86II::MRM3r:
3519  case X86II::MRM4r: case X86II::MRM5r:
3520  case X86II::MRM6r: case X86II::MRM7r:
3521    ++FinalSize;
3522    if (Desc->getOpcode() == X86::LFENCE ||
3523        Desc->getOpcode() == X86::MFENCE) {
3524      // Special handling of lfence and mfence;
3525      FinalSize += sizeRegModRMByte();
3526    } else if (Desc->getOpcode() == X86::MONITOR ||
3527               Desc->getOpcode() == X86::MWAIT) {
3528      // Special handling of monitor and mwait.
3529      FinalSize += sizeRegModRMByte() + 1; // +1 for the opcode.
3530    } else {
3531      ++CurOp;
3532      FinalSize += sizeRegModRMByte();
3533    }
3534
3535    if (CurOp != NumOps) {
3536      const MachineOperand &MO1 = MI.getOperand(CurOp++);
3537      unsigned Size = X86II::getSizeOfImm(Desc->TSFlags);
3538      if (MO1.isImm())
3539        FinalSize += sizeConstant(Size);
3540      else {
3541        bool dword = false;
3542        if (Opcode == X86::MOV64ri32)
3543          dword = true;
3544        if (MO1.isGlobal()) {
3545          FinalSize += sizeGlobalAddress(dword);
3546        } else if (MO1.isSymbol())
3547          FinalSize += sizeExternalSymbolAddress(dword);
3548        else if (MO1.isCPI())
3549          FinalSize += sizeConstPoolAddress(dword);
3550        else if (MO1.isJTI())
3551          FinalSize += sizeJumpTableAddress(dword);
3552      }
3553    }
3554    break;
3555
3556  case X86II::MRM0m: case X86II::MRM1m:
3557  case X86II::MRM2m: case X86II::MRM3m:
3558  case X86II::MRM4m: case X86II::MRM5m:
3559  case X86II::MRM6m: case X86II::MRM7m: {
3560
3561    ++FinalSize;
3562    FinalSize += getMemModRMByteSize(MI, CurOp, IsPIC, Is64BitMode);
3563    CurOp += X86AddrNumOperands;
3564
3565    if (CurOp != NumOps) {
3566      const MachineOperand &MO = MI.getOperand(CurOp++);
3567      unsigned Size = X86II::getSizeOfImm(Desc->TSFlags);
3568      if (MO.isImm())
3569        FinalSize += sizeConstant(Size);
3570      else {
3571        bool dword = false;
3572        if (Opcode == X86::MOV64mi32)
3573          dword = true;
3574        if (MO.isGlobal()) {
3575          FinalSize += sizeGlobalAddress(dword);
3576        } else if (MO.isSymbol())
3577          FinalSize += sizeExternalSymbolAddress(dword);
3578        else if (MO.isCPI())
3579          FinalSize += sizeConstPoolAddress(dword);
3580        else if (MO.isJTI())
3581          FinalSize += sizeJumpTableAddress(dword);
3582      }
3583    }
3584    break;
3585
3586  case X86II::MRM_C1:
3587  case X86II::MRM_C8:
3588  case X86II::MRM_C9:
3589  case X86II::MRM_E8:
3590  case X86II::MRM_F0:
3591    FinalSize += 2;
3592    break;
3593  }
3594
3595  case X86II::MRMInitReg:
3596    ++FinalSize;
3597    // Duplicate register, used by things like MOV8r0 (aka xor reg,reg).
3598    FinalSize += sizeRegModRMByte();
3599    ++CurOp;
3600    break;
3601  }
3602
3603  if (!Desc->isVariadic() && CurOp != NumOps) {
3604    std::string msg;
3605    raw_string_ostream Msg(msg);
3606    Msg << "Cannot determine size: " << MI;
3607    report_fatal_error(Msg.str());
3608  }
3609
3610
3611  return FinalSize;
3612}
3613
3614
3615unsigned X86InstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
3616  const TargetInstrDesc &Desc = MI->getDesc();
3617  bool IsPIC = TM.getRelocationModel() == Reloc::PIC_;
3618  bool Is64BitMode = TM.getSubtargetImpl()->is64Bit();
3619  unsigned Size = GetInstSizeWithDesc(*MI, &Desc, IsPIC, Is64BitMode);
3620  if (Desc.getOpcode() == X86::MOVPC32r)
3621    Size += GetInstSizeWithDesc(*MI, &get(X86::POP32r), IsPIC, Is64BitMode);
3622  return Size;
3623}
3624
3625/// getGlobalBaseReg - Return a virtual register initialized with the
3626/// the global base register value. Output instructions required to
3627/// initialize the register in the function entry block, if necessary.
3628///
3629unsigned X86InstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
3630  assert(!TM.getSubtarget<X86Subtarget>().is64Bit() &&
3631         "X86-64 PIC uses RIP relative addressing");
3632
3633  X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
3634  unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
3635  if (GlobalBaseReg != 0)
3636    return GlobalBaseReg;
3637
3638  // Insert the set of GlobalBaseReg into the first MBB of the function
3639  MachineBasicBlock &FirstMBB = MF->front();
3640  MachineBasicBlock::iterator MBBI = FirstMBB.begin();
3641  DebugLoc DL = FirstMBB.findDebugLoc(MBBI);
3642  MachineRegisterInfo &RegInfo = MF->getRegInfo();
3643  unsigned PC = RegInfo.createVirtualRegister(X86::GR32RegisterClass);
3644
3645  const TargetInstrInfo *TII = TM.getInstrInfo();
3646  // Operand of MovePCtoStack is completely ignored by asm printer. It's
3647  // only used in JIT code emission as displacement to pc.
3648  BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOVPC32r), PC).addImm(0);
3649
3650  // If we're using vanilla 'GOT' PIC style, we should use relative addressing
3651  // not to pc, but to _GLOBAL_OFFSET_TABLE_ external.
3652  if (TM.getSubtarget<X86Subtarget>().isPICStyleGOT()) {
3653    GlobalBaseReg = RegInfo.createVirtualRegister(X86::GR32RegisterClass);
3654    // Generate addl $__GLOBAL_OFFSET_TABLE_ + [.-piclabel], %some_register
3655    BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD32ri), GlobalBaseReg)
3656      .addReg(PC).addExternalSymbol("_GLOBAL_OFFSET_TABLE_",
3657                                    X86II::MO_GOT_ABSOLUTE_ADDRESS);
3658  } else {
3659    GlobalBaseReg = PC;
3660  }
3661
3662  X86FI->setGlobalBaseReg(GlobalBaseReg);
3663  return GlobalBaseReg;
3664}
3665
3666// These are the replaceable SSE instructions. Some of these have Int variants
3667// that we don't include here. We don't want to replace instructions selected
3668// by intrinsics.
3669static const unsigned ReplaceableInstrs[][3] = {
3670  //PackedInt       PackedSingle     PackedDouble
3671  { X86::MOVAPSmr,   X86::MOVAPDmr,  X86::MOVDQAmr  },
3672  { X86::MOVAPSrm,   X86::MOVAPDrm,  X86::MOVDQArm  },
3673  { X86::MOVAPSrr,   X86::MOVAPDrr,  X86::MOVDQArr  },
3674  { X86::MOVUPSmr,   X86::MOVUPDmr,  X86::MOVDQUmr  },
3675  { X86::MOVUPSrm,   X86::MOVUPDrm,  X86::MOVDQUrm  },
3676  { X86::MOVNTPSmr,  X86::MOVNTPDmr, X86::MOVNTDQmr },
3677  { X86::ANDNPSrm,   X86::ANDNPDrm,  X86::PANDNrm   },
3678  { X86::ANDNPSrr,   X86::ANDNPDrr,  X86::PANDNrr   },
3679  { X86::ANDPSrm,    X86::ANDPDrm,   X86::PANDrm    },
3680  { X86::ANDPSrr,    X86::ANDPDrr,   X86::PANDrr    },
3681  { X86::ORPSrm,     X86::ORPDrm,    X86::PORrm     },
3682  { X86::ORPSrr,     X86::ORPDrr,    X86::PORrr     },
3683  { X86::V_SET0PS,   X86::V_SET0PD,  X86::V_SET0PI  },
3684  { X86::XORPSrm,    X86::XORPDrm,   X86::PXORrm    },
3685  { X86::XORPSrr,    X86::XORPDrr,   X86::PXORrr    },
3686};
3687
3688// FIXME: Some shuffle and unpack instructions have equivalents in different
3689// domains, but they require a bit more work than just switching opcodes.
3690
3691static const unsigned *lookup(unsigned opcode, unsigned domain) {
3692  for (unsigned i = 0, e = array_lengthof(ReplaceableInstrs); i != e; ++i)
3693    if (ReplaceableInstrs[i][domain-1] == opcode)
3694      return ReplaceableInstrs[i];
3695  return 0;
3696}
3697
3698std::pair<uint16_t, uint16_t>
3699X86InstrInfo::GetSSEDomain(const MachineInstr *MI) const {
3700  uint16_t domain = (MI->getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
3701  return std::make_pair(domain,
3702                        domain && lookup(MI->getOpcode(), domain) ? 0xe : 0);
3703}
3704
3705void X86InstrInfo::SetSSEDomain(MachineInstr *MI, unsigned Domain) const {
3706  assert(Domain>0 && Domain<4 && "Invalid execution domain");
3707  uint16_t dom = (MI->getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
3708  assert(dom && "Not an SSE instruction");
3709  const unsigned *table = lookup(MI->getOpcode(), dom);
3710  assert(table && "Cannot change domain");
3711  MI->setDesc(get(table[Domain-1]));
3712}
3713