X86InstrInfo.cpp revision bcea4d6f283a5ae6f93dc8e10898311fe53d23a3 
1//===- X86InstrInfo.cpp - X86 Instruction Information -----------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file was developed by the LLVM research group and is distributed under
6// the University of Illinois Open Source License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the X86 implementation of the TargetInstrInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "X86InstrInfo.h"
15#include "X86.h"
16#include "X86InstrBuilder.h"
17#include "llvm/CodeGen/MachineInstrBuilder.h"
18#include "X86GenInstrInfo.inc"
19using namespace llvm;
20
21X86InstrInfo::X86InstrInfo()
22  : TargetInstrInfo(X86Insts, sizeof(X86Insts)/sizeof(X86Insts[0])) {
23}
24
25
26bool X86InstrInfo::isMoveInstr(const MachineInstr& MI,
27                               unsigned& sourceReg,
28                               unsigned& destReg) const {
29  MachineOpCode oc = MI.getOpcode();
30  if (oc == X86::MOV8rr || oc == X86::MOV16rr || oc == X86::MOV32rr ||
31      oc == X86::FpMOV) {
32      assert(MI.getNumOperands() == 2 &&
33             MI.getOperand(0).isRegister() &&
34             MI.getOperand(1).isRegister() &&
35             "invalid register-register move instruction");
36      sourceReg = MI.getOperand(1).getReg();
37      destReg = MI.getOperand(0).getReg();
38      return true;
39  }
40  return false;
41}
42
43/// convertToThreeAddress - This method must be implemented by targets that
44/// set the M_CONVERTIBLE_TO_3_ADDR flag.  When this flag is set, the target
45/// may be able to convert a two-address instruction into a true
46/// three-address instruction on demand.  This allows the X86 target (for
47/// example) to convert ADD and SHL instructions into LEA instructions if they
48/// would require register copies due to two-addressness.
49///
50/// This method returns a null pointer if the transformation cannot be
51/// performed, otherwise it returns the new instruction.
52///
53MachineInstr *X86InstrInfo::convertToThreeAddress(MachineInstr *MI) const {
54  // All instructions input are two-addr instructions.  Get the known operands.
55  unsigned Dest = MI->getOperand(0).getReg();
56  unsigned Src = MI->getOperand(1).getReg();
57
58  // FIXME: 16-bit LEA's are really slow on Athlons, but not bad on P4's.  When
59  // we have subtarget support, enable the 16-bit LEA generation here.
60  bool DisableLEA16 = true;
61
62  switch (MI->getOpcode()) {
63  case X86::INC32r:
64    assert(MI->getNumOperands() == 2 && "Unknown inc instruction!");
65    return addRegOffset(BuildMI(X86::LEA32r, 5, Dest), Src, 1);
66  case X86::INC16r:
67    if (DisableLEA16) return 0;
68    assert(MI->getNumOperands() == 2 && "Unknown inc instruction!");
69    return addRegOffset(BuildMI(X86::LEA16r, 5, Dest), Src, 1);
70  case X86::DEC32r:
71    assert(MI->getNumOperands() == 2 && "Unknown dec instruction!");
72    return addRegOffset(BuildMI(X86::LEA32r, 5, Dest), Src, -1);
73  case X86::DEC16r:
74    if (DisableLEA16) return 0;
75    assert(MI->getNumOperands() == 2 && "Unknown dec instruction!");
76    return addRegOffset(BuildMI(X86::LEA16r, 5, Dest), Src, -1);
77  case X86::ADD32rr:
78    assert(MI->getNumOperands() == 3 && "Unknown add instruction!");
79    return addRegReg(BuildMI(X86::LEA32r, 5, Dest), Src,
80                     MI->getOperand(2).getReg());
81  case X86::ADD16rr:
82    if (DisableLEA16) return 0;
83    assert(MI->getNumOperands() == 3 && "Unknown add instruction!");
84    return addRegReg(BuildMI(X86::LEA16r, 5, Dest), Src,
85                     MI->getOperand(2).getReg());
86  case X86::ADD32ri:
87    assert(MI->getNumOperands() == 3 && "Unknown add instruction!");
88    if (MI->getOperand(2).isImmediate())
89      return addRegOffset(BuildMI(X86::LEA32r, 5, Dest), Src,
90                          MI->getOperand(2).getImmedValue());
91    return 0;
92  case X86::ADD16ri:
93    if (DisableLEA16) return 0;
94    assert(MI->getNumOperands() == 3 && "Unknown add instruction!");
95    if (MI->getOperand(2).isImmediate())
96      return addRegOffset(BuildMI(X86::LEA16r, 5, Dest), Src,
97                          MI->getOperand(2).getImmedValue());
98    break;
99
100  case X86::SHL16ri:
101    if (DisableLEA16) return 0;
102  case X86::SHL32ri:
103    assert(MI->getNumOperands() == 3 && MI->getOperand(2).isImmediate() &&
104           "Unknown shl instruction!");
105    unsigned ShAmt = MI->getOperand(2).getImmedValue();
106    if (ShAmt == 1 || ShAmt == 2 || ShAmt == 3) {
107      X86AddressMode AM;
108      AM.Scale = 1 << ShAmt;
109      AM.IndexReg = Src;
110      unsigned Opc = MI->getOpcode() == X86::SHL32ri ? X86::LEA32r :X86::LEA16r;
111      return addFullAddress(BuildMI(Opc, 5, Dest), AM);
112    }
113    break;
114  }
115
116  return 0;
117}
118
119
120void X86InstrInfo::insertGoto(MachineBasicBlock& MBB,
121                              MachineBasicBlock& TMBB) const {
122  BuildMI(MBB, MBB.end(), X86::JMP, 1).addMBB(&TMBB);
123}
124
125MachineBasicBlock::iterator
126X86InstrInfo::reverseBranchCondition(MachineBasicBlock::iterator MI) const {
127  unsigned Opcode = MI->getOpcode();
128  assert(isBranch(Opcode) && "MachineInstr must be a branch");
129  unsigned ROpcode;
130  switch (Opcode) {
131  default: assert(0 && "Cannot reverse unconditional branches!");
132  case X86::JB:  ROpcode = X86::JAE; break;
133  case X86::JAE: ROpcode = X86::JB;  break;
134  case X86::JE:  ROpcode = X86::JNE; break;
135  case X86::JNE: ROpcode = X86::JE;  break;
136  case X86::JBE: ROpcode = X86::JA;  break;
137  case X86::JA:  ROpcode = X86::JBE; break;
138  case X86::JS:  ROpcode = X86::JNS; break;
139  case X86::JNS: ROpcode = X86::JS;  break;
140  case X86::JP:  ROpcode = X86::JNP; break;
141  case X86::JNP: ROpcode = X86::JP;  break;
142  case X86::JL:  ROpcode = X86::JGE; break;
143  case X86::JGE: ROpcode = X86::JL;  break;
144  case X86::JLE: ROpcode = X86::JG;  break;
145  case X86::JG:  ROpcode = X86::JLE; break;
146  }
147  MachineBasicBlock* MBB = MI->getParent();
148  MachineBasicBlock* TMBB = MI->getOperand(0).getMachineBasicBlock();
149  return BuildMI(*MBB, MBB->erase(MI), ROpcode, 1).addMBB(TMBB);
150}
151
152