X86InstrInfo.cpp revision d10a4ce5825d0981107c0106c49089b9e5792e40
1//===- X86InstrInfo.cpp - X86 Instruction Information -----------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the X86 implementation of the TargetInstrInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "X86InstrInfo.h" 15#include "X86.h" 16#include "X86GenInstrInfo.inc" 17#include "X86InstrBuilder.h" 18#include "X86MachineFunctionInfo.h" 19#include "X86Subtarget.h" 20#include "X86TargetMachine.h" 21#include "llvm/DerivedTypes.h" 22#include "llvm/ADT/STLExtras.h" 23#include "llvm/CodeGen/MachineConstantPool.h" 24#include "llvm/CodeGen/MachineFrameInfo.h" 25#include "llvm/CodeGen/MachineInstrBuilder.h" 26#include "llvm/CodeGen/MachineRegisterInfo.h" 27#include "llvm/CodeGen/LiveVariables.h" 28#include "llvm/Support/CommandLine.h" 29#include "llvm/Target/TargetOptions.h" 30#include "llvm/Target/TargetAsmInfo.h" 31 32using namespace llvm; 33 34namespace { 35 cl::opt<bool> 36 NoFusing("disable-spill-fusing", 37 cl::desc("Disable fusing of spill code into instructions")); 38 cl::opt<bool> 39 PrintFailedFusing("print-failed-fuse-candidates", 40 cl::desc("Print instructions that the allocator wants to" 41 " fuse, but the X86 backend currently can't"), 42 cl::Hidden); 43 cl::opt<bool> 44 ReMatPICStubLoad("remat-pic-stub-load", 45 cl::desc("Re-materialize load from stub in PIC mode"), 46 cl::init(false), cl::Hidden); 47} 48 49X86InstrInfo::X86InstrInfo(X86TargetMachine &tm) 50 : TargetInstrInfoImpl(X86Insts, array_lengthof(X86Insts)), 51 TM(tm), RI(tm, *this) { 52 SmallVector<unsigned,16> AmbEntries; 53 static const unsigned OpTbl2Addr[][2] = { 54 { X86::ADC32ri, X86::ADC32mi }, 55 { X86::ADC32ri8, X86::ADC32mi8 }, 56 { X86::ADC32rr, X86::ADC32mr }, 57 { X86::ADC64ri32, X86::ADC64mi32 }, 58 { X86::ADC64ri8, X86::ADC64mi8 }, 59 { X86::ADC64rr, X86::ADC64mr }, 60 { X86::ADD16ri, X86::ADD16mi }, 61 { X86::ADD16ri8, X86::ADD16mi8 }, 62 { X86::ADD16rr, X86::ADD16mr }, 63 { X86::ADD32ri, X86::ADD32mi }, 64 { X86::ADD32ri8, X86::ADD32mi8 }, 65 { X86::ADD32rr, X86::ADD32mr }, 66 { X86::ADD64ri32, X86::ADD64mi32 }, 67 { X86::ADD64ri8, X86::ADD64mi8 }, 68 { X86::ADD64rr, X86::ADD64mr }, 69 { X86::ADD8ri, X86::ADD8mi }, 70 { X86::ADD8rr, X86::ADD8mr }, 71 { X86::AND16ri, X86::AND16mi }, 72 { X86::AND16ri8, X86::AND16mi8 }, 73 { X86::AND16rr, X86::AND16mr }, 74 { X86::AND32ri, X86::AND32mi }, 75 { X86::AND32ri8, X86::AND32mi8 }, 76 { X86::AND32rr, X86::AND32mr }, 77 { X86::AND64ri32, X86::AND64mi32 }, 78 { X86::AND64ri8, X86::AND64mi8 }, 79 { X86::AND64rr, X86::AND64mr }, 80 { X86::AND8ri, X86::AND8mi }, 81 { X86::AND8rr, X86::AND8mr }, 82 { X86::DEC16r, X86::DEC16m }, 83 { X86::DEC32r, X86::DEC32m }, 84 { X86::DEC64_16r, X86::DEC64_16m }, 85 { X86::DEC64_32r, X86::DEC64_32m }, 86 { X86::DEC64r, X86::DEC64m }, 87 { X86::DEC8r, X86::DEC8m }, 88 { X86::INC16r, X86::INC16m }, 89 { X86::INC32r, X86::INC32m }, 90 { X86::INC64_16r, X86::INC64_16m }, 91 { X86::INC64_32r, X86::INC64_32m }, 92 { X86::INC64r, X86::INC64m }, 93 { X86::INC8r, X86::INC8m }, 94 { X86::NEG16r, X86::NEG16m }, 95 { X86::NEG32r, X86::NEG32m }, 96 { X86::NEG64r, X86::NEG64m }, 97 { X86::NEG8r, X86::NEG8m }, 98 { X86::NOT16r, X86::NOT16m }, 99 { X86::NOT32r, X86::NOT32m }, 100 { X86::NOT64r, X86::NOT64m }, 101 { X86::NOT8r, X86::NOT8m }, 102 { X86::OR16ri, X86::OR16mi }, 103 { X86::OR16ri8, X86::OR16mi8 }, 104 { X86::OR16rr, X86::OR16mr }, 105 { X86::OR32ri, X86::OR32mi }, 106 { X86::OR32ri8, X86::OR32mi8 }, 107 { X86::OR32rr, X86::OR32mr }, 108 { X86::OR64ri32, X86::OR64mi32 }, 109 { X86::OR64ri8, X86::OR64mi8 }, 110 { X86::OR64rr, X86::OR64mr }, 111 { X86::OR8ri, X86::OR8mi }, 112 { X86::OR8rr, X86::OR8mr }, 113 { X86::ROL16r1, X86::ROL16m1 }, 114 { X86::ROL16rCL, X86::ROL16mCL }, 115 { X86::ROL16ri, X86::ROL16mi }, 116 { X86::ROL32r1, X86::ROL32m1 }, 117 { X86::ROL32rCL, X86::ROL32mCL }, 118 { X86::ROL32ri, X86::ROL32mi }, 119 { X86::ROL64r1, X86::ROL64m1 }, 120 { X86::ROL64rCL, X86::ROL64mCL }, 121 { X86::ROL64ri, X86::ROL64mi }, 122 { X86::ROL8r1, X86::ROL8m1 }, 123 { X86::ROL8rCL, X86::ROL8mCL }, 124 { X86::ROL8ri, X86::ROL8mi }, 125 { X86::ROR16r1, X86::ROR16m1 }, 126 { X86::ROR16rCL, X86::ROR16mCL }, 127 { X86::ROR16ri, X86::ROR16mi }, 128 { X86::ROR32r1, X86::ROR32m1 }, 129 { X86::ROR32rCL, X86::ROR32mCL }, 130 { X86::ROR32ri, X86::ROR32mi }, 131 { X86::ROR64r1, X86::ROR64m1 }, 132 { X86::ROR64rCL, X86::ROR64mCL }, 133 { X86::ROR64ri, X86::ROR64mi }, 134 { X86::ROR8r1, X86::ROR8m1 }, 135 { X86::ROR8rCL, X86::ROR8mCL }, 136 { X86::ROR8ri, X86::ROR8mi }, 137 { X86::SAR16r1, X86::SAR16m1 }, 138 { X86::SAR16rCL, X86::SAR16mCL }, 139 { X86::SAR16ri, X86::SAR16mi }, 140 { X86::SAR32r1, X86::SAR32m1 }, 141 { X86::SAR32rCL, X86::SAR32mCL }, 142 { X86::SAR32ri, X86::SAR32mi }, 143 { X86::SAR64r1, X86::SAR64m1 }, 144 { X86::SAR64rCL, X86::SAR64mCL }, 145 { X86::SAR64ri, X86::SAR64mi }, 146 { X86::SAR8r1, X86::SAR8m1 }, 147 { X86::SAR8rCL, X86::SAR8mCL }, 148 { X86::SAR8ri, X86::SAR8mi }, 149 { X86::SBB32ri, X86::SBB32mi }, 150 { X86::SBB32ri8, X86::SBB32mi8 }, 151 { X86::SBB32rr, X86::SBB32mr }, 152 { X86::SBB64ri32, X86::SBB64mi32 }, 153 { X86::SBB64ri8, X86::SBB64mi8 }, 154 { X86::SBB64rr, X86::SBB64mr }, 155 { X86::SHL16rCL, X86::SHL16mCL }, 156 { X86::SHL16ri, X86::SHL16mi }, 157 { X86::SHL32rCL, X86::SHL32mCL }, 158 { X86::SHL32ri, X86::SHL32mi }, 159 { X86::SHL64rCL, X86::SHL64mCL }, 160 { X86::SHL64ri, X86::SHL64mi }, 161 { X86::SHL8rCL, X86::SHL8mCL }, 162 { X86::SHL8ri, X86::SHL8mi }, 163 { X86::SHLD16rrCL, X86::SHLD16mrCL }, 164 { X86::SHLD16rri8, X86::SHLD16mri8 }, 165 { X86::SHLD32rrCL, X86::SHLD32mrCL }, 166 { X86::SHLD32rri8, X86::SHLD32mri8 }, 167 { X86::SHLD64rrCL, X86::SHLD64mrCL }, 168 { X86::SHLD64rri8, X86::SHLD64mri8 }, 169 { X86::SHR16r1, X86::SHR16m1 }, 170 { X86::SHR16rCL, X86::SHR16mCL }, 171 { X86::SHR16ri, X86::SHR16mi }, 172 { X86::SHR32r1, X86::SHR32m1 }, 173 { X86::SHR32rCL, X86::SHR32mCL }, 174 { X86::SHR32ri, X86::SHR32mi }, 175 { X86::SHR64r1, X86::SHR64m1 }, 176 { X86::SHR64rCL, X86::SHR64mCL }, 177 { X86::SHR64ri, X86::SHR64mi }, 178 { X86::SHR8r1, X86::SHR8m1 }, 179 { X86::SHR8rCL, X86::SHR8mCL }, 180 { X86::SHR8ri, X86::SHR8mi }, 181 { X86::SHRD16rrCL, X86::SHRD16mrCL }, 182 { X86::SHRD16rri8, X86::SHRD16mri8 }, 183 { X86::SHRD32rrCL, X86::SHRD32mrCL }, 184 { X86::SHRD32rri8, X86::SHRD32mri8 }, 185 { X86::SHRD64rrCL, X86::SHRD64mrCL }, 186 { X86::SHRD64rri8, X86::SHRD64mri8 }, 187 { X86::SUB16ri, X86::SUB16mi }, 188 { X86::SUB16ri8, X86::SUB16mi8 }, 189 { X86::SUB16rr, X86::SUB16mr }, 190 { X86::SUB32ri, X86::SUB32mi }, 191 { X86::SUB32ri8, X86::SUB32mi8 }, 192 { X86::SUB32rr, X86::SUB32mr }, 193 { X86::SUB64ri32, X86::SUB64mi32 }, 194 { X86::SUB64ri8, X86::SUB64mi8 }, 195 { X86::SUB64rr, X86::SUB64mr }, 196 { X86::SUB8ri, X86::SUB8mi }, 197 { X86::SUB8rr, X86::SUB8mr }, 198 { X86::XOR16ri, X86::XOR16mi }, 199 { X86::XOR16ri8, X86::XOR16mi8 }, 200 { X86::XOR16rr, X86::XOR16mr }, 201 { X86::XOR32ri, X86::XOR32mi }, 202 { X86::XOR32ri8, X86::XOR32mi8 }, 203 { X86::XOR32rr, X86::XOR32mr }, 204 { X86::XOR64ri32, X86::XOR64mi32 }, 205 { X86::XOR64ri8, X86::XOR64mi8 }, 206 { X86::XOR64rr, X86::XOR64mr }, 207 { X86::XOR8ri, X86::XOR8mi }, 208 { X86::XOR8rr, X86::XOR8mr } 209 }; 210 211 for (unsigned i = 0, e = array_lengthof(OpTbl2Addr); i != e; ++i) { 212 unsigned RegOp = OpTbl2Addr[i][0]; 213 unsigned MemOp = OpTbl2Addr[i][1]; 214 if (!RegOp2MemOpTable2Addr.insert(std::make_pair((unsigned*)RegOp, 215 MemOp)).second) 216 assert(false && "Duplicated entries?"); 217 unsigned AuxInfo = 0 | (1 << 4) | (1 << 5); // Index 0,folded load and store 218 if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp, 219 std::make_pair(RegOp, 220 AuxInfo))).second) 221 AmbEntries.push_back(MemOp); 222 } 223 224 // If the third value is 1, then it's folding either a load or a store. 225 static const unsigned OpTbl0[][3] = { 226 { X86::BT16ri8, X86::BT16mi8, 1 }, 227 { X86::BT32ri8, X86::BT32mi8, 1 }, 228 { X86::BT64ri8, X86::BT64mi8, 1 }, 229 { X86::CALL32r, X86::CALL32m, 1 }, 230 { X86::CALL64r, X86::CALL64m, 1 }, 231 { X86::CMP16ri, X86::CMP16mi, 1 }, 232 { X86::CMP16ri8, X86::CMP16mi8, 1 }, 233 { X86::CMP16rr, X86::CMP16mr, 1 }, 234 { X86::CMP32ri, X86::CMP32mi, 1 }, 235 { X86::CMP32ri8, X86::CMP32mi8, 1 }, 236 { X86::CMP32rr, X86::CMP32mr, 1 }, 237 { X86::CMP64ri32, X86::CMP64mi32, 1 }, 238 { X86::CMP64ri8, X86::CMP64mi8, 1 }, 239 { X86::CMP64rr, X86::CMP64mr, 1 }, 240 { X86::CMP8ri, X86::CMP8mi, 1 }, 241 { X86::CMP8rr, X86::CMP8mr, 1 }, 242 { X86::DIV16r, X86::DIV16m, 1 }, 243 { X86::DIV32r, X86::DIV32m, 1 }, 244 { X86::DIV64r, X86::DIV64m, 1 }, 245 { X86::DIV8r, X86::DIV8m, 1 }, 246 { X86::EXTRACTPSrr, X86::EXTRACTPSmr, 0 }, 247 { X86::FsMOVAPDrr, X86::MOVSDmr, 0 }, 248 { X86::FsMOVAPSrr, X86::MOVSSmr, 0 }, 249 { X86::IDIV16r, X86::IDIV16m, 1 }, 250 { X86::IDIV32r, X86::IDIV32m, 1 }, 251 { X86::IDIV64r, X86::IDIV64m, 1 }, 252 { X86::IDIV8r, X86::IDIV8m, 1 }, 253 { X86::IMUL16r, X86::IMUL16m, 1 }, 254 { X86::IMUL32r, X86::IMUL32m, 1 }, 255 { X86::IMUL64r, X86::IMUL64m, 1 }, 256 { X86::IMUL8r, X86::IMUL8m, 1 }, 257 { X86::JMP32r, X86::JMP32m, 1 }, 258 { X86::JMP64r, X86::JMP64m, 1 }, 259 { X86::MOV16ri, X86::MOV16mi, 0 }, 260 { X86::MOV16rr, X86::MOV16mr, 0 }, 261 { X86::MOV32ri, X86::MOV32mi, 0 }, 262 { X86::MOV32rr, X86::MOV32mr, 0 }, 263 { X86::MOV64ri32, X86::MOV64mi32, 0 }, 264 { X86::MOV64rr, X86::MOV64mr, 0 }, 265 { X86::MOV8ri, X86::MOV8mi, 0 }, 266 { X86::MOV8rr, X86::MOV8mr, 0 }, 267 { X86::MOV8rr_NOREX, X86::MOV8mr_NOREX, 0 }, 268 { X86::MOVAPDrr, X86::MOVAPDmr, 0 }, 269 { X86::MOVAPSrr, X86::MOVAPSmr, 0 }, 270 { X86::MOVDQArr, X86::MOVDQAmr, 0 }, 271 { X86::MOVPDI2DIrr, X86::MOVPDI2DImr, 0 }, 272 { X86::MOVPQIto64rr,X86::MOVPQI2QImr, 0 }, 273 { X86::MOVPS2SSrr, X86::MOVPS2SSmr, 0 }, 274 { X86::MOVSDrr, X86::MOVSDmr, 0 }, 275 { X86::MOVSDto64rr, X86::MOVSDto64mr, 0 }, 276 { X86::MOVSS2DIrr, X86::MOVSS2DImr, 0 }, 277 { X86::MOVSSrr, X86::MOVSSmr, 0 }, 278 { X86::MOVUPDrr, X86::MOVUPDmr, 0 }, 279 { X86::MOVUPSrr, X86::MOVUPSmr, 0 }, 280 { X86::MUL16r, X86::MUL16m, 1 }, 281 { X86::MUL32r, X86::MUL32m, 1 }, 282 { X86::MUL64r, X86::MUL64m, 1 }, 283 { X86::MUL8r, X86::MUL8m, 1 }, 284 { X86::SETAEr, X86::SETAEm, 0 }, 285 { X86::SETAr, X86::SETAm, 0 }, 286 { X86::SETBEr, X86::SETBEm, 0 }, 287 { X86::SETBr, X86::SETBm, 0 }, 288 { X86::SETEr, X86::SETEm, 0 }, 289 { X86::SETGEr, X86::SETGEm, 0 }, 290 { X86::SETGr, X86::SETGm, 0 }, 291 { X86::SETLEr, X86::SETLEm, 0 }, 292 { X86::SETLr, X86::SETLm, 0 }, 293 { X86::SETNEr, X86::SETNEm, 0 }, 294 { X86::SETNOr, X86::SETNOm, 0 }, 295 { X86::SETNPr, X86::SETNPm, 0 }, 296 { X86::SETNSr, X86::SETNSm, 0 }, 297 { X86::SETOr, X86::SETOm, 0 }, 298 { X86::SETPr, X86::SETPm, 0 }, 299 { X86::SETSr, X86::SETSm, 0 }, 300 { X86::TAILJMPr, X86::TAILJMPm, 1 }, 301 { X86::TEST16ri, X86::TEST16mi, 1 }, 302 { X86::TEST32ri, X86::TEST32mi, 1 }, 303 { X86::TEST64ri32, X86::TEST64mi32, 1 }, 304 { X86::TEST8ri, X86::TEST8mi, 1 } 305 }; 306 307 for (unsigned i = 0, e = array_lengthof(OpTbl0); i != e; ++i) { 308 unsigned RegOp = OpTbl0[i][0]; 309 unsigned MemOp = OpTbl0[i][1]; 310 if (!RegOp2MemOpTable0.insert(std::make_pair((unsigned*)RegOp, 311 MemOp)).second) 312 assert(false && "Duplicated entries?"); 313 unsigned FoldedLoad = OpTbl0[i][2]; 314 // Index 0, folded load or store. 315 unsigned AuxInfo = 0 | (FoldedLoad << 4) | ((FoldedLoad^1) << 5); 316 if (RegOp != X86::FsMOVAPDrr && RegOp != X86::FsMOVAPSrr) 317 if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp, 318 std::make_pair(RegOp, AuxInfo))).second) 319 AmbEntries.push_back(MemOp); 320 } 321 322 static const unsigned OpTbl1[][2] = { 323 { X86::CMP16rr, X86::CMP16rm }, 324 { X86::CMP32rr, X86::CMP32rm }, 325 { X86::CMP64rr, X86::CMP64rm }, 326 { X86::CMP8rr, X86::CMP8rm }, 327 { X86::CVTSD2SSrr, X86::CVTSD2SSrm }, 328 { X86::CVTSI2SD64rr, X86::CVTSI2SD64rm }, 329 { X86::CVTSI2SDrr, X86::CVTSI2SDrm }, 330 { X86::CVTSI2SS64rr, X86::CVTSI2SS64rm }, 331 { X86::CVTSI2SSrr, X86::CVTSI2SSrm }, 332 { X86::CVTSS2SDrr, X86::CVTSS2SDrm }, 333 { X86::CVTTSD2SI64rr, X86::CVTTSD2SI64rm }, 334 { X86::CVTTSD2SIrr, X86::CVTTSD2SIrm }, 335 { X86::CVTTSS2SI64rr, X86::CVTTSS2SI64rm }, 336 { X86::CVTTSS2SIrr, X86::CVTTSS2SIrm }, 337 { X86::FsMOVAPDrr, X86::MOVSDrm }, 338 { X86::FsMOVAPSrr, X86::MOVSSrm }, 339 { X86::IMUL16rri, X86::IMUL16rmi }, 340 { X86::IMUL16rri8, X86::IMUL16rmi8 }, 341 { X86::IMUL32rri, X86::IMUL32rmi }, 342 { X86::IMUL32rri8, X86::IMUL32rmi8 }, 343 { X86::IMUL64rri32, X86::IMUL64rmi32 }, 344 { X86::IMUL64rri8, X86::IMUL64rmi8 }, 345 { X86::Int_CMPSDrr, X86::Int_CMPSDrm }, 346 { X86::Int_CMPSSrr, X86::Int_CMPSSrm }, 347 { X86::Int_COMISDrr, X86::Int_COMISDrm }, 348 { X86::Int_COMISSrr, X86::Int_COMISSrm }, 349 { X86::Int_CVTDQ2PDrr, X86::Int_CVTDQ2PDrm }, 350 { X86::Int_CVTDQ2PSrr, X86::Int_CVTDQ2PSrm }, 351 { X86::Int_CVTPD2DQrr, X86::Int_CVTPD2DQrm }, 352 { X86::Int_CVTPD2PSrr, X86::Int_CVTPD2PSrm }, 353 { X86::Int_CVTPS2DQrr, X86::Int_CVTPS2DQrm }, 354 { X86::Int_CVTPS2PDrr, X86::Int_CVTPS2PDrm }, 355 { X86::Int_CVTSD2SI64rr,X86::Int_CVTSD2SI64rm }, 356 { X86::Int_CVTSD2SIrr, X86::Int_CVTSD2SIrm }, 357 { X86::Int_CVTSD2SSrr, X86::Int_CVTSD2SSrm }, 358 { X86::Int_CVTSI2SD64rr,X86::Int_CVTSI2SD64rm }, 359 { X86::Int_CVTSI2SDrr, X86::Int_CVTSI2SDrm }, 360 { X86::Int_CVTSI2SS64rr,X86::Int_CVTSI2SS64rm }, 361 { X86::Int_CVTSI2SSrr, X86::Int_CVTSI2SSrm }, 362 { X86::Int_CVTSS2SDrr, X86::Int_CVTSS2SDrm }, 363 { X86::Int_CVTSS2SI64rr,X86::Int_CVTSS2SI64rm }, 364 { X86::Int_CVTSS2SIrr, X86::Int_CVTSS2SIrm }, 365 { X86::Int_CVTTPD2DQrr, X86::Int_CVTTPD2DQrm }, 366 { X86::Int_CVTTPS2DQrr, X86::Int_CVTTPS2DQrm }, 367 { X86::Int_CVTTSD2SI64rr,X86::Int_CVTTSD2SI64rm }, 368 { X86::Int_CVTTSD2SIrr, X86::Int_CVTTSD2SIrm }, 369 { X86::Int_CVTTSS2SI64rr,X86::Int_CVTTSS2SI64rm }, 370 { X86::Int_CVTTSS2SIrr, X86::Int_CVTTSS2SIrm }, 371 { X86::Int_UCOMISDrr, X86::Int_UCOMISDrm }, 372 { X86::Int_UCOMISSrr, X86::Int_UCOMISSrm }, 373 { X86::MOV16rr, X86::MOV16rm }, 374 { X86::MOV32rr, X86::MOV32rm }, 375 { X86::MOV64rr, X86::MOV64rm }, 376 { X86::MOV64toPQIrr, X86::MOVQI2PQIrm }, 377 { X86::MOV64toSDrr, X86::MOV64toSDrm }, 378 { X86::MOV8rr, X86::MOV8rm }, 379 { X86::MOVAPDrr, X86::MOVAPDrm }, 380 { X86::MOVAPSrr, X86::MOVAPSrm }, 381 { X86::MOVDDUPrr, X86::MOVDDUPrm }, 382 { X86::MOVDI2PDIrr, X86::MOVDI2PDIrm }, 383 { X86::MOVDI2SSrr, X86::MOVDI2SSrm }, 384 { X86::MOVDQArr, X86::MOVDQArm }, 385 { X86::MOVSD2PDrr, X86::MOVSD2PDrm }, 386 { X86::MOVSDrr, X86::MOVSDrm }, 387 { X86::MOVSHDUPrr, X86::MOVSHDUPrm }, 388 { X86::MOVSLDUPrr, X86::MOVSLDUPrm }, 389 { X86::MOVSS2PSrr, X86::MOVSS2PSrm }, 390 { X86::MOVSSrr, X86::MOVSSrm }, 391 { X86::MOVSX16rr8, X86::MOVSX16rm8 }, 392 { X86::MOVSX32rr16, X86::MOVSX32rm16 }, 393 { X86::MOVSX32rr8, X86::MOVSX32rm8 }, 394 { X86::MOVSX64rr16, X86::MOVSX64rm16 }, 395 { X86::MOVSX64rr32, X86::MOVSX64rm32 }, 396 { X86::MOVSX64rr8, X86::MOVSX64rm8 }, 397 { X86::MOVUPDrr, X86::MOVUPDrm }, 398 { X86::MOVUPSrr, X86::MOVUPSrm }, 399 { X86::MOVZDI2PDIrr, X86::MOVZDI2PDIrm }, 400 { X86::MOVZQI2PQIrr, X86::MOVZQI2PQIrm }, 401 { X86::MOVZPQILo2PQIrr, X86::MOVZPQILo2PQIrm }, 402 { X86::MOVZX16rr8, X86::MOVZX16rm8 }, 403 { X86::MOVZX32rr16, X86::MOVZX32rm16 }, 404 { X86::MOVZX32_NOREXrr8, X86::MOVZX32_NOREXrm8 }, 405 { X86::MOVZX32rr8, X86::MOVZX32rm8 }, 406 { X86::MOVZX64rr16, X86::MOVZX64rm16 }, 407 { X86::MOVZX64rr32, X86::MOVZX64rm32 }, 408 { X86::MOVZX64rr8, X86::MOVZX64rm8 }, 409 { X86::PSHUFDri, X86::PSHUFDmi }, 410 { X86::PSHUFHWri, X86::PSHUFHWmi }, 411 { X86::PSHUFLWri, X86::PSHUFLWmi }, 412 { X86::RCPPSr, X86::RCPPSm }, 413 { X86::RCPPSr_Int, X86::RCPPSm_Int }, 414 { X86::RSQRTPSr, X86::RSQRTPSm }, 415 { X86::RSQRTPSr_Int, X86::RSQRTPSm_Int }, 416 { X86::RSQRTSSr, X86::RSQRTSSm }, 417 { X86::RSQRTSSr_Int, X86::RSQRTSSm_Int }, 418 { X86::SQRTPDr, X86::SQRTPDm }, 419 { X86::SQRTPDr_Int, X86::SQRTPDm_Int }, 420 { X86::SQRTPSr, X86::SQRTPSm }, 421 { X86::SQRTPSr_Int, X86::SQRTPSm_Int }, 422 { X86::SQRTSDr, X86::SQRTSDm }, 423 { X86::SQRTSDr_Int, X86::SQRTSDm_Int }, 424 { X86::SQRTSSr, X86::SQRTSSm }, 425 { X86::SQRTSSr_Int, X86::SQRTSSm_Int }, 426 { X86::TEST16rr, X86::TEST16rm }, 427 { X86::TEST32rr, X86::TEST32rm }, 428 { X86::TEST64rr, X86::TEST64rm }, 429 { X86::TEST8rr, X86::TEST8rm }, 430 // FIXME: TEST*rr EAX,EAX ---> CMP [mem], 0 431 { X86::UCOMISDrr, X86::UCOMISDrm }, 432 { X86::UCOMISSrr, X86::UCOMISSrm } 433 }; 434 435 for (unsigned i = 0, e = array_lengthof(OpTbl1); i != e; ++i) { 436 unsigned RegOp = OpTbl1[i][0]; 437 unsigned MemOp = OpTbl1[i][1]; 438 if (!RegOp2MemOpTable1.insert(std::make_pair((unsigned*)RegOp, 439 MemOp)).second) 440 assert(false && "Duplicated entries?"); 441 unsigned AuxInfo = 1 | (1 << 4); // Index 1, folded load 442 if (RegOp != X86::FsMOVAPDrr && RegOp != X86::FsMOVAPSrr) 443 if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp, 444 std::make_pair(RegOp, AuxInfo))).second) 445 AmbEntries.push_back(MemOp); 446 } 447 448 static const unsigned OpTbl2[][2] = { 449 { X86::ADC32rr, X86::ADC32rm }, 450 { X86::ADC64rr, X86::ADC64rm }, 451 { X86::ADD16rr, X86::ADD16rm }, 452 { X86::ADD32rr, X86::ADD32rm }, 453 { X86::ADD64rr, X86::ADD64rm }, 454 { X86::ADD8rr, X86::ADD8rm }, 455 { X86::ADDPDrr, X86::ADDPDrm }, 456 { X86::ADDPSrr, X86::ADDPSrm }, 457 { X86::ADDSDrr, X86::ADDSDrm }, 458 { X86::ADDSSrr, X86::ADDSSrm }, 459 { X86::ADDSUBPDrr, X86::ADDSUBPDrm }, 460 { X86::ADDSUBPSrr, X86::ADDSUBPSrm }, 461 { X86::AND16rr, X86::AND16rm }, 462 { X86::AND32rr, X86::AND32rm }, 463 { X86::AND64rr, X86::AND64rm }, 464 { X86::AND8rr, X86::AND8rm }, 465 { X86::ANDNPDrr, X86::ANDNPDrm }, 466 { X86::ANDNPSrr, X86::ANDNPSrm }, 467 { X86::ANDPDrr, X86::ANDPDrm }, 468 { X86::ANDPSrr, X86::ANDPSrm }, 469 { X86::CMOVA16rr, X86::CMOVA16rm }, 470 { X86::CMOVA32rr, X86::CMOVA32rm }, 471 { X86::CMOVA64rr, X86::CMOVA64rm }, 472 { X86::CMOVAE16rr, X86::CMOVAE16rm }, 473 { X86::CMOVAE32rr, X86::CMOVAE32rm }, 474 { X86::CMOVAE64rr, X86::CMOVAE64rm }, 475 { X86::CMOVB16rr, X86::CMOVB16rm }, 476 { X86::CMOVB32rr, X86::CMOVB32rm }, 477 { X86::CMOVB64rr, X86::CMOVB64rm }, 478 { X86::CMOVBE16rr, X86::CMOVBE16rm }, 479 { X86::CMOVBE32rr, X86::CMOVBE32rm }, 480 { X86::CMOVBE64rr, X86::CMOVBE64rm }, 481 { X86::CMOVE16rr, X86::CMOVE16rm }, 482 { X86::CMOVE32rr, X86::CMOVE32rm }, 483 { X86::CMOVE64rr, X86::CMOVE64rm }, 484 { X86::CMOVG16rr, X86::CMOVG16rm }, 485 { X86::CMOVG32rr, X86::CMOVG32rm }, 486 { X86::CMOVG64rr, X86::CMOVG64rm }, 487 { X86::CMOVGE16rr, X86::CMOVGE16rm }, 488 { X86::CMOVGE32rr, X86::CMOVGE32rm }, 489 { X86::CMOVGE64rr, X86::CMOVGE64rm }, 490 { X86::CMOVL16rr, X86::CMOVL16rm }, 491 { X86::CMOVL32rr, X86::CMOVL32rm }, 492 { X86::CMOVL64rr, X86::CMOVL64rm }, 493 { X86::CMOVLE16rr, X86::CMOVLE16rm }, 494 { X86::CMOVLE32rr, X86::CMOVLE32rm }, 495 { X86::CMOVLE64rr, X86::CMOVLE64rm }, 496 { X86::CMOVNE16rr, X86::CMOVNE16rm }, 497 { X86::CMOVNE32rr, X86::CMOVNE32rm }, 498 { X86::CMOVNE64rr, X86::CMOVNE64rm }, 499 { X86::CMOVNO16rr, X86::CMOVNO16rm }, 500 { X86::CMOVNO32rr, X86::CMOVNO32rm }, 501 { X86::CMOVNO64rr, X86::CMOVNO64rm }, 502 { X86::CMOVNP16rr, X86::CMOVNP16rm }, 503 { X86::CMOVNP32rr, X86::CMOVNP32rm }, 504 { X86::CMOVNP64rr, X86::CMOVNP64rm }, 505 { X86::CMOVNS16rr, X86::CMOVNS16rm }, 506 { X86::CMOVNS32rr, X86::CMOVNS32rm }, 507 { X86::CMOVNS64rr, X86::CMOVNS64rm }, 508 { X86::CMOVO16rr, X86::CMOVO16rm }, 509 { X86::CMOVO32rr, X86::CMOVO32rm }, 510 { X86::CMOVO64rr, X86::CMOVO64rm }, 511 { X86::CMOVP16rr, X86::CMOVP16rm }, 512 { X86::CMOVP32rr, X86::CMOVP32rm }, 513 { X86::CMOVP64rr, X86::CMOVP64rm }, 514 { X86::CMOVS16rr, X86::CMOVS16rm }, 515 { X86::CMOVS32rr, X86::CMOVS32rm }, 516 { X86::CMOVS64rr, X86::CMOVS64rm }, 517 { X86::CMPPDrri, X86::CMPPDrmi }, 518 { X86::CMPPSrri, X86::CMPPSrmi }, 519 { X86::CMPSDrr, X86::CMPSDrm }, 520 { X86::CMPSSrr, X86::CMPSSrm }, 521 { X86::DIVPDrr, X86::DIVPDrm }, 522 { X86::DIVPSrr, X86::DIVPSrm }, 523 { X86::DIVSDrr, X86::DIVSDrm }, 524 { X86::DIVSSrr, X86::DIVSSrm }, 525 { X86::FsANDNPDrr, X86::FsANDNPDrm }, 526 { X86::FsANDNPSrr, X86::FsANDNPSrm }, 527 { X86::FsANDPDrr, X86::FsANDPDrm }, 528 { X86::FsANDPSrr, X86::FsANDPSrm }, 529 { X86::FsORPDrr, X86::FsORPDrm }, 530 { X86::FsORPSrr, X86::FsORPSrm }, 531 { X86::FsXORPDrr, X86::FsXORPDrm }, 532 { X86::FsXORPSrr, X86::FsXORPSrm }, 533 { X86::HADDPDrr, X86::HADDPDrm }, 534 { X86::HADDPSrr, X86::HADDPSrm }, 535 { X86::HSUBPDrr, X86::HSUBPDrm }, 536 { X86::HSUBPSrr, X86::HSUBPSrm }, 537 { X86::IMUL16rr, X86::IMUL16rm }, 538 { X86::IMUL32rr, X86::IMUL32rm }, 539 { X86::IMUL64rr, X86::IMUL64rm }, 540 { X86::MAXPDrr, X86::MAXPDrm }, 541 { X86::MAXPDrr_Int, X86::MAXPDrm_Int }, 542 { X86::MAXPSrr, X86::MAXPSrm }, 543 { X86::MAXPSrr_Int, X86::MAXPSrm_Int }, 544 { X86::MAXSDrr, X86::MAXSDrm }, 545 { X86::MAXSDrr_Int, X86::MAXSDrm_Int }, 546 { X86::MAXSSrr, X86::MAXSSrm }, 547 { X86::MAXSSrr_Int, X86::MAXSSrm_Int }, 548 { X86::MINPDrr, X86::MINPDrm }, 549 { X86::MINPDrr_Int, X86::MINPDrm_Int }, 550 { X86::MINPSrr, X86::MINPSrm }, 551 { X86::MINPSrr_Int, X86::MINPSrm_Int }, 552 { X86::MINSDrr, X86::MINSDrm }, 553 { X86::MINSDrr_Int, X86::MINSDrm_Int }, 554 { X86::MINSSrr, X86::MINSSrm }, 555 { X86::MINSSrr_Int, X86::MINSSrm_Int }, 556 { X86::MULPDrr, X86::MULPDrm }, 557 { X86::MULPSrr, X86::MULPSrm }, 558 { X86::MULSDrr, X86::MULSDrm }, 559 { X86::MULSSrr, X86::MULSSrm }, 560 { X86::OR16rr, X86::OR16rm }, 561 { X86::OR32rr, X86::OR32rm }, 562 { X86::OR64rr, X86::OR64rm }, 563 { X86::OR8rr, X86::OR8rm }, 564 { X86::ORPDrr, X86::ORPDrm }, 565 { X86::ORPSrr, X86::ORPSrm }, 566 { X86::PACKSSDWrr, X86::PACKSSDWrm }, 567 { X86::PACKSSWBrr, X86::PACKSSWBrm }, 568 { X86::PACKUSWBrr, X86::PACKUSWBrm }, 569 { X86::PADDBrr, X86::PADDBrm }, 570 { X86::PADDDrr, X86::PADDDrm }, 571 { X86::PADDQrr, X86::PADDQrm }, 572 { X86::PADDSBrr, X86::PADDSBrm }, 573 { X86::PADDSWrr, X86::PADDSWrm }, 574 { X86::PADDWrr, X86::PADDWrm }, 575 { X86::PANDNrr, X86::PANDNrm }, 576 { X86::PANDrr, X86::PANDrm }, 577 { X86::PAVGBrr, X86::PAVGBrm }, 578 { X86::PAVGWrr, X86::PAVGWrm }, 579 { X86::PCMPEQBrr, X86::PCMPEQBrm }, 580 { X86::PCMPEQDrr, X86::PCMPEQDrm }, 581 { X86::PCMPEQWrr, X86::PCMPEQWrm }, 582 { X86::PCMPGTBrr, X86::PCMPGTBrm }, 583 { X86::PCMPGTDrr, X86::PCMPGTDrm }, 584 { X86::PCMPGTWrr, X86::PCMPGTWrm }, 585 { X86::PINSRWrri, X86::PINSRWrmi }, 586 { X86::PMADDWDrr, X86::PMADDWDrm }, 587 { X86::PMAXSWrr, X86::PMAXSWrm }, 588 { X86::PMAXUBrr, X86::PMAXUBrm }, 589 { X86::PMINSWrr, X86::PMINSWrm }, 590 { X86::PMINUBrr, X86::PMINUBrm }, 591 { X86::PMULDQrr, X86::PMULDQrm }, 592 { X86::PMULHUWrr, X86::PMULHUWrm }, 593 { X86::PMULHWrr, X86::PMULHWrm }, 594 { X86::PMULLDrr, X86::PMULLDrm }, 595 { X86::PMULLDrr_int, X86::PMULLDrm_int }, 596 { X86::PMULLWrr, X86::PMULLWrm }, 597 { X86::PMULUDQrr, X86::PMULUDQrm }, 598 { X86::PORrr, X86::PORrm }, 599 { X86::PSADBWrr, X86::PSADBWrm }, 600 { X86::PSLLDrr, X86::PSLLDrm }, 601 { X86::PSLLQrr, X86::PSLLQrm }, 602 { X86::PSLLWrr, X86::PSLLWrm }, 603 { X86::PSRADrr, X86::PSRADrm }, 604 { X86::PSRAWrr, X86::PSRAWrm }, 605 { X86::PSRLDrr, X86::PSRLDrm }, 606 { X86::PSRLQrr, X86::PSRLQrm }, 607 { X86::PSRLWrr, X86::PSRLWrm }, 608 { X86::PSUBBrr, X86::PSUBBrm }, 609 { X86::PSUBDrr, X86::PSUBDrm }, 610 { X86::PSUBSBrr, X86::PSUBSBrm }, 611 { X86::PSUBSWrr, X86::PSUBSWrm }, 612 { X86::PSUBWrr, X86::PSUBWrm }, 613 { X86::PUNPCKHBWrr, X86::PUNPCKHBWrm }, 614 { X86::PUNPCKHDQrr, X86::PUNPCKHDQrm }, 615 { X86::PUNPCKHQDQrr, X86::PUNPCKHQDQrm }, 616 { X86::PUNPCKHWDrr, X86::PUNPCKHWDrm }, 617 { X86::PUNPCKLBWrr, X86::PUNPCKLBWrm }, 618 { X86::PUNPCKLDQrr, X86::PUNPCKLDQrm }, 619 { X86::PUNPCKLQDQrr, X86::PUNPCKLQDQrm }, 620 { X86::PUNPCKLWDrr, X86::PUNPCKLWDrm }, 621 { X86::PXORrr, X86::PXORrm }, 622 { X86::SBB32rr, X86::SBB32rm }, 623 { X86::SBB64rr, X86::SBB64rm }, 624 { X86::SHUFPDrri, X86::SHUFPDrmi }, 625 { X86::SHUFPSrri, X86::SHUFPSrmi }, 626 { X86::SUB16rr, X86::SUB16rm }, 627 { X86::SUB32rr, X86::SUB32rm }, 628 { X86::SUB64rr, X86::SUB64rm }, 629 { X86::SUB8rr, X86::SUB8rm }, 630 { X86::SUBPDrr, X86::SUBPDrm }, 631 { X86::SUBPSrr, X86::SUBPSrm }, 632 { X86::SUBSDrr, X86::SUBSDrm }, 633 { X86::SUBSSrr, X86::SUBSSrm }, 634 // FIXME: TEST*rr -> swapped operand of TEST*mr. 635 { X86::UNPCKHPDrr, X86::UNPCKHPDrm }, 636 { X86::UNPCKHPSrr, X86::UNPCKHPSrm }, 637 { X86::UNPCKLPDrr, X86::UNPCKLPDrm }, 638 { X86::UNPCKLPSrr, X86::UNPCKLPSrm }, 639 { X86::XOR16rr, X86::XOR16rm }, 640 { X86::XOR32rr, X86::XOR32rm }, 641 { X86::XOR64rr, X86::XOR64rm }, 642 { X86::XOR8rr, X86::XOR8rm }, 643 { X86::XORPDrr, X86::XORPDrm }, 644 { X86::XORPSrr, X86::XORPSrm } 645 }; 646 647 for (unsigned i = 0, e = array_lengthof(OpTbl2); i != e; ++i) { 648 unsigned RegOp = OpTbl2[i][0]; 649 unsigned MemOp = OpTbl2[i][1]; 650 if (!RegOp2MemOpTable2.insert(std::make_pair((unsigned*)RegOp, 651 MemOp)).second) 652 assert(false && "Duplicated entries?"); 653 unsigned AuxInfo = 2 | (1 << 4); // Index 2, folded load 654 if (!MemOp2RegOpTable.insert(std::make_pair((unsigned*)MemOp, 655 std::make_pair(RegOp, AuxInfo))).second) 656 AmbEntries.push_back(MemOp); 657 } 658 659 // Remove ambiguous entries. 660 assert(AmbEntries.empty() && "Duplicated entries in unfolding maps?"); 661} 662 663bool X86InstrInfo::isMoveInstr(const MachineInstr& MI, 664 unsigned &SrcReg, unsigned &DstReg, 665 unsigned &SrcSubIdx, unsigned &DstSubIdx) const { 666 switch (MI.getOpcode()) { 667 default: 668 return false; 669 case X86::MOV8rr: 670 case X86::MOV8rr_NOREX: 671 case X86::MOV16rr: 672 case X86::MOV32rr: 673 case X86::MOV64rr: 674 case X86::MOVSSrr: 675 case X86::MOVSDrr: 676 677 // FP Stack register class copies 678 case X86::MOV_Fp3232: case X86::MOV_Fp6464: case X86::MOV_Fp8080: 679 case X86::MOV_Fp3264: case X86::MOV_Fp3280: 680 case X86::MOV_Fp6432: case X86::MOV_Fp8032: 681 682 case X86::FsMOVAPSrr: 683 case X86::FsMOVAPDrr: 684 case X86::MOVAPSrr: 685 case X86::MOVAPDrr: 686 case X86::MOVDQArr: 687 case X86::MOVSS2PSrr: 688 case X86::MOVSD2PDrr: 689 case X86::MOVPS2SSrr: 690 case X86::MOVPD2SDrr: 691 case X86::MMX_MOVQ64rr: 692 assert(MI.getNumOperands() >= 2 && 693 MI.getOperand(0).isReg() && 694 MI.getOperand(1).isReg() && 695 "invalid register-register move instruction"); 696 SrcReg = MI.getOperand(1).getReg(); 697 DstReg = MI.getOperand(0).getReg(); 698 SrcSubIdx = MI.getOperand(1).getSubReg(); 699 DstSubIdx = MI.getOperand(0).getSubReg(); 700 return true; 701 } 702} 703 704unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr *MI, 705 int &FrameIndex) const { 706 switch (MI->getOpcode()) { 707 default: break; 708 case X86::MOV8rm: 709 case X86::MOV16rm: 710 case X86::MOV32rm: 711 case X86::MOV64rm: 712 case X86::LD_Fp64m: 713 case X86::MOVSSrm: 714 case X86::MOVSDrm: 715 case X86::MOVAPSrm: 716 case X86::MOVAPDrm: 717 case X86::MOVDQArm: 718 case X86::MMX_MOVD64rm: 719 case X86::MMX_MOVQ64rm: 720 if (MI->getOperand(1).isFI() && MI->getOperand(2).isImm() && 721 MI->getOperand(3).isReg() && MI->getOperand(4).isImm() && 722 MI->getOperand(2).getImm() == 1 && 723 MI->getOperand(3).getReg() == 0 && 724 MI->getOperand(4).getImm() == 0) { 725 FrameIndex = MI->getOperand(1).getIndex(); 726 return MI->getOperand(0).getReg(); 727 } 728 break; 729 } 730 return 0; 731} 732 733unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr *MI, 734 int &FrameIndex) const { 735 switch (MI->getOpcode()) { 736 default: break; 737 case X86::MOV8mr: 738 case X86::MOV16mr: 739 case X86::MOV32mr: 740 case X86::MOV64mr: 741 case X86::ST_FpP64m: 742 case X86::MOVSSmr: 743 case X86::MOVSDmr: 744 case X86::MOVAPSmr: 745 case X86::MOVAPDmr: 746 case X86::MOVDQAmr: 747 case X86::MMX_MOVD64mr: 748 case X86::MMX_MOVQ64mr: 749 case X86::MMX_MOVNTQmr: 750 if (MI->getOperand(0).isFI() && MI->getOperand(1).isImm() && 751 MI->getOperand(2).isReg() && MI->getOperand(3).isImm() && 752 MI->getOperand(1).getImm() == 1 && 753 MI->getOperand(2).getReg() == 0 && 754 MI->getOperand(3).getImm() == 0) { 755 FrameIndex = MI->getOperand(0).getIndex(); 756 return MI->getOperand(X86AddrNumOperands).getReg(); 757 } 758 break; 759 } 760 return 0; 761} 762 763 764/// regIsPICBase - Return true if register is PIC base (i.e.g defined by 765/// X86::MOVPC32r. 766static bool regIsPICBase(unsigned BaseReg, const MachineRegisterInfo &MRI) { 767 bool isPICBase = false; 768 for (MachineRegisterInfo::def_iterator I = MRI.def_begin(BaseReg), 769 E = MRI.def_end(); I != E; ++I) { 770 MachineInstr *DefMI = I.getOperand().getParent(); 771 if (DefMI->getOpcode() != X86::MOVPC32r) 772 return false; 773 assert(!isPICBase && "More than one PIC base?"); 774 isPICBase = true; 775 } 776 return isPICBase; 777} 778 779/// isGVStub - Return true if the GV requires an extra load to get the 780/// real address. 781static inline bool isGVStub(GlobalValue *GV, X86TargetMachine &TM) { 782 return TM.getSubtarget<X86Subtarget>().GVRequiresExtraLoad(GV, TM, false); 783} 784 785bool 786X86InstrInfo::isReallyTriviallyReMaterializable(const MachineInstr *MI) const { 787 switch (MI->getOpcode()) { 788 default: break; 789 case X86::MOV8rm: 790 case X86::MOV16rm: 791 case X86::MOV32rm: 792 case X86::MOV64rm: 793 case X86::LD_Fp64m: 794 case X86::MOVSSrm: 795 case X86::MOVSDrm: 796 case X86::MOVAPSrm: 797 case X86::MOVAPDrm: 798 case X86::MOVDQArm: 799 case X86::MMX_MOVD64rm: 800 case X86::MMX_MOVQ64rm: { 801 // Loads from constant pools are trivially rematerializable. 802 if (MI->getOperand(1).isReg() && 803 MI->getOperand(2).isImm() && 804 MI->getOperand(3).isReg() && MI->getOperand(3).getReg() == 0 && 805 (MI->getOperand(4).isCPI() || 806 (MI->getOperand(4).isGlobal() && 807 isGVStub(MI->getOperand(4).getGlobal(), TM)))) { 808 unsigned BaseReg = MI->getOperand(1).getReg(); 809 if (BaseReg == 0) 810 return true; 811 // Allow re-materialization of PIC load. 812 if (!ReMatPICStubLoad && MI->getOperand(4).isGlobal()) 813 return false; 814 const MachineFunction &MF = *MI->getParent()->getParent(); 815 const MachineRegisterInfo &MRI = MF.getRegInfo(); 816 bool isPICBase = false; 817 for (MachineRegisterInfo::def_iterator I = MRI.def_begin(BaseReg), 818 E = MRI.def_end(); I != E; ++I) { 819 MachineInstr *DefMI = I.getOperand().getParent(); 820 if (DefMI->getOpcode() != X86::MOVPC32r) 821 return false; 822 assert(!isPICBase && "More than one PIC base?"); 823 isPICBase = true; 824 } 825 return isPICBase; 826 } 827 return false; 828 } 829 830 case X86::LEA32r: 831 case X86::LEA64r: { 832 if (MI->getOperand(2).isImm() && 833 MI->getOperand(3).isReg() && MI->getOperand(3).getReg() == 0 && 834 !MI->getOperand(4).isReg()) { 835 // lea fi#, lea GV, etc. are all rematerializable. 836 if (!MI->getOperand(1).isReg()) 837 return true; 838 unsigned BaseReg = MI->getOperand(1).getReg(); 839 if (BaseReg == 0) 840 return true; 841 // Allow re-materialization of lea PICBase + x. 842 const MachineFunction &MF = *MI->getParent()->getParent(); 843 const MachineRegisterInfo &MRI = MF.getRegInfo(); 844 return regIsPICBase(BaseReg, MRI); 845 } 846 return false; 847 } 848 } 849 850 // All other instructions marked M_REMATERIALIZABLE are always trivially 851 // rematerializable. 852 return true; 853} 854 855/// isSafeToClobberEFLAGS - Return true if it's safe insert an instruction that 856/// would clobber the EFLAGS condition register. Note the result may be 857/// conservative. If it cannot definitely determine the safety after visiting 858/// two instructions it assumes it's not safe. 859static bool isSafeToClobberEFLAGS(MachineBasicBlock &MBB, 860 MachineBasicBlock::iterator I) { 861 // It's always safe to clobber EFLAGS at the end of a block. 862 if (I == MBB.end()) 863 return true; 864 865 // For compile time consideration, if we are not able to determine the 866 // safety after visiting 2 instructions, we will assume it's not safe. 867 for (unsigned i = 0; i < 2; ++i) { 868 bool SeenDef = false; 869 for (unsigned j = 0, e = I->getNumOperands(); j != e; ++j) { 870 MachineOperand &MO = I->getOperand(j); 871 if (!MO.isReg()) 872 continue; 873 if (MO.getReg() == X86::EFLAGS) { 874 if (MO.isUse()) 875 return false; 876 SeenDef = true; 877 } 878 } 879 880 if (SeenDef) 881 // This instruction defines EFLAGS, no need to look any further. 882 return true; 883 ++I; 884 885 // If we make it to the end of the block, it's safe to clobber EFLAGS. 886 if (I == MBB.end()) 887 return true; 888 } 889 890 // Conservative answer. 891 return false; 892} 893 894void X86InstrInfo::reMaterialize(MachineBasicBlock &MBB, 895 MachineBasicBlock::iterator I, 896 unsigned DestReg, 897 const MachineInstr *Orig) const { 898 DebugLoc DL = DebugLoc::getUnknownLoc(); 899 if (I != MBB.end()) DL = I->getDebugLoc(); 900 901 unsigned SubIdx = Orig->getOperand(0).isReg() 902 ? Orig->getOperand(0).getSubReg() : 0; 903 bool ChangeSubIdx = SubIdx != 0; 904 if (SubIdx && TargetRegisterInfo::isPhysicalRegister(DestReg)) { 905 DestReg = RI.getSubReg(DestReg, SubIdx); 906 SubIdx = 0; 907 } 908 909 // MOV32r0 etc. are implemented with xor which clobbers condition code. 910 // Re-materialize them as movri instructions to avoid side effects. 911 bool Emitted = false; 912 switch (Orig->getOpcode()) { 913 default: break; 914 case X86::MOV8r0: 915 case X86::MOV16r0: 916 case X86::MOV32r0: 917 case X86::MOV64r0: { 918 if (!isSafeToClobberEFLAGS(MBB, I)) { 919 unsigned Opc = 0; 920 switch (Orig->getOpcode()) { 921 default: break; 922 case X86::MOV8r0: Opc = X86::MOV8ri; break; 923 case X86::MOV16r0: Opc = X86::MOV16ri; break; 924 case X86::MOV32r0: Opc = X86::MOV32ri; break; 925 case X86::MOV64r0: Opc = X86::MOV64ri32; break; 926 } 927 BuildMI(MBB, I, DL, get(Opc), DestReg).addImm(0); 928 Emitted = true; 929 } 930 break; 931 } 932 } 933 934 if (!Emitted) { 935 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig); 936 MI->getOperand(0).setReg(DestReg); 937 MBB.insert(I, MI); 938 } 939 940 if (ChangeSubIdx) { 941 MachineInstr *NewMI = prior(I); 942 NewMI->getOperand(0).setSubReg(SubIdx); 943 } 944} 945 946/// isInvariantLoad - Return true if the specified instruction (which is marked 947/// mayLoad) is loading from a location whose value is invariant across the 948/// function. For example, loading a value from the constant pool or from 949/// from the argument area of a function if it does not change. This should 950/// only return true of *all* loads the instruction does are invariant (if it 951/// does multiple loads). 952bool X86InstrInfo::isInvariantLoad(const MachineInstr *MI) const { 953 // This code cares about loads from three cases: constant pool entries, 954 // invariant argument slots, and global stubs. In order to handle these cases 955 // for all of the myriad of X86 instructions, we just scan for a CP/FI/GV 956 // operand and base our analysis on it. This is safe because the address of 957 // none of these three cases is ever used as anything other than a load base 958 // and X86 doesn't have any instructions that load from multiple places. 959 960 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 961 const MachineOperand &MO = MI->getOperand(i); 962 // Loads from constant pools are trivially invariant. 963 if (MO.isCPI()) 964 return true; 965 966 if (MO.isGlobal()) 967 return isGVStub(MO.getGlobal(), TM); 968 969 // If this is a load from an invariant stack slot, the load is a constant. 970 if (MO.isFI()) { 971 const MachineFrameInfo &MFI = 972 *MI->getParent()->getParent()->getFrameInfo(); 973 int Idx = MO.getIndex(); 974 return MFI.isFixedObjectIndex(Idx) && MFI.isImmutableObjectIndex(Idx); 975 } 976 } 977 978 // All other instances of these instructions are presumed to have other 979 // issues. 980 return false; 981} 982 983/// hasLiveCondCodeDef - True if MI has a condition code def, e.g. EFLAGS, that 984/// is not marked dead. 985static bool hasLiveCondCodeDef(MachineInstr *MI) { 986 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 987 MachineOperand &MO = MI->getOperand(i); 988 if (MO.isReg() && MO.isDef() && 989 MO.getReg() == X86::EFLAGS && !MO.isDead()) { 990 return true; 991 } 992 } 993 return false; 994} 995 996/// convertToThreeAddress - This method must be implemented by targets that 997/// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target 998/// may be able to convert a two-address instruction into a true 999/// three-address instruction on demand. This allows the X86 target (for 1000/// example) to convert ADD and SHL instructions into LEA instructions if they 1001/// would require register copies due to two-addressness. 1002/// 1003/// This method returns a null pointer if the transformation cannot be 1004/// performed, otherwise it returns the new instruction. 1005/// 1006MachineInstr * 1007X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI, 1008 MachineBasicBlock::iterator &MBBI, 1009 LiveVariables *LV) const { 1010 MachineInstr *MI = MBBI; 1011 MachineFunction &MF = *MI->getParent()->getParent(); 1012 // All instructions input are two-addr instructions. Get the known operands. 1013 unsigned Dest = MI->getOperand(0).getReg(); 1014 unsigned Src = MI->getOperand(1).getReg(); 1015 bool isDead = MI->getOperand(0).isDead(); 1016 bool isKill = MI->getOperand(1).isKill(); 1017 1018 MachineInstr *NewMI = NULL; 1019 // FIXME: 16-bit LEA's are really slow on Athlons, but not bad on P4's. When 1020 // we have better subtarget support, enable the 16-bit LEA generation here. 1021 bool DisableLEA16 = true; 1022 1023 unsigned MIOpc = MI->getOpcode(); 1024 switch (MIOpc) { 1025 case X86::SHUFPSrri: { 1026 assert(MI->getNumOperands() == 4 && "Unknown shufps instruction!"); 1027 if (!TM.getSubtarget<X86Subtarget>().hasSSE2()) return 0; 1028 1029 unsigned B = MI->getOperand(1).getReg(); 1030 unsigned C = MI->getOperand(2).getReg(); 1031 if (B != C) return 0; 1032 unsigned A = MI->getOperand(0).getReg(); 1033 unsigned M = MI->getOperand(3).getImm(); 1034 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::PSHUFDri)) 1035 .addReg(A, true, false, false, isDead) 1036 .addReg(B, false, false, isKill).addImm(M); 1037 break; 1038 } 1039 case X86::SHL64ri: { 1040 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!"); 1041 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses 1042 // the flags produced by a shift yet, so this is safe. 1043 unsigned ShAmt = MI->getOperand(2).getImm(); 1044 if (ShAmt == 0 || ShAmt >= 4) return 0; 1045 1046 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r)) 1047 .addReg(Dest, true, false, false, isDead) 1048 .addReg(0).addImm(1 << ShAmt).addReg(Src, false, false, isKill).addImm(0); 1049 break; 1050 } 1051 case X86::SHL32ri: { 1052 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!"); 1053 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses 1054 // the flags produced by a shift yet, so this is safe. 1055 unsigned ShAmt = MI->getOperand(2).getImm(); 1056 if (ShAmt == 0 || ShAmt >= 4) return 0; 1057 1058 unsigned Opc = TM.getSubtarget<X86Subtarget>().is64Bit() ? 1059 X86::LEA64_32r : X86::LEA32r; 1060 NewMI = BuildMI(MF, MI->getDebugLoc(), get(Opc)) 1061 .addReg(Dest, true, false, false, isDead) 1062 .addReg(0).addImm(1 << ShAmt) 1063 .addReg(Src, false, false, isKill).addImm(0); 1064 break; 1065 } 1066 case X86::SHL16ri: { 1067 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!"); 1068 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses 1069 // the flags produced by a shift yet, so this is safe. 1070 unsigned ShAmt = MI->getOperand(2).getImm(); 1071 if (ShAmt == 0 || ShAmt >= 4) return 0; 1072 1073 if (DisableLEA16) { 1074 // If 16-bit LEA is disabled, use 32-bit LEA via subregisters. 1075 MachineRegisterInfo &RegInfo = MFI->getParent()->getRegInfo(); 1076 unsigned Opc = TM.getSubtarget<X86Subtarget>().is64Bit() 1077 ? X86::LEA64_32r : X86::LEA32r; 1078 unsigned leaInReg = RegInfo.createVirtualRegister(&X86::GR32RegClass); 1079 unsigned leaOutReg = RegInfo.createVirtualRegister(&X86::GR32RegClass); 1080 1081 // Build and insert into an implicit UNDEF value. This is OK because 1082 // well be shifting and then extracting the lower 16-bits. 1083 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg); 1084 MachineInstr *InsMI = 1085 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::INSERT_SUBREG),leaInReg) 1086 .addReg(leaInReg).addReg(Src, false, false, isKill) 1087 .addImm(X86::SUBREG_16BIT); 1088 1089 NewMI = BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(Opc), leaOutReg) 1090 .addReg(0).addImm(1 << ShAmt) 1091 .addReg(leaInReg, false, false, true).addImm(0); 1092 1093 MachineInstr *ExtMI = 1094 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::EXTRACT_SUBREG)) 1095 .addReg(Dest, true, false, false, isDead) 1096 .addReg(leaOutReg, false, false, true).addImm(X86::SUBREG_16BIT); 1097 1098 if (LV) { 1099 // Update live variables 1100 LV->getVarInfo(leaInReg).Kills.push_back(NewMI); 1101 LV->getVarInfo(leaOutReg).Kills.push_back(ExtMI); 1102 if (isKill) 1103 LV->replaceKillInstruction(Src, MI, InsMI); 1104 if (isDead) 1105 LV->replaceKillInstruction(Dest, MI, ExtMI); 1106 } 1107 return ExtMI; 1108 } else { 1109 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r)) 1110 .addReg(Dest, true, false, false, isDead) 1111 .addReg(0).addImm(1 << ShAmt) 1112 .addReg(Src, false, false, isKill).addImm(0); 1113 } 1114 break; 1115 } 1116 default: { 1117 // The following opcodes also sets the condition code register(s). Only 1118 // convert them to equivalent lea if the condition code register def's 1119 // are dead! 1120 if (hasLiveCondCodeDef(MI)) 1121 return 0; 1122 1123 bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit(); 1124 switch (MIOpc) { 1125 default: return 0; 1126 case X86::INC64r: 1127 case X86::INC32r: 1128 case X86::INC64_32r: { 1129 assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!"); 1130 unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r 1131 : (is64Bit ? X86::LEA64_32r : X86::LEA32r); 1132 NewMI = addLeaRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc)) 1133 .addReg(Dest, true, false, false, isDead), 1134 Src, isKill, 1); 1135 break; 1136 } 1137 case X86::INC16r: 1138 case X86::INC64_16r: 1139 if (DisableLEA16) return 0; 1140 assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!"); 1141 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r)) 1142 .addReg(Dest, true, false, false, isDead), 1143 Src, isKill, 1); 1144 break; 1145 case X86::DEC64r: 1146 case X86::DEC32r: 1147 case X86::DEC64_32r: { 1148 assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!"); 1149 unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r 1150 : (is64Bit ? X86::LEA64_32r : X86::LEA32r); 1151 NewMI = addLeaRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc)) 1152 .addReg(Dest, true, false, false, isDead), 1153 Src, isKill, -1); 1154 break; 1155 } 1156 case X86::DEC16r: 1157 case X86::DEC64_16r: 1158 if (DisableLEA16) return 0; 1159 assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!"); 1160 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r)) 1161 .addReg(Dest, true, false, false, isDead), 1162 Src, isKill, -1); 1163 break; 1164 case X86::ADD64rr: 1165 case X86::ADD32rr: { 1166 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!"); 1167 unsigned Opc = MIOpc == X86::ADD64rr ? X86::LEA64r 1168 : (is64Bit ? X86::LEA64_32r : X86::LEA32r); 1169 unsigned Src2 = MI->getOperand(2).getReg(); 1170 bool isKill2 = MI->getOperand(2).isKill(); 1171 NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(Opc)) 1172 .addReg(Dest, true, false, false, isDead), 1173 Src, isKill, Src2, isKill2); 1174 if (LV && isKill2) 1175 LV->replaceKillInstruction(Src2, MI, NewMI); 1176 break; 1177 } 1178 case X86::ADD16rr: { 1179 if (DisableLEA16) return 0; 1180 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!"); 1181 unsigned Src2 = MI->getOperand(2).getReg(); 1182 bool isKill2 = MI->getOperand(2).isKill(); 1183 NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r)) 1184 .addReg(Dest, true, false, false, isDead), 1185 Src, isKill, Src2, isKill2); 1186 if (LV && isKill2) 1187 LV->replaceKillInstruction(Src2, MI, NewMI); 1188 break; 1189 } 1190 case X86::ADD64ri32: 1191 case X86::ADD64ri8: 1192 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!"); 1193 if (MI->getOperand(2).isImm()) 1194 NewMI = addLeaRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r)) 1195 .addReg(Dest, true, false, false, isDead), 1196 Src, isKill, MI->getOperand(2).getImm()); 1197 break; 1198 case X86::ADD32ri: 1199 case X86::ADD32ri8: 1200 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!"); 1201 if (MI->getOperand(2).isImm()) { 1202 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r; 1203 NewMI = addLeaRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc)) 1204 .addReg(Dest, true, false, false, isDead), 1205 Src, isKill, MI->getOperand(2).getImm()); 1206 } 1207 break; 1208 case X86::ADD16ri: 1209 case X86::ADD16ri8: 1210 if (DisableLEA16) return 0; 1211 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!"); 1212 if (MI->getOperand(2).isImm()) 1213 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r)) 1214 .addReg(Dest, true, false, false, isDead), 1215 Src, isKill, MI->getOperand(2).getImm()); 1216 break; 1217 case X86::SHL16ri: 1218 if (DisableLEA16) return 0; 1219 case X86::SHL32ri: 1220 case X86::SHL64ri: { 1221 assert(MI->getNumOperands() >= 3 && MI->getOperand(2).isImm() && 1222 "Unknown shl instruction!"); 1223 unsigned ShAmt = MI->getOperand(2).getImm(); 1224 if (ShAmt == 1 || ShAmt == 2 || ShAmt == 3) { 1225 X86AddressMode AM; 1226 AM.Scale = 1 << ShAmt; 1227 AM.IndexReg = Src; 1228 unsigned Opc = MIOpc == X86::SHL64ri ? X86::LEA64r 1229 : (MIOpc == X86::SHL32ri 1230 ? (is64Bit ? X86::LEA64_32r : X86::LEA32r) : X86::LEA16r); 1231 NewMI = addFullAddress(BuildMI(MF, MI->getDebugLoc(), get(Opc)) 1232 .addReg(Dest, true, false, false, isDead), AM); 1233 if (isKill) 1234 NewMI->getOperand(3).setIsKill(true); 1235 } 1236 break; 1237 } 1238 } 1239 } 1240 } 1241 1242 if (!NewMI) return 0; 1243 1244 if (LV) { // Update live variables 1245 if (isKill) 1246 LV->replaceKillInstruction(Src, MI, NewMI); 1247 if (isDead) 1248 LV->replaceKillInstruction(Dest, MI, NewMI); 1249 } 1250 1251 MFI->insert(MBBI, NewMI); // Insert the new inst 1252 return NewMI; 1253} 1254 1255/// commuteInstruction - We have a few instructions that must be hacked on to 1256/// commute them. 1257/// 1258MachineInstr * 1259X86InstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const { 1260 switch (MI->getOpcode()) { 1261 case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I) 1262 case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I) 1263 case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I) 1264 case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I) 1265 case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I -> A = SHLD64rri8 C, B, (64-I) 1266 case X86::SHLD64rri8:{// A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, (64-I) 1267 unsigned Opc; 1268 unsigned Size; 1269 switch (MI->getOpcode()) { 1270 default: assert(0 && "Unreachable!"); 1271 case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break; 1272 case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break; 1273 case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break; 1274 case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break; 1275 case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break; 1276 case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break; 1277 } 1278 unsigned Amt = MI->getOperand(3).getImm(); 1279 if (NewMI) { 1280 MachineFunction &MF = *MI->getParent()->getParent(); 1281 MI = MF.CloneMachineInstr(MI); 1282 NewMI = false; 1283 } 1284 MI->setDesc(get(Opc)); 1285 MI->getOperand(3).setImm(Size-Amt); 1286 return TargetInstrInfoImpl::commuteInstruction(MI, NewMI); 1287 } 1288 case X86::CMOVB16rr: 1289 case X86::CMOVB32rr: 1290 case X86::CMOVB64rr: 1291 case X86::CMOVAE16rr: 1292 case X86::CMOVAE32rr: 1293 case X86::CMOVAE64rr: 1294 case X86::CMOVE16rr: 1295 case X86::CMOVE32rr: 1296 case X86::CMOVE64rr: 1297 case X86::CMOVNE16rr: 1298 case X86::CMOVNE32rr: 1299 case X86::CMOVNE64rr: 1300 case X86::CMOVBE16rr: 1301 case X86::CMOVBE32rr: 1302 case X86::CMOVBE64rr: 1303 case X86::CMOVA16rr: 1304 case X86::CMOVA32rr: 1305 case X86::CMOVA64rr: 1306 case X86::CMOVL16rr: 1307 case X86::CMOVL32rr: 1308 case X86::CMOVL64rr: 1309 case X86::CMOVGE16rr: 1310 case X86::CMOVGE32rr: 1311 case X86::CMOVGE64rr: 1312 case X86::CMOVLE16rr: 1313 case X86::CMOVLE32rr: 1314 case X86::CMOVLE64rr: 1315 case X86::CMOVG16rr: 1316 case X86::CMOVG32rr: 1317 case X86::CMOVG64rr: 1318 case X86::CMOVS16rr: 1319 case X86::CMOVS32rr: 1320 case X86::CMOVS64rr: 1321 case X86::CMOVNS16rr: 1322 case X86::CMOVNS32rr: 1323 case X86::CMOVNS64rr: 1324 case X86::CMOVP16rr: 1325 case X86::CMOVP32rr: 1326 case X86::CMOVP64rr: 1327 case X86::CMOVNP16rr: 1328 case X86::CMOVNP32rr: 1329 case X86::CMOVNP64rr: 1330 case X86::CMOVO16rr: 1331 case X86::CMOVO32rr: 1332 case X86::CMOVO64rr: 1333 case X86::CMOVNO16rr: 1334 case X86::CMOVNO32rr: 1335 case X86::CMOVNO64rr: { 1336 unsigned Opc = 0; 1337 switch (MI->getOpcode()) { 1338 default: break; 1339 case X86::CMOVB16rr: Opc = X86::CMOVAE16rr; break; 1340 case X86::CMOVB32rr: Opc = X86::CMOVAE32rr; break; 1341 case X86::CMOVB64rr: Opc = X86::CMOVAE64rr; break; 1342 case X86::CMOVAE16rr: Opc = X86::CMOVB16rr; break; 1343 case X86::CMOVAE32rr: Opc = X86::CMOVB32rr; break; 1344 case X86::CMOVAE64rr: Opc = X86::CMOVB64rr; break; 1345 case X86::CMOVE16rr: Opc = X86::CMOVNE16rr; break; 1346 case X86::CMOVE32rr: Opc = X86::CMOVNE32rr; break; 1347 case X86::CMOVE64rr: Opc = X86::CMOVNE64rr; break; 1348 case X86::CMOVNE16rr: Opc = X86::CMOVE16rr; break; 1349 case X86::CMOVNE32rr: Opc = X86::CMOVE32rr; break; 1350 case X86::CMOVNE64rr: Opc = X86::CMOVE64rr; break; 1351 case X86::CMOVBE16rr: Opc = X86::CMOVA16rr; break; 1352 case X86::CMOVBE32rr: Opc = X86::CMOVA32rr; break; 1353 case X86::CMOVBE64rr: Opc = X86::CMOVA64rr; break; 1354 case X86::CMOVA16rr: Opc = X86::CMOVBE16rr; break; 1355 case X86::CMOVA32rr: Opc = X86::CMOVBE32rr; break; 1356 case X86::CMOVA64rr: Opc = X86::CMOVBE64rr; break; 1357 case X86::CMOVL16rr: Opc = X86::CMOVGE16rr; break; 1358 case X86::CMOVL32rr: Opc = X86::CMOVGE32rr; break; 1359 case X86::CMOVL64rr: Opc = X86::CMOVGE64rr; break; 1360 case X86::CMOVGE16rr: Opc = X86::CMOVL16rr; break; 1361 case X86::CMOVGE32rr: Opc = X86::CMOVL32rr; break; 1362 case X86::CMOVGE64rr: Opc = X86::CMOVL64rr; break; 1363 case X86::CMOVLE16rr: Opc = X86::CMOVG16rr; break; 1364 case X86::CMOVLE32rr: Opc = X86::CMOVG32rr; break; 1365 case X86::CMOVLE64rr: Opc = X86::CMOVG64rr; break; 1366 case X86::CMOVG16rr: Opc = X86::CMOVLE16rr; break; 1367 case X86::CMOVG32rr: Opc = X86::CMOVLE32rr; break; 1368 case X86::CMOVG64rr: Opc = X86::CMOVLE64rr; break; 1369 case X86::CMOVS16rr: Opc = X86::CMOVNS16rr; break; 1370 case X86::CMOVS32rr: Opc = X86::CMOVNS32rr; break; 1371 case X86::CMOVS64rr: Opc = X86::CMOVNS32rr; break; 1372 case X86::CMOVNS16rr: Opc = X86::CMOVS16rr; break; 1373 case X86::CMOVNS32rr: Opc = X86::CMOVS32rr; break; 1374 case X86::CMOVNS64rr: Opc = X86::CMOVS64rr; break; 1375 case X86::CMOVP16rr: Opc = X86::CMOVNP16rr; break; 1376 case X86::CMOVP32rr: Opc = X86::CMOVNP32rr; break; 1377 case X86::CMOVP64rr: Opc = X86::CMOVNP32rr; break; 1378 case X86::CMOVNP16rr: Opc = X86::CMOVP16rr; break; 1379 case X86::CMOVNP32rr: Opc = X86::CMOVP32rr; break; 1380 case X86::CMOVNP64rr: Opc = X86::CMOVP64rr; break; 1381 case X86::CMOVO16rr: Opc = X86::CMOVNO16rr; break; 1382 case X86::CMOVO32rr: Opc = X86::CMOVNO32rr; break; 1383 case X86::CMOVO64rr: Opc = X86::CMOVNO32rr; break; 1384 case X86::CMOVNO16rr: Opc = X86::CMOVO16rr; break; 1385 case X86::CMOVNO32rr: Opc = X86::CMOVO32rr; break; 1386 case X86::CMOVNO64rr: Opc = X86::CMOVO64rr; break; 1387 } 1388 if (NewMI) { 1389 MachineFunction &MF = *MI->getParent()->getParent(); 1390 MI = MF.CloneMachineInstr(MI); 1391 NewMI = false; 1392 } 1393 MI->setDesc(get(Opc)); 1394 // Fallthrough intended. 1395 } 1396 default: 1397 return TargetInstrInfoImpl::commuteInstruction(MI, NewMI); 1398 } 1399} 1400 1401static X86::CondCode GetCondFromBranchOpc(unsigned BrOpc) { 1402 switch (BrOpc) { 1403 default: return X86::COND_INVALID; 1404 case X86::JE: return X86::COND_E; 1405 case X86::JNE: return X86::COND_NE; 1406 case X86::JL: return X86::COND_L; 1407 case X86::JLE: return X86::COND_LE; 1408 case X86::JG: return X86::COND_G; 1409 case X86::JGE: return X86::COND_GE; 1410 case X86::JB: return X86::COND_B; 1411 case X86::JBE: return X86::COND_BE; 1412 case X86::JA: return X86::COND_A; 1413 case X86::JAE: return X86::COND_AE; 1414 case X86::JS: return X86::COND_S; 1415 case X86::JNS: return X86::COND_NS; 1416 case X86::JP: return X86::COND_P; 1417 case X86::JNP: return X86::COND_NP; 1418 case X86::JO: return X86::COND_O; 1419 case X86::JNO: return X86::COND_NO; 1420 } 1421} 1422 1423unsigned X86::GetCondBranchFromCond(X86::CondCode CC) { 1424 switch (CC) { 1425 default: assert(0 && "Illegal condition code!"); 1426 case X86::COND_E: return X86::JE; 1427 case X86::COND_NE: return X86::JNE; 1428 case X86::COND_L: return X86::JL; 1429 case X86::COND_LE: return X86::JLE; 1430 case X86::COND_G: return X86::JG; 1431 case X86::COND_GE: return X86::JGE; 1432 case X86::COND_B: return X86::JB; 1433 case X86::COND_BE: return X86::JBE; 1434 case X86::COND_A: return X86::JA; 1435 case X86::COND_AE: return X86::JAE; 1436 case X86::COND_S: return X86::JS; 1437 case X86::COND_NS: return X86::JNS; 1438 case X86::COND_P: return X86::JP; 1439 case X86::COND_NP: return X86::JNP; 1440 case X86::COND_O: return X86::JO; 1441 case X86::COND_NO: return X86::JNO; 1442 } 1443} 1444 1445/// GetOppositeBranchCondition - Return the inverse of the specified condition, 1446/// e.g. turning COND_E to COND_NE. 1447X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) { 1448 switch (CC) { 1449 default: assert(0 && "Illegal condition code!"); 1450 case X86::COND_E: return X86::COND_NE; 1451 case X86::COND_NE: return X86::COND_E; 1452 case X86::COND_L: return X86::COND_GE; 1453 case X86::COND_LE: return X86::COND_G; 1454 case X86::COND_G: return X86::COND_LE; 1455 case X86::COND_GE: return X86::COND_L; 1456 case X86::COND_B: return X86::COND_AE; 1457 case X86::COND_BE: return X86::COND_A; 1458 case X86::COND_A: return X86::COND_BE; 1459 case X86::COND_AE: return X86::COND_B; 1460 case X86::COND_S: return X86::COND_NS; 1461 case X86::COND_NS: return X86::COND_S; 1462 case X86::COND_P: return X86::COND_NP; 1463 case X86::COND_NP: return X86::COND_P; 1464 case X86::COND_O: return X86::COND_NO; 1465 case X86::COND_NO: return X86::COND_O; 1466 } 1467} 1468 1469bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const { 1470 const TargetInstrDesc &TID = MI->getDesc(); 1471 if (!TID.isTerminator()) return false; 1472 1473 // Conditional branch is a special case. 1474 if (TID.isBranch() && !TID.isBarrier()) 1475 return true; 1476 if (!TID.isPredicable()) 1477 return true; 1478 return !isPredicated(MI); 1479} 1480 1481// For purposes of branch analysis do not count FP_REG_KILL as a terminator. 1482static bool isBrAnalysisUnpredicatedTerminator(const MachineInstr *MI, 1483 const X86InstrInfo &TII) { 1484 if (MI->getOpcode() == X86::FP_REG_KILL) 1485 return false; 1486 return TII.isUnpredicatedTerminator(MI); 1487} 1488 1489bool X86InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, 1490 MachineBasicBlock *&TBB, 1491 MachineBasicBlock *&FBB, 1492 SmallVectorImpl<MachineOperand> &Cond, 1493 bool AllowModify) const { 1494 // Start from the bottom of the block and work up, examining the 1495 // terminator instructions. 1496 MachineBasicBlock::iterator I = MBB.end(); 1497 while (I != MBB.begin()) { 1498 --I; 1499 // Working from the bottom, when we see a non-terminator 1500 // instruction, we're done. 1501 if (!isBrAnalysisUnpredicatedTerminator(I, *this)) 1502 break; 1503 // A terminator that isn't a branch can't easily be handled 1504 // by this analysis. 1505 if (!I->getDesc().isBranch()) 1506 return true; 1507 // Handle unconditional branches. 1508 if (I->getOpcode() == X86::JMP) { 1509 if (!AllowModify) { 1510 TBB = I->getOperand(0).getMBB(); 1511 return false; 1512 } 1513 1514 // If the block has any instructions after a JMP, delete them. 1515 while (next(I) != MBB.end()) 1516 next(I)->eraseFromParent(); 1517 Cond.clear(); 1518 FBB = 0; 1519 // Delete the JMP if it's equivalent to a fall-through. 1520 if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) { 1521 TBB = 0; 1522 I->eraseFromParent(); 1523 I = MBB.end(); 1524 continue; 1525 } 1526 // TBB is used to indicate the unconditinal destination. 1527 TBB = I->getOperand(0).getMBB(); 1528 continue; 1529 } 1530 // Handle conditional branches. 1531 X86::CondCode BranchCode = GetCondFromBranchOpc(I->getOpcode()); 1532 if (BranchCode == X86::COND_INVALID) 1533 return true; // Can't handle indirect branch. 1534 // Working from the bottom, handle the first conditional branch. 1535 if (Cond.empty()) { 1536 FBB = TBB; 1537 TBB = I->getOperand(0).getMBB(); 1538 Cond.push_back(MachineOperand::CreateImm(BranchCode)); 1539 continue; 1540 } 1541 // Handle subsequent conditional branches. Only handle the case 1542 // where all conditional branches branch to the same destination 1543 // and their condition opcodes fit one of the special 1544 // multi-branch idioms. 1545 assert(Cond.size() == 1); 1546 assert(TBB); 1547 // Only handle the case where all conditional branches branch to 1548 // the same destination. 1549 if (TBB != I->getOperand(0).getMBB()) 1550 return true; 1551 X86::CondCode OldBranchCode = (X86::CondCode)Cond[0].getImm(); 1552 // If the conditions are the same, we can leave them alone. 1553 if (OldBranchCode == BranchCode) 1554 continue; 1555 // If they differ, see if they fit one of the known patterns. 1556 // Theoretically we could handle more patterns here, but 1557 // we shouldn't expect to see them if instruction selection 1558 // has done a reasonable job. 1559 if ((OldBranchCode == X86::COND_NP && 1560 BranchCode == X86::COND_E) || 1561 (OldBranchCode == X86::COND_E && 1562 BranchCode == X86::COND_NP)) 1563 BranchCode = X86::COND_NP_OR_E; 1564 else if ((OldBranchCode == X86::COND_P && 1565 BranchCode == X86::COND_NE) || 1566 (OldBranchCode == X86::COND_NE && 1567 BranchCode == X86::COND_P)) 1568 BranchCode = X86::COND_NE_OR_P; 1569 else 1570 return true; 1571 // Update the MachineOperand. 1572 Cond[0].setImm(BranchCode); 1573 } 1574 1575 return false; 1576} 1577 1578unsigned X86InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const { 1579 MachineBasicBlock::iterator I = MBB.end(); 1580 unsigned Count = 0; 1581 1582 while (I != MBB.begin()) { 1583 --I; 1584 if (I->getOpcode() != X86::JMP && 1585 GetCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID) 1586 break; 1587 // Remove the branch. 1588 I->eraseFromParent(); 1589 I = MBB.end(); 1590 ++Count; 1591 } 1592 1593 return Count; 1594} 1595 1596unsigned 1597X86InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 1598 MachineBasicBlock *FBB, 1599 const SmallVectorImpl<MachineOperand> &Cond) const { 1600 // FIXME this should probably have a DebugLoc operand 1601 DebugLoc dl = DebugLoc::getUnknownLoc(); 1602 // Shouldn't be a fall through. 1603 assert(TBB && "InsertBranch must not be told to insert a fallthrough"); 1604 assert((Cond.size() == 1 || Cond.size() == 0) && 1605 "X86 branch conditions have one component!"); 1606 1607 if (Cond.empty()) { 1608 // Unconditional branch? 1609 assert(!FBB && "Unconditional branch with multiple successors!"); 1610 BuildMI(&MBB, dl, get(X86::JMP)).addMBB(TBB); 1611 return 1; 1612 } 1613 1614 // Conditional branch. 1615 unsigned Count = 0; 1616 X86::CondCode CC = (X86::CondCode)Cond[0].getImm(); 1617 switch (CC) { 1618 case X86::COND_NP_OR_E: 1619 // Synthesize NP_OR_E with two branches. 1620 BuildMI(&MBB, dl, get(X86::JNP)).addMBB(TBB); 1621 ++Count; 1622 BuildMI(&MBB, dl, get(X86::JE)).addMBB(TBB); 1623 ++Count; 1624 break; 1625 case X86::COND_NE_OR_P: 1626 // Synthesize NE_OR_P with two branches. 1627 BuildMI(&MBB, dl, get(X86::JNE)).addMBB(TBB); 1628 ++Count; 1629 BuildMI(&MBB, dl, get(X86::JP)).addMBB(TBB); 1630 ++Count; 1631 break; 1632 default: { 1633 unsigned Opc = GetCondBranchFromCond(CC); 1634 BuildMI(&MBB, dl, get(Opc)).addMBB(TBB); 1635 ++Count; 1636 } 1637 } 1638 if (FBB) { 1639 // Two-way Conditional branch. Insert the second branch. 1640 BuildMI(&MBB, dl, get(X86::JMP)).addMBB(FBB); 1641 ++Count; 1642 } 1643 return Count; 1644} 1645 1646/// isHReg - Test if the given register is a physical h register. 1647static bool isHReg(unsigned Reg) { 1648 return Reg == X86::AH || Reg == X86::BH || Reg == X86::CH || Reg == X86::DH; 1649} 1650 1651bool X86InstrInfo::copyRegToReg(MachineBasicBlock &MBB, 1652 MachineBasicBlock::iterator MI, 1653 unsigned DestReg, unsigned SrcReg, 1654 const TargetRegisterClass *DestRC, 1655 const TargetRegisterClass *SrcRC) const { 1656 DebugLoc DL = DebugLoc::getUnknownLoc(); 1657 if (MI != MBB.end()) DL = MI->getDebugLoc(); 1658 1659 if (DestRC == SrcRC) { 1660 unsigned Opc; 1661 if (DestRC == &X86::GR64RegClass) { 1662 Opc = X86::MOV64rr; 1663 } else if (DestRC == &X86::GR32RegClass) { 1664 Opc = X86::MOV32rr; 1665 } else if (DestRC == &X86::GR16RegClass) { 1666 Opc = X86::MOV16rr; 1667 } else if (DestRC == &X86::GR8RegClass) { 1668 // Copying two or from a physical H register on x86-64 requires a NOREX 1669 // move. Otherwise use a normal move. 1670 if ((isHReg(DestReg) || isHReg(SrcReg)) && 1671 TM.getSubtarget<X86Subtarget>().is64Bit()) 1672 Opc = X86::MOV8rr_NOREX; 1673 else 1674 Opc = X86::MOV8rr; 1675 } else if (DestRC == &X86::GR64_RegClass) { 1676 Opc = X86::MOV64rr; 1677 } else if (DestRC == &X86::GR32_RegClass) { 1678 Opc = X86::MOV32rr; 1679 } else if (DestRC == &X86::GR16_RegClass) { 1680 Opc = X86::MOV16rr; 1681 } else if (DestRC == &X86::GR8_RegClass) { 1682 Opc = X86::MOV8rr; 1683 } else if (DestRC == &X86::GR64_NOREXRegClass) { 1684 Opc = X86::MOV64rr; 1685 } else if (DestRC == &X86::GR32_NOREXRegClass) { 1686 Opc = X86::MOV32rr; 1687 } else if (DestRC == &X86::GR16_NOREXRegClass) { 1688 Opc = X86::MOV16rr; 1689 } else if (DestRC == &X86::GR8_NOREXRegClass) { 1690 Opc = X86::MOV8rr; 1691 } else if (DestRC == &X86::RFP32RegClass) { 1692 Opc = X86::MOV_Fp3232; 1693 } else if (DestRC == &X86::RFP64RegClass || DestRC == &X86::RSTRegClass) { 1694 Opc = X86::MOV_Fp6464; 1695 } else if (DestRC == &X86::RFP80RegClass) { 1696 Opc = X86::MOV_Fp8080; 1697 } else if (DestRC == &X86::FR32RegClass) { 1698 Opc = X86::FsMOVAPSrr; 1699 } else if (DestRC == &X86::FR64RegClass) { 1700 Opc = X86::FsMOVAPDrr; 1701 } else if (DestRC == &X86::VR128RegClass) { 1702 Opc = X86::MOVAPSrr; 1703 } else if (DestRC == &X86::VR64RegClass) { 1704 Opc = X86::MMX_MOVQ64rr; 1705 } else { 1706 return false; 1707 } 1708 BuildMI(MBB, MI, DL, get(Opc), DestReg).addReg(SrcReg); 1709 return true; 1710 } 1711 1712 // Moving EFLAGS to / from another register requires a push and a pop. 1713 if (SrcRC == &X86::CCRRegClass) { 1714 if (SrcReg != X86::EFLAGS) 1715 return false; 1716 if (DestRC == &X86::GR64RegClass) { 1717 BuildMI(MBB, MI, DL, get(X86::PUSHFQ)); 1718 BuildMI(MBB, MI, DL, get(X86::POP64r), DestReg); 1719 return true; 1720 } else if (DestRC == &X86::GR32RegClass) { 1721 BuildMI(MBB, MI, DL, get(X86::PUSHFD)); 1722 BuildMI(MBB, MI, DL, get(X86::POP32r), DestReg); 1723 return true; 1724 } 1725 } else if (DestRC == &X86::CCRRegClass) { 1726 if (DestReg != X86::EFLAGS) 1727 return false; 1728 if (SrcRC == &X86::GR64RegClass) { 1729 BuildMI(MBB, MI, DL, get(X86::PUSH64r)).addReg(SrcReg); 1730 BuildMI(MBB, MI, DL, get(X86::POPFQ)); 1731 return true; 1732 } else if (SrcRC == &X86::GR32RegClass) { 1733 BuildMI(MBB, MI, DL, get(X86::PUSH32r)).addReg(SrcReg); 1734 BuildMI(MBB, MI, DL, get(X86::POPFD)); 1735 return true; 1736 } 1737 } 1738 1739 // Moving from ST(0) turns into FpGET_ST0_32 etc. 1740 if (SrcRC == &X86::RSTRegClass) { 1741 // Copying from ST(0)/ST(1). 1742 if (SrcReg != X86::ST0 && SrcReg != X86::ST1) 1743 // Can only copy from ST(0)/ST(1) right now 1744 return false; 1745 bool isST0 = SrcReg == X86::ST0; 1746 unsigned Opc; 1747 if (DestRC == &X86::RFP32RegClass) 1748 Opc = isST0 ? X86::FpGET_ST0_32 : X86::FpGET_ST1_32; 1749 else if (DestRC == &X86::RFP64RegClass) 1750 Opc = isST0 ? X86::FpGET_ST0_64 : X86::FpGET_ST1_64; 1751 else { 1752 if (DestRC != &X86::RFP80RegClass) 1753 return false; 1754 Opc = isST0 ? X86::FpGET_ST0_80 : X86::FpGET_ST1_80; 1755 } 1756 BuildMI(MBB, MI, DL, get(Opc), DestReg); 1757 return true; 1758 } 1759 1760 // Moving to ST(0) turns into FpSET_ST0_32 etc. 1761 if (DestRC == &X86::RSTRegClass) { 1762 // Copying to ST(0) / ST(1). 1763 if (DestReg != X86::ST0 && DestReg != X86::ST1) 1764 // Can only copy to TOS right now 1765 return false; 1766 bool isST0 = DestReg == X86::ST0; 1767 unsigned Opc; 1768 if (SrcRC == &X86::RFP32RegClass) 1769 Opc = isST0 ? X86::FpSET_ST0_32 : X86::FpSET_ST1_32; 1770 else if (SrcRC == &X86::RFP64RegClass) 1771 Opc = isST0 ? X86::FpSET_ST0_64 : X86::FpSET_ST1_64; 1772 else { 1773 if (SrcRC != &X86::RFP80RegClass) 1774 return false; 1775 Opc = isST0 ? X86::FpSET_ST0_80 : X86::FpSET_ST1_80; 1776 } 1777 BuildMI(MBB, MI, DL, get(Opc)).addReg(SrcReg); 1778 return true; 1779 } 1780 1781 // Not yet supported! 1782 return false; 1783} 1784 1785static unsigned getStoreRegOpcode(const TargetRegisterClass *RC, 1786 bool isStackAligned) { 1787 unsigned Opc = 0; 1788 if (RC == &X86::GR64RegClass) { 1789 Opc = X86::MOV64mr; 1790 } else if (RC == &X86::GR32RegClass) { 1791 Opc = X86::MOV32mr; 1792 } else if (RC == &X86::GR16RegClass) { 1793 Opc = X86::MOV16mr; 1794 } else if (RC == &X86::GR8RegClass) { 1795 Opc = X86::MOV8mr; 1796 } else if (RC == &X86::GR64_RegClass) { 1797 Opc = X86::MOV64mr; 1798 } else if (RC == &X86::GR32_RegClass) { 1799 Opc = X86::MOV32mr; 1800 } else if (RC == &X86::GR16_RegClass) { 1801 Opc = X86::MOV16mr; 1802 } else if (RC == &X86::GR8_RegClass) { 1803 Opc = X86::MOV8mr; 1804 } else if (RC == &X86::GR64_NOREXRegClass) { 1805 Opc = X86::MOV64mr; 1806 } else if (RC == &X86::GR32_NOREXRegClass) { 1807 Opc = X86::MOV32mr; 1808 } else if (RC == &X86::GR16_NOREXRegClass) { 1809 Opc = X86::MOV16mr; 1810 } else if (RC == &X86::GR8_NOREXRegClass) { 1811 Opc = X86::MOV8mr; 1812 } else if (RC == &X86::RFP80RegClass) { 1813 Opc = X86::ST_FpP80m; // pops 1814 } else if (RC == &X86::RFP64RegClass) { 1815 Opc = X86::ST_Fp64m; 1816 } else if (RC == &X86::RFP32RegClass) { 1817 Opc = X86::ST_Fp32m; 1818 } else if (RC == &X86::FR32RegClass) { 1819 Opc = X86::MOVSSmr; 1820 } else if (RC == &X86::FR64RegClass) { 1821 Opc = X86::MOVSDmr; 1822 } else if (RC == &X86::VR128RegClass) { 1823 // If stack is realigned we can use aligned stores. 1824 Opc = isStackAligned ? X86::MOVAPSmr : X86::MOVUPSmr; 1825 } else if (RC == &X86::VR64RegClass) { 1826 Opc = X86::MMX_MOVQ64mr; 1827 } else { 1828 assert(0 && "Unknown regclass"); 1829 abort(); 1830 } 1831 1832 return Opc; 1833} 1834 1835void X86InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, 1836 MachineBasicBlock::iterator MI, 1837 unsigned SrcReg, bool isKill, int FrameIdx, 1838 const TargetRegisterClass *RC) const { 1839 const MachineFunction &MF = *MBB.getParent(); 1840 bool isAligned = (RI.getStackAlignment() >= 16) || 1841 RI.needsStackRealignment(MF); 1842 unsigned Opc = getStoreRegOpcode(RC, isAligned); 1843 DebugLoc DL = DebugLoc::getUnknownLoc(); 1844 if (MI != MBB.end()) DL = MI->getDebugLoc(); 1845 addFrameReference(BuildMI(MBB, MI, DL, get(Opc)), FrameIdx) 1846 .addReg(SrcReg, false, false, isKill); 1847} 1848 1849void X86InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, 1850 bool isKill, 1851 SmallVectorImpl<MachineOperand> &Addr, 1852 const TargetRegisterClass *RC, 1853 SmallVectorImpl<MachineInstr*> &NewMIs) const { 1854 bool isAligned = (RI.getStackAlignment() >= 16) || 1855 RI.needsStackRealignment(MF); 1856 unsigned Opc = getStoreRegOpcode(RC, isAligned); 1857 DebugLoc DL = DebugLoc::getUnknownLoc(); 1858 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc)); 1859 for (unsigned i = 0, e = Addr.size(); i != e; ++i) 1860 MIB.addOperand(Addr[i]); 1861 MIB.addReg(SrcReg, false, false, isKill); 1862 NewMIs.push_back(MIB); 1863} 1864 1865static unsigned getLoadRegOpcode(const TargetRegisterClass *RC, 1866 bool isStackAligned) { 1867 unsigned Opc = 0; 1868 if (RC == &X86::GR64RegClass) { 1869 Opc = X86::MOV64rm; 1870 } else if (RC == &X86::GR32RegClass) { 1871 Opc = X86::MOV32rm; 1872 } else if (RC == &X86::GR16RegClass) { 1873 Opc = X86::MOV16rm; 1874 } else if (RC == &X86::GR8RegClass) { 1875 Opc = X86::MOV8rm; 1876 } else if (RC == &X86::GR64_RegClass) { 1877 Opc = X86::MOV64rm; 1878 } else if (RC == &X86::GR32_RegClass) { 1879 Opc = X86::MOV32rm; 1880 } else if (RC == &X86::GR16_RegClass) { 1881 Opc = X86::MOV16rm; 1882 } else if (RC == &X86::GR8_RegClass) { 1883 Opc = X86::MOV8rm; 1884 } else if (RC == &X86::GR64_NOREXRegClass) { 1885 Opc = X86::MOV64rm; 1886 } else if (RC == &X86::GR32_NOREXRegClass) { 1887 Opc = X86::MOV32rm; 1888 } else if (RC == &X86::GR16_NOREXRegClass) { 1889 Opc = X86::MOV16rm; 1890 } else if (RC == &X86::GR8_NOREXRegClass) { 1891 Opc = X86::MOV8rm; 1892 } else if (RC == &X86::RFP80RegClass) { 1893 Opc = X86::LD_Fp80m; 1894 } else if (RC == &X86::RFP64RegClass) { 1895 Opc = X86::LD_Fp64m; 1896 } else if (RC == &X86::RFP32RegClass) { 1897 Opc = X86::LD_Fp32m; 1898 } else if (RC == &X86::FR32RegClass) { 1899 Opc = X86::MOVSSrm; 1900 } else if (RC == &X86::FR64RegClass) { 1901 Opc = X86::MOVSDrm; 1902 } else if (RC == &X86::VR128RegClass) { 1903 // If stack is realigned we can use aligned loads. 1904 Opc = isStackAligned ? X86::MOVAPSrm : X86::MOVUPSrm; 1905 } else if (RC == &X86::VR64RegClass) { 1906 Opc = X86::MMX_MOVQ64rm; 1907 } else { 1908 assert(0 && "Unknown regclass"); 1909 abort(); 1910 } 1911 1912 return Opc; 1913} 1914 1915void X86InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, 1916 MachineBasicBlock::iterator MI, 1917 unsigned DestReg, int FrameIdx, 1918 const TargetRegisterClass *RC) const{ 1919 const MachineFunction &MF = *MBB.getParent(); 1920 bool isAligned = (RI.getStackAlignment() >= 16) || 1921 RI.needsStackRealignment(MF); 1922 unsigned Opc = getLoadRegOpcode(RC, isAligned); 1923 DebugLoc DL = DebugLoc::getUnknownLoc(); 1924 if (MI != MBB.end()) DL = MI->getDebugLoc(); 1925 addFrameReference(BuildMI(MBB, MI, DL, get(Opc), DestReg), FrameIdx); 1926} 1927 1928void X86InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg, 1929 SmallVectorImpl<MachineOperand> &Addr, 1930 const TargetRegisterClass *RC, 1931 SmallVectorImpl<MachineInstr*> &NewMIs) const { 1932 bool isAligned = (RI.getStackAlignment() >= 16) || 1933 RI.needsStackRealignment(MF); 1934 unsigned Opc = getLoadRegOpcode(RC, isAligned); 1935 DebugLoc DL = DebugLoc::getUnknownLoc(); 1936 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg); 1937 for (unsigned i = 0, e = Addr.size(); i != e; ++i) 1938 MIB.addOperand(Addr[i]); 1939 NewMIs.push_back(MIB); 1940} 1941 1942bool X86InstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB, 1943 MachineBasicBlock::iterator MI, 1944 const std::vector<CalleeSavedInfo> &CSI) const { 1945 if (CSI.empty()) 1946 return false; 1947 1948 DebugLoc DL = DebugLoc::getUnknownLoc(); 1949 if (MI != MBB.end()) DL = MI->getDebugLoc(); 1950 1951 bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit(); 1952 unsigned SlotSize = is64Bit ? 8 : 4; 1953 1954 MachineFunction &MF = *MBB.getParent(); 1955 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>(); 1956 X86FI->setCalleeSavedFrameSize(CSI.size() * SlotSize); 1957 1958 unsigned Opc = is64Bit ? X86::PUSH64r : X86::PUSH32r; 1959 for (unsigned i = CSI.size(); i != 0; --i) { 1960 unsigned Reg = CSI[i-1].getReg(); 1961 // Add the callee-saved register as live-in. It's killed at the spill. 1962 MBB.addLiveIn(Reg); 1963 BuildMI(MBB, MI, DL, get(Opc)) 1964 .addReg(Reg, /*isDef=*/false, /*isImp=*/false, /*isKill=*/true); 1965 } 1966 return true; 1967} 1968 1969bool X86InstrInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB, 1970 MachineBasicBlock::iterator MI, 1971 const std::vector<CalleeSavedInfo> &CSI) const { 1972 if (CSI.empty()) 1973 return false; 1974 1975 DebugLoc DL = DebugLoc::getUnknownLoc(); 1976 if (MI != MBB.end()) DL = MI->getDebugLoc(); 1977 1978 bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit(); 1979 1980 unsigned Opc = is64Bit ? X86::POP64r : X86::POP32r; 1981 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 1982 unsigned Reg = CSI[i].getReg(); 1983 BuildMI(MBB, MI, DL, get(Opc), Reg); 1984 } 1985 return true; 1986} 1987 1988static MachineInstr *FuseTwoAddrInst(MachineFunction &MF, unsigned Opcode, 1989 const SmallVectorImpl<MachineOperand> &MOs, 1990 MachineInstr *MI, 1991 const TargetInstrInfo &TII) { 1992 // Create the base instruction with the memory operand as the first part. 1993 MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode), 1994 MI->getDebugLoc(), true); 1995 MachineInstrBuilder MIB(NewMI); 1996 unsigned NumAddrOps = MOs.size(); 1997 for (unsigned i = 0; i != NumAddrOps; ++i) 1998 MIB.addOperand(MOs[i]); 1999 if (NumAddrOps < 4) // FrameIndex only 2000 addOffset(MIB, 0); 2001 2002 // Loop over the rest of the ri operands, converting them over. 2003 unsigned NumOps = MI->getDesc().getNumOperands()-2; 2004 for (unsigned i = 0; i != NumOps; ++i) { 2005 MachineOperand &MO = MI->getOperand(i+2); 2006 MIB.addOperand(MO); 2007 } 2008 for (unsigned i = NumOps+2, e = MI->getNumOperands(); i != e; ++i) { 2009 MachineOperand &MO = MI->getOperand(i); 2010 MIB.addOperand(MO); 2011 } 2012 return MIB; 2013} 2014 2015static MachineInstr *FuseInst(MachineFunction &MF, 2016 unsigned Opcode, unsigned OpNo, 2017 const SmallVectorImpl<MachineOperand> &MOs, 2018 MachineInstr *MI, const TargetInstrInfo &TII) { 2019 MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode), 2020 MI->getDebugLoc(), true); 2021 MachineInstrBuilder MIB(NewMI); 2022 2023 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 2024 MachineOperand &MO = MI->getOperand(i); 2025 if (i == OpNo) { 2026 assert(MO.isReg() && "Expected to fold into reg operand!"); 2027 unsigned NumAddrOps = MOs.size(); 2028 for (unsigned i = 0; i != NumAddrOps; ++i) 2029 MIB.addOperand(MOs[i]); 2030 if (NumAddrOps < 4) // FrameIndex only 2031 addOffset(MIB, 0); 2032 } else { 2033 MIB.addOperand(MO); 2034 } 2035 } 2036 return MIB; 2037} 2038 2039static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode, 2040 const SmallVectorImpl<MachineOperand> &MOs, 2041 MachineInstr *MI) { 2042 MachineFunction &MF = *MI->getParent()->getParent(); 2043 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), TII.get(Opcode)); 2044 2045 unsigned NumAddrOps = MOs.size(); 2046 for (unsigned i = 0; i != NumAddrOps; ++i) 2047 MIB.addOperand(MOs[i]); 2048 if (NumAddrOps < 4) // FrameIndex only 2049 addOffset(MIB, 0); 2050 return MIB.addImm(0); 2051} 2052 2053MachineInstr* 2054X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF, 2055 MachineInstr *MI, unsigned i, 2056 const SmallVectorImpl<MachineOperand> &MOs) const{ 2057 const DenseMap<unsigned*, unsigned> *OpcodeTablePtr = NULL; 2058 bool isTwoAddrFold = false; 2059 unsigned NumOps = MI->getDesc().getNumOperands(); 2060 bool isTwoAddr = NumOps > 1 && 2061 MI->getDesc().getOperandConstraint(1, TOI::TIED_TO) != -1; 2062 2063 MachineInstr *NewMI = NULL; 2064 // Folding a memory location into the two-address part of a two-address 2065 // instruction is different than folding it other places. It requires 2066 // replacing the *two* registers with the memory location. 2067 if (isTwoAddr && NumOps >= 2 && i < 2 && 2068 MI->getOperand(0).isReg() && 2069 MI->getOperand(1).isReg() && 2070 MI->getOperand(0).getReg() == MI->getOperand(1).getReg()) { 2071 OpcodeTablePtr = &RegOp2MemOpTable2Addr; 2072 isTwoAddrFold = true; 2073 } else if (i == 0) { // If operand 0 2074 if (MI->getOpcode() == X86::MOV16r0) 2075 NewMI = MakeM0Inst(*this, X86::MOV16mi, MOs, MI); 2076 else if (MI->getOpcode() == X86::MOV32r0) 2077 NewMI = MakeM0Inst(*this, X86::MOV32mi, MOs, MI); 2078 else if (MI->getOpcode() == X86::MOV64r0) 2079 NewMI = MakeM0Inst(*this, X86::MOV64mi32, MOs, MI); 2080 else if (MI->getOpcode() == X86::MOV8r0) 2081 NewMI = MakeM0Inst(*this, X86::MOV8mi, MOs, MI); 2082 if (NewMI) 2083 return NewMI; 2084 2085 OpcodeTablePtr = &RegOp2MemOpTable0; 2086 } else if (i == 1) { 2087 OpcodeTablePtr = &RegOp2MemOpTable1; 2088 } else if (i == 2) { 2089 OpcodeTablePtr = &RegOp2MemOpTable2; 2090 } 2091 2092 // If table selected... 2093 if (OpcodeTablePtr) { 2094 // Find the Opcode to fuse 2095 DenseMap<unsigned*, unsigned>::iterator I = 2096 OpcodeTablePtr->find((unsigned*)MI->getOpcode()); 2097 if (I != OpcodeTablePtr->end()) { 2098 if (isTwoAddrFold) 2099 NewMI = FuseTwoAddrInst(MF, I->second, MOs, MI, *this); 2100 else 2101 NewMI = FuseInst(MF, I->second, i, MOs, MI, *this); 2102 return NewMI; 2103 } 2104 } 2105 2106 // No fusion 2107 if (PrintFailedFusing) 2108 cerr << "We failed to fuse operand " << i << " in " << *MI; 2109 return NULL; 2110} 2111 2112 2113MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF, 2114 MachineInstr *MI, 2115 const SmallVectorImpl<unsigned> &Ops, 2116 int FrameIndex) const { 2117 // Check switch flag 2118 if (NoFusing) return NULL; 2119 2120 const MachineFrameInfo *MFI = MF.getFrameInfo(); 2121 unsigned Alignment = MFI->getObjectAlignment(FrameIndex); 2122 // FIXME: Move alignment requirement into tables? 2123 if (Alignment < 16) { 2124 switch (MI->getOpcode()) { 2125 default: break; 2126 // Not always safe to fold movsd into these instructions since their load 2127 // folding variants expects the address to be 16 byte aligned. 2128 case X86::FsANDNPDrr: 2129 case X86::FsANDNPSrr: 2130 case X86::FsANDPDrr: 2131 case X86::FsANDPSrr: 2132 case X86::FsORPDrr: 2133 case X86::FsORPSrr: 2134 case X86::FsXORPDrr: 2135 case X86::FsXORPSrr: 2136 return NULL; 2137 } 2138 } 2139 2140 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) { 2141 unsigned NewOpc = 0; 2142 switch (MI->getOpcode()) { 2143 default: return NULL; 2144 case X86::TEST8rr: NewOpc = X86::CMP8ri; break; 2145 case X86::TEST16rr: NewOpc = X86::CMP16ri; break; 2146 case X86::TEST32rr: NewOpc = X86::CMP32ri; break; 2147 case X86::TEST64rr: NewOpc = X86::CMP64ri32; break; 2148 } 2149 // Change to CMPXXri r, 0 first. 2150 MI->setDesc(get(NewOpc)); 2151 MI->getOperand(1).ChangeToImmediate(0); 2152 } else if (Ops.size() != 1) 2153 return NULL; 2154 2155 SmallVector<MachineOperand,4> MOs; 2156 MOs.push_back(MachineOperand::CreateFI(FrameIndex)); 2157 return foldMemoryOperandImpl(MF, MI, Ops[0], MOs); 2158} 2159 2160MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF, 2161 MachineInstr *MI, 2162 const SmallVectorImpl<unsigned> &Ops, 2163 MachineInstr *LoadMI) const { 2164 // Check switch flag 2165 if (NoFusing) return NULL; 2166 2167 // Determine the alignment of the load. 2168 unsigned Alignment = 0; 2169 if (LoadMI->hasOneMemOperand()) 2170 Alignment = LoadMI->memoperands_begin()->getAlignment(); 2171 2172 // FIXME: Move alignment requirement into tables? 2173 if (Alignment < 16) { 2174 switch (MI->getOpcode()) { 2175 default: break; 2176 // Not always safe to fold movsd into these instructions since their load 2177 // folding variants expects the address to be 16 byte aligned. 2178 case X86::FsANDNPDrr: 2179 case X86::FsANDNPSrr: 2180 case X86::FsANDPDrr: 2181 case X86::FsANDPSrr: 2182 case X86::FsORPDrr: 2183 case X86::FsORPSrr: 2184 case X86::FsXORPDrr: 2185 case X86::FsXORPSrr: 2186 return NULL; 2187 } 2188 } 2189 2190 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) { 2191 unsigned NewOpc = 0; 2192 switch (MI->getOpcode()) { 2193 default: return NULL; 2194 case X86::TEST8rr: NewOpc = X86::CMP8ri; break; 2195 case X86::TEST16rr: NewOpc = X86::CMP16ri; break; 2196 case X86::TEST32rr: NewOpc = X86::CMP32ri; break; 2197 case X86::TEST64rr: NewOpc = X86::CMP64ri32; break; 2198 } 2199 // Change to CMPXXri r, 0 first. 2200 MI->setDesc(get(NewOpc)); 2201 MI->getOperand(1).ChangeToImmediate(0); 2202 } else if (Ops.size() != 1) 2203 return NULL; 2204 2205 SmallVector<MachineOperand,X86AddrNumOperands> MOs; 2206 if (LoadMI->getOpcode() == X86::V_SET0 || 2207 LoadMI->getOpcode() == X86::V_SETALLONES) { 2208 // Folding a V_SET0 or V_SETALLONES as a load, to ease register pressure. 2209 // Create a constant-pool entry and operands to load from it. 2210 2211 // x86-32 PIC requires a PIC base register for constant pools. 2212 unsigned PICBase = 0; 2213 if (TM.getRelocationModel() == Reloc::PIC_ && 2214 !TM.getSubtarget<X86Subtarget>().is64Bit()) 2215 // FIXME: PICBase = TM.getInstrInfo()->getGlobalBaseReg(&MF); 2216 // This doesn't work for several reasons. 2217 // 1. GlobalBaseReg may have been spilled. 2218 // 2. It may not be live at MI. 2219 return false; 2220 2221 // Create a v4i32 constant-pool entry. 2222 MachineConstantPool &MCP = *MF.getConstantPool(); 2223 const VectorType *Ty = VectorType::get(Type::Int32Ty, 4); 2224 Constant *C = LoadMI->getOpcode() == X86::V_SET0 ? 2225 ConstantVector::getNullValue(Ty) : 2226 ConstantVector::getAllOnesValue(Ty); 2227 unsigned CPI = MCP.getConstantPoolIndex(C, 16); 2228 2229 // Create operands to load from the constant pool entry. 2230 MOs.push_back(MachineOperand::CreateReg(PICBase, false)); 2231 MOs.push_back(MachineOperand::CreateImm(1)); 2232 MOs.push_back(MachineOperand::CreateReg(0, false)); 2233 MOs.push_back(MachineOperand::CreateCPI(CPI, 0)); 2234 MOs.push_back(MachineOperand::CreateReg(0, false)); 2235 } else { 2236 // Folding a normal load. Just copy the load's address operands. 2237 unsigned NumOps = LoadMI->getDesc().getNumOperands(); 2238 for (unsigned i = NumOps - X86AddrNumOperands; i != NumOps; ++i) 2239 MOs.push_back(LoadMI->getOperand(i)); 2240 } 2241 return foldMemoryOperandImpl(MF, MI, Ops[0], MOs); 2242} 2243 2244 2245bool X86InstrInfo::canFoldMemoryOperand(const MachineInstr *MI, 2246 const SmallVectorImpl<unsigned> &Ops) const { 2247 // Check switch flag 2248 if (NoFusing) return 0; 2249 2250 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) { 2251 switch (MI->getOpcode()) { 2252 default: return false; 2253 case X86::TEST8rr: 2254 case X86::TEST16rr: 2255 case X86::TEST32rr: 2256 case X86::TEST64rr: 2257 return true; 2258 } 2259 } 2260 2261 if (Ops.size() != 1) 2262 return false; 2263 2264 unsigned OpNum = Ops[0]; 2265 unsigned Opc = MI->getOpcode(); 2266 unsigned NumOps = MI->getDesc().getNumOperands(); 2267 bool isTwoAddr = NumOps > 1 && 2268 MI->getDesc().getOperandConstraint(1, TOI::TIED_TO) != -1; 2269 2270 // Folding a memory location into the two-address part of a two-address 2271 // instruction is different than folding it other places. It requires 2272 // replacing the *two* registers with the memory location. 2273 const DenseMap<unsigned*, unsigned> *OpcodeTablePtr = NULL; 2274 if (isTwoAddr && NumOps >= 2 && OpNum < 2) { 2275 OpcodeTablePtr = &RegOp2MemOpTable2Addr; 2276 } else if (OpNum == 0) { // If operand 0 2277 switch (Opc) { 2278 case X86::MOV16r0: 2279 case X86::MOV32r0: 2280 case X86::MOV64r0: 2281 case X86::MOV8r0: 2282 return true; 2283 default: break; 2284 } 2285 OpcodeTablePtr = &RegOp2MemOpTable0; 2286 } else if (OpNum == 1) { 2287 OpcodeTablePtr = &RegOp2MemOpTable1; 2288 } else if (OpNum == 2) { 2289 OpcodeTablePtr = &RegOp2MemOpTable2; 2290 } 2291 2292 if (OpcodeTablePtr) { 2293 // Find the Opcode to fuse 2294 DenseMap<unsigned*, unsigned>::iterator I = 2295 OpcodeTablePtr->find((unsigned*)Opc); 2296 if (I != OpcodeTablePtr->end()) 2297 return true; 2298 } 2299 return false; 2300} 2301 2302bool X86InstrInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, 2303 unsigned Reg, bool UnfoldLoad, bool UnfoldStore, 2304 SmallVectorImpl<MachineInstr*> &NewMIs) const { 2305 DenseMap<unsigned*, std::pair<unsigned,unsigned> >::iterator I = 2306 MemOp2RegOpTable.find((unsigned*)MI->getOpcode()); 2307 if (I == MemOp2RegOpTable.end()) 2308 return false; 2309 DebugLoc dl = MI->getDebugLoc(); 2310 unsigned Opc = I->second.first; 2311 unsigned Index = I->second.second & 0xf; 2312 bool FoldedLoad = I->second.second & (1 << 4); 2313 bool FoldedStore = I->second.second & (1 << 5); 2314 if (UnfoldLoad && !FoldedLoad) 2315 return false; 2316 UnfoldLoad &= FoldedLoad; 2317 if (UnfoldStore && !FoldedStore) 2318 return false; 2319 UnfoldStore &= FoldedStore; 2320 2321 const TargetInstrDesc &TID = get(Opc); 2322 const TargetOperandInfo &TOI = TID.OpInfo[Index]; 2323 const TargetRegisterClass *RC = TOI.isLookupPtrRegClass() 2324 ? RI.getPointerRegClass() : RI.getRegClass(TOI.RegClass); 2325 SmallVector<MachineOperand, X86AddrNumOperands> AddrOps; 2326 SmallVector<MachineOperand,2> BeforeOps; 2327 SmallVector<MachineOperand,2> AfterOps; 2328 SmallVector<MachineOperand,4> ImpOps; 2329 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 2330 MachineOperand &Op = MI->getOperand(i); 2331 if (i >= Index && i < Index + X86AddrNumOperands) 2332 AddrOps.push_back(Op); 2333 else if (Op.isReg() && Op.isImplicit()) 2334 ImpOps.push_back(Op); 2335 else if (i < Index) 2336 BeforeOps.push_back(Op); 2337 else if (i > Index) 2338 AfterOps.push_back(Op); 2339 } 2340 2341 // Emit the load instruction. 2342 if (UnfoldLoad) { 2343 loadRegFromAddr(MF, Reg, AddrOps, RC, NewMIs); 2344 if (UnfoldStore) { 2345 // Address operands cannot be marked isKill. 2346 for (unsigned i = 1; i != 1 + X86AddrNumOperands; ++i) { 2347 MachineOperand &MO = NewMIs[0]->getOperand(i); 2348 if (MO.isReg()) 2349 MO.setIsKill(false); 2350 } 2351 } 2352 } 2353 2354 // Emit the data processing instruction. 2355 MachineInstr *DataMI = MF.CreateMachineInstr(TID, MI->getDebugLoc(), true); 2356 MachineInstrBuilder MIB(DataMI); 2357 2358 if (FoldedStore) 2359 MIB.addReg(Reg, true); 2360 for (unsigned i = 0, e = BeforeOps.size(); i != e; ++i) 2361 MIB.addOperand(BeforeOps[i]); 2362 if (FoldedLoad) 2363 MIB.addReg(Reg); 2364 for (unsigned i = 0, e = AfterOps.size(); i != e; ++i) 2365 MIB.addOperand(AfterOps[i]); 2366 for (unsigned i = 0, e = ImpOps.size(); i != e; ++i) { 2367 MachineOperand &MO = ImpOps[i]; 2368 MIB.addReg(MO.getReg(), MO.isDef(), true, MO.isKill(), MO.isDead()); 2369 } 2370 // Change CMP32ri r, 0 back to TEST32rr r, r, etc. 2371 unsigned NewOpc = 0; 2372 switch (DataMI->getOpcode()) { 2373 default: break; 2374 case X86::CMP64ri32: 2375 case X86::CMP32ri: 2376 case X86::CMP16ri: 2377 case X86::CMP8ri: { 2378 MachineOperand &MO0 = DataMI->getOperand(0); 2379 MachineOperand &MO1 = DataMI->getOperand(1); 2380 if (MO1.getImm() == 0) { 2381 switch (DataMI->getOpcode()) { 2382 default: break; 2383 case X86::CMP64ri32: NewOpc = X86::TEST64rr; break; 2384 case X86::CMP32ri: NewOpc = X86::TEST32rr; break; 2385 case X86::CMP16ri: NewOpc = X86::TEST16rr; break; 2386 case X86::CMP8ri: NewOpc = X86::TEST8rr; break; 2387 } 2388 DataMI->setDesc(get(NewOpc)); 2389 MO1.ChangeToRegister(MO0.getReg(), false); 2390 } 2391 } 2392 } 2393 NewMIs.push_back(DataMI); 2394 2395 // Emit the store instruction. 2396 if (UnfoldStore) { 2397 const TargetOperandInfo &DstTOI = TID.OpInfo[0]; 2398 const TargetRegisterClass *DstRC = DstTOI.isLookupPtrRegClass() 2399 ? RI.getPointerRegClass() : RI.getRegClass(DstTOI.RegClass); 2400 storeRegToAddr(MF, Reg, true, AddrOps, DstRC, NewMIs); 2401 } 2402 2403 return true; 2404} 2405 2406bool 2407X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, 2408 SmallVectorImpl<SDNode*> &NewNodes) const { 2409 if (!N->isMachineOpcode()) 2410 return false; 2411 2412 DenseMap<unsigned*, std::pair<unsigned,unsigned> >::iterator I = 2413 MemOp2RegOpTable.find((unsigned*)N->getMachineOpcode()); 2414 if (I == MemOp2RegOpTable.end()) 2415 return false; 2416 unsigned Opc = I->second.first; 2417 unsigned Index = I->second.second & 0xf; 2418 bool FoldedLoad = I->second.second & (1 << 4); 2419 bool FoldedStore = I->second.second & (1 << 5); 2420 const TargetInstrDesc &TID = get(Opc); 2421 const TargetOperandInfo &TOI = TID.OpInfo[Index]; 2422 const TargetRegisterClass *RC = TOI.isLookupPtrRegClass() 2423 ? RI.getPointerRegClass() : RI.getRegClass(TOI.RegClass); 2424 unsigned NumDefs = TID.NumDefs; 2425 std::vector<SDValue> AddrOps; 2426 std::vector<SDValue> BeforeOps; 2427 std::vector<SDValue> AfterOps; 2428 DebugLoc dl = N->getDebugLoc(); 2429 unsigned NumOps = N->getNumOperands(); 2430 for (unsigned i = 0; i != NumOps-1; ++i) { 2431 SDValue Op = N->getOperand(i); 2432 if (i >= Index-NumDefs && i < Index-NumDefs + X86AddrNumOperands) 2433 AddrOps.push_back(Op); 2434 else if (i < Index-NumDefs) 2435 BeforeOps.push_back(Op); 2436 else if (i > Index-NumDefs) 2437 AfterOps.push_back(Op); 2438 } 2439 SDValue Chain = N->getOperand(NumOps-1); 2440 AddrOps.push_back(Chain); 2441 2442 // Emit the load instruction. 2443 SDNode *Load = 0; 2444 const MachineFunction &MF = DAG.getMachineFunction(); 2445 if (FoldedLoad) { 2446 MVT VT = *RC->vt_begin(); 2447 bool isAligned = (RI.getStackAlignment() >= 16) || 2448 RI.needsStackRealignment(MF); 2449 Load = DAG.getTargetNode(getLoadRegOpcode(RC, isAligned), dl, 2450 VT, MVT::Other, 2451 &AddrOps[0], AddrOps.size()); 2452 NewNodes.push_back(Load); 2453 } 2454 2455 // Emit the data processing instruction. 2456 std::vector<MVT> VTs; 2457 const TargetRegisterClass *DstRC = 0; 2458 if (TID.getNumDefs() > 0) { 2459 const TargetOperandInfo &DstTOI = TID.OpInfo[0]; 2460 DstRC = DstTOI.isLookupPtrRegClass() 2461 ? RI.getPointerRegClass() : RI.getRegClass(DstTOI.RegClass); 2462 VTs.push_back(*DstRC->vt_begin()); 2463 } 2464 for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) { 2465 MVT VT = N->getValueType(i); 2466 if (VT != MVT::Other && i >= (unsigned)TID.getNumDefs()) 2467 VTs.push_back(VT); 2468 } 2469 if (Load) 2470 BeforeOps.push_back(SDValue(Load, 0)); 2471 std::copy(AfterOps.begin(), AfterOps.end(), std::back_inserter(BeforeOps)); 2472 SDNode *NewNode= DAG.getTargetNode(Opc, dl, VTs, &BeforeOps[0], 2473 BeforeOps.size()); 2474 NewNodes.push_back(NewNode); 2475 2476 // Emit the store instruction. 2477 if (FoldedStore) { 2478 AddrOps.pop_back(); 2479 AddrOps.push_back(SDValue(NewNode, 0)); 2480 AddrOps.push_back(Chain); 2481 bool isAligned = (RI.getStackAlignment() >= 16) || 2482 RI.needsStackRealignment(MF); 2483 SDNode *Store = DAG.getTargetNode(getStoreRegOpcode(DstRC, isAligned), dl, 2484 MVT::Other, &AddrOps[0], AddrOps.size()); 2485 NewNodes.push_back(Store); 2486 } 2487 2488 return true; 2489} 2490 2491unsigned X86InstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc, 2492 bool UnfoldLoad, bool UnfoldStore) const { 2493 DenseMap<unsigned*, std::pair<unsigned,unsigned> >::iterator I = 2494 MemOp2RegOpTable.find((unsigned*)Opc); 2495 if (I == MemOp2RegOpTable.end()) 2496 return 0; 2497 bool FoldedLoad = I->second.second & (1 << 4); 2498 bool FoldedStore = I->second.second & (1 << 5); 2499 if (UnfoldLoad && !FoldedLoad) 2500 return 0; 2501 if (UnfoldStore && !FoldedStore) 2502 return 0; 2503 return I->second.first; 2504} 2505 2506bool X86InstrInfo::BlockHasNoFallThrough(const MachineBasicBlock &MBB) const { 2507 if (MBB.empty()) return false; 2508 2509 switch (MBB.back().getOpcode()) { 2510 case X86::TCRETURNri: 2511 case X86::TCRETURNdi: 2512 case X86::RET: // Return. 2513 case X86::RETI: 2514 case X86::TAILJMPd: 2515 case X86::TAILJMPr: 2516 case X86::TAILJMPm: 2517 case X86::JMP: // Uncond branch. 2518 case X86::JMP32r: // Indirect branch. 2519 case X86::JMP64r: // Indirect branch (64-bit). 2520 case X86::JMP32m: // Indirect branch through mem. 2521 case X86::JMP64m: // Indirect branch through mem (64-bit). 2522 return true; 2523 default: return false; 2524 } 2525} 2526 2527bool X86InstrInfo:: 2528ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { 2529 assert(Cond.size() == 1 && "Invalid X86 branch condition!"); 2530 X86::CondCode CC = static_cast<X86::CondCode>(Cond[0].getImm()); 2531 if (CC == X86::COND_NE_OR_P || CC == X86::COND_NP_OR_E) 2532 return true; 2533 Cond[0].setImm(GetOppositeBranchCondition(CC)); 2534 return false; 2535} 2536 2537bool X86InstrInfo:: 2538isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const { 2539 // FIXME: Return false for x87 stack register classes for now. We can't 2540 // allow any loads of these registers before FpGet_ST0_80. 2541 return !(RC == &X86::CCRRegClass || RC == &X86::RFP32RegClass || 2542 RC == &X86::RFP64RegClass || RC == &X86::RFP80RegClass); 2543} 2544 2545unsigned X86InstrInfo::sizeOfImm(const TargetInstrDesc *Desc) { 2546 switch (Desc->TSFlags & X86II::ImmMask) { 2547 case X86II::Imm8: return 1; 2548 case X86II::Imm16: return 2; 2549 case X86II::Imm32: return 4; 2550 case X86II::Imm64: return 8; 2551 default: assert(0 && "Immediate size not set!"); 2552 return 0; 2553 } 2554} 2555 2556/// isX86_64ExtendedReg - Is the MachineOperand a x86-64 extended register? 2557/// e.g. r8, xmm8, etc. 2558bool X86InstrInfo::isX86_64ExtendedReg(const MachineOperand &MO) { 2559 if (!MO.isReg()) return false; 2560 switch (MO.getReg()) { 2561 default: break; 2562 case X86::R8: case X86::R9: case X86::R10: case X86::R11: 2563 case X86::R12: case X86::R13: case X86::R14: case X86::R15: 2564 case X86::R8D: case X86::R9D: case X86::R10D: case X86::R11D: 2565 case X86::R12D: case X86::R13D: case X86::R14D: case X86::R15D: 2566 case X86::R8W: case X86::R9W: case X86::R10W: case X86::R11W: 2567 case X86::R12W: case X86::R13W: case X86::R14W: case X86::R15W: 2568 case X86::R8B: case X86::R9B: case X86::R10B: case X86::R11B: 2569 case X86::R12B: case X86::R13B: case X86::R14B: case X86::R15B: 2570 case X86::XMM8: case X86::XMM9: case X86::XMM10: case X86::XMM11: 2571 case X86::XMM12: case X86::XMM13: case X86::XMM14: case X86::XMM15: 2572 return true; 2573 } 2574 return false; 2575} 2576 2577 2578/// determineREX - Determine if the MachineInstr has to be encoded with a X86-64 2579/// REX prefix which specifies 1) 64-bit instructions, 2) non-default operand 2580/// size, and 3) use of X86-64 extended registers. 2581unsigned X86InstrInfo::determineREX(const MachineInstr &MI) { 2582 unsigned REX = 0; 2583 const TargetInstrDesc &Desc = MI.getDesc(); 2584 2585 // Pseudo instructions do not need REX prefix byte. 2586 if ((Desc.TSFlags & X86II::FormMask) == X86II::Pseudo) 2587 return 0; 2588 if (Desc.TSFlags & X86II::REX_W) 2589 REX |= 1 << 3; 2590 2591 unsigned NumOps = Desc.getNumOperands(); 2592 if (NumOps) { 2593 bool isTwoAddr = NumOps > 1 && 2594 Desc.getOperandConstraint(1, TOI::TIED_TO) != -1; 2595 2596 // If it accesses SPL, BPL, SIL, or DIL, then it requires a 0x40 REX prefix. 2597 unsigned i = isTwoAddr ? 1 : 0; 2598 for (unsigned e = NumOps; i != e; ++i) { 2599 const MachineOperand& MO = MI.getOperand(i); 2600 if (MO.isReg()) { 2601 unsigned Reg = MO.getReg(); 2602 if (isX86_64NonExtLowByteReg(Reg)) 2603 REX |= 0x40; 2604 } 2605 } 2606 2607 switch (Desc.TSFlags & X86II::FormMask) { 2608 case X86II::MRMInitReg: 2609 if (isX86_64ExtendedReg(MI.getOperand(0))) 2610 REX |= (1 << 0) | (1 << 2); 2611 break; 2612 case X86II::MRMSrcReg: { 2613 if (isX86_64ExtendedReg(MI.getOperand(0))) 2614 REX |= 1 << 2; 2615 i = isTwoAddr ? 2 : 1; 2616 for (unsigned e = NumOps; i != e; ++i) { 2617 const MachineOperand& MO = MI.getOperand(i); 2618 if (isX86_64ExtendedReg(MO)) 2619 REX |= 1 << 0; 2620 } 2621 break; 2622 } 2623 case X86II::MRMSrcMem: { 2624 if (isX86_64ExtendedReg(MI.getOperand(0))) 2625 REX |= 1 << 2; 2626 unsigned Bit = 0; 2627 i = isTwoAddr ? 2 : 1; 2628 for (; i != NumOps; ++i) { 2629 const MachineOperand& MO = MI.getOperand(i); 2630 if (MO.isReg()) { 2631 if (isX86_64ExtendedReg(MO)) 2632 REX |= 1 << Bit; 2633 Bit++; 2634 } 2635 } 2636 break; 2637 } 2638 case X86II::MRM0m: case X86II::MRM1m: 2639 case X86II::MRM2m: case X86II::MRM3m: 2640 case X86II::MRM4m: case X86II::MRM5m: 2641 case X86II::MRM6m: case X86II::MRM7m: 2642 case X86II::MRMDestMem: { 2643 unsigned e = (isTwoAddr ? X86AddrNumOperands+1 : X86AddrNumOperands); 2644 i = isTwoAddr ? 1 : 0; 2645 if (NumOps > e && isX86_64ExtendedReg(MI.getOperand(e))) 2646 REX |= 1 << 2; 2647 unsigned Bit = 0; 2648 for (; i != e; ++i) { 2649 const MachineOperand& MO = MI.getOperand(i); 2650 if (MO.isReg()) { 2651 if (isX86_64ExtendedReg(MO)) 2652 REX |= 1 << Bit; 2653 Bit++; 2654 } 2655 } 2656 break; 2657 } 2658 default: { 2659 if (isX86_64ExtendedReg(MI.getOperand(0))) 2660 REX |= 1 << 0; 2661 i = isTwoAddr ? 2 : 1; 2662 for (unsigned e = NumOps; i != e; ++i) { 2663 const MachineOperand& MO = MI.getOperand(i); 2664 if (isX86_64ExtendedReg(MO)) 2665 REX |= 1 << 2; 2666 } 2667 break; 2668 } 2669 } 2670 } 2671 return REX; 2672} 2673 2674/// sizePCRelativeBlockAddress - This method returns the size of a PC 2675/// relative block address instruction 2676/// 2677static unsigned sizePCRelativeBlockAddress() { 2678 return 4; 2679} 2680 2681/// sizeGlobalAddress - Give the size of the emission of this global address 2682/// 2683static unsigned sizeGlobalAddress(bool dword) { 2684 return dword ? 8 : 4; 2685} 2686 2687/// sizeConstPoolAddress - Give the size of the emission of this constant 2688/// pool address 2689/// 2690static unsigned sizeConstPoolAddress(bool dword) { 2691 return dword ? 8 : 4; 2692} 2693 2694/// sizeExternalSymbolAddress - Give the size of the emission of this external 2695/// symbol 2696/// 2697static unsigned sizeExternalSymbolAddress(bool dword) { 2698 return dword ? 8 : 4; 2699} 2700 2701/// sizeJumpTableAddress - Give the size of the emission of this jump 2702/// table address 2703/// 2704static unsigned sizeJumpTableAddress(bool dword) { 2705 return dword ? 8 : 4; 2706} 2707 2708static unsigned sizeConstant(unsigned Size) { 2709 return Size; 2710} 2711 2712static unsigned sizeRegModRMByte(){ 2713 return 1; 2714} 2715 2716static unsigned sizeSIBByte(){ 2717 return 1; 2718} 2719 2720static unsigned getDisplacementFieldSize(const MachineOperand *RelocOp) { 2721 unsigned FinalSize = 0; 2722 // If this is a simple integer displacement that doesn't require a relocation. 2723 if (!RelocOp) { 2724 FinalSize += sizeConstant(4); 2725 return FinalSize; 2726 } 2727 2728 // Otherwise, this is something that requires a relocation. 2729 if (RelocOp->isGlobal()) { 2730 FinalSize += sizeGlobalAddress(false); 2731 } else if (RelocOp->isCPI()) { 2732 FinalSize += sizeConstPoolAddress(false); 2733 } else if (RelocOp->isJTI()) { 2734 FinalSize += sizeJumpTableAddress(false); 2735 } else { 2736 assert(0 && "Unknown value to relocate!"); 2737 } 2738 return FinalSize; 2739} 2740 2741static unsigned getMemModRMByteSize(const MachineInstr &MI, unsigned Op, 2742 bool IsPIC, bool Is64BitMode) { 2743 const MachineOperand &Op3 = MI.getOperand(Op+3); 2744 int DispVal = 0; 2745 const MachineOperand *DispForReloc = 0; 2746 unsigned FinalSize = 0; 2747 2748 // Figure out what sort of displacement we have to handle here. 2749 if (Op3.isGlobal()) { 2750 DispForReloc = &Op3; 2751 } else if (Op3.isCPI()) { 2752 if (Is64BitMode || IsPIC) { 2753 DispForReloc = &Op3; 2754 } else { 2755 DispVal = 1; 2756 } 2757 } else if (Op3.isJTI()) { 2758 if (Is64BitMode || IsPIC) { 2759 DispForReloc = &Op3; 2760 } else { 2761 DispVal = 1; 2762 } 2763 } else { 2764 DispVal = 1; 2765 } 2766 2767 const MachineOperand &Base = MI.getOperand(Op); 2768 const MachineOperand &IndexReg = MI.getOperand(Op+2); 2769 2770 unsigned BaseReg = Base.getReg(); 2771 2772 // Is a SIB byte needed? 2773 if ((!Is64BitMode || DispForReloc) && IndexReg.getReg() == 0 && 2774 (BaseReg == 0 || X86RegisterInfo::getX86RegNum(BaseReg) != N86::ESP)) { 2775 if (BaseReg == 0) { // Just a displacement? 2776 // Emit special case [disp32] encoding 2777 ++FinalSize; 2778 FinalSize += getDisplacementFieldSize(DispForReloc); 2779 } else { 2780 unsigned BaseRegNo = X86RegisterInfo::getX86RegNum(BaseReg); 2781 if (!DispForReloc && DispVal == 0 && BaseRegNo != N86::EBP) { 2782 // Emit simple indirect register encoding... [EAX] f.e. 2783 ++FinalSize; 2784 // Be pessimistic and assume it's a disp32, not a disp8 2785 } else { 2786 // Emit the most general non-SIB encoding: [REG+disp32] 2787 ++FinalSize; 2788 FinalSize += getDisplacementFieldSize(DispForReloc); 2789 } 2790 } 2791 2792 } else { // We need a SIB byte, so start by outputting the ModR/M byte first 2793 assert(IndexReg.getReg() != X86::ESP && 2794 IndexReg.getReg() != X86::RSP && "Cannot use ESP as index reg!"); 2795 2796 bool ForceDisp32 = false; 2797 if (BaseReg == 0 || DispForReloc) { 2798 // Emit the normal disp32 encoding. 2799 ++FinalSize; 2800 ForceDisp32 = true; 2801 } else { 2802 ++FinalSize; 2803 } 2804 2805 FinalSize += sizeSIBByte(); 2806 2807 // Do we need to output a displacement? 2808 if (DispVal != 0 || ForceDisp32) { 2809 FinalSize += getDisplacementFieldSize(DispForReloc); 2810 } 2811 } 2812 return FinalSize; 2813} 2814 2815 2816static unsigned GetInstSizeWithDesc(const MachineInstr &MI, 2817 const TargetInstrDesc *Desc, 2818 bool IsPIC, bool Is64BitMode) { 2819 2820 unsigned Opcode = Desc->Opcode; 2821 unsigned FinalSize = 0; 2822 2823 // Emit the lock opcode prefix as needed. 2824 if (Desc->TSFlags & X86II::LOCK) ++FinalSize; 2825 2826 // Emit segment overrid opcode prefix as needed. 2827 switch (Desc->TSFlags & X86II::SegOvrMask) { 2828 case X86II::FS: 2829 case X86II::GS: 2830 ++FinalSize; 2831 break; 2832 default: assert(0 && "Invalid segment!"); 2833 case 0: break; // No segment override! 2834 } 2835 2836 // Emit the repeat opcode prefix as needed. 2837 if ((Desc->TSFlags & X86II::Op0Mask) == X86II::REP) ++FinalSize; 2838 2839 // Emit the operand size opcode prefix as needed. 2840 if (Desc->TSFlags & X86II::OpSize) ++FinalSize; 2841 2842 // Emit the address size opcode prefix as needed. 2843 if (Desc->TSFlags & X86II::AdSize) ++FinalSize; 2844 2845 bool Need0FPrefix = false; 2846 switch (Desc->TSFlags & X86II::Op0Mask) { 2847 case X86II::TB: // Two-byte opcode prefix 2848 case X86II::T8: // 0F 38 2849 case X86II::TA: // 0F 3A 2850 Need0FPrefix = true; 2851 break; 2852 case X86II::REP: break; // already handled. 2853 case X86II::XS: // F3 0F 2854 ++FinalSize; 2855 Need0FPrefix = true; 2856 break; 2857 case X86II::XD: // F2 0F 2858 ++FinalSize; 2859 Need0FPrefix = true; 2860 break; 2861 case X86II::D8: case X86II::D9: case X86II::DA: case X86II::DB: 2862 case X86II::DC: case X86II::DD: case X86II::DE: case X86II::DF: 2863 ++FinalSize; 2864 break; // Two-byte opcode prefix 2865 default: assert(0 && "Invalid prefix!"); 2866 case 0: break; // No prefix! 2867 } 2868 2869 if (Is64BitMode) { 2870 // REX prefix 2871 unsigned REX = X86InstrInfo::determineREX(MI); 2872 if (REX) 2873 ++FinalSize; 2874 } 2875 2876 // 0x0F escape code must be emitted just before the opcode. 2877 if (Need0FPrefix) 2878 ++FinalSize; 2879 2880 switch (Desc->TSFlags & X86II::Op0Mask) { 2881 case X86II::T8: // 0F 38 2882 ++FinalSize; 2883 break; 2884 case X86II::TA: // 0F 3A 2885 ++FinalSize; 2886 break; 2887 } 2888 2889 // If this is a two-address instruction, skip one of the register operands. 2890 unsigned NumOps = Desc->getNumOperands(); 2891 unsigned CurOp = 0; 2892 if (NumOps > 1 && Desc->getOperandConstraint(1, TOI::TIED_TO) != -1) 2893 CurOp++; 2894 2895 switch (Desc->TSFlags & X86II::FormMask) { 2896 default: assert(0 && "Unknown FormMask value in X86 MachineCodeEmitter!"); 2897 case X86II::Pseudo: 2898 // Remember the current PC offset, this is the PIC relocation 2899 // base address. 2900 switch (Opcode) { 2901 default: 2902 break; 2903 case TargetInstrInfo::INLINEASM: { 2904 const MachineFunction *MF = MI.getParent()->getParent(); 2905 const char *AsmStr = MI.getOperand(0).getSymbolName(); 2906 const TargetAsmInfo* AI = MF->getTarget().getTargetAsmInfo(); 2907 FinalSize += AI->getInlineAsmLength(AsmStr); 2908 break; 2909 } 2910 case TargetInstrInfo::DBG_LABEL: 2911 case TargetInstrInfo::EH_LABEL: 2912 break; 2913 case TargetInstrInfo::IMPLICIT_DEF: 2914 case TargetInstrInfo::DECLARE: 2915 case X86::DWARF_LOC: 2916 case X86::FP_REG_KILL: 2917 break; 2918 case X86::MOVPC32r: { 2919 // This emits the "call" portion of this pseudo instruction. 2920 ++FinalSize; 2921 FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc)); 2922 break; 2923 } 2924 } 2925 CurOp = NumOps; 2926 break; 2927 case X86II::RawFrm: 2928 ++FinalSize; 2929 2930 if (CurOp != NumOps) { 2931 const MachineOperand &MO = MI.getOperand(CurOp++); 2932 if (MO.isMBB()) { 2933 FinalSize += sizePCRelativeBlockAddress(); 2934 } else if (MO.isGlobal()) { 2935 FinalSize += sizeGlobalAddress(false); 2936 } else if (MO.isSymbol()) { 2937 FinalSize += sizeExternalSymbolAddress(false); 2938 } else if (MO.isImm()) { 2939 FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc)); 2940 } else { 2941 assert(0 && "Unknown RawFrm operand!"); 2942 } 2943 } 2944 break; 2945 2946 case X86II::AddRegFrm: 2947 ++FinalSize; 2948 ++CurOp; 2949 2950 if (CurOp != NumOps) { 2951 const MachineOperand &MO1 = MI.getOperand(CurOp++); 2952 unsigned Size = X86InstrInfo::sizeOfImm(Desc); 2953 if (MO1.isImm()) 2954 FinalSize += sizeConstant(Size); 2955 else { 2956 bool dword = false; 2957 if (Opcode == X86::MOV64ri) 2958 dword = true; 2959 if (MO1.isGlobal()) { 2960 FinalSize += sizeGlobalAddress(dword); 2961 } else if (MO1.isSymbol()) 2962 FinalSize += sizeExternalSymbolAddress(dword); 2963 else if (MO1.isCPI()) 2964 FinalSize += sizeConstPoolAddress(dword); 2965 else if (MO1.isJTI()) 2966 FinalSize += sizeJumpTableAddress(dword); 2967 } 2968 } 2969 break; 2970 2971 case X86II::MRMDestReg: { 2972 ++FinalSize; 2973 FinalSize += sizeRegModRMByte(); 2974 CurOp += 2; 2975 if (CurOp != NumOps) { 2976 ++CurOp; 2977 FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc)); 2978 } 2979 break; 2980 } 2981 case X86II::MRMDestMem: { 2982 ++FinalSize; 2983 FinalSize += getMemModRMByteSize(MI, CurOp, IsPIC, Is64BitMode); 2984 CurOp += 5; 2985 if (CurOp != NumOps) { 2986 ++CurOp; 2987 FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc)); 2988 } 2989 break; 2990 } 2991 2992 case X86II::MRMSrcReg: 2993 ++FinalSize; 2994 FinalSize += sizeRegModRMByte(); 2995 CurOp += 2; 2996 if (CurOp != NumOps) { 2997 ++CurOp; 2998 FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc)); 2999 } 3000 break; 3001 3002 case X86II::MRMSrcMem: { 3003 3004 ++FinalSize; 3005 FinalSize += getMemModRMByteSize(MI, CurOp+1, IsPIC, Is64BitMode); 3006 CurOp += 5; 3007 if (CurOp != NumOps) { 3008 ++CurOp; 3009 FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc)); 3010 } 3011 break; 3012 } 3013 3014 case X86II::MRM0r: case X86II::MRM1r: 3015 case X86II::MRM2r: case X86II::MRM3r: 3016 case X86II::MRM4r: case X86II::MRM5r: 3017 case X86II::MRM6r: case X86II::MRM7r: 3018 ++FinalSize; 3019 ++CurOp; 3020 FinalSize += sizeRegModRMByte(); 3021 3022 if (CurOp != NumOps) { 3023 const MachineOperand &MO1 = MI.getOperand(CurOp++); 3024 unsigned Size = X86InstrInfo::sizeOfImm(Desc); 3025 if (MO1.isImm()) 3026 FinalSize += sizeConstant(Size); 3027 else { 3028 bool dword = false; 3029 if (Opcode == X86::MOV64ri32) 3030 dword = true; 3031 if (MO1.isGlobal()) { 3032 FinalSize += sizeGlobalAddress(dword); 3033 } else if (MO1.isSymbol()) 3034 FinalSize += sizeExternalSymbolAddress(dword); 3035 else if (MO1.isCPI()) 3036 FinalSize += sizeConstPoolAddress(dword); 3037 else if (MO1.isJTI()) 3038 FinalSize += sizeJumpTableAddress(dword); 3039 } 3040 } 3041 break; 3042 3043 case X86II::MRM0m: case X86II::MRM1m: 3044 case X86II::MRM2m: case X86II::MRM3m: 3045 case X86II::MRM4m: case X86II::MRM5m: 3046 case X86II::MRM6m: case X86II::MRM7m: { 3047 3048 ++FinalSize; 3049 FinalSize += getMemModRMByteSize(MI, CurOp, IsPIC, Is64BitMode); 3050 CurOp += 4; 3051 3052 if (CurOp != NumOps) { 3053 const MachineOperand &MO = MI.getOperand(CurOp++); 3054 unsigned Size = X86InstrInfo::sizeOfImm(Desc); 3055 if (MO.isImm()) 3056 FinalSize += sizeConstant(Size); 3057 else { 3058 bool dword = false; 3059 if (Opcode == X86::MOV64mi32) 3060 dword = true; 3061 if (MO.isGlobal()) { 3062 FinalSize += sizeGlobalAddress(dword); 3063 } else if (MO.isSymbol()) 3064 FinalSize += sizeExternalSymbolAddress(dword); 3065 else if (MO.isCPI()) 3066 FinalSize += sizeConstPoolAddress(dword); 3067 else if (MO.isJTI()) 3068 FinalSize += sizeJumpTableAddress(dword); 3069 } 3070 } 3071 break; 3072 } 3073 3074 case X86II::MRMInitReg: 3075 ++FinalSize; 3076 // Duplicate register, used by things like MOV8r0 (aka xor reg,reg). 3077 FinalSize += sizeRegModRMByte(); 3078 ++CurOp; 3079 break; 3080 } 3081 3082 if (!Desc->isVariadic() && CurOp != NumOps) { 3083 cerr << "Cannot determine size: "; 3084 MI.dump(); 3085 cerr << '\n'; 3086 abort(); 3087 } 3088 3089 3090 return FinalSize; 3091} 3092 3093 3094unsigned X86InstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const { 3095 const TargetInstrDesc &Desc = MI->getDesc(); 3096 bool IsPIC = (TM.getRelocationModel() == Reloc::PIC_); 3097 bool Is64BitMode = TM.getSubtargetImpl()->is64Bit(); 3098 unsigned Size = GetInstSizeWithDesc(*MI, &Desc, IsPIC, Is64BitMode); 3099 if (Desc.getOpcode() == X86::MOVPC32r) { 3100 Size += GetInstSizeWithDesc(*MI, &get(X86::POP32r), IsPIC, Is64BitMode); 3101 } 3102 return Size; 3103} 3104 3105/// getGlobalBaseReg - Return a virtual register initialized with the 3106/// the global base register value. Output instructions required to 3107/// initialize the register in the function entry block, if necessary. 3108/// 3109unsigned X86InstrInfo::getGlobalBaseReg(MachineFunction *MF) const { 3110 assert(!TM.getSubtarget<X86Subtarget>().is64Bit() && 3111 "X86-64 PIC uses RIP relative addressing"); 3112 3113 X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>(); 3114 unsigned GlobalBaseReg = X86FI->getGlobalBaseReg(); 3115 if (GlobalBaseReg != 0) 3116 return GlobalBaseReg; 3117 3118 // Insert the set of GlobalBaseReg into the first MBB of the function 3119 MachineBasicBlock &FirstMBB = MF->front(); 3120 MachineBasicBlock::iterator MBBI = FirstMBB.begin(); 3121 DebugLoc DL = DebugLoc::getUnknownLoc(); 3122 if (MBBI != FirstMBB.end()) DL = MBBI->getDebugLoc(); 3123 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 3124 unsigned PC = RegInfo.createVirtualRegister(X86::GR32RegisterClass); 3125 3126 const TargetInstrInfo *TII = TM.getInstrInfo(); 3127 // Operand of MovePCtoStack is completely ignored by asm printer. It's 3128 // only used in JIT code emission as displacement to pc. 3129 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOVPC32r), PC) 3130 .addImm(0); 3131 3132 // If we're using vanilla 'GOT' PIC style, we should use relative addressing 3133 // not to pc, but to _GLOBAL_ADDRESS_TABLE_ external 3134 if (TM.getRelocationModel() == Reloc::PIC_ && 3135 TM.getSubtarget<X86Subtarget>().isPICStyleGOT()) { 3136 GlobalBaseReg = 3137 RegInfo.createVirtualRegister(X86::GR32RegisterClass); 3138 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD32ri), GlobalBaseReg) 3139 .addReg(PC).addExternalSymbol("_GLOBAL_OFFSET_TABLE_"); 3140 } else { 3141 GlobalBaseReg = PC; 3142 } 3143 3144 X86FI->setGlobalBaseReg(GlobalBaseReg); 3145 return GlobalBaseReg; 3146} 3147