X86InstrInfo.cpp revision f9b2dc66c87256b55f9bdfe037d1fa6f705200e8
1//===- X86InstrInfo.cpp - X86 Instruction Information -----------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the X86 implementation of the TargetInstrInfo class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "X86InstrInfo.h" 15#include "X86.h" 16#include "X86GenInstrInfo.inc" 17#include "X86InstrBuilder.h" 18#include "X86MachineFunctionInfo.h" 19#include "X86Subtarget.h" 20#include "X86TargetMachine.h" 21#include "llvm/DerivedTypes.h" 22#include "llvm/LLVMContext.h" 23#include "llvm/ADT/STLExtras.h" 24#include "llvm/CodeGen/MachineConstantPool.h" 25#include "llvm/CodeGen/MachineFrameInfo.h" 26#include "llvm/CodeGen/MachineInstrBuilder.h" 27#include "llvm/CodeGen/MachineRegisterInfo.h" 28#include "llvm/CodeGen/LiveVariables.h" 29#include "llvm/CodeGen/PseudoSourceValue.h" 30#include "llvm/MC/MCInst.h" 31#include "llvm/Support/CommandLine.h" 32#include "llvm/Support/Debug.h" 33#include "llvm/Support/ErrorHandling.h" 34#include "llvm/Support/raw_ostream.h" 35#include "llvm/Target/TargetOptions.h" 36#include "llvm/MC/MCAsmInfo.h" 37#include <limits> 38 39using namespace llvm; 40 41static cl::opt<bool> 42NoFusing("disable-spill-fusing", 43 cl::desc("Disable fusing of spill code into instructions")); 44static cl::opt<bool> 45PrintFailedFusing("print-failed-fuse-candidates", 46 cl::desc("Print instructions that the allocator wants to" 47 " fuse, but the X86 backend currently can't"), 48 cl::Hidden); 49static cl::opt<bool> 50ReMatPICStubLoad("remat-pic-stub-load", 51 cl::desc("Re-materialize load from stub in PIC mode"), 52 cl::init(false), cl::Hidden); 53 54X86InstrInfo::X86InstrInfo(X86TargetMachine &tm) 55 : TargetInstrInfoImpl(X86Insts, array_lengthof(X86Insts)), 56 TM(tm), RI(tm, *this) { 57 enum { 58 TB_NOT_REVERSABLE = 1U << 31, 59 TB_FLAGS = TB_NOT_REVERSABLE 60 }; 61 62 static const unsigned OpTbl2Addr[][2] = { 63 { X86::ADC32ri, X86::ADC32mi }, 64 { X86::ADC32ri8, X86::ADC32mi8 }, 65 { X86::ADC32rr, X86::ADC32mr }, 66 { X86::ADC64ri32, X86::ADC64mi32 }, 67 { X86::ADC64ri8, X86::ADC64mi8 }, 68 { X86::ADC64rr, X86::ADC64mr }, 69 { X86::ADD16ri, X86::ADD16mi }, 70 { X86::ADD16ri8, X86::ADD16mi8 }, 71 { X86::ADD16ri_DB, X86::ADD16mi | TB_NOT_REVERSABLE }, 72 { X86::ADD16ri8_DB, X86::ADD16mi8 | TB_NOT_REVERSABLE }, 73 { X86::ADD16rr, X86::ADD16mr }, 74 { X86::ADD16rr_DB, X86::ADD16mr | TB_NOT_REVERSABLE }, 75 { X86::ADD32ri, X86::ADD32mi }, 76 { X86::ADD32ri8, X86::ADD32mi8 }, 77 { X86::ADD32ri_DB, X86::ADD32mi | TB_NOT_REVERSABLE }, 78 { X86::ADD32ri8_DB, X86::ADD32mi8 | TB_NOT_REVERSABLE }, 79 { X86::ADD32rr, X86::ADD32mr }, 80 { X86::ADD32rr_DB, X86::ADD32mr | TB_NOT_REVERSABLE }, 81 { X86::ADD64ri32, X86::ADD64mi32 }, 82 { X86::ADD64ri8, X86::ADD64mi8 }, 83 { X86::ADD64ri32_DB,X86::ADD64mi32 | TB_NOT_REVERSABLE }, 84 { X86::ADD64ri8_DB, X86::ADD64mi8 | TB_NOT_REVERSABLE }, 85 { X86::ADD64rr, X86::ADD64mr }, 86 { X86::ADD64rr_DB, X86::ADD64mr | TB_NOT_REVERSABLE }, 87 { X86::ADD8ri, X86::ADD8mi }, 88 { X86::ADD8rr, X86::ADD8mr }, 89 { X86::AND16ri, X86::AND16mi }, 90 { X86::AND16ri8, X86::AND16mi8 }, 91 { X86::AND16rr, X86::AND16mr }, 92 { X86::AND32ri, X86::AND32mi }, 93 { X86::AND32ri8, X86::AND32mi8 }, 94 { X86::AND32rr, X86::AND32mr }, 95 { X86::AND64ri32, X86::AND64mi32 }, 96 { X86::AND64ri8, X86::AND64mi8 }, 97 { X86::AND64rr, X86::AND64mr }, 98 { X86::AND8ri, X86::AND8mi }, 99 { X86::AND8rr, X86::AND8mr }, 100 { X86::DEC16r, X86::DEC16m }, 101 { X86::DEC32r, X86::DEC32m }, 102 { X86::DEC64_16r, X86::DEC64_16m }, 103 { X86::DEC64_32r, X86::DEC64_32m }, 104 { X86::DEC64r, X86::DEC64m }, 105 { X86::DEC8r, X86::DEC8m }, 106 { X86::INC16r, X86::INC16m }, 107 { X86::INC32r, X86::INC32m }, 108 { X86::INC64_16r, X86::INC64_16m }, 109 { X86::INC64_32r, X86::INC64_32m }, 110 { X86::INC64r, X86::INC64m }, 111 { X86::INC8r, X86::INC8m }, 112 { X86::NEG16r, X86::NEG16m }, 113 { X86::NEG32r, X86::NEG32m }, 114 { X86::NEG64r, X86::NEG64m }, 115 { X86::NEG8r, X86::NEG8m }, 116 { X86::NOT16r, X86::NOT16m }, 117 { X86::NOT32r, X86::NOT32m }, 118 { X86::NOT64r, X86::NOT64m }, 119 { X86::NOT8r, X86::NOT8m }, 120 { X86::OR16ri, X86::OR16mi }, 121 { X86::OR16ri8, X86::OR16mi8 }, 122 { X86::OR16rr, X86::OR16mr }, 123 { X86::OR32ri, X86::OR32mi }, 124 { X86::OR32ri8, X86::OR32mi8 }, 125 { X86::OR32rr, X86::OR32mr }, 126 { X86::OR64ri32, X86::OR64mi32 }, 127 { X86::OR64ri8, X86::OR64mi8 }, 128 { X86::OR64rr, X86::OR64mr }, 129 { X86::OR8ri, X86::OR8mi }, 130 { X86::OR8rr, X86::OR8mr }, 131 { X86::ROL16r1, X86::ROL16m1 }, 132 { X86::ROL16rCL, X86::ROL16mCL }, 133 { X86::ROL16ri, X86::ROL16mi }, 134 { X86::ROL32r1, X86::ROL32m1 }, 135 { X86::ROL32rCL, X86::ROL32mCL }, 136 { X86::ROL32ri, X86::ROL32mi }, 137 { X86::ROL64r1, X86::ROL64m1 }, 138 { X86::ROL64rCL, X86::ROL64mCL }, 139 { X86::ROL64ri, X86::ROL64mi }, 140 { X86::ROL8r1, X86::ROL8m1 }, 141 { X86::ROL8rCL, X86::ROL8mCL }, 142 { X86::ROL8ri, X86::ROL8mi }, 143 { X86::ROR16r1, X86::ROR16m1 }, 144 { X86::ROR16rCL, X86::ROR16mCL }, 145 { X86::ROR16ri, X86::ROR16mi }, 146 { X86::ROR32r1, X86::ROR32m1 }, 147 { X86::ROR32rCL, X86::ROR32mCL }, 148 { X86::ROR32ri, X86::ROR32mi }, 149 { X86::ROR64r1, X86::ROR64m1 }, 150 { X86::ROR64rCL, X86::ROR64mCL }, 151 { X86::ROR64ri, X86::ROR64mi }, 152 { X86::ROR8r1, X86::ROR8m1 }, 153 { X86::ROR8rCL, X86::ROR8mCL }, 154 { X86::ROR8ri, X86::ROR8mi }, 155 { X86::SAR16r1, X86::SAR16m1 }, 156 { X86::SAR16rCL, X86::SAR16mCL }, 157 { X86::SAR16ri, X86::SAR16mi }, 158 { X86::SAR32r1, X86::SAR32m1 }, 159 { X86::SAR32rCL, X86::SAR32mCL }, 160 { X86::SAR32ri, X86::SAR32mi }, 161 { X86::SAR64r1, X86::SAR64m1 }, 162 { X86::SAR64rCL, X86::SAR64mCL }, 163 { X86::SAR64ri, X86::SAR64mi }, 164 { X86::SAR8r1, X86::SAR8m1 }, 165 { X86::SAR8rCL, X86::SAR8mCL }, 166 { X86::SAR8ri, X86::SAR8mi }, 167 { X86::SBB32ri, X86::SBB32mi }, 168 { X86::SBB32ri8, X86::SBB32mi8 }, 169 { X86::SBB32rr, X86::SBB32mr }, 170 { X86::SBB64ri32, X86::SBB64mi32 }, 171 { X86::SBB64ri8, X86::SBB64mi8 }, 172 { X86::SBB64rr, X86::SBB64mr }, 173 { X86::SHL16rCL, X86::SHL16mCL }, 174 { X86::SHL16ri, X86::SHL16mi }, 175 { X86::SHL32rCL, X86::SHL32mCL }, 176 { X86::SHL32ri, X86::SHL32mi }, 177 { X86::SHL64rCL, X86::SHL64mCL }, 178 { X86::SHL64ri, X86::SHL64mi }, 179 { X86::SHL8rCL, X86::SHL8mCL }, 180 { X86::SHL8ri, X86::SHL8mi }, 181 { X86::SHLD16rrCL, X86::SHLD16mrCL }, 182 { X86::SHLD16rri8, X86::SHLD16mri8 }, 183 { X86::SHLD32rrCL, X86::SHLD32mrCL }, 184 { X86::SHLD32rri8, X86::SHLD32mri8 }, 185 { X86::SHLD64rrCL, X86::SHLD64mrCL }, 186 { X86::SHLD64rri8, X86::SHLD64mri8 }, 187 { X86::SHR16r1, X86::SHR16m1 }, 188 { X86::SHR16rCL, X86::SHR16mCL }, 189 { X86::SHR16ri, X86::SHR16mi }, 190 { X86::SHR32r1, X86::SHR32m1 }, 191 { X86::SHR32rCL, X86::SHR32mCL }, 192 { X86::SHR32ri, X86::SHR32mi }, 193 { X86::SHR64r1, X86::SHR64m1 }, 194 { X86::SHR64rCL, X86::SHR64mCL }, 195 { X86::SHR64ri, X86::SHR64mi }, 196 { X86::SHR8r1, X86::SHR8m1 }, 197 { X86::SHR8rCL, X86::SHR8mCL }, 198 { X86::SHR8ri, X86::SHR8mi }, 199 { X86::SHRD16rrCL, X86::SHRD16mrCL }, 200 { X86::SHRD16rri8, X86::SHRD16mri8 }, 201 { X86::SHRD32rrCL, X86::SHRD32mrCL }, 202 { X86::SHRD32rri8, X86::SHRD32mri8 }, 203 { X86::SHRD64rrCL, X86::SHRD64mrCL }, 204 { X86::SHRD64rri8, X86::SHRD64mri8 }, 205 { X86::SUB16ri, X86::SUB16mi }, 206 { X86::SUB16ri8, X86::SUB16mi8 }, 207 { X86::SUB16rr, X86::SUB16mr }, 208 { X86::SUB32ri, X86::SUB32mi }, 209 { X86::SUB32ri8, X86::SUB32mi8 }, 210 { X86::SUB32rr, X86::SUB32mr }, 211 { X86::SUB64ri32, X86::SUB64mi32 }, 212 { X86::SUB64ri8, X86::SUB64mi8 }, 213 { X86::SUB64rr, X86::SUB64mr }, 214 { X86::SUB8ri, X86::SUB8mi }, 215 { X86::SUB8rr, X86::SUB8mr }, 216 { X86::XOR16ri, X86::XOR16mi }, 217 { X86::XOR16ri8, X86::XOR16mi8 }, 218 { X86::XOR16rr, X86::XOR16mr }, 219 { X86::XOR32ri, X86::XOR32mi }, 220 { X86::XOR32ri8, X86::XOR32mi8 }, 221 { X86::XOR32rr, X86::XOR32mr }, 222 { X86::XOR64ri32, X86::XOR64mi32 }, 223 { X86::XOR64ri8, X86::XOR64mi8 }, 224 { X86::XOR64rr, X86::XOR64mr }, 225 { X86::XOR8ri, X86::XOR8mi }, 226 { X86::XOR8rr, X86::XOR8mr } 227 }; 228 229 for (unsigned i = 0, e = array_lengthof(OpTbl2Addr); i != e; ++i) { 230 unsigned RegOp = OpTbl2Addr[i][0]; 231 unsigned MemOp = OpTbl2Addr[i][1] & ~TB_FLAGS; 232 assert(!RegOp2MemOpTable2Addr.count(RegOp) && "Duplicated entries?"); 233 RegOp2MemOpTable2Addr[RegOp] = std::make_pair(MemOp, 0U); 234 235 // If this is not a reversable operation (because there is a many->one) 236 // mapping, don't insert the reverse of the operation into MemOp2RegOpTable. 237 if (OpTbl2Addr[i][1] & TB_NOT_REVERSABLE) 238 continue; 239 240 // Index 0, folded load and store, no alignment requirement. 241 unsigned AuxInfo = 0 | (1 << 4) | (1 << 5); 242 243 assert(!MemOp2RegOpTable.count(MemOp) && 244 "Duplicated entries in unfolding maps?"); 245 MemOp2RegOpTable[MemOp] = std::make_pair(RegOp, AuxInfo); 246 } 247 248 // If the third value is 1, then it's folding either a load or a store. 249 static const unsigned OpTbl0[][4] = { 250 { X86::BT16ri8, X86::BT16mi8, 1, 0 }, 251 { X86::BT32ri8, X86::BT32mi8, 1, 0 }, 252 { X86::BT64ri8, X86::BT64mi8, 1, 0 }, 253 { X86::CALL32r, X86::CALL32m, 1, 0 }, 254 { X86::CALL64r, X86::CALL64m, 1, 0 }, 255 { X86::WINCALL64r, X86::WINCALL64m, 1, 0 }, 256 { X86::CMP16ri, X86::CMP16mi, 1, 0 }, 257 { X86::CMP16ri8, X86::CMP16mi8, 1, 0 }, 258 { X86::CMP16rr, X86::CMP16mr, 1, 0 }, 259 { X86::CMP32ri, X86::CMP32mi, 1, 0 }, 260 { X86::CMP32ri8, X86::CMP32mi8, 1, 0 }, 261 { X86::CMP32rr, X86::CMP32mr, 1, 0 }, 262 { X86::CMP64ri32, X86::CMP64mi32, 1, 0 }, 263 { X86::CMP64ri8, X86::CMP64mi8, 1, 0 }, 264 { X86::CMP64rr, X86::CMP64mr, 1, 0 }, 265 { X86::CMP8ri, X86::CMP8mi, 1, 0 }, 266 { X86::CMP8rr, X86::CMP8mr, 1, 0 }, 267 { X86::DIV16r, X86::DIV16m, 1, 0 }, 268 { X86::DIV32r, X86::DIV32m, 1, 0 }, 269 { X86::DIV64r, X86::DIV64m, 1, 0 }, 270 { X86::DIV8r, X86::DIV8m, 1, 0 }, 271 { X86::EXTRACTPSrr, X86::EXTRACTPSmr, 0, 16 }, 272 { X86::FsMOVAPDrr, X86::MOVSDmr | TB_NOT_REVERSABLE , 0, 0 }, 273 { X86::FsMOVAPSrr, X86::MOVSSmr | TB_NOT_REVERSABLE , 0, 0 }, 274 { X86::IDIV16r, X86::IDIV16m, 1, 0 }, 275 { X86::IDIV32r, X86::IDIV32m, 1, 0 }, 276 { X86::IDIV64r, X86::IDIV64m, 1, 0 }, 277 { X86::IDIV8r, X86::IDIV8m, 1, 0 }, 278 { X86::IMUL16r, X86::IMUL16m, 1, 0 }, 279 { X86::IMUL32r, X86::IMUL32m, 1, 0 }, 280 { X86::IMUL64r, X86::IMUL64m, 1, 0 }, 281 { X86::IMUL8r, X86::IMUL8m, 1, 0 }, 282 { X86::JMP32r, X86::JMP32m, 1, 0 }, 283 { X86::JMP64r, X86::JMP64m, 1, 0 }, 284 { X86::MOV16ri, X86::MOV16mi, 0, 0 }, 285 { X86::MOV16rr, X86::MOV16mr, 0, 0 }, 286 { X86::MOV32ri, X86::MOV32mi, 0, 0 }, 287 { X86::MOV32rr, X86::MOV32mr, 0, 0 }, 288 { X86::MOV64ri32, X86::MOV64mi32, 0, 0 }, 289 { X86::MOV64rr, X86::MOV64mr, 0, 0 }, 290 { X86::MOV8ri, X86::MOV8mi, 0, 0 }, 291 { X86::MOV8rr, X86::MOV8mr, 0, 0 }, 292 { X86::MOV8rr_NOREX, X86::MOV8mr_NOREX, 0, 0 }, 293 { X86::MOVAPDrr, X86::MOVAPDmr, 0, 16 }, 294 { X86::MOVAPSrr, X86::MOVAPSmr, 0, 16 }, 295 { X86::MOVDQArr, X86::MOVDQAmr, 0, 16 }, 296 { X86::MOVPDI2DIrr, X86::MOVPDI2DImr, 0, 0 }, 297 { X86::MOVPQIto64rr,X86::MOVPQI2QImr, 0, 0 }, 298 { X86::MOVSDto64rr, X86::MOVSDto64mr, 0, 0 }, 299 { X86::MOVSS2DIrr, X86::MOVSS2DImr, 0, 0 }, 300 { X86::MOVUPDrr, X86::MOVUPDmr, 0, 0 }, 301 { X86::MOVUPSrr, X86::MOVUPSmr, 0, 0 }, 302 { X86::MUL16r, X86::MUL16m, 1, 0 }, 303 { X86::MUL32r, X86::MUL32m, 1, 0 }, 304 { X86::MUL64r, X86::MUL64m, 1, 0 }, 305 { X86::MUL8r, X86::MUL8m, 1, 0 }, 306 { X86::SETAEr, X86::SETAEm, 0, 0 }, 307 { X86::SETAr, X86::SETAm, 0, 0 }, 308 { X86::SETBEr, X86::SETBEm, 0, 0 }, 309 { X86::SETBr, X86::SETBm, 0, 0 }, 310 { X86::SETEr, X86::SETEm, 0, 0 }, 311 { X86::SETGEr, X86::SETGEm, 0, 0 }, 312 { X86::SETGr, X86::SETGm, 0, 0 }, 313 { X86::SETLEr, X86::SETLEm, 0, 0 }, 314 { X86::SETLr, X86::SETLm, 0, 0 }, 315 { X86::SETNEr, X86::SETNEm, 0, 0 }, 316 { X86::SETNOr, X86::SETNOm, 0, 0 }, 317 { X86::SETNPr, X86::SETNPm, 0, 0 }, 318 { X86::SETNSr, X86::SETNSm, 0, 0 }, 319 { X86::SETOr, X86::SETOm, 0, 0 }, 320 { X86::SETPr, X86::SETPm, 0, 0 }, 321 { X86::SETSr, X86::SETSm, 0, 0 }, 322 { X86::TAILJMPr, X86::TAILJMPm, 1, 0 }, 323 { X86::TAILJMPr64, X86::TAILJMPm64, 1, 0 }, 324 { X86::TEST16ri, X86::TEST16mi, 1, 0 }, 325 { X86::TEST32ri, X86::TEST32mi, 1, 0 }, 326 { X86::TEST64ri32, X86::TEST64mi32, 1, 0 }, 327 { X86::TEST8ri, X86::TEST8mi, 1, 0 } 328 }; 329 330 for (unsigned i = 0, e = array_lengthof(OpTbl0); i != e; ++i) { 331 unsigned RegOp = OpTbl0[i][0]; 332 unsigned MemOp = OpTbl0[i][1] & ~TB_FLAGS; 333 unsigned FoldedLoad = OpTbl0[i][2]; 334 unsigned Align = OpTbl0[i][3]; 335 assert(!RegOp2MemOpTable0.count(RegOp) && "Duplicated entries?"); 336 RegOp2MemOpTable0[RegOp] = std::make_pair(MemOp, Align); 337 338 // If this is not a reversable operation (because there is a many->one) 339 // mapping, don't insert the reverse of the operation into MemOp2RegOpTable. 340 if (OpTbl0[i][1] & TB_NOT_REVERSABLE) 341 continue; 342 343 // Index 0, folded load or store. 344 unsigned AuxInfo = 0 | (FoldedLoad << 4) | ((FoldedLoad^1) << 5); 345 assert(!MemOp2RegOpTable.count(MemOp) && "Duplicated entries?"); 346 MemOp2RegOpTable[MemOp] = std::make_pair(RegOp, AuxInfo); 347 } 348 349 static const unsigned OpTbl1[][3] = { 350 { X86::CMP16rr, X86::CMP16rm, 0 }, 351 { X86::CMP32rr, X86::CMP32rm, 0 }, 352 { X86::CMP64rr, X86::CMP64rm, 0 }, 353 { X86::CMP8rr, X86::CMP8rm, 0 }, 354 { X86::CVTSD2SSrr, X86::CVTSD2SSrm, 0 }, 355 { X86::CVTSI2SD64rr, X86::CVTSI2SD64rm, 0 }, 356 { X86::CVTSI2SDrr, X86::CVTSI2SDrm, 0 }, 357 { X86::CVTSI2SS64rr, X86::CVTSI2SS64rm, 0 }, 358 { X86::CVTSI2SSrr, X86::CVTSI2SSrm, 0 }, 359 { X86::CVTSS2SDrr, X86::CVTSS2SDrm, 0 }, 360 { X86::CVTTSD2SI64rr, X86::CVTTSD2SI64rm, 0 }, 361 { X86::CVTTSD2SIrr, X86::CVTTSD2SIrm, 0 }, 362 { X86::CVTTSS2SI64rr, X86::CVTTSS2SI64rm, 0 }, 363 { X86::CVTTSS2SIrr, X86::CVTTSS2SIrm, 0 }, 364 { X86::FsMOVAPDrr, X86::MOVSDrm | TB_NOT_REVERSABLE , 0 }, 365 { X86::FsMOVAPSrr, X86::MOVSSrm | TB_NOT_REVERSABLE , 0 }, 366 { X86::IMUL16rri, X86::IMUL16rmi, 0 }, 367 { X86::IMUL16rri8, X86::IMUL16rmi8, 0 }, 368 { X86::IMUL32rri, X86::IMUL32rmi, 0 }, 369 { X86::IMUL32rri8, X86::IMUL32rmi8, 0 }, 370 { X86::IMUL64rri32, X86::IMUL64rmi32, 0 }, 371 { X86::IMUL64rri8, X86::IMUL64rmi8, 0 }, 372 { X86::Int_COMISDrr, X86::Int_COMISDrm, 0 }, 373 { X86::Int_COMISSrr, X86::Int_COMISSrm, 0 }, 374 { X86::Int_CVTDQ2PDrr, X86::Int_CVTDQ2PDrm, 16 }, 375 { X86::Int_CVTDQ2PSrr, X86::Int_CVTDQ2PSrm, 16 }, 376 { X86::Int_CVTPD2DQrr, X86::Int_CVTPD2DQrm, 16 }, 377 { X86::Int_CVTPD2PSrr, X86::Int_CVTPD2PSrm, 16 }, 378 { X86::Int_CVTPS2DQrr, X86::Int_CVTPS2DQrm, 16 }, 379 { X86::Int_CVTPS2PDrr, X86::Int_CVTPS2PDrm, 0 }, 380 { X86::CVTSD2SI64rr, X86::CVTSD2SI64rm, 0 }, 381 { X86::CVTSD2SIrr, X86::CVTSD2SIrm, 0 }, 382 { X86::Int_CVTSD2SSrr, X86::Int_CVTSD2SSrm, 0 }, 383 { X86::Int_CVTSI2SD64rr,X86::Int_CVTSI2SD64rm, 0 }, 384 { X86::Int_CVTSI2SDrr, X86::Int_CVTSI2SDrm, 0 }, 385 { X86::Int_CVTSI2SS64rr,X86::Int_CVTSI2SS64rm, 0 }, 386 { X86::Int_CVTSI2SSrr, X86::Int_CVTSI2SSrm, 0 }, 387 { X86::Int_CVTSS2SDrr, X86::Int_CVTSS2SDrm, 0 }, 388 { X86::Int_CVTSS2SI64rr,X86::Int_CVTSS2SI64rm, 0 }, 389 { X86::Int_CVTSS2SIrr, X86::Int_CVTSS2SIrm, 0 }, 390 { X86::CVTTPD2DQrr, X86::CVTTPD2DQrm, 16 }, 391 { X86::CVTTPS2DQrr, X86::CVTTPS2DQrm, 16 }, 392 { X86::Int_CVTTSD2SI64rr,X86::Int_CVTTSD2SI64rm, 0 }, 393 { X86::Int_CVTTSD2SIrr, X86::Int_CVTTSD2SIrm, 0 }, 394 { X86::Int_CVTTSS2SI64rr,X86::Int_CVTTSS2SI64rm, 0 }, 395 { X86::Int_CVTTSS2SIrr, X86::Int_CVTTSS2SIrm, 0 }, 396 { X86::Int_UCOMISDrr, X86::Int_UCOMISDrm, 0 }, 397 { X86::Int_UCOMISSrr, X86::Int_UCOMISSrm, 0 }, 398 { X86::MOV16rr, X86::MOV16rm, 0 }, 399 { X86::MOV32rr, X86::MOV32rm, 0 }, 400 { X86::MOV64rr, X86::MOV64rm, 0 }, 401 { X86::MOV64toPQIrr, X86::MOVQI2PQIrm, 0 }, 402 { X86::MOV64toSDrr, X86::MOV64toSDrm, 0 }, 403 { X86::MOV8rr, X86::MOV8rm, 0 }, 404 { X86::MOVAPDrr, X86::MOVAPDrm, 16 }, 405 { X86::MOVAPSrr, X86::MOVAPSrm, 16 }, 406 { X86::MOVDDUPrr, X86::MOVDDUPrm, 0 }, 407 { X86::MOVDI2PDIrr, X86::MOVDI2PDIrm, 0 }, 408 { X86::MOVDI2SSrr, X86::MOVDI2SSrm, 0 }, 409 { X86::MOVDQArr, X86::MOVDQArm, 16 }, 410 { X86::MOVSHDUPrr, X86::MOVSHDUPrm, 16 }, 411 { X86::MOVSLDUPrr, X86::MOVSLDUPrm, 16 }, 412 { X86::MOVSX16rr8, X86::MOVSX16rm8, 0 }, 413 { X86::MOVSX32rr16, X86::MOVSX32rm16, 0 }, 414 { X86::MOVSX32rr8, X86::MOVSX32rm8, 0 }, 415 { X86::MOVSX64rr16, X86::MOVSX64rm16, 0 }, 416 { X86::MOVSX64rr32, X86::MOVSX64rm32, 0 }, 417 { X86::MOVSX64rr8, X86::MOVSX64rm8, 0 }, 418 { X86::MOVUPDrr, X86::MOVUPDrm, 16 }, 419 { X86::MOVUPSrr, X86::MOVUPSrm, 0 }, 420 { X86::MOVZDI2PDIrr, X86::MOVZDI2PDIrm, 0 }, 421 { X86::MOVZQI2PQIrr, X86::MOVZQI2PQIrm, 0 }, 422 { X86::MOVZPQILo2PQIrr, X86::MOVZPQILo2PQIrm, 16 }, 423 { X86::MOVZX16rr8, X86::MOVZX16rm8, 0 }, 424 { X86::MOVZX32rr16, X86::MOVZX32rm16, 0 }, 425 { X86::MOVZX32_NOREXrr8, X86::MOVZX32_NOREXrm8, 0 }, 426 { X86::MOVZX32rr8, X86::MOVZX32rm8, 0 }, 427 { X86::MOVZX64rr16, X86::MOVZX64rm16, 0 }, 428 { X86::MOVZX64rr32, X86::MOVZX64rm32, 0 }, 429 { X86::MOVZX64rr8, X86::MOVZX64rm8, 0 }, 430 { X86::PSHUFDri, X86::PSHUFDmi, 16 }, 431 { X86::PSHUFHWri, X86::PSHUFHWmi, 16 }, 432 { X86::PSHUFLWri, X86::PSHUFLWmi, 16 }, 433 { X86::RCPPSr, X86::RCPPSm, 16 }, 434 { X86::RCPPSr_Int, X86::RCPPSm_Int, 16 }, 435 { X86::RSQRTPSr, X86::RSQRTPSm, 16 }, 436 { X86::RSQRTPSr_Int, X86::RSQRTPSm_Int, 16 }, 437 { X86::RSQRTSSr, X86::RSQRTSSm, 0 }, 438 { X86::RSQRTSSr_Int, X86::RSQRTSSm_Int, 0 }, 439 { X86::SQRTPDr, X86::SQRTPDm, 16 }, 440 { X86::SQRTPDr_Int, X86::SQRTPDm_Int, 16 }, 441 { X86::SQRTPSr, X86::SQRTPSm, 16 }, 442 { X86::SQRTPSr_Int, X86::SQRTPSm_Int, 16 }, 443 { X86::SQRTSDr, X86::SQRTSDm, 0 }, 444 { X86::SQRTSDr_Int, X86::SQRTSDm_Int, 0 }, 445 { X86::SQRTSSr, X86::SQRTSSm, 0 }, 446 { X86::SQRTSSr_Int, X86::SQRTSSm_Int, 0 }, 447 { X86::TEST16rr, X86::TEST16rm, 0 }, 448 { X86::TEST32rr, X86::TEST32rm, 0 }, 449 { X86::TEST64rr, X86::TEST64rm, 0 }, 450 { X86::TEST8rr, X86::TEST8rm, 0 }, 451 // FIXME: TEST*rr EAX,EAX ---> CMP [mem], 0 452 { X86::UCOMISDrr, X86::UCOMISDrm, 0 }, 453 { X86::UCOMISSrr, X86::UCOMISSrm, 0 } 454 }; 455 456 for (unsigned i = 0, e = array_lengthof(OpTbl1); i != e; ++i) { 457 unsigned RegOp = OpTbl1[i][0]; 458 unsigned MemOp = OpTbl1[i][1] & ~TB_FLAGS; 459 unsigned Align = OpTbl1[i][2]; 460 assert(!RegOp2MemOpTable1.count(RegOp) && "Duplicate entries"); 461 RegOp2MemOpTable1[RegOp] = std::make_pair(MemOp, Align); 462 463 // If this is not a reversable operation (because there is a many->one) 464 // mapping, don't insert the reverse of the operation into MemOp2RegOpTable. 465 if (OpTbl1[i][1] & TB_NOT_REVERSABLE) 466 continue; 467 468 // Index 1, folded load 469 unsigned AuxInfo = 1 | (1 << 4); 470 assert(!MemOp2RegOpTable.count(MemOp) && "Duplicate entries"); 471 MemOp2RegOpTable[MemOp] = std::make_pair(RegOp, AuxInfo); 472 } 473 474 static const unsigned OpTbl2[][3] = { 475 { X86::ADC32rr, X86::ADC32rm, 0 }, 476 { X86::ADC64rr, X86::ADC64rm, 0 }, 477 { X86::ADD16rr, X86::ADD16rm, 0 }, 478 { X86::ADD16rr_DB, X86::ADD16rm | TB_NOT_REVERSABLE, 0 }, 479 { X86::ADD32rr, X86::ADD32rm, 0 }, 480 { X86::ADD32rr_DB, X86::ADD32rm | TB_NOT_REVERSABLE, 0 }, 481 { X86::ADD64rr, X86::ADD64rm, 0 }, 482 { X86::ADD64rr_DB, X86::ADD64rm | TB_NOT_REVERSABLE, 0 }, 483 { X86::ADD8rr, X86::ADD8rm, 0 }, 484 { X86::ADDPDrr, X86::ADDPDrm, 16 }, 485 { X86::ADDPSrr, X86::ADDPSrm, 16 }, 486 { X86::ADDSDrr, X86::ADDSDrm, 0 }, 487 { X86::ADDSSrr, X86::ADDSSrm, 0 }, 488 { X86::ADDSUBPDrr, X86::ADDSUBPDrm, 16 }, 489 { X86::ADDSUBPSrr, X86::ADDSUBPSrm, 16 }, 490 { X86::AND16rr, X86::AND16rm, 0 }, 491 { X86::AND32rr, X86::AND32rm, 0 }, 492 { X86::AND64rr, X86::AND64rm, 0 }, 493 { X86::AND8rr, X86::AND8rm, 0 }, 494 { X86::ANDNPDrr, X86::ANDNPDrm, 16 }, 495 { X86::ANDNPSrr, X86::ANDNPSrm, 16 }, 496 { X86::ANDPDrr, X86::ANDPDrm, 16 }, 497 { X86::ANDPSrr, X86::ANDPSrm, 16 }, 498 { X86::CMOVA16rr, X86::CMOVA16rm, 0 }, 499 { X86::CMOVA32rr, X86::CMOVA32rm, 0 }, 500 { X86::CMOVA64rr, X86::CMOVA64rm, 0 }, 501 { X86::CMOVAE16rr, X86::CMOVAE16rm, 0 }, 502 { X86::CMOVAE32rr, X86::CMOVAE32rm, 0 }, 503 { X86::CMOVAE64rr, X86::CMOVAE64rm, 0 }, 504 { X86::CMOVB16rr, X86::CMOVB16rm, 0 }, 505 { X86::CMOVB32rr, X86::CMOVB32rm, 0 }, 506 { X86::CMOVB64rr, X86::CMOVB64rm, 0 }, 507 { X86::CMOVBE16rr, X86::CMOVBE16rm, 0 }, 508 { X86::CMOVBE32rr, X86::CMOVBE32rm, 0 }, 509 { X86::CMOVBE64rr, X86::CMOVBE64rm, 0 }, 510 { X86::CMOVE16rr, X86::CMOVE16rm, 0 }, 511 { X86::CMOVE32rr, X86::CMOVE32rm, 0 }, 512 { X86::CMOVE64rr, X86::CMOVE64rm, 0 }, 513 { X86::CMOVG16rr, X86::CMOVG16rm, 0 }, 514 { X86::CMOVG32rr, X86::CMOVG32rm, 0 }, 515 { X86::CMOVG64rr, X86::CMOVG64rm, 0 }, 516 { X86::CMOVGE16rr, X86::CMOVGE16rm, 0 }, 517 { X86::CMOVGE32rr, X86::CMOVGE32rm, 0 }, 518 { X86::CMOVGE64rr, X86::CMOVGE64rm, 0 }, 519 { X86::CMOVL16rr, X86::CMOVL16rm, 0 }, 520 { X86::CMOVL32rr, X86::CMOVL32rm, 0 }, 521 { X86::CMOVL64rr, X86::CMOVL64rm, 0 }, 522 { X86::CMOVLE16rr, X86::CMOVLE16rm, 0 }, 523 { X86::CMOVLE32rr, X86::CMOVLE32rm, 0 }, 524 { X86::CMOVLE64rr, X86::CMOVLE64rm, 0 }, 525 { X86::CMOVNE16rr, X86::CMOVNE16rm, 0 }, 526 { X86::CMOVNE32rr, X86::CMOVNE32rm, 0 }, 527 { X86::CMOVNE64rr, X86::CMOVNE64rm, 0 }, 528 { X86::CMOVNO16rr, X86::CMOVNO16rm, 0 }, 529 { X86::CMOVNO32rr, X86::CMOVNO32rm, 0 }, 530 { X86::CMOVNO64rr, X86::CMOVNO64rm, 0 }, 531 { X86::CMOVNP16rr, X86::CMOVNP16rm, 0 }, 532 { X86::CMOVNP32rr, X86::CMOVNP32rm, 0 }, 533 { X86::CMOVNP64rr, X86::CMOVNP64rm, 0 }, 534 { X86::CMOVNS16rr, X86::CMOVNS16rm, 0 }, 535 { X86::CMOVNS32rr, X86::CMOVNS32rm, 0 }, 536 { X86::CMOVNS64rr, X86::CMOVNS64rm, 0 }, 537 { X86::CMOVO16rr, X86::CMOVO16rm, 0 }, 538 { X86::CMOVO32rr, X86::CMOVO32rm, 0 }, 539 { X86::CMOVO64rr, X86::CMOVO64rm, 0 }, 540 { X86::CMOVP16rr, X86::CMOVP16rm, 0 }, 541 { X86::CMOVP32rr, X86::CMOVP32rm, 0 }, 542 { X86::CMOVP64rr, X86::CMOVP64rm, 0 }, 543 { X86::CMOVS16rr, X86::CMOVS16rm, 0 }, 544 { X86::CMOVS32rr, X86::CMOVS32rm, 0 }, 545 { X86::CMOVS64rr, X86::CMOVS64rm, 0 }, 546 { X86::CMPPDrri, X86::CMPPDrmi, 16 }, 547 { X86::CMPPSrri, X86::CMPPSrmi, 16 }, 548 { X86::CMPSDrr, X86::CMPSDrm, 0 }, 549 { X86::CMPSSrr, X86::CMPSSrm, 0 }, 550 { X86::DIVPDrr, X86::DIVPDrm, 16 }, 551 { X86::DIVPSrr, X86::DIVPSrm, 16 }, 552 { X86::DIVSDrr, X86::DIVSDrm, 0 }, 553 { X86::DIVSSrr, X86::DIVSSrm, 0 }, 554 { X86::FsANDNPDrr, X86::FsANDNPDrm, 16 }, 555 { X86::FsANDNPSrr, X86::FsANDNPSrm, 16 }, 556 { X86::FsANDPDrr, X86::FsANDPDrm, 16 }, 557 { X86::FsANDPSrr, X86::FsANDPSrm, 16 }, 558 { X86::FsORPDrr, X86::FsORPDrm, 16 }, 559 { X86::FsORPSrr, X86::FsORPSrm, 16 }, 560 { X86::FsXORPDrr, X86::FsXORPDrm, 16 }, 561 { X86::FsXORPSrr, X86::FsXORPSrm, 16 }, 562 { X86::HADDPDrr, X86::HADDPDrm, 16 }, 563 { X86::HADDPSrr, X86::HADDPSrm, 16 }, 564 { X86::HSUBPDrr, X86::HSUBPDrm, 16 }, 565 { X86::HSUBPSrr, X86::HSUBPSrm, 16 }, 566 { X86::IMUL16rr, X86::IMUL16rm, 0 }, 567 { X86::IMUL32rr, X86::IMUL32rm, 0 }, 568 { X86::IMUL64rr, X86::IMUL64rm, 0 }, 569 { X86::Int_CMPSDrr, X86::Int_CMPSDrm, 0 }, 570 { X86::Int_CMPSSrr, X86::Int_CMPSSrm, 0 }, 571 { X86::MAXPDrr, X86::MAXPDrm, 16 }, 572 { X86::MAXPDrr_Int, X86::MAXPDrm_Int, 16 }, 573 { X86::MAXPSrr, X86::MAXPSrm, 16 }, 574 { X86::MAXPSrr_Int, X86::MAXPSrm_Int, 16 }, 575 { X86::MAXSDrr, X86::MAXSDrm, 0 }, 576 { X86::MAXSDrr_Int, X86::MAXSDrm_Int, 0 }, 577 { X86::MAXSSrr, X86::MAXSSrm, 0 }, 578 { X86::MAXSSrr_Int, X86::MAXSSrm_Int, 0 }, 579 { X86::MINPDrr, X86::MINPDrm, 16 }, 580 { X86::MINPDrr_Int, X86::MINPDrm_Int, 16 }, 581 { X86::MINPSrr, X86::MINPSrm, 16 }, 582 { X86::MINPSrr_Int, X86::MINPSrm_Int, 16 }, 583 { X86::MINSDrr, X86::MINSDrm, 0 }, 584 { X86::MINSDrr_Int, X86::MINSDrm_Int, 0 }, 585 { X86::MINSSrr, X86::MINSSrm, 0 }, 586 { X86::MINSSrr_Int, X86::MINSSrm_Int, 0 }, 587 { X86::MULPDrr, X86::MULPDrm, 16 }, 588 { X86::MULPSrr, X86::MULPSrm, 16 }, 589 { X86::MULSDrr, X86::MULSDrm, 0 }, 590 { X86::MULSSrr, X86::MULSSrm, 0 }, 591 { X86::OR16rr, X86::OR16rm, 0 }, 592 { X86::OR32rr, X86::OR32rm, 0 }, 593 { X86::OR64rr, X86::OR64rm, 0 }, 594 { X86::OR8rr, X86::OR8rm, 0 }, 595 { X86::ORPDrr, X86::ORPDrm, 16 }, 596 { X86::ORPSrr, X86::ORPSrm, 16 }, 597 { X86::PACKSSDWrr, X86::PACKSSDWrm, 16 }, 598 { X86::PACKSSWBrr, X86::PACKSSWBrm, 16 }, 599 { X86::PACKUSWBrr, X86::PACKUSWBrm, 16 }, 600 { X86::PADDBrr, X86::PADDBrm, 16 }, 601 { X86::PADDDrr, X86::PADDDrm, 16 }, 602 { X86::PADDQrr, X86::PADDQrm, 16 }, 603 { X86::PADDSBrr, X86::PADDSBrm, 16 }, 604 { X86::PADDSWrr, X86::PADDSWrm, 16 }, 605 { X86::PADDWrr, X86::PADDWrm, 16 }, 606 { X86::PANDNrr, X86::PANDNrm, 16 }, 607 { X86::PANDrr, X86::PANDrm, 16 }, 608 { X86::PAVGBrr, X86::PAVGBrm, 16 }, 609 { X86::PAVGWrr, X86::PAVGWrm, 16 }, 610 { X86::PCMPEQBrr, X86::PCMPEQBrm, 16 }, 611 { X86::PCMPEQDrr, X86::PCMPEQDrm, 16 }, 612 { X86::PCMPEQWrr, X86::PCMPEQWrm, 16 }, 613 { X86::PCMPGTBrr, X86::PCMPGTBrm, 16 }, 614 { X86::PCMPGTDrr, X86::PCMPGTDrm, 16 }, 615 { X86::PCMPGTWrr, X86::PCMPGTWrm, 16 }, 616 { X86::PINSRWrri, X86::PINSRWrmi, 16 }, 617 { X86::PMADDWDrr, X86::PMADDWDrm, 16 }, 618 { X86::PMAXSWrr, X86::PMAXSWrm, 16 }, 619 { X86::PMAXUBrr, X86::PMAXUBrm, 16 }, 620 { X86::PMINSWrr, X86::PMINSWrm, 16 }, 621 { X86::PMINUBrr, X86::PMINUBrm, 16 }, 622 { X86::PMULDQrr, X86::PMULDQrm, 16 }, 623 { X86::PMULHUWrr, X86::PMULHUWrm, 16 }, 624 { X86::PMULHWrr, X86::PMULHWrm, 16 }, 625 { X86::PMULLDrr, X86::PMULLDrm, 16 }, 626 { X86::PMULLWrr, X86::PMULLWrm, 16 }, 627 { X86::PMULUDQrr, X86::PMULUDQrm, 16 }, 628 { X86::PORrr, X86::PORrm, 16 }, 629 { X86::PSADBWrr, X86::PSADBWrm, 16 }, 630 { X86::PSLLDrr, X86::PSLLDrm, 16 }, 631 { X86::PSLLQrr, X86::PSLLQrm, 16 }, 632 { X86::PSLLWrr, X86::PSLLWrm, 16 }, 633 { X86::PSRADrr, X86::PSRADrm, 16 }, 634 { X86::PSRAWrr, X86::PSRAWrm, 16 }, 635 { X86::PSRLDrr, X86::PSRLDrm, 16 }, 636 { X86::PSRLQrr, X86::PSRLQrm, 16 }, 637 { X86::PSRLWrr, X86::PSRLWrm, 16 }, 638 { X86::PSUBBrr, X86::PSUBBrm, 16 }, 639 { X86::PSUBDrr, X86::PSUBDrm, 16 }, 640 { X86::PSUBSBrr, X86::PSUBSBrm, 16 }, 641 { X86::PSUBSWrr, X86::PSUBSWrm, 16 }, 642 { X86::PSUBWrr, X86::PSUBWrm, 16 }, 643 { X86::PUNPCKHBWrr, X86::PUNPCKHBWrm, 16 }, 644 { X86::PUNPCKHDQrr, X86::PUNPCKHDQrm, 16 }, 645 { X86::PUNPCKHQDQrr, X86::PUNPCKHQDQrm, 16 }, 646 { X86::PUNPCKHWDrr, X86::PUNPCKHWDrm, 16 }, 647 { X86::PUNPCKLBWrr, X86::PUNPCKLBWrm, 16 }, 648 { X86::PUNPCKLDQrr, X86::PUNPCKLDQrm, 16 }, 649 { X86::PUNPCKLQDQrr, X86::PUNPCKLQDQrm, 16 }, 650 { X86::PUNPCKLWDrr, X86::PUNPCKLWDrm, 16 }, 651 { X86::PXORrr, X86::PXORrm, 16 }, 652 { X86::SBB32rr, X86::SBB32rm, 0 }, 653 { X86::SBB64rr, X86::SBB64rm, 0 }, 654 { X86::SHUFPDrri, X86::SHUFPDrmi, 16 }, 655 { X86::SHUFPSrri, X86::SHUFPSrmi, 16 }, 656 { X86::SUB16rr, X86::SUB16rm, 0 }, 657 { X86::SUB32rr, X86::SUB32rm, 0 }, 658 { X86::SUB64rr, X86::SUB64rm, 0 }, 659 { X86::SUB8rr, X86::SUB8rm, 0 }, 660 { X86::SUBPDrr, X86::SUBPDrm, 16 }, 661 { X86::SUBPSrr, X86::SUBPSrm, 16 }, 662 { X86::SUBSDrr, X86::SUBSDrm, 0 }, 663 { X86::SUBSSrr, X86::SUBSSrm, 0 }, 664 // FIXME: TEST*rr -> swapped operand of TEST*mr. 665 { X86::UNPCKHPDrr, X86::UNPCKHPDrm, 16 }, 666 { X86::UNPCKHPSrr, X86::UNPCKHPSrm, 16 }, 667 { X86::UNPCKLPDrr, X86::UNPCKLPDrm, 16 }, 668 { X86::UNPCKLPSrr, X86::UNPCKLPSrm, 16 }, 669 { X86::XOR16rr, X86::XOR16rm, 0 }, 670 { X86::XOR32rr, X86::XOR32rm, 0 }, 671 { X86::XOR64rr, X86::XOR64rm, 0 }, 672 { X86::XOR8rr, X86::XOR8rm, 0 }, 673 { X86::XORPDrr, X86::XORPDrm, 16 }, 674 { X86::XORPSrr, X86::XORPSrm, 16 } 675 }; 676 677 for (unsigned i = 0, e = array_lengthof(OpTbl2); i != e; ++i) { 678 unsigned RegOp = OpTbl2[i][0]; 679 unsigned MemOp = OpTbl2[i][1] & ~TB_FLAGS; 680 unsigned Align = OpTbl2[i][2]; 681 682 assert(!RegOp2MemOpTable2.count(RegOp) && "Duplicate entry!"); 683 RegOp2MemOpTable2[RegOp] = std::make_pair(MemOp, Align); 684 685 // If this is not a reversable operation (because there is a many->one) 686 // mapping, don't insert the reverse of the operation into MemOp2RegOpTable. 687 if (OpTbl2[i][1] & TB_NOT_REVERSABLE) 688 continue; 689 690 // Index 2, folded load 691 unsigned AuxInfo = 2 | (1 << 4); 692 assert(!MemOp2RegOpTable.count(MemOp) && 693 "Duplicated entries in unfolding maps?"); 694 MemOp2RegOpTable[MemOp] = std::make_pair(RegOp, AuxInfo); 695 } 696} 697 698bool 699X86InstrInfo::isCoalescableExtInstr(const MachineInstr &MI, 700 unsigned &SrcReg, unsigned &DstReg, 701 unsigned &SubIdx) const { 702 switch (MI.getOpcode()) { 703 default: break; 704 case X86::MOVSX16rr8: 705 case X86::MOVZX16rr8: 706 case X86::MOVSX32rr8: 707 case X86::MOVZX32rr8: 708 case X86::MOVSX64rr8: 709 case X86::MOVZX64rr8: 710 if (!TM.getSubtarget<X86Subtarget>().is64Bit()) 711 // It's not always legal to reference the low 8-bit of the larger 712 // register in 32-bit mode. 713 return false; 714 case X86::MOVSX32rr16: 715 case X86::MOVZX32rr16: 716 case X86::MOVSX64rr16: 717 case X86::MOVZX64rr16: 718 case X86::MOVSX64rr32: 719 case X86::MOVZX64rr32: { 720 if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg()) 721 // Be conservative. 722 return false; 723 SrcReg = MI.getOperand(1).getReg(); 724 DstReg = MI.getOperand(0).getReg(); 725 switch (MI.getOpcode()) { 726 default: 727 llvm_unreachable(0); 728 break; 729 case X86::MOVSX16rr8: 730 case X86::MOVZX16rr8: 731 case X86::MOVSX32rr8: 732 case X86::MOVZX32rr8: 733 case X86::MOVSX64rr8: 734 case X86::MOVZX64rr8: 735 SubIdx = X86::sub_8bit; 736 break; 737 case X86::MOVSX32rr16: 738 case X86::MOVZX32rr16: 739 case X86::MOVSX64rr16: 740 case X86::MOVZX64rr16: 741 SubIdx = X86::sub_16bit; 742 break; 743 case X86::MOVSX64rr32: 744 case X86::MOVZX64rr32: 745 SubIdx = X86::sub_32bit; 746 break; 747 } 748 return true; 749 } 750 } 751 return false; 752} 753 754/// isFrameOperand - Return true and the FrameIndex if the specified 755/// operand and follow operands form a reference to the stack frame. 756bool X86InstrInfo::isFrameOperand(const MachineInstr *MI, unsigned int Op, 757 int &FrameIndex) const { 758 if (MI->getOperand(Op).isFI() && MI->getOperand(Op+1).isImm() && 759 MI->getOperand(Op+2).isReg() && MI->getOperand(Op+3).isImm() && 760 MI->getOperand(Op+1).getImm() == 1 && 761 MI->getOperand(Op+2).getReg() == 0 && 762 MI->getOperand(Op+3).getImm() == 0) { 763 FrameIndex = MI->getOperand(Op).getIndex(); 764 return true; 765 } 766 return false; 767} 768 769static bool isFrameLoadOpcode(int Opcode) { 770 switch (Opcode) { 771 default: break; 772 case X86::MOV8rm: 773 case X86::MOV16rm: 774 case X86::MOV32rm: 775 case X86::MOV64rm: 776 case X86::LD_Fp64m: 777 case X86::MOVSSrm: 778 case X86::MOVSDrm: 779 case X86::MOVAPSrm: 780 case X86::MOVAPDrm: 781 case X86::MOVDQArm: 782 case X86::MMX_MOVD64rm: 783 case X86::MMX_MOVQ64rm: 784 return true; 785 break; 786 } 787 return false; 788} 789 790static bool isFrameStoreOpcode(int Opcode) { 791 switch (Opcode) { 792 default: break; 793 case X86::MOV8mr: 794 case X86::MOV16mr: 795 case X86::MOV32mr: 796 case X86::MOV64mr: 797 case X86::ST_FpP64m: 798 case X86::MOVSSmr: 799 case X86::MOVSDmr: 800 case X86::MOVAPSmr: 801 case X86::MOVAPDmr: 802 case X86::MOVDQAmr: 803 case X86::MMX_MOVD64mr: 804 case X86::MMX_MOVQ64mr: 805 case X86::MMX_MOVNTQmr: 806 return true; 807 } 808 return false; 809} 810 811unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr *MI, 812 int &FrameIndex) const { 813 if (isFrameLoadOpcode(MI->getOpcode())) 814 if (MI->getOperand(0).getSubReg() == 0 && isFrameOperand(MI, 1, FrameIndex)) 815 return MI->getOperand(0).getReg(); 816 return 0; 817} 818 819unsigned X86InstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI, 820 int &FrameIndex) const { 821 if (isFrameLoadOpcode(MI->getOpcode())) { 822 unsigned Reg; 823 if ((Reg = isLoadFromStackSlot(MI, FrameIndex))) 824 return Reg; 825 // Check for post-frame index elimination operations 826 const MachineMemOperand *Dummy; 827 return hasLoadFromStackSlot(MI, Dummy, FrameIndex); 828 } 829 return 0; 830} 831 832bool X86InstrInfo::hasLoadFromStackSlot(const MachineInstr *MI, 833 const MachineMemOperand *&MMO, 834 int &FrameIndex) const { 835 for (MachineInstr::mmo_iterator o = MI->memoperands_begin(), 836 oe = MI->memoperands_end(); 837 o != oe; 838 ++o) { 839 if ((*o)->isLoad() && (*o)->getValue()) 840 if (const FixedStackPseudoSourceValue *Value = 841 dyn_cast<const FixedStackPseudoSourceValue>((*o)->getValue())) { 842 FrameIndex = Value->getFrameIndex(); 843 MMO = *o; 844 return true; 845 } 846 } 847 return false; 848} 849 850unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr *MI, 851 int &FrameIndex) const { 852 if (isFrameStoreOpcode(MI->getOpcode())) 853 if (MI->getOperand(X86::AddrNumOperands).getSubReg() == 0 && 854 isFrameOperand(MI, 0, FrameIndex)) 855 return MI->getOperand(X86::AddrNumOperands).getReg(); 856 return 0; 857} 858 859unsigned X86InstrInfo::isStoreToStackSlotPostFE(const MachineInstr *MI, 860 int &FrameIndex) const { 861 if (isFrameStoreOpcode(MI->getOpcode())) { 862 unsigned Reg; 863 if ((Reg = isStoreToStackSlot(MI, FrameIndex))) 864 return Reg; 865 // Check for post-frame index elimination operations 866 const MachineMemOperand *Dummy; 867 return hasStoreToStackSlot(MI, Dummy, FrameIndex); 868 } 869 return 0; 870} 871 872bool X86InstrInfo::hasStoreToStackSlot(const MachineInstr *MI, 873 const MachineMemOperand *&MMO, 874 int &FrameIndex) const { 875 for (MachineInstr::mmo_iterator o = MI->memoperands_begin(), 876 oe = MI->memoperands_end(); 877 o != oe; 878 ++o) { 879 if ((*o)->isStore() && (*o)->getValue()) 880 if (const FixedStackPseudoSourceValue *Value = 881 dyn_cast<const FixedStackPseudoSourceValue>((*o)->getValue())) { 882 FrameIndex = Value->getFrameIndex(); 883 MMO = *o; 884 return true; 885 } 886 } 887 return false; 888} 889 890/// regIsPICBase - Return true if register is PIC base (i.e.g defined by 891/// X86::MOVPC32r. 892static bool regIsPICBase(unsigned BaseReg, const MachineRegisterInfo &MRI) { 893 bool isPICBase = false; 894 for (MachineRegisterInfo::def_iterator I = MRI.def_begin(BaseReg), 895 E = MRI.def_end(); I != E; ++I) { 896 MachineInstr *DefMI = I.getOperand().getParent(); 897 if (DefMI->getOpcode() != X86::MOVPC32r) 898 return false; 899 assert(!isPICBase && "More than one PIC base?"); 900 isPICBase = true; 901 } 902 return isPICBase; 903} 904 905bool 906X86InstrInfo::isReallyTriviallyReMaterializable(const MachineInstr *MI, 907 AliasAnalysis *AA) const { 908 switch (MI->getOpcode()) { 909 default: break; 910 case X86::MOV8rm: 911 case X86::MOV16rm: 912 case X86::MOV32rm: 913 case X86::MOV64rm: 914 case X86::LD_Fp64m: 915 case X86::MOVSSrm: 916 case X86::MOVSDrm: 917 case X86::MOVAPSrm: 918 case X86::MOVUPSrm: 919 case X86::MOVUPSrm_Int: 920 case X86::MOVAPDrm: 921 case X86::MOVDQArm: 922 case X86::MMX_MOVD64rm: 923 case X86::MMX_MOVQ64rm: 924 case X86::FsMOVAPSrm: 925 case X86::FsMOVAPDrm: { 926 // Loads from constant pools are trivially rematerializable. 927 if (MI->getOperand(1).isReg() && 928 MI->getOperand(2).isImm() && 929 MI->getOperand(3).isReg() && MI->getOperand(3).getReg() == 0 && 930 MI->isInvariantLoad(AA)) { 931 unsigned BaseReg = MI->getOperand(1).getReg(); 932 if (BaseReg == 0 || BaseReg == X86::RIP) 933 return true; 934 // Allow re-materialization of PIC load. 935 if (!ReMatPICStubLoad && MI->getOperand(4).isGlobal()) 936 return false; 937 const MachineFunction &MF = *MI->getParent()->getParent(); 938 const MachineRegisterInfo &MRI = MF.getRegInfo(); 939 bool isPICBase = false; 940 for (MachineRegisterInfo::def_iterator I = MRI.def_begin(BaseReg), 941 E = MRI.def_end(); I != E; ++I) { 942 MachineInstr *DefMI = I.getOperand().getParent(); 943 if (DefMI->getOpcode() != X86::MOVPC32r) 944 return false; 945 assert(!isPICBase && "More than one PIC base?"); 946 isPICBase = true; 947 } 948 return isPICBase; 949 } 950 return false; 951 } 952 953 case X86::LEA32r: 954 case X86::LEA64r: { 955 if (MI->getOperand(2).isImm() && 956 MI->getOperand(3).isReg() && MI->getOperand(3).getReg() == 0 && 957 !MI->getOperand(4).isReg()) { 958 // lea fi#, lea GV, etc. are all rematerializable. 959 if (!MI->getOperand(1).isReg()) 960 return true; 961 unsigned BaseReg = MI->getOperand(1).getReg(); 962 if (BaseReg == 0) 963 return true; 964 // Allow re-materialization of lea PICBase + x. 965 const MachineFunction &MF = *MI->getParent()->getParent(); 966 const MachineRegisterInfo &MRI = MF.getRegInfo(); 967 return regIsPICBase(BaseReg, MRI); 968 } 969 return false; 970 } 971 } 972 973 // All other instructions marked M_REMATERIALIZABLE are always trivially 974 // rematerializable. 975 return true; 976} 977 978/// isSafeToClobberEFLAGS - Return true if it's safe insert an instruction that 979/// would clobber the EFLAGS condition register. Note the result may be 980/// conservative. If it cannot definitely determine the safety after visiting 981/// a few instructions in each direction it assumes it's not safe. 982static bool isSafeToClobberEFLAGS(MachineBasicBlock &MBB, 983 MachineBasicBlock::iterator I) { 984 MachineBasicBlock::iterator E = MBB.end(); 985 986 // It's always safe to clobber EFLAGS at the end of a block. 987 if (I == E) 988 return true; 989 990 // For compile time consideration, if we are not able to determine the 991 // safety after visiting 4 instructions in each direction, we will assume 992 // it's not safe. 993 MachineBasicBlock::iterator Iter = I; 994 for (unsigned i = 0; i < 4; ++i) { 995 bool SeenDef = false; 996 for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) { 997 MachineOperand &MO = Iter->getOperand(j); 998 if (!MO.isReg()) 999 continue; 1000 if (MO.getReg() == X86::EFLAGS) { 1001 if (MO.isUse()) 1002 return false; 1003 SeenDef = true; 1004 } 1005 } 1006 1007 if (SeenDef) 1008 // This instruction defines EFLAGS, no need to look any further. 1009 return true; 1010 ++Iter; 1011 // Skip over DBG_VALUE. 1012 while (Iter != E && Iter->isDebugValue()) 1013 ++Iter; 1014 1015 // If we make it to the end of the block, it's safe to clobber EFLAGS. 1016 if (Iter == E) 1017 return true; 1018 } 1019 1020 MachineBasicBlock::iterator B = MBB.begin(); 1021 Iter = I; 1022 for (unsigned i = 0; i < 4; ++i) { 1023 // If we make it to the beginning of the block, it's safe to clobber 1024 // EFLAGS iff EFLAGS is not live-in. 1025 if (Iter == B) 1026 return !MBB.isLiveIn(X86::EFLAGS); 1027 1028 --Iter; 1029 // Skip over DBG_VALUE. 1030 while (Iter != B && Iter->isDebugValue()) 1031 --Iter; 1032 1033 bool SawKill = false; 1034 for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) { 1035 MachineOperand &MO = Iter->getOperand(j); 1036 if (MO.isReg() && MO.getReg() == X86::EFLAGS) { 1037 if (MO.isDef()) return MO.isDead(); 1038 if (MO.isKill()) SawKill = true; 1039 } 1040 } 1041 1042 if (SawKill) 1043 // This instruction kills EFLAGS and doesn't redefine it, so 1044 // there's no need to look further. 1045 return true; 1046 } 1047 1048 // Conservative answer. 1049 return false; 1050} 1051 1052void X86InstrInfo::reMaterialize(MachineBasicBlock &MBB, 1053 MachineBasicBlock::iterator I, 1054 unsigned DestReg, unsigned SubIdx, 1055 const MachineInstr *Orig, 1056 const TargetRegisterInfo &TRI) const { 1057 DebugLoc DL = Orig->getDebugLoc(); 1058 1059 // MOV32r0 etc. are implemented with xor which clobbers condition code. 1060 // Re-materialize them as movri instructions to avoid side effects. 1061 bool Clone = true; 1062 unsigned Opc = Orig->getOpcode(); 1063 switch (Opc) { 1064 default: break; 1065 case X86::MOV8r0: 1066 case X86::MOV16r0: 1067 case X86::MOV32r0: 1068 case X86::MOV64r0: { 1069 if (!isSafeToClobberEFLAGS(MBB, I)) { 1070 switch (Opc) { 1071 default: break; 1072 case X86::MOV8r0: Opc = X86::MOV8ri; break; 1073 case X86::MOV16r0: Opc = X86::MOV16ri; break; 1074 case X86::MOV32r0: Opc = X86::MOV32ri; break; 1075 case X86::MOV64r0: Opc = X86::MOV64ri64i32; break; 1076 } 1077 Clone = false; 1078 } 1079 break; 1080 } 1081 } 1082 1083 if (Clone) { 1084 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig); 1085 MBB.insert(I, MI); 1086 } else { 1087 BuildMI(MBB, I, DL, get(Opc)).addOperand(Orig->getOperand(0)).addImm(0); 1088 } 1089 1090 MachineInstr *NewMI = prior(I); 1091 NewMI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI); 1092} 1093 1094/// hasLiveCondCodeDef - True if MI has a condition code def, e.g. EFLAGS, that 1095/// is not marked dead. 1096static bool hasLiveCondCodeDef(MachineInstr *MI) { 1097 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 1098 MachineOperand &MO = MI->getOperand(i); 1099 if (MO.isReg() && MO.isDef() && 1100 MO.getReg() == X86::EFLAGS && !MO.isDead()) { 1101 return true; 1102 } 1103 } 1104 return false; 1105} 1106 1107/// convertToThreeAddressWithLEA - Helper for convertToThreeAddress when 1108/// 16-bit LEA is disabled, use 32-bit LEA to form 3-address code by promoting 1109/// to a 32-bit superregister and then truncating back down to a 16-bit 1110/// subregister. 1111MachineInstr * 1112X86InstrInfo::convertToThreeAddressWithLEA(unsigned MIOpc, 1113 MachineFunction::iterator &MFI, 1114 MachineBasicBlock::iterator &MBBI, 1115 LiveVariables *LV) const { 1116 MachineInstr *MI = MBBI; 1117 unsigned Dest = MI->getOperand(0).getReg(); 1118 unsigned Src = MI->getOperand(1).getReg(); 1119 bool isDead = MI->getOperand(0).isDead(); 1120 bool isKill = MI->getOperand(1).isKill(); 1121 1122 unsigned Opc = TM.getSubtarget<X86Subtarget>().is64Bit() 1123 ? X86::LEA64_32r : X86::LEA32r; 1124 MachineRegisterInfo &RegInfo = MFI->getParent()->getRegInfo(); 1125 unsigned leaInReg = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass); 1126 unsigned leaOutReg = RegInfo.createVirtualRegister(&X86::GR32RegClass); 1127 1128 // Build and insert into an implicit UNDEF value. This is OK because 1129 // well be shifting and then extracting the lower 16-bits. 1130 // This has the potential to cause partial register stall. e.g. 1131 // movw (%rbp,%rcx,2), %dx 1132 // leal -65(%rdx), %esi 1133 // But testing has shown this *does* help performance in 64-bit mode (at 1134 // least on modern x86 machines). 1135 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg); 1136 MachineInstr *InsMI = 1137 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(TargetOpcode::COPY)) 1138 .addReg(leaInReg, RegState::Define, X86::sub_16bit) 1139 .addReg(Src, getKillRegState(isKill)); 1140 1141 MachineInstrBuilder MIB = BuildMI(*MFI, MBBI, MI->getDebugLoc(), 1142 get(Opc), leaOutReg); 1143 switch (MIOpc) { 1144 default: 1145 llvm_unreachable(0); 1146 break; 1147 case X86::SHL16ri: { 1148 unsigned ShAmt = MI->getOperand(2).getImm(); 1149 MIB.addReg(0).addImm(1 << ShAmt) 1150 .addReg(leaInReg, RegState::Kill).addImm(0).addReg(0); 1151 break; 1152 } 1153 case X86::INC16r: 1154 case X86::INC64_16r: 1155 addRegOffset(MIB, leaInReg, true, 1); 1156 break; 1157 case X86::DEC16r: 1158 case X86::DEC64_16r: 1159 addRegOffset(MIB, leaInReg, true, -1); 1160 break; 1161 case X86::ADD16ri: 1162 case X86::ADD16ri8: 1163 case X86::ADD16ri_DB: 1164 case X86::ADD16ri8_DB: 1165 addRegOffset(MIB, leaInReg, true, MI->getOperand(2).getImm()); 1166 break; 1167 case X86::ADD16rr: 1168 case X86::ADD16rr_DB: { 1169 unsigned Src2 = MI->getOperand(2).getReg(); 1170 bool isKill2 = MI->getOperand(2).isKill(); 1171 unsigned leaInReg2 = 0; 1172 MachineInstr *InsMI2 = 0; 1173 if (Src == Src2) { 1174 // ADD16rr %reg1028<kill>, %reg1028 1175 // just a single insert_subreg. 1176 addRegReg(MIB, leaInReg, true, leaInReg, false); 1177 } else { 1178 leaInReg2 = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass); 1179 // Build and insert into an implicit UNDEF value. This is OK because 1180 // well be shifting and then extracting the lower 16-bits. 1181 BuildMI(*MFI, MIB, MI->getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg2); 1182 InsMI2 = 1183 BuildMI(*MFI, MIB, MI->getDebugLoc(), get(TargetOpcode::COPY)) 1184 .addReg(leaInReg2, RegState::Define, X86::sub_16bit) 1185 .addReg(Src2, getKillRegState(isKill2)); 1186 addRegReg(MIB, leaInReg, true, leaInReg2, true); 1187 } 1188 if (LV && isKill2 && InsMI2) 1189 LV->replaceKillInstruction(Src2, MI, InsMI2); 1190 break; 1191 } 1192 } 1193 1194 MachineInstr *NewMI = MIB; 1195 MachineInstr *ExtMI = 1196 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(TargetOpcode::COPY)) 1197 .addReg(Dest, RegState::Define | getDeadRegState(isDead)) 1198 .addReg(leaOutReg, RegState::Kill, X86::sub_16bit); 1199 1200 if (LV) { 1201 // Update live variables 1202 LV->getVarInfo(leaInReg).Kills.push_back(NewMI); 1203 LV->getVarInfo(leaOutReg).Kills.push_back(ExtMI); 1204 if (isKill) 1205 LV->replaceKillInstruction(Src, MI, InsMI); 1206 if (isDead) 1207 LV->replaceKillInstruction(Dest, MI, ExtMI); 1208 } 1209 1210 return ExtMI; 1211} 1212 1213/// convertToThreeAddress - This method must be implemented by targets that 1214/// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target 1215/// may be able to convert a two-address instruction into a true 1216/// three-address instruction on demand. This allows the X86 target (for 1217/// example) to convert ADD and SHL instructions into LEA instructions if they 1218/// would require register copies due to two-addressness. 1219/// 1220/// This method returns a null pointer if the transformation cannot be 1221/// performed, otherwise it returns the new instruction. 1222/// 1223MachineInstr * 1224X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI, 1225 MachineBasicBlock::iterator &MBBI, 1226 LiveVariables *LV) const { 1227 MachineInstr *MI = MBBI; 1228 MachineFunction &MF = *MI->getParent()->getParent(); 1229 // All instructions input are two-addr instructions. Get the known operands. 1230 unsigned Dest = MI->getOperand(0).getReg(); 1231 unsigned Src = MI->getOperand(1).getReg(); 1232 bool isDead = MI->getOperand(0).isDead(); 1233 bool isKill = MI->getOperand(1).isKill(); 1234 1235 MachineInstr *NewMI = NULL; 1236 // FIXME: 16-bit LEA's are really slow on Athlons, but not bad on P4's. When 1237 // we have better subtarget support, enable the 16-bit LEA generation here. 1238 // 16-bit LEA is also slow on Core2. 1239 bool DisableLEA16 = true; 1240 bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit(); 1241 1242 unsigned MIOpc = MI->getOpcode(); 1243 switch (MIOpc) { 1244 case X86::SHUFPSrri: { 1245 assert(MI->getNumOperands() == 4 && "Unknown shufps instruction!"); 1246 if (!TM.getSubtarget<X86Subtarget>().hasSSE2()) return 0; 1247 1248 unsigned B = MI->getOperand(1).getReg(); 1249 unsigned C = MI->getOperand(2).getReg(); 1250 if (B != C) return 0; 1251 unsigned A = MI->getOperand(0).getReg(); 1252 unsigned M = MI->getOperand(3).getImm(); 1253 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::PSHUFDri)) 1254 .addReg(A, RegState::Define | getDeadRegState(isDead)) 1255 .addReg(B, getKillRegState(isKill)).addImm(M); 1256 break; 1257 } 1258 case X86::SHL64ri: { 1259 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!"); 1260 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses 1261 // the flags produced by a shift yet, so this is safe. 1262 unsigned ShAmt = MI->getOperand(2).getImm(); 1263 if (ShAmt == 0 || ShAmt >= 4) return 0; 1264 1265 // LEA can't handle RSP. 1266 if (TargetRegisterInfo::isVirtualRegister(Src) && 1267 !MF.getRegInfo().constrainRegClass(Src, &X86::GR64_NOSPRegClass)) 1268 return 0; 1269 1270 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r)) 1271 .addReg(Dest, RegState::Define | getDeadRegState(isDead)) 1272 .addReg(0).addImm(1 << ShAmt) 1273 .addReg(Src, getKillRegState(isKill)) 1274 .addImm(0).addReg(0); 1275 break; 1276 } 1277 case X86::SHL32ri: { 1278 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!"); 1279 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses 1280 // the flags produced by a shift yet, so this is safe. 1281 unsigned ShAmt = MI->getOperand(2).getImm(); 1282 if (ShAmt == 0 || ShAmt >= 4) return 0; 1283 1284 // LEA can't handle ESP. 1285 if (TargetRegisterInfo::isVirtualRegister(Src) && 1286 !MF.getRegInfo().constrainRegClass(Src, &X86::GR32_NOSPRegClass)) 1287 return 0; 1288 1289 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r; 1290 NewMI = BuildMI(MF, MI->getDebugLoc(), get(Opc)) 1291 .addReg(Dest, RegState::Define | getDeadRegState(isDead)) 1292 .addReg(0).addImm(1 << ShAmt) 1293 .addReg(Src, getKillRegState(isKill)).addImm(0).addReg(0); 1294 break; 1295 } 1296 case X86::SHL16ri: { 1297 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!"); 1298 // NOTE: LEA doesn't produce flags like shift does, but LLVM never uses 1299 // the flags produced by a shift yet, so this is safe. 1300 unsigned ShAmt = MI->getOperand(2).getImm(); 1301 if (ShAmt == 0 || ShAmt >= 4) return 0; 1302 1303 if (DisableLEA16) 1304 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0; 1305 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r)) 1306 .addReg(Dest, RegState::Define | getDeadRegState(isDead)) 1307 .addReg(0).addImm(1 << ShAmt) 1308 .addReg(Src, getKillRegState(isKill)) 1309 .addImm(0).addReg(0); 1310 break; 1311 } 1312 default: { 1313 // The following opcodes also sets the condition code register(s). Only 1314 // convert them to equivalent lea if the condition code register def's 1315 // are dead! 1316 if (hasLiveCondCodeDef(MI)) 1317 return 0; 1318 1319 switch (MIOpc) { 1320 default: return 0; 1321 case X86::INC64r: 1322 case X86::INC32r: 1323 case X86::INC64_32r: { 1324 assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!"); 1325 unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r 1326 : (is64Bit ? X86::LEA64_32r : X86::LEA32r); 1327 1328 // LEA can't handle RSP. 1329 if (TargetRegisterInfo::isVirtualRegister(Src) && 1330 !MF.getRegInfo().constrainRegClass(Src, 1331 MIOpc == X86::INC64r ? X86::GR64_NOSPRegisterClass : 1332 X86::GR32_NOSPRegisterClass)) 1333 return 0; 1334 1335 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc)) 1336 .addReg(Dest, RegState::Define | 1337 getDeadRegState(isDead)), 1338 Src, isKill, 1); 1339 break; 1340 } 1341 case X86::INC16r: 1342 case X86::INC64_16r: 1343 if (DisableLEA16) 1344 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0; 1345 assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!"); 1346 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r)) 1347 .addReg(Dest, RegState::Define | 1348 getDeadRegState(isDead)), 1349 Src, isKill, 1); 1350 break; 1351 case X86::DEC64r: 1352 case X86::DEC32r: 1353 case X86::DEC64_32r: { 1354 assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!"); 1355 unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r 1356 : (is64Bit ? X86::LEA64_32r : X86::LEA32r); 1357 // LEA can't handle RSP. 1358 if (TargetRegisterInfo::isVirtualRegister(Src) && 1359 !MF.getRegInfo().constrainRegClass(Src, 1360 MIOpc == X86::DEC64r ? X86::GR64_NOSPRegisterClass : 1361 X86::GR32_NOSPRegisterClass)) 1362 return 0; 1363 1364 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc)) 1365 .addReg(Dest, RegState::Define | 1366 getDeadRegState(isDead)), 1367 Src, isKill, -1); 1368 break; 1369 } 1370 case X86::DEC16r: 1371 case X86::DEC64_16r: 1372 if (DisableLEA16) 1373 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0; 1374 assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!"); 1375 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r)) 1376 .addReg(Dest, RegState::Define | 1377 getDeadRegState(isDead)), 1378 Src, isKill, -1); 1379 break; 1380 case X86::ADD64rr: 1381 case X86::ADD64rr_DB: 1382 case X86::ADD32rr: 1383 case X86::ADD32rr_DB: { 1384 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!"); 1385 unsigned Opc; 1386 TargetRegisterClass *RC; 1387 if (MIOpc == X86::ADD64rr || MIOpc == X86::ADD64rr_DB) { 1388 Opc = X86::LEA64r; 1389 RC = X86::GR64_NOSPRegisterClass; 1390 } else { 1391 Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r; 1392 RC = X86::GR32_NOSPRegisterClass; 1393 } 1394 1395 1396 unsigned Src2 = MI->getOperand(2).getReg(); 1397 bool isKill2 = MI->getOperand(2).isKill(); 1398 1399 // LEA can't handle RSP. 1400 if (TargetRegisterInfo::isVirtualRegister(Src2) && 1401 !MF.getRegInfo().constrainRegClass(Src2, RC)) 1402 return 0; 1403 1404 NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(Opc)) 1405 .addReg(Dest, RegState::Define | 1406 getDeadRegState(isDead)), 1407 Src, isKill, Src2, isKill2); 1408 if (LV && isKill2) 1409 LV->replaceKillInstruction(Src2, MI, NewMI); 1410 break; 1411 } 1412 case X86::ADD16rr: 1413 case X86::ADD16rr_DB: { 1414 if (DisableLEA16) 1415 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0; 1416 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!"); 1417 unsigned Src2 = MI->getOperand(2).getReg(); 1418 bool isKill2 = MI->getOperand(2).isKill(); 1419 NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r)) 1420 .addReg(Dest, RegState::Define | 1421 getDeadRegState(isDead)), 1422 Src, isKill, Src2, isKill2); 1423 if (LV && isKill2) 1424 LV->replaceKillInstruction(Src2, MI, NewMI); 1425 break; 1426 } 1427 case X86::ADD64ri32: 1428 case X86::ADD64ri8: 1429 case X86::ADD64ri32_DB: 1430 case X86::ADD64ri8_DB: 1431 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!"); 1432 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r)) 1433 .addReg(Dest, RegState::Define | 1434 getDeadRegState(isDead)), 1435 Src, isKill, MI->getOperand(2).getImm()); 1436 break; 1437 case X86::ADD32ri: 1438 case X86::ADD32ri8: 1439 case X86::ADD32ri_DB: 1440 case X86::ADD32ri8_DB: { 1441 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!"); 1442 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r; 1443 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc)) 1444 .addReg(Dest, RegState::Define | 1445 getDeadRegState(isDead)), 1446 Src, isKill, MI->getOperand(2).getImm()); 1447 break; 1448 } 1449 case X86::ADD16ri: 1450 case X86::ADD16ri8: 1451 case X86::ADD16ri_DB: 1452 case X86::ADD16ri8_DB: 1453 if (DisableLEA16) 1454 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0; 1455 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!"); 1456 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r)) 1457 .addReg(Dest, RegState::Define | 1458 getDeadRegState(isDead)), 1459 Src, isKill, MI->getOperand(2).getImm()); 1460 break; 1461 } 1462 } 1463 } 1464 1465 if (!NewMI) return 0; 1466 1467 if (LV) { // Update live variables 1468 if (isKill) 1469 LV->replaceKillInstruction(Src, MI, NewMI); 1470 if (isDead) 1471 LV->replaceKillInstruction(Dest, MI, NewMI); 1472 } 1473 1474 MFI->insert(MBBI, NewMI); // Insert the new inst 1475 return NewMI; 1476} 1477 1478/// commuteInstruction - We have a few instructions that must be hacked on to 1479/// commute them. 1480/// 1481MachineInstr * 1482X86InstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const { 1483 switch (MI->getOpcode()) { 1484 case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I) 1485 case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I) 1486 case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I) 1487 case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I) 1488 case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I -> A = SHLD64rri8 C, B, (64-I) 1489 case X86::SHLD64rri8:{// A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, (64-I) 1490 unsigned Opc; 1491 unsigned Size; 1492 switch (MI->getOpcode()) { 1493 default: llvm_unreachable("Unreachable!"); 1494 case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break; 1495 case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break; 1496 case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break; 1497 case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break; 1498 case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break; 1499 case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break; 1500 } 1501 unsigned Amt = MI->getOperand(3).getImm(); 1502 if (NewMI) { 1503 MachineFunction &MF = *MI->getParent()->getParent(); 1504 MI = MF.CloneMachineInstr(MI); 1505 NewMI = false; 1506 } 1507 MI->setDesc(get(Opc)); 1508 MI->getOperand(3).setImm(Size-Amt); 1509 return TargetInstrInfoImpl::commuteInstruction(MI, NewMI); 1510 } 1511 case X86::CMOVB16rr: 1512 case X86::CMOVB32rr: 1513 case X86::CMOVB64rr: 1514 case X86::CMOVAE16rr: 1515 case X86::CMOVAE32rr: 1516 case X86::CMOVAE64rr: 1517 case X86::CMOVE16rr: 1518 case X86::CMOVE32rr: 1519 case X86::CMOVE64rr: 1520 case X86::CMOVNE16rr: 1521 case X86::CMOVNE32rr: 1522 case X86::CMOVNE64rr: 1523 case X86::CMOVBE16rr: 1524 case X86::CMOVBE32rr: 1525 case X86::CMOVBE64rr: 1526 case X86::CMOVA16rr: 1527 case X86::CMOVA32rr: 1528 case X86::CMOVA64rr: 1529 case X86::CMOVL16rr: 1530 case X86::CMOVL32rr: 1531 case X86::CMOVL64rr: 1532 case X86::CMOVGE16rr: 1533 case X86::CMOVGE32rr: 1534 case X86::CMOVGE64rr: 1535 case X86::CMOVLE16rr: 1536 case X86::CMOVLE32rr: 1537 case X86::CMOVLE64rr: 1538 case X86::CMOVG16rr: 1539 case X86::CMOVG32rr: 1540 case X86::CMOVG64rr: 1541 case X86::CMOVS16rr: 1542 case X86::CMOVS32rr: 1543 case X86::CMOVS64rr: 1544 case X86::CMOVNS16rr: 1545 case X86::CMOVNS32rr: 1546 case X86::CMOVNS64rr: 1547 case X86::CMOVP16rr: 1548 case X86::CMOVP32rr: 1549 case X86::CMOVP64rr: 1550 case X86::CMOVNP16rr: 1551 case X86::CMOVNP32rr: 1552 case X86::CMOVNP64rr: 1553 case X86::CMOVO16rr: 1554 case X86::CMOVO32rr: 1555 case X86::CMOVO64rr: 1556 case X86::CMOVNO16rr: 1557 case X86::CMOVNO32rr: 1558 case X86::CMOVNO64rr: { 1559 unsigned Opc = 0; 1560 switch (MI->getOpcode()) { 1561 default: break; 1562 case X86::CMOVB16rr: Opc = X86::CMOVAE16rr; break; 1563 case X86::CMOVB32rr: Opc = X86::CMOVAE32rr; break; 1564 case X86::CMOVB64rr: Opc = X86::CMOVAE64rr; break; 1565 case X86::CMOVAE16rr: Opc = X86::CMOVB16rr; break; 1566 case X86::CMOVAE32rr: Opc = X86::CMOVB32rr; break; 1567 case X86::CMOVAE64rr: Opc = X86::CMOVB64rr; break; 1568 case X86::CMOVE16rr: Opc = X86::CMOVNE16rr; break; 1569 case X86::CMOVE32rr: Opc = X86::CMOVNE32rr; break; 1570 case X86::CMOVE64rr: Opc = X86::CMOVNE64rr; break; 1571 case X86::CMOVNE16rr: Opc = X86::CMOVE16rr; break; 1572 case X86::CMOVNE32rr: Opc = X86::CMOVE32rr; break; 1573 case X86::CMOVNE64rr: Opc = X86::CMOVE64rr; break; 1574 case X86::CMOVBE16rr: Opc = X86::CMOVA16rr; break; 1575 case X86::CMOVBE32rr: Opc = X86::CMOVA32rr; break; 1576 case X86::CMOVBE64rr: Opc = X86::CMOVA64rr; break; 1577 case X86::CMOVA16rr: Opc = X86::CMOVBE16rr; break; 1578 case X86::CMOVA32rr: Opc = X86::CMOVBE32rr; break; 1579 case X86::CMOVA64rr: Opc = X86::CMOVBE64rr; break; 1580 case X86::CMOVL16rr: Opc = X86::CMOVGE16rr; break; 1581 case X86::CMOVL32rr: Opc = X86::CMOVGE32rr; break; 1582 case X86::CMOVL64rr: Opc = X86::CMOVGE64rr; break; 1583 case X86::CMOVGE16rr: Opc = X86::CMOVL16rr; break; 1584 case X86::CMOVGE32rr: Opc = X86::CMOVL32rr; break; 1585 case X86::CMOVGE64rr: Opc = X86::CMOVL64rr; break; 1586 case X86::CMOVLE16rr: Opc = X86::CMOVG16rr; break; 1587 case X86::CMOVLE32rr: Opc = X86::CMOVG32rr; break; 1588 case X86::CMOVLE64rr: Opc = X86::CMOVG64rr; break; 1589 case X86::CMOVG16rr: Opc = X86::CMOVLE16rr; break; 1590 case X86::CMOVG32rr: Opc = X86::CMOVLE32rr; break; 1591 case X86::CMOVG64rr: Opc = X86::CMOVLE64rr; break; 1592 case X86::CMOVS16rr: Opc = X86::CMOVNS16rr; break; 1593 case X86::CMOVS32rr: Opc = X86::CMOVNS32rr; break; 1594 case X86::CMOVS64rr: Opc = X86::CMOVNS64rr; break; 1595 case X86::CMOVNS16rr: Opc = X86::CMOVS16rr; break; 1596 case X86::CMOVNS32rr: Opc = X86::CMOVS32rr; break; 1597 case X86::CMOVNS64rr: Opc = X86::CMOVS64rr; break; 1598 case X86::CMOVP16rr: Opc = X86::CMOVNP16rr; break; 1599 case X86::CMOVP32rr: Opc = X86::CMOVNP32rr; break; 1600 case X86::CMOVP64rr: Opc = X86::CMOVNP64rr; break; 1601 case X86::CMOVNP16rr: Opc = X86::CMOVP16rr; break; 1602 case X86::CMOVNP32rr: Opc = X86::CMOVP32rr; break; 1603 case X86::CMOVNP64rr: Opc = X86::CMOVP64rr; break; 1604 case X86::CMOVO16rr: Opc = X86::CMOVNO16rr; break; 1605 case X86::CMOVO32rr: Opc = X86::CMOVNO32rr; break; 1606 case X86::CMOVO64rr: Opc = X86::CMOVNO64rr; break; 1607 case X86::CMOVNO16rr: Opc = X86::CMOVO16rr; break; 1608 case X86::CMOVNO32rr: Opc = X86::CMOVO32rr; break; 1609 case X86::CMOVNO64rr: Opc = X86::CMOVO64rr; break; 1610 } 1611 if (NewMI) { 1612 MachineFunction &MF = *MI->getParent()->getParent(); 1613 MI = MF.CloneMachineInstr(MI); 1614 NewMI = false; 1615 } 1616 MI->setDesc(get(Opc)); 1617 // Fallthrough intended. 1618 } 1619 default: 1620 return TargetInstrInfoImpl::commuteInstruction(MI, NewMI); 1621 } 1622} 1623 1624static X86::CondCode GetCondFromBranchOpc(unsigned BrOpc) { 1625 switch (BrOpc) { 1626 default: return X86::COND_INVALID; 1627 case X86::JE_4: return X86::COND_E; 1628 case X86::JNE_4: return X86::COND_NE; 1629 case X86::JL_4: return X86::COND_L; 1630 case X86::JLE_4: return X86::COND_LE; 1631 case X86::JG_4: return X86::COND_G; 1632 case X86::JGE_4: return X86::COND_GE; 1633 case X86::JB_4: return X86::COND_B; 1634 case X86::JBE_4: return X86::COND_BE; 1635 case X86::JA_4: return X86::COND_A; 1636 case X86::JAE_4: return X86::COND_AE; 1637 case X86::JS_4: return X86::COND_S; 1638 case X86::JNS_4: return X86::COND_NS; 1639 case X86::JP_4: return X86::COND_P; 1640 case X86::JNP_4: return X86::COND_NP; 1641 case X86::JO_4: return X86::COND_O; 1642 case X86::JNO_4: return X86::COND_NO; 1643 } 1644} 1645 1646unsigned X86::GetCondBranchFromCond(X86::CondCode CC) { 1647 switch (CC) { 1648 default: llvm_unreachable("Illegal condition code!"); 1649 case X86::COND_E: return X86::JE_4; 1650 case X86::COND_NE: return X86::JNE_4; 1651 case X86::COND_L: return X86::JL_4; 1652 case X86::COND_LE: return X86::JLE_4; 1653 case X86::COND_G: return X86::JG_4; 1654 case X86::COND_GE: return X86::JGE_4; 1655 case X86::COND_B: return X86::JB_4; 1656 case X86::COND_BE: return X86::JBE_4; 1657 case X86::COND_A: return X86::JA_4; 1658 case X86::COND_AE: return X86::JAE_4; 1659 case X86::COND_S: return X86::JS_4; 1660 case X86::COND_NS: return X86::JNS_4; 1661 case X86::COND_P: return X86::JP_4; 1662 case X86::COND_NP: return X86::JNP_4; 1663 case X86::COND_O: return X86::JO_4; 1664 case X86::COND_NO: return X86::JNO_4; 1665 } 1666} 1667 1668/// GetOppositeBranchCondition - Return the inverse of the specified condition, 1669/// e.g. turning COND_E to COND_NE. 1670X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) { 1671 switch (CC) { 1672 default: llvm_unreachable("Illegal condition code!"); 1673 case X86::COND_E: return X86::COND_NE; 1674 case X86::COND_NE: return X86::COND_E; 1675 case X86::COND_L: return X86::COND_GE; 1676 case X86::COND_LE: return X86::COND_G; 1677 case X86::COND_G: return X86::COND_LE; 1678 case X86::COND_GE: return X86::COND_L; 1679 case X86::COND_B: return X86::COND_AE; 1680 case X86::COND_BE: return X86::COND_A; 1681 case X86::COND_A: return X86::COND_BE; 1682 case X86::COND_AE: return X86::COND_B; 1683 case X86::COND_S: return X86::COND_NS; 1684 case X86::COND_NS: return X86::COND_S; 1685 case X86::COND_P: return X86::COND_NP; 1686 case X86::COND_NP: return X86::COND_P; 1687 case X86::COND_O: return X86::COND_NO; 1688 case X86::COND_NO: return X86::COND_O; 1689 } 1690} 1691 1692bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const { 1693 const TargetInstrDesc &TID = MI->getDesc(); 1694 if (!TID.isTerminator()) return false; 1695 1696 // Conditional branch is a special case. 1697 if (TID.isBranch() && !TID.isBarrier()) 1698 return true; 1699 if (!TID.isPredicable()) 1700 return true; 1701 return !isPredicated(MI); 1702} 1703 1704bool X86InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, 1705 MachineBasicBlock *&TBB, 1706 MachineBasicBlock *&FBB, 1707 SmallVectorImpl<MachineOperand> &Cond, 1708 bool AllowModify) const { 1709 // Start from the bottom of the block and work up, examining the 1710 // terminator instructions. 1711 MachineBasicBlock::iterator I = MBB.end(); 1712 MachineBasicBlock::iterator UnCondBrIter = MBB.end(); 1713 while (I != MBB.begin()) { 1714 --I; 1715 if (I->isDebugValue()) 1716 continue; 1717 1718 // Working from the bottom, when we see a non-terminator instruction, we're 1719 // done. 1720 if (!isUnpredicatedTerminator(I)) 1721 break; 1722 1723 // A terminator that isn't a branch can't easily be handled by this 1724 // analysis. 1725 if (!I->getDesc().isBranch()) 1726 return true; 1727 1728 // Handle unconditional branches. 1729 if (I->getOpcode() == X86::JMP_4) { 1730 UnCondBrIter = I; 1731 1732 if (!AllowModify) { 1733 TBB = I->getOperand(0).getMBB(); 1734 continue; 1735 } 1736 1737 // If the block has any instructions after a JMP, delete them. 1738 while (llvm::next(I) != MBB.end()) 1739 llvm::next(I)->eraseFromParent(); 1740 1741 Cond.clear(); 1742 FBB = 0; 1743 1744 // Delete the JMP if it's equivalent to a fall-through. 1745 if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) { 1746 TBB = 0; 1747 I->eraseFromParent(); 1748 I = MBB.end(); 1749 UnCondBrIter = MBB.end(); 1750 continue; 1751 } 1752 1753 // TBB is used to indicate the unconditional destination. 1754 TBB = I->getOperand(0).getMBB(); 1755 continue; 1756 } 1757 1758 // Handle conditional branches. 1759 X86::CondCode BranchCode = GetCondFromBranchOpc(I->getOpcode()); 1760 if (BranchCode == X86::COND_INVALID) 1761 return true; // Can't handle indirect branch. 1762 1763 // Working from the bottom, handle the first conditional branch. 1764 if (Cond.empty()) { 1765 MachineBasicBlock *TargetBB = I->getOperand(0).getMBB(); 1766 if (AllowModify && UnCondBrIter != MBB.end() && 1767 MBB.isLayoutSuccessor(TargetBB)) { 1768 // If we can modify the code and it ends in something like: 1769 // 1770 // jCC L1 1771 // jmp L2 1772 // L1: 1773 // ... 1774 // L2: 1775 // 1776 // Then we can change this to: 1777 // 1778 // jnCC L2 1779 // L1: 1780 // ... 1781 // L2: 1782 // 1783 // Which is a bit more efficient. 1784 // We conditionally jump to the fall-through block. 1785 BranchCode = GetOppositeBranchCondition(BranchCode); 1786 unsigned JNCC = GetCondBranchFromCond(BranchCode); 1787 MachineBasicBlock::iterator OldInst = I; 1788 1789 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(JNCC)) 1790 .addMBB(UnCondBrIter->getOperand(0).getMBB()); 1791 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(X86::JMP_4)) 1792 .addMBB(TargetBB); 1793 MBB.addSuccessor(TargetBB); 1794 1795 OldInst->eraseFromParent(); 1796 UnCondBrIter->eraseFromParent(); 1797 1798 // Restart the analysis. 1799 UnCondBrIter = MBB.end(); 1800 I = MBB.end(); 1801 continue; 1802 } 1803 1804 FBB = TBB; 1805 TBB = I->getOperand(0).getMBB(); 1806 Cond.push_back(MachineOperand::CreateImm(BranchCode)); 1807 continue; 1808 } 1809 1810 // Handle subsequent conditional branches. Only handle the case where all 1811 // conditional branches branch to the same destination and their condition 1812 // opcodes fit one of the special multi-branch idioms. 1813 assert(Cond.size() == 1); 1814 assert(TBB); 1815 1816 // Only handle the case where all conditional branches branch to the same 1817 // destination. 1818 if (TBB != I->getOperand(0).getMBB()) 1819 return true; 1820 1821 // If the conditions are the same, we can leave them alone. 1822 X86::CondCode OldBranchCode = (X86::CondCode)Cond[0].getImm(); 1823 if (OldBranchCode == BranchCode) 1824 continue; 1825 1826 // If they differ, see if they fit one of the known patterns. Theoretically, 1827 // we could handle more patterns here, but we shouldn't expect to see them 1828 // if instruction selection has done a reasonable job. 1829 if ((OldBranchCode == X86::COND_NP && 1830 BranchCode == X86::COND_E) || 1831 (OldBranchCode == X86::COND_E && 1832 BranchCode == X86::COND_NP)) 1833 BranchCode = X86::COND_NP_OR_E; 1834 else if ((OldBranchCode == X86::COND_P && 1835 BranchCode == X86::COND_NE) || 1836 (OldBranchCode == X86::COND_NE && 1837 BranchCode == X86::COND_P)) 1838 BranchCode = X86::COND_NE_OR_P; 1839 else 1840 return true; 1841 1842 // Update the MachineOperand. 1843 Cond[0].setImm(BranchCode); 1844 } 1845 1846 return false; 1847} 1848 1849unsigned X86InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const { 1850 MachineBasicBlock::iterator I = MBB.end(); 1851 unsigned Count = 0; 1852 1853 while (I != MBB.begin()) { 1854 --I; 1855 if (I->isDebugValue()) 1856 continue; 1857 if (I->getOpcode() != X86::JMP_4 && 1858 GetCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID) 1859 break; 1860 // Remove the branch. 1861 I->eraseFromParent(); 1862 I = MBB.end(); 1863 ++Count; 1864 } 1865 1866 return Count; 1867} 1868 1869unsigned 1870X86InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 1871 MachineBasicBlock *FBB, 1872 const SmallVectorImpl<MachineOperand> &Cond, 1873 DebugLoc DL) const { 1874 // Shouldn't be a fall through. 1875 assert(TBB && "InsertBranch must not be told to insert a fallthrough"); 1876 assert((Cond.size() == 1 || Cond.size() == 0) && 1877 "X86 branch conditions have one component!"); 1878 1879 if (Cond.empty()) { 1880 // Unconditional branch? 1881 assert(!FBB && "Unconditional branch with multiple successors!"); 1882 BuildMI(&MBB, DL, get(X86::JMP_4)).addMBB(TBB); 1883 return 1; 1884 } 1885 1886 // Conditional branch. 1887 unsigned Count = 0; 1888 X86::CondCode CC = (X86::CondCode)Cond[0].getImm(); 1889 switch (CC) { 1890 case X86::COND_NP_OR_E: 1891 // Synthesize NP_OR_E with two branches. 1892 BuildMI(&MBB, DL, get(X86::JNP_4)).addMBB(TBB); 1893 ++Count; 1894 BuildMI(&MBB, DL, get(X86::JE_4)).addMBB(TBB); 1895 ++Count; 1896 break; 1897 case X86::COND_NE_OR_P: 1898 // Synthesize NE_OR_P with two branches. 1899 BuildMI(&MBB, DL, get(X86::JNE_4)).addMBB(TBB); 1900 ++Count; 1901 BuildMI(&MBB, DL, get(X86::JP_4)).addMBB(TBB); 1902 ++Count; 1903 break; 1904 default: { 1905 unsigned Opc = GetCondBranchFromCond(CC); 1906 BuildMI(&MBB, DL, get(Opc)).addMBB(TBB); 1907 ++Count; 1908 } 1909 } 1910 if (FBB) { 1911 // Two-way Conditional branch. Insert the second branch. 1912 BuildMI(&MBB, DL, get(X86::JMP_4)).addMBB(FBB); 1913 ++Count; 1914 } 1915 return Count; 1916} 1917 1918/// isHReg - Test if the given register is a physical h register. 1919static bool isHReg(unsigned Reg) { 1920 return X86::GR8_ABCD_HRegClass.contains(Reg); 1921} 1922 1923// Try and copy between VR128/VR64 and GR64 registers. 1924static unsigned CopyToFromAsymmetricReg(unsigned DestReg, unsigned SrcReg) { 1925 // SrcReg(VR128) -> DestReg(GR64) 1926 // SrcReg(VR64) -> DestReg(GR64) 1927 // SrcReg(GR64) -> DestReg(VR128) 1928 // SrcReg(GR64) -> DestReg(VR64) 1929 1930 if (X86::GR64RegClass.contains(DestReg)) { 1931 if (X86::VR128RegClass.contains(SrcReg)) { 1932 // Copy from a VR128 register to a GR64 register. 1933 return X86::MOVPQIto64rr; 1934 } else if (X86::VR64RegClass.contains(SrcReg)) { 1935 // Copy from a VR64 register to a GR64 register. 1936 return X86::MOVSDto64rr; 1937 } 1938 } else if (X86::GR64RegClass.contains(SrcReg)) { 1939 // Copy from a GR64 register to a VR128 register. 1940 if (X86::VR128RegClass.contains(DestReg)) 1941 return X86::MOV64toPQIrr; 1942 // Copy from a GR64 register to a VR64 register. 1943 else if (X86::VR64RegClass.contains(DestReg)) 1944 return X86::MOV64toSDrr; 1945 } 1946 1947 return 0; 1948} 1949 1950void X86InstrInfo::copyPhysReg(MachineBasicBlock &MBB, 1951 MachineBasicBlock::iterator MI, DebugLoc DL, 1952 unsigned DestReg, unsigned SrcReg, 1953 bool KillSrc) const { 1954 // First deal with the normal symmetric copies. 1955 unsigned Opc = 0; 1956 if (X86::GR64RegClass.contains(DestReg, SrcReg)) 1957 Opc = X86::MOV64rr; 1958 else if (X86::GR32RegClass.contains(DestReg, SrcReg)) 1959 Opc = X86::MOV32rr; 1960 else if (X86::GR16RegClass.contains(DestReg, SrcReg)) 1961 Opc = X86::MOV16rr; 1962 else if (X86::GR8RegClass.contains(DestReg, SrcReg)) { 1963 // Copying to or from a physical H register on x86-64 requires a NOREX 1964 // move. Otherwise use a normal move. 1965 if ((isHReg(DestReg) || isHReg(SrcReg)) && 1966 TM.getSubtarget<X86Subtarget>().is64Bit()) 1967 Opc = X86::MOV8rr_NOREX; 1968 else 1969 Opc = X86::MOV8rr; 1970 } else if (X86::VR128RegClass.contains(DestReg, SrcReg)) 1971 Opc = X86::MOVAPSrr; 1972 else if (X86::VR64RegClass.contains(DestReg, SrcReg)) 1973 Opc = X86::MMX_MOVQ64rr; 1974 else 1975 Opc = CopyToFromAsymmetricReg(DestReg, SrcReg); 1976 1977 if (Opc) { 1978 BuildMI(MBB, MI, DL, get(Opc), DestReg) 1979 .addReg(SrcReg, getKillRegState(KillSrc)); 1980 return; 1981 } 1982 1983 // Moving EFLAGS to / from another register requires a push and a pop. 1984 if (SrcReg == X86::EFLAGS) { 1985 if (X86::GR64RegClass.contains(DestReg)) { 1986 BuildMI(MBB, MI, DL, get(X86::PUSHF64)); 1987 BuildMI(MBB, MI, DL, get(X86::POP64r), DestReg); 1988 return; 1989 } else if (X86::GR32RegClass.contains(DestReg)) { 1990 BuildMI(MBB, MI, DL, get(X86::PUSHF32)); 1991 BuildMI(MBB, MI, DL, get(X86::POP32r), DestReg); 1992 return; 1993 } 1994 } 1995 if (DestReg == X86::EFLAGS) { 1996 if (X86::GR64RegClass.contains(SrcReg)) { 1997 BuildMI(MBB, MI, DL, get(X86::PUSH64r)) 1998 .addReg(SrcReg, getKillRegState(KillSrc)); 1999 BuildMI(MBB, MI, DL, get(X86::POPF64)); 2000 return; 2001 } else if (X86::GR32RegClass.contains(SrcReg)) { 2002 BuildMI(MBB, MI, DL, get(X86::PUSH32r)) 2003 .addReg(SrcReg, getKillRegState(KillSrc)); 2004 BuildMI(MBB, MI, DL, get(X86::POPF32)); 2005 return; 2006 } 2007 } 2008 2009 DEBUG(dbgs() << "Cannot copy " << RI.getName(SrcReg) 2010 << " to " << RI.getName(DestReg) << '\n'); 2011 llvm_unreachable("Cannot emit physreg copy instruction"); 2012} 2013 2014static unsigned getLoadStoreRegOpcode(unsigned Reg, 2015 const TargetRegisterClass *RC, 2016 bool isStackAligned, 2017 const TargetMachine &TM, 2018 bool load) { 2019 switch (RC->getID()) { 2020 default: 2021 llvm_unreachable("Unknown regclass"); 2022 case X86::GR64RegClassID: 2023 case X86::GR64_ABCDRegClassID: 2024 case X86::GR64_NOREXRegClassID: 2025 case X86::GR64_NOREX_NOSPRegClassID: 2026 case X86::GR64_NOSPRegClassID: 2027 case X86::GR64_TCRegClassID: 2028 case X86::GR64_TCW64RegClassID: 2029 return load ? X86::MOV64rm : X86::MOV64mr; 2030 case X86::GR32RegClassID: 2031 case X86::GR32_ABCDRegClassID: 2032 case X86::GR32_ADRegClassID: 2033 case X86::GR32_NOREXRegClassID: 2034 case X86::GR32_NOSPRegClassID: 2035 case X86::GR32_TCRegClassID: 2036 return load ? X86::MOV32rm : X86::MOV32mr; 2037 case X86::GR16RegClassID: 2038 case X86::GR16_ABCDRegClassID: 2039 case X86::GR16_NOREXRegClassID: 2040 return load ? X86::MOV16rm : X86::MOV16mr; 2041 case X86::GR8RegClassID: 2042 // Copying to or from a physical H register on x86-64 requires a NOREX 2043 // move. Otherwise use a normal move. 2044 if (isHReg(Reg) && 2045 TM.getSubtarget<X86Subtarget>().is64Bit()) 2046 return load ? X86::MOV8rm_NOREX : X86::MOV8mr_NOREX; 2047 else 2048 return load ? X86::MOV8rm : X86::MOV8mr; 2049 case X86::GR8_ABCD_LRegClassID: 2050 case X86::GR8_NOREXRegClassID: 2051 return load ? X86::MOV8rm :X86::MOV8mr; 2052 case X86::GR8_ABCD_HRegClassID: 2053 if (TM.getSubtarget<X86Subtarget>().is64Bit()) 2054 return load ? X86::MOV8rm_NOREX : X86::MOV8mr_NOREX; 2055 else 2056 return load ? X86::MOV8rm : X86::MOV8mr; 2057 case X86::RFP80RegClassID: 2058 return load ? X86::LD_Fp80m : X86::ST_FpP80m; 2059 case X86::RFP64RegClassID: 2060 return load ? X86::LD_Fp64m : X86::ST_Fp64m; 2061 case X86::RFP32RegClassID: 2062 return load ? X86::LD_Fp32m : X86::ST_Fp32m; 2063 case X86::FR32RegClassID: 2064 return load ? X86::MOVSSrm : X86::MOVSSmr; 2065 case X86::FR64RegClassID: 2066 return load ? X86::MOVSDrm : X86::MOVSDmr; 2067 case X86::VR128RegClassID: 2068 // If stack is realigned we can use aligned stores. 2069 if (isStackAligned) 2070 return load ? X86::MOVAPSrm : X86::MOVAPSmr; 2071 else 2072 return load ? X86::MOVUPSrm : X86::MOVUPSmr; 2073 case X86::VR64RegClassID: 2074 return load ? X86::MMX_MOVQ64rm : X86::MMX_MOVQ64mr; 2075 } 2076} 2077 2078static unsigned getStoreRegOpcode(unsigned SrcReg, 2079 const TargetRegisterClass *RC, 2080 bool isStackAligned, 2081 TargetMachine &TM) { 2082 return getLoadStoreRegOpcode(SrcReg, RC, isStackAligned, TM, false); 2083} 2084 2085 2086static unsigned getLoadRegOpcode(unsigned DestReg, 2087 const TargetRegisterClass *RC, 2088 bool isStackAligned, 2089 const TargetMachine &TM) { 2090 return getLoadStoreRegOpcode(DestReg, RC, isStackAligned, TM, true); 2091} 2092 2093void X86InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, 2094 MachineBasicBlock::iterator MI, 2095 unsigned SrcReg, bool isKill, int FrameIdx, 2096 const TargetRegisterClass *RC, 2097 const TargetRegisterInfo *TRI) const { 2098 const MachineFunction &MF = *MBB.getParent(); 2099 assert(MF.getFrameInfo()->getObjectSize(FrameIdx) >= RC->getSize() && 2100 "Stack slot too small for store"); 2101 bool isAligned = (RI.getStackAlignment() >= 16) || RI.canRealignStack(MF); 2102 unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, TM); 2103 DebugLoc DL = MBB.findDebugLoc(MI); 2104 addFrameReference(BuildMI(MBB, MI, DL, get(Opc)), FrameIdx) 2105 .addReg(SrcReg, getKillRegState(isKill)); 2106} 2107 2108void X86InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, 2109 bool isKill, 2110 SmallVectorImpl<MachineOperand> &Addr, 2111 const TargetRegisterClass *RC, 2112 MachineInstr::mmo_iterator MMOBegin, 2113 MachineInstr::mmo_iterator MMOEnd, 2114 SmallVectorImpl<MachineInstr*> &NewMIs) const { 2115 bool isAligned = MMOBegin != MMOEnd && (*MMOBegin)->getAlignment() >= 16; 2116 unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, TM); 2117 DebugLoc DL; 2118 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc)); 2119 for (unsigned i = 0, e = Addr.size(); i != e; ++i) 2120 MIB.addOperand(Addr[i]); 2121 MIB.addReg(SrcReg, getKillRegState(isKill)); 2122 (*MIB).setMemRefs(MMOBegin, MMOEnd); 2123 NewMIs.push_back(MIB); 2124} 2125 2126 2127void X86InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, 2128 MachineBasicBlock::iterator MI, 2129 unsigned DestReg, int FrameIdx, 2130 const TargetRegisterClass *RC, 2131 const TargetRegisterInfo *TRI) const { 2132 const MachineFunction &MF = *MBB.getParent(); 2133 bool isAligned = (RI.getStackAlignment() >= 16) || RI.canRealignStack(MF); 2134 unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, TM); 2135 DebugLoc DL = MBB.findDebugLoc(MI); 2136 addFrameReference(BuildMI(MBB, MI, DL, get(Opc), DestReg), FrameIdx); 2137} 2138 2139void X86InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg, 2140 SmallVectorImpl<MachineOperand> &Addr, 2141 const TargetRegisterClass *RC, 2142 MachineInstr::mmo_iterator MMOBegin, 2143 MachineInstr::mmo_iterator MMOEnd, 2144 SmallVectorImpl<MachineInstr*> &NewMIs) const { 2145 bool isAligned = MMOBegin != MMOEnd && (*MMOBegin)->getAlignment() >= 16; 2146 unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, TM); 2147 DebugLoc DL; 2148 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg); 2149 for (unsigned i = 0, e = Addr.size(); i != e; ++i) 2150 MIB.addOperand(Addr[i]); 2151 (*MIB).setMemRefs(MMOBegin, MMOEnd); 2152 NewMIs.push_back(MIB); 2153} 2154 2155MachineInstr* 2156X86InstrInfo::emitFrameIndexDebugValue(MachineFunction &MF, 2157 int FrameIx, uint64_t Offset, 2158 const MDNode *MDPtr, 2159 DebugLoc DL) const { 2160 X86AddressMode AM; 2161 AM.BaseType = X86AddressMode::FrameIndexBase; 2162 AM.Base.FrameIndex = FrameIx; 2163 MachineInstrBuilder MIB = BuildMI(MF, DL, get(X86::DBG_VALUE)); 2164 addFullAddress(MIB, AM).addImm(Offset).addMetadata(MDPtr); 2165 return &*MIB; 2166} 2167 2168static MachineInstr *FuseTwoAddrInst(MachineFunction &MF, unsigned Opcode, 2169 const SmallVectorImpl<MachineOperand> &MOs, 2170 MachineInstr *MI, 2171 const TargetInstrInfo &TII) { 2172 // Create the base instruction with the memory operand as the first part. 2173 MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode), 2174 MI->getDebugLoc(), true); 2175 MachineInstrBuilder MIB(NewMI); 2176 unsigned NumAddrOps = MOs.size(); 2177 for (unsigned i = 0; i != NumAddrOps; ++i) 2178 MIB.addOperand(MOs[i]); 2179 if (NumAddrOps < 4) // FrameIndex only 2180 addOffset(MIB, 0); 2181 2182 // Loop over the rest of the ri operands, converting them over. 2183 unsigned NumOps = MI->getDesc().getNumOperands()-2; 2184 for (unsigned i = 0; i != NumOps; ++i) { 2185 MachineOperand &MO = MI->getOperand(i+2); 2186 MIB.addOperand(MO); 2187 } 2188 for (unsigned i = NumOps+2, e = MI->getNumOperands(); i != e; ++i) { 2189 MachineOperand &MO = MI->getOperand(i); 2190 MIB.addOperand(MO); 2191 } 2192 return MIB; 2193} 2194 2195static MachineInstr *FuseInst(MachineFunction &MF, 2196 unsigned Opcode, unsigned OpNo, 2197 const SmallVectorImpl<MachineOperand> &MOs, 2198 MachineInstr *MI, const TargetInstrInfo &TII) { 2199 MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode), 2200 MI->getDebugLoc(), true); 2201 MachineInstrBuilder MIB(NewMI); 2202 2203 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 2204 MachineOperand &MO = MI->getOperand(i); 2205 if (i == OpNo) { 2206 assert(MO.isReg() && "Expected to fold into reg operand!"); 2207 unsigned NumAddrOps = MOs.size(); 2208 for (unsigned i = 0; i != NumAddrOps; ++i) 2209 MIB.addOperand(MOs[i]); 2210 if (NumAddrOps < 4) // FrameIndex only 2211 addOffset(MIB, 0); 2212 } else { 2213 MIB.addOperand(MO); 2214 } 2215 } 2216 return MIB; 2217} 2218 2219static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode, 2220 const SmallVectorImpl<MachineOperand> &MOs, 2221 MachineInstr *MI) { 2222 MachineFunction &MF = *MI->getParent()->getParent(); 2223 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), TII.get(Opcode)); 2224 2225 unsigned NumAddrOps = MOs.size(); 2226 for (unsigned i = 0; i != NumAddrOps; ++i) 2227 MIB.addOperand(MOs[i]); 2228 if (NumAddrOps < 4) // FrameIndex only 2229 addOffset(MIB, 0); 2230 return MIB.addImm(0); 2231} 2232 2233MachineInstr* 2234X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF, 2235 MachineInstr *MI, unsigned i, 2236 const SmallVectorImpl<MachineOperand> &MOs, 2237 unsigned Size, unsigned Align) const { 2238 const DenseMap<unsigned, std::pair<unsigned,unsigned> > *OpcodeTablePtr = 0; 2239 bool isTwoAddrFold = false; 2240 unsigned NumOps = MI->getDesc().getNumOperands(); 2241 bool isTwoAddr = NumOps > 1 && 2242 MI->getDesc().getOperandConstraint(1, TOI::TIED_TO) != -1; 2243 2244 MachineInstr *NewMI = NULL; 2245 // Folding a memory location into the two-address part of a two-address 2246 // instruction is different than folding it other places. It requires 2247 // replacing the *two* registers with the memory location. 2248 if (isTwoAddr && NumOps >= 2 && i < 2 && 2249 MI->getOperand(0).isReg() && 2250 MI->getOperand(1).isReg() && 2251 MI->getOperand(0).getReg() == MI->getOperand(1).getReg()) { 2252 OpcodeTablePtr = &RegOp2MemOpTable2Addr; 2253 isTwoAddrFold = true; 2254 } else if (i == 0) { // If operand 0 2255 if (MI->getOpcode() == X86::MOV64r0) 2256 NewMI = MakeM0Inst(*this, X86::MOV64mi32, MOs, MI); 2257 else if (MI->getOpcode() == X86::MOV32r0) 2258 NewMI = MakeM0Inst(*this, X86::MOV32mi, MOs, MI); 2259 else if (MI->getOpcode() == X86::MOV16r0) 2260 NewMI = MakeM0Inst(*this, X86::MOV16mi, MOs, MI); 2261 else if (MI->getOpcode() == X86::MOV8r0) 2262 NewMI = MakeM0Inst(*this, X86::MOV8mi, MOs, MI); 2263 if (NewMI) 2264 return NewMI; 2265 2266 OpcodeTablePtr = &RegOp2MemOpTable0; 2267 } else if (i == 1) { 2268 OpcodeTablePtr = &RegOp2MemOpTable1; 2269 } else if (i == 2) { 2270 OpcodeTablePtr = &RegOp2MemOpTable2; 2271 } 2272 2273 // If table selected... 2274 if (OpcodeTablePtr) { 2275 // Find the Opcode to fuse 2276 DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I = 2277 OpcodeTablePtr->find(MI->getOpcode()); 2278 if (I != OpcodeTablePtr->end()) { 2279 unsigned Opcode = I->second.first; 2280 unsigned MinAlign = I->second.second; 2281 if (Align < MinAlign) 2282 return NULL; 2283 bool NarrowToMOV32rm = false; 2284 if (Size) { 2285 unsigned RCSize = MI->getDesc().OpInfo[i].getRegClass(&RI)->getSize(); 2286 if (Size < RCSize) { 2287 // Check if it's safe to fold the load. If the size of the object is 2288 // narrower than the load width, then it's not. 2289 if (Opcode != X86::MOV64rm || RCSize != 8 || Size != 4) 2290 return NULL; 2291 // If this is a 64-bit load, but the spill slot is 32, then we can do 2292 // a 32-bit load which is implicitly zero-extended. This likely is due 2293 // to liveintervalanalysis remat'ing a load from stack slot. 2294 if (MI->getOperand(0).getSubReg() || MI->getOperand(1).getSubReg()) 2295 return NULL; 2296 Opcode = X86::MOV32rm; 2297 NarrowToMOV32rm = true; 2298 } 2299 } 2300 2301 if (isTwoAddrFold) 2302 NewMI = FuseTwoAddrInst(MF, Opcode, MOs, MI, *this); 2303 else 2304 NewMI = FuseInst(MF, Opcode, i, MOs, MI, *this); 2305 2306 if (NarrowToMOV32rm) { 2307 // If this is the special case where we use a MOV32rm to load a 32-bit 2308 // value and zero-extend the top bits. Change the destination register 2309 // to a 32-bit one. 2310 unsigned DstReg = NewMI->getOperand(0).getReg(); 2311 if (TargetRegisterInfo::isPhysicalRegister(DstReg)) 2312 NewMI->getOperand(0).setReg(RI.getSubReg(DstReg, 2313 X86::sub_32bit)); 2314 else 2315 NewMI->getOperand(0).setSubReg(X86::sub_32bit); 2316 } 2317 return NewMI; 2318 } 2319 } 2320 2321 // No fusion 2322 if (PrintFailedFusing && !MI->isCopy()) 2323 dbgs() << "We failed to fuse operand " << i << " in " << *MI; 2324 return NULL; 2325} 2326 2327 2328MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF, 2329 MachineInstr *MI, 2330 const SmallVectorImpl<unsigned> &Ops, 2331 int FrameIndex) const { 2332 // Check switch flag 2333 if (NoFusing) return NULL; 2334 2335 if (!MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize)) 2336 switch (MI->getOpcode()) { 2337 case X86::CVTSD2SSrr: 2338 case X86::Int_CVTSD2SSrr: 2339 case X86::CVTSS2SDrr: 2340 case X86::Int_CVTSS2SDrr: 2341 case X86::RCPSSr: 2342 case X86::RCPSSr_Int: 2343 case X86::ROUNDSDr: 2344 case X86::ROUNDSSr: 2345 case X86::RSQRTSSr: 2346 case X86::RSQRTSSr_Int: 2347 case X86::SQRTSSr: 2348 case X86::SQRTSSr_Int: 2349 return 0; 2350 } 2351 2352 const MachineFrameInfo *MFI = MF.getFrameInfo(); 2353 unsigned Size = MFI->getObjectSize(FrameIndex); 2354 unsigned Alignment = MFI->getObjectAlignment(FrameIndex); 2355 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) { 2356 unsigned NewOpc = 0; 2357 unsigned RCSize = 0; 2358 switch (MI->getOpcode()) { 2359 default: return NULL; 2360 case X86::TEST8rr: NewOpc = X86::CMP8ri; RCSize = 1; break; 2361 case X86::TEST16rr: NewOpc = X86::CMP16ri8; RCSize = 2; break; 2362 case X86::TEST32rr: NewOpc = X86::CMP32ri8; RCSize = 4; break; 2363 case X86::TEST64rr: NewOpc = X86::CMP64ri8; RCSize = 8; break; 2364 } 2365 // Check if it's safe to fold the load. If the size of the object is 2366 // narrower than the load width, then it's not. 2367 if (Size < RCSize) 2368 return NULL; 2369 // Change to CMPXXri r, 0 first. 2370 MI->setDesc(get(NewOpc)); 2371 MI->getOperand(1).ChangeToImmediate(0); 2372 } else if (Ops.size() != 1) 2373 return NULL; 2374 2375 SmallVector<MachineOperand,4> MOs; 2376 MOs.push_back(MachineOperand::CreateFI(FrameIndex)); 2377 return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, Size, Alignment); 2378} 2379 2380MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF, 2381 MachineInstr *MI, 2382 const SmallVectorImpl<unsigned> &Ops, 2383 MachineInstr *LoadMI) const { 2384 // Check switch flag 2385 if (NoFusing) return NULL; 2386 2387 if (!MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize)) 2388 switch (MI->getOpcode()) { 2389 case X86::CVTSD2SSrr: 2390 case X86::Int_CVTSD2SSrr: 2391 case X86::CVTSS2SDrr: 2392 case X86::Int_CVTSS2SDrr: 2393 case X86::RCPSSr: 2394 case X86::RCPSSr_Int: 2395 case X86::ROUNDSDr: 2396 case X86::ROUNDSSr: 2397 case X86::RSQRTSSr: 2398 case X86::RSQRTSSr_Int: 2399 case X86::SQRTSSr: 2400 case X86::SQRTSSr_Int: 2401 return 0; 2402 } 2403 2404 // Determine the alignment of the load. 2405 unsigned Alignment = 0; 2406 if (LoadMI->hasOneMemOperand()) 2407 Alignment = (*LoadMI->memoperands_begin())->getAlignment(); 2408 else 2409 switch (LoadMI->getOpcode()) { 2410 case X86::AVX_SET0PSY: 2411 case X86::AVX_SET0PDY: 2412 Alignment = 32; 2413 break; 2414 case X86::V_SET0PS: 2415 case X86::V_SET0PD: 2416 case X86::V_SET0PI: 2417 case X86::V_SETALLONES: 2418 case X86::AVX_SET0PS: 2419 case X86::AVX_SET0PD: 2420 case X86::AVX_SET0PI: 2421 Alignment = 16; 2422 break; 2423 case X86::FsFLD0SD: 2424 case X86::VFsFLD0SD: 2425 Alignment = 8; 2426 break; 2427 case X86::FsFLD0SS: 2428 case X86::VFsFLD0SS: 2429 Alignment = 4; 2430 break; 2431 default: 2432 llvm_unreachable("Don't know how to fold this instruction!"); 2433 } 2434 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) { 2435 unsigned NewOpc = 0; 2436 switch (MI->getOpcode()) { 2437 default: return NULL; 2438 case X86::TEST8rr: NewOpc = X86::CMP8ri; break; 2439 case X86::TEST16rr: NewOpc = X86::CMP16ri8; break; 2440 case X86::TEST32rr: NewOpc = X86::CMP32ri8; break; 2441 case X86::TEST64rr: NewOpc = X86::CMP64ri8; break; 2442 } 2443 // Change to CMPXXri r, 0 first. 2444 MI->setDesc(get(NewOpc)); 2445 MI->getOperand(1).ChangeToImmediate(0); 2446 } else if (Ops.size() != 1) 2447 return NULL; 2448 2449 // Make sure the subregisters match. 2450 // Otherwise we risk changing the size of the load. 2451 if (LoadMI->getOperand(0).getSubReg() != MI->getOperand(Ops[0]).getSubReg()) 2452 return NULL; 2453 2454 SmallVector<MachineOperand,X86::AddrNumOperands> MOs; 2455 switch (LoadMI->getOpcode()) { 2456 case X86::V_SET0PS: 2457 case X86::V_SET0PD: 2458 case X86::V_SET0PI: 2459 case X86::V_SETALLONES: 2460 case X86::AVX_SET0PS: 2461 case X86::AVX_SET0PD: 2462 case X86::AVX_SET0PI: 2463 case X86::AVX_SET0PSY: 2464 case X86::AVX_SET0PDY: 2465 case X86::FsFLD0SD: 2466 case X86::FsFLD0SS: { 2467 // Folding a V_SET0P? or V_SETALLONES as a load, to ease register pressure. 2468 // Create a constant-pool entry and operands to load from it. 2469 2470 // Medium and large mode can't fold loads this way. 2471 if (TM.getCodeModel() != CodeModel::Small && 2472 TM.getCodeModel() != CodeModel::Kernel) 2473 return NULL; 2474 2475 // x86-32 PIC requires a PIC base register for constant pools. 2476 unsigned PICBase = 0; 2477 if (TM.getRelocationModel() == Reloc::PIC_) { 2478 if (TM.getSubtarget<X86Subtarget>().is64Bit()) 2479 PICBase = X86::RIP; 2480 else 2481 // FIXME: PICBase = getGlobalBaseReg(&MF); 2482 // This doesn't work for several reasons. 2483 // 1. GlobalBaseReg may have been spilled. 2484 // 2. It may not be live at MI. 2485 return NULL; 2486 } 2487 2488 // Create a constant-pool entry. 2489 MachineConstantPool &MCP = *MF.getConstantPool(); 2490 const Type *Ty; 2491 unsigned Opc = LoadMI->getOpcode(); 2492 if (Opc == X86::FsFLD0SS || Opc == X86::VFsFLD0SS) 2493 Ty = Type::getFloatTy(MF.getFunction()->getContext()); 2494 else if (Opc == X86::FsFLD0SD || Opc == X86::VFsFLD0SD) 2495 Ty = Type::getDoubleTy(MF.getFunction()->getContext()); 2496 else if (Opc == X86::AVX_SET0PSY || Opc == X86::AVX_SET0PDY) 2497 Ty = VectorType::get(Type::getFloatTy(MF.getFunction()->getContext()), 8); 2498 else 2499 Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 4); 2500 const Constant *C = LoadMI->getOpcode() == X86::V_SETALLONES ? 2501 Constant::getAllOnesValue(Ty) : 2502 Constant::getNullValue(Ty); 2503 unsigned CPI = MCP.getConstantPoolIndex(C, Alignment); 2504 2505 // Create operands to load from the constant pool entry. 2506 MOs.push_back(MachineOperand::CreateReg(PICBase, false)); 2507 MOs.push_back(MachineOperand::CreateImm(1)); 2508 MOs.push_back(MachineOperand::CreateReg(0, false)); 2509 MOs.push_back(MachineOperand::CreateCPI(CPI, 0)); 2510 MOs.push_back(MachineOperand::CreateReg(0, false)); 2511 break; 2512 } 2513 default: { 2514 // Folding a normal load. Just copy the load's address operands. 2515 unsigned NumOps = LoadMI->getDesc().getNumOperands(); 2516 for (unsigned i = NumOps - X86::AddrNumOperands; i != NumOps; ++i) 2517 MOs.push_back(LoadMI->getOperand(i)); 2518 break; 2519 } 2520 } 2521 return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, 0, Alignment); 2522} 2523 2524 2525bool X86InstrInfo::canFoldMemoryOperand(const MachineInstr *MI, 2526 const SmallVectorImpl<unsigned> &Ops) const { 2527 // Check switch flag 2528 if (NoFusing) return 0; 2529 2530 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) { 2531 switch (MI->getOpcode()) { 2532 default: return false; 2533 case X86::TEST8rr: 2534 case X86::TEST16rr: 2535 case X86::TEST32rr: 2536 case X86::TEST64rr: 2537 return true; 2538 } 2539 } 2540 2541 if (Ops.size() != 1) 2542 return false; 2543 2544 unsigned OpNum = Ops[0]; 2545 unsigned Opc = MI->getOpcode(); 2546 unsigned NumOps = MI->getDesc().getNumOperands(); 2547 bool isTwoAddr = NumOps > 1 && 2548 MI->getDesc().getOperandConstraint(1, TOI::TIED_TO) != -1; 2549 2550 // Folding a memory location into the two-address part of a two-address 2551 // instruction is different than folding it other places. It requires 2552 // replacing the *two* registers with the memory location. 2553 const DenseMap<unsigned, std::pair<unsigned,unsigned> > *OpcodeTablePtr = 0; 2554 if (isTwoAddr && NumOps >= 2 && OpNum < 2) { 2555 OpcodeTablePtr = &RegOp2MemOpTable2Addr; 2556 } else if (OpNum == 0) { // If operand 0 2557 switch (Opc) { 2558 case X86::MOV8r0: 2559 case X86::MOV16r0: 2560 case X86::MOV32r0: 2561 case X86::MOV64r0: return true; 2562 default: break; 2563 } 2564 OpcodeTablePtr = &RegOp2MemOpTable0; 2565 } else if (OpNum == 1) { 2566 OpcodeTablePtr = &RegOp2MemOpTable1; 2567 } else if (OpNum == 2) { 2568 OpcodeTablePtr = &RegOp2MemOpTable2; 2569 } 2570 2571 if (OpcodeTablePtr && OpcodeTablePtr->count(Opc)) 2572 return true; 2573 return TargetInstrInfoImpl::canFoldMemoryOperand(MI, Ops); 2574} 2575 2576bool X86InstrInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, 2577 unsigned Reg, bool UnfoldLoad, bool UnfoldStore, 2578 SmallVectorImpl<MachineInstr*> &NewMIs) const { 2579 DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I = 2580 MemOp2RegOpTable.find(MI->getOpcode()); 2581 if (I == MemOp2RegOpTable.end()) 2582 return false; 2583 unsigned Opc = I->second.first; 2584 unsigned Index = I->second.second & 0xf; 2585 bool FoldedLoad = I->second.second & (1 << 4); 2586 bool FoldedStore = I->second.second & (1 << 5); 2587 if (UnfoldLoad && !FoldedLoad) 2588 return false; 2589 UnfoldLoad &= FoldedLoad; 2590 if (UnfoldStore && !FoldedStore) 2591 return false; 2592 UnfoldStore &= FoldedStore; 2593 2594 const TargetInstrDesc &TID = get(Opc); 2595 const TargetOperandInfo &TOI = TID.OpInfo[Index]; 2596 const TargetRegisterClass *RC = TOI.getRegClass(&RI); 2597 if (!MI->hasOneMemOperand() && 2598 RC == &X86::VR128RegClass && 2599 !TM.getSubtarget<X86Subtarget>().isUnalignedMemAccessFast()) 2600 // Without memoperands, loadRegFromAddr and storeRegToStackSlot will 2601 // conservatively assume the address is unaligned. That's bad for 2602 // performance. 2603 return false; 2604 SmallVector<MachineOperand, X86::AddrNumOperands> AddrOps; 2605 SmallVector<MachineOperand,2> BeforeOps; 2606 SmallVector<MachineOperand,2> AfterOps; 2607 SmallVector<MachineOperand,4> ImpOps; 2608 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 2609 MachineOperand &Op = MI->getOperand(i); 2610 if (i >= Index && i < Index + X86::AddrNumOperands) 2611 AddrOps.push_back(Op); 2612 else if (Op.isReg() && Op.isImplicit()) 2613 ImpOps.push_back(Op); 2614 else if (i < Index) 2615 BeforeOps.push_back(Op); 2616 else if (i > Index) 2617 AfterOps.push_back(Op); 2618 } 2619 2620 // Emit the load instruction. 2621 if (UnfoldLoad) { 2622 std::pair<MachineInstr::mmo_iterator, 2623 MachineInstr::mmo_iterator> MMOs = 2624 MF.extractLoadMemRefs(MI->memoperands_begin(), 2625 MI->memoperands_end()); 2626 loadRegFromAddr(MF, Reg, AddrOps, RC, MMOs.first, MMOs.second, NewMIs); 2627 if (UnfoldStore) { 2628 // Address operands cannot be marked isKill. 2629 for (unsigned i = 1; i != 1 + X86::AddrNumOperands; ++i) { 2630 MachineOperand &MO = NewMIs[0]->getOperand(i); 2631 if (MO.isReg()) 2632 MO.setIsKill(false); 2633 } 2634 } 2635 } 2636 2637 // Emit the data processing instruction. 2638 MachineInstr *DataMI = MF.CreateMachineInstr(TID, MI->getDebugLoc(), true); 2639 MachineInstrBuilder MIB(DataMI); 2640 2641 if (FoldedStore) 2642 MIB.addReg(Reg, RegState::Define); 2643 for (unsigned i = 0, e = BeforeOps.size(); i != e; ++i) 2644 MIB.addOperand(BeforeOps[i]); 2645 if (FoldedLoad) 2646 MIB.addReg(Reg); 2647 for (unsigned i = 0, e = AfterOps.size(); i != e; ++i) 2648 MIB.addOperand(AfterOps[i]); 2649 for (unsigned i = 0, e = ImpOps.size(); i != e; ++i) { 2650 MachineOperand &MO = ImpOps[i]; 2651 MIB.addReg(MO.getReg(), 2652 getDefRegState(MO.isDef()) | 2653 RegState::Implicit | 2654 getKillRegState(MO.isKill()) | 2655 getDeadRegState(MO.isDead()) | 2656 getUndefRegState(MO.isUndef())); 2657 } 2658 // Change CMP32ri r, 0 back to TEST32rr r, r, etc. 2659 unsigned NewOpc = 0; 2660 switch (DataMI->getOpcode()) { 2661 default: break; 2662 case X86::CMP64ri32: 2663 case X86::CMP64ri8: 2664 case X86::CMP32ri: 2665 case X86::CMP32ri8: 2666 case X86::CMP16ri: 2667 case X86::CMP16ri8: 2668 case X86::CMP8ri: { 2669 MachineOperand &MO0 = DataMI->getOperand(0); 2670 MachineOperand &MO1 = DataMI->getOperand(1); 2671 if (MO1.getImm() == 0) { 2672 switch (DataMI->getOpcode()) { 2673 default: break; 2674 case X86::CMP64ri8: 2675 case X86::CMP64ri32: NewOpc = X86::TEST64rr; break; 2676 case X86::CMP32ri8: 2677 case X86::CMP32ri: NewOpc = X86::TEST32rr; break; 2678 case X86::CMP16ri8: 2679 case X86::CMP16ri: NewOpc = X86::TEST16rr; break; 2680 case X86::CMP8ri: NewOpc = X86::TEST8rr; break; 2681 } 2682 DataMI->setDesc(get(NewOpc)); 2683 MO1.ChangeToRegister(MO0.getReg(), false); 2684 } 2685 } 2686 } 2687 NewMIs.push_back(DataMI); 2688 2689 // Emit the store instruction. 2690 if (UnfoldStore) { 2691 const TargetRegisterClass *DstRC = TID.OpInfo[0].getRegClass(&RI); 2692 std::pair<MachineInstr::mmo_iterator, 2693 MachineInstr::mmo_iterator> MMOs = 2694 MF.extractStoreMemRefs(MI->memoperands_begin(), 2695 MI->memoperands_end()); 2696 storeRegToAddr(MF, Reg, true, AddrOps, DstRC, MMOs.first, MMOs.second, NewMIs); 2697 } 2698 2699 return true; 2700} 2701 2702bool 2703X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, 2704 SmallVectorImpl<SDNode*> &NewNodes) const { 2705 if (!N->isMachineOpcode()) 2706 return false; 2707 2708 DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I = 2709 MemOp2RegOpTable.find(N->getMachineOpcode()); 2710 if (I == MemOp2RegOpTable.end()) 2711 return false; 2712 unsigned Opc = I->second.first; 2713 unsigned Index = I->second.second & 0xf; 2714 bool FoldedLoad = I->second.second & (1 << 4); 2715 bool FoldedStore = I->second.second & (1 << 5); 2716 const TargetInstrDesc &TID = get(Opc); 2717 const TargetRegisterClass *RC = TID.OpInfo[Index].getRegClass(&RI); 2718 unsigned NumDefs = TID.NumDefs; 2719 std::vector<SDValue> AddrOps; 2720 std::vector<SDValue> BeforeOps; 2721 std::vector<SDValue> AfterOps; 2722 DebugLoc dl = N->getDebugLoc(); 2723 unsigned NumOps = N->getNumOperands(); 2724 for (unsigned i = 0; i != NumOps-1; ++i) { 2725 SDValue Op = N->getOperand(i); 2726 if (i >= Index-NumDefs && i < Index-NumDefs + X86::AddrNumOperands) 2727 AddrOps.push_back(Op); 2728 else if (i < Index-NumDefs) 2729 BeforeOps.push_back(Op); 2730 else if (i > Index-NumDefs) 2731 AfterOps.push_back(Op); 2732 } 2733 SDValue Chain = N->getOperand(NumOps-1); 2734 AddrOps.push_back(Chain); 2735 2736 // Emit the load instruction. 2737 SDNode *Load = 0; 2738 MachineFunction &MF = DAG.getMachineFunction(); 2739 if (FoldedLoad) { 2740 EVT VT = *RC->vt_begin(); 2741 std::pair<MachineInstr::mmo_iterator, 2742 MachineInstr::mmo_iterator> MMOs = 2743 MF.extractLoadMemRefs(cast<MachineSDNode>(N)->memoperands_begin(), 2744 cast<MachineSDNode>(N)->memoperands_end()); 2745 if (!(*MMOs.first) && 2746 RC == &X86::VR128RegClass && 2747 !TM.getSubtarget<X86Subtarget>().isUnalignedMemAccessFast()) 2748 // Do not introduce a slow unaligned load. 2749 return false; 2750 bool isAligned = (*MMOs.first) && (*MMOs.first)->getAlignment() >= 16; 2751 Load = DAG.getMachineNode(getLoadRegOpcode(0, RC, isAligned, TM), dl, 2752 VT, MVT::Other, &AddrOps[0], AddrOps.size()); 2753 NewNodes.push_back(Load); 2754 2755 // Preserve memory reference information. 2756 cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second); 2757 } 2758 2759 // Emit the data processing instruction. 2760 std::vector<EVT> VTs; 2761 const TargetRegisterClass *DstRC = 0; 2762 if (TID.getNumDefs() > 0) { 2763 DstRC = TID.OpInfo[0].getRegClass(&RI); 2764 VTs.push_back(*DstRC->vt_begin()); 2765 } 2766 for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) { 2767 EVT VT = N->getValueType(i); 2768 if (VT != MVT::Other && i >= (unsigned)TID.getNumDefs()) 2769 VTs.push_back(VT); 2770 } 2771 if (Load) 2772 BeforeOps.push_back(SDValue(Load, 0)); 2773 std::copy(AfterOps.begin(), AfterOps.end(), std::back_inserter(BeforeOps)); 2774 SDNode *NewNode= DAG.getMachineNode(Opc, dl, VTs, &BeforeOps[0], 2775 BeforeOps.size()); 2776 NewNodes.push_back(NewNode); 2777 2778 // Emit the store instruction. 2779 if (FoldedStore) { 2780 AddrOps.pop_back(); 2781 AddrOps.push_back(SDValue(NewNode, 0)); 2782 AddrOps.push_back(Chain); 2783 std::pair<MachineInstr::mmo_iterator, 2784 MachineInstr::mmo_iterator> MMOs = 2785 MF.extractStoreMemRefs(cast<MachineSDNode>(N)->memoperands_begin(), 2786 cast<MachineSDNode>(N)->memoperands_end()); 2787 if (!(*MMOs.first) && 2788 RC == &X86::VR128RegClass && 2789 !TM.getSubtarget<X86Subtarget>().isUnalignedMemAccessFast()) 2790 // Do not introduce a slow unaligned store. 2791 return false; 2792 bool isAligned = (*MMOs.first) && (*MMOs.first)->getAlignment() >= 16; 2793 SDNode *Store = DAG.getMachineNode(getStoreRegOpcode(0, DstRC, 2794 isAligned, TM), 2795 dl, MVT::Other, 2796 &AddrOps[0], AddrOps.size()); 2797 NewNodes.push_back(Store); 2798 2799 // Preserve memory reference information. 2800 cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second); 2801 } 2802 2803 return true; 2804} 2805 2806unsigned X86InstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc, 2807 bool UnfoldLoad, bool UnfoldStore, 2808 unsigned *LoadRegIndex) const { 2809 DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I = 2810 MemOp2RegOpTable.find(Opc); 2811 if (I == MemOp2RegOpTable.end()) 2812 return 0; 2813 bool FoldedLoad = I->second.second & (1 << 4); 2814 bool FoldedStore = I->second.second & (1 << 5); 2815 if (UnfoldLoad && !FoldedLoad) 2816 return 0; 2817 if (UnfoldStore && !FoldedStore) 2818 return 0; 2819 if (LoadRegIndex) 2820 *LoadRegIndex = I->second.second & 0xf; 2821 return I->second.first; 2822} 2823 2824bool 2825X86InstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, 2826 int64_t &Offset1, int64_t &Offset2) const { 2827 if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode()) 2828 return false; 2829 unsigned Opc1 = Load1->getMachineOpcode(); 2830 unsigned Opc2 = Load2->getMachineOpcode(); 2831 switch (Opc1) { 2832 default: return false; 2833 case X86::MOV8rm: 2834 case X86::MOV16rm: 2835 case X86::MOV32rm: 2836 case X86::MOV64rm: 2837 case X86::LD_Fp32m: 2838 case X86::LD_Fp64m: 2839 case X86::LD_Fp80m: 2840 case X86::MOVSSrm: 2841 case X86::MOVSDrm: 2842 case X86::MMX_MOVD64rm: 2843 case X86::MMX_MOVQ64rm: 2844 case X86::FsMOVAPSrm: 2845 case X86::FsMOVAPDrm: 2846 case X86::MOVAPSrm: 2847 case X86::MOVUPSrm: 2848 case X86::MOVUPSrm_Int: 2849 case X86::MOVAPDrm: 2850 case X86::MOVDQArm: 2851 case X86::MOVDQUrm: 2852 case X86::MOVDQUrm_Int: 2853 break; 2854 } 2855 switch (Opc2) { 2856 default: return false; 2857 case X86::MOV8rm: 2858 case X86::MOV16rm: 2859 case X86::MOV32rm: 2860 case X86::MOV64rm: 2861 case X86::LD_Fp32m: 2862 case X86::LD_Fp64m: 2863 case X86::LD_Fp80m: 2864 case X86::MOVSSrm: 2865 case X86::MOVSDrm: 2866 case X86::MMX_MOVD64rm: 2867 case X86::MMX_MOVQ64rm: 2868 case X86::FsMOVAPSrm: 2869 case X86::FsMOVAPDrm: 2870 case X86::MOVAPSrm: 2871 case X86::MOVUPSrm: 2872 case X86::MOVUPSrm_Int: 2873 case X86::MOVAPDrm: 2874 case X86::MOVDQArm: 2875 case X86::MOVDQUrm: 2876 case X86::MOVDQUrm_Int: 2877 break; 2878 } 2879 2880 // Check if chain operands and base addresses match. 2881 if (Load1->getOperand(0) != Load2->getOperand(0) || 2882 Load1->getOperand(5) != Load2->getOperand(5)) 2883 return false; 2884 // Segment operands should match as well. 2885 if (Load1->getOperand(4) != Load2->getOperand(4)) 2886 return false; 2887 // Scale should be 1, Index should be Reg0. 2888 if (Load1->getOperand(1) == Load2->getOperand(1) && 2889 Load1->getOperand(2) == Load2->getOperand(2)) { 2890 if (cast<ConstantSDNode>(Load1->getOperand(1))->getZExtValue() != 1) 2891 return false; 2892 2893 // Now let's examine the displacements. 2894 if (isa<ConstantSDNode>(Load1->getOperand(3)) && 2895 isa<ConstantSDNode>(Load2->getOperand(3))) { 2896 Offset1 = cast<ConstantSDNode>(Load1->getOperand(3))->getSExtValue(); 2897 Offset2 = cast<ConstantSDNode>(Load2->getOperand(3))->getSExtValue(); 2898 return true; 2899 } 2900 } 2901 return false; 2902} 2903 2904bool X86InstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, 2905 int64_t Offset1, int64_t Offset2, 2906 unsigned NumLoads) const { 2907 assert(Offset2 > Offset1); 2908 if ((Offset2 - Offset1) / 8 > 64) 2909 return false; 2910 2911 unsigned Opc1 = Load1->getMachineOpcode(); 2912 unsigned Opc2 = Load2->getMachineOpcode(); 2913 if (Opc1 != Opc2) 2914 return false; // FIXME: overly conservative? 2915 2916 switch (Opc1) { 2917 default: break; 2918 case X86::LD_Fp32m: 2919 case X86::LD_Fp64m: 2920 case X86::LD_Fp80m: 2921 case X86::MMX_MOVD64rm: 2922 case X86::MMX_MOVQ64rm: 2923 return false; 2924 } 2925 2926 EVT VT = Load1->getValueType(0); 2927 switch (VT.getSimpleVT().SimpleTy) { 2928 default: 2929 // XMM registers. In 64-bit mode we can be a bit more aggressive since we 2930 // have 16 of them to play with. 2931 if (TM.getSubtargetImpl()->is64Bit()) { 2932 if (NumLoads >= 3) 2933 return false; 2934 } else if (NumLoads) { 2935 return false; 2936 } 2937 break; 2938 case MVT::i8: 2939 case MVT::i16: 2940 case MVT::i32: 2941 case MVT::i64: 2942 case MVT::f32: 2943 case MVT::f64: 2944 if (NumLoads) 2945 return false; 2946 break; 2947 } 2948 2949 return true; 2950} 2951 2952 2953bool X86InstrInfo:: 2954ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { 2955 assert(Cond.size() == 1 && "Invalid X86 branch condition!"); 2956 X86::CondCode CC = static_cast<X86::CondCode>(Cond[0].getImm()); 2957 if (CC == X86::COND_NE_OR_P || CC == X86::COND_NP_OR_E) 2958 return true; 2959 Cond[0].setImm(GetOppositeBranchCondition(CC)); 2960 return false; 2961} 2962 2963bool X86InstrInfo:: 2964isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const { 2965 // FIXME: Return false for x87 stack register classes for now. We can't 2966 // allow any loads of these registers before FpGet_ST0_80. 2967 return !(RC == &X86::CCRRegClass || RC == &X86::RFP32RegClass || 2968 RC == &X86::RFP64RegClass || RC == &X86::RFP80RegClass); 2969} 2970 2971 2972/// isX86_64ExtendedReg - Is the MachineOperand a x86-64 extended (r8 or higher) 2973/// register? e.g. r8, xmm8, xmm13, etc. 2974bool X86InstrInfo::isX86_64ExtendedReg(unsigned RegNo) { 2975 switch (RegNo) { 2976 default: break; 2977 case X86::R8: case X86::R9: case X86::R10: case X86::R11: 2978 case X86::R12: case X86::R13: case X86::R14: case X86::R15: 2979 case X86::R8D: case X86::R9D: case X86::R10D: case X86::R11D: 2980 case X86::R12D: case X86::R13D: case X86::R14D: case X86::R15D: 2981 case X86::R8W: case X86::R9W: case X86::R10W: case X86::R11W: 2982 case X86::R12W: case X86::R13W: case X86::R14W: case X86::R15W: 2983 case X86::R8B: case X86::R9B: case X86::R10B: case X86::R11B: 2984 case X86::R12B: case X86::R13B: case X86::R14B: case X86::R15B: 2985 case X86::XMM8: case X86::XMM9: case X86::XMM10: case X86::XMM11: 2986 case X86::XMM12: case X86::XMM13: case X86::XMM14: case X86::XMM15: 2987 case X86::YMM8: case X86::YMM9: case X86::YMM10: case X86::YMM11: 2988 case X86::YMM12: case X86::YMM13: case X86::YMM14: case X86::YMM15: 2989 case X86::CR8: case X86::CR9: case X86::CR10: case X86::CR11: 2990 case X86::CR12: case X86::CR13: case X86::CR14: case X86::CR15: 2991 return true; 2992 } 2993 return false; 2994} 2995 2996/// getGlobalBaseReg - Return a virtual register initialized with the 2997/// the global base register value. Output instructions required to 2998/// initialize the register in the function entry block, if necessary. 2999/// 3000/// TODO: Eliminate this and move the code to X86MachineFunctionInfo. 3001/// 3002unsigned X86InstrInfo::getGlobalBaseReg(MachineFunction *MF) const { 3003 assert(!TM.getSubtarget<X86Subtarget>().is64Bit() && 3004 "X86-64 PIC uses RIP relative addressing"); 3005 3006 X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>(); 3007 unsigned GlobalBaseReg = X86FI->getGlobalBaseReg(); 3008 if (GlobalBaseReg != 0) 3009 return GlobalBaseReg; 3010 3011 // Create the register. The code to initialize it is inserted 3012 // later, by the CGBR pass (below). 3013 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 3014 GlobalBaseReg = RegInfo.createVirtualRegister(X86::GR32RegisterClass); 3015 X86FI->setGlobalBaseReg(GlobalBaseReg); 3016 return GlobalBaseReg; 3017} 3018 3019// These are the replaceable SSE instructions. Some of these have Int variants 3020// that we don't include here. We don't want to replace instructions selected 3021// by intrinsics. 3022static const unsigned ReplaceableInstrs[][3] = { 3023 //PackedSingle PackedDouble PackedInt 3024 { X86::MOVAPSmr, X86::MOVAPDmr, X86::MOVDQAmr }, 3025 { X86::MOVAPSrm, X86::MOVAPDrm, X86::MOVDQArm }, 3026 { X86::MOVAPSrr, X86::MOVAPDrr, X86::MOVDQArr }, 3027 { X86::MOVUPSmr, X86::MOVUPDmr, X86::MOVDQUmr }, 3028 { X86::MOVUPSrm, X86::MOVUPDrm, X86::MOVDQUrm }, 3029 { X86::MOVNTPSmr, X86::MOVNTPDmr, X86::MOVNTDQmr }, 3030 { X86::ANDNPSrm, X86::ANDNPDrm, X86::PANDNrm }, 3031 { X86::ANDNPSrr, X86::ANDNPDrr, X86::PANDNrr }, 3032 { X86::ANDPSrm, X86::ANDPDrm, X86::PANDrm }, 3033 { X86::ANDPSrr, X86::ANDPDrr, X86::PANDrr }, 3034 { X86::ORPSrm, X86::ORPDrm, X86::PORrm }, 3035 { X86::ORPSrr, X86::ORPDrr, X86::PORrr }, 3036 { X86::V_SET0PS, X86::V_SET0PD, X86::V_SET0PI }, 3037 { X86::XORPSrm, X86::XORPDrm, X86::PXORrm }, 3038 { X86::XORPSrr, X86::XORPDrr, X86::PXORrr }, 3039 // AVX 128-bit support 3040 { X86::VMOVAPSmr, X86::VMOVAPDmr, X86::VMOVDQAmr }, 3041 { X86::VMOVAPSrm, X86::VMOVAPDrm, X86::VMOVDQArm }, 3042 { X86::VMOVAPSrr, X86::VMOVAPDrr, X86::VMOVDQArr }, 3043 { X86::VMOVUPSmr, X86::VMOVUPDmr, X86::VMOVDQUmr }, 3044 { X86::VMOVUPSrm, X86::VMOVUPDrm, X86::VMOVDQUrm }, 3045 { X86::VMOVNTPSmr, X86::VMOVNTPDmr, X86::VMOVNTDQmr }, 3046 { X86::VANDNPSrm, X86::VANDNPDrm, X86::VPANDNrm }, 3047 { X86::VANDNPSrr, X86::VANDNPDrr, X86::VPANDNrr }, 3048 { X86::VANDPSrm, X86::VANDPDrm, X86::VPANDrm }, 3049 { X86::VANDPSrr, X86::VANDPDrr, X86::VPANDrr }, 3050 { X86::VORPSrm, X86::VORPDrm, X86::VPORrm }, 3051 { X86::VORPSrr, X86::VORPDrr, X86::VPORrr }, 3052 { X86::AVX_SET0PS, X86::AVX_SET0PD, X86::AVX_SET0PI }, 3053 { X86::VXORPSrm, X86::VXORPDrm, X86::VPXORrm }, 3054 { X86::VXORPSrr, X86::VXORPDrr, X86::VPXORrr }, 3055}; 3056 3057// FIXME: Some shuffle and unpack instructions have equivalents in different 3058// domains, but they require a bit more work than just switching opcodes. 3059 3060static const unsigned *lookup(unsigned opcode, unsigned domain) { 3061 for (unsigned i = 0, e = array_lengthof(ReplaceableInstrs); i != e; ++i) 3062 if (ReplaceableInstrs[i][domain-1] == opcode) 3063 return ReplaceableInstrs[i]; 3064 return 0; 3065} 3066 3067std::pair<uint16_t, uint16_t> 3068X86InstrInfo::GetSSEDomain(const MachineInstr *MI) const { 3069 uint16_t domain = (MI->getDesc().TSFlags >> X86II::SSEDomainShift) & 3; 3070 return std::make_pair(domain, 3071 domain && lookup(MI->getOpcode(), domain) ? 0xe : 0); 3072} 3073 3074void X86InstrInfo::SetSSEDomain(MachineInstr *MI, unsigned Domain) const { 3075 assert(Domain>0 && Domain<4 && "Invalid execution domain"); 3076 uint16_t dom = (MI->getDesc().TSFlags >> X86II::SSEDomainShift) & 3; 3077 assert(dom && "Not an SSE instruction"); 3078 const unsigned *table = lookup(MI->getOpcode(), dom); 3079 assert(table && "Cannot change domain"); 3080 MI->setDesc(get(table[Domain-1])); 3081} 3082 3083/// getNoopForMachoTarget - Return the noop instruction to use for a noop. 3084void X86InstrInfo::getNoopForMachoTarget(MCInst &NopInst) const { 3085 NopInst.setOpcode(X86::NOOP); 3086} 3087 3088bool X86InstrInfo::isHighLatencyDef(int opc) const { 3089 switch (opc) { 3090 default: return false; 3091 case X86::DIVSDrm: 3092 case X86::DIVSDrm_Int: 3093 case X86::DIVSDrr: 3094 case X86::DIVSDrr_Int: 3095 case X86::DIVSSrm: 3096 case X86::DIVSSrm_Int: 3097 case X86::DIVSSrr: 3098 case X86::DIVSSrr_Int: 3099 case X86::SQRTPDm: 3100 case X86::SQRTPDm_Int: 3101 case X86::SQRTPDr: 3102 case X86::SQRTPDr_Int: 3103 case X86::SQRTPSm: 3104 case X86::SQRTPSm_Int: 3105 case X86::SQRTPSr: 3106 case X86::SQRTPSr_Int: 3107 case X86::SQRTSDm: 3108 case X86::SQRTSDm_Int: 3109 case X86::SQRTSDr: 3110 case X86::SQRTSDr_Int: 3111 case X86::SQRTSSm: 3112 case X86::SQRTSSm_Int: 3113 case X86::SQRTSSr: 3114 case X86::SQRTSSr_Int: 3115 return true; 3116 } 3117} 3118 3119bool X86InstrInfo:: 3120hasHighOperandLatency(const InstrItineraryData *ItinData, 3121 const MachineRegisterInfo *MRI, 3122 const MachineInstr *DefMI, unsigned DefIdx, 3123 const MachineInstr *UseMI, unsigned UseIdx) const { 3124 return isHighLatencyDef(DefMI->getOpcode()); 3125} 3126 3127namespace { 3128 /// CGBR - Create Global Base Reg pass. This initializes the PIC 3129 /// global base register for x86-32. 3130 struct CGBR : public MachineFunctionPass { 3131 static char ID; 3132 CGBR() : MachineFunctionPass(ID) {} 3133 3134 virtual bool runOnMachineFunction(MachineFunction &MF) { 3135 const X86TargetMachine *TM = 3136 static_cast<const X86TargetMachine *>(&MF.getTarget()); 3137 3138 assert(!TM->getSubtarget<X86Subtarget>().is64Bit() && 3139 "X86-64 PIC uses RIP relative addressing"); 3140 3141 // Only emit a global base reg in PIC mode. 3142 if (TM->getRelocationModel() != Reloc::PIC_) 3143 return false; 3144 3145 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>(); 3146 unsigned GlobalBaseReg = X86FI->getGlobalBaseReg(); 3147 3148 // If we didn't need a GlobalBaseReg, don't insert code. 3149 if (GlobalBaseReg == 0) 3150 return false; 3151 3152 // Insert the set of GlobalBaseReg into the first MBB of the function 3153 MachineBasicBlock &FirstMBB = MF.front(); 3154 MachineBasicBlock::iterator MBBI = FirstMBB.begin(); 3155 DebugLoc DL = FirstMBB.findDebugLoc(MBBI); 3156 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 3157 const X86InstrInfo *TII = TM->getInstrInfo(); 3158 3159 unsigned PC; 3160 if (TM->getSubtarget<X86Subtarget>().isPICStyleGOT()) 3161 PC = RegInfo.createVirtualRegister(X86::GR32RegisterClass); 3162 else 3163 PC = GlobalBaseReg; 3164 3165 // Operand of MovePCtoStack is completely ignored by asm printer. It's 3166 // only used in JIT code emission as displacement to pc. 3167 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOVPC32r), PC).addImm(0); 3168 3169 // If we're using vanilla 'GOT' PIC style, we should use relative addressing 3170 // not to pc, but to _GLOBAL_OFFSET_TABLE_ external. 3171 if (TM->getSubtarget<X86Subtarget>().isPICStyleGOT()) { 3172 // Generate addl $__GLOBAL_OFFSET_TABLE_ + [.-piclabel], %some_register 3173 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD32ri), GlobalBaseReg) 3174 .addReg(PC).addExternalSymbol("_GLOBAL_OFFSET_TABLE_", 3175 X86II::MO_GOT_ABSOLUTE_ADDRESS); 3176 } 3177 3178 return true; 3179 } 3180 3181 virtual const char *getPassName() const { 3182 return "X86 PIC Global Base Reg Initialization"; 3183 } 3184 3185 virtual void getAnalysisUsage(AnalysisUsage &AU) const { 3186 AU.setPreservesCFG(); 3187 MachineFunctionPass::getAnalysisUsage(AU); 3188 } 3189 }; 3190} 3191 3192char CGBR::ID = 0; 3193FunctionPass* 3194llvm::createGlobalBaseRegPass() { return new CGBR(); } 3195