1//===- AsmWriterEmitter.cpp - Generate an assembly writer -----------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This tablegen backend emits an assembly printer for the current target. 11// Note that this is currently fairly skeletal, but will grow over time. 12// 13//===----------------------------------------------------------------------===// 14 15#include "AsmWriterInst.h" 16#include "CodeGenTarget.h" 17#include "SequenceToOffsetTable.h" 18#include "llvm/ADT/SmallString.h" 19#include "llvm/ADT/StringExtras.h" 20#include "llvm/ADT/Twine.h" 21#include "llvm/Support/Debug.h" 22#include "llvm/Support/Format.h" 23#include "llvm/Support/MathExtras.h" 24#include "llvm/TableGen/Error.h" 25#include "llvm/TableGen/Record.h" 26#include "llvm/TableGen/TableGenBackend.h" 27#include <algorithm> 28#include <cassert> 29#include <map> 30#include <utility> 31#include <vector> 32using namespace llvm; 33 34#define DEBUG_TYPE "asm-writer-emitter" 35 36namespace { 37class AsmWriterEmitter { 38 RecordKeeper &Records; 39 CodeGenTarget Target; 40 ArrayRef<const CodeGenInstruction *> NumberedInstructions; 41 std::vector<AsmWriterInst> Instructions; 42public: 43 AsmWriterEmitter(RecordKeeper &R); 44 45 void run(raw_ostream &o); 46 47private: 48 void EmitPrintInstruction(raw_ostream &o); 49 void EmitGetRegisterName(raw_ostream &o); 50 void EmitPrintAliasInstruction(raw_ostream &O); 51 52 void FindUniqueOperandCommands(std::vector<std::string> &UOC, 53 std::vector<std::vector<unsigned>> &InstIdxs, 54 std::vector<unsigned> &InstOpsUsed, 55 bool PassSubtarget) const; 56}; 57} // end anonymous namespace 58 59static void PrintCases(std::vector<std::pair<std::string, 60 AsmWriterOperand> > &OpsToPrint, raw_ostream &O, 61 bool PassSubtarget) { 62 O << " case " << OpsToPrint.back().first << ":"; 63 AsmWriterOperand TheOp = OpsToPrint.back().second; 64 OpsToPrint.pop_back(); 65 66 // Check to see if any other operands are identical in this list, and if so, 67 // emit a case label for them. 68 for (unsigned i = OpsToPrint.size(); i != 0; --i) 69 if (OpsToPrint[i-1].second == TheOp) { 70 O << "\n case " << OpsToPrint[i-1].first << ":"; 71 OpsToPrint.erase(OpsToPrint.begin()+i-1); 72 } 73 74 // Finally, emit the code. 75 O << "\n " << TheOp.getCode(PassSubtarget); 76 O << "\n break;\n"; 77} 78 79 80/// EmitInstructions - Emit the last instruction in the vector and any other 81/// instructions that are suitably similar to it. 82static void EmitInstructions(std::vector<AsmWriterInst> &Insts, 83 raw_ostream &O, bool PassSubtarget) { 84 AsmWriterInst FirstInst = Insts.back(); 85 Insts.pop_back(); 86 87 std::vector<AsmWriterInst> SimilarInsts; 88 unsigned DifferingOperand = ~0; 89 for (unsigned i = Insts.size(); i != 0; --i) { 90 unsigned DiffOp = Insts[i-1].MatchesAllButOneOp(FirstInst); 91 if (DiffOp != ~1U) { 92 if (DifferingOperand == ~0U) // First match! 93 DifferingOperand = DiffOp; 94 95 // If this differs in the same operand as the rest of the instructions in 96 // this class, move it to the SimilarInsts list. 97 if (DifferingOperand == DiffOp || DiffOp == ~0U) { 98 SimilarInsts.push_back(Insts[i-1]); 99 Insts.erase(Insts.begin()+i-1); 100 } 101 } 102 } 103 104 O << " case " << FirstInst.CGI->Namespace << "::" 105 << FirstInst.CGI->TheDef->getName() << ":\n"; 106 for (const AsmWriterInst &AWI : SimilarInsts) 107 O << " case " << AWI.CGI->Namespace << "::" 108 << AWI.CGI->TheDef->getName() << ":\n"; 109 for (unsigned i = 0, e = FirstInst.Operands.size(); i != e; ++i) { 110 if (i != DifferingOperand) { 111 // If the operand is the same for all instructions, just print it. 112 O << " " << FirstInst.Operands[i].getCode(PassSubtarget); 113 } else { 114 // If this is the operand that varies between all of the instructions, 115 // emit a switch for just this operand now. 116 O << " switch (MI->getOpcode()) {\n"; 117 O << " default: llvm_unreachable(\"Unexpected opcode.\");\n"; 118 std::vector<std::pair<std::string, AsmWriterOperand> > OpsToPrint; 119 OpsToPrint.push_back(std::make_pair(FirstInst.CGI->Namespace + "::" + 120 FirstInst.CGI->TheDef->getName(), 121 FirstInst.Operands[i])); 122 123 for (const AsmWriterInst &AWI : SimilarInsts) { 124 OpsToPrint.push_back(std::make_pair(AWI.CGI->Namespace+"::"+ 125 AWI.CGI->TheDef->getName(), 126 AWI.Operands[i])); 127 } 128 std::reverse(OpsToPrint.begin(), OpsToPrint.end()); 129 while (!OpsToPrint.empty()) 130 PrintCases(OpsToPrint, O, PassSubtarget); 131 O << " }"; 132 } 133 O << "\n"; 134 } 135 O << " break;\n"; 136} 137 138void AsmWriterEmitter:: 139FindUniqueOperandCommands(std::vector<std::string> &UniqueOperandCommands, 140 std::vector<std::vector<unsigned>> &InstIdxs, 141 std::vector<unsigned> &InstOpsUsed, 142 bool PassSubtarget) const { 143 144 // This vector parallels UniqueOperandCommands, keeping track of which 145 // instructions each case are used for. It is a comma separated string of 146 // enums. 147 std::vector<std::string> InstrsForCase; 148 InstrsForCase.resize(UniqueOperandCommands.size()); 149 InstOpsUsed.assign(UniqueOperandCommands.size(), 0); 150 151 for (size_t i = 0, e = Instructions.size(); i != e; ++i) { 152 const AsmWriterInst &Inst = Instructions[i]; 153 if (Inst.Operands.empty()) 154 continue; // Instruction already done. 155 156 std::string Command = " "+Inst.Operands[0].getCode(PassSubtarget)+"\n"; 157 158 // Check to see if we already have 'Command' in UniqueOperandCommands. 159 // If not, add it. 160 auto I = std::find(UniqueOperandCommands.begin(), 161 UniqueOperandCommands.end(), Command); 162 if (I != UniqueOperandCommands.end()) { 163 size_t idx = I - UniqueOperandCommands.begin(); 164 InstrsForCase[idx] += ", "; 165 InstrsForCase[idx] += Inst.CGI->TheDef->getName(); 166 InstIdxs[idx].push_back(i); 167 } else { 168 UniqueOperandCommands.push_back(std::move(Command)); 169 InstrsForCase.push_back(Inst.CGI->TheDef->getName()); 170 InstIdxs.emplace_back(); 171 InstIdxs.back().push_back(i); 172 173 // This command matches one operand so far. 174 InstOpsUsed.push_back(1); 175 } 176 } 177 178 // For each entry of UniqueOperandCommands, there is a set of instructions 179 // that uses it. If the next command of all instructions in the set are 180 // identical, fold it into the command. 181 for (size_t CommandIdx = 0, e = UniqueOperandCommands.size(); 182 CommandIdx != e; ++CommandIdx) { 183 184 const auto &Idxs = InstIdxs[CommandIdx]; 185 186 for (unsigned Op = 1; ; ++Op) { 187 // Find the first instruction in the set. 188 const AsmWriterInst &FirstInst = Instructions[Idxs.front()]; 189 // If this instruction has no more operands, we isn't anything to merge 190 // into this command. 191 if (FirstInst.Operands.size() == Op) 192 break; 193 194 // Otherwise, scan to see if all of the other instructions in this command 195 // set share the operand. 196 if (std::any_of(Idxs.begin()+1, Idxs.end(), 197 [&](unsigned Idx) { 198 const AsmWriterInst &OtherInst = Instructions[Idx]; 199 return OtherInst.Operands.size() == Op || 200 OtherInst.Operands[Op] != FirstInst.Operands[Op]; 201 })) 202 break; 203 204 // Okay, everything in this command set has the same next operand. Add it 205 // to UniqueOperandCommands and remember that it was consumed. 206 std::string Command = " " + 207 FirstInst.Operands[Op].getCode(PassSubtarget) + "\n"; 208 209 UniqueOperandCommands[CommandIdx] += Command; 210 InstOpsUsed[CommandIdx]++; 211 } 212 } 213 214 // Prepend some of the instructions each case is used for onto the case val. 215 for (unsigned i = 0, e = InstrsForCase.size(); i != e; ++i) { 216 std::string Instrs = InstrsForCase[i]; 217 if (Instrs.size() > 70) { 218 Instrs.erase(Instrs.begin()+70, Instrs.end()); 219 Instrs += "..."; 220 } 221 222 if (!Instrs.empty()) 223 UniqueOperandCommands[i] = " // " + Instrs + "\n" + 224 UniqueOperandCommands[i]; 225 } 226} 227 228 229static void UnescapeString(std::string &Str) { 230 for (unsigned i = 0; i != Str.size(); ++i) { 231 if (Str[i] == '\\' && i != Str.size()-1) { 232 switch (Str[i+1]) { 233 default: continue; // Don't execute the code after the switch. 234 case 'a': Str[i] = '\a'; break; 235 case 'b': Str[i] = '\b'; break; 236 case 'e': Str[i] = 27; break; 237 case 'f': Str[i] = '\f'; break; 238 case 'n': Str[i] = '\n'; break; 239 case 'r': Str[i] = '\r'; break; 240 case 't': Str[i] = '\t'; break; 241 case 'v': Str[i] = '\v'; break; 242 case '"': Str[i] = '\"'; break; 243 case '\'': Str[i] = '\''; break; 244 case '\\': Str[i] = '\\'; break; 245 } 246 // Nuke the second character. 247 Str.erase(Str.begin()+i+1); 248 } 249 } 250} 251 252/// EmitPrintInstruction - Generate the code for the "printInstruction" method 253/// implementation. Destroys all instances of AsmWriterInst information, by 254/// clearing the Instructions vector. 255void AsmWriterEmitter::EmitPrintInstruction(raw_ostream &O) { 256 Record *AsmWriter = Target.getAsmWriter(); 257 std::string ClassName = AsmWriter->getValueAsString("AsmWriterClassName"); 258 bool PassSubtarget = AsmWriter->getValueAsInt("PassSubtarget"); 259 260 O << 261 "/// printInstruction - This method is automatically generated by tablegen\n" 262 "/// from the instruction set description.\n" 263 "void " << Target.getName() << ClassName 264 << "::printInstruction(const MCInst *MI, " 265 << (PassSubtarget ? "const MCSubtargetInfo &STI, " : "") 266 << "raw_ostream &O) {\n"; 267 268 // Build an aggregate string, and build a table of offsets into it. 269 SequenceToOffsetTable<std::string> StringTable; 270 271 /// OpcodeInfo - This encodes the index of the string to use for the first 272 /// chunk of the output as well as indices used for operand printing. 273 std::vector<uint64_t> OpcodeInfo(NumberedInstructions.size()); 274 const unsigned OpcodeInfoBits = 64; 275 276 // Add all strings to the string table upfront so it can generate an optimized 277 // representation. 278 for (AsmWriterInst &AWI : Instructions) { 279 if (AWI.Operands[0].OperandType == 280 AsmWriterOperand::isLiteralTextOperand && 281 !AWI.Operands[0].Str.empty()) { 282 std::string Str = AWI.Operands[0].Str; 283 UnescapeString(Str); 284 StringTable.add(Str); 285 } 286 } 287 288 StringTable.layout(); 289 290 unsigned MaxStringIdx = 0; 291 for (AsmWriterInst &AWI : Instructions) { 292 unsigned Idx; 293 if (AWI.Operands[0].OperandType != AsmWriterOperand::isLiteralTextOperand || 294 AWI.Operands[0].Str.empty()) { 295 // Something handled by the asmwriter printer, but with no leading string. 296 Idx = StringTable.get(""); 297 } else { 298 std::string Str = AWI.Operands[0].Str; 299 UnescapeString(Str); 300 Idx = StringTable.get(Str); 301 MaxStringIdx = std::max(MaxStringIdx, Idx); 302 303 // Nuke the string from the operand list. It is now handled! 304 AWI.Operands.erase(AWI.Operands.begin()); 305 } 306 307 // Bias offset by one since we want 0 as a sentinel. 308 OpcodeInfo[AWI.CGIIndex] = Idx+1; 309 } 310 311 // Figure out how many bits we used for the string index. 312 unsigned AsmStrBits = Log2_32_Ceil(MaxStringIdx+2); 313 314 // To reduce code size, we compactify common instructions into a few bits 315 // in the opcode-indexed table. 316 unsigned BitsLeft = OpcodeInfoBits-AsmStrBits; 317 318 std::vector<std::vector<std::string>> TableDrivenOperandPrinters; 319 320 while (1) { 321 std::vector<std::string> UniqueOperandCommands; 322 std::vector<std::vector<unsigned>> InstIdxs; 323 std::vector<unsigned> NumInstOpsHandled; 324 FindUniqueOperandCommands(UniqueOperandCommands, InstIdxs, 325 NumInstOpsHandled, PassSubtarget); 326 327 // If we ran out of operands to print, we're done. 328 if (UniqueOperandCommands.empty()) break; 329 330 // Compute the number of bits we need to represent these cases, this is 331 // ceil(log2(numentries)). 332 unsigned NumBits = Log2_32_Ceil(UniqueOperandCommands.size()); 333 334 // If we don't have enough bits for this operand, don't include it. 335 if (NumBits > BitsLeft) { 336 DEBUG(errs() << "Not enough bits to densely encode " << NumBits 337 << " more bits\n"); 338 break; 339 } 340 341 // Otherwise, we can include this in the initial lookup table. Add it in. 342 for (size_t i = 0, e = InstIdxs.size(); i != e; ++i) { 343 unsigned NumOps = NumInstOpsHandled[i]; 344 for (unsigned Idx : InstIdxs[i]) { 345 OpcodeInfo[Instructions[Idx].CGIIndex] |= 346 (uint64_t)i << (OpcodeInfoBits-BitsLeft); 347 // Remove the info about this operand from the instruction. 348 AsmWriterInst &Inst = Instructions[Idx]; 349 if (!Inst.Operands.empty()) { 350 assert(NumOps <= Inst.Operands.size() && 351 "Can't remove this many ops!"); 352 Inst.Operands.erase(Inst.Operands.begin(), 353 Inst.Operands.begin()+NumOps); 354 } 355 } 356 } 357 BitsLeft -= NumBits; 358 359 // Remember the handlers for this set of operands. 360 TableDrivenOperandPrinters.push_back(std::move(UniqueOperandCommands)); 361 } 362 363 // Emit the string table itself. 364 O << " static const char AsmStrs[] = {\n"; 365 StringTable.emit(O, printChar); 366 O << " };\n\n"; 367 368 // Emit the lookup tables in pieces to minimize wasted bytes. 369 unsigned BytesNeeded = ((OpcodeInfoBits - BitsLeft) + 7) / 8; 370 unsigned Table = 0, Shift = 0; 371 SmallString<128> BitsString; 372 raw_svector_ostream BitsOS(BitsString); 373 // If the total bits is more than 32-bits we need to use a 64-bit type. 374 BitsOS << " uint" << ((BitsLeft < (OpcodeInfoBits - 32)) ? 64 : 32) 375 << "_t Bits = 0;\n"; 376 while (BytesNeeded != 0) { 377 // Figure out how big this table section needs to be, but no bigger than 4. 378 unsigned TableSize = std::min(1 << Log2_32(BytesNeeded), 4); 379 BytesNeeded -= TableSize; 380 TableSize *= 8; // Convert to bits; 381 uint64_t Mask = (1ULL << TableSize) - 1; 382 O << " static const uint" << TableSize << "_t OpInfo" << Table 383 << "[] = {\n"; 384 for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) { 385 O << " " << ((OpcodeInfo[i] >> Shift) & Mask) << "U,\t// " 386 << NumberedInstructions[i]->TheDef->getName() << "\n"; 387 } 388 O << " };\n\n"; 389 // Emit string to combine the individual table lookups. 390 BitsOS << " Bits |= "; 391 // If the total bits is more than 32-bits we need to use a 64-bit type. 392 if (BitsLeft < (OpcodeInfoBits - 32)) 393 BitsOS << "(uint64_t)"; 394 BitsOS << "OpInfo" << Table << "[MI->getOpcode()] << " << Shift << ";\n"; 395 // Prepare the shift for the next iteration and increment the table count. 396 Shift += TableSize; 397 ++Table; 398 } 399 400 // Emit the initial tab character. 401 O << " O << \"\\t\";\n\n"; 402 403 O << " // Emit the opcode for the instruction.\n"; 404 O << BitsString; 405 406 // Emit the starting string. 407 O << " assert(Bits != 0 && \"Cannot print this instruction.\");\n" 408 << " O << AsmStrs+(Bits & " << (1 << AsmStrBits)-1 << ")-1;\n\n"; 409 410 // Output the table driven operand information. 411 BitsLeft = OpcodeInfoBits-AsmStrBits; 412 for (unsigned i = 0, e = TableDrivenOperandPrinters.size(); i != e; ++i) { 413 std::vector<std::string> &Commands = TableDrivenOperandPrinters[i]; 414 415 // Compute the number of bits we need to represent these cases, this is 416 // ceil(log2(numentries)). 417 unsigned NumBits = Log2_32_Ceil(Commands.size()); 418 assert(NumBits <= BitsLeft && "consistency error"); 419 420 // Emit code to extract this field from Bits. 421 O << "\n // Fragment " << i << " encoded into " << NumBits 422 << " bits for " << Commands.size() << " unique commands.\n"; 423 424 if (Commands.size() == 2) { 425 // Emit two possibilitys with if/else. 426 O << " if ((Bits >> " 427 << (OpcodeInfoBits-BitsLeft) << ") & " 428 << ((1 << NumBits)-1) << ") {\n" 429 << Commands[1] 430 << " } else {\n" 431 << Commands[0] 432 << " }\n\n"; 433 } else if (Commands.size() == 1) { 434 // Emit a single possibility. 435 O << Commands[0] << "\n\n"; 436 } else { 437 O << " switch ((Bits >> " 438 << (OpcodeInfoBits-BitsLeft) << ") & " 439 << ((1 << NumBits)-1) << ") {\n" 440 << " default: llvm_unreachable(\"Invalid command number.\");\n"; 441 442 // Print out all the cases. 443 for (unsigned j = 0, e = Commands.size(); j != e; ++j) { 444 O << " case " << j << ":\n"; 445 O << Commands[j]; 446 O << " break;\n"; 447 } 448 O << " }\n\n"; 449 } 450 BitsLeft -= NumBits; 451 } 452 453 // Okay, delete instructions with no operand info left. 454 auto I = std::remove_if(Instructions.begin(), Instructions.end(), 455 [](AsmWriterInst &Inst) { 456 return Inst.Operands.empty(); 457 }); 458 Instructions.erase(I, Instructions.end()); 459 460 461 // Because this is a vector, we want to emit from the end. Reverse all of the 462 // elements in the vector. 463 std::reverse(Instructions.begin(), Instructions.end()); 464 465 466 // Now that we've emitted all of the operand info that fit into 64 bits, emit 467 // information for those instructions that are left. This is a less dense 468 // encoding, but we expect the main 64-bit table to handle the majority of 469 // instructions. 470 if (!Instructions.empty()) { 471 // Find the opcode # of inline asm. 472 O << " switch (MI->getOpcode()) {\n"; 473 O << " default: llvm_unreachable(\"Unexpected opcode.\");\n"; 474 while (!Instructions.empty()) 475 EmitInstructions(Instructions, O, PassSubtarget); 476 477 O << " }\n"; 478 } 479 480 O << "}\n"; 481} 482 483static const char *getMinimalTypeForRange(uint64_t Range) { 484 assert(Range < 0xFFFFFFFFULL && "Enum too large"); 485 if (Range > 0xFFFF) 486 return "uint32_t"; 487 if (Range > 0xFF) 488 return "uint16_t"; 489 return "uint8_t"; 490} 491 492static void 493emitRegisterNameString(raw_ostream &O, StringRef AltName, 494 const std::deque<CodeGenRegister> &Registers) { 495 SequenceToOffsetTable<std::string> StringTable; 496 SmallVector<std::string, 4> AsmNames(Registers.size()); 497 unsigned i = 0; 498 for (const auto &Reg : Registers) { 499 std::string &AsmName = AsmNames[i++]; 500 501 // "NoRegAltName" is special. We don't need to do a lookup for that, 502 // as it's just a reference to the default register name. 503 if (AltName == "" || AltName == "NoRegAltName") { 504 AsmName = Reg.TheDef->getValueAsString("AsmName"); 505 if (AsmName.empty()) 506 AsmName = Reg.getName(); 507 } else { 508 // Make sure the register has an alternate name for this index. 509 std::vector<Record*> AltNameList = 510 Reg.TheDef->getValueAsListOfDefs("RegAltNameIndices"); 511 unsigned Idx = 0, e; 512 for (e = AltNameList.size(); 513 Idx < e && (AltNameList[Idx]->getName() != AltName); 514 ++Idx) 515 ; 516 // If the register has an alternate name for this index, use it. 517 // Otherwise, leave it empty as an error flag. 518 if (Idx < e) { 519 std::vector<std::string> AltNames = 520 Reg.TheDef->getValueAsListOfStrings("AltNames"); 521 if (AltNames.size() <= Idx) 522 PrintFatalError(Reg.TheDef->getLoc(), 523 "Register definition missing alt name for '" + 524 AltName + "'."); 525 AsmName = AltNames[Idx]; 526 } 527 } 528 StringTable.add(AsmName); 529 } 530 531 StringTable.layout(); 532 O << " static const char AsmStrs" << AltName << "[] = {\n"; 533 StringTable.emit(O, printChar); 534 O << " };\n\n"; 535 536 O << " static const " << getMinimalTypeForRange(StringTable.size()-1) 537 << " RegAsmOffset" << AltName << "[] = {"; 538 for (unsigned i = 0, e = Registers.size(); i != e; ++i) { 539 if ((i % 14) == 0) 540 O << "\n "; 541 O << StringTable.get(AsmNames[i]) << ", "; 542 } 543 O << "\n };\n" 544 << "\n"; 545} 546 547void AsmWriterEmitter::EmitGetRegisterName(raw_ostream &O) { 548 Record *AsmWriter = Target.getAsmWriter(); 549 std::string ClassName = AsmWriter->getValueAsString("AsmWriterClassName"); 550 const auto &Registers = Target.getRegBank().getRegisters(); 551 const std::vector<Record*> &AltNameIndices = Target.getRegAltNameIndices(); 552 bool hasAltNames = AltNameIndices.size() > 1; 553 std::string Namespace = 554 Registers.front().TheDef->getValueAsString("Namespace"); 555 556 O << 557 "\n\n/// getRegisterName - This method is automatically generated by tblgen\n" 558 "/// from the register set description. This returns the assembler name\n" 559 "/// for the specified register.\n" 560 "const char *" << Target.getName() << ClassName << "::"; 561 if (hasAltNames) 562 O << "\ngetRegisterName(unsigned RegNo, unsigned AltIdx) {\n"; 563 else 564 O << "getRegisterName(unsigned RegNo) {\n"; 565 O << " assert(RegNo && RegNo < " << (Registers.size()+1) 566 << " && \"Invalid register number!\");\n" 567 << "\n"; 568 569 if (hasAltNames) { 570 for (const Record *R : AltNameIndices) 571 emitRegisterNameString(O, R->getName(), Registers); 572 } else 573 emitRegisterNameString(O, "", Registers); 574 575 if (hasAltNames) { 576 O << " switch(AltIdx) {\n" 577 << " default: llvm_unreachable(\"Invalid register alt name index!\");\n"; 578 for (const Record *R : AltNameIndices) { 579 const std::string &AltName = R->getName(); 580 std::string Prefix = !Namespace.empty() ? Namespace + "::" : ""; 581 O << " case " << Prefix << AltName << ":\n" 582 << " assert(*(AsmStrs" << AltName << "+RegAsmOffset" 583 << AltName << "[RegNo-1]) &&\n" 584 << " \"Invalid alt name index for register!\");\n" 585 << " return AsmStrs" << AltName << "+RegAsmOffset" 586 << AltName << "[RegNo-1];\n"; 587 } 588 O << " }\n"; 589 } else { 590 O << " assert (*(AsmStrs+RegAsmOffset[RegNo-1]) &&\n" 591 << " \"Invalid alt name index for register!\");\n" 592 << " return AsmStrs+RegAsmOffset[RegNo-1];\n"; 593 } 594 O << "}\n"; 595} 596 597namespace { 598// IAPrinter - Holds information about an InstAlias. Two InstAliases match if 599// they both have the same conditionals. In which case, we cannot print out the 600// alias for that pattern. 601class IAPrinter { 602 std::vector<std::string> Conds; 603 std::map<StringRef, std::pair<int, int>> OpMap; 604 605 std::string Result; 606 std::string AsmString; 607public: 608 IAPrinter(std::string R, std::string AS) 609 : Result(std::move(R)), AsmString(std::move(AS)) {} 610 611 void addCond(const std::string &C) { Conds.push_back(C); } 612 613 void addOperand(StringRef Op, int OpIdx, int PrintMethodIdx = -1) { 614 assert(OpIdx >= 0 && OpIdx < 0xFE && "Idx out of range"); 615 assert(PrintMethodIdx >= -1 && PrintMethodIdx < 0xFF && 616 "Idx out of range"); 617 OpMap[Op] = std::make_pair(OpIdx, PrintMethodIdx); 618 } 619 620 bool isOpMapped(StringRef Op) { return OpMap.find(Op) != OpMap.end(); } 621 int getOpIndex(StringRef Op) { return OpMap[Op].first; } 622 std::pair<int, int> &getOpData(StringRef Op) { return OpMap[Op]; } 623 624 std::pair<StringRef, StringRef::iterator> parseName(StringRef::iterator Start, 625 StringRef::iterator End) { 626 StringRef::iterator I = Start; 627 StringRef::iterator Next; 628 if (*I == '{') { 629 // ${some_name} 630 Start = ++I; 631 while (I != End && *I != '}') 632 ++I; 633 Next = I; 634 // eat the final '}' 635 if (Next != End) 636 ++Next; 637 } else { 638 // $name, just eat the usual suspects. 639 while (I != End && 640 ((*I >= 'a' && *I <= 'z') || (*I >= 'A' && *I <= 'Z') || 641 (*I >= '0' && *I <= '9') || *I == '_')) 642 ++I; 643 Next = I; 644 } 645 646 return std::make_pair(StringRef(Start, I - Start), Next); 647 } 648 649 void print(raw_ostream &O) { 650 if (Conds.empty()) { 651 O.indent(6) << "return true;\n"; 652 return; 653 } 654 655 O << "if ("; 656 657 for (std::vector<std::string>::iterator 658 I = Conds.begin(), E = Conds.end(); I != E; ++I) { 659 if (I != Conds.begin()) { 660 O << " &&\n"; 661 O.indent(8); 662 } 663 664 O << *I; 665 } 666 667 O << ") {\n"; 668 O.indent(6) << "// " << Result << "\n"; 669 670 // Directly mangle mapped operands into the string. Each operand is 671 // identified by a '$' sign followed by a byte identifying the number of the 672 // operand. We add one to the index to avoid zero bytes. 673 StringRef ASM(AsmString); 674 SmallString<128> OutString; 675 raw_svector_ostream OS(OutString); 676 for (StringRef::iterator I = ASM.begin(), E = ASM.end(); I != E;) { 677 OS << *I; 678 if (*I == '$') { 679 StringRef Name; 680 std::tie(Name, I) = parseName(++I, E); 681 assert(isOpMapped(Name) && "Unmapped operand!"); 682 683 int OpIndex, PrintIndex; 684 std::tie(OpIndex, PrintIndex) = getOpData(Name); 685 if (PrintIndex == -1) { 686 // Can use the default printOperand route. 687 OS << format("\\x%02X", (unsigned char)OpIndex + 1); 688 } else 689 // 3 bytes if a PrintMethod is needed: 0xFF, the MCInst operand 690 // number, and which of our pre-detected Methods to call. 691 OS << format("\\xFF\\x%02X\\x%02X", OpIndex + 1, PrintIndex + 1); 692 } else { 693 ++I; 694 } 695 } 696 697 // Emit the string. 698 O.indent(6) << "AsmString = \"" << OutString << "\";\n"; 699 700 O.indent(6) << "break;\n"; 701 O.indent(4) << '}'; 702 } 703 704 bool operator==(const IAPrinter &RHS) const { 705 if (Conds.size() != RHS.Conds.size()) 706 return false; 707 708 unsigned Idx = 0; 709 for (const auto &str : Conds) 710 if (str != RHS.Conds[Idx++]) 711 return false; 712 713 return true; 714 } 715}; 716 717} // end anonymous namespace 718 719static unsigned CountNumOperands(StringRef AsmString, unsigned Variant) { 720 std::string FlatAsmString = 721 CodeGenInstruction::FlattenAsmStringVariants(AsmString, Variant); 722 AsmString = FlatAsmString; 723 724 return AsmString.count(' ') + AsmString.count('\t'); 725} 726 727namespace { 728struct AliasPriorityComparator { 729 typedef std::pair<CodeGenInstAlias, int> ValueType; 730 bool operator()(const ValueType &LHS, const ValueType &RHS) { 731 if (LHS.second == RHS.second) { 732 // We don't actually care about the order, but for consistency it 733 // shouldn't depend on pointer comparisons. 734 return LHS.first.TheDef->getName() < RHS.first.TheDef->getName(); 735 } 736 737 // Aliases with larger priorities should be considered first. 738 return LHS.second > RHS.second; 739 } 740}; 741} 742 743 744void AsmWriterEmitter::EmitPrintAliasInstruction(raw_ostream &O) { 745 Record *AsmWriter = Target.getAsmWriter(); 746 747 O << "\n#ifdef PRINT_ALIAS_INSTR\n"; 748 O << "#undef PRINT_ALIAS_INSTR\n\n"; 749 750 ////////////////////////////// 751 // Gather information about aliases we need to print 752 ////////////////////////////// 753 754 // Emit the method that prints the alias instruction. 755 std::string ClassName = AsmWriter->getValueAsString("AsmWriterClassName"); 756 unsigned Variant = AsmWriter->getValueAsInt("Variant"); 757 bool PassSubtarget = AsmWriter->getValueAsInt("PassSubtarget"); 758 759 std::vector<Record*> AllInstAliases = 760 Records.getAllDerivedDefinitions("InstAlias"); 761 762 // Create a map from the qualified name to a list of potential matches. 763 typedef std::set<std::pair<CodeGenInstAlias, int>, AliasPriorityComparator> 764 AliasWithPriority; 765 std::map<std::string, AliasWithPriority> AliasMap; 766 for (Record *R : AllInstAliases) { 767 int Priority = R->getValueAsInt("EmitPriority"); 768 if (Priority < 1) 769 continue; // Aliases with priority 0 are never emitted. 770 771 const DagInit *DI = R->getValueAsDag("ResultInst"); 772 const DefInit *Op = cast<DefInit>(DI->getOperator()); 773 AliasMap[getQualifiedName(Op->getDef())].insert( 774 std::make_pair(CodeGenInstAlias(R, Variant, Target), Priority)); 775 } 776 777 // A map of which conditions need to be met for each instruction operand 778 // before it can be matched to the mnemonic. 779 std::map<std::string, std::vector<IAPrinter>> IAPrinterMap; 780 781 std::vector<std::string> PrintMethods; 782 783 // A list of MCOperandPredicates for all operands in use, and the reverse map 784 std::vector<const Record*> MCOpPredicates; 785 DenseMap<const Record*, unsigned> MCOpPredicateMap; 786 787 for (auto &Aliases : AliasMap) { 788 for (auto &Alias : Aliases.second) { 789 const CodeGenInstAlias &CGA = Alias.first; 790 unsigned LastOpNo = CGA.ResultInstOperandIndex.size(); 791 unsigned NumResultOps = 792 CountNumOperands(CGA.ResultInst->AsmString, Variant); 793 794 // Don't emit the alias if it has more operands than what it's aliasing. 795 if (NumResultOps < CountNumOperands(CGA.AsmString, Variant)) 796 continue; 797 798 IAPrinter IAP(CGA.Result->getAsString(), CGA.AsmString); 799 800 std::string Namespace = Target.getName(); 801 std::vector<Record *> ReqFeatures; 802 if (PassSubtarget) { 803 // We only consider ReqFeatures predicates if PassSubtarget 804 std::vector<Record *> RF = 805 CGA.TheDef->getValueAsListOfDefs("Predicates"); 806 std::copy_if(RF.begin(), RF.end(), std::back_inserter(ReqFeatures), 807 [](Record *R) { 808 return R->getValueAsBit("AssemblerMatcherPredicate"); 809 }); 810 } 811 812 unsigned NumMIOps = 0; 813 for (auto &Operand : CGA.ResultOperands) 814 NumMIOps += Operand.getMINumOperands(); 815 816 std::string Cond; 817 Cond = std::string("MI->getNumOperands() == ") + llvm::utostr(NumMIOps); 818 IAP.addCond(Cond); 819 820 bool CantHandle = false; 821 822 unsigned MIOpNum = 0; 823 for (unsigned i = 0, e = LastOpNo; i != e; ++i) { 824 std::string Op = "MI->getOperand(" + llvm::utostr(MIOpNum) + ")"; 825 826 const CodeGenInstAlias::ResultOperand &RO = CGA.ResultOperands[i]; 827 828 switch (RO.Kind) { 829 case CodeGenInstAlias::ResultOperand::K_Record: { 830 const Record *Rec = RO.getRecord(); 831 StringRef ROName = RO.getName(); 832 int PrintMethodIdx = -1; 833 834 // These two may have a PrintMethod, which we want to record (if it's 835 // the first time we've seen it) and provide an index for the aliasing 836 // code to use. 837 if (Rec->isSubClassOf("RegisterOperand") || 838 Rec->isSubClassOf("Operand")) { 839 std::string PrintMethod = Rec->getValueAsString("PrintMethod"); 840 if (PrintMethod != "" && PrintMethod != "printOperand") { 841 PrintMethodIdx = std::find(PrintMethods.begin(), 842 PrintMethods.end(), PrintMethod) - 843 PrintMethods.begin(); 844 if (static_cast<unsigned>(PrintMethodIdx) == PrintMethods.size()) 845 PrintMethods.push_back(PrintMethod); 846 } 847 } 848 849 if (Rec->isSubClassOf("RegisterOperand")) 850 Rec = Rec->getValueAsDef("RegClass"); 851 if (Rec->isSubClassOf("RegisterClass")) { 852 IAP.addCond(Op + ".isReg()"); 853 854 if (!IAP.isOpMapped(ROName)) { 855 IAP.addOperand(ROName, MIOpNum, PrintMethodIdx); 856 Record *R = CGA.ResultOperands[i].getRecord(); 857 if (R->isSubClassOf("RegisterOperand")) 858 R = R->getValueAsDef("RegClass"); 859 Cond = std::string("MRI.getRegClass(") + Target.getName() + "::" + 860 R->getName() + "RegClassID)" 861 ".contains(" + Op + ".getReg())"; 862 } else { 863 Cond = Op + ".getReg() == MI->getOperand(" + 864 llvm::utostr(IAP.getOpIndex(ROName)) + ").getReg()"; 865 } 866 } else { 867 // Assume all printable operands are desired for now. This can be 868 // overridden in the InstAlias instantiation if necessary. 869 IAP.addOperand(ROName, MIOpNum, PrintMethodIdx); 870 871 // There might be an additional predicate on the MCOperand 872 unsigned Entry = MCOpPredicateMap[Rec]; 873 if (!Entry) { 874 if (!Rec->isValueUnset("MCOperandPredicate")) { 875 MCOpPredicates.push_back(Rec); 876 Entry = MCOpPredicates.size(); 877 MCOpPredicateMap[Rec] = Entry; 878 } else 879 break; // No conditions on this operand at all 880 } 881 Cond = Target.getName() + ClassName + "ValidateMCOperand(" + 882 Op + ", STI, " + llvm::utostr(Entry) + ")"; 883 } 884 // for all subcases of ResultOperand::K_Record: 885 IAP.addCond(Cond); 886 break; 887 } 888 case CodeGenInstAlias::ResultOperand::K_Imm: { 889 // Just because the alias has an immediate result, doesn't mean the 890 // MCInst will. An MCExpr could be present, for example. 891 IAP.addCond(Op + ".isImm()"); 892 893 Cond = Op + ".getImm() == " + 894 llvm::utostr(CGA.ResultOperands[i].getImm()); 895 IAP.addCond(Cond); 896 break; 897 } 898 case CodeGenInstAlias::ResultOperand::K_Reg: 899 // If this is zero_reg, something's playing tricks we're not 900 // equipped to handle. 901 if (!CGA.ResultOperands[i].getRegister()) { 902 CantHandle = true; 903 break; 904 } 905 906 Cond = Op + ".getReg() == " + Target.getName() + "::" + 907 CGA.ResultOperands[i].getRegister()->getName(); 908 IAP.addCond(Cond); 909 break; 910 } 911 912 MIOpNum += RO.getMINumOperands(); 913 } 914 915 if (CantHandle) continue; 916 917 for (auto I = ReqFeatures.cbegin(); I != ReqFeatures.cend(); I++) { 918 Record *R = *I; 919 std::string AsmCondString = R->getValueAsString("AssemblerCondString"); 920 921 // AsmCondString has syntax [!]F(,[!]F)* 922 SmallVector<StringRef, 4> Ops; 923 SplitString(AsmCondString, Ops, ","); 924 assert(!Ops.empty() && "AssemblerCondString cannot be empty"); 925 926 for (auto &Op : Ops) { 927 assert(!Op.empty() && "Empty operator"); 928 if (Op[0] == '!') 929 Cond = "!STI.getFeatureBits()[" + Namespace + "::" + 930 Op.substr(1).str() + "]"; 931 else 932 Cond = "STI.getFeatureBits()[" + Namespace + "::" + Op.str() + "]"; 933 IAP.addCond(Cond); 934 } 935 } 936 937 IAPrinterMap[Aliases.first].push_back(std::move(IAP)); 938 } 939 } 940 941 ////////////////////////////// 942 // Write out the printAliasInstr function 943 ////////////////////////////// 944 945 std::string Header; 946 raw_string_ostream HeaderO(Header); 947 948 HeaderO << "bool " << Target.getName() << ClassName 949 << "::printAliasInstr(const MCInst" 950 << " *MI, " << (PassSubtarget ? "const MCSubtargetInfo &STI, " : "") 951 << "raw_ostream &OS) {\n"; 952 953 std::string Cases; 954 raw_string_ostream CasesO(Cases); 955 956 for (auto &Entry : IAPrinterMap) { 957 std::vector<IAPrinter> &IAPs = Entry.second; 958 std::vector<IAPrinter*> UniqueIAPs; 959 960 for (auto &LHS : IAPs) { 961 bool IsDup = false; 962 for (const auto &RHS : IAPs) { 963 if (&LHS != &RHS && LHS == RHS) { 964 IsDup = true; 965 break; 966 } 967 } 968 969 if (!IsDup) 970 UniqueIAPs.push_back(&LHS); 971 } 972 973 if (UniqueIAPs.empty()) continue; 974 975 CasesO.indent(2) << "case " << Entry.first << ":\n"; 976 977 for (IAPrinter *IAP : UniqueIAPs) { 978 CasesO.indent(4); 979 IAP->print(CasesO); 980 CasesO << '\n'; 981 } 982 983 CasesO.indent(4) << "return false;\n"; 984 } 985 986 if (CasesO.str().empty()) { 987 O << HeaderO.str(); 988 O << " return false;\n"; 989 O << "}\n\n"; 990 O << "#endif // PRINT_ALIAS_INSTR\n"; 991 return; 992 } 993 994 if (!MCOpPredicates.empty()) 995 O << "static bool " << Target.getName() << ClassName 996 << "ValidateMCOperand(const MCOperand &MCOp,\n" 997 << " const MCSubtargetInfo &STI,\n" 998 << " unsigned PredicateIndex);\n"; 999 1000 O << HeaderO.str(); 1001 O.indent(2) << "const char *AsmString;\n"; 1002 O.indent(2) << "switch (MI->getOpcode()) {\n"; 1003 O.indent(2) << "default: return false;\n"; 1004 O << CasesO.str(); 1005 O.indent(2) << "}\n\n"; 1006 1007 // Code that prints the alias, replacing the operands with the ones from the 1008 // MCInst. 1009 O << " unsigned I = 0;\n"; 1010 O << " while (AsmString[I] != ' ' && AsmString[I] != '\\t' &&\n"; 1011 O << " AsmString[I] != '$' && AsmString[I] != '\\0')\n"; 1012 O << " ++I;\n"; 1013 O << " OS << '\\t' << StringRef(AsmString, I);\n"; 1014 1015 O << " if (AsmString[I] != '\\0') {\n"; 1016 O << " if (AsmString[I] == ' ' || AsmString[I] == '\\t')"; 1017 O << " OS << '\\t';\n"; 1018 O << " do {\n"; 1019 O << " if (AsmString[I] == '$') {\n"; 1020 O << " ++I;\n"; 1021 O << " if (AsmString[I] == (char)0xff) {\n"; 1022 O << " ++I;\n"; 1023 O << " int OpIdx = AsmString[I++] - 1;\n"; 1024 O << " int PrintMethodIdx = AsmString[I++] - 1;\n"; 1025 O << " printCustomAliasOperand(MI, OpIdx, PrintMethodIdx, "; 1026 O << (PassSubtarget ? "STI, " : ""); 1027 O << "OS);\n"; 1028 O << " } else\n"; 1029 O << " printOperand(MI, unsigned(AsmString[I++]) - 1, "; 1030 O << (PassSubtarget ? "STI, " : ""); 1031 O << "OS);\n"; 1032 O << " } else {\n"; 1033 O << " OS << AsmString[I++];\n"; 1034 O << " }\n"; 1035 O << " } while (AsmString[I] != '\\0');\n"; 1036 O << " }\n\n"; 1037 1038 O << " return true;\n"; 1039 O << "}\n\n"; 1040 1041 ////////////////////////////// 1042 // Write out the printCustomAliasOperand function 1043 ////////////////////////////// 1044 1045 O << "void " << Target.getName() << ClassName << "::" 1046 << "printCustomAliasOperand(\n" 1047 << " const MCInst *MI, unsigned OpIdx,\n" 1048 << " unsigned PrintMethodIdx,\n" 1049 << (PassSubtarget ? " const MCSubtargetInfo &STI,\n" : "") 1050 << " raw_ostream &OS) {\n"; 1051 if (PrintMethods.empty()) 1052 O << " llvm_unreachable(\"Unknown PrintMethod kind\");\n"; 1053 else { 1054 O << " switch (PrintMethodIdx) {\n" 1055 << " default:\n" 1056 << " llvm_unreachable(\"Unknown PrintMethod kind\");\n" 1057 << " break;\n"; 1058 1059 for (unsigned i = 0; i < PrintMethods.size(); ++i) { 1060 O << " case " << i << ":\n" 1061 << " " << PrintMethods[i] << "(MI, OpIdx, " 1062 << (PassSubtarget ? "STI, " : "") << "OS);\n" 1063 << " break;\n"; 1064 } 1065 O << " }\n"; 1066 } 1067 O << "}\n\n"; 1068 1069 if (!MCOpPredicates.empty()) { 1070 O << "static bool " << Target.getName() << ClassName 1071 << "ValidateMCOperand(const MCOperand &MCOp,\n" 1072 << " const MCSubtargetInfo &STI,\n" 1073 << " unsigned PredicateIndex) {\n" 1074 << " switch (PredicateIndex) {\n" 1075 << " default:\n" 1076 << " llvm_unreachable(\"Unknown MCOperandPredicate kind\");\n" 1077 << " break;\n"; 1078 1079 for (unsigned i = 0; i < MCOpPredicates.size(); ++i) { 1080 Init *MCOpPred = MCOpPredicates[i]->getValueInit("MCOperandPredicate"); 1081 if (CodeInit *SI = dyn_cast<CodeInit>(MCOpPred)) { 1082 O << " case " << i + 1 << ": {\n" 1083 << SI->getValue() << "\n" 1084 << " }\n"; 1085 } else 1086 llvm_unreachable("Unexpected MCOperandPredicate field!"); 1087 } 1088 O << " }\n" 1089 << "}\n\n"; 1090 } 1091 1092 O << "#endif // PRINT_ALIAS_INSTR\n"; 1093} 1094 1095AsmWriterEmitter::AsmWriterEmitter(RecordKeeper &R) : Records(R), Target(R) { 1096 Record *AsmWriter = Target.getAsmWriter(); 1097 unsigned Variant = AsmWriter->getValueAsInt("Variant"); 1098 1099 // Get the instruction numbering. 1100 NumberedInstructions = Target.getInstructionsByEnumValue(); 1101 1102 for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) { 1103 const CodeGenInstruction *I = NumberedInstructions[i]; 1104 if (!I->AsmString.empty() && I->TheDef->getName() != "PHI") 1105 Instructions.emplace_back(*I, i, Variant); 1106 } 1107} 1108 1109void AsmWriterEmitter::run(raw_ostream &O) { 1110 EmitPrintInstruction(O); 1111 EmitGetRegisterName(O); 1112 EmitPrintAliasInstruction(O); 1113} 1114 1115 1116namespace llvm { 1117 1118void EmitAsmWriter(RecordKeeper &RK, raw_ostream &OS) { 1119 emitSourceFileHeader("Assembly Writer Source Fragment", OS); 1120 AsmWriterEmitter(RK).run(OS); 1121} 1122 1123} // End llvm namespace 1124