r300_state.c revision 2eeaf773fdd58c176f7cdbcd05b75ad3a5ecab4c
1/* 2 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com> 3 * Copyright 2009 Marek Olšák <maraeo@gmail.com> 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * on the rights to use, copy, modify, merge, publish, distribute, sub 9 * license, and/or sell copies of the Software, and to permit persons to whom 10 * the Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, 20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 22 * USE OR OTHER DEALINGS IN THE SOFTWARE. */ 23 24#include "draw/draw_context.h" 25 26#include "util/u_blitter.h" 27#include "util/u_math.h" 28#include "util/u_mm.h" 29#include "util/u_memory.h" 30#include "util/u_pack_color.h" 31 32#include "tgsi/tgsi_parse.h" 33 34#include "pipe/p_config.h" 35 36#include "r300_cb.h" 37#include "r300_context.h" 38#include "r300_emit.h" 39#include "r300_reg.h" 40#include "r300_screen.h" 41#include "r300_screen_buffer.h" 42#include "r300_state_inlines.h" 43#include "r300_fs.h" 44#include "r300_texture.h" 45#include "r300_vs.h" 46#include "r300_winsys.h" 47#include "r300_hyperz.h" 48 49/* r300_state: Functions used to intialize state context by translating 50 * Gallium state objects into semi-native r300 state objects. */ 51 52#define UPDATE_STATE(cso, atom) \ 53 if (cso != atom.state) { \ 54 atom.state = cso; \ 55 atom.dirty = TRUE; \ 56 } 57 58static boolean blend_discard_if_src_alpha_0(unsigned srcRGB, unsigned srcA, 59 unsigned dstRGB, unsigned dstA) 60{ 61 /* If the blend equation is ADD or REVERSE_SUBTRACT, 62 * SRC_ALPHA == 0, and the following state is set, the colorbuffer 63 * will not be changed. 64 * Notice that the dst factors are the src factors inverted. */ 65 return (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA || 66 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE || 67 srcRGB == PIPE_BLENDFACTOR_ZERO) && 68 (srcA == PIPE_BLENDFACTOR_SRC_COLOR || 69 srcA == PIPE_BLENDFACTOR_SRC_ALPHA || 70 srcA == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE || 71 srcA == PIPE_BLENDFACTOR_ZERO) && 72 (dstRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA || 73 dstRGB == PIPE_BLENDFACTOR_ONE) && 74 (dstA == PIPE_BLENDFACTOR_INV_SRC_COLOR || 75 dstA == PIPE_BLENDFACTOR_INV_SRC_ALPHA || 76 dstA == PIPE_BLENDFACTOR_ONE); 77} 78 79static boolean blend_discard_if_src_alpha_1(unsigned srcRGB, unsigned srcA, 80 unsigned dstRGB, unsigned dstA) 81{ 82 /* If the blend equation is ADD or REVERSE_SUBTRACT, 83 * SRC_ALPHA == 1, and the following state is set, the colorbuffer 84 * will not be changed. 85 * Notice that the dst factors are the src factors inverted. */ 86 return (srcRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA || 87 srcRGB == PIPE_BLENDFACTOR_ZERO) && 88 (srcA == PIPE_BLENDFACTOR_INV_SRC_COLOR || 89 srcA == PIPE_BLENDFACTOR_INV_SRC_ALPHA || 90 srcA == PIPE_BLENDFACTOR_ZERO) && 91 (dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA || 92 dstRGB == PIPE_BLENDFACTOR_ONE) && 93 (dstA == PIPE_BLENDFACTOR_SRC_COLOR || 94 dstA == PIPE_BLENDFACTOR_SRC_ALPHA || 95 dstA == PIPE_BLENDFACTOR_ONE); 96} 97 98static boolean blend_discard_if_src_color_0(unsigned srcRGB, unsigned srcA, 99 unsigned dstRGB, unsigned dstA) 100{ 101 /* If the blend equation is ADD or REVERSE_SUBTRACT, 102 * SRC_COLOR == (0,0,0), and the following state is set, the colorbuffer 103 * will not be changed. 104 * Notice that the dst factors are the src factors inverted. */ 105 return (srcRGB == PIPE_BLENDFACTOR_SRC_COLOR || 106 srcRGB == PIPE_BLENDFACTOR_ZERO) && 107 (srcA == PIPE_BLENDFACTOR_ZERO) && 108 (dstRGB == PIPE_BLENDFACTOR_INV_SRC_COLOR || 109 dstRGB == PIPE_BLENDFACTOR_ONE) && 110 (dstA == PIPE_BLENDFACTOR_ONE); 111} 112 113static boolean blend_discard_if_src_color_1(unsigned srcRGB, unsigned srcA, 114 unsigned dstRGB, unsigned dstA) 115{ 116 /* If the blend equation is ADD or REVERSE_SUBTRACT, 117 * SRC_COLOR == (1,1,1), and the following state is set, the colorbuffer 118 * will not be changed. 119 * Notice that the dst factors are the src factors inverted. */ 120 return (srcRGB == PIPE_BLENDFACTOR_INV_SRC_COLOR || 121 srcRGB == PIPE_BLENDFACTOR_ZERO) && 122 (srcA == PIPE_BLENDFACTOR_ZERO) && 123 (dstRGB == PIPE_BLENDFACTOR_SRC_COLOR || 124 dstRGB == PIPE_BLENDFACTOR_ONE) && 125 (dstA == PIPE_BLENDFACTOR_ONE); 126} 127 128static boolean blend_discard_if_src_alpha_color_0(unsigned srcRGB, unsigned srcA, 129 unsigned dstRGB, unsigned dstA) 130{ 131 /* If the blend equation is ADD or REVERSE_SUBTRACT, 132 * SRC_ALPHA_COLOR == (0,0,0,0), and the following state is set, 133 * the colorbuffer will not be changed. 134 * Notice that the dst factors are the src factors inverted. */ 135 return (srcRGB == PIPE_BLENDFACTOR_SRC_COLOR || 136 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA || 137 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE || 138 srcRGB == PIPE_BLENDFACTOR_ZERO) && 139 (srcA == PIPE_BLENDFACTOR_SRC_COLOR || 140 srcA == PIPE_BLENDFACTOR_SRC_ALPHA || 141 srcA == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE || 142 srcA == PIPE_BLENDFACTOR_ZERO) && 143 (dstRGB == PIPE_BLENDFACTOR_INV_SRC_COLOR || 144 dstRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA || 145 dstRGB == PIPE_BLENDFACTOR_ONE) && 146 (dstA == PIPE_BLENDFACTOR_INV_SRC_COLOR || 147 dstA == PIPE_BLENDFACTOR_INV_SRC_ALPHA || 148 dstA == PIPE_BLENDFACTOR_ONE); 149} 150 151static boolean blend_discard_if_src_alpha_color_1(unsigned srcRGB, unsigned srcA, 152 unsigned dstRGB, unsigned dstA) 153{ 154 /* If the blend equation is ADD or REVERSE_SUBTRACT, 155 * SRC_ALPHA_COLOR == (1,1,1,1), and the following state is set, 156 * the colorbuffer will not be changed. 157 * Notice that the dst factors are the src factors inverted. */ 158 return (srcRGB == PIPE_BLENDFACTOR_INV_SRC_COLOR || 159 srcRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA || 160 srcRGB == PIPE_BLENDFACTOR_ZERO) && 161 (srcA == PIPE_BLENDFACTOR_INV_SRC_COLOR || 162 srcA == PIPE_BLENDFACTOR_INV_SRC_ALPHA || 163 srcA == PIPE_BLENDFACTOR_ZERO) && 164 (dstRGB == PIPE_BLENDFACTOR_SRC_COLOR || 165 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA || 166 dstRGB == PIPE_BLENDFACTOR_ONE) && 167 (dstA == PIPE_BLENDFACTOR_SRC_COLOR || 168 dstA == PIPE_BLENDFACTOR_SRC_ALPHA || 169 dstA == PIPE_BLENDFACTOR_ONE); 170} 171 172static unsigned bgra_cmask(unsigned mask) 173{ 174 /* Gallium uses RGBA color ordering while R300 expects BGRA. */ 175 176 return ((mask & PIPE_MASK_R) << 2) | 177 ((mask & PIPE_MASK_B) >> 2) | 178 (mask & (PIPE_MASK_G | PIPE_MASK_A)); 179} 180 181/* Create a new blend state based on the CSO blend state. 182 * 183 * This encompasses alpha blending, logic/raster ops, and blend dithering. */ 184static void* r300_create_blend_state(struct pipe_context* pipe, 185 const struct pipe_blend_state* state) 186{ 187 struct r300_screen* r300screen = r300_screen(pipe->screen); 188 struct r300_blend_state* blend = CALLOC_STRUCT(r300_blend_state); 189 uint32_t blend_control = 0; /* R300_RB3D_CBLEND: 0x4e04 */ 190 uint32_t alpha_blend_control = 0; /* R300_RB3D_ABLEND: 0x4e08 */ 191 uint32_t color_channel_mask = 0; /* R300_RB3D_COLOR_CHANNEL_MASK: 0x4e0c */ 192 uint32_t rop = 0; /* R300_RB3D_ROPCNTL: 0x4e18 */ 193 uint32_t dither = 0; /* R300_RB3D_DITHER_CTL: 0x4e50 */ 194 CB_LOCALS; 195 196 if (state->rt[0].blend_enable) 197 { 198 unsigned eqRGB = state->rt[0].rgb_func; 199 unsigned srcRGB = state->rt[0].rgb_src_factor; 200 unsigned dstRGB = state->rt[0].rgb_dst_factor; 201 202 unsigned eqA = state->rt[0].alpha_func; 203 unsigned srcA = state->rt[0].alpha_src_factor; 204 unsigned dstA = state->rt[0].alpha_dst_factor; 205 206 /* despite the name, ALPHA_BLEND_ENABLE has nothing to do with alpha, 207 * this is just the crappy D3D naming */ 208 blend_control = R300_ALPHA_BLEND_ENABLE | 209 r300_translate_blend_function(eqRGB) | 210 ( r300_translate_blend_factor(srcRGB) << R300_SRC_BLEND_SHIFT) | 211 ( r300_translate_blend_factor(dstRGB) << R300_DST_BLEND_SHIFT); 212 213 /* Optimization: some operations do not require the destination color. 214 * 215 * When SRC_ALPHA_SATURATE is used, colorbuffer reads must be enabled, 216 * otherwise blending gives incorrect results. It seems to be 217 * a hardware bug. */ 218 if (eqRGB == PIPE_BLEND_MIN || eqA == PIPE_BLEND_MIN || 219 eqRGB == PIPE_BLEND_MAX || eqA == PIPE_BLEND_MAX || 220 dstRGB != PIPE_BLENDFACTOR_ZERO || 221 dstA != PIPE_BLENDFACTOR_ZERO || 222 srcRGB == PIPE_BLENDFACTOR_DST_COLOR || 223 srcRGB == PIPE_BLENDFACTOR_DST_ALPHA || 224 srcRGB == PIPE_BLENDFACTOR_INV_DST_COLOR || 225 srcRGB == PIPE_BLENDFACTOR_INV_DST_ALPHA || 226 srcA == PIPE_BLENDFACTOR_DST_COLOR || 227 srcA == PIPE_BLENDFACTOR_DST_ALPHA || 228 srcA == PIPE_BLENDFACTOR_INV_DST_COLOR || 229 srcA == PIPE_BLENDFACTOR_INV_DST_ALPHA || 230 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE) { 231 /* Enable reading from the colorbuffer. */ 232 blend_control |= R300_READ_ENABLE; 233 234 if (r300screen->caps.is_r500) { 235 /* Optimization: Depending on incoming pixels, we can 236 * conditionally disable the reading in hardware... */ 237 if (eqRGB != PIPE_BLEND_MIN && eqA != PIPE_BLEND_MIN && 238 eqRGB != PIPE_BLEND_MAX && eqA != PIPE_BLEND_MAX) { 239 /* Disable reading if SRC_ALPHA == 0. */ 240 if ((dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA || 241 dstRGB == PIPE_BLENDFACTOR_ZERO) && 242 (dstA == PIPE_BLENDFACTOR_SRC_COLOR || 243 dstA == PIPE_BLENDFACTOR_SRC_ALPHA || 244 dstA == PIPE_BLENDFACTOR_ZERO)) { 245 blend_control |= R500_SRC_ALPHA_0_NO_READ; 246 } 247 248 /* Disable reading if SRC_ALPHA == 1. */ 249 if ((dstRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA || 250 dstRGB == PIPE_BLENDFACTOR_ZERO) && 251 (dstA == PIPE_BLENDFACTOR_INV_SRC_COLOR || 252 dstA == PIPE_BLENDFACTOR_INV_SRC_ALPHA || 253 dstA == PIPE_BLENDFACTOR_ZERO)) { 254 blend_control |= R500_SRC_ALPHA_1_NO_READ; 255 } 256 } 257 } 258 } 259 260 /* Optimization: discard pixels which don't change the colorbuffer. 261 * 262 * The code below is non-trivial and some math is involved. 263 * 264 * Discarding pixels must be disabled when FP16 AA is enabled. 265 * This is a hardware bug. Also, this implementation wouldn't work 266 * with FP blending enabled and equation clamping disabled. 267 * 268 * Equations other than ADD are rarely used and therefore won't be 269 * optimized. */ 270 if ((eqRGB == PIPE_BLEND_ADD || eqRGB == PIPE_BLEND_REVERSE_SUBTRACT) && 271 (eqA == PIPE_BLEND_ADD || eqA == PIPE_BLEND_REVERSE_SUBTRACT)) { 272 /* ADD: X+Y 273 * REVERSE_SUBTRACT: Y-X 274 * 275 * The idea is: 276 * If X = src*srcFactor = 0 and Y = dst*dstFactor = 1, 277 * then CB will not be changed. 278 * 279 * Given the srcFactor and dstFactor variables, we can derive 280 * what src and dst should be equal to and discard appropriate 281 * pixels. 282 */ 283 if (blend_discard_if_src_alpha_0(srcRGB, srcA, dstRGB, dstA)) { 284 blend_control |= R300_DISCARD_SRC_PIXELS_SRC_ALPHA_0; 285 } else if (blend_discard_if_src_alpha_1(srcRGB, srcA, 286 dstRGB, dstA)) { 287 blend_control |= R300_DISCARD_SRC_PIXELS_SRC_ALPHA_1; 288 } else if (blend_discard_if_src_color_0(srcRGB, srcA, 289 dstRGB, dstA)) { 290 blend_control |= R300_DISCARD_SRC_PIXELS_SRC_COLOR_0; 291 } else if (blend_discard_if_src_color_1(srcRGB, srcA, 292 dstRGB, dstA)) { 293 blend_control |= R300_DISCARD_SRC_PIXELS_SRC_COLOR_1; 294 } else if (blend_discard_if_src_alpha_color_0(srcRGB, srcA, 295 dstRGB, dstA)) { 296 blend_control |= 297 R300_DISCARD_SRC_PIXELS_SRC_ALPHA_COLOR_0; 298 } else if (blend_discard_if_src_alpha_color_1(srcRGB, srcA, 299 dstRGB, dstA)) { 300 blend_control |= 301 R300_DISCARD_SRC_PIXELS_SRC_ALPHA_COLOR_1; 302 } 303 } 304 305 /* separate alpha */ 306 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) { 307 blend_control |= R300_SEPARATE_ALPHA_ENABLE; 308 alpha_blend_control = 309 r300_translate_blend_function(eqA) | 310 (r300_translate_blend_factor(srcA) << R300_SRC_BLEND_SHIFT) | 311 (r300_translate_blend_factor(dstA) << R300_DST_BLEND_SHIFT); 312 } 313 } 314 315 /* PIPE_LOGICOP_* don't need to be translated, fortunately. */ 316 if (state->logicop_enable) { 317 rop = R300_RB3D_ROPCNTL_ROP_ENABLE | 318 (state->logicop_func) << R300_RB3D_ROPCNTL_ROP_SHIFT; 319 } 320 321 /* Color channel masks for all MRTs. */ 322 color_channel_mask = bgra_cmask(state->rt[0].colormask); 323 if (r300screen->caps.is_r500 && state->independent_blend_enable) { 324 if (state->rt[1].blend_enable) { 325 color_channel_mask |= bgra_cmask(state->rt[1].colormask) << 4; 326 } 327 if (state->rt[2].blend_enable) { 328 color_channel_mask |= bgra_cmask(state->rt[2].colormask) << 8; 329 } 330 if (state->rt[3].blend_enable) { 331 color_channel_mask |= bgra_cmask(state->rt[3].colormask) << 12; 332 } 333 } 334 335 /* Neither fglrx nor classic r300 ever set this, regardless of dithering 336 * state. Since it's an optional implementation detail, we can leave it 337 * out and never dither. 338 * 339 * This could be revisited if we ever get quality or conformance hints. 340 * 341 if (state->dither) { 342 dither = R300_RB3D_DITHER_CTL_DITHER_MODE_LUT | 343 R300_RB3D_DITHER_CTL_ALPHA_DITHER_MODE_LUT; 344 } 345 */ 346 347 /* Build a command buffer. */ 348 BEGIN_CB(blend->cb, 8); 349 OUT_CB_REG(R300_RB3D_ROPCNTL, rop); 350 OUT_CB_REG_SEQ(R300_RB3D_CBLEND, 3); 351 OUT_CB(blend_control); 352 OUT_CB(alpha_blend_control); 353 OUT_CB(color_channel_mask); 354 OUT_CB_REG(R300_RB3D_DITHER_CTL, dither); 355 END_CB; 356 357 /* The same as above, but with no colorbuffer reads and writes. */ 358 BEGIN_CB(blend->cb_no_readwrite, 8); 359 OUT_CB_REG(R300_RB3D_ROPCNTL, rop); 360 OUT_CB_REG_SEQ(R300_RB3D_CBLEND, 3); 361 OUT_CB(0); 362 OUT_CB(0); 363 OUT_CB(0); 364 OUT_CB_REG(R300_RB3D_DITHER_CTL, dither); 365 END_CB; 366 367 return (void*)blend; 368} 369 370/* Bind blend state. */ 371static void r300_bind_blend_state(struct pipe_context* pipe, 372 void* state) 373{ 374 struct r300_context* r300 = r300_context(pipe); 375 376 UPDATE_STATE(state, r300->blend_state); 377} 378 379/* Free blend state. */ 380static void r300_delete_blend_state(struct pipe_context* pipe, 381 void* state) 382{ 383 FREE(state); 384} 385 386/* Convert float to 10bit integer */ 387static unsigned float_to_fixed10(float f) 388{ 389 return CLAMP((unsigned)(f * 1023.9f), 0, 1023); 390} 391 392/* Set blend color. 393 * Setup both R300 and R500 registers, figure out later which one to write. */ 394static void r300_set_blend_color(struct pipe_context* pipe, 395 const struct pipe_blend_color* color) 396{ 397 struct r300_context* r300 = r300_context(pipe); 398 struct r300_blend_color_state* state = 399 (struct r300_blend_color_state*)r300->blend_color_state.state; 400 CB_LOCALS; 401 402 if (r300->screen->caps.is_r500) { 403 /* XXX if FP16 blending is enabled, we should use the FP16 format */ 404 BEGIN_CB(state->cb, 3); 405 OUT_CB_REG_SEQ(R500_RB3D_CONSTANT_COLOR_AR, 2); 406 OUT_CB(float_to_fixed10(color->color[0]) | 407 (float_to_fixed10(color->color[3]) << 16)); 408 OUT_CB(float_to_fixed10(color->color[2]) | 409 (float_to_fixed10(color->color[1]) << 16)); 410 END_CB; 411 } else { 412 union util_color uc; 413 util_pack_color(color->color, PIPE_FORMAT_B8G8R8A8_UNORM, &uc); 414 415 BEGIN_CB(state->cb, 2); 416 OUT_CB_REG(R300_RB3D_BLEND_COLOR, uc.ui); 417 END_CB; 418 } 419 420 r300->blend_color_state.dirty = TRUE; 421} 422 423static void r300_set_clip_state(struct pipe_context* pipe, 424 const struct pipe_clip_state* state) 425{ 426 struct r300_context* r300 = r300_context(pipe); 427 struct r300_clip_state *clip = 428 (struct r300_clip_state*)r300->clip_state.state; 429 CB_LOCALS; 430 431 clip->clip = *state; 432 433 if (r300->screen->caps.has_tcl) { 434 r300->clip_state.size = 2 + !!state->nr * 3 + state->nr * 4; 435 436 BEGIN_CB(clip->cb, r300->clip_state.size); 437 if (state->nr) { 438 OUT_CB_REG(R300_VAP_PVS_VECTOR_INDX_REG, 439 (r300->screen->caps.is_r500 ? 440 R500_PVS_UCP_START : R300_PVS_UCP_START)); 441 OUT_CB_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, state->nr * 4); 442 OUT_CB_TABLE(state->ucp, state->nr * 4); 443 } 444 OUT_CB_REG(R300_VAP_CLIP_CNTL, ((1 << state->nr) - 1) | 445 R300_PS_UCP_MODE_CLIP_AS_TRIFAN | 446 (state->depth_clamp ? R300_CLIP_DISABLE : 0)); 447 END_CB; 448 449 r300->clip_state.dirty = TRUE; 450 } else { 451 draw_set_clip_state(r300->draw, state); 452 } 453} 454 455static void 456r300_set_sample_mask(struct pipe_context *pipe, 457 unsigned sample_mask) 458{ 459} 460 461 462/* Create a new depth, stencil, and alpha state based on the CSO dsa state. 463 * 464 * This contains the depth buffer, stencil buffer, alpha test, and such. 465 * On the Radeon, depth and stencil buffer setup are intertwined, which is 466 * the reason for some of the strange-looking assignments across registers. */ 467static void* 468 r300_create_dsa_state(struct pipe_context* pipe, 469 const struct pipe_depth_stencil_alpha_state* state) 470{ 471 struct r300_capabilities *caps = &r300_screen(pipe->screen)->caps; 472 struct r300_dsa_state* dsa = CALLOC_STRUCT(r300_dsa_state); 473 CB_LOCALS; 474 475 dsa->dsa = *state; 476 477 /* Depth test setup. - separate write mask depth for decomp flush */ 478 if (state->depth.writemask) { 479 dsa->z_buffer_control |= R300_Z_WRITE_ENABLE; 480 } 481 482 if (state->depth.enabled) { 483 dsa->z_buffer_control |= R300_Z_ENABLE; 484 485 dsa->z_stencil_control |= 486 (r300_translate_depth_stencil_function(state->depth.func) << 487 R300_Z_FUNC_SHIFT); 488 } 489 490 /* Stencil buffer setup. */ 491 if (state->stencil[0].enabled) { 492 dsa->z_buffer_control |= R300_STENCIL_ENABLE; 493 dsa->z_stencil_control |= 494 (r300_translate_depth_stencil_function(state->stencil[0].func) << 495 R300_S_FRONT_FUNC_SHIFT) | 496 (r300_translate_stencil_op(state->stencil[0].fail_op) << 497 R300_S_FRONT_SFAIL_OP_SHIFT) | 498 (r300_translate_stencil_op(state->stencil[0].zpass_op) << 499 R300_S_FRONT_ZPASS_OP_SHIFT) | 500 (r300_translate_stencil_op(state->stencil[0].zfail_op) << 501 R300_S_FRONT_ZFAIL_OP_SHIFT); 502 503 dsa->stencil_ref_mask = 504 (state->stencil[0].valuemask << R300_STENCILMASK_SHIFT) | 505 (state->stencil[0].writemask << R300_STENCILWRITEMASK_SHIFT); 506 507 if (state->stencil[1].enabled) { 508 dsa->two_sided = TRUE; 509 510 dsa->z_buffer_control |= R300_STENCIL_FRONT_BACK; 511 dsa->z_stencil_control |= 512 (r300_translate_depth_stencil_function(state->stencil[1].func) << 513 R300_S_BACK_FUNC_SHIFT) | 514 (r300_translate_stencil_op(state->stencil[1].fail_op) << 515 R300_S_BACK_SFAIL_OP_SHIFT) | 516 (r300_translate_stencil_op(state->stencil[1].zpass_op) << 517 R300_S_BACK_ZPASS_OP_SHIFT) | 518 (r300_translate_stencil_op(state->stencil[1].zfail_op) << 519 R300_S_BACK_ZFAIL_OP_SHIFT); 520 521 dsa->stencil_ref_bf = 522 (state->stencil[1].valuemask << R300_STENCILMASK_SHIFT) | 523 (state->stencil[1].writemask << R300_STENCILWRITEMASK_SHIFT); 524 525 if (caps->is_r500) { 526 dsa->z_buffer_control |= R500_STENCIL_REFMASK_FRONT_BACK; 527 } else { 528 dsa->two_sided_stencil_ref = 529 (state->stencil[0].valuemask != state->stencil[1].valuemask || 530 state->stencil[0].writemask != state->stencil[1].writemask); 531 } 532 } 533 } 534 535 /* Alpha test setup. */ 536 if (state->alpha.enabled) { 537 dsa->alpha_function = 538 r300_translate_alpha_function(state->alpha.func) | 539 R300_FG_ALPHA_FUNC_ENABLE; 540 541 /* We could use 10bit alpha ref but who needs that? */ 542 dsa->alpha_function |= float_to_ubyte(state->alpha.ref_value); 543 544 if (caps->is_r500) 545 dsa->alpha_function |= R500_FG_ALPHA_FUNC_8BIT; 546 } 547 548 BEGIN_CB(&dsa->cb_begin, 8); 549 OUT_CB_REG(R300_FG_ALPHA_FUNC, dsa->alpha_function); 550 OUT_CB_REG_SEQ(R300_ZB_CNTL, 3); 551 OUT_CB(dsa->z_buffer_control); 552 OUT_CB(dsa->z_stencil_control); 553 OUT_CB(dsa->stencil_ref_mask); 554 OUT_CB_REG(R500_ZB_STENCILREFMASK_BF, dsa->stencil_ref_bf); 555 END_CB; 556 557 BEGIN_CB(dsa->cb_no_readwrite, 8); 558 OUT_CB_REG(R300_FG_ALPHA_FUNC, dsa->alpha_function); 559 OUT_CB_REG_SEQ(R300_ZB_CNTL, 3); 560 OUT_CB(0); 561 OUT_CB(0); 562 OUT_CB(0); 563 OUT_CB_REG(R500_ZB_STENCILREFMASK_BF, 0); 564 END_CB; 565 566 return (void*)dsa; 567} 568 569static void r300_dsa_inject_stencilref(struct r300_context *r300) 570{ 571 struct r300_dsa_state *dsa = 572 (struct r300_dsa_state*)r300->dsa_state.state; 573 574 if (!dsa) 575 return; 576 577 dsa->stencil_ref_mask = 578 (dsa->stencil_ref_mask & ~R300_STENCILREF_MASK) | 579 r300->stencil_ref.ref_value[0]; 580 dsa->stencil_ref_bf = 581 (dsa->stencil_ref_bf & ~R300_STENCILREF_MASK) | 582 r300->stencil_ref.ref_value[1]; 583} 584 585/* Bind DSA state. */ 586static void r300_bind_dsa_state(struct pipe_context* pipe, 587 void* state) 588{ 589 struct r300_context* r300 = r300_context(pipe); 590 591 if (!state) { 592 return; 593 } 594 595 UPDATE_STATE(state, r300->dsa_state); 596 597 r300->hyperz_state.dirty = TRUE; /* Will be updated before the emission. */ 598 r300_dsa_inject_stencilref(r300); 599} 600 601/* Free DSA state. */ 602static void r300_delete_dsa_state(struct pipe_context* pipe, 603 void* state) 604{ 605 FREE(state); 606} 607 608static void r300_set_stencil_ref(struct pipe_context* pipe, 609 const struct pipe_stencil_ref* sr) 610{ 611 struct r300_context* r300 = r300_context(pipe); 612 613 r300->stencil_ref = *sr; 614 615 r300_dsa_inject_stencilref(r300); 616 r300->dsa_state.dirty = TRUE; 617} 618 619static void r300_tex_set_tiling_flags(struct r300_context *r300, 620 struct r300_texture *tex, unsigned level) 621{ 622 /* Check if the macrotile flag needs to be changed. 623 * Skip changing the flags otherwise. */ 624 if (tex->desc.macrotile[tex->surface_level] != 625 tex->desc.macrotile[level]) { 626 /* Tiling determines how DRM treats the buffer data. 627 * We must flush CS when changing it if the buffer is referenced. */ 628 if (r300->rws->cs_is_buffer_referenced(r300->cs, 629 tex->buffer, R300_REF_CS)) 630 r300->context.flush(&r300->context, 0, NULL); 631 632 r300->rws->buffer_set_tiling(r300->rws, tex->buffer, 633 tex->desc.microtile, tex->desc.macrotile[level], 634 tex->desc.stride_in_bytes[0]); 635 636 tex->surface_level = level; 637 } 638} 639 640/* This switcheroo is needed just because of goddamned MACRO_SWITCH. */ 641static void r300_fb_set_tiling_flags(struct r300_context *r300, 642 const struct pipe_framebuffer_state *state) 643{ 644 unsigned i; 645 646 /* Set tiling flags for new surfaces. */ 647 for (i = 0; i < state->nr_cbufs; i++) { 648 r300_tex_set_tiling_flags(r300, 649 r300_texture(state->cbufs[i]->texture), 650 state->cbufs[i]->level); 651 } 652 if (state->zsbuf) { 653 r300_tex_set_tiling_flags(r300, 654 r300_texture(state->zsbuf->texture), 655 state->zsbuf->level); 656 } 657} 658 659static void r300_print_fb_surf_info(struct pipe_surface *surf, unsigned index, 660 const char *binding) 661{ 662 struct pipe_resource *tex = surf->texture; 663 struct r300_texture *rtex = r300_texture(tex); 664 665 fprintf(stderr, 666 "r300: %s[%i] Dim: %ix%i, Offset: %i, ZSlice: %i, " 667 "Face: %i, Level: %i, Format: %s\n" 668 669 "r300: TEX: Macro: %s, Micro: %s, Pitch: %i, " 670 "Dim: %ix%ix%i, LastLevel: %i, Format: %s\n", 671 672 binding, index, surf->width, surf->height, surf->offset, 673 surf->zslice, surf->face, surf->level, 674 util_format_short_name(surf->format), 675 676 rtex->desc.macrotile[0] ? "YES" : " NO", 677 rtex->desc.microtile ? "YES" : " NO", 678 rtex->desc.stride_in_pixels[0], 679 tex->width0, tex->height0, tex->depth0, 680 tex->last_level, util_format_short_name(tex->format)); 681} 682 683void r300_mark_fb_state_dirty(struct r300_context *r300, 684 enum r300_fb_state_change change) 685{ 686 struct pipe_framebuffer_state *state = r300->fb_state.state; 687 boolean has_hyperz = r300->rws->get_value(r300->rws, R300_CAN_HYPERZ); 688 689 /* What is marked as dirty depends on the enum r300_fb_state_change. */ 690 r300->gpu_flush.dirty = TRUE; 691 r300->fb_state.dirty = TRUE; 692 r300->hyperz_state.dirty = TRUE; 693 694 if (change == R300_CHANGED_FB_STATE) { 695 r300->aa_state.dirty = TRUE; 696 r300->fb_state_pipelined.dirty = TRUE; 697 } 698 699 /* Now compute the fb_state atom size. */ 700 r300->fb_state.size = 2 + (8 * state->nr_cbufs); 701 702 if (r300->cbzb_clear) 703 r300->fb_state.size += 10; 704 else if (state->zsbuf) { 705 r300->fb_state.size += 10; 706 if (has_hyperz) 707 r300->fb_state.size += r300->screen->caps.hiz_ram ? 8 : 4; 708 } 709 710 /* The size of the rest of atoms stays the same. */ 711} 712 713static void 714 r300_set_framebuffer_state(struct pipe_context* pipe, 715 const struct pipe_framebuffer_state* state) 716{ 717 struct r300_context* r300 = r300_context(pipe); 718 struct r300_aa_state *aa = (struct r300_aa_state*)r300->aa_state.state; 719 struct pipe_framebuffer_state *old_state = r300->fb_state.state; 720 boolean has_hyperz = r300->rws->get_value(r300->rws, R300_CAN_HYPERZ); 721 unsigned max_width, max_height, i; 722 uint32_t zbuffer_bpp = 0; 723 int blocksize; 724 725 if (r300->screen->caps.is_r500) { 726 max_width = max_height = 4096; 727 } else if (r300->screen->caps.is_r400) { 728 max_width = max_height = 4021; 729 } else { 730 max_width = max_height = 2560; 731 } 732 733 if (state->width > max_width || state->height > max_height) { 734 fprintf(stderr, "r300: Implementation error: Render targets are too " 735 "big in %s, refusing to bind framebuffer state!\n", __FUNCTION__); 736 return; 737 } 738 739 /* If nr_cbufs is changed from zero to non-zero or vice versa... */ 740 if (!!old_state->nr_cbufs != !!state->nr_cbufs) { 741 r300->blend_state.dirty = TRUE; 742 } 743 /* If zsbuf is set from NULL to non-NULL or vice versa.. */ 744 if (!!old_state->zsbuf != !!state->zsbuf) { 745 r300->dsa_state.dirty = TRUE; 746 } 747 748 /* The tiling flags are dependent on the surface miplevel, unfortunately. */ 749 r300_fb_set_tiling_flags(r300, state); 750 751 util_assign_framebuffer_state(r300->fb_state.state, state); 752 753 r300_mark_fb_state_dirty(r300, R300_CHANGED_FB_STATE); 754 755 r300->z_compression = false; 756 757 if (state->zsbuf) { 758 blocksize = util_format_get_blocksize(state->zsbuf->texture->format); 759 switch (blocksize) { 760 case 2: 761 zbuffer_bpp = 16; 762 break; 763 case 4: 764 zbuffer_bpp = 24; 765 break; 766 } 767 if (has_hyperz) { 768 struct r300_surface *zs_surf = r300_surface(state->zsbuf); 769 struct r300_texture *tex; 770 int compress = r300->screen->caps.is_rv350 ? RV350_Z_COMPRESS_88 : R300_Z_COMPRESS_44; 771 int level = zs_surf->base.level; 772 773 tex = r300_texture(zs_surf->base.texture); 774 775 /* work out whether we can support hiz on this buffer */ 776 r300_hiz_alloc_block(r300, zs_surf); 777 778 /* work out whether we can support zmask features on this buffer */ 779 r300_zmask_alloc_block(r300, zs_surf, compress); 780 781 if (tex->zmask_mem[level]) { 782 /* compression causes hangs on 16-bit */ 783 if (zbuffer_bpp == 24) 784 r300->z_compression = compress; 785 } 786 DBG(r300, DBG_HYPERZ, 787 "hyper-z features: hiz: %d @ %08x z-compression: %d z-fastfill: %d @ %08x\n", tex->hiz_mem[level] ? 1 : 0, 788 tex->hiz_mem[level] ? tex->hiz_mem[level]->ofs : 0xdeadbeef, 789 r300->z_compression, tex->zmask_mem[level] ? 1 : 0, 790 tex->zmask_mem[level] ? tex->zmask_mem[level]->ofs : 0xdeadbeef); 791 } 792 793 /* Polygon offset depends on the zbuffer bit depth. */ 794 if (r300->zbuffer_bpp != zbuffer_bpp) { 795 r300->zbuffer_bpp = zbuffer_bpp; 796 797 if (r300->polygon_offset_enabled) 798 r300->rs_state.dirty = TRUE; 799 } 800 } 801 802 /* Set up AA config. */ 803 if (r300->rws->get_value(r300->rws, R300_VID_DRM_2_3_0)) { 804 if (state->nr_cbufs && state->cbufs[0]->texture->nr_samples > 1) { 805 aa->aa_config = R300_GB_AA_CONFIG_AA_ENABLE; 806 807 switch (state->cbufs[0]->texture->nr_samples) { 808 case 2: 809 aa->aa_config |= R300_GB_AA_CONFIG_NUM_AA_SUBSAMPLES_2; 810 break; 811 case 3: 812 aa->aa_config |= R300_GB_AA_CONFIG_NUM_AA_SUBSAMPLES_3; 813 break; 814 case 4: 815 aa->aa_config |= R300_GB_AA_CONFIG_NUM_AA_SUBSAMPLES_4; 816 break; 817 case 6: 818 aa->aa_config |= R300_GB_AA_CONFIG_NUM_AA_SUBSAMPLES_6; 819 break; 820 } 821 } else { 822 aa->aa_config = 0; 823 } 824 } 825 826 if (DBG_ON(r300, DBG_FB)) { 827 fprintf(stderr, "r300: set_framebuffer_state:\n"); 828 for (i = 0; i < state->nr_cbufs; i++) { 829 r300_print_fb_surf_info(state->cbufs[i], i, "CB"); 830 } 831 if (state->zsbuf) { 832 r300_print_fb_surf_info(state->zsbuf, 0, "ZB"); 833 } 834 } 835} 836 837/* Create fragment shader state. */ 838static void* r300_create_fs_state(struct pipe_context* pipe, 839 const struct pipe_shader_state* shader) 840{ 841 struct r300_fragment_shader* fs = NULL; 842 843 fs = (struct r300_fragment_shader*)CALLOC_STRUCT(r300_fragment_shader); 844 845 /* Copy state directly into shader. */ 846 fs->state = *shader; 847 fs->state.tokens = tgsi_dup_tokens(shader->tokens); 848 849 return (void*)fs; 850} 851 852void r300_mark_fs_code_dirty(struct r300_context *r300) 853{ 854 struct r300_fragment_shader* fs = r300_fs(r300); 855 856 r300->fs.dirty = TRUE; 857 r300->fs_rc_constant_state.dirty = TRUE; 858 r300->fs_constants.dirty = TRUE; 859 r300->fs.size = fs->shader->cb_code_size; 860 861 if (r300->screen->caps.is_r500) { 862 r300->fs_rc_constant_state.size = fs->shader->rc_state_count * 7; 863 r300->fs_constants.size = fs->shader->externals_count * 4 + 3; 864 } else { 865 r300->fs_rc_constant_state.size = fs->shader->rc_state_count * 5; 866 r300->fs_constants.size = fs->shader->externals_count * 4 + 1; 867 } 868} 869 870/* Bind fragment shader state. */ 871static void r300_bind_fs_state(struct pipe_context* pipe, void* shader) 872{ 873 struct r300_context* r300 = r300_context(pipe); 874 struct r300_fragment_shader* fs = (struct r300_fragment_shader*)shader; 875 876 if (fs == NULL) { 877 r300->fs.state = NULL; 878 return; 879 } 880 881 r300->fs.state = fs; 882 r300_pick_fragment_shader(r300); 883 r300_mark_fs_code_dirty(r300); 884 885 r300->rs_block_state.dirty = TRUE; /* Will be updated before the emission. */ 886} 887 888/* Delete fragment shader state. */ 889static void r300_delete_fs_state(struct pipe_context* pipe, void* shader) 890{ 891 struct r300_fragment_shader* fs = (struct r300_fragment_shader*)shader; 892 struct r300_fragment_shader_code *tmp, *ptr = fs->first; 893 894 while (ptr) { 895 tmp = ptr; 896 ptr = ptr->next; 897 rc_constants_destroy(&tmp->code.constants); 898 FREE(tmp->cb_code); 899 FREE(tmp); 900 } 901 FREE((void*)fs->state.tokens); 902 FREE(shader); 903} 904 905static void r300_set_polygon_stipple(struct pipe_context* pipe, 906 const struct pipe_poly_stipple* state) 907{ 908 /* XXX no idea how to set this up, but not terribly important */ 909} 910 911/* Create a new rasterizer state based on the CSO rasterizer state. 912 * 913 * This is a very large chunk of state, and covers most of the graphics 914 * backend (GB), geometry assembly (GA), and setup unit (SU) blocks. 915 * 916 * In a not entirely unironic sidenote, this state has nearly nothing to do 917 * with the actual block on the Radeon called the rasterizer (RS). */ 918static void* r300_create_rs_state(struct pipe_context* pipe, 919 const struct pipe_rasterizer_state* state) 920{ 921 struct r300_rs_state* rs = CALLOC_STRUCT(r300_rs_state); 922 int i; 923 float psiz; 924 uint32_t vap_control_status; /* R300_VAP_CNTL_STATUS: 0x2140 */ 925 uint32_t point_size; /* R300_GA_POINT_SIZE: 0x421c */ 926 uint32_t point_minmax; /* R300_GA_POINT_MINMAX: 0x4230 */ 927 uint32_t line_control; /* R300_GA_LINE_CNTL: 0x4234 */ 928 uint32_t polygon_offset_enable; /* R300_SU_POLY_OFFSET_ENABLE: 0x42b4 */ 929 uint32_t cull_mode; /* R300_SU_CULL_MODE: 0x42b8 */ 930 uint32_t line_stipple_config; /* R300_GA_LINE_STIPPLE_CONFIG: 0x4328 */ 931 uint32_t line_stipple_value; /* R300_GA_LINE_STIPPLE_VALUE: 0x4260 */ 932 uint32_t polygon_mode; /* R300_GA_POLY_MODE: 0x4288 */ 933 uint32_t clip_rule; /* R300_SC_CLIP_RULE: 0x43D0 */ 934 935 /* Specifies top of Raster pipe specific enable controls, 936 * i.e. texture coordinates stuffing for points, lines, triangles */ 937 uint32_t stuffing_enable; /* R300_GB_ENABLE: 0x4008 */ 938 939 /* Point sprites texture coordinates, 0: lower left, 1: upper right */ 940 float point_texcoord_left; /* R300_GA_POINT_S0: 0x4200 */ 941 float point_texcoord_bottom = 0;/* R300_GA_POINT_T0: 0x4204 */ 942 float point_texcoord_right; /* R300_GA_POINT_S1: 0x4208 */ 943 float point_texcoord_top = 0; /* R300_GA_POINT_T1: 0x420c */ 944 CB_LOCALS; 945 946 /* Copy rasterizer state. */ 947 rs->rs = *state; 948 rs->rs_draw = *state; 949 950 /* Override some states for Draw. */ 951 rs->rs_draw.sprite_coord_enable = 0; /* We can do this in HW. */ 952 953#ifdef PIPE_ARCH_LITTLE_ENDIAN 954 vap_control_status = R300_VC_NO_SWAP; 955#else 956 vap_control_status = R300_VC_32BIT_SWAP; 957#endif 958 959 /* If no TCL engine is present, turn off the HW TCL. */ 960 if (!r300_screen(pipe->screen)->caps.has_tcl) { 961 vap_control_status |= R300_VAP_TCL_BYPASS; 962 } 963 964 /* Point size width and height. */ 965 point_size = 966 pack_float_16_6x(state->point_size) | 967 (pack_float_16_6x(state->point_size) << R300_POINTSIZE_X_SHIFT); 968 969 /* Point size clamping. */ 970 if (state->point_size_per_vertex) { 971 /* Per-vertex point size. 972 * Clamp to [0, max FB size] */ 973 psiz = pipe->screen->get_paramf(pipe->screen, 974 PIPE_CAP_MAX_POINT_WIDTH); 975 point_minmax = 976 pack_float_16_6x(psiz) << R300_GA_POINT_MINMAX_MAX_SHIFT; 977 } else { 978 /* We cannot disable the point-size vertex output, 979 * so clamp it. */ 980 psiz = state->point_size; 981 point_minmax = 982 (pack_float_16_6x(psiz) << R300_GA_POINT_MINMAX_MIN_SHIFT) | 983 (pack_float_16_6x(psiz) << R300_GA_POINT_MINMAX_MAX_SHIFT); 984 } 985 986 /* Line control. */ 987 line_control = pack_float_16_6x(state->line_width) | 988 R300_GA_LINE_CNTL_END_TYPE_COMP; 989 990 /* Enable polygon mode */ 991 polygon_mode = 0; 992 if (state->fill_front != PIPE_POLYGON_MODE_FILL || 993 state->fill_back != PIPE_POLYGON_MODE_FILL) { 994 polygon_mode = R300_GA_POLY_MODE_DUAL; 995 } 996 997 /* Front face */ 998 if (state->front_ccw) 999 cull_mode = R300_FRONT_FACE_CCW; 1000 else 1001 cull_mode = R300_FRONT_FACE_CW; 1002 1003 /* Polygon offset */ 1004 polygon_offset_enable = 0; 1005 if (util_get_offset(state, state->fill_front)) { 1006 polygon_offset_enable |= R300_FRONT_ENABLE; 1007 } 1008 if (util_get_offset(state, state->fill_back)) { 1009 polygon_offset_enable |= R300_BACK_ENABLE; 1010 } 1011 1012 rs->polygon_offset_enable = polygon_offset_enable != 0; 1013 1014 /* Polygon mode */ 1015 if (polygon_mode) { 1016 polygon_mode |= 1017 r300_translate_polygon_mode_front(state->fill_front); 1018 polygon_mode |= 1019 r300_translate_polygon_mode_back(state->fill_back); 1020 } 1021 1022 if (state->cull_face & PIPE_FACE_FRONT) { 1023 cull_mode |= R300_CULL_FRONT; 1024 } 1025 if (state->cull_face & PIPE_FACE_BACK) { 1026 cull_mode |= R300_CULL_BACK; 1027 } 1028 1029 if (state->line_stipple_enable) { 1030 line_stipple_config = 1031 R300_GA_LINE_STIPPLE_CONFIG_LINE_RESET_LINE | 1032 (fui((float)state->line_stipple_factor) & 1033 R300_GA_LINE_STIPPLE_CONFIG_STIPPLE_SCALE_MASK); 1034 /* XXX this might need to be scaled up */ 1035 line_stipple_value = state->line_stipple_pattern; 1036 } else { 1037 line_stipple_config = 0; 1038 line_stipple_value = 0; 1039 } 1040 1041 if (state->flatshade) { 1042 rs->color_control = R300_SHADE_MODEL_FLAT; 1043 } else { 1044 rs->color_control = R300_SHADE_MODEL_SMOOTH; 1045 } 1046 1047 clip_rule = state->scissor ? 0xAAAA : 0xFFFF; 1048 1049 /* Point sprites */ 1050 stuffing_enable = 0; 1051 if (state->sprite_coord_enable) { 1052 stuffing_enable = R300_GB_POINT_STUFF_ENABLE; 1053 for (i = 0; i < 8; i++) { 1054 if (state->sprite_coord_enable & (1 << i)) 1055 stuffing_enable |= 1056 R300_GB_TEX_ST << (R300_GB_TEX0_SOURCE_SHIFT + (i*2)); 1057 } 1058 1059 point_texcoord_left = 0.0f; 1060 point_texcoord_right = 1.0f; 1061 1062 switch (state->sprite_coord_mode) { 1063 case PIPE_SPRITE_COORD_UPPER_LEFT: 1064 point_texcoord_top = 0.0f; 1065 point_texcoord_bottom = 1.0f; 1066 break; 1067 case PIPE_SPRITE_COORD_LOWER_LEFT: 1068 point_texcoord_top = 1.0f; 1069 point_texcoord_bottom = 0.0f; 1070 break; 1071 } 1072 } 1073 1074 /* Build the main command buffer. */ 1075 BEGIN_CB(rs->cb_main, 25); 1076 OUT_CB_REG(R300_VAP_CNTL_STATUS, vap_control_status); 1077 OUT_CB_REG(R300_GA_POINT_SIZE, point_size); 1078 OUT_CB_REG_SEQ(R300_GA_POINT_MINMAX, 2); 1079 OUT_CB(point_minmax); 1080 OUT_CB(line_control); 1081 OUT_CB_REG_SEQ(R300_SU_POLY_OFFSET_ENABLE, 2); 1082 OUT_CB(polygon_offset_enable); 1083 rs->cull_mode_index = 9; 1084 OUT_CB(cull_mode); 1085 OUT_CB_REG(R300_GA_LINE_STIPPLE_CONFIG, line_stipple_config); 1086 OUT_CB_REG(R300_GA_LINE_STIPPLE_VALUE, line_stipple_value); 1087 OUT_CB_REG(R300_GA_POLY_MODE, polygon_mode); 1088 OUT_CB_REG(R300_SC_CLIP_RULE, clip_rule); 1089 OUT_CB_REG(R300_GB_ENABLE, stuffing_enable); 1090 OUT_CB_REG_SEQ(R300_GA_POINT_S0, 4); 1091 OUT_CB_32F(point_texcoord_left); 1092 OUT_CB_32F(point_texcoord_bottom); 1093 OUT_CB_32F(point_texcoord_right); 1094 OUT_CB_32F(point_texcoord_top); 1095 END_CB; 1096 1097 /* Build the two command buffers for polygon offset setup. */ 1098 if (polygon_offset_enable) { 1099 float scale = state->offset_scale * 12; 1100 float offset = state->offset_units * 4; 1101 1102 BEGIN_CB(rs->cb_poly_offset_zb16, 5); 1103 OUT_CB_REG_SEQ(R300_SU_POLY_OFFSET_FRONT_SCALE, 4); 1104 OUT_CB_32F(scale); 1105 OUT_CB_32F(offset); 1106 OUT_CB_32F(scale); 1107 OUT_CB_32F(offset); 1108 END_CB; 1109 1110 offset = state->offset_units * 2; 1111 1112 BEGIN_CB(rs->cb_poly_offset_zb24, 5); 1113 OUT_CB_REG_SEQ(R300_SU_POLY_OFFSET_FRONT_SCALE, 4); 1114 OUT_CB_32F(scale); 1115 OUT_CB_32F(offset); 1116 OUT_CB_32F(scale); 1117 OUT_CB_32F(offset); 1118 END_CB; 1119 } 1120 1121 return (void*)rs; 1122} 1123 1124/* Bind rasterizer state. */ 1125static void r300_bind_rs_state(struct pipe_context* pipe, void* state) 1126{ 1127 struct r300_context* r300 = r300_context(pipe); 1128 struct r300_rs_state* rs = (struct r300_rs_state*)state; 1129 int last_sprite_coord_enable = r300->sprite_coord_enable; 1130 boolean last_two_sided_color = r300->two_sided_color; 1131 1132 if (r300->draw && rs) { 1133 draw_set_rasterizer_state(r300->draw, &rs->rs_draw, state); 1134 } 1135 1136 if (rs) { 1137 r300->polygon_offset_enabled = rs->polygon_offset_enable; 1138 r300->sprite_coord_enable = rs->rs.sprite_coord_enable; 1139 r300->two_sided_color = rs->rs.light_twoside; 1140 } else { 1141 r300->polygon_offset_enabled = FALSE; 1142 r300->sprite_coord_enable = 0; 1143 r300->two_sided_color = FALSE; 1144 } 1145 1146 UPDATE_STATE(state, r300->rs_state); 1147 r300->rs_state.size = 25 + (r300->polygon_offset_enabled ? 5 : 0); 1148 1149 if (last_sprite_coord_enable != r300->sprite_coord_enable || 1150 last_two_sided_color != r300->two_sided_color) { 1151 r300->rs_block_state.dirty = TRUE; 1152 } 1153} 1154 1155/* Free rasterizer state. */ 1156static void r300_delete_rs_state(struct pipe_context* pipe, void* state) 1157{ 1158 FREE(state); 1159} 1160 1161static void* 1162 r300_create_sampler_state(struct pipe_context* pipe, 1163 const struct pipe_sampler_state* state) 1164{ 1165 struct r300_context* r300 = r300_context(pipe); 1166 struct r300_sampler_state* sampler = CALLOC_STRUCT(r300_sampler_state); 1167 boolean is_r500 = r300->screen->caps.is_r500; 1168 int lod_bias; 1169 union util_color uc; 1170 1171 sampler->state = *state; 1172 1173 /* r300 doesn't handle CLAMP and MIRROR_CLAMP correctly when either MAG 1174 * or MIN filter is NEAREST. Since texwrap produces same results 1175 * for CLAMP and CLAMP_TO_EDGE, we use them instead. */ 1176 if (sampler->state.min_img_filter == PIPE_TEX_FILTER_NEAREST || 1177 sampler->state.mag_img_filter == PIPE_TEX_FILTER_NEAREST) { 1178 /* Wrap S. */ 1179 if (sampler->state.wrap_s == PIPE_TEX_WRAP_CLAMP) 1180 sampler->state.wrap_s = PIPE_TEX_WRAP_CLAMP_TO_EDGE; 1181 else if (sampler->state.wrap_s == PIPE_TEX_WRAP_MIRROR_CLAMP) 1182 sampler->state.wrap_s = PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE; 1183 1184 /* Wrap T. */ 1185 if (sampler->state.wrap_t == PIPE_TEX_WRAP_CLAMP) 1186 sampler->state.wrap_t = PIPE_TEX_WRAP_CLAMP_TO_EDGE; 1187 else if (sampler->state.wrap_t == PIPE_TEX_WRAP_MIRROR_CLAMP) 1188 sampler->state.wrap_t = PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE; 1189 1190 /* Wrap R. */ 1191 if (sampler->state.wrap_r == PIPE_TEX_WRAP_CLAMP) 1192 sampler->state.wrap_r = PIPE_TEX_WRAP_CLAMP_TO_EDGE; 1193 else if (sampler->state.wrap_r == PIPE_TEX_WRAP_MIRROR_CLAMP) 1194 sampler->state.wrap_r = PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE; 1195 } 1196 1197 sampler->filter0 |= 1198 (r300_translate_wrap(sampler->state.wrap_s) << R300_TX_WRAP_S_SHIFT) | 1199 (r300_translate_wrap(sampler->state.wrap_t) << R300_TX_WRAP_T_SHIFT) | 1200 (r300_translate_wrap(sampler->state.wrap_r) << R300_TX_WRAP_R_SHIFT); 1201 1202 sampler->filter0 |= r300_translate_tex_filters(state->min_img_filter, 1203 state->mag_img_filter, 1204 state->min_mip_filter, 1205 state->max_anisotropy > 0); 1206 1207 sampler->filter0 |= r300_anisotropy(state->max_anisotropy); 1208 1209 /* Unfortunately, r300-r500 don't support floating-point mipmap lods. */ 1210 /* We must pass these to the merge function to clamp them properly. */ 1211 sampler->min_lod = MAX2((unsigned)state->min_lod, 0); 1212 sampler->max_lod = MAX2((unsigned)ceilf(state->max_lod), 0); 1213 1214 lod_bias = CLAMP((int)(state->lod_bias * 32 + 1), -(1 << 9), (1 << 9) - 1); 1215 1216 sampler->filter1 |= (lod_bias << R300_LOD_BIAS_SHIFT) & R300_LOD_BIAS_MASK; 1217 1218 /* This is very high quality anisotropic filtering for R5xx. 1219 * It's good for benchmarking the performance of texturing but 1220 * in practice we don't want to slow down the driver because it's 1221 * a pretty good performance killer. Feel free to play with it. */ 1222 if (DBG_ON(r300, DBG_ANISOHQ) && is_r500) { 1223 sampler->filter1 |= r500_anisotropy(state->max_anisotropy); 1224 } 1225 1226 util_pack_color(state->border_color, PIPE_FORMAT_B8G8R8A8_UNORM, &uc); 1227 sampler->border_color = uc.ui; 1228 1229 /* R500-specific fixups and optimizations */ 1230 if (r300->screen->caps.is_r500) { 1231 sampler->filter1 |= R500_BORDER_FIX; 1232 } 1233 1234 return (void*)sampler; 1235} 1236 1237static void r300_bind_sampler_states(struct pipe_context* pipe, 1238 unsigned count, 1239 void** states) 1240{ 1241 struct r300_context* r300 = r300_context(pipe); 1242 struct r300_textures_state* state = 1243 (struct r300_textures_state*)r300->textures_state.state; 1244 unsigned tex_units = r300->screen->caps.num_tex_units; 1245 1246 if (count > tex_units) { 1247 return; 1248 } 1249 1250 memcpy(state->sampler_states, states, sizeof(void*) * count); 1251 state->sampler_state_count = count; 1252 1253 r300->textures_state.dirty = TRUE; 1254} 1255 1256static void r300_lacks_vertex_textures(struct pipe_context* pipe, 1257 unsigned count, 1258 void** states) 1259{ 1260} 1261 1262static void r300_delete_sampler_state(struct pipe_context* pipe, void* state) 1263{ 1264 FREE(state); 1265} 1266 1267static uint32_t r300_assign_texture_cache_region(unsigned index, unsigned num) 1268{ 1269 /* This looks like a hack, but I believe it's suppose to work like 1270 * that. To illustrate how this works, let's assume you have 5 textures. 1271 * From docs, 5 and the successive numbers are: 1272 * 1273 * FOURTH_1 = 5 1274 * FOURTH_2 = 6 1275 * FOURTH_3 = 7 1276 * EIGHTH_0 = 8 1277 * EIGHTH_1 = 9 1278 * 1279 * First 3 textures will get 3/4 of size of the cache, divived evenly 1280 * between them. The last 1/4 of the cache must be divided between 1281 * the last 2 textures, each will therefore get 1/8 of the cache. 1282 * Why not just to use "5 + texture_index" ? 1283 * 1284 * This simple trick works for all "num" <= 16. 1285 */ 1286 if (num <= 1) 1287 return R300_TX_CACHE(R300_TX_CACHE_WHOLE); 1288 else 1289 return R300_TX_CACHE(num + index); 1290} 1291 1292static void r300_set_fragment_sampler_views(struct pipe_context* pipe, 1293 unsigned count, 1294 struct pipe_sampler_view** views) 1295{ 1296 struct r300_context* r300 = r300_context(pipe); 1297 struct r300_textures_state* state = 1298 (struct r300_textures_state*)r300->textures_state.state; 1299 struct r300_texture *texture; 1300 unsigned i, real_num_views = 0, view_index = 0; 1301 unsigned tex_units = r300->screen->caps.num_tex_units; 1302 boolean dirty_tex = FALSE; 1303 1304 if (count > tex_units) { 1305 return; 1306 } 1307 1308 /* Calculate the real number of views. */ 1309 for (i = 0; i < count; i++) { 1310 if (views[i]) 1311 real_num_views++; 1312 } 1313 1314 for (i = 0; i < count; i++) { 1315 if (&state->sampler_views[i]->base != views[i]) { 1316 pipe_sampler_view_reference( 1317 (struct pipe_sampler_view**)&state->sampler_views[i], 1318 views[i]); 1319 1320 if (!views[i]) { 1321 continue; 1322 } 1323 1324 /* A new sampler view (= texture)... */ 1325 dirty_tex = TRUE; 1326 1327 /* Set the texrect factor in the fragment shader. 1328 * Needed for RECT and NPOT fallback. */ 1329 texture = r300_texture(views[i]->texture); 1330 if (texture->desc.is_npot) { 1331 r300->fs_rc_constant_state.dirty = TRUE; 1332 } 1333 1334 state->sampler_views[i]->texcache_region = 1335 r300_assign_texture_cache_region(view_index, real_num_views); 1336 view_index++; 1337 } 1338 } 1339 1340 for (i = count; i < tex_units; i++) { 1341 if (state->sampler_views[i]) { 1342 pipe_sampler_view_reference( 1343 (struct pipe_sampler_view**)&state->sampler_views[i], 1344 NULL); 1345 } 1346 } 1347 1348 state->sampler_view_count = count; 1349 1350 r300->textures_state.dirty = TRUE; 1351 1352 if (dirty_tex) { 1353 r300->texture_cache_inval.dirty = TRUE; 1354 } 1355} 1356 1357static struct pipe_sampler_view * 1358r300_create_sampler_view(struct pipe_context *pipe, 1359 struct pipe_resource *texture, 1360 const struct pipe_sampler_view *templ) 1361{ 1362 struct r300_sampler_view *view = CALLOC_STRUCT(r300_sampler_view); 1363 struct r300_texture *tex = r300_texture(texture); 1364 boolean is_r500 = r300_screen(pipe->screen)->caps.is_r500; 1365 1366 if (view) { 1367 view->base = *templ; 1368 view->base.reference.count = 1; 1369 view->base.context = pipe; 1370 view->base.texture = NULL; 1371 pipe_resource_reference(&view->base.texture, texture); 1372 1373 view->swizzle[0] = templ->swizzle_r; 1374 view->swizzle[1] = templ->swizzle_g; 1375 view->swizzle[2] = templ->swizzle_b; 1376 view->swizzle[3] = templ->swizzle_a; 1377 1378 view->format = tex->tx_format; 1379 view->format.format1 |= r300_translate_texformat(templ->format, 1380 view->swizzle, 1381 is_r500); 1382 if (is_r500) { 1383 view->format.format2 |= r500_tx_format_msb_bit(templ->format); 1384 } 1385 } 1386 1387 return (struct pipe_sampler_view*)view; 1388} 1389 1390static void 1391r300_sampler_view_destroy(struct pipe_context *pipe, 1392 struct pipe_sampler_view *view) 1393{ 1394 pipe_resource_reference(&view->texture, NULL); 1395 FREE(view); 1396} 1397 1398static void r300_set_scissor_state(struct pipe_context* pipe, 1399 const struct pipe_scissor_state* state) 1400{ 1401 struct r300_context* r300 = r300_context(pipe); 1402 1403 memcpy(r300->scissor_state.state, state, 1404 sizeof(struct pipe_scissor_state)); 1405 1406 r300->scissor_state.dirty = TRUE; 1407} 1408 1409static void r300_set_viewport_state(struct pipe_context* pipe, 1410 const struct pipe_viewport_state* state) 1411{ 1412 struct r300_context* r300 = r300_context(pipe); 1413 struct r300_viewport_state* viewport = 1414 (struct r300_viewport_state*)r300->viewport_state.state; 1415 1416 r300->viewport = *state; 1417 1418 if (r300->draw) { 1419 draw_set_viewport_state(r300->draw, state); 1420 viewport->vte_control = R300_VTX_XY_FMT | R300_VTX_Z_FMT; 1421 return; 1422 } 1423 1424 /* Do the transform in HW. */ 1425 viewport->vte_control = R300_VTX_W0_FMT; 1426 1427 if (state->scale[0] != 1.0f) { 1428 viewport->xscale = state->scale[0]; 1429 viewport->vte_control |= R300_VPORT_X_SCALE_ENA; 1430 } 1431 if (state->scale[1] != 1.0f) { 1432 viewport->yscale = state->scale[1]; 1433 viewport->vte_control |= R300_VPORT_Y_SCALE_ENA; 1434 } 1435 if (state->scale[2] != 1.0f) { 1436 viewport->zscale = state->scale[2]; 1437 viewport->vte_control |= R300_VPORT_Z_SCALE_ENA; 1438 } 1439 if (state->translate[0] != 0.0f) { 1440 viewport->xoffset = state->translate[0]; 1441 viewport->vte_control |= R300_VPORT_X_OFFSET_ENA; 1442 } 1443 if (state->translate[1] != 0.0f) { 1444 viewport->yoffset = state->translate[1]; 1445 viewport->vte_control |= R300_VPORT_Y_OFFSET_ENA; 1446 } 1447 if (state->translate[2] != 0.0f) { 1448 viewport->zoffset = state->translate[2]; 1449 viewport->vte_control |= R300_VPORT_Z_OFFSET_ENA; 1450 } 1451 1452 r300->viewport_state.dirty = TRUE; 1453 if (r300->fs.state && r300_fs(r300)->shader->inputs.wpos != ATTR_UNUSED) { 1454 r300->fs_rc_constant_state.dirty = TRUE; 1455 } 1456} 1457 1458static void r300_set_vertex_buffers(struct pipe_context* pipe, 1459 unsigned count, 1460 const struct pipe_vertex_buffer* buffers) 1461{ 1462 struct r300_context* r300 = r300_context(pipe); 1463 struct pipe_vertex_buffer *vbo; 1464 unsigned i, max_index = (1 << 24) - 1; 1465 boolean any_user_buffer = FALSE; 1466 1467 if (count == r300->vertex_buffer_count && 1468 memcmp(r300->vertex_buffer, buffers, 1469 sizeof(struct pipe_vertex_buffer) * count) == 0) { 1470 return; 1471 } 1472 1473 if (r300->screen->caps.has_tcl) { 1474 /* HW TCL. */ 1475 r300->incompatible_vb_layout = FALSE; 1476 1477 /* Check if the strides and offsets are aligned to the size of DWORD. */ 1478 for (i = 0; i < count; i++) { 1479 if (buffers[i].buffer) { 1480 if (buffers[i].stride % 4 != 0 || 1481 buffers[i].buffer_offset % 4 != 0) { 1482 r300->incompatible_vb_layout = TRUE; 1483 break; 1484 } 1485 } 1486 } 1487 1488 for (i = 0; i < count; i++) { 1489 /* Why, yes, I AM casting away constness. How did you know? */ 1490 vbo = (struct pipe_vertex_buffer*)&buffers[i]; 1491 1492 /* Skip NULL buffers */ 1493 if (!buffers[i].buffer) { 1494 continue; 1495 } 1496 1497 if (r300_buffer_is_user_buffer(vbo->buffer)) { 1498 any_user_buffer = TRUE; 1499 } 1500 1501 if (vbo->max_index == ~0) { 1502 /* if no VBO stride then only one vertex value so max index is 1 */ 1503 /* should think about converting to VS constants like svga does */ 1504 if (!vbo->stride) 1505 vbo->max_index = 1; 1506 else 1507 vbo->max_index = 1508 (vbo->buffer->width0 - vbo->buffer_offset) / vbo->stride; 1509 } 1510 1511 max_index = MIN2(vbo->max_index, max_index); 1512 } 1513 1514 r300->any_user_vbs = any_user_buffer; 1515 r300->vertex_buffer_max_index = max_index; 1516 1517 } else { 1518 /* SW TCL. */ 1519 draw_set_vertex_buffers(r300->draw, count, buffers); 1520 } 1521 1522 /* Common code. */ 1523 for (i = 0; i < count; i++) { 1524 /* Reference our buffer. */ 1525 pipe_resource_reference(&r300->vertex_buffer[i].buffer, buffers[i].buffer); 1526 } 1527 for (; i < r300->vertex_buffer_count; i++) { 1528 /* Dereference any old buffers. */ 1529 pipe_resource_reference(&r300->vertex_buffer[i].buffer, NULL); 1530 } 1531 1532 memcpy(r300->vertex_buffer, buffers, 1533 sizeof(struct pipe_vertex_buffer) * count); 1534 r300->vertex_buffer_count = count; 1535} 1536 1537static void r300_set_index_buffer(struct pipe_context* pipe, 1538 const struct pipe_index_buffer *ib) 1539{ 1540 struct r300_context* r300 = r300_context(pipe); 1541 1542 if (ib) { 1543 pipe_resource_reference(&r300->index_buffer.buffer, ib->buffer); 1544 memcpy(&r300->index_buffer, ib, sizeof(r300->index_buffer)); 1545 } 1546 else { 1547 pipe_resource_reference(&r300->index_buffer.buffer, NULL); 1548 memset(&r300->index_buffer, 0, sizeof(r300->index_buffer)); 1549 } 1550 1551 /* TODO make this more like a state */ 1552} 1553 1554/* Initialize the PSC tables. */ 1555static void r300_vertex_psc(struct r300_vertex_element_state *velems) 1556{ 1557 struct r300_vertex_stream_state *vstream = &velems->vertex_stream; 1558 uint16_t type, swizzle; 1559 enum pipe_format format; 1560 unsigned i; 1561 1562 if (velems->count > 16) { 1563 fprintf(stderr, "r300: More than 16 vertex elements are not supported," 1564 " requested %i, using 16.\n", velems->count); 1565 velems->count = 16; 1566 } 1567 1568 /* Vertex shaders have no semantics on their inputs, 1569 * so PSC should just route stuff based on the vertex elements, 1570 * and not on attrib information. */ 1571 for (i = 0; i < velems->count; i++) { 1572 format = velems->hw_format[i]; 1573 1574 type = r300_translate_vertex_data_type(format); 1575 if (type == R300_INVALID_FORMAT) { 1576 fprintf(stderr, "r300: Bad vertex format %s.\n", 1577 util_format_short_name(format)); 1578 assert(0); 1579 abort(); 1580 } 1581 1582 type |= i << R300_DST_VEC_LOC_SHIFT; 1583 swizzle = r300_translate_vertex_data_swizzle(format); 1584 1585 if (i & 1) { 1586 vstream->vap_prog_stream_cntl[i >> 1] |= type << 16; 1587 vstream->vap_prog_stream_cntl_ext[i >> 1] |= swizzle << 16; 1588 } else { 1589 vstream->vap_prog_stream_cntl[i >> 1] |= type; 1590 vstream->vap_prog_stream_cntl_ext[i >> 1] |= swizzle; 1591 } 1592 } 1593 1594 /* Set the last vector in the PSC. */ 1595 if (i) { 1596 i -= 1; 1597 } 1598 vstream->vap_prog_stream_cntl[i >> 1] |= 1599 (R300_LAST_VEC << (i & 1 ? 16 : 0)); 1600 1601 vstream->count = (i >> 1) + 1; 1602} 1603 1604#define FORMAT_REPLACE(what, withwhat) \ 1605 case PIPE_FORMAT_##what: *format = PIPE_FORMAT_##withwhat; break 1606 1607static void* r300_create_vertex_elements_state(struct pipe_context* pipe, 1608 unsigned count, 1609 const struct pipe_vertex_element* attribs) 1610{ 1611 struct r300_vertex_element_state *velems; 1612 unsigned i; 1613 enum pipe_format *format; 1614 1615 assert(count <= PIPE_MAX_ATTRIBS); 1616 velems = CALLOC_STRUCT(r300_vertex_element_state); 1617 if (velems != NULL) { 1618 velems->count = count; 1619 memcpy(velems->velem, attribs, sizeof(struct pipe_vertex_element) * count); 1620 1621 if (r300_screen(pipe->screen)->caps.has_tcl) { 1622 /* Set the best hw format in case the original format is not 1623 * supported by hw. */ 1624 for (i = 0; i < count; i++) { 1625 velems->hw_format[i] = velems->velem[i].src_format; 1626 format = &velems->hw_format[i]; 1627 1628 /* This is basically the list of unsupported formats. 1629 * For now we don't care about the alignment, that's going to 1630 * be sorted out after the PSC setup. */ 1631 switch (*format) { 1632 FORMAT_REPLACE(R64_FLOAT, R32_FLOAT); 1633 FORMAT_REPLACE(R64G64_FLOAT, R32G32_FLOAT); 1634 FORMAT_REPLACE(R64G64B64_FLOAT, R32G32B32_FLOAT); 1635 FORMAT_REPLACE(R64G64B64A64_FLOAT, R32G32B32A32_FLOAT); 1636 1637 FORMAT_REPLACE(R32_UNORM, R32_FLOAT); 1638 FORMAT_REPLACE(R32G32_UNORM, R32G32_FLOAT); 1639 FORMAT_REPLACE(R32G32B32_UNORM, R32G32B32_FLOAT); 1640 FORMAT_REPLACE(R32G32B32A32_UNORM, R32G32B32A32_FLOAT); 1641 1642 FORMAT_REPLACE(R32_USCALED, R32_FLOAT); 1643 FORMAT_REPLACE(R32G32_USCALED, R32G32_FLOAT); 1644 FORMAT_REPLACE(R32G32B32_USCALED, R32G32B32_FLOAT); 1645 FORMAT_REPLACE(R32G32B32A32_USCALED,R32G32B32A32_FLOAT); 1646 1647 FORMAT_REPLACE(R32_SNORM, R32_FLOAT); 1648 FORMAT_REPLACE(R32G32_SNORM, R32G32_FLOAT); 1649 FORMAT_REPLACE(R32G32B32_SNORM, R32G32B32_FLOAT); 1650 FORMAT_REPLACE(R32G32B32A32_SNORM, R32G32B32A32_FLOAT); 1651 1652 FORMAT_REPLACE(R32_SSCALED, R32_FLOAT); 1653 FORMAT_REPLACE(R32G32_SSCALED, R32G32_FLOAT); 1654 FORMAT_REPLACE(R32G32B32_SSCALED, R32G32B32_FLOAT); 1655 FORMAT_REPLACE(R32G32B32A32_SSCALED,R32G32B32A32_FLOAT); 1656 1657 FORMAT_REPLACE(R32_FIXED, R32_FLOAT); 1658 FORMAT_REPLACE(R32G32_FIXED, R32G32_FLOAT); 1659 FORMAT_REPLACE(R32G32B32_FIXED, R32G32B32_FLOAT); 1660 FORMAT_REPLACE(R32G32B32A32_FIXED, R32G32B32A32_FLOAT); 1661 1662 default:; 1663 } 1664 1665 velems->incompatible_layout = 1666 velems->incompatible_layout || 1667 velems->velem[i].src_format != velems->hw_format[i] || 1668 velems->velem[i].src_offset % 4 != 0; 1669 } 1670 1671 /* Now setup PSC. 1672 * The unused components will be replaced by (..., 0, 1). */ 1673 r300_vertex_psc(velems); 1674 1675 /* Align the formats to the size of DWORD. 1676 * We only care about the blocksizes of the formats since 1677 * swizzles are already set up. 1678 * Also compute the vertex size. */ 1679 for (i = 0; i < count; i++) { 1680 /* This is OK because we check for aligned strides too. */ 1681 velems->hw_format_size[i] = 1682 align(util_format_get_blocksize(velems->hw_format[i]), 4); 1683 velems->vertex_size_dwords += velems->hw_format_size[i] / 4; 1684 } 1685 } 1686 } 1687 return velems; 1688} 1689 1690static void r300_bind_vertex_elements_state(struct pipe_context *pipe, 1691 void *state) 1692{ 1693 struct r300_context *r300 = r300_context(pipe); 1694 struct r300_vertex_element_state *velems = state; 1695 1696 if (velems == NULL) { 1697 return; 1698 } 1699 1700 r300->velems = velems; 1701 1702 if (r300->draw) { 1703 draw_set_vertex_elements(r300->draw, velems->count, velems->velem); 1704 return; 1705 } 1706 1707 UPDATE_STATE(&velems->vertex_stream, r300->vertex_stream_state); 1708 r300->vertex_stream_state.size = (1 + velems->vertex_stream.count) * 2; 1709} 1710 1711static void r300_delete_vertex_elements_state(struct pipe_context *pipe, void *state) 1712{ 1713 FREE(state); 1714} 1715 1716static void* r300_create_vs_state(struct pipe_context* pipe, 1717 const struct pipe_shader_state* shader) 1718{ 1719 struct r300_context* r300 = r300_context(pipe); 1720 struct r300_vertex_shader* vs = CALLOC_STRUCT(r300_vertex_shader); 1721 1722 /* Copy state directly into shader. */ 1723 vs->state = *shader; 1724 vs->state.tokens = tgsi_dup_tokens(shader->tokens); 1725 1726 if (r300->screen->caps.has_tcl) { 1727 r300_init_vs_outputs(vs); 1728 r300_translate_vertex_shader(r300, vs); 1729 } else { 1730 r300_draw_init_vertex_shader(r300->draw, vs); 1731 } 1732 1733 return vs; 1734} 1735 1736static void r300_bind_vs_state(struct pipe_context* pipe, void* shader) 1737{ 1738 struct r300_context* r300 = r300_context(pipe); 1739 struct r300_vertex_shader* vs = (struct r300_vertex_shader*)shader; 1740 1741 if (vs == NULL) { 1742 r300->vs_state.state = NULL; 1743 return; 1744 } 1745 if (vs == r300->vs_state.state) { 1746 return; 1747 } 1748 r300->vs_state.state = vs; 1749 1750 /* The majority of the RS block bits is dependent on the vertex shader. */ 1751 r300->rs_block_state.dirty = TRUE; /* Will be updated before the emission. */ 1752 1753 if (r300->screen->caps.has_tcl) { 1754 unsigned fc_op_dwords = r300->screen->caps.is_r500 ? 3 : 2; 1755 r300->vs_state.dirty = TRUE; 1756 r300->vs_state.size = 1757 vs->code.length + 9 + 1758 (vs->immediates_count ? vs->immediates_count * 4 + 3 : 0) + 1759 (vs->code.num_fc_ops ? vs->code.num_fc_ops * fc_op_dwords + 4 : 0); 1760 1761 if (vs->externals_count) { 1762 r300->vs_constants.dirty = TRUE; 1763 r300->vs_constants.size = vs->externals_count * 4 + 3; 1764 } else { 1765 r300->vs_constants.size = 0; 1766 } 1767 1768 r300->pvs_flush.dirty = TRUE; 1769 } else { 1770 draw_bind_vertex_shader(r300->draw, 1771 (struct draw_vertex_shader*)vs->draw_vs); 1772 } 1773} 1774 1775static void r300_delete_vs_state(struct pipe_context* pipe, void* shader) 1776{ 1777 struct r300_context* r300 = r300_context(pipe); 1778 struct r300_vertex_shader* vs = (struct r300_vertex_shader*)shader; 1779 1780 if (r300->screen->caps.has_tcl) { 1781 rc_constants_destroy(&vs->code.constants); 1782 } else { 1783 draw_delete_vertex_shader(r300->draw, 1784 (struct draw_vertex_shader*)vs->draw_vs); 1785 } 1786 1787 FREE((void*)vs->state.tokens); 1788 FREE(shader); 1789} 1790 1791static void r300_set_constant_buffer(struct pipe_context *pipe, 1792 uint shader, uint index, 1793 struct pipe_resource *buf) 1794{ 1795 struct r300_context* r300 = r300_context(pipe); 1796 struct r300_constant_buffer *cbuf; 1797 uint32_t *mapped = r300_buffer(buf)->user_buffer; 1798 int max_size = 0, max_size_bytes = 0, clamped_size = 0; 1799 1800 switch (shader) { 1801 case PIPE_SHADER_VERTEX: 1802 cbuf = (struct r300_constant_buffer*)r300->vs_constants.state; 1803 max_size = 256; 1804 break; 1805 case PIPE_SHADER_FRAGMENT: 1806 cbuf = (struct r300_constant_buffer*)r300->fs_constants.state; 1807 if (r300->screen->caps.is_r500) { 1808 max_size = 256; 1809 } else { 1810 max_size = 32; 1811 } 1812 break; 1813 default: 1814 assert(0); 1815 return; 1816 } 1817 max_size_bytes = max_size * 4 * sizeof(float); 1818 1819 if (buf == NULL || buf->width0 == 0 || 1820 (mapped = r300_buffer(buf)->constant_buffer) == NULL) { 1821 cbuf->count = 0; 1822 return; 1823 } 1824 1825 if (shader == PIPE_SHADER_FRAGMENT || 1826 (shader == PIPE_SHADER_VERTEX && r300->screen->caps.has_tcl)) { 1827 assert((buf->width0 % (4 * sizeof(float))) == 0); 1828 1829 /* Check the size of the constant buffer. */ 1830 /* XXX Subtract immediates and RC_STATE_* variables. */ 1831 if (buf->width0 > max_size_bytes) { 1832 fprintf(stderr, "r300: Max size of the constant buffer is " 1833 "%i*4 floats.\n", max_size); 1834 } 1835 1836 clamped_size = MIN2(buf->width0, max_size_bytes); 1837 cbuf->count = clamped_size / (4 * sizeof(float)); 1838 cbuf->ptr = mapped; 1839 } 1840 1841 if (shader == PIPE_SHADER_VERTEX) { 1842 if (r300->screen->caps.has_tcl) { 1843 if (r300->vs_constants.size) { 1844 r300->vs_constants.dirty = TRUE; 1845 } 1846 r300->pvs_flush.dirty = TRUE; 1847 } else if (r300->draw) { 1848 draw_set_mapped_constant_buffer(r300->draw, PIPE_SHADER_VERTEX, 1849 0, mapped, buf->width0); 1850 } 1851 } else if (shader == PIPE_SHADER_FRAGMENT) { 1852 r300->fs_constants.dirty = TRUE; 1853 } 1854} 1855 1856void r300_init_state_functions(struct r300_context* r300) 1857{ 1858 r300->context.create_blend_state = r300_create_blend_state; 1859 r300->context.bind_blend_state = r300_bind_blend_state; 1860 r300->context.delete_blend_state = r300_delete_blend_state; 1861 1862 r300->context.set_blend_color = r300_set_blend_color; 1863 1864 r300->context.set_clip_state = r300_set_clip_state; 1865 r300->context.set_sample_mask = r300_set_sample_mask; 1866 1867 r300->context.set_constant_buffer = r300_set_constant_buffer; 1868 1869 r300->context.create_depth_stencil_alpha_state = r300_create_dsa_state; 1870 r300->context.bind_depth_stencil_alpha_state = r300_bind_dsa_state; 1871 r300->context.delete_depth_stencil_alpha_state = r300_delete_dsa_state; 1872 1873 r300->context.set_stencil_ref = r300_set_stencil_ref; 1874 1875 r300->context.set_framebuffer_state = r300_set_framebuffer_state; 1876 1877 r300->context.create_fs_state = r300_create_fs_state; 1878 r300->context.bind_fs_state = r300_bind_fs_state; 1879 r300->context.delete_fs_state = r300_delete_fs_state; 1880 1881 r300->context.set_polygon_stipple = r300_set_polygon_stipple; 1882 1883 r300->context.create_rasterizer_state = r300_create_rs_state; 1884 r300->context.bind_rasterizer_state = r300_bind_rs_state; 1885 r300->context.delete_rasterizer_state = r300_delete_rs_state; 1886 1887 r300->context.create_sampler_state = r300_create_sampler_state; 1888 r300->context.bind_fragment_sampler_states = r300_bind_sampler_states; 1889 r300->context.bind_vertex_sampler_states = r300_lacks_vertex_textures; 1890 r300->context.delete_sampler_state = r300_delete_sampler_state; 1891 1892 r300->context.set_fragment_sampler_views = r300_set_fragment_sampler_views; 1893 r300->context.create_sampler_view = r300_create_sampler_view; 1894 r300->context.sampler_view_destroy = r300_sampler_view_destroy; 1895 1896 r300->context.set_scissor_state = r300_set_scissor_state; 1897 1898 r300->context.set_viewport_state = r300_set_viewport_state; 1899 1900 r300->context.set_vertex_buffers = r300_set_vertex_buffers; 1901 r300->context.set_index_buffer = r300_set_index_buffer; 1902 1903 r300->context.create_vertex_elements_state = r300_create_vertex_elements_state; 1904 r300->context.bind_vertex_elements_state = r300_bind_vertex_elements_state; 1905 r300->context.delete_vertex_elements_state = r300_delete_vertex_elements_state; 1906 1907 r300->context.create_vs_state = r300_create_vs_state; 1908 r300->context.bind_vs_state = r300_bind_vs_state; 1909 r300->context.delete_vs_state = r300_delete_vs_state; 1910} 1911