r300_state.c revision 3eb557778376bcbbc6f25da88ffbaa269607254c
1/* 2 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com> 3 * Copyright 2009 Marek Olšák <maraeo@gmail.com> 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * on the rights to use, copy, modify, merge, publish, distribute, sub 9 * license, and/or sell copies of the Software, and to permit persons to whom 10 * the Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, 20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 22 * USE OR OTHER DEALINGS IN THE SOFTWARE. */ 23 24#include "draw/draw_context.h" 25 26#include "util/u_blitter.h" 27#include "util/u_math.h" 28#include "util/u_memory.h" 29#include "util/u_pack_color.h" 30 31#include "tgsi/tgsi_parse.h" 32 33#include "pipe/p_config.h" 34 35#include "r300_cb.h" 36#include "r300_context.h" 37#include "r300_emit.h" 38#include "r300_reg.h" 39#include "r300_screen.h" 40#include "r300_screen_buffer.h" 41#include "r300_state_inlines.h" 42#include "r300_fs.h" 43#include "r300_texture.h" 44#include "r300_vs.h" 45#include "r300_winsys.h" 46 47/* r300_state: Functions used to intialize state context by translating 48 * Gallium state objects into semi-native r300 state objects. */ 49 50#define UPDATE_STATE(cso, atom) \ 51 if (cso != atom.state) { \ 52 atom.state = cso; \ 53 atom.dirty = TRUE; \ 54 } 55 56static boolean blend_discard_if_src_alpha_0(unsigned srcRGB, unsigned srcA, 57 unsigned dstRGB, unsigned dstA) 58{ 59 /* If the blend equation is ADD or REVERSE_SUBTRACT, 60 * SRC_ALPHA == 0, and the following state is set, the colorbuffer 61 * will not be changed. 62 * Notice that the dst factors are the src factors inverted. */ 63 return (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA || 64 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE || 65 srcRGB == PIPE_BLENDFACTOR_ZERO) && 66 (srcA == PIPE_BLENDFACTOR_SRC_COLOR || 67 srcA == PIPE_BLENDFACTOR_SRC_ALPHA || 68 srcA == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE || 69 srcA == PIPE_BLENDFACTOR_ZERO) && 70 (dstRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA || 71 dstRGB == PIPE_BLENDFACTOR_ONE) && 72 (dstA == PIPE_BLENDFACTOR_INV_SRC_COLOR || 73 dstA == PIPE_BLENDFACTOR_INV_SRC_ALPHA || 74 dstA == PIPE_BLENDFACTOR_ONE); 75} 76 77static boolean blend_discard_if_src_alpha_1(unsigned srcRGB, unsigned srcA, 78 unsigned dstRGB, unsigned dstA) 79{ 80 /* If the blend equation is ADD or REVERSE_SUBTRACT, 81 * SRC_ALPHA == 1, and the following state is set, the colorbuffer 82 * will not be changed. 83 * Notice that the dst factors are the src factors inverted. */ 84 return (srcRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA || 85 srcRGB == PIPE_BLENDFACTOR_ZERO) && 86 (srcA == PIPE_BLENDFACTOR_INV_SRC_COLOR || 87 srcA == PIPE_BLENDFACTOR_INV_SRC_ALPHA || 88 srcA == PIPE_BLENDFACTOR_ZERO) && 89 (dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA || 90 dstRGB == PIPE_BLENDFACTOR_ONE) && 91 (dstA == PIPE_BLENDFACTOR_SRC_COLOR || 92 dstA == PIPE_BLENDFACTOR_SRC_ALPHA || 93 dstA == PIPE_BLENDFACTOR_ONE); 94} 95 96static boolean blend_discard_if_src_color_0(unsigned srcRGB, unsigned srcA, 97 unsigned dstRGB, unsigned dstA) 98{ 99 /* If the blend equation is ADD or REVERSE_SUBTRACT, 100 * SRC_COLOR == (0,0,0), and the following state is set, the colorbuffer 101 * will not be changed. 102 * Notice that the dst factors are the src factors inverted. */ 103 return (srcRGB == PIPE_BLENDFACTOR_SRC_COLOR || 104 srcRGB == PIPE_BLENDFACTOR_ZERO) && 105 (srcA == PIPE_BLENDFACTOR_ZERO) && 106 (dstRGB == PIPE_BLENDFACTOR_INV_SRC_COLOR || 107 dstRGB == PIPE_BLENDFACTOR_ONE) && 108 (dstA == PIPE_BLENDFACTOR_ONE); 109} 110 111static boolean blend_discard_if_src_color_1(unsigned srcRGB, unsigned srcA, 112 unsigned dstRGB, unsigned dstA) 113{ 114 /* If the blend equation is ADD or REVERSE_SUBTRACT, 115 * SRC_COLOR == (1,1,1), and the following state is set, the colorbuffer 116 * will not be changed. 117 * Notice that the dst factors are the src factors inverted. */ 118 return (srcRGB == PIPE_BLENDFACTOR_INV_SRC_COLOR || 119 srcRGB == PIPE_BLENDFACTOR_ZERO) && 120 (srcA == PIPE_BLENDFACTOR_ZERO) && 121 (dstRGB == PIPE_BLENDFACTOR_SRC_COLOR || 122 dstRGB == PIPE_BLENDFACTOR_ONE) && 123 (dstA == PIPE_BLENDFACTOR_ONE); 124} 125 126static boolean blend_discard_if_src_alpha_color_0(unsigned srcRGB, unsigned srcA, 127 unsigned dstRGB, unsigned dstA) 128{ 129 /* If the blend equation is ADD or REVERSE_SUBTRACT, 130 * SRC_ALPHA_COLOR == (0,0,0,0), and the following state is set, 131 * the colorbuffer will not be changed. 132 * Notice that the dst factors are the src factors inverted. */ 133 return (srcRGB == PIPE_BLENDFACTOR_SRC_COLOR || 134 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA || 135 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE || 136 srcRGB == PIPE_BLENDFACTOR_ZERO) && 137 (srcA == PIPE_BLENDFACTOR_SRC_COLOR || 138 srcA == PIPE_BLENDFACTOR_SRC_ALPHA || 139 srcA == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE || 140 srcA == PIPE_BLENDFACTOR_ZERO) && 141 (dstRGB == PIPE_BLENDFACTOR_INV_SRC_COLOR || 142 dstRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA || 143 dstRGB == PIPE_BLENDFACTOR_ONE) && 144 (dstA == PIPE_BLENDFACTOR_INV_SRC_COLOR || 145 dstA == PIPE_BLENDFACTOR_INV_SRC_ALPHA || 146 dstA == PIPE_BLENDFACTOR_ONE); 147} 148 149static boolean blend_discard_if_src_alpha_color_1(unsigned srcRGB, unsigned srcA, 150 unsigned dstRGB, unsigned dstA) 151{ 152 /* If the blend equation is ADD or REVERSE_SUBTRACT, 153 * SRC_ALPHA_COLOR == (1,1,1,1), and the following state is set, 154 * the colorbuffer will not be changed. 155 * Notice that the dst factors are the src factors inverted. */ 156 return (srcRGB == PIPE_BLENDFACTOR_INV_SRC_COLOR || 157 srcRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA || 158 srcRGB == PIPE_BLENDFACTOR_ZERO) && 159 (srcA == PIPE_BLENDFACTOR_INV_SRC_COLOR || 160 srcA == PIPE_BLENDFACTOR_INV_SRC_ALPHA || 161 srcA == PIPE_BLENDFACTOR_ZERO) && 162 (dstRGB == PIPE_BLENDFACTOR_SRC_COLOR || 163 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA || 164 dstRGB == PIPE_BLENDFACTOR_ONE) && 165 (dstA == PIPE_BLENDFACTOR_SRC_COLOR || 166 dstA == PIPE_BLENDFACTOR_SRC_ALPHA || 167 dstA == PIPE_BLENDFACTOR_ONE); 168} 169 170static unsigned bgra_cmask(unsigned mask) 171{ 172 /* Gallium uses RGBA color ordering while R300 expects BGRA. */ 173 174 return ((mask & PIPE_MASK_R) << 2) | 175 ((mask & PIPE_MASK_B) >> 2) | 176 (mask & (PIPE_MASK_G | PIPE_MASK_A)); 177} 178 179/* Create a new blend state based on the CSO blend state. 180 * 181 * This encompasses alpha blending, logic/raster ops, and blend dithering. */ 182static void* r300_create_blend_state(struct pipe_context* pipe, 183 const struct pipe_blend_state* state) 184{ 185 struct r300_screen* r300screen = r300_screen(pipe->screen); 186 struct r300_blend_state* blend = CALLOC_STRUCT(r300_blend_state); 187 uint32_t blend_control = 0; /* R300_RB3D_CBLEND: 0x4e04 */ 188 uint32_t alpha_blend_control = 0; /* R300_RB3D_ABLEND: 0x4e08 */ 189 uint32_t color_channel_mask = 0; /* R300_RB3D_COLOR_CHANNEL_MASK: 0x4e0c */ 190 uint32_t rop = 0; /* R300_RB3D_ROPCNTL: 0x4e18 */ 191 uint32_t dither = 0; /* R300_RB3D_DITHER_CTL: 0x4e50 */ 192 CB_LOCALS; 193 194 if (state->rt[0].blend_enable) 195 { 196 unsigned eqRGB = state->rt[0].rgb_func; 197 unsigned srcRGB = state->rt[0].rgb_src_factor; 198 unsigned dstRGB = state->rt[0].rgb_dst_factor; 199 200 unsigned eqA = state->rt[0].alpha_func; 201 unsigned srcA = state->rt[0].alpha_src_factor; 202 unsigned dstA = state->rt[0].alpha_dst_factor; 203 204 /* despite the name, ALPHA_BLEND_ENABLE has nothing to do with alpha, 205 * this is just the crappy D3D naming */ 206 blend_control = R300_ALPHA_BLEND_ENABLE | 207 r300_translate_blend_function(eqRGB) | 208 ( r300_translate_blend_factor(srcRGB) << R300_SRC_BLEND_SHIFT) | 209 ( r300_translate_blend_factor(dstRGB) << R300_DST_BLEND_SHIFT); 210 211 /* Optimization: some operations do not require the destination color. 212 * 213 * When SRC_ALPHA_SATURATE is used, colorbuffer reads must be enabled, 214 * otherwise blending gives incorrect results. It seems to be 215 * a hardware bug. */ 216 if (eqRGB == PIPE_BLEND_MIN || eqA == PIPE_BLEND_MIN || 217 eqRGB == PIPE_BLEND_MAX || eqA == PIPE_BLEND_MAX || 218 dstRGB != PIPE_BLENDFACTOR_ZERO || 219 dstA != PIPE_BLENDFACTOR_ZERO || 220 srcRGB == PIPE_BLENDFACTOR_DST_COLOR || 221 srcRGB == PIPE_BLENDFACTOR_DST_ALPHA || 222 srcRGB == PIPE_BLENDFACTOR_INV_DST_COLOR || 223 srcRGB == PIPE_BLENDFACTOR_INV_DST_ALPHA || 224 srcA == PIPE_BLENDFACTOR_DST_COLOR || 225 srcA == PIPE_BLENDFACTOR_DST_ALPHA || 226 srcA == PIPE_BLENDFACTOR_INV_DST_COLOR || 227 srcA == PIPE_BLENDFACTOR_INV_DST_ALPHA || 228 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE) { 229 /* Enable reading from the colorbuffer. */ 230 blend_control |= R300_READ_ENABLE; 231 232 if (r300screen->caps.is_r500) { 233 /* Optimization: Depending on incoming pixels, we can 234 * conditionally disable the reading in hardware... */ 235 if (eqRGB != PIPE_BLEND_MIN && eqA != PIPE_BLEND_MIN && 236 eqRGB != PIPE_BLEND_MAX && eqA != PIPE_BLEND_MAX) { 237 /* Disable reading if SRC_ALPHA == 0. */ 238 if ((dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA || 239 dstRGB == PIPE_BLENDFACTOR_ZERO) && 240 (dstA == PIPE_BLENDFACTOR_SRC_COLOR || 241 dstA == PIPE_BLENDFACTOR_SRC_ALPHA || 242 dstA == PIPE_BLENDFACTOR_ZERO)) { 243 blend_control |= R500_SRC_ALPHA_0_NO_READ; 244 } 245 246 /* Disable reading if SRC_ALPHA == 1. */ 247 if ((dstRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA || 248 dstRGB == PIPE_BLENDFACTOR_ZERO) && 249 (dstA == PIPE_BLENDFACTOR_INV_SRC_COLOR || 250 dstA == PIPE_BLENDFACTOR_INV_SRC_ALPHA || 251 dstA == PIPE_BLENDFACTOR_ZERO)) { 252 blend_control |= R500_SRC_ALPHA_1_NO_READ; 253 } 254 } 255 } 256 } 257 258 /* Optimization: discard pixels which don't change the colorbuffer. 259 * 260 * The code below is non-trivial and some math is involved. 261 * 262 * Discarding pixels must be disabled when FP16 AA is enabled. 263 * This is a hardware bug. Also, this implementation wouldn't work 264 * with FP blending enabled and equation clamping disabled. 265 * 266 * Equations other than ADD are rarely used and therefore won't be 267 * optimized. */ 268 if ((eqRGB == PIPE_BLEND_ADD || eqRGB == PIPE_BLEND_REVERSE_SUBTRACT) && 269 (eqA == PIPE_BLEND_ADD || eqA == PIPE_BLEND_REVERSE_SUBTRACT)) { 270 /* ADD: X+Y 271 * REVERSE_SUBTRACT: Y-X 272 * 273 * The idea is: 274 * If X = src*srcFactor = 0 and Y = dst*dstFactor = 1, 275 * then CB will not be changed. 276 * 277 * Given the srcFactor and dstFactor variables, we can derive 278 * what src and dst should be equal to and discard appropriate 279 * pixels. 280 */ 281 if (blend_discard_if_src_alpha_0(srcRGB, srcA, dstRGB, dstA)) { 282 blend_control |= R300_DISCARD_SRC_PIXELS_SRC_ALPHA_0; 283 } else if (blend_discard_if_src_alpha_1(srcRGB, srcA, 284 dstRGB, dstA)) { 285 blend_control |= R300_DISCARD_SRC_PIXELS_SRC_ALPHA_1; 286 } else if (blend_discard_if_src_color_0(srcRGB, srcA, 287 dstRGB, dstA)) { 288 blend_control |= R300_DISCARD_SRC_PIXELS_SRC_COLOR_0; 289 } else if (blend_discard_if_src_color_1(srcRGB, srcA, 290 dstRGB, dstA)) { 291 blend_control |= R300_DISCARD_SRC_PIXELS_SRC_COLOR_1; 292 } else if (blend_discard_if_src_alpha_color_0(srcRGB, srcA, 293 dstRGB, dstA)) { 294 blend_control |= 295 R300_DISCARD_SRC_PIXELS_SRC_ALPHA_COLOR_0; 296 } else if (blend_discard_if_src_alpha_color_1(srcRGB, srcA, 297 dstRGB, dstA)) { 298 blend_control |= 299 R300_DISCARD_SRC_PIXELS_SRC_ALPHA_COLOR_1; 300 } 301 } 302 303 /* separate alpha */ 304 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) { 305 blend_control |= R300_SEPARATE_ALPHA_ENABLE; 306 alpha_blend_control = 307 r300_translate_blend_function(eqA) | 308 (r300_translate_blend_factor(srcA) << R300_SRC_BLEND_SHIFT) | 309 (r300_translate_blend_factor(dstA) << R300_DST_BLEND_SHIFT); 310 } 311 } 312 313 /* PIPE_LOGICOP_* don't need to be translated, fortunately. */ 314 if (state->logicop_enable) { 315 rop = R300_RB3D_ROPCNTL_ROP_ENABLE | 316 (state->logicop_func) << R300_RB3D_ROPCNTL_ROP_SHIFT; 317 } 318 319 /* Color channel masks for all MRTs. */ 320 color_channel_mask = bgra_cmask(state->rt[0].colormask); 321 if (r300screen->caps.is_r500 && state->independent_blend_enable) { 322 if (state->rt[1].blend_enable) { 323 color_channel_mask |= bgra_cmask(state->rt[1].colormask) << 4; 324 } 325 if (state->rt[2].blend_enable) { 326 color_channel_mask |= bgra_cmask(state->rt[2].colormask) << 8; 327 } 328 if (state->rt[3].blend_enable) { 329 color_channel_mask |= bgra_cmask(state->rt[3].colormask) << 12; 330 } 331 } 332 333 /* Neither fglrx nor classic r300 ever set this, regardless of dithering 334 * state. Since it's an optional implementation detail, we can leave it 335 * out and never dither. 336 * 337 * This could be revisited if we ever get quality or conformance hints. 338 * 339 if (state->dither) { 340 dither = R300_RB3D_DITHER_CTL_DITHER_MODE_LUT | 341 R300_RB3D_DITHER_CTL_ALPHA_DITHER_MODE_LUT; 342 } 343 */ 344 345 /* Build a command buffer. */ 346 BEGIN_CB(blend->cb, 8); 347 OUT_CB_REG(R300_RB3D_ROPCNTL, rop); 348 OUT_CB_REG_SEQ(R300_RB3D_CBLEND, 3); 349 OUT_CB(blend_control); 350 OUT_CB(alpha_blend_control); 351 OUT_CB(color_channel_mask); 352 OUT_CB_REG(R300_RB3D_DITHER_CTL, dither); 353 END_CB; 354 355 /* The same as above, but with no colorbuffer reads and writes. */ 356 BEGIN_CB(blend->cb_no_readwrite, 8); 357 OUT_CB_REG(R300_RB3D_ROPCNTL, rop); 358 OUT_CB_REG_SEQ(R300_RB3D_CBLEND, 3); 359 OUT_CB(0); 360 OUT_CB(0); 361 OUT_CB(0); 362 OUT_CB_REG(R300_RB3D_DITHER_CTL, dither); 363 END_CB; 364 365 return (void*)blend; 366} 367 368/* Bind blend state. */ 369static void r300_bind_blend_state(struct pipe_context* pipe, 370 void* state) 371{ 372 struct r300_context* r300 = r300_context(pipe); 373 374 UPDATE_STATE(state, r300->blend_state); 375} 376 377/* Free blend state. */ 378static void r300_delete_blend_state(struct pipe_context* pipe, 379 void* state) 380{ 381 FREE(state); 382} 383 384/* Convert float to 10bit integer */ 385static unsigned float_to_fixed10(float f) 386{ 387 return CLAMP((unsigned)(f * 1023.9f), 0, 1023); 388} 389 390/* Set blend color. 391 * Setup both R300 and R500 registers, figure out later which one to write. */ 392static void r300_set_blend_color(struct pipe_context* pipe, 393 const struct pipe_blend_color* color) 394{ 395 struct r300_context* r300 = r300_context(pipe); 396 struct r300_blend_color_state* state = 397 (struct r300_blend_color_state*)r300->blend_color_state.state; 398 CB_LOCALS; 399 400 if (r300->screen->caps.is_r500) { 401 /* XXX if FP16 blending is enabled, we should use the FP16 format */ 402 BEGIN_CB(state->cb, 3); 403 OUT_CB_REG_SEQ(R500_RB3D_CONSTANT_COLOR_AR, 2); 404 OUT_CB(float_to_fixed10(color->color[0]) | 405 (float_to_fixed10(color->color[3]) << 16)); 406 OUT_CB(float_to_fixed10(color->color[2]) | 407 (float_to_fixed10(color->color[1]) << 16)); 408 END_CB; 409 } else { 410 union util_color uc; 411 util_pack_color(color->color, PIPE_FORMAT_B8G8R8A8_UNORM, &uc); 412 413 BEGIN_CB(state->cb, 2); 414 OUT_CB_REG(R300_RB3D_BLEND_COLOR, uc.ui); 415 END_CB; 416 } 417 418 r300->blend_color_state.dirty = TRUE; 419} 420 421static void r300_set_clip_state(struct pipe_context* pipe, 422 const struct pipe_clip_state* state) 423{ 424 struct r300_context* r300 = r300_context(pipe); 425 struct r300_clip_state *clip = 426 (struct r300_clip_state*)r300->clip_state.state; 427 CB_LOCALS; 428 429 clip->clip = *state; 430 431 if (r300->screen->caps.has_tcl) { 432 BEGIN_CB(clip->cb, 29); 433 OUT_CB_REG(R300_VAP_PVS_VECTOR_INDX_REG, 434 (r300->screen->caps.is_r500 ? 435 R500_PVS_UCP_START : R300_PVS_UCP_START)); 436 OUT_CB_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, 6 * 4); 437 OUT_CB_TABLE(state->ucp, 6 * 4); 438 OUT_CB_REG(R300_VAP_CLIP_CNTL, ((1 << state->nr) - 1) | 439 R300_PS_UCP_MODE_CLIP_AS_TRIFAN); 440 END_CB; 441 442 r300->clip_state.dirty = TRUE; 443 } else { 444 draw_flush(r300->draw); 445 draw_set_clip_state(r300->draw, state); 446 } 447} 448 449static void 450r300_set_sample_mask(struct pipe_context *pipe, 451 unsigned sample_mask) 452{ 453} 454 455 456/* Create a new depth, stencil, and alpha state based on the CSO dsa state. 457 * 458 * This contains the depth buffer, stencil buffer, alpha test, and such. 459 * On the Radeon, depth and stencil buffer setup are intertwined, which is 460 * the reason for some of the strange-looking assignments across registers. */ 461static void* 462 r300_create_dsa_state(struct pipe_context* pipe, 463 const struct pipe_depth_stencil_alpha_state* state) 464{ 465 struct r300_capabilities *caps = &r300_screen(pipe->screen)->caps; 466 struct r300_dsa_state* dsa = CALLOC_STRUCT(r300_dsa_state); 467 CB_LOCALS; 468 469 dsa->dsa = *state; 470 471 /* Depth test setup. */ 472 if (state->depth.enabled) { 473 dsa->z_buffer_control |= R300_Z_ENABLE; 474 475 if (state->depth.writemask) { 476 dsa->z_buffer_control |= R300_Z_WRITE_ENABLE; 477 } 478 479 dsa->z_stencil_control |= 480 (r300_translate_depth_stencil_function(state->depth.func) << 481 R300_Z_FUNC_SHIFT); 482 } 483 484 /* Stencil buffer setup. */ 485 if (state->stencil[0].enabled) { 486 dsa->z_buffer_control |= R300_STENCIL_ENABLE; 487 dsa->z_stencil_control |= 488 (r300_translate_depth_stencil_function(state->stencil[0].func) << 489 R300_S_FRONT_FUNC_SHIFT) | 490 (r300_translate_stencil_op(state->stencil[0].fail_op) << 491 R300_S_FRONT_SFAIL_OP_SHIFT) | 492 (r300_translate_stencil_op(state->stencil[0].zpass_op) << 493 R300_S_FRONT_ZPASS_OP_SHIFT) | 494 (r300_translate_stencil_op(state->stencil[0].zfail_op) << 495 R300_S_FRONT_ZFAIL_OP_SHIFT); 496 497 dsa->stencil_ref_mask = 498 (state->stencil[0].valuemask << R300_STENCILMASK_SHIFT) | 499 (state->stencil[0].writemask << R300_STENCILWRITEMASK_SHIFT); 500 501 if (state->stencil[1].enabled) { 502 dsa->two_sided = TRUE; 503 504 dsa->z_buffer_control |= R300_STENCIL_FRONT_BACK; 505 dsa->z_stencil_control |= 506 (r300_translate_depth_stencil_function(state->stencil[1].func) << 507 R300_S_BACK_FUNC_SHIFT) | 508 (r300_translate_stencil_op(state->stencil[1].fail_op) << 509 R300_S_BACK_SFAIL_OP_SHIFT) | 510 (r300_translate_stencil_op(state->stencil[1].zpass_op) << 511 R300_S_BACK_ZPASS_OP_SHIFT) | 512 (r300_translate_stencil_op(state->stencil[1].zfail_op) << 513 R300_S_BACK_ZFAIL_OP_SHIFT); 514 515 dsa->stencil_ref_bf = 516 (state->stencil[1].valuemask << R300_STENCILMASK_SHIFT) | 517 (state->stencil[1].writemask << R300_STENCILWRITEMASK_SHIFT); 518 519 if (caps->is_r500) { 520 dsa->z_buffer_control |= R500_STENCIL_REFMASK_FRONT_BACK; 521 } else { 522 dsa->two_sided_stencil_ref = 523 (state->stencil[0].valuemask != state->stencil[1].valuemask || 524 state->stencil[0].writemask != state->stencil[1].writemask); 525 } 526 } 527 } 528 529 /* Alpha test setup. */ 530 if (state->alpha.enabled) { 531 dsa->alpha_function = 532 r300_translate_alpha_function(state->alpha.func) | 533 R300_FG_ALPHA_FUNC_ENABLE; 534 535 /* We could use 10bit alpha ref but who needs that? */ 536 dsa->alpha_function |= float_to_ubyte(state->alpha.ref_value); 537 538 if (caps->is_r500) 539 dsa->alpha_function |= R500_FG_ALPHA_FUNC_8BIT; 540 } 541 542 BEGIN_CB(&dsa->cb_begin, 8); 543 OUT_CB_REG(R300_FG_ALPHA_FUNC, dsa->alpha_function); 544 OUT_CB_REG_SEQ(R300_ZB_CNTL, 3); 545 OUT_CB(dsa->z_buffer_control); 546 OUT_CB(dsa->z_stencil_control); 547 OUT_CB(dsa->stencil_ref_mask); 548 OUT_CB_REG(R500_ZB_STENCILREFMASK_BF, dsa->stencil_ref_bf); 549 END_CB; 550 551 BEGIN_CB(dsa->cb_no_readwrite, 8); 552 OUT_CB_REG(R300_FG_ALPHA_FUNC, dsa->alpha_function); 553 OUT_CB_REG_SEQ(R300_ZB_CNTL, 3); 554 OUT_CB(0); 555 OUT_CB(0); 556 OUT_CB(0); 557 OUT_CB_REG(R500_ZB_STENCILREFMASK_BF, 0); 558 END_CB; 559 560 return (void*)dsa; 561} 562 563static void r300_dsa_inject_stencilref(struct r300_context *r300) 564{ 565 struct r300_dsa_state *dsa = 566 (struct r300_dsa_state*)r300->dsa_state.state; 567 568 if (!dsa) 569 return; 570 571 dsa->stencil_ref_mask = 572 (dsa->stencil_ref_mask & ~R300_STENCILREF_MASK) | 573 r300->stencil_ref.ref_value[0]; 574 dsa->stencil_ref_bf = 575 (dsa->stencil_ref_bf & ~R300_STENCILREF_MASK) | 576 r300->stencil_ref.ref_value[1]; 577} 578 579/* Bind DSA state. */ 580static void r300_bind_dsa_state(struct pipe_context* pipe, 581 void* state) 582{ 583 struct r300_context* r300 = r300_context(pipe); 584 585 if (!state) { 586 return; 587 } 588 589 UPDATE_STATE(state, r300->dsa_state); 590 591 r300_dsa_inject_stencilref(r300); 592} 593 594/* Free DSA state. */ 595static void r300_delete_dsa_state(struct pipe_context* pipe, 596 void* state) 597{ 598 FREE(state); 599} 600 601static void r300_set_stencil_ref(struct pipe_context* pipe, 602 const struct pipe_stencil_ref* sr) 603{ 604 struct r300_context* r300 = r300_context(pipe); 605 606 r300->stencil_ref = *sr; 607 608 r300_dsa_inject_stencilref(r300); 609 r300->dsa_state.dirty = TRUE; 610} 611 612static void r300_tex_set_tiling_flags(struct r300_context *r300, 613 struct r300_texture *tex, unsigned level) 614{ 615 /* Check if the macrotile flag needs to be changed. 616 * Skip changing the flags otherwise. */ 617 if (tex->mip_macrotile[tex->surface_level] != tex->mip_macrotile[level]) { 618 /* Tiling determines how DRM treats the buffer data. 619 * We must flush CS when changing it if the buffer is referenced. */ 620 if (r300->rws->cs_is_buffer_referenced(r300->cs, 621 tex->buffer, R300_REF_CS)) 622 r300->context.flush(&r300->context, 0, NULL); 623 624 r300->rws->buffer_set_tiling(r300->rws, tex->buffer, 625 tex->microtile, tex->mip_macrotile[level], 626 tex->pitch[0] * util_format_get_blocksize(tex->b.b.format)); 627 628 tex->surface_level = level; 629 } 630} 631 632/* This switcheroo is needed just because of goddamned MACRO_SWITCH. */ 633static void r300_fb_set_tiling_flags(struct r300_context *r300, 634 const struct pipe_framebuffer_state *state) 635{ 636 unsigned i; 637 638 /* Set tiling flags for new surfaces. */ 639 for (i = 0; i < state->nr_cbufs; i++) { 640 r300_tex_set_tiling_flags(r300, 641 r300_texture(state->cbufs[i]->texture), 642 state->cbufs[i]->level); 643 } 644 if (state->zsbuf) { 645 r300_tex_set_tiling_flags(r300, 646 r300_texture(state->zsbuf->texture), 647 state->zsbuf->level); 648 } 649} 650 651static void r300_print_fb_surf_info(struct pipe_surface *surf, unsigned index, 652 const char *binding) 653{ 654 struct pipe_resource *tex = surf->texture; 655 struct r300_texture *rtex = r300_texture(tex); 656 657 fprintf(stderr, 658 "r300: %s[%i] Dim: %ix%i, Offset: %i, ZSlice: %i, " 659 "Face: %i, Level: %i, Format: %s\n" 660 661 "r300: TEX: Macro: %s, Micro: %s, Pitch: %i, " 662 "Dim: %ix%ix%i, LastLevel: %i, Format: %s\n", 663 664 binding, index, surf->width, surf->height, surf->offset, 665 surf->zslice, surf->face, surf->level, 666 util_format_short_name(surf->format), 667 668 rtex->macrotile ? "YES" : " NO", rtex->microtile ? "YES" : " NO", 669 rtex->hwpitch[0], tex->width0, tex->height0, tex->depth0, 670 tex->last_level, util_format_short_name(tex->format)); 671} 672 673void r300_mark_fb_state_dirty(struct r300_context *r300, 674 enum r300_fb_state_change change) 675{ 676 struct pipe_framebuffer_state *state = r300->fb_state.state; 677 678 /* What is marked as dirty depends on the enum r300_fb_state_change. */ 679 r300->gpu_flush.dirty = TRUE; 680 r300->fb_state.dirty = TRUE; 681 r300->hyperz_state.dirty = TRUE; 682 683 if (change == R300_CHANGED_FB_STATE) { 684 r300->aa_state.dirty = TRUE; 685 r300->fb_state_pipelined.dirty = TRUE; 686 } 687 688 /* Now compute the fb_state atom size. */ 689 r300->fb_state.size = 2 + (8 * state->nr_cbufs); 690 691 if (r300->cbzb_clear) 692 r300->fb_state.size += 10; 693 else if (state->zsbuf) 694 r300->fb_state.size += r300->screen->caps.has_hiz ? 18 : 14; 695 696 /* The size of the rest of atoms stays the same. */ 697} 698 699static void 700 r300_set_framebuffer_state(struct pipe_context* pipe, 701 const struct pipe_framebuffer_state* state) 702{ 703 struct r300_context* r300 = r300_context(pipe); 704 struct r300_aa_state *aa = (struct r300_aa_state*)r300->aa_state.state; 705 struct pipe_framebuffer_state *old_state = r300->fb_state.state; 706 unsigned max_width, max_height, i; 707 uint32_t zbuffer_bpp = 0; 708 709 if (r300->screen->caps.is_r500) { 710 max_width = max_height = 4096; 711 } else if (r300->screen->caps.is_r400) { 712 max_width = max_height = 4021; 713 } else { 714 max_width = max_height = 2560; 715 } 716 717 if (state->width > max_width || state->height > max_height) { 718 fprintf(stderr, "r300: Implementation error: Render targets are too " 719 "big in %s, refusing to bind framebuffer state!\n", __FUNCTION__); 720 return; 721 } 722 723 if (r300->draw) { 724 draw_flush(r300->draw); 725 } 726 727 /* If nr_cbufs is changed from zero to non-zero or vice versa... */ 728 if (!!old_state->nr_cbufs != !!state->nr_cbufs) { 729 r300->blend_state.dirty = TRUE; 730 } 731 /* If zsbuf is set from NULL to non-NULL or vice versa.. */ 732 if (!!old_state->zsbuf != !!state->zsbuf) { 733 r300->dsa_state.dirty = TRUE; 734 } 735 736 /* The tiling flags are dependent on the surface miplevel, unfortunately. */ 737 r300_fb_set_tiling_flags(r300, state); 738 739 util_assign_framebuffer_state(r300->fb_state.state, state); 740 741 r300_mark_fb_state_dirty(r300, R300_CHANGED_FB_STATE); 742 743 /* Polygon offset depends on the zbuffer bit depth. */ 744 if (state->zsbuf && r300->polygon_offset_enabled) { 745 switch (util_format_get_blocksize(state->zsbuf->texture->format)) { 746 case 2: 747 zbuffer_bpp = 16; 748 break; 749 case 4: 750 zbuffer_bpp = 24; 751 break; 752 } 753 754 if (r300->zbuffer_bpp != zbuffer_bpp) { 755 r300->zbuffer_bpp = zbuffer_bpp; 756 r300->rs_state.dirty = TRUE; 757 } 758 } 759 760 /* Set up AA config. */ 761 if (r300->rws->get_value(r300->rws, R300_VID_DRM_2_3_0)) { 762 if (state->nr_cbufs && state->cbufs[0]->texture->nr_samples > 1) { 763 aa->aa_config = R300_GB_AA_CONFIG_AA_ENABLE; 764 765 switch (state->cbufs[0]->texture->nr_samples) { 766 case 2: 767 aa->aa_config |= R300_GB_AA_CONFIG_NUM_AA_SUBSAMPLES_2; 768 break; 769 case 3: 770 aa->aa_config |= R300_GB_AA_CONFIG_NUM_AA_SUBSAMPLES_3; 771 break; 772 case 4: 773 aa->aa_config |= R300_GB_AA_CONFIG_NUM_AA_SUBSAMPLES_4; 774 break; 775 case 6: 776 aa->aa_config |= R300_GB_AA_CONFIG_NUM_AA_SUBSAMPLES_6; 777 break; 778 } 779 } else { 780 aa->aa_config = 0; 781 } 782 } 783 784 if (DBG_ON(r300, DBG_FB)) { 785 fprintf(stderr, "r300: set_framebuffer_state:\n"); 786 for (i = 0; i < state->nr_cbufs; i++) { 787 r300_print_fb_surf_info(state->cbufs[i], i, "CB"); 788 } 789 if (state->zsbuf) { 790 r300_print_fb_surf_info(state->zsbuf, 0, "ZB"); 791 } 792 } 793} 794 795/* Create fragment shader state. */ 796static void* r300_create_fs_state(struct pipe_context* pipe, 797 const struct pipe_shader_state* shader) 798{ 799 struct r300_fragment_shader* fs = NULL; 800 801 fs = (struct r300_fragment_shader*)CALLOC_STRUCT(r300_fragment_shader); 802 803 /* Copy state directly into shader. */ 804 fs->state = *shader; 805 fs->state.tokens = tgsi_dup_tokens(shader->tokens); 806 807 return (void*)fs; 808} 809 810void r300_mark_fs_code_dirty(struct r300_context *r300) 811{ 812 struct r300_fragment_shader* fs = r300_fs(r300); 813 814 r300->fs.dirty = TRUE; 815 r300->fs_rc_constant_state.dirty = TRUE; 816 r300->fs_constants.dirty = TRUE; 817 r300->fs.size = fs->shader->cb_code_size; 818 819 if (r300->screen->caps.is_r500) { 820 r300->fs_rc_constant_state.size = fs->shader->rc_state_count * 7; 821 r300->fs_constants.size = fs->shader->externals_count * 4 + 3; 822 } else { 823 r300->fs_rc_constant_state.size = fs->shader->rc_state_count * 5; 824 r300->fs_constants.size = fs->shader->externals_count * 4 + 1; 825 } 826} 827 828/* Bind fragment shader state. */ 829static void r300_bind_fs_state(struct pipe_context* pipe, void* shader) 830{ 831 struct r300_context* r300 = r300_context(pipe); 832 struct r300_fragment_shader* fs = (struct r300_fragment_shader*)shader; 833 834 if (fs == NULL) { 835 r300->fs.state = NULL; 836 return; 837 } 838 839 r300->fs.state = fs; 840 r300_pick_fragment_shader(r300); 841 r300_mark_fs_code_dirty(r300); 842 843 r300->rs_block_state.dirty = TRUE; /* Will be updated before the emission. */ 844} 845 846/* Delete fragment shader state. */ 847static void r300_delete_fs_state(struct pipe_context* pipe, void* shader) 848{ 849 struct r300_fragment_shader* fs = (struct r300_fragment_shader*)shader; 850 struct r300_fragment_shader_code *tmp, *ptr = fs->first; 851 852 while (ptr) { 853 tmp = ptr; 854 ptr = ptr->next; 855 rc_constants_destroy(&tmp->code.constants); 856 FREE(tmp->cb_code); 857 FREE(tmp); 858 } 859 FREE((void*)fs->state.tokens); 860 FREE(shader); 861} 862 863static void r300_set_polygon_stipple(struct pipe_context* pipe, 864 const struct pipe_poly_stipple* state) 865{ 866 /* XXX no idea how to set this up, but not terribly important */ 867} 868 869/* Create a new rasterizer state based on the CSO rasterizer state. 870 * 871 * This is a very large chunk of state, and covers most of the graphics 872 * backend (GB), geometry assembly (GA), and setup unit (SU) blocks. 873 * 874 * In a not entirely unironic sidenote, this state has nearly nothing to do 875 * with the actual block on the Radeon called the rasterizer (RS). */ 876static void* r300_create_rs_state(struct pipe_context* pipe, 877 const struct pipe_rasterizer_state* state) 878{ 879 struct r300_rs_state* rs = CALLOC_STRUCT(r300_rs_state); 880 int i; 881 float psiz; 882 uint32_t vap_control_status; /* R300_VAP_CNTL_STATUS: 0x2140 */ 883 uint32_t point_size; /* R300_GA_POINT_SIZE: 0x421c */ 884 uint32_t point_minmax; /* R300_GA_POINT_MINMAX: 0x4230 */ 885 uint32_t line_control; /* R300_GA_LINE_CNTL: 0x4234 */ 886 uint32_t polygon_offset_enable; /* R300_SU_POLY_OFFSET_ENABLE: 0x42b4 */ 887 uint32_t cull_mode; /* R300_SU_CULL_MODE: 0x42b8 */ 888 uint32_t line_stipple_config; /* R300_GA_LINE_STIPPLE_CONFIG: 0x4328 */ 889 uint32_t line_stipple_value; /* R300_GA_LINE_STIPPLE_VALUE: 0x4260 */ 890 uint32_t polygon_mode; /* R300_GA_POLY_MODE: 0x4288 */ 891 uint32_t clip_rule; /* R300_SC_CLIP_RULE: 0x43D0 */ 892 893 /* Specifies top of Raster pipe specific enable controls, 894 * i.e. texture coordinates stuffing for points, lines, triangles */ 895 uint32_t stuffing_enable; /* R300_GB_ENABLE: 0x4008 */ 896 897 /* Point sprites texture coordinates, 0: lower left, 1: upper right */ 898 float point_texcoord_left; /* R300_GA_POINT_S0: 0x4200 */ 899 float point_texcoord_bottom = 0;/* R300_GA_POINT_T0: 0x4204 */ 900 float point_texcoord_right; /* R300_GA_POINT_S1: 0x4208 */ 901 float point_texcoord_top = 0; /* R300_GA_POINT_T1: 0x420c */ 902 CB_LOCALS; 903 904 /* Copy rasterizer state. */ 905 rs->rs = *state; 906 rs->rs_draw = *state; 907 908 /* Override some states for Draw. */ 909 rs->rs_draw.sprite_coord_enable = 0; /* We can do this in HW. */ 910 911#ifdef PIPE_ARCH_LITTLE_ENDIAN 912 vap_control_status = R300_VC_NO_SWAP; 913#else 914 vap_control_status = R300_VC_32BIT_SWAP; 915#endif 916 917 /* If no TCL engine is present, turn off the HW TCL. */ 918 if (!r300_screen(pipe->screen)->caps.has_tcl) { 919 vap_control_status |= R300_VAP_TCL_BYPASS; 920 } 921 922 /* Point size width and height. */ 923 point_size = 924 pack_float_16_6x(state->point_size) | 925 (pack_float_16_6x(state->point_size) << R300_POINTSIZE_X_SHIFT); 926 927 /* Point size clamping. */ 928 if (state->point_size_per_vertex) { 929 /* Per-vertex point size. 930 * Clamp to [0, max FB size] */ 931 psiz = pipe->screen->get_paramf(pipe->screen, 932 PIPE_CAP_MAX_POINT_WIDTH); 933 point_minmax = 934 pack_float_16_6x(psiz) << R300_GA_POINT_MINMAX_MAX_SHIFT; 935 } else { 936 /* We cannot disable the point-size vertex output, 937 * so clamp it. */ 938 psiz = state->point_size; 939 point_minmax = 940 (pack_float_16_6x(psiz) << R300_GA_POINT_MINMAX_MIN_SHIFT) | 941 (pack_float_16_6x(psiz) << R300_GA_POINT_MINMAX_MAX_SHIFT); 942 } 943 944 /* Line control. */ 945 line_control = pack_float_16_6x(state->line_width) | 946 R300_GA_LINE_CNTL_END_TYPE_COMP; 947 948 /* Enable polygon mode */ 949 polygon_mode = 0; 950 if (state->fill_front != PIPE_POLYGON_MODE_FILL || 951 state->fill_back != PIPE_POLYGON_MODE_FILL) { 952 polygon_mode = R300_GA_POLY_MODE_DUAL; 953 } 954 955 /* Front face */ 956 if (state->front_ccw) 957 cull_mode = R300_FRONT_FACE_CCW; 958 else 959 cull_mode = R300_FRONT_FACE_CW; 960 961 /* Polygon offset */ 962 polygon_offset_enable = 0; 963 if (util_get_offset(state, state->fill_front)) { 964 polygon_offset_enable |= R300_FRONT_ENABLE; 965 } 966 if (util_get_offset(state, state->fill_back)) { 967 polygon_offset_enable |= R300_BACK_ENABLE; 968 } 969 970 rs->polygon_offset_enable = polygon_offset_enable != 0; 971 972 /* Polygon mode */ 973 if (polygon_mode) { 974 polygon_mode |= 975 r300_translate_polygon_mode_front(state->fill_front); 976 polygon_mode |= 977 r300_translate_polygon_mode_back(state->fill_back); 978 } 979 980 if (state->cull_face & PIPE_FACE_FRONT) { 981 cull_mode |= R300_CULL_FRONT; 982 } 983 if (state->cull_face & PIPE_FACE_BACK) { 984 cull_mode |= R300_CULL_BACK; 985 } 986 987 if (state->line_stipple_enable) { 988 line_stipple_config = 989 R300_GA_LINE_STIPPLE_CONFIG_LINE_RESET_LINE | 990 (fui((float)state->line_stipple_factor) & 991 R300_GA_LINE_STIPPLE_CONFIG_STIPPLE_SCALE_MASK); 992 /* XXX this might need to be scaled up */ 993 line_stipple_value = state->line_stipple_pattern; 994 } else { 995 line_stipple_config = 0; 996 line_stipple_value = 0; 997 } 998 999 if (state->flatshade) { 1000 rs->color_control = R300_SHADE_MODEL_FLAT; 1001 } else { 1002 rs->color_control = R300_SHADE_MODEL_SMOOTH; 1003 } 1004 1005 clip_rule = state->scissor ? 0xAAAA : 0xFFFF; 1006 1007 /* Point sprites */ 1008 stuffing_enable = 0; 1009 if (state->sprite_coord_enable) { 1010 stuffing_enable = R300_GB_POINT_STUFF_ENABLE; 1011 for (i = 0; i < 8; i++) { 1012 if (state->sprite_coord_enable & (1 << i)) 1013 stuffing_enable |= 1014 R300_GB_TEX_STR << (R300_GB_TEX0_SOURCE_SHIFT + (i*2)); 1015 } 1016 1017 point_texcoord_left = 0.0f; 1018 point_texcoord_right = 1.0f; 1019 1020 switch (state->sprite_coord_mode) { 1021 case PIPE_SPRITE_COORD_UPPER_LEFT: 1022 point_texcoord_top = 0.0f; 1023 point_texcoord_bottom = 1.0f; 1024 break; 1025 case PIPE_SPRITE_COORD_LOWER_LEFT: 1026 point_texcoord_top = 1.0f; 1027 point_texcoord_bottom = 0.0f; 1028 break; 1029 } 1030 } 1031 1032 /* Build the main command buffer. */ 1033 BEGIN_CB(rs->cb_main, 25); 1034 OUT_CB_REG(R300_VAP_CNTL_STATUS, vap_control_status); 1035 OUT_CB_REG(R300_GA_POINT_SIZE, point_size); 1036 OUT_CB_REG_SEQ(R300_GA_POINT_MINMAX, 2); 1037 OUT_CB(point_minmax); 1038 OUT_CB(line_control); 1039 OUT_CB_REG_SEQ(R300_SU_POLY_OFFSET_ENABLE, 2); 1040 OUT_CB(polygon_offset_enable); 1041 rs->cull_mode_index = 9; 1042 OUT_CB(cull_mode); 1043 OUT_CB_REG(R300_GA_LINE_STIPPLE_CONFIG, line_stipple_config); 1044 OUT_CB_REG(R300_GA_LINE_STIPPLE_VALUE, line_stipple_value); 1045 OUT_CB_REG(R300_GA_POLY_MODE, polygon_mode); 1046 OUT_CB_REG(R300_SC_CLIP_RULE, clip_rule); 1047 OUT_CB_REG(R300_GB_ENABLE, stuffing_enable); 1048 OUT_CB_REG_SEQ(R300_GA_POINT_S0, 4); 1049 OUT_CB_32F(point_texcoord_left); 1050 OUT_CB_32F(point_texcoord_bottom); 1051 OUT_CB_32F(point_texcoord_right); 1052 OUT_CB_32F(point_texcoord_top); 1053 END_CB; 1054 1055 /* Build the two command buffers for polygon offset setup. */ 1056 if (polygon_offset_enable) { 1057 float scale = state->offset_scale * 12; 1058 float offset = state->offset_units * 4; 1059 1060 BEGIN_CB(rs->cb_poly_offset_zb16, 5); 1061 OUT_CB_REG_SEQ(R300_SU_POLY_OFFSET_FRONT_SCALE, 4); 1062 OUT_CB_32F(scale); 1063 OUT_CB_32F(offset); 1064 OUT_CB_32F(scale); 1065 OUT_CB_32F(offset); 1066 END_CB; 1067 1068 offset = state->offset_units * 2; 1069 1070 BEGIN_CB(rs->cb_poly_offset_zb24, 5); 1071 OUT_CB_REG_SEQ(R300_SU_POLY_OFFSET_FRONT_SCALE, 4); 1072 OUT_CB_32F(scale); 1073 OUT_CB_32F(offset); 1074 OUT_CB_32F(scale); 1075 OUT_CB_32F(offset); 1076 END_CB; 1077 } 1078 1079 return (void*)rs; 1080} 1081 1082/* Bind rasterizer state. */ 1083static void r300_bind_rs_state(struct pipe_context* pipe, void* state) 1084{ 1085 struct r300_context* r300 = r300_context(pipe); 1086 struct r300_rs_state* rs = (struct r300_rs_state*)state; 1087 int last_sprite_coord_enable = r300->sprite_coord_enable; 1088 boolean last_two_sided_color = r300->two_sided_color; 1089 1090 if (r300->draw && rs) { 1091 draw_flush(r300->draw); 1092 draw_set_rasterizer_state(r300->draw, &rs->rs_draw, state); 1093 } 1094 1095 if (rs) { 1096 r300->polygon_offset_enabled = (rs->rs.offset_point || 1097 rs->rs.offset_line || 1098 rs->rs.offset_tri); 1099 r300->sprite_coord_enable = rs->rs.sprite_coord_enable; 1100 r300->two_sided_color = rs->rs.light_twoside; 1101 } else { 1102 r300->polygon_offset_enabled = FALSE; 1103 r300->sprite_coord_enable = 0; 1104 r300->two_sided_color = FALSE; 1105 } 1106 1107 UPDATE_STATE(state, r300->rs_state); 1108 r300->rs_state.size = 25 + (r300->polygon_offset_enabled ? 5 : 0); 1109 1110 if (last_sprite_coord_enable != r300->sprite_coord_enable || 1111 last_two_sided_color != r300->two_sided_color) { 1112 r300->rs_block_state.dirty = TRUE; 1113 } 1114} 1115 1116/* Free rasterizer state. */ 1117static void r300_delete_rs_state(struct pipe_context* pipe, void* state) 1118{ 1119 FREE(state); 1120} 1121 1122static void* 1123 r300_create_sampler_state(struct pipe_context* pipe, 1124 const struct pipe_sampler_state* state) 1125{ 1126 struct r300_context* r300 = r300_context(pipe); 1127 struct r300_sampler_state* sampler = CALLOC_STRUCT(r300_sampler_state); 1128 boolean is_r500 = r300->screen->caps.is_r500; 1129 int lod_bias; 1130 union util_color uc; 1131 1132 sampler->state = *state; 1133 1134 /* r300 doesn't handle CLAMP and MIRROR_CLAMP correctly when either MAG 1135 * or MIN filter is NEAREST. Since texwrap produces same results 1136 * for CLAMP and CLAMP_TO_EDGE, we use them instead. */ 1137 if (sampler->state.min_img_filter == PIPE_TEX_FILTER_NEAREST || 1138 sampler->state.mag_img_filter == PIPE_TEX_FILTER_NEAREST) { 1139 /* Wrap S. */ 1140 if (sampler->state.wrap_s == PIPE_TEX_WRAP_CLAMP) 1141 sampler->state.wrap_s = PIPE_TEX_WRAP_CLAMP_TO_EDGE; 1142 else if (sampler->state.wrap_s == PIPE_TEX_WRAP_MIRROR_CLAMP) 1143 sampler->state.wrap_s = PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE; 1144 1145 /* Wrap T. */ 1146 if (sampler->state.wrap_t == PIPE_TEX_WRAP_CLAMP) 1147 sampler->state.wrap_t = PIPE_TEX_WRAP_CLAMP_TO_EDGE; 1148 else if (sampler->state.wrap_t == PIPE_TEX_WRAP_MIRROR_CLAMP) 1149 sampler->state.wrap_t = PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE; 1150 1151 /* Wrap R. */ 1152 if (sampler->state.wrap_r == PIPE_TEX_WRAP_CLAMP) 1153 sampler->state.wrap_r = PIPE_TEX_WRAP_CLAMP_TO_EDGE; 1154 else if (sampler->state.wrap_r == PIPE_TEX_WRAP_MIRROR_CLAMP) 1155 sampler->state.wrap_r = PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE; 1156 } 1157 1158 sampler->filter0 |= 1159 (r300_translate_wrap(sampler->state.wrap_s) << R300_TX_WRAP_S_SHIFT) | 1160 (r300_translate_wrap(sampler->state.wrap_t) << R300_TX_WRAP_T_SHIFT) | 1161 (r300_translate_wrap(sampler->state.wrap_r) << R300_TX_WRAP_R_SHIFT); 1162 1163 sampler->filter0 |= r300_translate_tex_filters(state->min_img_filter, 1164 state->mag_img_filter, 1165 state->min_mip_filter, 1166 state->max_anisotropy > 0); 1167 1168 sampler->filter0 |= r300_anisotropy(state->max_anisotropy); 1169 1170 /* Unfortunately, r300-r500 don't support floating-point mipmap lods. */ 1171 /* We must pass these to the merge function to clamp them properly. */ 1172 sampler->min_lod = MAX2((unsigned)state->min_lod, 0); 1173 sampler->max_lod = MAX2((unsigned)ceilf(state->max_lod), 0); 1174 1175 lod_bias = CLAMP((int)(state->lod_bias * 32 + 1), -(1 << 9), (1 << 9) - 1); 1176 1177 sampler->filter1 |= (lod_bias << R300_LOD_BIAS_SHIFT) & R300_LOD_BIAS_MASK; 1178 1179 /* This is very high quality anisotropic filtering for R5xx. 1180 * It's good for benchmarking the performance of texturing but 1181 * in practice we don't want to slow down the driver because it's 1182 * a pretty good performance killer. Feel free to play with it. */ 1183 if (DBG_ON(r300, DBG_ANISOHQ) && is_r500) { 1184 sampler->filter1 |= r500_anisotropy(state->max_anisotropy); 1185 } 1186 1187 util_pack_color(state->border_color, PIPE_FORMAT_B8G8R8A8_UNORM, &uc); 1188 sampler->border_color = uc.ui; 1189 1190 /* R500-specific fixups and optimizations */ 1191 if (r300->screen->caps.is_r500) { 1192 sampler->filter1 |= R500_BORDER_FIX; 1193 } 1194 1195 return (void*)sampler; 1196} 1197 1198static void r300_bind_sampler_states(struct pipe_context* pipe, 1199 unsigned count, 1200 void** states) 1201{ 1202 struct r300_context* r300 = r300_context(pipe); 1203 struct r300_textures_state* state = 1204 (struct r300_textures_state*)r300->textures_state.state; 1205 unsigned tex_units = r300->screen->caps.num_tex_units; 1206 1207 if (count > tex_units) { 1208 return; 1209 } 1210 1211 memcpy(state->sampler_states, states, sizeof(void*) * count); 1212 state->sampler_state_count = count; 1213 1214 r300->textures_state.dirty = TRUE; 1215} 1216 1217static void r300_lacks_vertex_textures(struct pipe_context* pipe, 1218 unsigned count, 1219 void** states) 1220{ 1221} 1222 1223static void r300_delete_sampler_state(struct pipe_context* pipe, void* state) 1224{ 1225 FREE(state); 1226} 1227 1228static uint32_t r300_assign_texture_cache_region(unsigned index, unsigned num) 1229{ 1230 /* This looks like a hack, but I believe it's suppose to work like 1231 * that. To illustrate how this works, let's assume you have 5 textures. 1232 * From docs, 5 and the successive numbers are: 1233 * 1234 * FOURTH_1 = 5 1235 * FOURTH_2 = 6 1236 * FOURTH_3 = 7 1237 * EIGHTH_0 = 8 1238 * EIGHTH_1 = 9 1239 * 1240 * First 3 textures will get 3/4 of size of the cache, divived evenly 1241 * between them. The last 1/4 of the cache must be divided between 1242 * the last 2 textures, each will therefore get 1/8 of the cache. 1243 * Why not just to use "5 + texture_index" ? 1244 * 1245 * This simple trick works for all "num" <= 16. 1246 */ 1247 if (num <= 1) 1248 return R300_TX_CACHE(R300_TX_CACHE_WHOLE); 1249 else 1250 return R300_TX_CACHE(num + index); 1251} 1252 1253static void r300_set_fragment_sampler_views(struct pipe_context* pipe, 1254 unsigned count, 1255 struct pipe_sampler_view** views) 1256{ 1257 struct r300_context* r300 = r300_context(pipe); 1258 struct r300_textures_state* state = 1259 (struct r300_textures_state*)r300->textures_state.state; 1260 struct r300_texture *texture; 1261 unsigned i, real_num_views = 0, view_index = 0; 1262 unsigned tex_units = r300->screen->caps.num_tex_units; 1263 boolean dirty_tex = FALSE; 1264 1265 if (count > tex_units) { 1266 return; 1267 } 1268 1269 /* Calculate the real number of views. */ 1270 for (i = 0; i < count; i++) { 1271 if (views[i]) 1272 real_num_views++; 1273 } 1274 1275 for (i = 0; i < count; i++) { 1276 if (&state->sampler_views[i]->base != views[i]) { 1277 pipe_sampler_view_reference( 1278 (struct pipe_sampler_view**)&state->sampler_views[i], 1279 views[i]); 1280 1281 if (!views[i]) { 1282 continue; 1283 } 1284 1285 /* A new sampler view (= texture)... */ 1286 dirty_tex = TRUE; 1287 1288 /* Set the texrect factor in the fragment shader. 1289 * Needed for RECT and NPOT fallback. */ 1290 texture = r300_texture(views[i]->texture); 1291 if (texture->uses_pitch) { 1292 r300->fs_rc_constant_state.dirty = TRUE; 1293 } 1294 1295 state->sampler_views[i]->texcache_region = 1296 r300_assign_texture_cache_region(view_index, real_num_views); 1297 view_index++; 1298 } 1299 } 1300 1301 for (i = count; i < tex_units; i++) { 1302 if (state->sampler_views[i]) { 1303 pipe_sampler_view_reference( 1304 (struct pipe_sampler_view**)&state->sampler_views[i], 1305 NULL); 1306 } 1307 } 1308 1309 state->sampler_view_count = count; 1310 1311 r300->textures_state.dirty = TRUE; 1312 1313 if (dirty_tex) { 1314 r300->texture_cache_inval.dirty = TRUE; 1315 } 1316} 1317 1318static struct pipe_sampler_view * 1319r300_create_sampler_view(struct pipe_context *pipe, 1320 struct pipe_resource *texture, 1321 const struct pipe_sampler_view *templ) 1322{ 1323 struct r300_sampler_view *view = CALLOC_STRUCT(r300_sampler_view); 1324 struct r300_texture *tex = r300_texture(texture); 1325 1326 if (view) { 1327 view->base = *templ; 1328 view->base.reference.count = 1; 1329 view->base.context = pipe; 1330 view->base.texture = NULL; 1331 pipe_resource_reference(&view->base.texture, texture); 1332 1333 view->swizzle[0] = templ->swizzle_r; 1334 view->swizzle[1] = templ->swizzle_g; 1335 view->swizzle[2] = templ->swizzle_b; 1336 view->swizzle[3] = templ->swizzle_a; 1337 1338 view->format = tex->tx_format; 1339 view->format.format1 |= r300_translate_texformat(templ->format, 1340 view->swizzle); 1341 if (r300_screen(pipe->screen)->caps.is_r500) { 1342 view->format.format2 |= r500_tx_format_msb_bit(templ->format); 1343 } 1344 } 1345 1346 return (struct pipe_sampler_view*)view; 1347} 1348 1349static void 1350r300_sampler_view_destroy(struct pipe_context *pipe, 1351 struct pipe_sampler_view *view) 1352{ 1353 pipe_resource_reference(&view->texture, NULL); 1354 FREE(view); 1355} 1356 1357static void r300_set_scissor_state(struct pipe_context* pipe, 1358 const struct pipe_scissor_state* state) 1359{ 1360 struct r300_context* r300 = r300_context(pipe); 1361 1362 memcpy(r300->scissor_state.state, state, 1363 sizeof(struct pipe_scissor_state)); 1364 1365 r300->scissor_state.dirty = TRUE; 1366} 1367 1368static void r300_set_viewport_state(struct pipe_context* pipe, 1369 const struct pipe_viewport_state* state) 1370{ 1371 struct r300_context* r300 = r300_context(pipe); 1372 struct r300_viewport_state* viewport = 1373 (struct r300_viewport_state*)r300->viewport_state.state; 1374 1375 r300->viewport = *state; 1376 1377 if (r300->draw) { 1378 draw_flush(r300->draw); 1379 draw_set_viewport_state(r300->draw, state); 1380 viewport->vte_control = R300_VTX_XY_FMT | R300_VTX_Z_FMT; 1381 return; 1382 } 1383 1384 /* Do the transform in HW. */ 1385 viewport->vte_control = R300_VTX_W0_FMT; 1386 1387 if (state->scale[0] != 1.0f) { 1388 viewport->xscale = state->scale[0]; 1389 viewport->vte_control |= R300_VPORT_X_SCALE_ENA; 1390 } 1391 if (state->scale[1] != 1.0f) { 1392 viewport->yscale = state->scale[1]; 1393 viewport->vte_control |= R300_VPORT_Y_SCALE_ENA; 1394 } 1395 if (state->scale[2] != 1.0f) { 1396 viewport->zscale = state->scale[2]; 1397 viewport->vte_control |= R300_VPORT_Z_SCALE_ENA; 1398 } 1399 if (state->translate[0] != 0.0f) { 1400 viewport->xoffset = state->translate[0]; 1401 viewport->vte_control |= R300_VPORT_X_OFFSET_ENA; 1402 } 1403 if (state->translate[1] != 0.0f) { 1404 viewport->yoffset = state->translate[1]; 1405 viewport->vte_control |= R300_VPORT_Y_OFFSET_ENA; 1406 } 1407 if (state->translate[2] != 0.0f) { 1408 viewport->zoffset = state->translate[2]; 1409 viewport->vte_control |= R300_VPORT_Z_OFFSET_ENA; 1410 } 1411 1412 r300->viewport_state.dirty = TRUE; 1413 if (r300->fs.state && r300_fs(r300)->shader->inputs.wpos != ATTR_UNUSED) { 1414 r300->fs_rc_constant_state.dirty = TRUE; 1415 } 1416} 1417 1418static void r300_set_vertex_buffers(struct pipe_context* pipe, 1419 unsigned count, 1420 const struct pipe_vertex_buffer* buffers) 1421{ 1422 struct r300_context* r300 = r300_context(pipe); 1423 struct pipe_vertex_buffer *vbo; 1424 unsigned i, max_index = (1 << 24) - 1; 1425 boolean any_user_buffer = FALSE; 1426 1427 if (count == r300->vertex_buffer_count && 1428 memcmp(r300->vertex_buffer, buffers, 1429 sizeof(struct pipe_vertex_buffer) * count) == 0) { 1430 return; 1431 } 1432 1433 if (r300->screen->caps.has_tcl) { 1434 /* HW TCL. */ 1435 r300->incompatible_vb_layout = FALSE; 1436 1437 /* Check if the strides and offsets are aligned to the size of DWORD. */ 1438 for (i = 0; i < count; i++) { 1439 if (buffers[i].buffer) { 1440 if (buffers[i].stride % 4 != 0 || 1441 buffers[i].buffer_offset % 4 != 0) { 1442 r300->incompatible_vb_layout = TRUE; 1443 break; 1444 } 1445 } 1446 } 1447 1448 for (i = 0; i < count; i++) { 1449 /* Why, yes, I AM casting away constness. How did you know? */ 1450 vbo = (struct pipe_vertex_buffer*)&buffers[i]; 1451 1452 /* Skip NULL buffers */ 1453 if (!buffers[i].buffer) { 1454 continue; 1455 } 1456 1457 if (r300_buffer_is_user_buffer(vbo->buffer)) { 1458 any_user_buffer = TRUE; 1459 } 1460 1461 if (vbo->max_index == ~0) { 1462 /* if no VBO stride then only one vertex value so max index is 1 */ 1463 /* should think about converting to VS constants like svga does */ 1464 if (!vbo->stride) 1465 vbo->max_index = 1; 1466 else 1467 vbo->max_index = 1468 (vbo->buffer->width0 - vbo->buffer_offset) / vbo->stride; 1469 } 1470 1471 max_index = MIN2(vbo->max_index, max_index); 1472 } 1473 1474 r300->any_user_vbs = any_user_buffer; 1475 r300->vertex_buffer_max_index = max_index; 1476 1477 } else { 1478 /* SW TCL. */ 1479 draw_flush(r300->draw); 1480 draw_set_vertex_buffers(r300->draw, count, buffers); 1481 } 1482 1483 /* Common code. */ 1484 for (i = 0; i < count; i++) { 1485 /* Reference our buffer. */ 1486 pipe_resource_reference(&r300->vertex_buffer[i].buffer, buffers[i].buffer); 1487 } 1488 for (; i < r300->vertex_buffer_count; i++) { 1489 /* Dereference any old buffers. */ 1490 pipe_resource_reference(&r300->vertex_buffer[i].buffer, NULL); 1491 } 1492 1493 memcpy(r300->vertex_buffer, buffers, 1494 sizeof(struct pipe_vertex_buffer) * count); 1495 r300->vertex_buffer_count = count; 1496} 1497 1498/* Initialize the PSC tables. */ 1499static void r300_vertex_psc(struct r300_vertex_element_state *velems) 1500{ 1501 struct r300_vertex_stream_state *vstream = &velems->vertex_stream; 1502 uint16_t type, swizzle; 1503 enum pipe_format format; 1504 unsigned i; 1505 1506 if (velems->count > 16) { 1507 fprintf(stderr, "r300: More than 16 vertex elements are not supported," 1508 " requested %i, using 16.\n", velems->count); 1509 velems->count = 16; 1510 } 1511 1512 /* Vertex shaders have no semantics on their inputs, 1513 * so PSC should just route stuff based on the vertex elements, 1514 * and not on attrib information. */ 1515 for (i = 0; i < velems->count; i++) { 1516 format = velems->hw_format[i]; 1517 1518 type = r300_translate_vertex_data_type(format); 1519 if (type == R300_INVALID_FORMAT) { 1520 fprintf(stderr, "r300: Bad vertex format %s.\n", 1521 util_format_short_name(format)); 1522 assert(0); 1523 abort(); 1524 } 1525 1526 type |= i << R300_DST_VEC_LOC_SHIFT; 1527 swizzle = r300_translate_vertex_data_swizzle(format); 1528 1529 if (i & 1) { 1530 vstream->vap_prog_stream_cntl[i >> 1] |= type << 16; 1531 vstream->vap_prog_stream_cntl_ext[i >> 1] |= swizzle << 16; 1532 } else { 1533 vstream->vap_prog_stream_cntl[i >> 1] |= type; 1534 vstream->vap_prog_stream_cntl_ext[i >> 1] |= swizzle; 1535 } 1536 } 1537 1538 /* Set the last vector in the PSC. */ 1539 if (i) { 1540 i -= 1; 1541 } 1542 vstream->vap_prog_stream_cntl[i >> 1] |= 1543 (R300_LAST_VEC << (i & 1 ? 16 : 0)); 1544 1545 vstream->count = (i >> 1) + 1; 1546} 1547 1548#define FORMAT_REPLACE(what, withwhat) \ 1549 case PIPE_FORMAT_##what: *format = PIPE_FORMAT_##withwhat; break 1550 1551static void* r300_create_vertex_elements_state(struct pipe_context* pipe, 1552 unsigned count, 1553 const struct pipe_vertex_element* attribs) 1554{ 1555 struct r300_vertex_element_state *velems; 1556 unsigned i; 1557 enum pipe_format *format; 1558 1559 assert(count <= PIPE_MAX_ATTRIBS); 1560 velems = CALLOC_STRUCT(r300_vertex_element_state); 1561 if (velems != NULL) { 1562 velems->count = count; 1563 memcpy(velems->velem, attribs, sizeof(struct pipe_vertex_element) * count); 1564 1565 if (r300_screen(pipe->screen)->caps.has_tcl) { 1566 /* Set the best hw format in case the original format is not 1567 * supported by hw. */ 1568 for (i = 0; i < count; i++) { 1569 velems->hw_format[i] = velems->velem[i].src_format; 1570 format = &velems->hw_format[i]; 1571 1572 /* This is basically the list of unsupported formats. 1573 * For now we don't care about the alignment, that's going to 1574 * be sorted out after the PSC setup. */ 1575 switch (*format) { 1576 FORMAT_REPLACE(R64_FLOAT, R32_FLOAT); 1577 FORMAT_REPLACE(R64G64_FLOAT, R32G32_FLOAT); 1578 FORMAT_REPLACE(R64G64B64_FLOAT, R32G32B32_FLOAT); 1579 FORMAT_REPLACE(R64G64B64A64_FLOAT, R32G32B32A32_FLOAT); 1580 1581 FORMAT_REPLACE(R32_UNORM, R32_FLOAT); 1582 FORMAT_REPLACE(R32G32_UNORM, R32G32_FLOAT); 1583 FORMAT_REPLACE(R32G32B32_UNORM, R32G32B32_FLOAT); 1584 FORMAT_REPLACE(R32G32B32A32_UNORM, R32G32B32A32_FLOAT); 1585 1586 FORMAT_REPLACE(R32_USCALED, R32_FLOAT); 1587 FORMAT_REPLACE(R32G32_USCALED, R32G32_FLOAT); 1588 FORMAT_REPLACE(R32G32B32_USCALED, R32G32B32_FLOAT); 1589 FORMAT_REPLACE(R32G32B32A32_USCALED,R32G32B32A32_FLOAT); 1590 1591 FORMAT_REPLACE(R32_SNORM, R32_FLOAT); 1592 FORMAT_REPLACE(R32G32_SNORM, R32G32_FLOAT); 1593 FORMAT_REPLACE(R32G32B32_SNORM, R32G32B32_FLOAT); 1594 FORMAT_REPLACE(R32G32B32A32_SNORM, R32G32B32A32_FLOAT); 1595 1596 FORMAT_REPLACE(R32_SSCALED, R32_FLOAT); 1597 FORMAT_REPLACE(R32G32_SSCALED, R32G32_FLOAT); 1598 FORMAT_REPLACE(R32G32B32_SSCALED, R32G32B32_FLOAT); 1599 FORMAT_REPLACE(R32G32B32A32_SSCALED,R32G32B32A32_FLOAT); 1600 1601 FORMAT_REPLACE(R32_FIXED, R32_FLOAT); 1602 FORMAT_REPLACE(R32G32_FIXED, R32G32_FLOAT); 1603 FORMAT_REPLACE(R32G32B32_FIXED, R32G32B32_FLOAT); 1604 FORMAT_REPLACE(R32G32B32A32_FIXED, R32G32B32A32_FLOAT); 1605 1606 default:; 1607 } 1608 1609 velems->incompatible_layout = 1610 velems->incompatible_layout || 1611 velems->velem[i].src_format != velems->hw_format[i] || 1612 velems->velem[i].src_offset % 4 != 0; 1613 } 1614 1615 /* Now setup PSC. 1616 * The unused components will be replaced by (..., 0, 1). */ 1617 r300_vertex_psc(velems); 1618 1619 /* Align the formats to the size of DWORD. 1620 * We only care about the blocksizes of the formats since 1621 * swizzles are already set up. 1622 * Also compute the vertex size. */ 1623 for (i = 0; i < count; i++) { 1624 /* This is OK because we check for aligned strides too. */ 1625 velems->hw_format_size[i] = 1626 align(util_format_get_blocksize(velems->hw_format[i]), 4); 1627 velems->vertex_size_dwords += velems->hw_format_size[i] / 4; 1628 } 1629 } 1630 } 1631 return velems; 1632} 1633 1634static void r300_bind_vertex_elements_state(struct pipe_context *pipe, 1635 void *state) 1636{ 1637 struct r300_context *r300 = r300_context(pipe); 1638 struct r300_vertex_element_state *velems = state; 1639 1640 if (velems == NULL) { 1641 return; 1642 } 1643 1644 r300->velems = velems; 1645 1646 if (r300->draw) { 1647 draw_flush(r300->draw); 1648 draw_set_vertex_elements(r300->draw, velems->count, velems->velem); 1649 return; 1650 } 1651 1652 UPDATE_STATE(&velems->vertex_stream, r300->vertex_stream_state); 1653 r300->vertex_stream_state.size = (1 + velems->vertex_stream.count) * 2; 1654} 1655 1656static void r300_delete_vertex_elements_state(struct pipe_context *pipe, void *state) 1657{ 1658 FREE(state); 1659} 1660 1661static void* r300_create_vs_state(struct pipe_context* pipe, 1662 const struct pipe_shader_state* shader) 1663{ 1664 struct r300_context* r300 = r300_context(pipe); 1665 struct r300_vertex_shader* vs = CALLOC_STRUCT(r300_vertex_shader); 1666 1667 /* Copy state directly into shader. */ 1668 vs->state = *shader; 1669 vs->state.tokens = tgsi_dup_tokens(shader->tokens); 1670 1671 if (r300->screen->caps.has_tcl) { 1672 r300_init_vs_outputs(vs); 1673 r300_translate_vertex_shader(r300, vs); 1674 } else { 1675 r300_draw_init_vertex_shader(r300->draw, vs); 1676 } 1677 1678 return vs; 1679} 1680 1681static void r300_bind_vs_state(struct pipe_context* pipe, void* shader) 1682{ 1683 struct r300_context* r300 = r300_context(pipe); 1684 struct r300_vertex_shader* vs = (struct r300_vertex_shader*)shader; 1685 1686 if (vs == NULL) { 1687 r300->vs_state.state = NULL; 1688 return; 1689 } 1690 if (vs == r300->vs_state.state) { 1691 return; 1692 } 1693 r300->vs_state.state = vs; 1694 1695 /* The majority of the RS block bits is dependent on the vertex shader. */ 1696 r300->rs_block_state.dirty = TRUE; /* Will be updated before the emission. */ 1697 1698 if (r300->screen->caps.has_tcl) { 1699 r300->vs_state.dirty = TRUE; 1700 r300->vs_state.size = 1701 vs->code.length + 9 + 1702 (vs->immediates_count ? vs->immediates_count * 4 + 3 : 0); 1703 1704 if (vs->externals_count) { 1705 r300->vs_constants.dirty = TRUE; 1706 r300->vs_constants.size = vs->externals_count * 4 + 3; 1707 } else { 1708 r300->vs_constants.size = 0; 1709 } 1710 1711 r300->pvs_flush.dirty = TRUE; 1712 } else { 1713 draw_flush(r300->draw); 1714 draw_bind_vertex_shader(r300->draw, 1715 (struct draw_vertex_shader*)vs->draw_vs); 1716 } 1717} 1718 1719static void r300_delete_vs_state(struct pipe_context* pipe, void* shader) 1720{ 1721 struct r300_context* r300 = r300_context(pipe); 1722 struct r300_vertex_shader* vs = (struct r300_vertex_shader*)shader; 1723 1724 if (r300->screen->caps.has_tcl) { 1725 rc_constants_destroy(&vs->code.constants); 1726 } else { 1727 draw_delete_vertex_shader(r300->draw, 1728 (struct draw_vertex_shader*)vs->draw_vs); 1729 } 1730 1731 FREE((void*)vs->state.tokens); 1732 FREE(shader); 1733} 1734 1735static void r300_set_constant_buffer(struct pipe_context *pipe, 1736 uint shader, uint index, 1737 struct pipe_resource *buf) 1738{ 1739 struct r300_context* r300 = r300_context(pipe); 1740 struct r300_constant_buffer *cbuf; 1741 uint32_t *mapped = r300_buffer(buf)->user_buffer; 1742 int max_size = 0, max_size_bytes = 0, clamped_size = 0; 1743 1744 switch (shader) { 1745 case PIPE_SHADER_VERTEX: 1746 cbuf = (struct r300_constant_buffer*)r300->vs_constants.state; 1747 max_size = 256; 1748 break; 1749 case PIPE_SHADER_FRAGMENT: 1750 cbuf = (struct r300_constant_buffer*)r300->fs_constants.state; 1751 if (r300->screen->caps.is_r500) { 1752 max_size = 256; 1753 } else { 1754 max_size = 32; 1755 } 1756 break; 1757 default: 1758 assert(0); 1759 return; 1760 } 1761 max_size_bytes = max_size * 4 * sizeof(float); 1762 1763 if (buf == NULL || buf->width0 == 0 || 1764 (mapped = r300_buffer(buf)->constant_buffer) == NULL) { 1765 cbuf->count = 0; 1766 return; 1767 } 1768 1769 if (shader == PIPE_SHADER_FRAGMENT || 1770 (shader == PIPE_SHADER_VERTEX && r300->screen->caps.has_tcl)) { 1771 assert((buf->width0 % (4 * sizeof(float))) == 0); 1772 1773 /* Check the size of the constant buffer. */ 1774 /* XXX Subtract immediates and RC_STATE_* variables. */ 1775 if (buf->width0 > max_size_bytes) { 1776 fprintf(stderr, "r300: Max size of the constant buffer is " 1777 "%i*4 floats.\n", max_size); 1778 } 1779 1780 clamped_size = MIN2(buf->width0, max_size_bytes); 1781 cbuf->count = clamped_size / (4 * sizeof(float)); 1782 cbuf->ptr = mapped; 1783 } 1784 1785 if (shader == PIPE_SHADER_VERTEX) { 1786 if (r300->screen->caps.has_tcl) { 1787 if (r300->vs_constants.size) { 1788 r300->vs_constants.dirty = TRUE; 1789 } 1790 r300->pvs_flush.dirty = TRUE; 1791 } else if (r300->draw) { 1792 draw_set_mapped_constant_buffer(r300->draw, PIPE_SHADER_VERTEX, 1793 0, mapped, buf->width0); 1794 } 1795 } else if (shader == PIPE_SHADER_FRAGMENT) { 1796 r300->fs_constants.dirty = TRUE; 1797 } 1798} 1799 1800void r300_init_state_functions(struct r300_context* r300) 1801{ 1802 r300->context.create_blend_state = r300_create_blend_state; 1803 r300->context.bind_blend_state = r300_bind_blend_state; 1804 r300->context.delete_blend_state = r300_delete_blend_state; 1805 1806 r300->context.set_blend_color = r300_set_blend_color; 1807 1808 r300->context.set_clip_state = r300_set_clip_state; 1809 r300->context.set_sample_mask = r300_set_sample_mask; 1810 1811 r300->context.set_constant_buffer = r300_set_constant_buffer; 1812 1813 r300->context.create_depth_stencil_alpha_state = r300_create_dsa_state; 1814 r300->context.bind_depth_stencil_alpha_state = r300_bind_dsa_state; 1815 r300->context.delete_depth_stencil_alpha_state = r300_delete_dsa_state; 1816 1817 r300->context.set_stencil_ref = r300_set_stencil_ref; 1818 1819 r300->context.set_framebuffer_state = r300_set_framebuffer_state; 1820 1821 r300->context.create_fs_state = r300_create_fs_state; 1822 r300->context.bind_fs_state = r300_bind_fs_state; 1823 r300->context.delete_fs_state = r300_delete_fs_state; 1824 1825 r300->context.set_polygon_stipple = r300_set_polygon_stipple; 1826 1827 r300->context.create_rasterizer_state = r300_create_rs_state; 1828 r300->context.bind_rasterizer_state = r300_bind_rs_state; 1829 r300->context.delete_rasterizer_state = r300_delete_rs_state; 1830 1831 r300->context.create_sampler_state = r300_create_sampler_state; 1832 r300->context.bind_fragment_sampler_states = r300_bind_sampler_states; 1833 r300->context.bind_vertex_sampler_states = r300_lacks_vertex_textures; 1834 r300->context.delete_sampler_state = r300_delete_sampler_state; 1835 1836 r300->context.set_fragment_sampler_views = r300_set_fragment_sampler_views; 1837 r300->context.create_sampler_view = r300_create_sampler_view; 1838 r300->context.sampler_view_destroy = r300_sampler_view_destroy; 1839 1840 r300->context.set_scissor_state = r300_set_scissor_state; 1841 1842 r300->context.set_viewport_state = r300_set_viewport_state; 1843 1844 r300->context.set_vertex_buffers = r300_set_vertex_buffers; 1845 1846 r300->context.create_vertex_elements_state = r300_create_vertex_elements_state; 1847 r300->context.bind_vertex_elements_state = r300_bind_vertex_elements_state; 1848 r300->context.delete_vertex_elements_state = r300_delete_vertex_elements_state; 1849 1850 r300->context.create_vs_state = r300_create_vs_state; 1851 r300->context.bind_vs_state = r300_bind_vs_state; 1852 r300->context.delete_vs_state = r300_delete_vs_state; 1853} 1854