r300_state.c revision 57438adf3217955f16491ef8deeffafe05c2f7f8
1/* 2 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com> 3 * Copyright 2009 Marek Olšák <maraeo@gmail.com> 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * on the rights to use, copy, modify, merge, publish, distribute, sub 9 * license, and/or sell copies of the Software, and to permit persons to whom 10 * the Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, 20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 22 * USE OR OTHER DEALINGS IN THE SOFTWARE. */ 23 24#include "draw/draw_context.h" 25 26#include "util/u_blitter.h" 27#include "util/u_math.h" 28#include "util/u_memory.h" 29#include "util/u_pack_color.h" 30 31#include "tgsi/tgsi_parse.h" 32 33#include "pipe/p_config.h" 34 35#include "r300_cb.h" 36#include "r300_context.h" 37#include "r300_emit.h" 38#include "r300_reg.h" 39#include "r300_screen.h" 40#include "r300_screen_buffer.h" 41#include "r300_state_inlines.h" 42#include "r300_fs.h" 43#include "r300_texture.h" 44#include "r300_vs.h" 45#include "r300_winsys.h" 46 47/* r300_state: Functions used to intialize state context by translating 48 * Gallium state objects into semi-native r300 state objects. */ 49 50#define UPDATE_STATE(cso, atom) \ 51 if (cso != atom.state) { \ 52 atom.state = cso; \ 53 atom.dirty = TRUE; \ 54 } 55 56static boolean blend_discard_if_src_alpha_0(unsigned srcRGB, unsigned srcA, 57 unsigned dstRGB, unsigned dstA) 58{ 59 /* If the blend equation is ADD or REVERSE_SUBTRACT, 60 * SRC_ALPHA == 0, and the following state is set, the colorbuffer 61 * will not be changed. 62 * Notice that the dst factors are the src factors inverted. */ 63 return (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA || 64 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE || 65 srcRGB == PIPE_BLENDFACTOR_ZERO) && 66 (srcA == PIPE_BLENDFACTOR_SRC_COLOR || 67 srcA == PIPE_BLENDFACTOR_SRC_ALPHA || 68 srcA == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE || 69 srcA == PIPE_BLENDFACTOR_ZERO) && 70 (dstRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA || 71 dstRGB == PIPE_BLENDFACTOR_ONE) && 72 (dstA == PIPE_BLENDFACTOR_INV_SRC_COLOR || 73 dstA == PIPE_BLENDFACTOR_INV_SRC_ALPHA || 74 dstA == PIPE_BLENDFACTOR_ONE); 75} 76 77static boolean blend_discard_if_src_alpha_1(unsigned srcRGB, unsigned srcA, 78 unsigned dstRGB, unsigned dstA) 79{ 80 /* If the blend equation is ADD or REVERSE_SUBTRACT, 81 * SRC_ALPHA == 1, and the following state is set, the colorbuffer 82 * will not be changed. 83 * Notice that the dst factors are the src factors inverted. */ 84 return (srcRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA || 85 srcRGB == PIPE_BLENDFACTOR_ZERO) && 86 (srcA == PIPE_BLENDFACTOR_INV_SRC_COLOR || 87 srcA == PIPE_BLENDFACTOR_INV_SRC_ALPHA || 88 srcA == PIPE_BLENDFACTOR_ZERO) && 89 (dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA || 90 dstRGB == PIPE_BLENDFACTOR_ONE) && 91 (dstA == PIPE_BLENDFACTOR_SRC_COLOR || 92 dstA == PIPE_BLENDFACTOR_SRC_ALPHA || 93 dstA == PIPE_BLENDFACTOR_ONE); 94} 95 96static boolean blend_discard_if_src_color_0(unsigned srcRGB, unsigned srcA, 97 unsigned dstRGB, unsigned dstA) 98{ 99 /* If the blend equation is ADD or REVERSE_SUBTRACT, 100 * SRC_COLOR == (0,0,0), and the following state is set, the colorbuffer 101 * will not be changed. 102 * Notice that the dst factors are the src factors inverted. */ 103 return (srcRGB == PIPE_BLENDFACTOR_SRC_COLOR || 104 srcRGB == PIPE_BLENDFACTOR_ZERO) && 105 (srcA == PIPE_BLENDFACTOR_ZERO) && 106 (dstRGB == PIPE_BLENDFACTOR_INV_SRC_COLOR || 107 dstRGB == PIPE_BLENDFACTOR_ONE) && 108 (dstA == PIPE_BLENDFACTOR_ONE); 109} 110 111static boolean blend_discard_if_src_color_1(unsigned srcRGB, unsigned srcA, 112 unsigned dstRGB, unsigned dstA) 113{ 114 /* If the blend equation is ADD or REVERSE_SUBTRACT, 115 * SRC_COLOR == (1,1,1), and the following state is set, the colorbuffer 116 * will not be changed. 117 * Notice that the dst factors are the src factors inverted. */ 118 return (srcRGB == PIPE_BLENDFACTOR_INV_SRC_COLOR || 119 srcRGB == PIPE_BLENDFACTOR_ZERO) && 120 (srcA == PIPE_BLENDFACTOR_ZERO) && 121 (dstRGB == PIPE_BLENDFACTOR_SRC_COLOR || 122 dstRGB == PIPE_BLENDFACTOR_ONE) && 123 (dstA == PIPE_BLENDFACTOR_ONE); 124} 125 126static boolean blend_discard_if_src_alpha_color_0(unsigned srcRGB, unsigned srcA, 127 unsigned dstRGB, unsigned dstA) 128{ 129 /* If the blend equation is ADD or REVERSE_SUBTRACT, 130 * SRC_ALPHA_COLOR == (0,0,0,0), and the following state is set, 131 * the colorbuffer will not be changed. 132 * Notice that the dst factors are the src factors inverted. */ 133 return (srcRGB == PIPE_BLENDFACTOR_SRC_COLOR || 134 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA || 135 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE || 136 srcRGB == PIPE_BLENDFACTOR_ZERO) && 137 (srcA == PIPE_BLENDFACTOR_SRC_COLOR || 138 srcA == PIPE_BLENDFACTOR_SRC_ALPHA || 139 srcA == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE || 140 srcA == PIPE_BLENDFACTOR_ZERO) && 141 (dstRGB == PIPE_BLENDFACTOR_INV_SRC_COLOR || 142 dstRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA || 143 dstRGB == PIPE_BLENDFACTOR_ONE) && 144 (dstA == PIPE_BLENDFACTOR_INV_SRC_COLOR || 145 dstA == PIPE_BLENDFACTOR_INV_SRC_ALPHA || 146 dstA == PIPE_BLENDFACTOR_ONE); 147} 148 149static boolean blend_discard_if_src_alpha_color_1(unsigned srcRGB, unsigned srcA, 150 unsigned dstRGB, unsigned dstA) 151{ 152 /* If the blend equation is ADD or REVERSE_SUBTRACT, 153 * SRC_ALPHA_COLOR == (1,1,1,1), and the following state is set, 154 * the colorbuffer will not be changed. 155 * Notice that the dst factors are the src factors inverted. */ 156 return (srcRGB == PIPE_BLENDFACTOR_INV_SRC_COLOR || 157 srcRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA || 158 srcRGB == PIPE_BLENDFACTOR_ZERO) && 159 (srcA == PIPE_BLENDFACTOR_INV_SRC_COLOR || 160 srcA == PIPE_BLENDFACTOR_INV_SRC_ALPHA || 161 srcA == PIPE_BLENDFACTOR_ZERO) && 162 (dstRGB == PIPE_BLENDFACTOR_SRC_COLOR || 163 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA || 164 dstRGB == PIPE_BLENDFACTOR_ONE) && 165 (dstA == PIPE_BLENDFACTOR_SRC_COLOR || 166 dstA == PIPE_BLENDFACTOR_SRC_ALPHA || 167 dstA == PIPE_BLENDFACTOR_ONE); 168} 169 170static unsigned bgra_cmask(unsigned mask) 171{ 172 /* Gallium uses RGBA color ordering while R300 expects BGRA. */ 173 174 return ((mask & PIPE_MASK_R) << 2) | 175 ((mask & PIPE_MASK_B) >> 2) | 176 (mask & (PIPE_MASK_G | PIPE_MASK_A)); 177} 178 179/* Create a new blend state based on the CSO blend state. 180 * 181 * This encompasses alpha blending, logic/raster ops, and blend dithering. */ 182static void* r300_create_blend_state(struct pipe_context* pipe, 183 const struct pipe_blend_state* state) 184{ 185 struct r300_screen* r300screen = r300_screen(pipe->screen); 186 struct r300_blend_state* blend = CALLOC_STRUCT(r300_blend_state); 187 uint32_t blend_control = 0; /* R300_RB3D_CBLEND: 0x4e04 */ 188 uint32_t alpha_blend_control = 0; /* R300_RB3D_ABLEND: 0x4e08 */ 189 uint32_t color_channel_mask = 0; /* R300_RB3D_COLOR_CHANNEL_MASK: 0x4e0c */ 190 uint32_t rop = 0; /* R300_RB3D_ROPCNTL: 0x4e18 */ 191 uint32_t dither = 0; /* R300_RB3D_DITHER_CTL: 0x4e50 */ 192 CB_LOCALS; 193 194 if (state->rt[0].blend_enable) 195 { 196 unsigned eqRGB = state->rt[0].rgb_func; 197 unsigned srcRGB = state->rt[0].rgb_src_factor; 198 unsigned dstRGB = state->rt[0].rgb_dst_factor; 199 200 unsigned eqA = state->rt[0].alpha_func; 201 unsigned srcA = state->rt[0].alpha_src_factor; 202 unsigned dstA = state->rt[0].alpha_dst_factor; 203 204 /* despite the name, ALPHA_BLEND_ENABLE has nothing to do with alpha, 205 * this is just the crappy D3D naming */ 206 blend_control = R300_ALPHA_BLEND_ENABLE | 207 r300_translate_blend_function(eqRGB) | 208 ( r300_translate_blend_factor(srcRGB) << R300_SRC_BLEND_SHIFT) | 209 ( r300_translate_blend_factor(dstRGB) << R300_DST_BLEND_SHIFT); 210 211 /* Optimization: some operations do not require the destination color. 212 * 213 * When SRC_ALPHA_SATURATE is used, colorbuffer reads must be enabled, 214 * otherwise blending gives incorrect results. It seems to be 215 * a hardware bug. */ 216 if (eqRGB == PIPE_BLEND_MIN || eqA == PIPE_BLEND_MIN || 217 eqRGB == PIPE_BLEND_MAX || eqA == PIPE_BLEND_MAX || 218 dstRGB != PIPE_BLENDFACTOR_ZERO || 219 dstA != PIPE_BLENDFACTOR_ZERO || 220 srcRGB == PIPE_BLENDFACTOR_DST_COLOR || 221 srcRGB == PIPE_BLENDFACTOR_DST_ALPHA || 222 srcRGB == PIPE_BLENDFACTOR_INV_DST_COLOR || 223 srcRGB == PIPE_BLENDFACTOR_INV_DST_ALPHA || 224 srcA == PIPE_BLENDFACTOR_DST_COLOR || 225 srcA == PIPE_BLENDFACTOR_DST_ALPHA || 226 srcA == PIPE_BLENDFACTOR_INV_DST_COLOR || 227 srcA == PIPE_BLENDFACTOR_INV_DST_ALPHA || 228 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE) { 229 /* Enable reading from the colorbuffer. */ 230 blend_control |= R300_READ_ENABLE; 231 232 if (r300screen->caps.is_r500) { 233 /* Optimization: Depending on incoming pixels, we can 234 * conditionally disable the reading in hardware... */ 235 if (eqRGB != PIPE_BLEND_MIN && eqA != PIPE_BLEND_MIN && 236 eqRGB != PIPE_BLEND_MAX && eqA != PIPE_BLEND_MAX) { 237 /* Disable reading if SRC_ALPHA == 0. */ 238 if ((dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA || 239 dstRGB == PIPE_BLENDFACTOR_ZERO) && 240 (dstA == PIPE_BLENDFACTOR_SRC_COLOR || 241 dstA == PIPE_BLENDFACTOR_SRC_ALPHA || 242 dstA == PIPE_BLENDFACTOR_ZERO)) { 243 blend_control |= R500_SRC_ALPHA_0_NO_READ; 244 } 245 246 /* Disable reading if SRC_ALPHA == 1. */ 247 if ((dstRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA || 248 dstRGB == PIPE_BLENDFACTOR_ZERO) && 249 (dstA == PIPE_BLENDFACTOR_INV_SRC_COLOR || 250 dstA == PIPE_BLENDFACTOR_INV_SRC_ALPHA || 251 dstA == PIPE_BLENDFACTOR_ZERO)) { 252 blend_control |= R500_SRC_ALPHA_1_NO_READ; 253 } 254 } 255 } 256 } 257 258 /* Optimization: discard pixels which don't change the colorbuffer. 259 * 260 * The code below is non-trivial and some math is involved. 261 * 262 * Discarding pixels must be disabled when FP16 AA is enabled. 263 * This is a hardware bug. Also, this implementation wouldn't work 264 * with FP blending enabled and equation clamping disabled. 265 * 266 * Equations other than ADD are rarely used and therefore won't be 267 * optimized. */ 268 if ((eqRGB == PIPE_BLEND_ADD || eqRGB == PIPE_BLEND_REVERSE_SUBTRACT) && 269 (eqA == PIPE_BLEND_ADD || eqA == PIPE_BLEND_REVERSE_SUBTRACT)) { 270 /* ADD: X+Y 271 * REVERSE_SUBTRACT: Y-X 272 * 273 * The idea is: 274 * If X = src*srcFactor = 0 and Y = dst*dstFactor = 1, 275 * then CB will not be changed. 276 * 277 * Given the srcFactor and dstFactor variables, we can derive 278 * what src and dst should be equal to and discard appropriate 279 * pixels. 280 */ 281 if (blend_discard_if_src_alpha_0(srcRGB, srcA, dstRGB, dstA)) { 282 blend_control |= R300_DISCARD_SRC_PIXELS_SRC_ALPHA_0; 283 } else if (blend_discard_if_src_alpha_1(srcRGB, srcA, 284 dstRGB, dstA)) { 285 blend_control |= R300_DISCARD_SRC_PIXELS_SRC_ALPHA_1; 286 } else if (blend_discard_if_src_color_0(srcRGB, srcA, 287 dstRGB, dstA)) { 288 blend_control |= R300_DISCARD_SRC_PIXELS_SRC_COLOR_0; 289 } else if (blend_discard_if_src_color_1(srcRGB, srcA, 290 dstRGB, dstA)) { 291 blend_control |= R300_DISCARD_SRC_PIXELS_SRC_COLOR_1; 292 } else if (blend_discard_if_src_alpha_color_0(srcRGB, srcA, 293 dstRGB, dstA)) { 294 blend_control |= 295 R300_DISCARD_SRC_PIXELS_SRC_ALPHA_COLOR_0; 296 } else if (blend_discard_if_src_alpha_color_1(srcRGB, srcA, 297 dstRGB, dstA)) { 298 blend_control |= 299 R300_DISCARD_SRC_PIXELS_SRC_ALPHA_COLOR_1; 300 } 301 } 302 303 /* separate alpha */ 304 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) { 305 blend_control |= R300_SEPARATE_ALPHA_ENABLE; 306 alpha_blend_control = 307 r300_translate_blend_function(eqA) | 308 (r300_translate_blend_factor(srcA) << R300_SRC_BLEND_SHIFT) | 309 (r300_translate_blend_factor(dstA) << R300_DST_BLEND_SHIFT); 310 } 311 } 312 313 /* PIPE_LOGICOP_* don't need to be translated, fortunately. */ 314 if (state->logicop_enable) { 315 rop = R300_RB3D_ROPCNTL_ROP_ENABLE | 316 (state->logicop_func) << R300_RB3D_ROPCNTL_ROP_SHIFT; 317 } 318 319 /* Color channel masks for all MRTs. */ 320 color_channel_mask = bgra_cmask(state->rt[0].colormask); 321 if (r300screen->caps.is_r500 && state->independent_blend_enable) { 322 if (state->rt[1].blend_enable) { 323 color_channel_mask |= bgra_cmask(state->rt[1].colormask) << 4; 324 } 325 if (state->rt[2].blend_enable) { 326 color_channel_mask |= bgra_cmask(state->rt[2].colormask) << 8; 327 } 328 if (state->rt[3].blend_enable) { 329 color_channel_mask |= bgra_cmask(state->rt[3].colormask) << 12; 330 } 331 } 332 333 /* Neither fglrx nor classic r300 ever set this, regardless of dithering 334 * state. Since it's an optional implementation detail, we can leave it 335 * out and never dither. 336 * 337 * This could be revisited if we ever get quality or conformance hints. 338 * 339 if (state->dither) { 340 dither = R300_RB3D_DITHER_CTL_DITHER_MODE_LUT | 341 R300_RB3D_DITHER_CTL_ALPHA_DITHER_MODE_LUT; 342 } 343 */ 344 345 /* Build a command buffer. */ 346 BEGIN_CB(blend->cb, 8); 347 OUT_CB_REG(R300_RB3D_ROPCNTL, rop); 348 OUT_CB_REG_SEQ(R300_RB3D_CBLEND, 3); 349 OUT_CB(blend_control); 350 OUT_CB(alpha_blend_control); 351 OUT_CB(color_channel_mask); 352 OUT_CB_REG(R300_RB3D_DITHER_CTL, dither); 353 END_CB; 354 355 /* The same as above, but with no colorbuffer reads and writes. */ 356 BEGIN_CB(blend->cb_no_readwrite, 8); 357 OUT_CB_REG(R300_RB3D_ROPCNTL, rop); 358 OUT_CB_REG_SEQ(R300_RB3D_CBLEND, 3); 359 OUT_CB(0); 360 OUT_CB(0); 361 OUT_CB(0); 362 OUT_CB_REG(R300_RB3D_DITHER_CTL, dither); 363 END_CB; 364 365 return (void*)blend; 366} 367 368/* Bind blend state. */ 369static void r300_bind_blend_state(struct pipe_context* pipe, 370 void* state) 371{ 372 struct r300_context* r300 = r300_context(pipe); 373 374 UPDATE_STATE(state, r300->blend_state); 375} 376 377/* Free blend state. */ 378static void r300_delete_blend_state(struct pipe_context* pipe, 379 void* state) 380{ 381 FREE(state); 382} 383 384/* Convert float to 10bit integer */ 385static unsigned float_to_fixed10(float f) 386{ 387 return CLAMP((unsigned)(f * 1023.9f), 0, 1023); 388} 389 390/* Set blend color. 391 * Setup both R300 and R500 registers, figure out later which one to write. */ 392static void r300_set_blend_color(struct pipe_context* pipe, 393 const struct pipe_blend_color* color) 394{ 395 struct r300_context* r300 = r300_context(pipe); 396 struct r300_blend_color_state* state = 397 (struct r300_blend_color_state*)r300->blend_color_state.state; 398 CB_LOCALS; 399 400 if (r300->screen->caps.is_r500) { 401 /* XXX if FP16 blending is enabled, we should use the FP16 format */ 402 BEGIN_CB(state->cb, 3); 403 OUT_CB_REG_SEQ(R500_RB3D_CONSTANT_COLOR_AR, 2); 404 OUT_CB(float_to_fixed10(color->color[0]) | 405 (float_to_fixed10(color->color[3]) << 16)); 406 OUT_CB(float_to_fixed10(color->color[2]) | 407 (float_to_fixed10(color->color[1]) << 16)); 408 END_CB; 409 } else { 410 union util_color uc; 411 util_pack_color(color->color, PIPE_FORMAT_B8G8R8A8_UNORM, &uc); 412 413 BEGIN_CB(state->cb, 2); 414 OUT_CB_REG(R300_RB3D_BLEND_COLOR, uc.ui); 415 END_CB; 416 } 417 418 r300->blend_color_state.dirty = TRUE; 419} 420 421static void r300_set_clip_state(struct pipe_context* pipe, 422 const struct pipe_clip_state* state) 423{ 424 struct r300_context* r300 = r300_context(pipe); 425 struct r300_clip_state *clip = 426 (struct r300_clip_state*)r300->clip_state.state; 427 CB_LOCALS; 428 429 clip->clip = *state; 430 431 if (r300->screen->caps.has_tcl) { 432 r300->clip_state.size = 2 + !!state->nr * 3 + state->nr * 4; 433 434 BEGIN_CB(clip->cb, r300->clip_state.size); 435 if (state->nr) { 436 OUT_CB_REG(R300_VAP_PVS_VECTOR_INDX_REG, 437 (r300->screen->caps.is_r500 ? 438 R500_PVS_UCP_START : R300_PVS_UCP_START)); 439 OUT_CB_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, state->nr * 4); 440 OUT_CB_TABLE(state->ucp, state->nr * 4); 441 } 442 OUT_CB_REG(R300_VAP_CLIP_CNTL, ((1 << state->nr) - 1) | 443 R300_PS_UCP_MODE_CLIP_AS_TRIFAN | 444 (state->depth_clamp ? R300_CLIP_DISABLE : 0)); 445 END_CB; 446 447 r300->clip_state.dirty = TRUE; 448 } else { 449 draw_set_clip_state(r300->draw, state); 450 } 451} 452 453static void 454r300_set_sample_mask(struct pipe_context *pipe, 455 unsigned sample_mask) 456{ 457} 458 459 460/* Create a new depth, stencil, and alpha state based on the CSO dsa state. 461 * 462 * This contains the depth buffer, stencil buffer, alpha test, and such. 463 * On the Radeon, depth and stencil buffer setup are intertwined, which is 464 * the reason for some of the strange-looking assignments across registers. */ 465static void* 466 r300_create_dsa_state(struct pipe_context* pipe, 467 const struct pipe_depth_stencil_alpha_state* state) 468{ 469 struct r300_capabilities *caps = &r300_screen(pipe->screen)->caps; 470 struct r300_dsa_state* dsa = CALLOC_STRUCT(r300_dsa_state); 471 CB_LOCALS; 472 473 dsa->dsa = *state; 474 475 /* Depth test setup. */ 476 if (state->depth.enabled) { 477 dsa->z_buffer_control |= R300_Z_ENABLE; 478 479 if (state->depth.writemask) { 480 dsa->z_buffer_control |= R300_Z_WRITE_ENABLE; 481 } 482 483 dsa->z_stencil_control |= 484 (r300_translate_depth_stencil_function(state->depth.func) << 485 R300_Z_FUNC_SHIFT); 486 } 487 488 /* Stencil buffer setup. */ 489 if (state->stencil[0].enabled) { 490 dsa->z_buffer_control |= R300_STENCIL_ENABLE; 491 dsa->z_stencil_control |= 492 (r300_translate_depth_stencil_function(state->stencil[0].func) << 493 R300_S_FRONT_FUNC_SHIFT) | 494 (r300_translate_stencil_op(state->stencil[0].fail_op) << 495 R300_S_FRONT_SFAIL_OP_SHIFT) | 496 (r300_translate_stencil_op(state->stencil[0].zpass_op) << 497 R300_S_FRONT_ZPASS_OP_SHIFT) | 498 (r300_translate_stencil_op(state->stencil[0].zfail_op) << 499 R300_S_FRONT_ZFAIL_OP_SHIFT); 500 501 dsa->stencil_ref_mask = 502 (state->stencil[0].valuemask << R300_STENCILMASK_SHIFT) | 503 (state->stencil[0].writemask << R300_STENCILWRITEMASK_SHIFT); 504 505 if (state->stencil[1].enabled) { 506 dsa->two_sided = TRUE; 507 508 dsa->z_buffer_control |= R300_STENCIL_FRONT_BACK; 509 dsa->z_stencil_control |= 510 (r300_translate_depth_stencil_function(state->stencil[1].func) << 511 R300_S_BACK_FUNC_SHIFT) | 512 (r300_translate_stencil_op(state->stencil[1].fail_op) << 513 R300_S_BACK_SFAIL_OP_SHIFT) | 514 (r300_translate_stencil_op(state->stencil[1].zpass_op) << 515 R300_S_BACK_ZPASS_OP_SHIFT) | 516 (r300_translate_stencil_op(state->stencil[1].zfail_op) << 517 R300_S_BACK_ZFAIL_OP_SHIFT); 518 519 dsa->stencil_ref_bf = 520 (state->stencil[1].valuemask << R300_STENCILMASK_SHIFT) | 521 (state->stencil[1].writemask << R300_STENCILWRITEMASK_SHIFT); 522 523 if (caps->is_r500) { 524 dsa->z_buffer_control |= R500_STENCIL_REFMASK_FRONT_BACK; 525 } else { 526 dsa->two_sided_stencil_ref = 527 (state->stencil[0].valuemask != state->stencil[1].valuemask || 528 state->stencil[0].writemask != state->stencil[1].writemask); 529 } 530 } 531 } 532 533 /* Alpha test setup. */ 534 if (state->alpha.enabled) { 535 dsa->alpha_function = 536 r300_translate_alpha_function(state->alpha.func) | 537 R300_FG_ALPHA_FUNC_ENABLE; 538 539 /* We could use 10bit alpha ref but who needs that? */ 540 dsa->alpha_function |= float_to_ubyte(state->alpha.ref_value); 541 542 if (caps->is_r500) 543 dsa->alpha_function |= R500_FG_ALPHA_FUNC_8BIT; 544 } 545 546 BEGIN_CB(&dsa->cb_begin, 8); 547 OUT_CB_REG(R300_FG_ALPHA_FUNC, dsa->alpha_function); 548 OUT_CB_REG_SEQ(R300_ZB_CNTL, 3); 549 OUT_CB(dsa->z_buffer_control); 550 OUT_CB(dsa->z_stencil_control); 551 OUT_CB(dsa->stencil_ref_mask); 552 OUT_CB_REG(R500_ZB_STENCILREFMASK_BF, dsa->stencil_ref_bf); 553 END_CB; 554 555 BEGIN_CB(dsa->cb_no_readwrite, 8); 556 OUT_CB_REG(R300_FG_ALPHA_FUNC, dsa->alpha_function); 557 OUT_CB_REG_SEQ(R300_ZB_CNTL, 3); 558 OUT_CB(0); 559 OUT_CB(0); 560 OUT_CB(0); 561 OUT_CB_REG(R500_ZB_STENCILREFMASK_BF, 0); 562 END_CB; 563 564 return (void*)dsa; 565} 566 567static void r300_dsa_inject_stencilref(struct r300_context *r300) 568{ 569 struct r300_dsa_state *dsa = 570 (struct r300_dsa_state*)r300->dsa_state.state; 571 572 if (!dsa) 573 return; 574 575 dsa->stencil_ref_mask = 576 (dsa->stencil_ref_mask & ~R300_STENCILREF_MASK) | 577 r300->stencil_ref.ref_value[0]; 578 dsa->stencil_ref_bf = 579 (dsa->stencil_ref_bf & ~R300_STENCILREF_MASK) | 580 r300->stencil_ref.ref_value[1]; 581} 582 583/* Bind DSA state. */ 584static void r300_bind_dsa_state(struct pipe_context* pipe, 585 void* state) 586{ 587 struct r300_context* r300 = r300_context(pipe); 588 589 if (!state) { 590 return; 591 } 592 593 UPDATE_STATE(state, r300->dsa_state); 594 595 r300_dsa_inject_stencilref(r300); 596} 597 598/* Free DSA state. */ 599static void r300_delete_dsa_state(struct pipe_context* pipe, 600 void* state) 601{ 602 FREE(state); 603} 604 605static void r300_set_stencil_ref(struct pipe_context* pipe, 606 const struct pipe_stencil_ref* sr) 607{ 608 struct r300_context* r300 = r300_context(pipe); 609 610 r300->stencil_ref = *sr; 611 612 r300_dsa_inject_stencilref(r300); 613 r300->dsa_state.dirty = TRUE; 614} 615 616static void r300_tex_set_tiling_flags(struct r300_context *r300, 617 struct r300_texture *tex, unsigned level) 618{ 619 /* Check if the macrotile flag needs to be changed. 620 * Skip changing the flags otherwise. */ 621 if (tex->desc.macrotile[tex->surface_level] != 622 tex->desc.macrotile[level]) { 623 /* Tiling determines how DRM treats the buffer data. 624 * We must flush CS when changing it if the buffer is referenced. */ 625 if (r300->rws->cs_is_buffer_referenced(r300->cs, 626 tex->buffer, R300_REF_CS)) 627 r300->context.flush(&r300->context, 0, NULL); 628 629 r300->rws->buffer_set_tiling(r300->rws, tex->buffer, 630 tex->desc.microtile, tex->desc.macrotile[level], 631 tex->desc.stride_in_bytes[0]); 632 633 tex->surface_level = level; 634 } 635} 636 637/* This switcheroo is needed just because of goddamned MACRO_SWITCH. */ 638static void r300_fb_set_tiling_flags(struct r300_context *r300, 639 const struct pipe_framebuffer_state *state) 640{ 641 unsigned i; 642 643 /* Set tiling flags for new surfaces. */ 644 for (i = 0; i < state->nr_cbufs; i++) { 645 r300_tex_set_tiling_flags(r300, 646 r300_texture(state->cbufs[i]->texture), 647 state->cbufs[i]->level); 648 } 649 if (state->zsbuf) { 650 r300_tex_set_tiling_flags(r300, 651 r300_texture(state->zsbuf->texture), 652 state->zsbuf->level); 653 } 654} 655 656static void r300_print_fb_surf_info(struct pipe_surface *surf, unsigned index, 657 const char *binding) 658{ 659 struct pipe_resource *tex = surf->texture; 660 struct r300_texture *rtex = r300_texture(tex); 661 662 fprintf(stderr, 663 "r300: %s[%i] Dim: %ix%i, Offset: %i, ZSlice: %i, " 664 "Face: %i, Level: %i, Format: %s\n" 665 666 "r300: TEX: Macro: %s, Micro: %s, Pitch: %i, " 667 "Dim: %ix%ix%i, LastLevel: %i, Format: %s\n", 668 669 binding, index, surf->width, surf->height, surf->offset, 670 surf->zslice, surf->face, surf->level, 671 util_format_short_name(surf->format), 672 673 rtex->desc.macrotile[0] ? "YES" : " NO", 674 rtex->desc.microtile ? "YES" : " NO", 675 rtex->desc.stride_in_pixels[0], 676 tex->width0, tex->height0, tex->depth0, 677 tex->last_level, util_format_short_name(tex->format)); 678} 679 680void r300_mark_fb_state_dirty(struct r300_context *r300, 681 enum r300_fb_state_change change) 682{ 683 struct pipe_framebuffer_state *state = r300->fb_state.state; 684 685 /* What is marked as dirty depends on the enum r300_fb_state_change. */ 686 r300->gpu_flush.dirty = TRUE; 687 r300->fb_state.dirty = TRUE; 688 r300->hyperz_state.dirty = TRUE; 689 690 if (change == R300_CHANGED_FB_STATE) { 691 r300->aa_state.dirty = TRUE; 692 r300->fb_state_pipelined.dirty = TRUE; 693 } 694 695 /* Now compute the fb_state atom size. */ 696 r300->fb_state.size = 2 + (8 * state->nr_cbufs); 697 698 if (r300->cbzb_clear) 699 r300->fb_state.size += 10; 700 else if (state->zsbuf) 701 r300->fb_state.size += r300->screen->caps.has_hiz ? 18 : 14; 702 703 /* The size of the rest of atoms stays the same. */ 704} 705 706static void 707 r300_set_framebuffer_state(struct pipe_context* pipe, 708 const struct pipe_framebuffer_state* state) 709{ 710 struct r300_context* r300 = r300_context(pipe); 711 struct r300_aa_state *aa = (struct r300_aa_state*)r300->aa_state.state; 712 struct pipe_framebuffer_state *old_state = r300->fb_state.state; 713 unsigned max_width, max_height, i; 714 uint32_t zbuffer_bpp = 0; 715 716 if (r300->screen->caps.is_r500) { 717 max_width = max_height = 4096; 718 } else if (r300->screen->caps.is_r400) { 719 max_width = max_height = 4021; 720 } else { 721 max_width = max_height = 2560; 722 } 723 724 if (state->width > max_width || state->height > max_height) { 725 fprintf(stderr, "r300: Implementation error: Render targets are too " 726 "big in %s, refusing to bind framebuffer state!\n", __FUNCTION__); 727 return; 728 } 729 730 /* If nr_cbufs is changed from zero to non-zero or vice versa... */ 731 if (!!old_state->nr_cbufs != !!state->nr_cbufs) { 732 r300->blend_state.dirty = TRUE; 733 } 734 /* If zsbuf is set from NULL to non-NULL or vice versa.. */ 735 if (!!old_state->zsbuf != !!state->zsbuf) { 736 r300->dsa_state.dirty = TRUE; 737 } 738 739 /* The tiling flags are dependent on the surface miplevel, unfortunately. */ 740 r300_fb_set_tiling_flags(r300, state); 741 742 util_assign_framebuffer_state(r300->fb_state.state, state); 743 744 r300_mark_fb_state_dirty(r300, R300_CHANGED_FB_STATE); 745 746 /* Polygon offset depends on the zbuffer bit depth. */ 747 if (state->zsbuf) { 748 switch (util_format_get_blocksize(state->zsbuf->texture->format)) { 749 case 2: 750 zbuffer_bpp = 16; 751 break; 752 case 4: 753 zbuffer_bpp = 24; 754 break; 755 } 756 757 if (r300->zbuffer_bpp != zbuffer_bpp) { 758 r300->zbuffer_bpp = zbuffer_bpp; 759 760 if (r300->polygon_offset_enabled) 761 r300->rs_state.dirty = TRUE; 762 } 763 } 764 765 /* Set up AA config. */ 766 if (r300->rws->get_value(r300->rws, R300_VID_DRM_2_3_0)) { 767 if (state->nr_cbufs && state->cbufs[0]->texture->nr_samples > 1) { 768 aa->aa_config = R300_GB_AA_CONFIG_AA_ENABLE; 769 770 switch (state->cbufs[0]->texture->nr_samples) { 771 case 2: 772 aa->aa_config |= R300_GB_AA_CONFIG_NUM_AA_SUBSAMPLES_2; 773 break; 774 case 3: 775 aa->aa_config |= R300_GB_AA_CONFIG_NUM_AA_SUBSAMPLES_3; 776 break; 777 case 4: 778 aa->aa_config |= R300_GB_AA_CONFIG_NUM_AA_SUBSAMPLES_4; 779 break; 780 case 6: 781 aa->aa_config |= R300_GB_AA_CONFIG_NUM_AA_SUBSAMPLES_6; 782 break; 783 } 784 } else { 785 aa->aa_config = 0; 786 } 787 } 788 789 if (DBG_ON(r300, DBG_FB)) { 790 fprintf(stderr, "r300: set_framebuffer_state:\n"); 791 for (i = 0; i < state->nr_cbufs; i++) { 792 r300_print_fb_surf_info(state->cbufs[i], i, "CB"); 793 } 794 if (state->zsbuf) { 795 r300_print_fb_surf_info(state->zsbuf, 0, "ZB"); 796 } 797 } 798} 799 800/* Create fragment shader state. */ 801static void* r300_create_fs_state(struct pipe_context* pipe, 802 const struct pipe_shader_state* shader) 803{ 804 struct r300_fragment_shader* fs = NULL; 805 806 fs = (struct r300_fragment_shader*)CALLOC_STRUCT(r300_fragment_shader); 807 808 /* Copy state directly into shader. */ 809 fs->state = *shader; 810 fs->state.tokens = tgsi_dup_tokens(shader->tokens); 811 812 return (void*)fs; 813} 814 815void r300_mark_fs_code_dirty(struct r300_context *r300) 816{ 817 struct r300_fragment_shader* fs = r300_fs(r300); 818 819 r300->fs.dirty = TRUE; 820 r300->fs_rc_constant_state.dirty = TRUE; 821 r300->fs_constants.dirty = TRUE; 822 r300->fs.size = fs->shader->cb_code_size; 823 824 if (r300->screen->caps.is_r500) { 825 r300->fs_rc_constant_state.size = fs->shader->rc_state_count * 7; 826 r300->fs_constants.size = fs->shader->externals_count * 4 + 3; 827 } else { 828 r300->fs_rc_constant_state.size = fs->shader->rc_state_count * 5; 829 r300->fs_constants.size = fs->shader->externals_count * 4 + 1; 830 } 831} 832 833/* Bind fragment shader state. */ 834static void r300_bind_fs_state(struct pipe_context* pipe, void* shader) 835{ 836 struct r300_context* r300 = r300_context(pipe); 837 struct r300_fragment_shader* fs = (struct r300_fragment_shader*)shader; 838 839 if (fs == NULL) { 840 r300->fs.state = NULL; 841 return; 842 } 843 844 r300->fs.state = fs; 845 r300_pick_fragment_shader(r300); 846 r300_mark_fs_code_dirty(r300); 847 848 r300->rs_block_state.dirty = TRUE; /* Will be updated before the emission. */ 849} 850 851/* Delete fragment shader state. */ 852static void r300_delete_fs_state(struct pipe_context* pipe, void* shader) 853{ 854 struct r300_fragment_shader* fs = (struct r300_fragment_shader*)shader; 855 struct r300_fragment_shader_code *tmp, *ptr = fs->first; 856 857 while (ptr) { 858 tmp = ptr; 859 ptr = ptr->next; 860 rc_constants_destroy(&tmp->code.constants); 861 FREE(tmp->cb_code); 862 FREE(tmp); 863 } 864 FREE((void*)fs->state.tokens); 865 FREE(shader); 866} 867 868static void r300_set_polygon_stipple(struct pipe_context* pipe, 869 const struct pipe_poly_stipple* state) 870{ 871 /* XXX no idea how to set this up, but not terribly important */ 872} 873 874/* Create a new rasterizer state based on the CSO rasterizer state. 875 * 876 * This is a very large chunk of state, and covers most of the graphics 877 * backend (GB), geometry assembly (GA), and setup unit (SU) blocks. 878 * 879 * In a not entirely unironic sidenote, this state has nearly nothing to do 880 * with the actual block on the Radeon called the rasterizer (RS). */ 881static void* r300_create_rs_state(struct pipe_context* pipe, 882 const struct pipe_rasterizer_state* state) 883{ 884 struct r300_rs_state* rs = CALLOC_STRUCT(r300_rs_state); 885 int i; 886 float psiz; 887 uint32_t vap_control_status; /* R300_VAP_CNTL_STATUS: 0x2140 */ 888 uint32_t point_size; /* R300_GA_POINT_SIZE: 0x421c */ 889 uint32_t point_minmax; /* R300_GA_POINT_MINMAX: 0x4230 */ 890 uint32_t line_control; /* R300_GA_LINE_CNTL: 0x4234 */ 891 uint32_t polygon_offset_enable; /* R300_SU_POLY_OFFSET_ENABLE: 0x42b4 */ 892 uint32_t cull_mode; /* R300_SU_CULL_MODE: 0x42b8 */ 893 uint32_t line_stipple_config; /* R300_GA_LINE_STIPPLE_CONFIG: 0x4328 */ 894 uint32_t line_stipple_value; /* R300_GA_LINE_STIPPLE_VALUE: 0x4260 */ 895 uint32_t polygon_mode; /* R300_GA_POLY_MODE: 0x4288 */ 896 uint32_t clip_rule; /* R300_SC_CLIP_RULE: 0x43D0 */ 897 898 /* Specifies top of Raster pipe specific enable controls, 899 * i.e. texture coordinates stuffing for points, lines, triangles */ 900 uint32_t stuffing_enable; /* R300_GB_ENABLE: 0x4008 */ 901 902 /* Point sprites texture coordinates, 0: lower left, 1: upper right */ 903 float point_texcoord_left; /* R300_GA_POINT_S0: 0x4200 */ 904 float point_texcoord_bottom = 0;/* R300_GA_POINT_T0: 0x4204 */ 905 float point_texcoord_right; /* R300_GA_POINT_S1: 0x4208 */ 906 float point_texcoord_top = 0; /* R300_GA_POINT_T1: 0x420c */ 907 CB_LOCALS; 908 909 /* Copy rasterizer state. */ 910 rs->rs = *state; 911 rs->rs_draw = *state; 912 913 /* Override some states for Draw. */ 914 rs->rs_draw.sprite_coord_enable = 0; /* We can do this in HW. */ 915 916#ifdef PIPE_ARCH_LITTLE_ENDIAN 917 vap_control_status = R300_VC_NO_SWAP; 918#else 919 vap_control_status = R300_VC_32BIT_SWAP; 920#endif 921 922 /* If no TCL engine is present, turn off the HW TCL. */ 923 if (!r300_screen(pipe->screen)->caps.has_tcl) { 924 vap_control_status |= R300_VAP_TCL_BYPASS; 925 } 926 927 /* Point size width and height. */ 928 point_size = 929 pack_float_16_6x(state->point_size) | 930 (pack_float_16_6x(state->point_size) << R300_POINTSIZE_X_SHIFT); 931 932 /* Point size clamping. */ 933 if (state->point_size_per_vertex) { 934 /* Per-vertex point size. 935 * Clamp to [0, max FB size] */ 936 psiz = pipe->screen->get_paramf(pipe->screen, 937 PIPE_CAP_MAX_POINT_WIDTH); 938 point_minmax = 939 pack_float_16_6x(psiz) << R300_GA_POINT_MINMAX_MAX_SHIFT; 940 } else { 941 /* We cannot disable the point-size vertex output, 942 * so clamp it. */ 943 psiz = state->point_size; 944 point_minmax = 945 (pack_float_16_6x(psiz) << R300_GA_POINT_MINMAX_MIN_SHIFT) | 946 (pack_float_16_6x(psiz) << R300_GA_POINT_MINMAX_MAX_SHIFT); 947 } 948 949 /* Line control. */ 950 line_control = pack_float_16_6x(state->line_width) | 951 R300_GA_LINE_CNTL_END_TYPE_COMP; 952 953 /* Enable polygon mode */ 954 polygon_mode = 0; 955 if (state->fill_front != PIPE_POLYGON_MODE_FILL || 956 state->fill_back != PIPE_POLYGON_MODE_FILL) { 957 polygon_mode = R300_GA_POLY_MODE_DUAL; 958 } 959 960 /* Front face */ 961 if (state->front_ccw) 962 cull_mode = R300_FRONT_FACE_CCW; 963 else 964 cull_mode = R300_FRONT_FACE_CW; 965 966 /* Polygon offset */ 967 polygon_offset_enable = 0; 968 if (util_get_offset(state, state->fill_front)) { 969 polygon_offset_enable |= R300_FRONT_ENABLE; 970 } 971 if (util_get_offset(state, state->fill_back)) { 972 polygon_offset_enable |= R300_BACK_ENABLE; 973 } 974 975 rs->polygon_offset_enable = polygon_offset_enable != 0; 976 977 /* Polygon mode */ 978 if (polygon_mode) { 979 polygon_mode |= 980 r300_translate_polygon_mode_front(state->fill_front); 981 polygon_mode |= 982 r300_translate_polygon_mode_back(state->fill_back); 983 } 984 985 if (state->cull_face & PIPE_FACE_FRONT) { 986 cull_mode |= R300_CULL_FRONT; 987 } 988 if (state->cull_face & PIPE_FACE_BACK) { 989 cull_mode |= R300_CULL_BACK; 990 } 991 992 if (state->line_stipple_enable) { 993 line_stipple_config = 994 R300_GA_LINE_STIPPLE_CONFIG_LINE_RESET_LINE | 995 (fui((float)state->line_stipple_factor) & 996 R300_GA_LINE_STIPPLE_CONFIG_STIPPLE_SCALE_MASK); 997 /* XXX this might need to be scaled up */ 998 line_stipple_value = state->line_stipple_pattern; 999 } else { 1000 line_stipple_config = 0; 1001 line_stipple_value = 0; 1002 } 1003 1004 if (state->flatshade) { 1005 rs->color_control = R300_SHADE_MODEL_FLAT; 1006 } else { 1007 rs->color_control = R300_SHADE_MODEL_SMOOTH; 1008 } 1009 1010 clip_rule = state->scissor ? 0xAAAA : 0xFFFF; 1011 1012 /* Point sprites */ 1013 stuffing_enable = 0; 1014 if (state->sprite_coord_enable) { 1015 stuffing_enable = R300_GB_POINT_STUFF_ENABLE; 1016 for (i = 0; i < 8; i++) { 1017 if (state->sprite_coord_enable & (1 << i)) 1018 stuffing_enable |= 1019 R300_GB_TEX_ST << (R300_GB_TEX0_SOURCE_SHIFT + (i*2)); 1020 } 1021 1022 point_texcoord_left = 0.0f; 1023 point_texcoord_right = 1.0f; 1024 1025 switch (state->sprite_coord_mode) { 1026 case PIPE_SPRITE_COORD_UPPER_LEFT: 1027 point_texcoord_top = 0.0f; 1028 point_texcoord_bottom = 1.0f; 1029 break; 1030 case PIPE_SPRITE_COORD_LOWER_LEFT: 1031 point_texcoord_top = 1.0f; 1032 point_texcoord_bottom = 0.0f; 1033 break; 1034 } 1035 } 1036 1037 /* Build the main command buffer. */ 1038 BEGIN_CB(rs->cb_main, 25); 1039 OUT_CB_REG(R300_VAP_CNTL_STATUS, vap_control_status); 1040 OUT_CB_REG(R300_GA_POINT_SIZE, point_size); 1041 OUT_CB_REG_SEQ(R300_GA_POINT_MINMAX, 2); 1042 OUT_CB(point_minmax); 1043 OUT_CB(line_control); 1044 OUT_CB_REG_SEQ(R300_SU_POLY_OFFSET_ENABLE, 2); 1045 OUT_CB(polygon_offset_enable); 1046 rs->cull_mode_index = 9; 1047 OUT_CB(cull_mode); 1048 OUT_CB_REG(R300_GA_LINE_STIPPLE_CONFIG, line_stipple_config); 1049 OUT_CB_REG(R300_GA_LINE_STIPPLE_VALUE, line_stipple_value); 1050 OUT_CB_REG(R300_GA_POLY_MODE, polygon_mode); 1051 OUT_CB_REG(R300_SC_CLIP_RULE, clip_rule); 1052 OUT_CB_REG(R300_GB_ENABLE, stuffing_enable); 1053 OUT_CB_REG_SEQ(R300_GA_POINT_S0, 4); 1054 OUT_CB_32F(point_texcoord_left); 1055 OUT_CB_32F(point_texcoord_bottom); 1056 OUT_CB_32F(point_texcoord_right); 1057 OUT_CB_32F(point_texcoord_top); 1058 END_CB; 1059 1060 /* Build the two command buffers for polygon offset setup. */ 1061 if (polygon_offset_enable) { 1062 float scale = state->offset_scale * 12; 1063 float offset = state->offset_units * 4; 1064 1065 BEGIN_CB(rs->cb_poly_offset_zb16, 5); 1066 OUT_CB_REG_SEQ(R300_SU_POLY_OFFSET_FRONT_SCALE, 4); 1067 OUT_CB_32F(scale); 1068 OUT_CB_32F(offset); 1069 OUT_CB_32F(scale); 1070 OUT_CB_32F(offset); 1071 END_CB; 1072 1073 offset = state->offset_units * 2; 1074 1075 BEGIN_CB(rs->cb_poly_offset_zb24, 5); 1076 OUT_CB_REG_SEQ(R300_SU_POLY_OFFSET_FRONT_SCALE, 4); 1077 OUT_CB_32F(scale); 1078 OUT_CB_32F(offset); 1079 OUT_CB_32F(scale); 1080 OUT_CB_32F(offset); 1081 END_CB; 1082 } 1083 1084 return (void*)rs; 1085} 1086 1087/* Bind rasterizer state. */ 1088static void r300_bind_rs_state(struct pipe_context* pipe, void* state) 1089{ 1090 struct r300_context* r300 = r300_context(pipe); 1091 struct r300_rs_state* rs = (struct r300_rs_state*)state; 1092 int last_sprite_coord_enable = r300->sprite_coord_enable; 1093 boolean last_two_sided_color = r300->two_sided_color; 1094 1095 if (r300->draw && rs) { 1096 draw_set_rasterizer_state(r300->draw, &rs->rs_draw, state); 1097 } 1098 1099 if (rs) { 1100 r300->polygon_offset_enabled = rs->polygon_offset_enable; 1101 r300->sprite_coord_enable = rs->rs.sprite_coord_enable; 1102 r300->two_sided_color = rs->rs.light_twoside; 1103 } else { 1104 r300->polygon_offset_enabled = FALSE; 1105 r300->sprite_coord_enable = 0; 1106 r300->two_sided_color = FALSE; 1107 } 1108 1109 UPDATE_STATE(state, r300->rs_state); 1110 r300->rs_state.size = 25 + (r300->polygon_offset_enabled ? 5 : 0); 1111 1112 if (last_sprite_coord_enable != r300->sprite_coord_enable || 1113 last_two_sided_color != r300->two_sided_color) { 1114 r300->rs_block_state.dirty = TRUE; 1115 } 1116} 1117 1118/* Free rasterizer state. */ 1119static void r300_delete_rs_state(struct pipe_context* pipe, void* state) 1120{ 1121 FREE(state); 1122} 1123 1124static void* 1125 r300_create_sampler_state(struct pipe_context* pipe, 1126 const struct pipe_sampler_state* state) 1127{ 1128 struct r300_context* r300 = r300_context(pipe); 1129 struct r300_sampler_state* sampler = CALLOC_STRUCT(r300_sampler_state); 1130 boolean is_r500 = r300->screen->caps.is_r500; 1131 int lod_bias; 1132 union util_color uc; 1133 1134 sampler->state = *state; 1135 1136 /* r300 doesn't handle CLAMP and MIRROR_CLAMP correctly when either MAG 1137 * or MIN filter is NEAREST. Since texwrap produces same results 1138 * for CLAMP and CLAMP_TO_EDGE, we use them instead. */ 1139 if (sampler->state.min_img_filter == PIPE_TEX_FILTER_NEAREST || 1140 sampler->state.mag_img_filter == PIPE_TEX_FILTER_NEAREST) { 1141 /* Wrap S. */ 1142 if (sampler->state.wrap_s == PIPE_TEX_WRAP_CLAMP) 1143 sampler->state.wrap_s = PIPE_TEX_WRAP_CLAMP_TO_EDGE; 1144 else if (sampler->state.wrap_s == PIPE_TEX_WRAP_MIRROR_CLAMP) 1145 sampler->state.wrap_s = PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE; 1146 1147 /* Wrap T. */ 1148 if (sampler->state.wrap_t == PIPE_TEX_WRAP_CLAMP) 1149 sampler->state.wrap_t = PIPE_TEX_WRAP_CLAMP_TO_EDGE; 1150 else if (sampler->state.wrap_t == PIPE_TEX_WRAP_MIRROR_CLAMP) 1151 sampler->state.wrap_t = PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE; 1152 1153 /* Wrap R. */ 1154 if (sampler->state.wrap_r == PIPE_TEX_WRAP_CLAMP) 1155 sampler->state.wrap_r = PIPE_TEX_WRAP_CLAMP_TO_EDGE; 1156 else if (sampler->state.wrap_r == PIPE_TEX_WRAP_MIRROR_CLAMP) 1157 sampler->state.wrap_r = PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE; 1158 } 1159 1160 sampler->filter0 |= 1161 (r300_translate_wrap(sampler->state.wrap_s) << R300_TX_WRAP_S_SHIFT) | 1162 (r300_translate_wrap(sampler->state.wrap_t) << R300_TX_WRAP_T_SHIFT) | 1163 (r300_translate_wrap(sampler->state.wrap_r) << R300_TX_WRAP_R_SHIFT); 1164 1165 sampler->filter0 |= r300_translate_tex_filters(state->min_img_filter, 1166 state->mag_img_filter, 1167 state->min_mip_filter, 1168 state->max_anisotropy > 0); 1169 1170 sampler->filter0 |= r300_anisotropy(state->max_anisotropy); 1171 1172 /* Unfortunately, r300-r500 don't support floating-point mipmap lods. */ 1173 /* We must pass these to the merge function to clamp them properly. */ 1174 sampler->min_lod = MAX2((unsigned)state->min_lod, 0); 1175 sampler->max_lod = MAX2((unsigned)ceilf(state->max_lod), 0); 1176 1177 lod_bias = CLAMP((int)(state->lod_bias * 32 + 1), -(1 << 9), (1 << 9) - 1); 1178 1179 sampler->filter1 |= (lod_bias << R300_LOD_BIAS_SHIFT) & R300_LOD_BIAS_MASK; 1180 1181 /* This is very high quality anisotropic filtering for R5xx. 1182 * It's good for benchmarking the performance of texturing but 1183 * in practice we don't want to slow down the driver because it's 1184 * a pretty good performance killer. Feel free to play with it. */ 1185 if (DBG_ON(r300, DBG_ANISOHQ) && is_r500) { 1186 sampler->filter1 |= r500_anisotropy(state->max_anisotropy); 1187 } 1188 1189 util_pack_color(state->border_color, PIPE_FORMAT_B8G8R8A8_UNORM, &uc); 1190 sampler->border_color = uc.ui; 1191 1192 /* R500-specific fixups and optimizations */ 1193 if (r300->screen->caps.is_r500) { 1194 sampler->filter1 |= R500_BORDER_FIX; 1195 } 1196 1197 return (void*)sampler; 1198} 1199 1200static void r300_bind_sampler_states(struct pipe_context* pipe, 1201 unsigned count, 1202 void** states) 1203{ 1204 struct r300_context* r300 = r300_context(pipe); 1205 struct r300_textures_state* state = 1206 (struct r300_textures_state*)r300->textures_state.state; 1207 unsigned tex_units = r300->screen->caps.num_tex_units; 1208 1209 if (count > tex_units) { 1210 return; 1211 } 1212 1213 memcpy(state->sampler_states, states, sizeof(void*) * count); 1214 state->sampler_state_count = count; 1215 1216 r300->textures_state.dirty = TRUE; 1217} 1218 1219static void r300_lacks_vertex_textures(struct pipe_context* pipe, 1220 unsigned count, 1221 void** states) 1222{ 1223} 1224 1225static void r300_delete_sampler_state(struct pipe_context* pipe, void* state) 1226{ 1227 FREE(state); 1228} 1229 1230static uint32_t r300_assign_texture_cache_region(unsigned index, unsigned num) 1231{ 1232 /* This looks like a hack, but I believe it's suppose to work like 1233 * that. To illustrate how this works, let's assume you have 5 textures. 1234 * From docs, 5 and the successive numbers are: 1235 * 1236 * FOURTH_1 = 5 1237 * FOURTH_2 = 6 1238 * FOURTH_3 = 7 1239 * EIGHTH_0 = 8 1240 * EIGHTH_1 = 9 1241 * 1242 * First 3 textures will get 3/4 of size of the cache, divived evenly 1243 * between them. The last 1/4 of the cache must be divided between 1244 * the last 2 textures, each will therefore get 1/8 of the cache. 1245 * Why not just to use "5 + texture_index" ? 1246 * 1247 * This simple trick works for all "num" <= 16. 1248 */ 1249 if (num <= 1) 1250 return R300_TX_CACHE(R300_TX_CACHE_WHOLE); 1251 else 1252 return R300_TX_CACHE(num + index); 1253} 1254 1255static void r300_set_fragment_sampler_views(struct pipe_context* pipe, 1256 unsigned count, 1257 struct pipe_sampler_view** views) 1258{ 1259 struct r300_context* r300 = r300_context(pipe); 1260 struct r300_textures_state* state = 1261 (struct r300_textures_state*)r300->textures_state.state; 1262 struct r300_texture *texture; 1263 unsigned i, real_num_views = 0, view_index = 0; 1264 unsigned tex_units = r300->screen->caps.num_tex_units; 1265 boolean dirty_tex = FALSE; 1266 1267 if (count > tex_units) { 1268 return; 1269 } 1270 1271 /* Calculate the real number of views. */ 1272 for (i = 0; i < count; i++) { 1273 if (views[i]) 1274 real_num_views++; 1275 } 1276 1277 for (i = 0; i < count; i++) { 1278 if (&state->sampler_views[i]->base != views[i]) { 1279 pipe_sampler_view_reference( 1280 (struct pipe_sampler_view**)&state->sampler_views[i], 1281 views[i]); 1282 1283 if (!views[i]) { 1284 continue; 1285 } 1286 1287 /* A new sampler view (= texture)... */ 1288 dirty_tex = TRUE; 1289 1290 /* Set the texrect factor in the fragment shader. 1291 * Needed for RECT and NPOT fallback. */ 1292 texture = r300_texture(views[i]->texture); 1293 if (texture->desc.is_npot) { 1294 r300->fs_rc_constant_state.dirty = TRUE; 1295 } 1296 1297 state->sampler_views[i]->texcache_region = 1298 r300_assign_texture_cache_region(view_index, real_num_views); 1299 view_index++; 1300 } 1301 } 1302 1303 for (i = count; i < tex_units; i++) { 1304 if (state->sampler_views[i]) { 1305 pipe_sampler_view_reference( 1306 (struct pipe_sampler_view**)&state->sampler_views[i], 1307 NULL); 1308 } 1309 } 1310 1311 state->sampler_view_count = count; 1312 1313 r300->textures_state.dirty = TRUE; 1314 1315 if (dirty_tex) { 1316 r300->texture_cache_inval.dirty = TRUE; 1317 } 1318} 1319 1320static struct pipe_sampler_view * 1321r300_create_sampler_view(struct pipe_context *pipe, 1322 struct pipe_resource *texture, 1323 const struct pipe_sampler_view *templ) 1324{ 1325 struct r300_sampler_view *view = CALLOC_STRUCT(r300_sampler_view); 1326 struct r300_texture *tex = r300_texture(texture); 1327 boolean is_r500 = r300_screen(pipe->screen)->caps.is_r500; 1328 1329 if (view) { 1330 view->base = *templ; 1331 view->base.reference.count = 1; 1332 view->base.context = pipe; 1333 view->base.texture = NULL; 1334 pipe_resource_reference(&view->base.texture, texture); 1335 1336 view->swizzle[0] = templ->swizzle_r; 1337 view->swizzle[1] = templ->swizzle_g; 1338 view->swizzle[2] = templ->swizzle_b; 1339 view->swizzle[3] = templ->swizzle_a; 1340 1341 view->format = tex->tx_format; 1342 view->format.format1 |= r300_translate_texformat(templ->format, 1343 view->swizzle, 1344 is_r500); 1345 if (is_r500) { 1346 view->format.format2 |= r500_tx_format_msb_bit(templ->format); 1347 } 1348 } 1349 1350 return (struct pipe_sampler_view*)view; 1351} 1352 1353static void 1354r300_sampler_view_destroy(struct pipe_context *pipe, 1355 struct pipe_sampler_view *view) 1356{ 1357 pipe_resource_reference(&view->texture, NULL); 1358 FREE(view); 1359} 1360 1361static void r300_set_scissor_state(struct pipe_context* pipe, 1362 const struct pipe_scissor_state* state) 1363{ 1364 struct r300_context* r300 = r300_context(pipe); 1365 1366 memcpy(r300->scissor_state.state, state, 1367 sizeof(struct pipe_scissor_state)); 1368 1369 r300->scissor_state.dirty = TRUE; 1370} 1371 1372static void r300_set_viewport_state(struct pipe_context* pipe, 1373 const struct pipe_viewport_state* state) 1374{ 1375 struct r300_context* r300 = r300_context(pipe); 1376 struct r300_viewport_state* viewport = 1377 (struct r300_viewport_state*)r300->viewport_state.state; 1378 1379 r300->viewport = *state; 1380 1381 if (r300->draw) { 1382 draw_set_viewport_state(r300->draw, state); 1383 viewport->vte_control = R300_VTX_XY_FMT | R300_VTX_Z_FMT; 1384 return; 1385 } 1386 1387 /* Do the transform in HW. */ 1388 viewport->vte_control = R300_VTX_W0_FMT; 1389 1390 if (state->scale[0] != 1.0f) { 1391 viewport->xscale = state->scale[0]; 1392 viewport->vte_control |= R300_VPORT_X_SCALE_ENA; 1393 } 1394 if (state->scale[1] != 1.0f) { 1395 viewport->yscale = state->scale[1]; 1396 viewport->vte_control |= R300_VPORT_Y_SCALE_ENA; 1397 } 1398 if (state->scale[2] != 1.0f) { 1399 viewport->zscale = state->scale[2]; 1400 viewport->vte_control |= R300_VPORT_Z_SCALE_ENA; 1401 } 1402 if (state->translate[0] != 0.0f) { 1403 viewport->xoffset = state->translate[0]; 1404 viewport->vte_control |= R300_VPORT_X_OFFSET_ENA; 1405 } 1406 if (state->translate[1] != 0.0f) { 1407 viewport->yoffset = state->translate[1]; 1408 viewport->vte_control |= R300_VPORT_Y_OFFSET_ENA; 1409 } 1410 if (state->translate[2] != 0.0f) { 1411 viewport->zoffset = state->translate[2]; 1412 viewport->vte_control |= R300_VPORT_Z_OFFSET_ENA; 1413 } 1414 1415 r300->viewport_state.dirty = TRUE; 1416 if (r300->fs.state && r300_fs(r300)->shader->inputs.wpos != ATTR_UNUSED) { 1417 r300->fs_rc_constant_state.dirty = TRUE; 1418 } 1419} 1420 1421static void r300_set_vertex_buffers(struct pipe_context* pipe, 1422 unsigned count, 1423 const struct pipe_vertex_buffer* buffers) 1424{ 1425 struct r300_context* r300 = r300_context(pipe); 1426 struct pipe_vertex_buffer *vbo; 1427 unsigned i, max_index = (1 << 24) - 1; 1428 boolean any_user_buffer = FALSE; 1429 1430 if (count == r300->vertex_buffer_count && 1431 memcmp(r300->vertex_buffer, buffers, 1432 sizeof(struct pipe_vertex_buffer) * count) == 0) { 1433 return; 1434 } 1435 1436 if (r300->screen->caps.has_tcl) { 1437 /* HW TCL. */ 1438 r300->incompatible_vb_layout = FALSE; 1439 1440 /* Check if the strides and offsets are aligned to the size of DWORD. */ 1441 for (i = 0; i < count; i++) { 1442 if (buffers[i].buffer) { 1443 if (buffers[i].stride % 4 != 0 || 1444 buffers[i].buffer_offset % 4 != 0) { 1445 r300->incompatible_vb_layout = TRUE; 1446 break; 1447 } 1448 } 1449 } 1450 1451 for (i = 0; i < count; i++) { 1452 /* Why, yes, I AM casting away constness. How did you know? */ 1453 vbo = (struct pipe_vertex_buffer*)&buffers[i]; 1454 1455 /* Skip NULL buffers */ 1456 if (!buffers[i].buffer) { 1457 continue; 1458 } 1459 1460 if (r300_buffer_is_user_buffer(vbo->buffer)) { 1461 any_user_buffer = TRUE; 1462 } 1463 1464 if (vbo->max_index == ~0) { 1465 /* if no VBO stride then only one vertex value so max index is 1 */ 1466 /* should think about converting to VS constants like svga does */ 1467 if (!vbo->stride) 1468 vbo->max_index = 1; 1469 else 1470 vbo->max_index = 1471 (vbo->buffer->width0 - vbo->buffer_offset) / vbo->stride; 1472 } 1473 1474 max_index = MIN2(vbo->max_index, max_index); 1475 } 1476 1477 r300->any_user_vbs = any_user_buffer; 1478 r300->vertex_buffer_max_index = max_index; 1479 1480 } else { 1481 /* SW TCL. */ 1482 draw_set_vertex_buffers(r300->draw, count, buffers); 1483 } 1484 1485 /* Common code. */ 1486 for (i = 0; i < count; i++) { 1487 /* Reference our buffer. */ 1488 pipe_resource_reference(&r300->vertex_buffer[i].buffer, buffers[i].buffer); 1489 } 1490 for (; i < r300->vertex_buffer_count; i++) { 1491 /* Dereference any old buffers. */ 1492 pipe_resource_reference(&r300->vertex_buffer[i].buffer, NULL); 1493 } 1494 1495 memcpy(r300->vertex_buffer, buffers, 1496 sizeof(struct pipe_vertex_buffer) * count); 1497 r300->vertex_buffer_count = count; 1498} 1499 1500static void r300_set_index_buffer(struct pipe_context* pipe, 1501 const struct pipe_index_buffer *ib) 1502{ 1503 struct r300_context* r300 = r300_context(pipe); 1504 1505 if (ib) { 1506 pipe_resource_reference(&r300->index_buffer.buffer, ib->buffer); 1507 memcpy(&r300->index_buffer, ib, sizeof(r300->index_buffer)); 1508 } 1509 else { 1510 pipe_resource_reference(&r300->index_buffer.buffer, NULL); 1511 memset(&r300->index_buffer, 0, sizeof(r300->index_buffer)); 1512 } 1513 1514 /* TODO make this more like a state */ 1515} 1516 1517/* Initialize the PSC tables. */ 1518static void r300_vertex_psc(struct r300_vertex_element_state *velems) 1519{ 1520 struct r300_vertex_stream_state *vstream = &velems->vertex_stream; 1521 uint16_t type, swizzle; 1522 enum pipe_format format; 1523 unsigned i; 1524 1525 if (velems->count > 16) { 1526 fprintf(stderr, "r300: More than 16 vertex elements are not supported," 1527 " requested %i, using 16.\n", velems->count); 1528 velems->count = 16; 1529 } 1530 1531 /* Vertex shaders have no semantics on their inputs, 1532 * so PSC should just route stuff based on the vertex elements, 1533 * and not on attrib information. */ 1534 for (i = 0; i < velems->count; i++) { 1535 format = velems->hw_format[i]; 1536 1537 type = r300_translate_vertex_data_type(format); 1538 if (type == R300_INVALID_FORMAT) { 1539 fprintf(stderr, "r300: Bad vertex format %s.\n", 1540 util_format_short_name(format)); 1541 assert(0); 1542 abort(); 1543 } 1544 1545 type |= i << R300_DST_VEC_LOC_SHIFT; 1546 swizzle = r300_translate_vertex_data_swizzle(format); 1547 1548 if (i & 1) { 1549 vstream->vap_prog_stream_cntl[i >> 1] |= type << 16; 1550 vstream->vap_prog_stream_cntl_ext[i >> 1] |= swizzle << 16; 1551 } else { 1552 vstream->vap_prog_stream_cntl[i >> 1] |= type; 1553 vstream->vap_prog_stream_cntl_ext[i >> 1] |= swizzle; 1554 } 1555 } 1556 1557 /* Set the last vector in the PSC. */ 1558 if (i) { 1559 i -= 1; 1560 } 1561 vstream->vap_prog_stream_cntl[i >> 1] |= 1562 (R300_LAST_VEC << (i & 1 ? 16 : 0)); 1563 1564 vstream->count = (i >> 1) + 1; 1565} 1566 1567#define FORMAT_REPLACE(what, withwhat) \ 1568 case PIPE_FORMAT_##what: *format = PIPE_FORMAT_##withwhat; break 1569 1570static void* r300_create_vertex_elements_state(struct pipe_context* pipe, 1571 unsigned count, 1572 const struct pipe_vertex_element* attribs) 1573{ 1574 struct r300_vertex_element_state *velems; 1575 unsigned i; 1576 enum pipe_format *format; 1577 1578 assert(count <= PIPE_MAX_ATTRIBS); 1579 velems = CALLOC_STRUCT(r300_vertex_element_state); 1580 if (velems != NULL) { 1581 velems->count = count; 1582 memcpy(velems->velem, attribs, sizeof(struct pipe_vertex_element) * count); 1583 1584 if (r300_screen(pipe->screen)->caps.has_tcl) { 1585 /* Set the best hw format in case the original format is not 1586 * supported by hw. */ 1587 for (i = 0; i < count; i++) { 1588 velems->hw_format[i] = velems->velem[i].src_format; 1589 format = &velems->hw_format[i]; 1590 1591 /* This is basically the list of unsupported formats. 1592 * For now we don't care about the alignment, that's going to 1593 * be sorted out after the PSC setup. */ 1594 switch (*format) { 1595 FORMAT_REPLACE(R64_FLOAT, R32_FLOAT); 1596 FORMAT_REPLACE(R64G64_FLOAT, R32G32_FLOAT); 1597 FORMAT_REPLACE(R64G64B64_FLOAT, R32G32B32_FLOAT); 1598 FORMAT_REPLACE(R64G64B64A64_FLOAT, R32G32B32A32_FLOAT); 1599 1600 FORMAT_REPLACE(R32_UNORM, R32_FLOAT); 1601 FORMAT_REPLACE(R32G32_UNORM, R32G32_FLOAT); 1602 FORMAT_REPLACE(R32G32B32_UNORM, R32G32B32_FLOAT); 1603 FORMAT_REPLACE(R32G32B32A32_UNORM, R32G32B32A32_FLOAT); 1604 1605 FORMAT_REPLACE(R32_USCALED, R32_FLOAT); 1606 FORMAT_REPLACE(R32G32_USCALED, R32G32_FLOAT); 1607 FORMAT_REPLACE(R32G32B32_USCALED, R32G32B32_FLOAT); 1608 FORMAT_REPLACE(R32G32B32A32_USCALED,R32G32B32A32_FLOAT); 1609 1610 FORMAT_REPLACE(R32_SNORM, R32_FLOAT); 1611 FORMAT_REPLACE(R32G32_SNORM, R32G32_FLOAT); 1612 FORMAT_REPLACE(R32G32B32_SNORM, R32G32B32_FLOAT); 1613 FORMAT_REPLACE(R32G32B32A32_SNORM, R32G32B32A32_FLOAT); 1614 1615 FORMAT_REPLACE(R32_SSCALED, R32_FLOAT); 1616 FORMAT_REPLACE(R32G32_SSCALED, R32G32_FLOAT); 1617 FORMAT_REPLACE(R32G32B32_SSCALED, R32G32B32_FLOAT); 1618 FORMAT_REPLACE(R32G32B32A32_SSCALED,R32G32B32A32_FLOAT); 1619 1620 FORMAT_REPLACE(R32_FIXED, R32_FLOAT); 1621 FORMAT_REPLACE(R32G32_FIXED, R32G32_FLOAT); 1622 FORMAT_REPLACE(R32G32B32_FIXED, R32G32B32_FLOAT); 1623 FORMAT_REPLACE(R32G32B32A32_FIXED, R32G32B32A32_FLOAT); 1624 1625 default:; 1626 } 1627 1628 velems->incompatible_layout = 1629 velems->incompatible_layout || 1630 velems->velem[i].src_format != velems->hw_format[i] || 1631 velems->velem[i].src_offset % 4 != 0; 1632 } 1633 1634 /* Now setup PSC. 1635 * The unused components will be replaced by (..., 0, 1). */ 1636 r300_vertex_psc(velems); 1637 1638 /* Align the formats to the size of DWORD. 1639 * We only care about the blocksizes of the formats since 1640 * swizzles are already set up. 1641 * Also compute the vertex size. */ 1642 for (i = 0; i < count; i++) { 1643 /* This is OK because we check for aligned strides too. */ 1644 velems->hw_format_size[i] = 1645 align(util_format_get_blocksize(velems->hw_format[i]), 4); 1646 velems->vertex_size_dwords += velems->hw_format_size[i] / 4; 1647 } 1648 } 1649 } 1650 return velems; 1651} 1652 1653static void r300_bind_vertex_elements_state(struct pipe_context *pipe, 1654 void *state) 1655{ 1656 struct r300_context *r300 = r300_context(pipe); 1657 struct r300_vertex_element_state *velems = state; 1658 1659 if (velems == NULL) { 1660 return; 1661 } 1662 1663 r300->velems = velems; 1664 1665 if (r300->draw) { 1666 draw_set_vertex_elements(r300->draw, velems->count, velems->velem); 1667 return; 1668 } 1669 1670 UPDATE_STATE(&velems->vertex_stream, r300->vertex_stream_state); 1671 r300->vertex_stream_state.size = (1 + velems->vertex_stream.count) * 2; 1672} 1673 1674static void r300_delete_vertex_elements_state(struct pipe_context *pipe, void *state) 1675{ 1676 FREE(state); 1677} 1678 1679static void* r300_create_vs_state(struct pipe_context* pipe, 1680 const struct pipe_shader_state* shader) 1681{ 1682 struct r300_context* r300 = r300_context(pipe); 1683 struct r300_vertex_shader* vs = CALLOC_STRUCT(r300_vertex_shader); 1684 1685 /* Copy state directly into shader. */ 1686 vs->state = *shader; 1687 vs->state.tokens = tgsi_dup_tokens(shader->tokens); 1688 1689 if (r300->screen->caps.has_tcl) { 1690 r300_init_vs_outputs(vs); 1691 r300_translate_vertex_shader(r300, vs); 1692 } else { 1693 r300_draw_init_vertex_shader(r300->draw, vs); 1694 } 1695 1696 return vs; 1697} 1698 1699static void r300_bind_vs_state(struct pipe_context* pipe, void* shader) 1700{ 1701 struct r300_context* r300 = r300_context(pipe); 1702 struct r300_vertex_shader* vs = (struct r300_vertex_shader*)shader; 1703 1704 if (vs == NULL) { 1705 r300->vs_state.state = NULL; 1706 return; 1707 } 1708 if (vs == r300->vs_state.state) { 1709 return; 1710 } 1711 r300->vs_state.state = vs; 1712 1713 /* The majority of the RS block bits is dependent on the vertex shader. */ 1714 r300->rs_block_state.dirty = TRUE; /* Will be updated before the emission. */ 1715 1716 if (r300->screen->caps.has_tcl) { 1717 r300->vs_state.dirty = TRUE; 1718 r300->vs_state.size = 1719 vs->code.length + 9 + 1720 (vs->immediates_count ? vs->immediates_count * 4 + 3 : 0); 1721 1722 if (vs->externals_count) { 1723 r300->vs_constants.dirty = TRUE; 1724 r300->vs_constants.size = vs->externals_count * 4 + 3; 1725 } else { 1726 r300->vs_constants.size = 0; 1727 } 1728 1729 r300->pvs_flush.dirty = TRUE; 1730 } else { 1731 draw_bind_vertex_shader(r300->draw, 1732 (struct draw_vertex_shader*)vs->draw_vs); 1733 } 1734} 1735 1736static void r300_delete_vs_state(struct pipe_context* pipe, void* shader) 1737{ 1738 struct r300_context* r300 = r300_context(pipe); 1739 struct r300_vertex_shader* vs = (struct r300_vertex_shader*)shader; 1740 1741 if (r300->screen->caps.has_tcl) { 1742 rc_constants_destroy(&vs->code.constants); 1743 } else { 1744 draw_delete_vertex_shader(r300->draw, 1745 (struct draw_vertex_shader*)vs->draw_vs); 1746 } 1747 1748 FREE((void*)vs->state.tokens); 1749 FREE(shader); 1750} 1751 1752static void r300_set_constant_buffer(struct pipe_context *pipe, 1753 uint shader, uint index, 1754 struct pipe_resource *buf) 1755{ 1756 struct r300_context* r300 = r300_context(pipe); 1757 struct r300_constant_buffer *cbuf; 1758 uint32_t *mapped = r300_buffer(buf)->user_buffer; 1759 int max_size = 0, max_size_bytes = 0, clamped_size = 0; 1760 1761 switch (shader) { 1762 case PIPE_SHADER_VERTEX: 1763 cbuf = (struct r300_constant_buffer*)r300->vs_constants.state; 1764 max_size = 256; 1765 break; 1766 case PIPE_SHADER_FRAGMENT: 1767 cbuf = (struct r300_constant_buffer*)r300->fs_constants.state; 1768 if (r300->screen->caps.is_r500) { 1769 max_size = 256; 1770 } else { 1771 max_size = 32; 1772 } 1773 break; 1774 default: 1775 assert(0); 1776 return; 1777 } 1778 max_size_bytes = max_size * 4 * sizeof(float); 1779 1780 if (buf == NULL || buf->width0 == 0 || 1781 (mapped = r300_buffer(buf)->constant_buffer) == NULL) { 1782 cbuf->count = 0; 1783 return; 1784 } 1785 1786 if (shader == PIPE_SHADER_FRAGMENT || 1787 (shader == PIPE_SHADER_VERTEX && r300->screen->caps.has_tcl)) { 1788 assert((buf->width0 % (4 * sizeof(float))) == 0); 1789 1790 /* Check the size of the constant buffer. */ 1791 /* XXX Subtract immediates and RC_STATE_* variables. */ 1792 if (buf->width0 > max_size_bytes) { 1793 fprintf(stderr, "r300: Max size of the constant buffer is " 1794 "%i*4 floats.\n", max_size); 1795 } 1796 1797 clamped_size = MIN2(buf->width0, max_size_bytes); 1798 cbuf->count = clamped_size / (4 * sizeof(float)); 1799 cbuf->ptr = mapped; 1800 } 1801 1802 if (shader == PIPE_SHADER_VERTEX) { 1803 if (r300->screen->caps.has_tcl) { 1804 if (r300->vs_constants.size) { 1805 r300->vs_constants.dirty = TRUE; 1806 } 1807 r300->pvs_flush.dirty = TRUE; 1808 } else if (r300->draw) { 1809 draw_set_mapped_constant_buffer(r300->draw, PIPE_SHADER_VERTEX, 1810 0, mapped, buf->width0); 1811 } 1812 } else if (shader == PIPE_SHADER_FRAGMENT) { 1813 r300->fs_constants.dirty = TRUE; 1814 } 1815} 1816 1817void r300_init_state_functions(struct r300_context* r300) 1818{ 1819 r300->context.create_blend_state = r300_create_blend_state; 1820 r300->context.bind_blend_state = r300_bind_blend_state; 1821 r300->context.delete_blend_state = r300_delete_blend_state; 1822 1823 r300->context.set_blend_color = r300_set_blend_color; 1824 1825 r300->context.set_clip_state = r300_set_clip_state; 1826 r300->context.set_sample_mask = r300_set_sample_mask; 1827 1828 r300->context.set_constant_buffer = r300_set_constant_buffer; 1829 1830 r300->context.create_depth_stencil_alpha_state = r300_create_dsa_state; 1831 r300->context.bind_depth_stencil_alpha_state = r300_bind_dsa_state; 1832 r300->context.delete_depth_stencil_alpha_state = r300_delete_dsa_state; 1833 1834 r300->context.set_stencil_ref = r300_set_stencil_ref; 1835 1836 r300->context.set_framebuffer_state = r300_set_framebuffer_state; 1837 1838 r300->context.create_fs_state = r300_create_fs_state; 1839 r300->context.bind_fs_state = r300_bind_fs_state; 1840 r300->context.delete_fs_state = r300_delete_fs_state; 1841 1842 r300->context.set_polygon_stipple = r300_set_polygon_stipple; 1843 1844 r300->context.create_rasterizer_state = r300_create_rs_state; 1845 r300->context.bind_rasterizer_state = r300_bind_rs_state; 1846 r300->context.delete_rasterizer_state = r300_delete_rs_state; 1847 1848 r300->context.create_sampler_state = r300_create_sampler_state; 1849 r300->context.bind_fragment_sampler_states = r300_bind_sampler_states; 1850 r300->context.bind_vertex_sampler_states = r300_lacks_vertex_textures; 1851 r300->context.delete_sampler_state = r300_delete_sampler_state; 1852 1853 r300->context.set_fragment_sampler_views = r300_set_fragment_sampler_views; 1854 r300->context.create_sampler_view = r300_create_sampler_view; 1855 r300->context.sampler_view_destroy = r300_sampler_view_destroy; 1856 1857 r300->context.set_scissor_state = r300_set_scissor_state; 1858 1859 r300->context.set_viewport_state = r300_set_viewport_state; 1860 1861 r300->context.set_vertex_buffers = r300_set_vertex_buffers; 1862 r300->context.set_index_buffer = r300_set_index_buffer; 1863 1864 r300->context.create_vertex_elements_state = r300_create_vertex_elements_state; 1865 r300->context.bind_vertex_elements_state = r300_bind_vertex_elements_state; 1866 r300->context.delete_vertex_elements_state = r300_delete_vertex_elements_state; 1867 1868 r300->context.create_vs_state = r300_create_vs_state; 1869 r300->context.bind_vs_state = r300_bind_vs_state; 1870 r300->context.delete_vs_state = r300_delete_vs_state; 1871} 1872