r300_state.c revision 6a34287bb5147a3213e94d88c97db4ec403509ae
1/* 2 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com> 3 * Copyright 2009 Marek Olšák <maraeo@gmail.com> 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * on the rights to use, copy, modify, merge, publish, distribute, sub 9 * license, and/or sell copies of the Software, and to permit persons to whom 10 * the Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, 20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 22 * USE OR OTHER DEALINGS IN THE SOFTWARE. */ 23 24#include "draw/draw_context.h" 25 26#include "util/u_blitter.h" 27#include "util/u_math.h" 28#include "util/u_memory.h" 29#include "util/u_pack_color.h" 30 31#include "tgsi/tgsi_parse.h" 32 33#include "pipe/p_config.h" 34 35#include "r300_cb.h" 36#include "r300_context.h" 37#include "r300_emit.h" 38#include "r300_reg.h" 39#include "r300_screen.h" 40#include "r300_screen_buffer.h" 41#include "r300_state_inlines.h" 42#include "r300_fs.h" 43#include "r300_texture.h" 44#include "r300_vs.h" 45#include "r300_winsys.h" 46 47/* r300_state: Functions used to intialize state context by translating 48 * Gallium state objects into semi-native r300 state objects. */ 49 50#define UPDATE_STATE(cso, atom) \ 51 if (cso != atom.state) { \ 52 atom.state = cso; \ 53 atom.dirty = TRUE; \ 54 } 55 56static boolean blend_discard_if_src_alpha_0(unsigned srcRGB, unsigned srcA, 57 unsigned dstRGB, unsigned dstA) 58{ 59 /* If the blend equation is ADD or REVERSE_SUBTRACT, 60 * SRC_ALPHA == 0, and the following state is set, the colorbuffer 61 * will not be changed. 62 * Notice that the dst factors are the src factors inverted. */ 63 return (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA || 64 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE || 65 srcRGB == PIPE_BLENDFACTOR_ZERO) && 66 (srcA == PIPE_BLENDFACTOR_SRC_COLOR || 67 srcA == PIPE_BLENDFACTOR_SRC_ALPHA || 68 srcA == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE || 69 srcA == PIPE_BLENDFACTOR_ZERO) && 70 (dstRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA || 71 dstRGB == PIPE_BLENDFACTOR_ONE) && 72 (dstA == PIPE_BLENDFACTOR_INV_SRC_COLOR || 73 dstA == PIPE_BLENDFACTOR_INV_SRC_ALPHA || 74 dstA == PIPE_BLENDFACTOR_ONE); 75} 76 77static boolean blend_discard_if_src_alpha_1(unsigned srcRGB, unsigned srcA, 78 unsigned dstRGB, unsigned dstA) 79{ 80 /* If the blend equation is ADD or REVERSE_SUBTRACT, 81 * SRC_ALPHA == 1, and the following state is set, the colorbuffer 82 * will not be changed. 83 * Notice that the dst factors are the src factors inverted. */ 84 return (srcRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA || 85 srcRGB == PIPE_BLENDFACTOR_ZERO) && 86 (srcA == PIPE_BLENDFACTOR_INV_SRC_COLOR || 87 srcA == PIPE_BLENDFACTOR_INV_SRC_ALPHA || 88 srcA == PIPE_BLENDFACTOR_ZERO) && 89 (dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA || 90 dstRGB == PIPE_BLENDFACTOR_ONE) && 91 (dstA == PIPE_BLENDFACTOR_SRC_COLOR || 92 dstA == PIPE_BLENDFACTOR_SRC_ALPHA || 93 dstA == PIPE_BLENDFACTOR_ONE); 94} 95 96static boolean blend_discard_if_src_color_0(unsigned srcRGB, unsigned srcA, 97 unsigned dstRGB, unsigned dstA) 98{ 99 /* If the blend equation is ADD or REVERSE_SUBTRACT, 100 * SRC_COLOR == (0,0,0), and the following state is set, the colorbuffer 101 * will not be changed. 102 * Notice that the dst factors are the src factors inverted. */ 103 return (srcRGB == PIPE_BLENDFACTOR_SRC_COLOR || 104 srcRGB == PIPE_BLENDFACTOR_ZERO) && 105 (srcA == PIPE_BLENDFACTOR_ZERO) && 106 (dstRGB == PIPE_BLENDFACTOR_INV_SRC_COLOR || 107 dstRGB == PIPE_BLENDFACTOR_ONE) && 108 (dstA == PIPE_BLENDFACTOR_ONE); 109} 110 111static boolean blend_discard_if_src_color_1(unsigned srcRGB, unsigned srcA, 112 unsigned dstRGB, unsigned dstA) 113{ 114 /* If the blend equation is ADD or REVERSE_SUBTRACT, 115 * SRC_COLOR == (1,1,1), and the following state is set, the colorbuffer 116 * will not be changed. 117 * Notice that the dst factors are the src factors inverted. */ 118 return (srcRGB == PIPE_BLENDFACTOR_INV_SRC_COLOR || 119 srcRGB == PIPE_BLENDFACTOR_ZERO) && 120 (srcA == PIPE_BLENDFACTOR_ZERO) && 121 (dstRGB == PIPE_BLENDFACTOR_SRC_COLOR || 122 dstRGB == PIPE_BLENDFACTOR_ONE) && 123 (dstA == PIPE_BLENDFACTOR_ONE); 124} 125 126static boolean blend_discard_if_src_alpha_color_0(unsigned srcRGB, unsigned srcA, 127 unsigned dstRGB, unsigned dstA) 128{ 129 /* If the blend equation is ADD or REVERSE_SUBTRACT, 130 * SRC_ALPHA_COLOR == (0,0,0,0), and the following state is set, 131 * the colorbuffer will not be changed. 132 * Notice that the dst factors are the src factors inverted. */ 133 return (srcRGB == PIPE_BLENDFACTOR_SRC_COLOR || 134 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA || 135 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE || 136 srcRGB == PIPE_BLENDFACTOR_ZERO) && 137 (srcA == PIPE_BLENDFACTOR_SRC_COLOR || 138 srcA == PIPE_BLENDFACTOR_SRC_ALPHA || 139 srcA == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE || 140 srcA == PIPE_BLENDFACTOR_ZERO) && 141 (dstRGB == PIPE_BLENDFACTOR_INV_SRC_COLOR || 142 dstRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA || 143 dstRGB == PIPE_BLENDFACTOR_ONE) && 144 (dstA == PIPE_BLENDFACTOR_INV_SRC_COLOR || 145 dstA == PIPE_BLENDFACTOR_INV_SRC_ALPHA || 146 dstA == PIPE_BLENDFACTOR_ONE); 147} 148 149static boolean blend_discard_if_src_alpha_color_1(unsigned srcRGB, unsigned srcA, 150 unsigned dstRGB, unsigned dstA) 151{ 152 /* If the blend equation is ADD or REVERSE_SUBTRACT, 153 * SRC_ALPHA_COLOR == (1,1,1,1), and the following state is set, 154 * the colorbuffer will not be changed. 155 * Notice that the dst factors are the src factors inverted. */ 156 return (srcRGB == PIPE_BLENDFACTOR_INV_SRC_COLOR || 157 srcRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA || 158 srcRGB == PIPE_BLENDFACTOR_ZERO) && 159 (srcA == PIPE_BLENDFACTOR_INV_SRC_COLOR || 160 srcA == PIPE_BLENDFACTOR_INV_SRC_ALPHA || 161 srcA == PIPE_BLENDFACTOR_ZERO) && 162 (dstRGB == PIPE_BLENDFACTOR_SRC_COLOR || 163 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA || 164 dstRGB == PIPE_BLENDFACTOR_ONE) && 165 (dstA == PIPE_BLENDFACTOR_SRC_COLOR || 166 dstA == PIPE_BLENDFACTOR_SRC_ALPHA || 167 dstA == PIPE_BLENDFACTOR_ONE); 168} 169 170static unsigned bgra_cmask(unsigned mask) 171{ 172 /* Gallium uses RGBA color ordering while R300 expects BGRA. */ 173 174 return ((mask & PIPE_MASK_R) << 2) | 175 ((mask & PIPE_MASK_B) >> 2) | 176 (mask & (PIPE_MASK_G | PIPE_MASK_A)); 177} 178 179/* Create a new blend state based on the CSO blend state. 180 * 181 * This encompasses alpha blending, logic/raster ops, and blend dithering. */ 182static void* r300_create_blend_state(struct pipe_context* pipe, 183 const struct pipe_blend_state* state) 184{ 185 struct r300_screen* r300screen = r300_screen(pipe->screen); 186 struct r300_blend_state* blend = CALLOC_STRUCT(r300_blend_state); 187 uint32_t blend_control = 0; /* R300_RB3D_CBLEND: 0x4e04 */ 188 uint32_t alpha_blend_control = 0; /* R300_RB3D_ABLEND: 0x4e08 */ 189 uint32_t color_channel_mask = 0; /* R300_RB3D_COLOR_CHANNEL_MASK: 0x4e0c */ 190 uint32_t rop = 0; /* R300_RB3D_ROPCNTL: 0x4e18 */ 191 uint32_t dither = 0; /* R300_RB3D_DITHER_CTL: 0x4e50 */ 192 CB_LOCALS; 193 194 if (state->rt[0].blend_enable) 195 { 196 unsigned eqRGB = state->rt[0].rgb_func; 197 unsigned srcRGB = state->rt[0].rgb_src_factor; 198 unsigned dstRGB = state->rt[0].rgb_dst_factor; 199 200 unsigned eqA = state->rt[0].alpha_func; 201 unsigned srcA = state->rt[0].alpha_src_factor; 202 unsigned dstA = state->rt[0].alpha_dst_factor; 203 204 /* despite the name, ALPHA_BLEND_ENABLE has nothing to do with alpha, 205 * this is just the crappy D3D naming */ 206 blend_control = R300_ALPHA_BLEND_ENABLE | 207 r300_translate_blend_function(eqRGB) | 208 ( r300_translate_blend_factor(srcRGB) << R300_SRC_BLEND_SHIFT) | 209 ( r300_translate_blend_factor(dstRGB) << R300_DST_BLEND_SHIFT); 210 211 /* Optimization: some operations do not require the destination color. 212 * 213 * When SRC_ALPHA_SATURATE is used, colorbuffer reads must be enabled, 214 * otherwise blending gives incorrect results. It seems to be 215 * a hardware bug. */ 216 if (eqRGB == PIPE_BLEND_MIN || eqA == PIPE_BLEND_MIN || 217 eqRGB == PIPE_BLEND_MAX || eqA == PIPE_BLEND_MAX || 218 dstRGB != PIPE_BLENDFACTOR_ZERO || 219 dstA != PIPE_BLENDFACTOR_ZERO || 220 srcRGB == PIPE_BLENDFACTOR_DST_COLOR || 221 srcRGB == PIPE_BLENDFACTOR_DST_ALPHA || 222 srcRGB == PIPE_BLENDFACTOR_INV_DST_COLOR || 223 srcRGB == PIPE_BLENDFACTOR_INV_DST_ALPHA || 224 srcA == PIPE_BLENDFACTOR_DST_COLOR || 225 srcA == PIPE_BLENDFACTOR_DST_ALPHA || 226 srcA == PIPE_BLENDFACTOR_INV_DST_COLOR || 227 srcA == PIPE_BLENDFACTOR_INV_DST_ALPHA || 228 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE) { 229 /* Enable reading from the colorbuffer. */ 230 blend_control |= R300_READ_ENABLE; 231 232 if (r300screen->caps.is_r500) { 233 /* Optimization: Depending on incoming pixels, we can 234 * conditionally disable the reading in hardware... */ 235 if (eqRGB != PIPE_BLEND_MIN && eqA != PIPE_BLEND_MIN && 236 eqRGB != PIPE_BLEND_MAX && eqA != PIPE_BLEND_MAX) { 237 /* Disable reading if SRC_ALPHA == 0. */ 238 if ((dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA || 239 dstRGB == PIPE_BLENDFACTOR_ZERO) && 240 (dstA == PIPE_BLENDFACTOR_SRC_COLOR || 241 dstA == PIPE_BLENDFACTOR_SRC_ALPHA || 242 dstA == PIPE_BLENDFACTOR_ZERO)) { 243 blend_control |= R500_SRC_ALPHA_0_NO_READ; 244 } 245 246 /* Disable reading if SRC_ALPHA == 1. */ 247 if ((dstRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA || 248 dstRGB == PIPE_BLENDFACTOR_ZERO) && 249 (dstA == PIPE_BLENDFACTOR_INV_SRC_COLOR || 250 dstA == PIPE_BLENDFACTOR_INV_SRC_ALPHA || 251 dstA == PIPE_BLENDFACTOR_ZERO)) { 252 blend_control |= R500_SRC_ALPHA_1_NO_READ; 253 } 254 } 255 } 256 } 257 258 /* Optimization: discard pixels which don't change the colorbuffer. 259 * 260 * The code below is non-trivial and some math is involved. 261 * 262 * Discarding pixels must be disabled when FP16 AA is enabled. 263 * This is a hardware bug. Also, this implementation wouldn't work 264 * with FP blending enabled and equation clamping disabled. 265 * 266 * Equations other than ADD are rarely used and therefore won't be 267 * optimized. */ 268 if ((eqRGB == PIPE_BLEND_ADD || eqRGB == PIPE_BLEND_REVERSE_SUBTRACT) && 269 (eqA == PIPE_BLEND_ADD || eqA == PIPE_BLEND_REVERSE_SUBTRACT)) { 270 /* ADD: X+Y 271 * REVERSE_SUBTRACT: Y-X 272 * 273 * The idea is: 274 * If X = src*srcFactor = 0 and Y = dst*dstFactor = 1, 275 * then CB will not be changed. 276 * 277 * Given the srcFactor and dstFactor variables, we can derive 278 * what src and dst should be equal to and discard appropriate 279 * pixels. 280 */ 281 if (blend_discard_if_src_alpha_0(srcRGB, srcA, dstRGB, dstA)) { 282 blend_control |= R300_DISCARD_SRC_PIXELS_SRC_ALPHA_0; 283 } else if (blend_discard_if_src_alpha_1(srcRGB, srcA, 284 dstRGB, dstA)) { 285 blend_control |= R300_DISCARD_SRC_PIXELS_SRC_ALPHA_1; 286 } else if (blend_discard_if_src_color_0(srcRGB, srcA, 287 dstRGB, dstA)) { 288 blend_control |= R300_DISCARD_SRC_PIXELS_SRC_COLOR_0; 289 } else if (blend_discard_if_src_color_1(srcRGB, srcA, 290 dstRGB, dstA)) { 291 blend_control |= R300_DISCARD_SRC_PIXELS_SRC_COLOR_1; 292 } else if (blend_discard_if_src_alpha_color_0(srcRGB, srcA, 293 dstRGB, dstA)) { 294 blend_control |= 295 R300_DISCARD_SRC_PIXELS_SRC_ALPHA_COLOR_0; 296 } else if (blend_discard_if_src_alpha_color_1(srcRGB, srcA, 297 dstRGB, dstA)) { 298 blend_control |= 299 R300_DISCARD_SRC_PIXELS_SRC_ALPHA_COLOR_1; 300 } 301 } 302 303 /* separate alpha */ 304 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) { 305 blend_control |= R300_SEPARATE_ALPHA_ENABLE; 306 alpha_blend_control = 307 r300_translate_blend_function(eqA) | 308 (r300_translate_blend_factor(srcA) << R300_SRC_BLEND_SHIFT) | 309 (r300_translate_blend_factor(dstA) << R300_DST_BLEND_SHIFT); 310 } 311 } 312 313 /* PIPE_LOGICOP_* don't need to be translated, fortunately. */ 314 if (state->logicop_enable) { 315 rop = R300_RB3D_ROPCNTL_ROP_ENABLE | 316 (state->logicop_func) << R300_RB3D_ROPCNTL_ROP_SHIFT; 317 } 318 319 /* Color channel masks for all MRTs. */ 320 color_channel_mask = bgra_cmask(state->rt[0].colormask); 321 if (r300screen->caps.is_r500 && state->independent_blend_enable) { 322 if (state->rt[1].blend_enable) { 323 color_channel_mask |= bgra_cmask(state->rt[1].colormask) << 4; 324 } 325 if (state->rt[2].blend_enable) { 326 color_channel_mask |= bgra_cmask(state->rt[2].colormask) << 8; 327 } 328 if (state->rt[3].blend_enable) { 329 color_channel_mask |= bgra_cmask(state->rt[3].colormask) << 12; 330 } 331 } 332 333 /* Neither fglrx nor classic r300 ever set this, regardless of dithering 334 * state. Since it's an optional implementation detail, we can leave it 335 * out and never dither. 336 * 337 * This could be revisited if we ever get quality or conformance hints. 338 * 339 if (state->dither) { 340 dither = R300_RB3D_DITHER_CTL_DITHER_MODE_LUT | 341 R300_RB3D_DITHER_CTL_ALPHA_DITHER_MODE_LUT; 342 } 343 */ 344 345 /* Build a command buffer. */ 346 BEGIN_CB(blend->cb, 8); 347 OUT_CB_REG(R300_RB3D_ROPCNTL, rop); 348 OUT_CB_REG_SEQ(R300_RB3D_CBLEND, 3); 349 OUT_CB(blend_control); 350 OUT_CB(alpha_blend_control); 351 OUT_CB(color_channel_mask); 352 OUT_CB_REG(R300_RB3D_DITHER_CTL, dither); 353 END_CB; 354 355 /* The same as above, but with no colorbuffer reads and writes. */ 356 BEGIN_CB(blend->cb_no_readwrite, 8); 357 OUT_CB_REG(R300_RB3D_ROPCNTL, rop); 358 OUT_CB_REG_SEQ(R300_RB3D_CBLEND, 3); 359 OUT_CB(0); 360 OUT_CB(0); 361 OUT_CB(0); 362 OUT_CB_REG(R300_RB3D_DITHER_CTL, dither); 363 END_CB; 364 365 return (void*)blend; 366} 367 368/* Bind blend state. */ 369static void r300_bind_blend_state(struct pipe_context* pipe, 370 void* state) 371{ 372 struct r300_context* r300 = r300_context(pipe); 373 374 UPDATE_STATE(state, r300->blend_state); 375} 376 377/* Free blend state. */ 378static void r300_delete_blend_state(struct pipe_context* pipe, 379 void* state) 380{ 381 FREE(state); 382} 383 384/* Convert float to 10bit integer */ 385static unsigned float_to_fixed10(float f) 386{ 387 return CLAMP((unsigned)(f * 1023.9f), 0, 1023); 388} 389 390/* Set blend color. 391 * Setup both R300 and R500 registers, figure out later which one to write. */ 392static void r300_set_blend_color(struct pipe_context* pipe, 393 const struct pipe_blend_color* color) 394{ 395 struct r300_context* r300 = r300_context(pipe); 396 struct r300_blend_color_state* state = 397 (struct r300_blend_color_state*)r300->blend_color_state.state; 398 CB_LOCALS; 399 400 if (r300->screen->caps.is_r500) { 401 /* XXX if FP16 blending is enabled, we should use the FP16 format */ 402 BEGIN_CB(state->cb, 3); 403 OUT_CB_REG_SEQ(R500_RB3D_CONSTANT_COLOR_AR, 2); 404 OUT_CB(float_to_fixed10(color->color[0]) | 405 (float_to_fixed10(color->color[3]) << 16)); 406 OUT_CB(float_to_fixed10(color->color[2]) | 407 (float_to_fixed10(color->color[1]) << 16)); 408 END_CB; 409 } else { 410 union util_color uc; 411 util_pack_color(color->color, PIPE_FORMAT_B8G8R8A8_UNORM, &uc); 412 413 BEGIN_CB(state->cb, 2); 414 OUT_CB_REG(R300_RB3D_BLEND_COLOR, uc.ui); 415 END_CB; 416 } 417 418 r300->blend_color_state.dirty = TRUE; 419} 420 421static void r300_set_clip_state(struct pipe_context* pipe, 422 const struct pipe_clip_state* state) 423{ 424 struct r300_context* r300 = r300_context(pipe); 425 struct r300_clip_state *clip = 426 (struct r300_clip_state*)r300->clip_state.state; 427 CB_LOCALS; 428 429 clip->clip = *state; 430 431 if (r300->screen->caps.has_tcl) { 432 BEGIN_CB(clip->cb, 29); 433 OUT_CB_REG(R300_VAP_PVS_VECTOR_INDX_REG, 434 (r300->screen->caps.is_r500 ? 435 R500_PVS_UCP_START : R300_PVS_UCP_START)); 436 OUT_CB_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, 6 * 4); 437 OUT_CB_TABLE(state->ucp, 6 * 4); 438 OUT_CB_REG(R300_VAP_CLIP_CNTL, ((1 << state->nr) - 1) | 439 R300_PS_UCP_MODE_CLIP_AS_TRIFAN); 440 END_CB; 441 442 r300->clip_state.dirty = TRUE; 443 } else { 444 draw_flush(r300->draw); 445 draw_set_clip_state(r300->draw, state); 446 } 447} 448 449static void 450r300_set_sample_mask(struct pipe_context *pipe, 451 unsigned sample_mask) 452{ 453} 454 455 456/* Create a new depth, stencil, and alpha state based on the CSO dsa state. 457 * 458 * This contains the depth buffer, stencil buffer, alpha test, and such. 459 * On the Radeon, depth and stencil buffer setup are intertwined, which is 460 * the reason for some of the strange-looking assignments across registers. */ 461static void* 462 r300_create_dsa_state(struct pipe_context* pipe, 463 const struct pipe_depth_stencil_alpha_state* state) 464{ 465 struct r300_capabilities *caps = &r300_screen(pipe->screen)->caps; 466 struct r300_dsa_state* dsa = CALLOC_STRUCT(r300_dsa_state); 467 CB_LOCALS; 468 469 dsa->dsa = *state; 470 471 /* Depth test setup. */ 472 if (state->depth.enabled) { 473 dsa->z_buffer_control |= R300_Z_ENABLE; 474 475 if (state->depth.writemask) { 476 dsa->z_buffer_control |= R300_Z_WRITE_ENABLE; 477 } 478 479 dsa->z_stencil_control |= 480 (r300_translate_depth_stencil_function(state->depth.func) << 481 R300_Z_FUNC_SHIFT); 482 } 483 484 /* Stencil buffer setup. */ 485 if (state->stencil[0].enabled) { 486 dsa->z_buffer_control |= R300_STENCIL_ENABLE; 487 dsa->z_stencil_control |= 488 (r300_translate_depth_stencil_function(state->stencil[0].func) << 489 R300_S_FRONT_FUNC_SHIFT) | 490 (r300_translate_stencil_op(state->stencil[0].fail_op) << 491 R300_S_FRONT_SFAIL_OP_SHIFT) | 492 (r300_translate_stencil_op(state->stencil[0].zpass_op) << 493 R300_S_FRONT_ZPASS_OP_SHIFT) | 494 (r300_translate_stencil_op(state->stencil[0].zfail_op) << 495 R300_S_FRONT_ZFAIL_OP_SHIFT); 496 497 dsa->stencil_ref_mask = 498 (state->stencil[0].valuemask << R300_STENCILMASK_SHIFT) | 499 (state->stencil[0].writemask << R300_STENCILWRITEMASK_SHIFT); 500 501 if (state->stencil[1].enabled) { 502 dsa->two_sided = TRUE; 503 504 dsa->z_buffer_control |= R300_STENCIL_FRONT_BACK; 505 dsa->z_stencil_control |= 506 (r300_translate_depth_stencil_function(state->stencil[1].func) << 507 R300_S_BACK_FUNC_SHIFT) | 508 (r300_translate_stencil_op(state->stencil[1].fail_op) << 509 R300_S_BACK_SFAIL_OP_SHIFT) | 510 (r300_translate_stencil_op(state->stencil[1].zpass_op) << 511 R300_S_BACK_ZPASS_OP_SHIFT) | 512 (r300_translate_stencil_op(state->stencil[1].zfail_op) << 513 R300_S_BACK_ZFAIL_OP_SHIFT); 514 515 dsa->stencil_ref_bf = 516 (state->stencil[1].valuemask << R300_STENCILMASK_SHIFT) | 517 (state->stencil[1].writemask << R300_STENCILWRITEMASK_SHIFT); 518 519 if (caps->is_r500) { 520 dsa->z_buffer_control |= R500_STENCIL_REFMASK_FRONT_BACK; 521 } else { 522 dsa->two_sided_stencil_ref = 523 (state->stencil[0].valuemask != state->stencil[1].valuemask || 524 state->stencil[0].writemask != state->stencil[1].writemask); 525 } 526 } 527 } 528 529 /* Alpha test setup. */ 530 if (state->alpha.enabled) { 531 dsa->alpha_function = 532 r300_translate_alpha_function(state->alpha.func) | 533 R300_FG_ALPHA_FUNC_ENABLE; 534 535 /* We could use 10bit alpha ref but who needs that? */ 536 dsa->alpha_function |= float_to_ubyte(state->alpha.ref_value); 537 538 if (caps->is_r500) 539 dsa->alpha_function |= R500_FG_ALPHA_FUNC_8BIT; 540 } 541 542 BEGIN_CB(&dsa->cb_begin, 8); 543 OUT_CB_REG(R300_FG_ALPHA_FUNC, dsa->alpha_function); 544 OUT_CB_REG_SEQ(R300_ZB_CNTL, 3); 545 OUT_CB(dsa->z_buffer_control); 546 OUT_CB(dsa->z_stencil_control); 547 OUT_CB(dsa->stencil_ref_mask); 548 OUT_CB_REG(R500_ZB_STENCILREFMASK_BF, dsa->stencil_ref_bf); 549 END_CB; 550 551 BEGIN_CB(dsa->cb_no_readwrite, 8); 552 OUT_CB_REG(R300_FG_ALPHA_FUNC, dsa->alpha_function); 553 OUT_CB_REG_SEQ(R300_ZB_CNTL, 3); 554 OUT_CB(0); 555 OUT_CB(0); 556 OUT_CB(0); 557 OUT_CB_REG(R500_ZB_STENCILREFMASK_BF, 0); 558 END_CB; 559 560 return (void*)dsa; 561} 562 563static void r300_dsa_inject_stencilref(struct r300_context *r300) 564{ 565 struct r300_dsa_state *dsa = 566 (struct r300_dsa_state*)r300->dsa_state.state; 567 568 if (!dsa) 569 return; 570 571 dsa->stencil_ref_mask = 572 (dsa->stencil_ref_mask & ~R300_STENCILREF_MASK) | 573 r300->stencil_ref.ref_value[0]; 574 dsa->stencil_ref_bf = 575 (dsa->stencil_ref_bf & ~R300_STENCILREF_MASK) | 576 r300->stencil_ref.ref_value[1]; 577} 578 579/* Bind DSA state. */ 580static void r300_bind_dsa_state(struct pipe_context* pipe, 581 void* state) 582{ 583 struct r300_context* r300 = r300_context(pipe); 584 585 if (!state) { 586 return; 587 } 588 589 UPDATE_STATE(state, r300->dsa_state); 590 591 r300_dsa_inject_stencilref(r300); 592} 593 594/* Free DSA state. */ 595static void r300_delete_dsa_state(struct pipe_context* pipe, 596 void* state) 597{ 598 FREE(state); 599} 600 601static void r300_set_stencil_ref(struct pipe_context* pipe, 602 const struct pipe_stencil_ref* sr) 603{ 604 struct r300_context* r300 = r300_context(pipe); 605 606 r300->stencil_ref = *sr; 607 608 r300_dsa_inject_stencilref(r300); 609 r300->dsa_state.dirty = TRUE; 610} 611 612static void r300_tex_set_tiling_flags(struct r300_context *r300, 613 struct r300_texture *tex, unsigned level) 614{ 615 /* Check if the macrotile flag needs to be changed. 616 * Skip changing the flags otherwise. */ 617 if (tex->mip_macrotile[tex->surface_level] != tex->mip_macrotile[level]) { 618 /* Tiling determines how DRM treats the buffer data. 619 * We must flush CS when changing it if the buffer is referenced. */ 620 if (r300->rws->is_buffer_referenced(r300->rws, tex->buffer, R300_REF_CS)) 621 r300->context.flush(&r300->context, 0, NULL); 622 623 r300->rws->buffer_set_tiling(r300->rws, tex->buffer, 624 tex->pitch[0] * util_format_get_blocksize(tex->b.b.format), 625 tex->microtile, 626 tex->mip_macrotile[level]); 627 628 tex->surface_level = level; 629 } 630} 631 632/* This switcheroo is needed just because of goddamned MACRO_SWITCH. */ 633static void r300_fb_set_tiling_flags(struct r300_context *r300, 634 const struct pipe_framebuffer_state *state) 635{ 636 unsigned i; 637 638 /* Set tiling flags for new surfaces. */ 639 for (i = 0; i < state->nr_cbufs; i++) { 640 r300_tex_set_tiling_flags(r300, 641 r300_texture(state->cbufs[i]->texture), 642 state->cbufs[i]->level); 643 } 644 if (state->zsbuf) { 645 r300_tex_set_tiling_flags(r300, 646 r300_texture(state->zsbuf->texture), 647 state->zsbuf->level); 648 } 649} 650 651static void r300_print_fb_surf_info(struct pipe_surface *surf, unsigned index, 652 const char *binding) 653{ 654 struct pipe_resource *tex = surf->texture; 655 struct r300_texture *rtex = r300_texture(tex); 656 657 fprintf(stderr, 658 "r300: %s[%i] Dim: %ix%i, Offset: %i, ZSlice: %i, " 659 "Face: %i, Level: %i, Format: %s\n" 660 661 "r300: TEX: Macro: %s, Micro: %s, Pitch: %i, " 662 "Dim: %ix%ix%i, LastLevel: %i, Format: %s\n", 663 664 binding, index, surf->width, surf->height, surf->offset, 665 surf->zslice, surf->face, surf->level, 666 util_format_short_name(surf->format), 667 668 rtex->macrotile ? "YES" : " NO", rtex->microtile ? "YES" : " NO", 669 rtex->hwpitch[0], tex->width0, tex->height0, tex->depth0, 670 tex->last_level, util_format_short_name(tex->format)); 671} 672 673static void 674 r300_set_framebuffer_state(struct pipe_context* pipe, 675 const struct pipe_framebuffer_state* state) 676{ 677 struct r300_context* r300 = r300_context(pipe); 678 struct r300_aa_state *aa = (struct r300_aa_state*)r300->aa_state.state; 679 struct pipe_framebuffer_state *old_state = r300->fb_state.state; 680 unsigned max_width, max_height, i; 681 uint32_t zbuffer_bpp = 0; 682 683 if (r300->screen->caps.is_r500) { 684 max_width = max_height = 4096; 685 } else if (r300->screen->caps.is_r400) { 686 max_width = max_height = 4021; 687 } else { 688 max_width = max_height = 2560; 689 } 690 691 if (state->width > max_width || state->height > max_height) { 692 fprintf(stderr, "r300: Implementation error: Render targets are too " 693 "big in %s, refusing to bind framebuffer state!\n", __FUNCTION__); 694 return; 695 } 696 697 if (r300->draw) { 698 draw_flush(r300->draw); 699 } 700 701 r300->gpu_flush.dirty = TRUE; 702 r300->aa_state.dirty = TRUE; 703 r300->fb_state.dirty = TRUE; 704 r300->hyperz_state.dirty = TRUE; 705 r300->fb_state_pipelined.dirty = TRUE; 706 707 /* If nr_cbufs is changed from zero to non-zero or vice versa... */ 708 if (!!old_state->nr_cbufs != !!state->nr_cbufs) { 709 r300->blend_state.dirty = TRUE; 710 } 711 /* If zsbuf is set from NULL to non-NULL or vice versa.. */ 712 if (!!old_state->zsbuf != !!state->zsbuf) { 713 r300->dsa_state.dirty = TRUE; 714 } 715 716 /* The tiling flags are dependent on the surface miplevel, unfortunately. */ 717 r300_fb_set_tiling_flags(r300, state); 718 719 util_assign_framebuffer_state(r300->fb_state.state, state); 720 721 r300->fb_state.size = 722 2 + 723 (8 * state->nr_cbufs) + 724 (state->zsbuf ? (r300->screen->caps.has_hiz ? 18 : 14) : 0); 725 726 /* Polygon offset depends on the zbuffer bit depth. */ 727 if (state->zsbuf && r300->polygon_offset_enabled) { 728 switch (util_format_get_blocksize(state->zsbuf->texture->format)) { 729 case 2: 730 zbuffer_bpp = 16; 731 break; 732 case 4: 733 zbuffer_bpp = 24; 734 break; 735 } 736 737 if (r300->zbuffer_bpp != zbuffer_bpp) { 738 r300->zbuffer_bpp = zbuffer_bpp; 739 r300->rs_state.dirty = TRUE; 740 } 741 } 742 743 /* Set up AA config. */ 744 if (r300->rws->get_value(r300->rws, R300_VID_DRM_2_3_0)) { 745 if (state->nr_cbufs && state->cbufs[0]->texture->nr_samples > 1) { 746 aa->aa_config = R300_GB_AA_CONFIG_AA_ENABLE; 747 748 switch (state->cbufs[0]->texture->nr_samples) { 749 case 2: 750 aa->aa_config |= R300_GB_AA_CONFIG_NUM_AA_SUBSAMPLES_2; 751 break; 752 case 3: 753 aa->aa_config |= R300_GB_AA_CONFIG_NUM_AA_SUBSAMPLES_3; 754 break; 755 case 4: 756 aa->aa_config |= R300_GB_AA_CONFIG_NUM_AA_SUBSAMPLES_4; 757 break; 758 case 6: 759 aa->aa_config |= R300_GB_AA_CONFIG_NUM_AA_SUBSAMPLES_6; 760 break; 761 } 762 } else { 763 aa->aa_config = 0; 764 } 765 } 766 767 if (DBG_ON(r300, DBG_FB)) { 768 fprintf(stderr, "r300: set_framebuffer_state:\n"); 769 for (i = 0; i < state->nr_cbufs; i++) { 770 r300_print_fb_surf_info(state->cbufs[i], i, "CB"); 771 } 772 if (state->zsbuf) { 773 r300_print_fb_surf_info(state->zsbuf, 0, "ZB"); 774 } 775 } 776} 777 778/* Create fragment shader state. */ 779static void* r300_create_fs_state(struct pipe_context* pipe, 780 const struct pipe_shader_state* shader) 781{ 782 struct r300_fragment_shader* fs = NULL; 783 784 fs = (struct r300_fragment_shader*)CALLOC_STRUCT(r300_fragment_shader); 785 786 /* Copy state directly into shader. */ 787 fs->state = *shader; 788 fs->state.tokens = tgsi_dup_tokens(shader->tokens); 789 790 return (void*)fs; 791} 792 793void r300_mark_fs_code_dirty(struct r300_context *r300) 794{ 795 struct r300_fragment_shader* fs = r300_fs(r300); 796 797 r300->fs.dirty = TRUE; 798 r300->fs_rc_constant_state.dirty = TRUE; 799 r300->fs_constants.dirty = TRUE; 800 r300->fs.size = fs->shader->cb_code_size; 801 802 if (r300->screen->caps.is_r500) { 803 r300->fs_rc_constant_state.size = fs->shader->rc_state_count * 7; 804 r300->fs_constants.size = fs->shader->externals_count * 4 + 3; 805 } else { 806 r300->fs_rc_constant_state.size = fs->shader->rc_state_count * 5; 807 r300->fs_constants.size = fs->shader->externals_count * 4 + 1; 808 } 809} 810 811/* Bind fragment shader state. */ 812static void r300_bind_fs_state(struct pipe_context* pipe, void* shader) 813{ 814 struct r300_context* r300 = r300_context(pipe); 815 struct r300_fragment_shader* fs = (struct r300_fragment_shader*)shader; 816 817 if (fs == NULL) { 818 r300->fs.state = NULL; 819 return; 820 } 821 822 r300->fs.state = fs; 823 r300_pick_fragment_shader(r300); 824 r300_mark_fs_code_dirty(r300); 825 826 r300->rs_block_state.dirty = TRUE; /* Will be updated before the emission. */ 827} 828 829/* Delete fragment shader state. */ 830static void r300_delete_fs_state(struct pipe_context* pipe, void* shader) 831{ 832 struct r300_fragment_shader* fs = (struct r300_fragment_shader*)shader; 833 struct r300_fragment_shader_code *tmp, *ptr = fs->first; 834 835 while (ptr) { 836 tmp = ptr; 837 ptr = ptr->next; 838 rc_constants_destroy(&tmp->code.constants); 839 FREE(tmp->cb_code); 840 FREE(tmp); 841 } 842 FREE((void*)fs->state.tokens); 843 FREE(shader); 844} 845 846static void r300_set_polygon_stipple(struct pipe_context* pipe, 847 const struct pipe_poly_stipple* state) 848{ 849 /* XXX no idea how to set this up, but not terribly important */ 850} 851 852/* Create a new rasterizer state based on the CSO rasterizer state. 853 * 854 * This is a very large chunk of state, and covers most of the graphics 855 * backend (GB), geometry assembly (GA), and setup unit (SU) blocks. 856 * 857 * In a not entirely unironic sidenote, this state has nearly nothing to do 858 * with the actual block on the Radeon called the rasterizer (RS). */ 859static void* r300_create_rs_state(struct pipe_context* pipe, 860 const struct pipe_rasterizer_state* state) 861{ 862 struct r300_rs_state* rs = CALLOC_STRUCT(r300_rs_state); 863 int i; 864 float psiz; 865 uint32_t vap_control_status; /* R300_VAP_CNTL_STATUS: 0x2140 */ 866 uint32_t point_size; /* R300_GA_POINT_SIZE: 0x421c */ 867 uint32_t point_minmax; /* R300_GA_POINT_MINMAX: 0x4230 */ 868 uint32_t line_control; /* R300_GA_LINE_CNTL: 0x4234 */ 869 uint32_t polygon_offset_enable; /* R300_SU_POLY_OFFSET_ENABLE: 0x42b4 */ 870 uint32_t cull_mode; /* R300_SU_CULL_MODE: 0x42b8 */ 871 uint32_t line_stipple_config; /* R300_GA_LINE_STIPPLE_CONFIG: 0x4328 */ 872 uint32_t line_stipple_value; /* R300_GA_LINE_STIPPLE_VALUE: 0x4260 */ 873 uint32_t polygon_mode; /* R300_GA_POLY_MODE: 0x4288 */ 874 uint32_t clip_rule; /* R300_SC_CLIP_RULE: 0x43D0 */ 875 876 /* Specifies top of Raster pipe specific enable controls, 877 * i.e. texture coordinates stuffing for points, lines, triangles */ 878 uint32_t stuffing_enable; /* R300_GB_ENABLE: 0x4008 */ 879 880 /* Point sprites texture coordinates, 0: lower left, 1: upper right */ 881 float point_texcoord_left; /* R300_GA_POINT_S0: 0x4200 */ 882 float point_texcoord_bottom; /* R300_GA_POINT_T0: 0x4204 */ 883 float point_texcoord_right; /* R300_GA_POINT_S1: 0x4208 */ 884 float point_texcoord_top; /* R300_GA_POINT_T1: 0x420c */ 885 CB_LOCALS; 886 887 /* Copy rasterizer state. */ 888 rs->rs = *state; 889 rs->rs_draw = *state; 890 891 /* Override some states for Draw. */ 892 rs->rs_draw.sprite_coord_enable = 0; /* We can do this in HW. */ 893 894#ifdef PIPE_ARCH_LITTLE_ENDIAN 895 vap_control_status = R300_VC_NO_SWAP; 896#else 897 vap_control_status = R300_VC_32BIT_SWAP; 898#endif 899 900 /* If no TCL engine is present, turn off the HW TCL. */ 901 if (!r300_screen(pipe->screen)->caps.has_tcl) { 902 vap_control_status |= R300_VAP_TCL_BYPASS; 903 } 904 905 /* Point size width and height. */ 906 point_size = 907 pack_float_16_6x(state->point_size) | 908 (pack_float_16_6x(state->point_size) << R300_POINTSIZE_X_SHIFT); 909 910 /* Point size clamping. */ 911 if (state->point_size_per_vertex) { 912 /* Per-vertex point size. 913 * Clamp to [0, max FB size] */ 914 psiz = pipe->screen->get_paramf(pipe->screen, 915 PIPE_CAP_MAX_POINT_WIDTH); 916 point_minmax = 917 pack_float_16_6x(psiz) << R300_GA_POINT_MINMAX_MAX_SHIFT; 918 } else { 919 /* We cannot disable the point-size vertex output, 920 * so clamp it. */ 921 psiz = state->point_size; 922 point_minmax = 923 (pack_float_16_6x(psiz) << R300_GA_POINT_MINMAX_MIN_SHIFT) | 924 (pack_float_16_6x(psiz) << R300_GA_POINT_MINMAX_MAX_SHIFT); 925 } 926 927 /* Line control. */ 928 line_control = pack_float_16_6x(state->line_width) | 929 R300_GA_LINE_CNTL_END_TYPE_COMP; 930 931 /* Enable polygon mode */ 932 polygon_mode = 0; 933 if (state->fill_front != PIPE_POLYGON_MODE_FILL || 934 state->fill_back != PIPE_POLYGON_MODE_FILL) { 935 polygon_mode = R300_GA_POLY_MODE_DUAL; 936 } 937 938 /* Front face */ 939 if (state->front_ccw) 940 cull_mode = R300_FRONT_FACE_CCW; 941 else 942 cull_mode = R300_FRONT_FACE_CW; 943 944 /* Polygon offset */ 945 polygon_offset_enable = 0; 946 if (util_get_offset(state, state->fill_front)) { 947 polygon_offset_enable |= R300_FRONT_ENABLE; 948 } 949 if (util_get_offset(state, state->fill_back)) { 950 polygon_offset_enable |= R300_BACK_ENABLE; 951 } 952 953 rs->polygon_offset_enable = polygon_offset_enable != 0; 954 955 /* Polygon mode */ 956 if (polygon_mode) { 957 polygon_mode |= 958 r300_translate_polygon_mode_front(state->fill_front); 959 polygon_mode |= 960 r300_translate_polygon_mode_back(state->fill_back); 961 } 962 963 if (state->cull_face & PIPE_FACE_FRONT) { 964 cull_mode |= R300_CULL_FRONT; 965 } 966 if (state->cull_face & PIPE_FACE_BACK) { 967 cull_mode |= R300_CULL_BACK; 968 } 969 970 if (state->line_stipple_enable) { 971 line_stipple_config = 972 R300_GA_LINE_STIPPLE_CONFIG_LINE_RESET_LINE | 973 (fui((float)state->line_stipple_factor) & 974 R300_GA_LINE_STIPPLE_CONFIG_STIPPLE_SCALE_MASK); 975 /* XXX this might need to be scaled up */ 976 line_stipple_value = state->line_stipple_pattern; 977 } 978 979 if (state->flatshade) { 980 rs->color_control = R300_SHADE_MODEL_FLAT; 981 } else { 982 rs->color_control = R300_SHADE_MODEL_SMOOTH; 983 } 984 985 clip_rule = state->scissor ? 0xAAAA : 0xFFFF; 986 987 /* Point sprites */ 988 stuffing_enable = 0; 989 if (state->sprite_coord_enable) { 990 stuffing_enable = R300_GB_POINT_STUFF_ENABLE; 991 for (i = 0; i < 8; i++) { 992 if (state->sprite_coord_enable & (1 << i)) 993 stuffing_enable |= 994 R300_GB_TEX_STR << (R300_GB_TEX0_SOURCE_SHIFT + (i*2)); 995 } 996 997 point_texcoord_left = 0.0f; 998 point_texcoord_right = 1.0f; 999 1000 switch (state->sprite_coord_mode) { 1001 case PIPE_SPRITE_COORD_UPPER_LEFT: 1002 point_texcoord_top = 0.0f; 1003 point_texcoord_bottom = 1.0f; 1004 break; 1005 case PIPE_SPRITE_COORD_LOWER_LEFT: 1006 point_texcoord_top = 1.0f; 1007 point_texcoord_bottom = 0.0f; 1008 break; 1009 } 1010 } 1011 1012 /* Build the main command buffer. */ 1013 BEGIN_CB(rs->cb_main, 25); 1014 OUT_CB_REG(R300_VAP_CNTL_STATUS, vap_control_status); 1015 OUT_CB_REG(R300_GA_POINT_SIZE, point_size); 1016 OUT_CB_REG_SEQ(R300_GA_POINT_MINMAX, 2); 1017 OUT_CB(point_minmax); 1018 OUT_CB(line_control); 1019 OUT_CB_REG_SEQ(R300_SU_POLY_OFFSET_ENABLE, 2); 1020 OUT_CB(polygon_offset_enable); 1021 rs->cull_mode_index = 9; 1022 OUT_CB(cull_mode); 1023 OUT_CB_REG(R300_GA_LINE_STIPPLE_CONFIG, line_stipple_config); 1024 OUT_CB_REG(R300_GA_LINE_STIPPLE_VALUE, line_stipple_value); 1025 OUT_CB_REG(R300_GA_POLY_MODE, polygon_mode); 1026 OUT_CB_REG(R300_SC_CLIP_RULE, clip_rule); 1027 OUT_CB_REG(R300_GB_ENABLE, stuffing_enable); 1028 OUT_CB_REG_SEQ(R300_GA_POINT_S0, 4); 1029 OUT_CB_32F(point_texcoord_left); 1030 OUT_CB_32F(point_texcoord_bottom); 1031 OUT_CB_32F(point_texcoord_right); 1032 OUT_CB_32F(point_texcoord_top); 1033 END_CB; 1034 1035 /* Build the two command buffers for polygon offset setup. */ 1036 if (polygon_offset_enable) { 1037 float scale = state->offset_scale * 12; 1038 float offset = state->offset_units * 4; 1039 1040 BEGIN_CB(rs->cb_poly_offset_zb16, 5); 1041 OUT_CB_REG_SEQ(R300_SU_POLY_OFFSET_FRONT_SCALE, 4); 1042 OUT_CB_32F(scale); 1043 OUT_CB_32F(offset); 1044 OUT_CB_32F(scale); 1045 OUT_CB_32F(offset); 1046 END_CB; 1047 1048 offset = state->offset_units * 2; 1049 1050 BEGIN_CB(rs->cb_poly_offset_zb24, 5); 1051 OUT_CB_REG_SEQ(R300_SU_POLY_OFFSET_FRONT_SCALE, 4); 1052 OUT_CB_32F(scale); 1053 OUT_CB_32F(offset); 1054 OUT_CB_32F(scale); 1055 OUT_CB_32F(offset); 1056 END_CB; 1057 } 1058 1059 return (void*)rs; 1060} 1061 1062/* Bind rasterizer state. */ 1063static void r300_bind_rs_state(struct pipe_context* pipe, void* state) 1064{ 1065 struct r300_context* r300 = r300_context(pipe); 1066 struct r300_rs_state* rs = (struct r300_rs_state*)state; 1067 int last_sprite_coord_enable = r300->sprite_coord_enable; 1068 boolean last_two_sided_color = r300->two_sided_color; 1069 1070 if (r300->draw && rs) { 1071 draw_flush(r300->draw); 1072 draw_set_rasterizer_state(r300->draw, &rs->rs_draw, state); 1073 } 1074 1075 if (rs) { 1076 r300->polygon_offset_enabled = (rs->rs.offset_point || 1077 rs->rs.offset_line || 1078 rs->rs.offset_tri); 1079 r300->sprite_coord_enable = rs->rs.sprite_coord_enable; 1080 r300->two_sided_color = rs->rs.light_twoside; 1081 } else { 1082 r300->polygon_offset_enabled = FALSE; 1083 r300->sprite_coord_enable = 0; 1084 r300->two_sided_color = FALSE; 1085 } 1086 1087 UPDATE_STATE(state, r300->rs_state); 1088 r300->rs_state.size = 25 + (r300->polygon_offset_enabled ? 5 : 0); 1089 1090 if (last_sprite_coord_enable != r300->sprite_coord_enable || 1091 last_two_sided_color != r300->two_sided_color) { 1092 r300->rs_block_state.dirty = TRUE; 1093 } 1094} 1095 1096/* Free rasterizer state. */ 1097static void r300_delete_rs_state(struct pipe_context* pipe, void* state) 1098{ 1099 FREE(state); 1100} 1101 1102static void* 1103 r300_create_sampler_state(struct pipe_context* pipe, 1104 const struct pipe_sampler_state* state) 1105{ 1106 struct r300_context* r300 = r300_context(pipe); 1107 struct r300_sampler_state* sampler = CALLOC_STRUCT(r300_sampler_state); 1108 boolean is_r500 = r300->screen->caps.is_r500; 1109 int lod_bias; 1110 union util_color uc; 1111 1112 sampler->state = *state; 1113 1114 /* r300 doesn't handle CLAMP and MIRROR_CLAMP correctly when either MAG 1115 * or MIN filter is NEAREST. Since texwrap produces same results 1116 * for CLAMP and CLAMP_TO_EDGE, we use them instead. */ 1117 if (sampler->state.min_img_filter == PIPE_TEX_FILTER_NEAREST || 1118 sampler->state.mag_img_filter == PIPE_TEX_FILTER_NEAREST) { 1119 /* Wrap S. */ 1120 if (sampler->state.wrap_s == PIPE_TEX_WRAP_CLAMP) 1121 sampler->state.wrap_s = PIPE_TEX_WRAP_CLAMP_TO_EDGE; 1122 else if (sampler->state.wrap_s == PIPE_TEX_WRAP_MIRROR_CLAMP) 1123 sampler->state.wrap_s = PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE; 1124 1125 /* Wrap T. */ 1126 if (sampler->state.wrap_t == PIPE_TEX_WRAP_CLAMP) 1127 sampler->state.wrap_t = PIPE_TEX_WRAP_CLAMP_TO_EDGE; 1128 else if (sampler->state.wrap_t == PIPE_TEX_WRAP_MIRROR_CLAMP) 1129 sampler->state.wrap_t = PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE; 1130 1131 /* Wrap R. */ 1132 if (sampler->state.wrap_r == PIPE_TEX_WRAP_CLAMP) 1133 sampler->state.wrap_r = PIPE_TEX_WRAP_CLAMP_TO_EDGE; 1134 else if (sampler->state.wrap_r == PIPE_TEX_WRAP_MIRROR_CLAMP) 1135 sampler->state.wrap_r = PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE; 1136 } 1137 1138 sampler->filter0 |= 1139 (r300_translate_wrap(sampler->state.wrap_s) << R300_TX_WRAP_S_SHIFT) | 1140 (r300_translate_wrap(sampler->state.wrap_t) << R300_TX_WRAP_T_SHIFT) | 1141 (r300_translate_wrap(sampler->state.wrap_r) << R300_TX_WRAP_R_SHIFT); 1142 1143 sampler->filter0 |= r300_translate_tex_filters(state->min_img_filter, 1144 state->mag_img_filter, 1145 state->min_mip_filter, 1146 state->max_anisotropy > 0); 1147 1148 sampler->filter0 |= r300_anisotropy(state->max_anisotropy); 1149 1150 /* Unfortunately, r300-r500 don't support floating-point mipmap lods. */ 1151 /* We must pass these to the merge function to clamp them properly. */ 1152 sampler->min_lod = MAX2((unsigned)state->min_lod, 0); 1153 sampler->max_lod = MAX2((unsigned)ceilf(state->max_lod), 0); 1154 1155 lod_bias = CLAMP((int)(state->lod_bias * 32 + 1), -(1 << 9), (1 << 9) - 1); 1156 1157 sampler->filter1 |= lod_bias << R300_LOD_BIAS_SHIFT; 1158 1159 /* This is very high quality anisotropic filtering for R5xx. 1160 * It's good for benchmarking the performance of texturing but 1161 * in practice we don't want to slow down the driver because it's 1162 * a pretty good performance killer. Feel free to play with it. */ 1163 if (DBG_ON(r300, DBG_ANISOHQ) && is_r500) { 1164 sampler->filter1 |= r500_anisotropy(state->max_anisotropy); 1165 } 1166 1167 util_pack_color(state->border_color, PIPE_FORMAT_B8G8R8A8_UNORM, &uc); 1168 sampler->border_color = uc.ui; 1169 1170 /* R500-specific fixups and optimizations */ 1171 if (r300->screen->caps.is_r500) { 1172 sampler->filter1 |= R500_BORDER_FIX; 1173 } 1174 1175 return (void*)sampler; 1176} 1177 1178static void r300_bind_sampler_states(struct pipe_context* pipe, 1179 unsigned count, 1180 void** states) 1181{ 1182 struct r300_context* r300 = r300_context(pipe); 1183 struct r300_textures_state* state = 1184 (struct r300_textures_state*)r300->textures_state.state; 1185 unsigned tex_units = r300->screen->caps.num_tex_units; 1186 1187 if (count > tex_units) { 1188 return; 1189 } 1190 1191 memcpy(state->sampler_states, states, sizeof(void*) * count); 1192 state->sampler_state_count = count; 1193 1194 r300->textures_state.dirty = TRUE; 1195} 1196 1197static void r300_lacks_vertex_textures(struct pipe_context* pipe, 1198 unsigned count, 1199 void** states) 1200{ 1201} 1202 1203static void r300_delete_sampler_state(struct pipe_context* pipe, void* state) 1204{ 1205 FREE(state); 1206} 1207 1208static uint32_t r300_assign_texture_cache_region(unsigned index, unsigned num) 1209{ 1210 /* This looks like a hack, but I believe it's suppose to work like 1211 * that. To illustrate how this works, let's assume you have 5 textures. 1212 * From docs, 5 and the successive numbers are: 1213 * 1214 * FOURTH_1 = 5 1215 * FOURTH_2 = 6 1216 * FOURTH_3 = 7 1217 * EIGHTH_0 = 8 1218 * EIGHTH_1 = 9 1219 * 1220 * First 3 textures will get 3/4 of size of the cache, divived evenly 1221 * between them. The last 1/4 of the cache must be divided between 1222 * the last 2 textures, each will therefore get 1/8 of the cache. 1223 * Why not just to use "5 + texture_index" ? 1224 * 1225 * This simple trick works for all "num" <= 16. 1226 */ 1227 if (num <= 1) 1228 return R300_TX_CACHE(R300_TX_CACHE_WHOLE); 1229 else 1230 return R300_TX_CACHE(num + index); 1231} 1232 1233static void r300_set_fragment_sampler_views(struct pipe_context* pipe, 1234 unsigned count, 1235 struct pipe_sampler_view** views) 1236{ 1237 struct r300_context* r300 = r300_context(pipe); 1238 struct r300_textures_state* state = 1239 (struct r300_textures_state*)r300->textures_state.state; 1240 struct r300_texture *texture; 1241 unsigned i, real_num_views = 0, view_index = 0; 1242 unsigned tex_units = r300->screen->caps.num_tex_units; 1243 boolean dirty_tex = FALSE; 1244 1245 if (count > tex_units) { 1246 return; 1247 } 1248 1249 /* Calculate the real number of views. */ 1250 for (i = 0; i < count; i++) { 1251 if (views[i]) 1252 real_num_views++; 1253 } 1254 1255 for (i = 0; i < count; i++) { 1256 if (&state->sampler_views[i]->base != views[i]) { 1257 pipe_sampler_view_reference( 1258 (struct pipe_sampler_view**)&state->sampler_views[i], 1259 views[i]); 1260 1261 if (!views[i]) { 1262 continue; 1263 } 1264 1265 /* A new sampler view (= texture)... */ 1266 dirty_tex = TRUE; 1267 1268 /* Set the texrect factor in the fragment shader. 1269 * Needed for RECT and NPOT fallback. */ 1270 texture = r300_texture(views[i]->texture); 1271 if (texture->uses_pitch) { 1272 r300->fs_rc_constant_state.dirty = TRUE; 1273 } 1274 1275 state->sampler_views[i]->texcache_region = 1276 r300_assign_texture_cache_region(view_index, real_num_views); 1277 view_index++; 1278 } 1279 } 1280 1281 for (i = count; i < tex_units; i++) { 1282 if (state->sampler_views[i]) { 1283 pipe_sampler_view_reference( 1284 (struct pipe_sampler_view**)&state->sampler_views[i], 1285 NULL); 1286 } 1287 } 1288 1289 state->sampler_view_count = count; 1290 1291 r300->textures_state.dirty = TRUE; 1292 1293 if (dirty_tex) { 1294 r300->texture_cache_inval.dirty = TRUE; 1295 } 1296} 1297 1298static struct pipe_sampler_view * 1299r300_create_sampler_view(struct pipe_context *pipe, 1300 struct pipe_resource *texture, 1301 const struct pipe_sampler_view *templ) 1302{ 1303 struct r300_sampler_view *view = CALLOC_STRUCT(r300_sampler_view); 1304 struct r300_texture *tex = r300_texture(texture); 1305 1306 if (view) { 1307 view->base = *templ; 1308 view->base.reference.count = 1; 1309 view->base.context = pipe; 1310 view->base.texture = NULL; 1311 pipe_resource_reference(&view->base.texture, texture); 1312 1313 view->swizzle[0] = templ->swizzle_r; 1314 view->swizzle[1] = templ->swizzle_g; 1315 view->swizzle[2] = templ->swizzle_b; 1316 view->swizzle[3] = templ->swizzle_a; 1317 1318 view->format = tex->tx_format; 1319 view->format.format1 |= r300_translate_texformat(templ->format, 1320 view->swizzle); 1321 if (r300_screen(pipe->screen)->caps.is_r500) { 1322 view->format.format2 |= r500_tx_format_msb_bit(templ->format); 1323 } 1324 } 1325 1326 return (struct pipe_sampler_view*)view; 1327} 1328 1329static void 1330r300_sampler_view_destroy(struct pipe_context *pipe, 1331 struct pipe_sampler_view *view) 1332{ 1333 pipe_resource_reference(&view->texture, NULL); 1334 FREE(view); 1335} 1336 1337static void r300_set_scissor_state(struct pipe_context* pipe, 1338 const struct pipe_scissor_state* state) 1339{ 1340 struct r300_context* r300 = r300_context(pipe); 1341 1342 memcpy(r300->scissor_state.state, state, 1343 sizeof(struct pipe_scissor_state)); 1344 1345 r300->scissor_state.dirty = TRUE; 1346} 1347 1348static void r300_set_viewport_state(struct pipe_context* pipe, 1349 const struct pipe_viewport_state* state) 1350{ 1351 struct r300_context* r300 = r300_context(pipe); 1352 struct r300_viewport_state* viewport = 1353 (struct r300_viewport_state*)r300->viewport_state.state; 1354 1355 r300->viewport = *state; 1356 1357 if (r300->draw) { 1358 draw_flush(r300->draw); 1359 draw_set_viewport_state(r300->draw, state); 1360 viewport->vte_control = R300_VTX_XY_FMT | R300_VTX_Z_FMT; 1361 return; 1362 } 1363 1364 /* Do the transform in HW. */ 1365 viewport->vte_control = R300_VTX_W0_FMT; 1366 1367 if (state->scale[0] != 1.0f) { 1368 viewport->xscale = state->scale[0]; 1369 viewport->vte_control |= R300_VPORT_X_SCALE_ENA; 1370 } 1371 if (state->scale[1] != 1.0f) { 1372 viewport->yscale = state->scale[1]; 1373 viewport->vte_control |= R300_VPORT_Y_SCALE_ENA; 1374 } 1375 if (state->scale[2] != 1.0f) { 1376 viewport->zscale = state->scale[2]; 1377 viewport->vte_control |= R300_VPORT_Z_SCALE_ENA; 1378 } 1379 if (state->translate[0] != 0.0f) { 1380 viewport->xoffset = state->translate[0]; 1381 viewport->vte_control |= R300_VPORT_X_OFFSET_ENA; 1382 } 1383 if (state->translate[1] != 0.0f) { 1384 viewport->yoffset = state->translate[1]; 1385 viewport->vte_control |= R300_VPORT_Y_OFFSET_ENA; 1386 } 1387 if (state->translate[2] != 0.0f) { 1388 viewport->zoffset = state->translate[2]; 1389 viewport->vte_control |= R300_VPORT_Z_OFFSET_ENA; 1390 } 1391 1392 r300->viewport_state.dirty = TRUE; 1393 if (r300->fs.state && r300_fs(r300)->shader->inputs.wpos != ATTR_UNUSED) { 1394 r300->fs_rc_constant_state.dirty = TRUE; 1395 } 1396} 1397 1398static void r300_set_vertex_buffers(struct pipe_context* pipe, 1399 unsigned count, 1400 const struct pipe_vertex_buffer* buffers) 1401{ 1402 struct r300_context* r300 = r300_context(pipe); 1403 struct pipe_vertex_buffer *vbo; 1404 unsigned i, max_index = (1 << 24) - 1; 1405 boolean any_user_buffer = FALSE; 1406 1407 if (count == r300->vertex_buffer_count && 1408 memcmp(r300->vertex_buffer, buffers, 1409 sizeof(struct pipe_vertex_buffer) * count) == 0) { 1410 return; 1411 } 1412 1413 if (r300->screen->caps.has_tcl) { 1414 /* HW TCL. */ 1415 r300->incompatible_vb_layout = FALSE; 1416 1417 /* Check if the strides and offsets are aligned to the size of DWORD. */ 1418 for (i = 0; i < count; i++) { 1419 if (buffers[i].buffer) { 1420 if (buffers[i].stride % 4 != 0 || 1421 buffers[i].buffer_offset % 4 != 0) { 1422 r300->incompatible_vb_layout = TRUE; 1423 break; 1424 } 1425 } 1426 } 1427 1428 for (i = 0; i < count; i++) { 1429 /* Why, yes, I AM casting away constness. How did you know? */ 1430 vbo = (struct pipe_vertex_buffer*)&buffers[i]; 1431 1432 /* Skip NULL buffers */ 1433 if (!buffers[i].buffer) { 1434 continue; 1435 } 1436 1437 if (r300_buffer_is_user_buffer(vbo->buffer)) { 1438 any_user_buffer = TRUE; 1439 } 1440 1441 if (vbo->max_index == ~0) { 1442 /* if no VBO stride then only one vertex value so max index is 1 */ 1443 /* should think about converting to VS constants like svga does */ 1444 if (!vbo->stride) 1445 vbo->max_index = 1; 1446 else 1447 vbo->max_index = 1448 (vbo->buffer->width0 - vbo->buffer_offset) / vbo->stride; 1449 } 1450 1451 max_index = MIN2(vbo->max_index, max_index); 1452 } 1453 1454 r300->any_user_vbs = any_user_buffer; 1455 r300->vertex_buffer_max_index = max_index; 1456 1457 } else { 1458 /* SW TCL. */ 1459 draw_flush(r300->draw); 1460 draw_set_vertex_buffers(r300->draw, count, buffers); 1461 } 1462 1463 /* Common code. */ 1464 for (i = 0; i < count; i++) { 1465 /* Reference our buffer. */ 1466 pipe_resource_reference(&r300->vertex_buffer[i].buffer, buffers[i].buffer); 1467 } 1468 for (; i < r300->vertex_buffer_count; i++) { 1469 /* Dereference any old buffers. */ 1470 pipe_resource_reference(&r300->vertex_buffer[i].buffer, NULL); 1471 } 1472 1473 memcpy(r300->vertex_buffer, buffers, 1474 sizeof(struct pipe_vertex_buffer) * count); 1475 r300->vertex_buffer_count = count; 1476} 1477 1478/* Initialize the PSC tables. */ 1479static void r300_vertex_psc(struct r300_vertex_element_state *velems) 1480{ 1481 struct r300_vertex_stream_state *vstream = &velems->vertex_stream; 1482 uint16_t type, swizzle; 1483 enum pipe_format format; 1484 unsigned i; 1485 1486 if (velems->count > 16) { 1487 fprintf(stderr, "r300: More than 16 vertex elements are not supported," 1488 " requested %i, using 16.\n", velems->count); 1489 velems->count = 16; 1490 } 1491 1492 /* Vertex shaders have no semantics on their inputs, 1493 * so PSC should just route stuff based on the vertex elements, 1494 * and not on attrib information. */ 1495 for (i = 0; i < velems->count; i++) { 1496 format = velems->hw_format[i]; 1497 1498 type = r300_translate_vertex_data_type(format); 1499 if (type == R300_INVALID_FORMAT) { 1500 fprintf(stderr, "r300: Bad vertex format %s.\n", 1501 util_format_short_name(format)); 1502 assert(0); 1503 abort(); 1504 } 1505 1506 type |= i << R300_DST_VEC_LOC_SHIFT; 1507 swizzle = r300_translate_vertex_data_swizzle(format); 1508 1509 if (i & 1) { 1510 vstream->vap_prog_stream_cntl[i >> 1] |= type << 16; 1511 vstream->vap_prog_stream_cntl_ext[i >> 1] |= swizzle << 16; 1512 } else { 1513 vstream->vap_prog_stream_cntl[i >> 1] |= type; 1514 vstream->vap_prog_stream_cntl_ext[i >> 1] |= swizzle; 1515 } 1516 } 1517 1518 /* Set the last vector in the PSC. */ 1519 if (i) { 1520 i -= 1; 1521 } 1522 vstream->vap_prog_stream_cntl[i >> 1] |= 1523 (R300_LAST_VEC << (i & 1 ? 16 : 0)); 1524 1525 vstream->count = (i >> 1) + 1; 1526} 1527 1528#define FORMAT_REPLACE(what, withwhat) \ 1529 case PIPE_FORMAT_##what: *format = PIPE_FORMAT_##withwhat; break 1530 1531static void* r300_create_vertex_elements_state(struct pipe_context* pipe, 1532 unsigned count, 1533 const struct pipe_vertex_element* attribs) 1534{ 1535 struct r300_vertex_element_state *velems; 1536 unsigned i; 1537 enum pipe_format *format; 1538 1539 assert(count <= PIPE_MAX_ATTRIBS); 1540 velems = CALLOC_STRUCT(r300_vertex_element_state); 1541 if (velems != NULL) { 1542 velems->count = count; 1543 memcpy(velems->velem, attribs, sizeof(struct pipe_vertex_element) * count); 1544 1545 if (r300_screen(pipe->screen)->caps.has_tcl) { 1546 /* Set the best hw format in case the original format is not 1547 * supported by hw. */ 1548 for (i = 0; i < count; i++) { 1549 velems->hw_format[i] = velems->velem[i].src_format; 1550 format = &velems->hw_format[i]; 1551 1552 /* This is basically the list of unsupported formats. 1553 * For now we don't care about the alignment, that's going to 1554 * be sorted out after the PSC setup. */ 1555 switch (*format) { 1556 FORMAT_REPLACE(R64_FLOAT, R32_FLOAT); 1557 FORMAT_REPLACE(R64G64_FLOAT, R32G32_FLOAT); 1558 FORMAT_REPLACE(R64G64B64_FLOAT, R32G32B32_FLOAT); 1559 FORMAT_REPLACE(R64G64B64A64_FLOAT, R32G32B32A32_FLOAT); 1560 1561 FORMAT_REPLACE(R32_UNORM, R32_FLOAT); 1562 FORMAT_REPLACE(R32G32_UNORM, R32G32_FLOAT); 1563 FORMAT_REPLACE(R32G32B32_UNORM, R32G32B32_FLOAT); 1564 FORMAT_REPLACE(R32G32B32A32_UNORM, R32G32B32A32_FLOAT); 1565 1566 FORMAT_REPLACE(R32_USCALED, R32_FLOAT); 1567 FORMAT_REPLACE(R32G32_USCALED, R32G32_FLOAT); 1568 FORMAT_REPLACE(R32G32B32_USCALED, R32G32B32_FLOAT); 1569 FORMAT_REPLACE(R32G32B32A32_USCALED,R32G32B32A32_FLOAT); 1570 1571 FORMAT_REPLACE(R32_SNORM, R32_FLOAT); 1572 FORMAT_REPLACE(R32G32_SNORM, R32G32_FLOAT); 1573 FORMAT_REPLACE(R32G32B32_SNORM, R32G32B32_FLOAT); 1574 FORMAT_REPLACE(R32G32B32A32_SNORM, R32G32B32A32_FLOAT); 1575 1576 FORMAT_REPLACE(R32_SSCALED, R32_FLOAT); 1577 FORMAT_REPLACE(R32G32_SSCALED, R32G32_FLOAT); 1578 FORMAT_REPLACE(R32G32B32_SSCALED, R32G32B32_FLOAT); 1579 FORMAT_REPLACE(R32G32B32A32_SSCALED,R32G32B32A32_FLOAT); 1580 1581 FORMAT_REPLACE(R32_FIXED, R32_FLOAT); 1582 FORMAT_REPLACE(R32G32_FIXED, R32G32_FLOAT); 1583 FORMAT_REPLACE(R32G32B32_FIXED, R32G32B32_FLOAT); 1584 FORMAT_REPLACE(R32G32B32A32_FIXED, R32G32B32A32_FLOAT); 1585 1586 default:; 1587 } 1588 1589 velems->incompatible_layout = 1590 velems->incompatible_layout || 1591 velems->velem[i].src_format != velems->hw_format[i] || 1592 velems->velem[i].src_offset % 4 != 0; 1593 } 1594 1595 /* Now setup PSC. 1596 * The unused components will be replaced by (..., 0, 1). */ 1597 r300_vertex_psc(velems); 1598 1599 /* Align the formats to the size of DWORD. 1600 * We only care about the blocksizes of the formats since 1601 * swizzles are already set up. 1602 * Also compute the vertex size. */ 1603 for (i = 0; i < count; i++) { 1604 /* This is OK because we check for aligned strides too. */ 1605 velems->hw_format_size[i] = 1606 align(util_format_get_blocksize(velems->hw_format[i]), 4); 1607 velems->vertex_size_dwords += velems->hw_format_size[i] / 4; 1608 } 1609 } 1610 } 1611 return velems; 1612} 1613 1614static void r300_bind_vertex_elements_state(struct pipe_context *pipe, 1615 void *state) 1616{ 1617 struct r300_context *r300 = r300_context(pipe); 1618 struct r300_vertex_element_state *velems = state; 1619 1620 if (velems == NULL) { 1621 return; 1622 } 1623 1624 r300->velems = velems; 1625 1626 if (r300->draw) { 1627 draw_flush(r300->draw); 1628 draw_set_vertex_elements(r300->draw, velems->count, velems->velem); 1629 return; 1630 } 1631 1632 UPDATE_STATE(&velems->vertex_stream, r300->vertex_stream_state); 1633 r300->vertex_stream_state.size = (1 + velems->vertex_stream.count) * 2; 1634} 1635 1636static void r300_delete_vertex_elements_state(struct pipe_context *pipe, void *state) 1637{ 1638 FREE(state); 1639} 1640 1641static void* r300_create_vs_state(struct pipe_context* pipe, 1642 const struct pipe_shader_state* shader) 1643{ 1644 struct r300_context* r300 = r300_context(pipe); 1645 struct r300_vertex_shader* vs = CALLOC_STRUCT(r300_vertex_shader); 1646 1647 /* Copy state directly into shader. */ 1648 vs->state = *shader; 1649 vs->state.tokens = tgsi_dup_tokens(shader->tokens); 1650 1651 if (r300->screen->caps.has_tcl) { 1652 r300_init_vs_outputs(vs); 1653 r300_translate_vertex_shader(r300, vs); 1654 } else { 1655 r300_draw_init_vertex_shader(r300->draw, vs); 1656 } 1657 1658 return vs; 1659} 1660 1661static void r300_bind_vs_state(struct pipe_context* pipe, void* shader) 1662{ 1663 struct r300_context* r300 = r300_context(pipe); 1664 struct r300_vertex_shader* vs = (struct r300_vertex_shader*)shader; 1665 1666 if (vs == NULL) { 1667 r300->vs_state.state = NULL; 1668 return; 1669 } 1670 if (vs == r300->vs_state.state) { 1671 return; 1672 } 1673 r300->vs_state.state = vs; 1674 1675 /* The majority of the RS block bits is dependent on the vertex shader. */ 1676 r300->rs_block_state.dirty = TRUE; /* Will be updated before the emission. */ 1677 1678 if (r300->screen->caps.has_tcl) { 1679 r300->vs_state.dirty = TRUE; 1680 r300->vs_state.size = 1681 vs->code.length + 9 + 1682 (vs->immediates_count ? vs->immediates_count * 4 + 3 : 0); 1683 1684 if (vs->externals_count) { 1685 r300->vs_constants.dirty = TRUE; 1686 r300->vs_constants.size = vs->externals_count * 4 + 3; 1687 } else { 1688 r300->vs_constants.size = 0; 1689 } 1690 1691 r300->pvs_flush.dirty = TRUE; 1692 } else { 1693 draw_flush(r300->draw); 1694 draw_bind_vertex_shader(r300->draw, 1695 (struct draw_vertex_shader*)vs->draw_vs); 1696 } 1697} 1698 1699static void r300_delete_vs_state(struct pipe_context* pipe, void* shader) 1700{ 1701 struct r300_context* r300 = r300_context(pipe); 1702 struct r300_vertex_shader* vs = (struct r300_vertex_shader*)shader; 1703 1704 if (r300->screen->caps.has_tcl) { 1705 rc_constants_destroy(&vs->code.constants); 1706 } else { 1707 draw_delete_vertex_shader(r300->draw, 1708 (struct draw_vertex_shader*)vs->draw_vs); 1709 } 1710 1711 FREE((void*)vs->state.tokens); 1712 FREE(shader); 1713} 1714 1715static void r300_set_constant_buffer(struct pipe_context *pipe, 1716 uint shader, uint index, 1717 struct pipe_resource *buf) 1718{ 1719 struct r300_context* r300 = r300_context(pipe); 1720 struct r300_constant_buffer *cbuf; 1721 struct pipe_transfer *tr; 1722 float *mapped; 1723 int max_size = 0, max_size_bytes = 0, clamped_size = 0; 1724 1725 switch (shader) { 1726 case PIPE_SHADER_VERTEX: 1727 cbuf = (struct r300_constant_buffer*)r300->vs_constants.state; 1728 max_size = 256; 1729 break; 1730 case PIPE_SHADER_FRAGMENT: 1731 cbuf = (struct r300_constant_buffer*)r300->fs_constants.state; 1732 if (r300->screen->caps.is_r500) { 1733 max_size = 256; 1734 } else { 1735 max_size = 32; 1736 } 1737 break; 1738 default: 1739 assert(0); 1740 return; 1741 } 1742 max_size_bytes = max_size * 4 * sizeof(float); 1743 1744 if (buf == NULL || buf->width0 == 0 || 1745 (mapped = pipe_buffer_map(pipe, buf, PIPE_TRANSFER_READ, &tr)) == NULL) 1746 { 1747 cbuf->count = 0; 1748 return; 1749 } 1750 1751 if (shader == PIPE_SHADER_FRAGMENT || 1752 (shader == PIPE_SHADER_VERTEX && r300->screen->caps.has_tcl)) { 1753 assert((buf->width0 % (4 * sizeof(float))) == 0); 1754 1755 /* Check the size of the constant buffer. */ 1756 /* XXX Subtract immediates and RC_STATE_* variables. */ 1757 if (buf->width0 > max_size_bytes) { 1758 fprintf(stderr, "r300: Max size of the constant buffer is " 1759 "%i*4 floats.\n", max_size); 1760 } 1761 1762 clamped_size = MIN2(buf->width0, max_size_bytes); 1763 cbuf->count = clamped_size / (4 * sizeof(float)); 1764 1765 if (shader == PIPE_SHADER_FRAGMENT && !r300->screen->caps.is_r500) { 1766 unsigned i,j; 1767 1768 /* Convert constants to float24. */ 1769 for (i = 0; i < cbuf->count; i++) 1770 for (j = 0; j < 4; j++) 1771 cbuf->constants[i][j] = pack_float24(mapped[i*4+j]); 1772 } else { 1773 memcpy(cbuf->constants, mapped, clamped_size); 1774 } 1775 } 1776 1777 if (shader == PIPE_SHADER_VERTEX) { 1778 if (r300->screen->caps.has_tcl) { 1779 if (r300->vs_constants.size) { 1780 r300->vs_constants.dirty = TRUE; 1781 } 1782 r300->pvs_flush.dirty = TRUE; 1783 } else if (r300->draw) { 1784 draw_set_mapped_constant_buffer(r300->draw, PIPE_SHADER_VERTEX, 1785 0, mapped, buf->width0); 1786 } 1787 } else if (shader == PIPE_SHADER_FRAGMENT) { 1788 r300->fs_constants.dirty = TRUE; 1789 } 1790 1791 pipe_buffer_unmap(pipe, buf, tr); 1792} 1793 1794void r300_init_state_functions(struct r300_context* r300) 1795{ 1796 r300->context.create_blend_state = r300_create_blend_state; 1797 r300->context.bind_blend_state = r300_bind_blend_state; 1798 r300->context.delete_blend_state = r300_delete_blend_state; 1799 1800 r300->context.set_blend_color = r300_set_blend_color; 1801 1802 r300->context.set_clip_state = r300_set_clip_state; 1803 r300->context.set_sample_mask = r300_set_sample_mask; 1804 1805 r300->context.set_constant_buffer = r300_set_constant_buffer; 1806 1807 r300->context.create_depth_stencil_alpha_state = r300_create_dsa_state; 1808 r300->context.bind_depth_stencil_alpha_state = r300_bind_dsa_state; 1809 r300->context.delete_depth_stencil_alpha_state = r300_delete_dsa_state; 1810 1811 r300->context.set_stencil_ref = r300_set_stencil_ref; 1812 1813 r300->context.set_framebuffer_state = r300_set_framebuffer_state; 1814 1815 r300->context.create_fs_state = r300_create_fs_state; 1816 r300->context.bind_fs_state = r300_bind_fs_state; 1817 r300->context.delete_fs_state = r300_delete_fs_state; 1818 1819 r300->context.set_polygon_stipple = r300_set_polygon_stipple; 1820 1821 r300->context.create_rasterizer_state = r300_create_rs_state; 1822 r300->context.bind_rasterizer_state = r300_bind_rs_state; 1823 r300->context.delete_rasterizer_state = r300_delete_rs_state; 1824 1825 r300->context.create_sampler_state = r300_create_sampler_state; 1826 r300->context.bind_fragment_sampler_states = r300_bind_sampler_states; 1827 r300->context.bind_vertex_sampler_states = r300_lacks_vertex_textures; 1828 r300->context.delete_sampler_state = r300_delete_sampler_state; 1829 1830 r300->context.set_fragment_sampler_views = r300_set_fragment_sampler_views; 1831 r300->context.create_sampler_view = r300_create_sampler_view; 1832 r300->context.sampler_view_destroy = r300_sampler_view_destroy; 1833 1834 r300->context.set_scissor_state = r300_set_scissor_state; 1835 1836 r300->context.set_viewport_state = r300_set_viewport_state; 1837 1838 r300->context.set_vertex_buffers = r300_set_vertex_buffers; 1839 1840 r300->context.create_vertex_elements_state = r300_create_vertex_elements_state; 1841 r300->context.bind_vertex_elements_state = r300_bind_vertex_elements_state; 1842 r300->context.delete_vertex_elements_state = r300_delete_vertex_elements_state; 1843 1844 r300->context.create_vs_state = r300_create_vs_state; 1845 r300->context.bind_vs_state = r300_bind_vs_state; 1846 r300->context.delete_vs_state = r300_delete_vs_state; 1847} 1848