r300_state.c revision 6f2936c654c68388b9c43a189a1b8c06f3a9d241
1/* 2 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com> 3 * Copyright 2009 Marek Olšák <maraeo@gmail.com> 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * on the rights to use, copy, modify, merge, publish, distribute, sub 9 * license, and/or sell copies of the Software, and to permit persons to whom 10 * the Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, 20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 22 * USE OR OTHER DEALINGS IN THE SOFTWARE. */ 23 24#include "draw/draw_context.h" 25 26#include "util/u_blitter.h" 27#include "util/u_math.h" 28#include "util/u_memory.h" 29#include "util/u_pack_color.h" 30 31#include "tgsi/tgsi_parse.h" 32 33#include "pipe/p_config.h" 34 35#include "r300_cb.h" 36#include "r300_context.h" 37#include "r300_emit.h" 38#include "r300_reg.h" 39#include "r300_screen.h" 40#include "r300_screen_buffer.h" 41#include "r300_state_inlines.h" 42#include "r300_fs.h" 43#include "r300_texture.h" 44#include "r300_vs.h" 45#include "r300_winsys.h" 46 47/* r300_state: Functions used to intialize state context by translating 48 * Gallium state objects into semi-native r300 state objects. */ 49 50#define UPDATE_STATE(cso, atom) \ 51 if (cso != atom.state) { \ 52 atom.state = cso; \ 53 atom.dirty = TRUE; \ 54 } 55 56static boolean blend_discard_if_src_alpha_0(unsigned srcRGB, unsigned srcA, 57 unsigned dstRGB, unsigned dstA) 58{ 59 /* If the blend equation is ADD or REVERSE_SUBTRACT, 60 * SRC_ALPHA == 0, and the following state is set, the colorbuffer 61 * will not be changed. 62 * Notice that the dst factors are the src factors inverted. */ 63 return (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA || 64 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE || 65 srcRGB == PIPE_BLENDFACTOR_ZERO) && 66 (srcA == PIPE_BLENDFACTOR_SRC_COLOR || 67 srcA == PIPE_BLENDFACTOR_SRC_ALPHA || 68 srcA == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE || 69 srcA == PIPE_BLENDFACTOR_ZERO) && 70 (dstRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA || 71 dstRGB == PIPE_BLENDFACTOR_ONE) && 72 (dstA == PIPE_BLENDFACTOR_INV_SRC_COLOR || 73 dstA == PIPE_BLENDFACTOR_INV_SRC_ALPHA || 74 dstA == PIPE_BLENDFACTOR_ONE); 75} 76 77static boolean blend_discard_if_src_alpha_1(unsigned srcRGB, unsigned srcA, 78 unsigned dstRGB, unsigned dstA) 79{ 80 /* If the blend equation is ADD or REVERSE_SUBTRACT, 81 * SRC_ALPHA == 1, and the following state is set, the colorbuffer 82 * will not be changed. 83 * Notice that the dst factors are the src factors inverted. */ 84 return (srcRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA || 85 srcRGB == PIPE_BLENDFACTOR_ZERO) && 86 (srcA == PIPE_BLENDFACTOR_INV_SRC_COLOR || 87 srcA == PIPE_BLENDFACTOR_INV_SRC_ALPHA || 88 srcA == PIPE_BLENDFACTOR_ZERO) && 89 (dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA || 90 dstRGB == PIPE_BLENDFACTOR_ONE) && 91 (dstA == PIPE_BLENDFACTOR_SRC_COLOR || 92 dstA == PIPE_BLENDFACTOR_SRC_ALPHA || 93 dstA == PIPE_BLENDFACTOR_ONE); 94} 95 96static boolean blend_discard_if_src_color_0(unsigned srcRGB, unsigned srcA, 97 unsigned dstRGB, unsigned dstA) 98{ 99 /* If the blend equation is ADD or REVERSE_SUBTRACT, 100 * SRC_COLOR == (0,0,0), and the following state is set, the colorbuffer 101 * will not be changed. 102 * Notice that the dst factors are the src factors inverted. */ 103 return (srcRGB == PIPE_BLENDFACTOR_SRC_COLOR || 104 srcRGB == PIPE_BLENDFACTOR_ZERO) && 105 (srcA == PIPE_BLENDFACTOR_ZERO) && 106 (dstRGB == PIPE_BLENDFACTOR_INV_SRC_COLOR || 107 dstRGB == PIPE_BLENDFACTOR_ONE) && 108 (dstA == PIPE_BLENDFACTOR_ONE); 109} 110 111static boolean blend_discard_if_src_color_1(unsigned srcRGB, unsigned srcA, 112 unsigned dstRGB, unsigned dstA) 113{ 114 /* If the blend equation is ADD or REVERSE_SUBTRACT, 115 * SRC_COLOR == (1,1,1), and the following state is set, the colorbuffer 116 * will not be changed. 117 * Notice that the dst factors are the src factors inverted. */ 118 return (srcRGB == PIPE_BLENDFACTOR_INV_SRC_COLOR || 119 srcRGB == PIPE_BLENDFACTOR_ZERO) && 120 (srcA == PIPE_BLENDFACTOR_ZERO) && 121 (dstRGB == PIPE_BLENDFACTOR_SRC_COLOR || 122 dstRGB == PIPE_BLENDFACTOR_ONE) && 123 (dstA == PIPE_BLENDFACTOR_ONE); 124} 125 126static boolean blend_discard_if_src_alpha_color_0(unsigned srcRGB, unsigned srcA, 127 unsigned dstRGB, unsigned dstA) 128{ 129 /* If the blend equation is ADD or REVERSE_SUBTRACT, 130 * SRC_ALPHA_COLOR == (0,0,0,0), and the following state is set, 131 * the colorbuffer will not be changed. 132 * Notice that the dst factors are the src factors inverted. */ 133 return (srcRGB == PIPE_BLENDFACTOR_SRC_COLOR || 134 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA || 135 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE || 136 srcRGB == PIPE_BLENDFACTOR_ZERO) && 137 (srcA == PIPE_BLENDFACTOR_SRC_COLOR || 138 srcA == PIPE_BLENDFACTOR_SRC_ALPHA || 139 srcA == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE || 140 srcA == PIPE_BLENDFACTOR_ZERO) && 141 (dstRGB == PIPE_BLENDFACTOR_INV_SRC_COLOR || 142 dstRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA || 143 dstRGB == PIPE_BLENDFACTOR_ONE) && 144 (dstA == PIPE_BLENDFACTOR_INV_SRC_COLOR || 145 dstA == PIPE_BLENDFACTOR_INV_SRC_ALPHA || 146 dstA == PIPE_BLENDFACTOR_ONE); 147} 148 149static boolean blend_discard_if_src_alpha_color_1(unsigned srcRGB, unsigned srcA, 150 unsigned dstRGB, unsigned dstA) 151{ 152 /* If the blend equation is ADD or REVERSE_SUBTRACT, 153 * SRC_ALPHA_COLOR == (1,1,1,1), and the following state is set, 154 * the colorbuffer will not be changed. 155 * Notice that the dst factors are the src factors inverted. */ 156 return (srcRGB == PIPE_BLENDFACTOR_INV_SRC_COLOR || 157 srcRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA || 158 srcRGB == PIPE_BLENDFACTOR_ZERO) && 159 (srcA == PIPE_BLENDFACTOR_INV_SRC_COLOR || 160 srcA == PIPE_BLENDFACTOR_INV_SRC_ALPHA || 161 srcA == PIPE_BLENDFACTOR_ZERO) && 162 (dstRGB == PIPE_BLENDFACTOR_SRC_COLOR || 163 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA || 164 dstRGB == PIPE_BLENDFACTOR_ONE) && 165 (dstA == PIPE_BLENDFACTOR_SRC_COLOR || 166 dstA == PIPE_BLENDFACTOR_SRC_ALPHA || 167 dstA == PIPE_BLENDFACTOR_ONE); 168} 169 170static unsigned bgra_cmask(unsigned mask) 171{ 172 /* Gallium uses RGBA color ordering while R300 expects BGRA. */ 173 174 return ((mask & PIPE_MASK_R) << 2) | 175 ((mask & PIPE_MASK_B) >> 2) | 176 (mask & (PIPE_MASK_G | PIPE_MASK_A)); 177} 178 179/* Create a new blend state based on the CSO blend state. 180 * 181 * This encompasses alpha blending, logic/raster ops, and blend dithering. */ 182static void* r300_create_blend_state(struct pipe_context* pipe, 183 const struct pipe_blend_state* state) 184{ 185 struct r300_screen* r300screen = r300_screen(pipe->screen); 186 struct r300_blend_state* blend = CALLOC_STRUCT(r300_blend_state); 187 uint32_t blend_control = 0; /* R300_RB3D_CBLEND: 0x4e04 */ 188 uint32_t alpha_blend_control = 0; /* R300_RB3D_ABLEND: 0x4e08 */ 189 uint32_t color_channel_mask = 0; /* R300_RB3D_COLOR_CHANNEL_MASK: 0x4e0c */ 190 uint32_t rop = 0; /* R300_RB3D_ROPCNTL: 0x4e18 */ 191 uint32_t dither = 0; /* R300_RB3D_DITHER_CTL: 0x4e50 */ 192 CB_LOCALS; 193 194 if (state->rt[0].blend_enable) 195 { 196 unsigned eqRGB = state->rt[0].rgb_func; 197 unsigned srcRGB = state->rt[0].rgb_src_factor; 198 unsigned dstRGB = state->rt[0].rgb_dst_factor; 199 200 unsigned eqA = state->rt[0].alpha_func; 201 unsigned srcA = state->rt[0].alpha_src_factor; 202 unsigned dstA = state->rt[0].alpha_dst_factor; 203 204 /* despite the name, ALPHA_BLEND_ENABLE has nothing to do with alpha, 205 * this is just the crappy D3D naming */ 206 blend_control = R300_ALPHA_BLEND_ENABLE | 207 r300_translate_blend_function(eqRGB) | 208 ( r300_translate_blend_factor(srcRGB) << R300_SRC_BLEND_SHIFT) | 209 ( r300_translate_blend_factor(dstRGB) << R300_DST_BLEND_SHIFT); 210 211 /* Optimization: some operations do not require the destination color. 212 * 213 * When SRC_ALPHA_SATURATE is used, colorbuffer reads must be enabled, 214 * otherwise blending gives incorrect results. It seems to be 215 * a hardware bug. */ 216 if (eqRGB == PIPE_BLEND_MIN || eqA == PIPE_BLEND_MIN || 217 eqRGB == PIPE_BLEND_MAX || eqA == PIPE_BLEND_MAX || 218 dstRGB != PIPE_BLENDFACTOR_ZERO || 219 dstA != PIPE_BLENDFACTOR_ZERO || 220 srcRGB == PIPE_BLENDFACTOR_DST_COLOR || 221 srcRGB == PIPE_BLENDFACTOR_DST_ALPHA || 222 srcRGB == PIPE_BLENDFACTOR_INV_DST_COLOR || 223 srcRGB == PIPE_BLENDFACTOR_INV_DST_ALPHA || 224 srcA == PIPE_BLENDFACTOR_DST_COLOR || 225 srcA == PIPE_BLENDFACTOR_DST_ALPHA || 226 srcA == PIPE_BLENDFACTOR_INV_DST_COLOR || 227 srcA == PIPE_BLENDFACTOR_INV_DST_ALPHA || 228 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE) { 229 /* Enable reading from the colorbuffer. */ 230 blend_control |= R300_READ_ENABLE; 231 232 if (r300screen->caps.is_r500) { 233 /* Optimization: Depending on incoming pixels, we can 234 * conditionally disable the reading in hardware... */ 235 if (eqRGB != PIPE_BLEND_MIN && eqA != PIPE_BLEND_MIN && 236 eqRGB != PIPE_BLEND_MAX && eqA != PIPE_BLEND_MAX) { 237 /* Disable reading if SRC_ALPHA == 0. */ 238 if ((dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA || 239 dstRGB == PIPE_BLENDFACTOR_ZERO) && 240 (dstA == PIPE_BLENDFACTOR_SRC_COLOR || 241 dstA == PIPE_BLENDFACTOR_SRC_ALPHA || 242 dstA == PIPE_BLENDFACTOR_ZERO)) { 243 blend_control |= R500_SRC_ALPHA_0_NO_READ; 244 } 245 246 /* Disable reading if SRC_ALPHA == 1. */ 247 if ((dstRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA || 248 dstRGB == PIPE_BLENDFACTOR_ZERO) && 249 (dstA == PIPE_BLENDFACTOR_INV_SRC_COLOR || 250 dstA == PIPE_BLENDFACTOR_INV_SRC_ALPHA || 251 dstA == PIPE_BLENDFACTOR_ZERO)) { 252 blend_control |= R500_SRC_ALPHA_1_NO_READ; 253 } 254 } 255 } 256 } 257 258 /* Optimization: discard pixels which don't change the colorbuffer. 259 * 260 * The code below is non-trivial and some math is involved. 261 * 262 * Discarding pixels must be disabled when FP16 AA is enabled. 263 * This is a hardware bug. Also, this implementation wouldn't work 264 * with FP blending enabled and equation clamping disabled. 265 * 266 * Equations other than ADD are rarely used and therefore won't be 267 * optimized. */ 268 if ((eqRGB == PIPE_BLEND_ADD || eqRGB == PIPE_BLEND_REVERSE_SUBTRACT) && 269 (eqA == PIPE_BLEND_ADD || eqA == PIPE_BLEND_REVERSE_SUBTRACT)) { 270 /* ADD: X+Y 271 * REVERSE_SUBTRACT: Y-X 272 * 273 * The idea is: 274 * If X = src*srcFactor = 0 and Y = dst*dstFactor = 1, 275 * then CB will not be changed. 276 * 277 * Given the srcFactor and dstFactor variables, we can derive 278 * what src and dst should be equal to and discard appropriate 279 * pixels. 280 */ 281 if (blend_discard_if_src_alpha_0(srcRGB, srcA, dstRGB, dstA)) { 282 blend_control |= R300_DISCARD_SRC_PIXELS_SRC_ALPHA_0; 283 } else if (blend_discard_if_src_alpha_1(srcRGB, srcA, 284 dstRGB, dstA)) { 285 blend_control |= R300_DISCARD_SRC_PIXELS_SRC_ALPHA_1; 286 } else if (blend_discard_if_src_color_0(srcRGB, srcA, 287 dstRGB, dstA)) { 288 blend_control |= R300_DISCARD_SRC_PIXELS_SRC_COLOR_0; 289 } else if (blend_discard_if_src_color_1(srcRGB, srcA, 290 dstRGB, dstA)) { 291 blend_control |= R300_DISCARD_SRC_PIXELS_SRC_COLOR_1; 292 } else if (blend_discard_if_src_alpha_color_0(srcRGB, srcA, 293 dstRGB, dstA)) { 294 blend_control |= 295 R300_DISCARD_SRC_PIXELS_SRC_ALPHA_COLOR_0; 296 } else if (blend_discard_if_src_alpha_color_1(srcRGB, srcA, 297 dstRGB, dstA)) { 298 blend_control |= 299 R300_DISCARD_SRC_PIXELS_SRC_ALPHA_COLOR_1; 300 } 301 } 302 303 /* separate alpha */ 304 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) { 305 blend_control |= R300_SEPARATE_ALPHA_ENABLE; 306 alpha_blend_control = 307 r300_translate_blend_function(eqA) | 308 (r300_translate_blend_factor(srcA) << R300_SRC_BLEND_SHIFT) | 309 (r300_translate_blend_factor(dstA) << R300_DST_BLEND_SHIFT); 310 } 311 } 312 313 /* PIPE_LOGICOP_* don't need to be translated, fortunately. */ 314 if (state->logicop_enable) { 315 rop = R300_RB3D_ROPCNTL_ROP_ENABLE | 316 (state->logicop_func) << R300_RB3D_ROPCNTL_ROP_SHIFT; 317 } 318 319 /* Color channel masks for all MRTs. */ 320 color_channel_mask = bgra_cmask(state->rt[0].colormask); 321 if (r300screen->caps.is_r500 && state->independent_blend_enable) { 322 if (state->rt[1].blend_enable) { 323 color_channel_mask |= bgra_cmask(state->rt[1].colormask) << 4; 324 } 325 if (state->rt[2].blend_enable) { 326 color_channel_mask |= bgra_cmask(state->rt[2].colormask) << 8; 327 } 328 if (state->rt[3].blend_enable) { 329 color_channel_mask |= bgra_cmask(state->rt[3].colormask) << 12; 330 } 331 } 332 333 /* Neither fglrx nor classic r300 ever set this, regardless of dithering 334 * state. Since it's an optional implementation detail, we can leave it 335 * out and never dither. 336 * 337 * This could be revisited if we ever get quality or conformance hints. 338 * 339 if (state->dither) { 340 dither = R300_RB3D_DITHER_CTL_DITHER_MODE_LUT | 341 R300_RB3D_DITHER_CTL_ALPHA_DITHER_MODE_LUT; 342 } 343 */ 344 345 /* Build a command buffer. */ 346 BEGIN_CB(blend->cb, 8); 347 OUT_CB_REG(R300_RB3D_ROPCNTL, rop); 348 OUT_CB_REG_SEQ(R300_RB3D_CBLEND, 3); 349 OUT_CB(blend_control); 350 OUT_CB(alpha_blend_control); 351 OUT_CB(color_channel_mask); 352 OUT_CB_REG(R300_RB3D_DITHER_CTL, dither); 353 END_CB; 354 355 /* The same as above, but with no colorbuffer reads and writes. */ 356 BEGIN_CB(blend->cb_no_readwrite, 8); 357 OUT_CB_REG(R300_RB3D_ROPCNTL, rop); 358 OUT_CB_REG_SEQ(R300_RB3D_CBLEND, 3); 359 OUT_CB(0); 360 OUT_CB(0); 361 OUT_CB(0); 362 OUT_CB_REG(R300_RB3D_DITHER_CTL, dither); 363 END_CB; 364 365 return (void*)blend; 366} 367 368/* Bind blend state. */ 369static void r300_bind_blend_state(struct pipe_context* pipe, 370 void* state) 371{ 372 struct r300_context* r300 = r300_context(pipe); 373 374 UPDATE_STATE(state, r300->blend_state); 375} 376 377/* Free blend state. */ 378static void r300_delete_blend_state(struct pipe_context* pipe, 379 void* state) 380{ 381 FREE(state); 382} 383 384/* Convert float to 10bit integer */ 385static unsigned float_to_fixed10(float f) 386{ 387 return CLAMP((unsigned)(f * 1023.9f), 0, 1023); 388} 389 390/* Set blend color. 391 * Setup both R300 and R500 registers, figure out later which one to write. */ 392static void r300_set_blend_color(struct pipe_context* pipe, 393 const struct pipe_blend_color* color) 394{ 395 struct r300_context* r300 = r300_context(pipe); 396 struct r300_blend_color_state* state = 397 (struct r300_blend_color_state*)r300->blend_color_state.state; 398 CB_LOCALS; 399 400 if (r300->screen->caps.is_r500) { 401 /* XXX if FP16 blending is enabled, we should use the FP16 format */ 402 BEGIN_CB(state->cb, 3); 403 OUT_CB_REG_SEQ(R500_RB3D_CONSTANT_COLOR_AR, 2); 404 OUT_CB(float_to_fixed10(color->color[0]) | 405 (float_to_fixed10(color->color[3]) << 16)); 406 OUT_CB(float_to_fixed10(color->color[2]) | 407 (float_to_fixed10(color->color[1]) << 16)); 408 END_CB; 409 } else { 410 union util_color uc; 411 util_pack_color(color->color, PIPE_FORMAT_B8G8R8A8_UNORM, &uc); 412 413 BEGIN_CB(state->cb, 2); 414 OUT_CB_REG(R300_RB3D_BLEND_COLOR, uc.ui); 415 END_CB; 416 } 417 418 r300->blend_color_state.dirty = TRUE; 419} 420 421static void r300_set_clip_state(struct pipe_context* pipe, 422 const struct pipe_clip_state* state) 423{ 424 struct r300_context* r300 = r300_context(pipe); 425 struct r300_clip_state *clip = 426 (struct r300_clip_state*)r300->clip_state.state; 427 CB_LOCALS; 428 429 clip->clip = *state; 430 431 if (r300->screen->caps.has_tcl) { 432 r300->clip_state.size = 2 + !!state->nr * 3 + state->nr * 4; 433 434 BEGIN_CB(clip->cb, r300->clip_state.size); 435 if (state->nr) { 436 OUT_CB_REG(R300_VAP_PVS_VECTOR_INDX_REG, 437 (r300->screen->caps.is_r500 ? 438 R500_PVS_UCP_START : R300_PVS_UCP_START)); 439 OUT_CB_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, state->nr * 4); 440 OUT_CB_TABLE(state->ucp, state->nr * 4); 441 } 442 OUT_CB_REG(R300_VAP_CLIP_CNTL, ((1 << state->nr) - 1) | 443 R300_PS_UCP_MODE_CLIP_AS_TRIFAN | 444 (state->depth_clamp ? R300_CLIP_DISABLE : 0)); 445 END_CB; 446 447 r300->clip_state.dirty = TRUE; 448 } else { 449 draw_flush(r300->draw); 450 draw_set_clip_state(r300->draw, state); 451 } 452} 453 454static void 455r300_set_sample_mask(struct pipe_context *pipe, 456 unsigned sample_mask) 457{ 458} 459 460 461/* Create a new depth, stencil, and alpha state based on the CSO dsa state. 462 * 463 * This contains the depth buffer, stencil buffer, alpha test, and such. 464 * On the Radeon, depth and stencil buffer setup are intertwined, which is 465 * the reason for some of the strange-looking assignments across registers. */ 466static void* 467 r300_create_dsa_state(struct pipe_context* pipe, 468 const struct pipe_depth_stencil_alpha_state* state) 469{ 470 struct r300_capabilities *caps = &r300_screen(pipe->screen)->caps; 471 struct r300_dsa_state* dsa = CALLOC_STRUCT(r300_dsa_state); 472 CB_LOCALS; 473 474 dsa->dsa = *state; 475 476 /* Depth test setup. */ 477 if (state->depth.enabled) { 478 dsa->z_buffer_control |= R300_Z_ENABLE; 479 480 if (state->depth.writemask) { 481 dsa->z_buffer_control |= R300_Z_WRITE_ENABLE; 482 } 483 484 dsa->z_stencil_control |= 485 (r300_translate_depth_stencil_function(state->depth.func) << 486 R300_Z_FUNC_SHIFT); 487 } 488 489 /* Stencil buffer setup. */ 490 if (state->stencil[0].enabled) { 491 dsa->z_buffer_control |= R300_STENCIL_ENABLE; 492 dsa->z_stencil_control |= 493 (r300_translate_depth_stencil_function(state->stencil[0].func) << 494 R300_S_FRONT_FUNC_SHIFT) | 495 (r300_translate_stencil_op(state->stencil[0].fail_op) << 496 R300_S_FRONT_SFAIL_OP_SHIFT) | 497 (r300_translate_stencil_op(state->stencil[0].zpass_op) << 498 R300_S_FRONT_ZPASS_OP_SHIFT) | 499 (r300_translate_stencil_op(state->stencil[0].zfail_op) << 500 R300_S_FRONT_ZFAIL_OP_SHIFT); 501 502 dsa->stencil_ref_mask = 503 (state->stencil[0].valuemask << R300_STENCILMASK_SHIFT) | 504 (state->stencil[0].writemask << R300_STENCILWRITEMASK_SHIFT); 505 506 if (state->stencil[1].enabled) { 507 dsa->two_sided = TRUE; 508 509 dsa->z_buffer_control |= R300_STENCIL_FRONT_BACK; 510 dsa->z_stencil_control |= 511 (r300_translate_depth_stencil_function(state->stencil[1].func) << 512 R300_S_BACK_FUNC_SHIFT) | 513 (r300_translate_stencil_op(state->stencil[1].fail_op) << 514 R300_S_BACK_SFAIL_OP_SHIFT) | 515 (r300_translate_stencil_op(state->stencil[1].zpass_op) << 516 R300_S_BACK_ZPASS_OP_SHIFT) | 517 (r300_translate_stencil_op(state->stencil[1].zfail_op) << 518 R300_S_BACK_ZFAIL_OP_SHIFT); 519 520 dsa->stencil_ref_bf = 521 (state->stencil[1].valuemask << R300_STENCILMASK_SHIFT) | 522 (state->stencil[1].writemask << R300_STENCILWRITEMASK_SHIFT); 523 524 if (caps->is_r500) { 525 dsa->z_buffer_control |= R500_STENCIL_REFMASK_FRONT_BACK; 526 } else { 527 dsa->two_sided_stencil_ref = 528 (state->stencil[0].valuemask != state->stencil[1].valuemask || 529 state->stencil[0].writemask != state->stencil[1].writemask); 530 } 531 } 532 } 533 534 /* Alpha test setup. */ 535 if (state->alpha.enabled) { 536 dsa->alpha_function = 537 r300_translate_alpha_function(state->alpha.func) | 538 R300_FG_ALPHA_FUNC_ENABLE; 539 540 /* We could use 10bit alpha ref but who needs that? */ 541 dsa->alpha_function |= float_to_ubyte(state->alpha.ref_value); 542 543 if (caps->is_r500) 544 dsa->alpha_function |= R500_FG_ALPHA_FUNC_8BIT; 545 } 546 547 BEGIN_CB(&dsa->cb_begin, 8); 548 OUT_CB_REG(R300_FG_ALPHA_FUNC, dsa->alpha_function); 549 OUT_CB_REG_SEQ(R300_ZB_CNTL, 3); 550 OUT_CB(dsa->z_buffer_control); 551 OUT_CB(dsa->z_stencil_control); 552 OUT_CB(dsa->stencil_ref_mask); 553 OUT_CB_REG(R500_ZB_STENCILREFMASK_BF, dsa->stencil_ref_bf); 554 END_CB; 555 556 BEGIN_CB(dsa->cb_no_readwrite, 8); 557 OUT_CB_REG(R300_FG_ALPHA_FUNC, dsa->alpha_function); 558 OUT_CB_REG_SEQ(R300_ZB_CNTL, 3); 559 OUT_CB(0); 560 OUT_CB(0); 561 OUT_CB(0); 562 OUT_CB_REG(R500_ZB_STENCILREFMASK_BF, 0); 563 END_CB; 564 565 return (void*)dsa; 566} 567 568static void r300_dsa_inject_stencilref(struct r300_context *r300) 569{ 570 struct r300_dsa_state *dsa = 571 (struct r300_dsa_state*)r300->dsa_state.state; 572 573 if (!dsa) 574 return; 575 576 dsa->stencil_ref_mask = 577 (dsa->stencil_ref_mask & ~R300_STENCILREF_MASK) | 578 r300->stencil_ref.ref_value[0]; 579 dsa->stencil_ref_bf = 580 (dsa->stencil_ref_bf & ~R300_STENCILREF_MASK) | 581 r300->stencil_ref.ref_value[1]; 582} 583 584/* Bind DSA state. */ 585static void r300_bind_dsa_state(struct pipe_context* pipe, 586 void* state) 587{ 588 struct r300_context* r300 = r300_context(pipe); 589 590 if (!state) { 591 return; 592 } 593 594 UPDATE_STATE(state, r300->dsa_state); 595 596 r300_dsa_inject_stencilref(r300); 597} 598 599/* Free DSA state. */ 600static void r300_delete_dsa_state(struct pipe_context* pipe, 601 void* state) 602{ 603 FREE(state); 604} 605 606static void r300_set_stencil_ref(struct pipe_context* pipe, 607 const struct pipe_stencil_ref* sr) 608{ 609 struct r300_context* r300 = r300_context(pipe); 610 611 r300->stencil_ref = *sr; 612 613 r300_dsa_inject_stencilref(r300); 614 r300->dsa_state.dirty = TRUE; 615} 616 617static void r300_tex_set_tiling_flags(struct r300_context *r300, 618 struct r300_texture *tex, unsigned level) 619{ 620 /* Check if the macrotile flag needs to be changed. 621 * Skip changing the flags otherwise. */ 622 if (tex->desc.macrotile[tex->surface_level] != 623 tex->desc.macrotile[level]) { 624 /* Tiling determines how DRM treats the buffer data. 625 * We must flush CS when changing it if the buffer is referenced. */ 626 if (r300->rws->cs_is_buffer_referenced(r300->cs, 627 tex->buffer, R300_REF_CS)) 628 r300->context.flush(&r300->context, 0, NULL); 629 630 r300->rws->buffer_set_tiling(r300->rws, tex->buffer, 631 tex->desc.microtile, tex->desc.macrotile[level], 632 tex->desc.stride_in_bytes[0]); 633 634 tex->surface_level = level; 635 } 636} 637 638/* This switcheroo is needed just because of goddamned MACRO_SWITCH. */ 639static void r300_fb_set_tiling_flags(struct r300_context *r300, 640 const struct pipe_framebuffer_state *state) 641{ 642 unsigned i; 643 644 /* Set tiling flags for new surfaces. */ 645 for (i = 0; i < state->nr_cbufs; i++) { 646 r300_tex_set_tiling_flags(r300, 647 r300_texture(state->cbufs[i]->texture), 648 state->cbufs[i]->level); 649 } 650 if (state->zsbuf) { 651 r300_tex_set_tiling_flags(r300, 652 r300_texture(state->zsbuf->texture), 653 state->zsbuf->level); 654 } 655} 656 657static void r300_print_fb_surf_info(struct pipe_surface *surf, unsigned index, 658 const char *binding) 659{ 660 struct pipe_resource *tex = surf->texture; 661 struct r300_texture *rtex = r300_texture(tex); 662 663 fprintf(stderr, 664 "r300: %s[%i] Dim: %ix%i, Offset: %i, ZSlice: %i, " 665 "Face: %i, Level: %i, Format: %s\n" 666 667 "r300: TEX: Macro: %s, Micro: %s, Pitch: %i, " 668 "Dim: %ix%ix%i, LastLevel: %i, Format: %s\n", 669 670 binding, index, surf->width, surf->height, surf->offset, 671 surf->zslice, surf->face, surf->level, 672 util_format_short_name(surf->format), 673 674 rtex->desc.macrotile[0] ? "YES" : " NO", 675 rtex->desc.microtile ? "YES" : " NO", 676 rtex->desc.stride_in_pixels[0], 677 tex->width0, tex->height0, tex->depth0, 678 tex->last_level, util_format_short_name(tex->format)); 679} 680 681void r300_mark_fb_state_dirty(struct r300_context *r300, 682 enum r300_fb_state_change change) 683{ 684 struct pipe_framebuffer_state *state = r300->fb_state.state; 685 686 /* What is marked as dirty depends on the enum r300_fb_state_change. */ 687 r300->gpu_flush.dirty = TRUE; 688 r300->fb_state.dirty = TRUE; 689 r300->hyperz_state.dirty = TRUE; 690 691 if (change == R300_CHANGED_FB_STATE) { 692 r300->aa_state.dirty = TRUE; 693 r300->fb_state_pipelined.dirty = TRUE; 694 } 695 696 /* Now compute the fb_state atom size. */ 697 r300->fb_state.size = 2 + (8 * state->nr_cbufs); 698 699 if (r300->cbzb_clear) 700 r300->fb_state.size += 10; 701 else if (state->zsbuf) 702 r300->fb_state.size += r300->screen->caps.has_hiz ? 18 : 14; 703 704 /* The size of the rest of atoms stays the same. */ 705} 706 707static void 708 r300_set_framebuffer_state(struct pipe_context* pipe, 709 const struct pipe_framebuffer_state* state) 710{ 711 struct r300_context* r300 = r300_context(pipe); 712 struct r300_aa_state *aa = (struct r300_aa_state*)r300->aa_state.state; 713 struct pipe_framebuffer_state *old_state = r300->fb_state.state; 714 unsigned max_width, max_height, i; 715 uint32_t zbuffer_bpp = 0; 716 717 if (r300->screen->caps.is_r500) { 718 max_width = max_height = 4096; 719 } else if (r300->screen->caps.is_r400) { 720 max_width = max_height = 4021; 721 } else { 722 max_width = max_height = 2560; 723 } 724 725 if (state->width > max_width || state->height > max_height) { 726 fprintf(stderr, "r300: Implementation error: Render targets are too " 727 "big in %s, refusing to bind framebuffer state!\n", __FUNCTION__); 728 return; 729 } 730 731 if (r300->draw) { 732 draw_flush(r300->draw); 733 } 734 735 /* If nr_cbufs is changed from zero to non-zero or vice versa... */ 736 if (!!old_state->nr_cbufs != !!state->nr_cbufs) { 737 r300->blend_state.dirty = TRUE; 738 } 739 /* If zsbuf is set from NULL to non-NULL or vice versa.. */ 740 if (!!old_state->zsbuf != !!state->zsbuf) { 741 r300->dsa_state.dirty = TRUE; 742 } 743 744 /* The tiling flags are dependent on the surface miplevel, unfortunately. */ 745 r300_fb_set_tiling_flags(r300, state); 746 747 util_assign_framebuffer_state(r300->fb_state.state, state); 748 749 r300_mark_fb_state_dirty(r300, R300_CHANGED_FB_STATE); 750 751 /* Polygon offset depends on the zbuffer bit depth. */ 752 if (state->zsbuf && r300->polygon_offset_enabled) { 753 switch (util_format_get_blocksize(state->zsbuf->texture->format)) { 754 case 2: 755 zbuffer_bpp = 16; 756 break; 757 case 4: 758 zbuffer_bpp = 24; 759 break; 760 } 761 762 if (r300->zbuffer_bpp != zbuffer_bpp) { 763 r300->zbuffer_bpp = zbuffer_bpp; 764 r300->rs_state.dirty = TRUE; 765 } 766 } 767 768 /* Set up AA config. */ 769 if (r300->rws->get_value(r300->rws, R300_VID_DRM_2_3_0)) { 770 if (state->nr_cbufs && state->cbufs[0]->texture->nr_samples > 1) { 771 aa->aa_config = R300_GB_AA_CONFIG_AA_ENABLE; 772 773 switch (state->cbufs[0]->texture->nr_samples) { 774 case 2: 775 aa->aa_config |= R300_GB_AA_CONFIG_NUM_AA_SUBSAMPLES_2; 776 break; 777 case 3: 778 aa->aa_config |= R300_GB_AA_CONFIG_NUM_AA_SUBSAMPLES_3; 779 break; 780 case 4: 781 aa->aa_config |= R300_GB_AA_CONFIG_NUM_AA_SUBSAMPLES_4; 782 break; 783 case 6: 784 aa->aa_config |= R300_GB_AA_CONFIG_NUM_AA_SUBSAMPLES_6; 785 break; 786 } 787 } else { 788 aa->aa_config = 0; 789 } 790 } 791 792 if (DBG_ON(r300, DBG_FB)) { 793 fprintf(stderr, "r300: set_framebuffer_state:\n"); 794 for (i = 0; i < state->nr_cbufs; i++) { 795 r300_print_fb_surf_info(state->cbufs[i], i, "CB"); 796 } 797 if (state->zsbuf) { 798 r300_print_fb_surf_info(state->zsbuf, 0, "ZB"); 799 } 800 } 801} 802 803/* Create fragment shader state. */ 804static void* r300_create_fs_state(struct pipe_context* pipe, 805 const struct pipe_shader_state* shader) 806{ 807 struct r300_fragment_shader* fs = NULL; 808 809 fs = (struct r300_fragment_shader*)CALLOC_STRUCT(r300_fragment_shader); 810 811 /* Copy state directly into shader. */ 812 fs->state = *shader; 813 fs->state.tokens = tgsi_dup_tokens(shader->tokens); 814 815 return (void*)fs; 816} 817 818void r300_mark_fs_code_dirty(struct r300_context *r300) 819{ 820 struct r300_fragment_shader* fs = r300_fs(r300); 821 822 r300->fs.dirty = TRUE; 823 r300->fs_rc_constant_state.dirty = TRUE; 824 r300->fs_constants.dirty = TRUE; 825 r300->fs.size = fs->shader->cb_code_size; 826 827 if (r300->screen->caps.is_r500) { 828 r300->fs_rc_constant_state.size = fs->shader->rc_state_count * 7; 829 r300->fs_constants.size = fs->shader->externals_count * 4 + 3; 830 } else { 831 r300->fs_rc_constant_state.size = fs->shader->rc_state_count * 5; 832 r300->fs_constants.size = fs->shader->externals_count * 4 + 1; 833 } 834} 835 836/* Bind fragment shader state. */ 837static void r300_bind_fs_state(struct pipe_context* pipe, void* shader) 838{ 839 struct r300_context* r300 = r300_context(pipe); 840 struct r300_fragment_shader* fs = (struct r300_fragment_shader*)shader; 841 842 if (fs == NULL) { 843 r300->fs.state = NULL; 844 return; 845 } 846 847 r300->fs.state = fs; 848 r300_pick_fragment_shader(r300); 849 r300_mark_fs_code_dirty(r300); 850 851 r300->rs_block_state.dirty = TRUE; /* Will be updated before the emission. */ 852} 853 854/* Delete fragment shader state. */ 855static void r300_delete_fs_state(struct pipe_context* pipe, void* shader) 856{ 857 struct r300_fragment_shader* fs = (struct r300_fragment_shader*)shader; 858 struct r300_fragment_shader_code *tmp, *ptr = fs->first; 859 860 while (ptr) { 861 tmp = ptr; 862 ptr = ptr->next; 863 rc_constants_destroy(&tmp->code.constants); 864 FREE(tmp->cb_code); 865 FREE(tmp); 866 } 867 FREE((void*)fs->state.tokens); 868 FREE(shader); 869} 870 871static void r300_set_polygon_stipple(struct pipe_context* pipe, 872 const struct pipe_poly_stipple* state) 873{ 874 /* XXX no idea how to set this up, but not terribly important */ 875} 876 877/* Create a new rasterizer state based on the CSO rasterizer state. 878 * 879 * This is a very large chunk of state, and covers most of the graphics 880 * backend (GB), geometry assembly (GA), and setup unit (SU) blocks. 881 * 882 * In a not entirely unironic sidenote, this state has nearly nothing to do 883 * with the actual block on the Radeon called the rasterizer (RS). */ 884static void* r300_create_rs_state(struct pipe_context* pipe, 885 const struct pipe_rasterizer_state* state) 886{ 887 struct r300_rs_state* rs = CALLOC_STRUCT(r300_rs_state); 888 int i; 889 float psiz; 890 uint32_t vap_control_status; /* R300_VAP_CNTL_STATUS: 0x2140 */ 891 uint32_t point_size; /* R300_GA_POINT_SIZE: 0x421c */ 892 uint32_t point_minmax; /* R300_GA_POINT_MINMAX: 0x4230 */ 893 uint32_t line_control; /* R300_GA_LINE_CNTL: 0x4234 */ 894 uint32_t polygon_offset_enable; /* R300_SU_POLY_OFFSET_ENABLE: 0x42b4 */ 895 uint32_t cull_mode; /* R300_SU_CULL_MODE: 0x42b8 */ 896 uint32_t line_stipple_config; /* R300_GA_LINE_STIPPLE_CONFIG: 0x4328 */ 897 uint32_t line_stipple_value; /* R300_GA_LINE_STIPPLE_VALUE: 0x4260 */ 898 uint32_t polygon_mode; /* R300_GA_POLY_MODE: 0x4288 */ 899 uint32_t clip_rule; /* R300_SC_CLIP_RULE: 0x43D0 */ 900 901 /* Specifies top of Raster pipe specific enable controls, 902 * i.e. texture coordinates stuffing for points, lines, triangles */ 903 uint32_t stuffing_enable; /* R300_GB_ENABLE: 0x4008 */ 904 905 /* Point sprites texture coordinates, 0: lower left, 1: upper right */ 906 float point_texcoord_left; /* R300_GA_POINT_S0: 0x4200 */ 907 float point_texcoord_bottom = 0;/* R300_GA_POINT_T0: 0x4204 */ 908 float point_texcoord_right; /* R300_GA_POINT_S1: 0x4208 */ 909 float point_texcoord_top = 0; /* R300_GA_POINT_T1: 0x420c */ 910 CB_LOCALS; 911 912 /* Copy rasterizer state. */ 913 rs->rs = *state; 914 rs->rs_draw = *state; 915 916 /* Override some states for Draw. */ 917 rs->rs_draw.sprite_coord_enable = 0; /* We can do this in HW. */ 918 919#ifdef PIPE_ARCH_LITTLE_ENDIAN 920 vap_control_status = R300_VC_NO_SWAP; 921#else 922 vap_control_status = R300_VC_32BIT_SWAP; 923#endif 924 925 /* If no TCL engine is present, turn off the HW TCL. */ 926 if (!r300_screen(pipe->screen)->caps.has_tcl) { 927 vap_control_status |= R300_VAP_TCL_BYPASS; 928 } 929 930 /* Point size width and height. */ 931 point_size = 932 pack_float_16_6x(state->point_size) | 933 (pack_float_16_6x(state->point_size) << R300_POINTSIZE_X_SHIFT); 934 935 /* Point size clamping. */ 936 if (state->point_size_per_vertex) { 937 /* Per-vertex point size. 938 * Clamp to [0, max FB size] */ 939 psiz = pipe->screen->get_paramf(pipe->screen, 940 PIPE_CAP_MAX_POINT_WIDTH); 941 point_minmax = 942 pack_float_16_6x(psiz) << R300_GA_POINT_MINMAX_MAX_SHIFT; 943 } else { 944 /* We cannot disable the point-size vertex output, 945 * so clamp it. */ 946 psiz = state->point_size; 947 point_minmax = 948 (pack_float_16_6x(psiz) << R300_GA_POINT_MINMAX_MIN_SHIFT) | 949 (pack_float_16_6x(psiz) << R300_GA_POINT_MINMAX_MAX_SHIFT); 950 } 951 952 /* Line control. */ 953 line_control = pack_float_16_6x(state->line_width) | 954 R300_GA_LINE_CNTL_END_TYPE_COMP; 955 956 /* Enable polygon mode */ 957 polygon_mode = 0; 958 if (state->fill_front != PIPE_POLYGON_MODE_FILL || 959 state->fill_back != PIPE_POLYGON_MODE_FILL) { 960 polygon_mode = R300_GA_POLY_MODE_DUAL; 961 } 962 963 /* Front face */ 964 if (state->front_ccw) 965 cull_mode = R300_FRONT_FACE_CCW; 966 else 967 cull_mode = R300_FRONT_FACE_CW; 968 969 /* Polygon offset */ 970 polygon_offset_enable = 0; 971 if (util_get_offset(state, state->fill_front)) { 972 polygon_offset_enable |= R300_FRONT_ENABLE; 973 } 974 if (util_get_offset(state, state->fill_back)) { 975 polygon_offset_enable |= R300_BACK_ENABLE; 976 } 977 978 rs->polygon_offset_enable = polygon_offset_enable != 0; 979 980 /* Polygon mode */ 981 if (polygon_mode) { 982 polygon_mode |= 983 r300_translate_polygon_mode_front(state->fill_front); 984 polygon_mode |= 985 r300_translate_polygon_mode_back(state->fill_back); 986 } 987 988 if (state->cull_face & PIPE_FACE_FRONT) { 989 cull_mode |= R300_CULL_FRONT; 990 } 991 if (state->cull_face & PIPE_FACE_BACK) { 992 cull_mode |= R300_CULL_BACK; 993 } 994 995 if (state->line_stipple_enable) { 996 line_stipple_config = 997 R300_GA_LINE_STIPPLE_CONFIG_LINE_RESET_LINE | 998 (fui((float)state->line_stipple_factor) & 999 R300_GA_LINE_STIPPLE_CONFIG_STIPPLE_SCALE_MASK); 1000 /* XXX this might need to be scaled up */ 1001 line_stipple_value = state->line_stipple_pattern; 1002 } else { 1003 line_stipple_config = 0; 1004 line_stipple_value = 0; 1005 } 1006 1007 if (state->flatshade) { 1008 rs->color_control = R300_SHADE_MODEL_FLAT; 1009 } else { 1010 rs->color_control = R300_SHADE_MODEL_SMOOTH; 1011 } 1012 1013 clip_rule = state->scissor ? 0xAAAA : 0xFFFF; 1014 1015 /* Point sprites */ 1016 stuffing_enable = 0; 1017 if (state->sprite_coord_enable) { 1018 stuffing_enable = R300_GB_POINT_STUFF_ENABLE; 1019 for (i = 0; i < 8; i++) { 1020 if (state->sprite_coord_enable & (1 << i)) 1021 stuffing_enable |= 1022 R300_GB_TEX_STR << (R300_GB_TEX0_SOURCE_SHIFT + (i*2)); 1023 } 1024 1025 point_texcoord_left = 0.0f; 1026 point_texcoord_right = 1.0f; 1027 1028 switch (state->sprite_coord_mode) { 1029 case PIPE_SPRITE_COORD_UPPER_LEFT: 1030 point_texcoord_top = 0.0f; 1031 point_texcoord_bottom = 1.0f; 1032 break; 1033 case PIPE_SPRITE_COORD_LOWER_LEFT: 1034 point_texcoord_top = 1.0f; 1035 point_texcoord_bottom = 0.0f; 1036 break; 1037 } 1038 } 1039 1040 /* Build the main command buffer. */ 1041 BEGIN_CB(rs->cb_main, 25); 1042 OUT_CB_REG(R300_VAP_CNTL_STATUS, vap_control_status); 1043 OUT_CB_REG(R300_GA_POINT_SIZE, point_size); 1044 OUT_CB_REG_SEQ(R300_GA_POINT_MINMAX, 2); 1045 OUT_CB(point_minmax); 1046 OUT_CB(line_control); 1047 OUT_CB_REG_SEQ(R300_SU_POLY_OFFSET_ENABLE, 2); 1048 OUT_CB(polygon_offset_enable); 1049 rs->cull_mode_index = 9; 1050 OUT_CB(cull_mode); 1051 OUT_CB_REG(R300_GA_LINE_STIPPLE_CONFIG, line_stipple_config); 1052 OUT_CB_REG(R300_GA_LINE_STIPPLE_VALUE, line_stipple_value); 1053 OUT_CB_REG(R300_GA_POLY_MODE, polygon_mode); 1054 OUT_CB_REG(R300_SC_CLIP_RULE, clip_rule); 1055 OUT_CB_REG(R300_GB_ENABLE, stuffing_enable); 1056 OUT_CB_REG_SEQ(R300_GA_POINT_S0, 4); 1057 OUT_CB_32F(point_texcoord_left); 1058 OUT_CB_32F(point_texcoord_bottom); 1059 OUT_CB_32F(point_texcoord_right); 1060 OUT_CB_32F(point_texcoord_top); 1061 END_CB; 1062 1063 /* Build the two command buffers for polygon offset setup. */ 1064 if (polygon_offset_enable) { 1065 float scale = state->offset_scale * 12; 1066 float offset = state->offset_units * 4; 1067 1068 BEGIN_CB(rs->cb_poly_offset_zb16, 5); 1069 OUT_CB_REG_SEQ(R300_SU_POLY_OFFSET_FRONT_SCALE, 4); 1070 OUT_CB_32F(scale); 1071 OUT_CB_32F(offset); 1072 OUT_CB_32F(scale); 1073 OUT_CB_32F(offset); 1074 END_CB; 1075 1076 offset = state->offset_units * 2; 1077 1078 BEGIN_CB(rs->cb_poly_offset_zb24, 5); 1079 OUT_CB_REG_SEQ(R300_SU_POLY_OFFSET_FRONT_SCALE, 4); 1080 OUT_CB_32F(scale); 1081 OUT_CB_32F(offset); 1082 OUT_CB_32F(scale); 1083 OUT_CB_32F(offset); 1084 END_CB; 1085 } 1086 1087 return (void*)rs; 1088} 1089 1090/* Bind rasterizer state. */ 1091static void r300_bind_rs_state(struct pipe_context* pipe, void* state) 1092{ 1093 struct r300_context* r300 = r300_context(pipe); 1094 struct r300_rs_state* rs = (struct r300_rs_state*)state; 1095 int last_sprite_coord_enable = r300->sprite_coord_enable; 1096 boolean last_two_sided_color = r300->two_sided_color; 1097 1098 if (r300->draw && rs) { 1099 draw_flush(r300->draw); 1100 draw_set_rasterizer_state(r300->draw, &rs->rs_draw, state); 1101 } 1102 1103 if (rs) { 1104 r300->polygon_offset_enabled = (rs->rs.offset_point || 1105 rs->rs.offset_line || 1106 rs->rs.offset_tri); 1107 r300->sprite_coord_enable = rs->rs.sprite_coord_enable; 1108 r300->two_sided_color = rs->rs.light_twoside; 1109 } else { 1110 r300->polygon_offset_enabled = FALSE; 1111 r300->sprite_coord_enable = 0; 1112 r300->two_sided_color = FALSE; 1113 } 1114 1115 UPDATE_STATE(state, r300->rs_state); 1116 r300->rs_state.size = 25 + (r300->polygon_offset_enabled ? 5 : 0); 1117 1118 if (last_sprite_coord_enable != r300->sprite_coord_enable || 1119 last_two_sided_color != r300->two_sided_color) { 1120 r300->rs_block_state.dirty = TRUE; 1121 } 1122} 1123 1124/* Free rasterizer state. */ 1125static void r300_delete_rs_state(struct pipe_context* pipe, void* state) 1126{ 1127 FREE(state); 1128} 1129 1130static void* 1131 r300_create_sampler_state(struct pipe_context* pipe, 1132 const struct pipe_sampler_state* state) 1133{ 1134 struct r300_context* r300 = r300_context(pipe); 1135 struct r300_sampler_state* sampler = CALLOC_STRUCT(r300_sampler_state); 1136 boolean is_r500 = r300->screen->caps.is_r500; 1137 int lod_bias; 1138 union util_color uc; 1139 1140 sampler->state = *state; 1141 1142 /* r300 doesn't handle CLAMP and MIRROR_CLAMP correctly when either MAG 1143 * or MIN filter is NEAREST. Since texwrap produces same results 1144 * for CLAMP and CLAMP_TO_EDGE, we use them instead. */ 1145 if (sampler->state.min_img_filter == PIPE_TEX_FILTER_NEAREST || 1146 sampler->state.mag_img_filter == PIPE_TEX_FILTER_NEAREST) { 1147 /* Wrap S. */ 1148 if (sampler->state.wrap_s == PIPE_TEX_WRAP_CLAMP) 1149 sampler->state.wrap_s = PIPE_TEX_WRAP_CLAMP_TO_EDGE; 1150 else if (sampler->state.wrap_s == PIPE_TEX_WRAP_MIRROR_CLAMP) 1151 sampler->state.wrap_s = PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE; 1152 1153 /* Wrap T. */ 1154 if (sampler->state.wrap_t == PIPE_TEX_WRAP_CLAMP) 1155 sampler->state.wrap_t = PIPE_TEX_WRAP_CLAMP_TO_EDGE; 1156 else if (sampler->state.wrap_t == PIPE_TEX_WRAP_MIRROR_CLAMP) 1157 sampler->state.wrap_t = PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE; 1158 1159 /* Wrap R. */ 1160 if (sampler->state.wrap_r == PIPE_TEX_WRAP_CLAMP) 1161 sampler->state.wrap_r = PIPE_TEX_WRAP_CLAMP_TO_EDGE; 1162 else if (sampler->state.wrap_r == PIPE_TEX_WRAP_MIRROR_CLAMP) 1163 sampler->state.wrap_r = PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE; 1164 } 1165 1166 sampler->filter0 |= 1167 (r300_translate_wrap(sampler->state.wrap_s) << R300_TX_WRAP_S_SHIFT) | 1168 (r300_translate_wrap(sampler->state.wrap_t) << R300_TX_WRAP_T_SHIFT) | 1169 (r300_translate_wrap(sampler->state.wrap_r) << R300_TX_WRAP_R_SHIFT); 1170 1171 sampler->filter0 |= r300_translate_tex_filters(state->min_img_filter, 1172 state->mag_img_filter, 1173 state->min_mip_filter, 1174 state->max_anisotropy > 0); 1175 1176 sampler->filter0 |= r300_anisotropy(state->max_anisotropy); 1177 1178 /* Unfortunately, r300-r500 don't support floating-point mipmap lods. */ 1179 /* We must pass these to the merge function to clamp them properly. */ 1180 sampler->min_lod = MAX2((unsigned)state->min_lod, 0); 1181 sampler->max_lod = MAX2((unsigned)ceilf(state->max_lod), 0); 1182 1183 lod_bias = CLAMP((int)(state->lod_bias * 32 + 1), -(1 << 9), (1 << 9) - 1); 1184 1185 sampler->filter1 |= (lod_bias << R300_LOD_BIAS_SHIFT) & R300_LOD_BIAS_MASK; 1186 1187 /* This is very high quality anisotropic filtering for R5xx. 1188 * It's good for benchmarking the performance of texturing but 1189 * in practice we don't want to slow down the driver because it's 1190 * a pretty good performance killer. Feel free to play with it. */ 1191 if (DBG_ON(r300, DBG_ANISOHQ) && is_r500) { 1192 sampler->filter1 |= r500_anisotropy(state->max_anisotropy); 1193 } 1194 1195 util_pack_color(state->border_color, PIPE_FORMAT_B8G8R8A8_UNORM, &uc); 1196 sampler->border_color = uc.ui; 1197 1198 /* R500-specific fixups and optimizations */ 1199 if (r300->screen->caps.is_r500) { 1200 sampler->filter1 |= R500_BORDER_FIX; 1201 } 1202 1203 return (void*)sampler; 1204} 1205 1206static void r300_bind_sampler_states(struct pipe_context* pipe, 1207 unsigned count, 1208 void** states) 1209{ 1210 struct r300_context* r300 = r300_context(pipe); 1211 struct r300_textures_state* state = 1212 (struct r300_textures_state*)r300->textures_state.state; 1213 unsigned tex_units = r300->screen->caps.num_tex_units; 1214 1215 if (count > tex_units) { 1216 return; 1217 } 1218 1219 memcpy(state->sampler_states, states, sizeof(void*) * count); 1220 state->sampler_state_count = count; 1221 1222 r300->textures_state.dirty = TRUE; 1223} 1224 1225static void r300_lacks_vertex_textures(struct pipe_context* pipe, 1226 unsigned count, 1227 void** states) 1228{ 1229} 1230 1231static void r300_delete_sampler_state(struct pipe_context* pipe, void* state) 1232{ 1233 FREE(state); 1234} 1235 1236static uint32_t r300_assign_texture_cache_region(unsigned index, unsigned num) 1237{ 1238 /* This looks like a hack, but I believe it's suppose to work like 1239 * that. To illustrate how this works, let's assume you have 5 textures. 1240 * From docs, 5 and the successive numbers are: 1241 * 1242 * FOURTH_1 = 5 1243 * FOURTH_2 = 6 1244 * FOURTH_3 = 7 1245 * EIGHTH_0 = 8 1246 * EIGHTH_1 = 9 1247 * 1248 * First 3 textures will get 3/4 of size of the cache, divived evenly 1249 * between them. The last 1/4 of the cache must be divided between 1250 * the last 2 textures, each will therefore get 1/8 of the cache. 1251 * Why not just to use "5 + texture_index" ? 1252 * 1253 * This simple trick works for all "num" <= 16. 1254 */ 1255 if (num <= 1) 1256 return R300_TX_CACHE(R300_TX_CACHE_WHOLE); 1257 else 1258 return R300_TX_CACHE(num + index); 1259} 1260 1261static void r300_set_fragment_sampler_views(struct pipe_context* pipe, 1262 unsigned count, 1263 struct pipe_sampler_view** views) 1264{ 1265 struct r300_context* r300 = r300_context(pipe); 1266 struct r300_textures_state* state = 1267 (struct r300_textures_state*)r300->textures_state.state; 1268 struct r300_texture *texture; 1269 unsigned i, real_num_views = 0, view_index = 0; 1270 unsigned tex_units = r300->screen->caps.num_tex_units; 1271 boolean dirty_tex = FALSE; 1272 1273 if (count > tex_units) { 1274 return; 1275 } 1276 1277 /* Calculate the real number of views. */ 1278 for (i = 0; i < count; i++) { 1279 if (views[i]) 1280 real_num_views++; 1281 } 1282 1283 for (i = 0; i < count; i++) { 1284 if (&state->sampler_views[i]->base != views[i]) { 1285 pipe_sampler_view_reference( 1286 (struct pipe_sampler_view**)&state->sampler_views[i], 1287 views[i]); 1288 1289 if (!views[i]) { 1290 continue; 1291 } 1292 1293 /* A new sampler view (= texture)... */ 1294 dirty_tex = TRUE; 1295 1296 /* Set the texrect factor in the fragment shader. 1297 * Needed for RECT and NPOT fallback. */ 1298 texture = r300_texture(views[i]->texture); 1299 if (texture->desc.is_npot) { 1300 r300->fs_rc_constant_state.dirty = TRUE; 1301 } 1302 1303 state->sampler_views[i]->texcache_region = 1304 r300_assign_texture_cache_region(view_index, real_num_views); 1305 view_index++; 1306 } 1307 } 1308 1309 for (i = count; i < tex_units; i++) { 1310 if (state->sampler_views[i]) { 1311 pipe_sampler_view_reference( 1312 (struct pipe_sampler_view**)&state->sampler_views[i], 1313 NULL); 1314 } 1315 } 1316 1317 state->sampler_view_count = count; 1318 1319 r300->textures_state.dirty = TRUE; 1320 1321 if (dirty_tex) { 1322 r300->texture_cache_inval.dirty = TRUE; 1323 } 1324} 1325 1326static struct pipe_sampler_view * 1327r300_create_sampler_view(struct pipe_context *pipe, 1328 struct pipe_resource *texture, 1329 const struct pipe_sampler_view *templ) 1330{ 1331 struct r300_sampler_view *view = CALLOC_STRUCT(r300_sampler_view); 1332 struct r300_texture *tex = r300_texture(texture); 1333 boolean is_r500 = r300_screen(pipe->screen)->caps.is_r500; 1334 1335 if (view) { 1336 view->base = *templ; 1337 view->base.reference.count = 1; 1338 view->base.context = pipe; 1339 view->base.texture = NULL; 1340 pipe_resource_reference(&view->base.texture, texture); 1341 1342 view->swizzle[0] = templ->swizzle_r; 1343 view->swizzle[1] = templ->swizzle_g; 1344 view->swizzle[2] = templ->swizzle_b; 1345 view->swizzle[3] = templ->swizzle_a; 1346 1347 view->format = tex->tx_format; 1348 view->format.format1 |= r300_translate_texformat(templ->format, 1349 view->swizzle, 1350 is_r500); 1351 if (is_r500) { 1352 view->format.format2 |= r500_tx_format_msb_bit(templ->format); 1353 } 1354 } 1355 1356 return (struct pipe_sampler_view*)view; 1357} 1358 1359static void 1360r300_sampler_view_destroy(struct pipe_context *pipe, 1361 struct pipe_sampler_view *view) 1362{ 1363 pipe_resource_reference(&view->texture, NULL); 1364 FREE(view); 1365} 1366 1367static void r300_set_scissor_state(struct pipe_context* pipe, 1368 const struct pipe_scissor_state* state) 1369{ 1370 struct r300_context* r300 = r300_context(pipe); 1371 1372 memcpy(r300->scissor_state.state, state, 1373 sizeof(struct pipe_scissor_state)); 1374 1375 r300->scissor_state.dirty = TRUE; 1376} 1377 1378static void r300_set_viewport_state(struct pipe_context* pipe, 1379 const struct pipe_viewport_state* state) 1380{ 1381 struct r300_context* r300 = r300_context(pipe); 1382 struct r300_viewport_state* viewport = 1383 (struct r300_viewport_state*)r300->viewport_state.state; 1384 1385 r300->viewport = *state; 1386 1387 if (r300->draw) { 1388 draw_flush(r300->draw); 1389 draw_set_viewport_state(r300->draw, state); 1390 viewport->vte_control = R300_VTX_XY_FMT | R300_VTX_Z_FMT; 1391 return; 1392 } 1393 1394 /* Do the transform in HW. */ 1395 viewport->vte_control = R300_VTX_W0_FMT; 1396 1397 if (state->scale[0] != 1.0f) { 1398 viewport->xscale = state->scale[0]; 1399 viewport->vte_control |= R300_VPORT_X_SCALE_ENA; 1400 } 1401 if (state->scale[1] != 1.0f) { 1402 viewport->yscale = state->scale[1]; 1403 viewport->vte_control |= R300_VPORT_Y_SCALE_ENA; 1404 } 1405 if (state->scale[2] != 1.0f) { 1406 viewport->zscale = state->scale[2]; 1407 viewport->vte_control |= R300_VPORT_Z_SCALE_ENA; 1408 } 1409 if (state->translate[0] != 0.0f) { 1410 viewport->xoffset = state->translate[0]; 1411 viewport->vte_control |= R300_VPORT_X_OFFSET_ENA; 1412 } 1413 if (state->translate[1] != 0.0f) { 1414 viewport->yoffset = state->translate[1]; 1415 viewport->vte_control |= R300_VPORT_Y_OFFSET_ENA; 1416 } 1417 if (state->translate[2] != 0.0f) { 1418 viewport->zoffset = state->translate[2]; 1419 viewport->vte_control |= R300_VPORT_Z_OFFSET_ENA; 1420 } 1421 1422 r300->viewport_state.dirty = TRUE; 1423 if (r300->fs.state && r300_fs(r300)->shader->inputs.wpos != ATTR_UNUSED) { 1424 r300->fs_rc_constant_state.dirty = TRUE; 1425 } 1426} 1427 1428static void r300_set_vertex_buffers(struct pipe_context* pipe, 1429 unsigned count, 1430 const struct pipe_vertex_buffer* buffers) 1431{ 1432 struct r300_context* r300 = r300_context(pipe); 1433 struct pipe_vertex_buffer *vbo; 1434 unsigned i, max_index = (1 << 24) - 1; 1435 boolean any_user_buffer = FALSE; 1436 1437 if (count == r300->vertex_buffer_count && 1438 memcmp(r300->vertex_buffer, buffers, 1439 sizeof(struct pipe_vertex_buffer) * count) == 0) { 1440 return; 1441 } 1442 1443 if (r300->screen->caps.has_tcl) { 1444 /* HW TCL. */ 1445 r300->incompatible_vb_layout = FALSE; 1446 1447 /* Check if the strides and offsets are aligned to the size of DWORD. */ 1448 for (i = 0; i < count; i++) { 1449 if (buffers[i].buffer) { 1450 if (buffers[i].stride % 4 != 0 || 1451 buffers[i].buffer_offset % 4 != 0) { 1452 r300->incompatible_vb_layout = TRUE; 1453 break; 1454 } 1455 } 1456 } 1457 1458 for (i = 0; i < count; i++) { 1459 /* Why, yes, I AM casting away constness. How did you know? */ 1460 vbo = (struct pipe_vertex_buffer*)&buffers[i]; 1461 1462 /* Skip NULL buffers */ 1463 if (!buffers[i].buffer) { 1464 continue; 1465 } 1466 1467 if (r300_buffer_is_user_buffer(vbo->buffer)) { 1468 any_user_buffer = TRUE; 1469 } 1470 1471 if (vbo->max_index == ~0) { 1472 /* if no VBO stride then only one vertex value so max index is 1 */ 1473 /* should think about converting to VS constants like svga does */ 1474 if (!vbo->stride) 1475 vbo->max_index = 1; 1476 else 1477 vbo->max_index = 1478 (vbo->buffer->width0 - vbo->buffer_offset) / vbo->stride; 1479 } 1480 1481 max_index = MIN2(vbo->max_index, max_index); 1482 } 1483 1484 r300->any_user_vbs = any_user_buffer; 1485 r300->vertex_buffer_max_index = max_index; 1486 1487 } else { 1488 /* SW TCL. */ 1489 draw_flush(r300->draw); 1490 draw_set_vertex_buffers(r300->draw, count, buffers); 1491 } 1492 1493 /* Common code. */ 1494 for (i = 0; i < count; i++) { 1495 /* Reference our buffer. */ 1496 pipe_resource_reference(&r300->vertex_buffer[i].buffer, buffers[i].buffer); 1497 } 1498 for (; i < r300->vertex_buffer_count; i++) { 1499 /* Dereference any old buffers. */ 1500 pipe_resource_reference(&r300->vertex_buffer[i].buffer, NULL); 1501 } 1502 1503 memcpy(r300->vertex_buffer, buffers, 1504 sizeof(struct pipe_vertex_buffer) * count); 1505 r300->vertex_buffer_count = count; 1506} 1507 1508/* Initialize the PSC tables. */ 1509static void r300_vertex_psc(struct r300_vertex_element_state *velems) 1510{ 1511 struct r300_vertex_stream_state *vstream = &velems->vertex_stream; 1512 uint16_t type, swizzle; 1513 enum pipe_format format; 1514 unsigned i; 1515 1516 if (velems->count > 16) { 1517 fprintf(stderr, "r300: More than 16 vertex elements are not supported," 1518 " requested %i, using 16.\n", velems->count); 1519 velems->count = 16; 1520 } 1521 1522 /* Vertex shaders have no semantics on their inputs, 1523 * so PSC should just route stuff based on the vertex elements, 1524 * and not on attrib information. */ 1525 for (i = 0; i < velems->count; i++) { 1526 format = velems->hw_format[i]; 1527 1528 type = r300_translate_vertex_data_type(format); 1529 if (type == R300_INVALID_FORMAT) { 1530 fprintf(stderr, "r300: Bad vertex format %s.\n", 1531 util_format_short_name(format)); 1532 assert(0); 1533 abort(); 1534 } 1535 1536 type |= i << R300_DST_VEC_LOC_SHIFT; 1537 swizzle = r300_translate_vertex_data_swizzle(format); 1538 1539 if (i & 1) { 1540 vstream->vap_prog_stream_cntl[i >> 1] |= type << 16; 1541 vstream->vap_prog_stream_cntl_ext[i >> 1] |= swizzle << 16; 1542 } else { 1543 vstream->vap_prog_stream_cntl[i >> 1] |= type; 1544 vstream->vap_prog_stream_cntl_ext[i >> 1] |= swizzle; 1545 } 1546 } 1547 1548 /* Set the last vector in the PSC. */ 1549 if (i) { 1550 i -= 1; 1551 } 1552 vstream->vap_prog_stream_cntl[i >> 1] |= 1553 (R300_LAST_VEC << (i & 1 ? 16 : 0)); 1554 1555 vstream->count = (i >> 1) + 1; 1556} 1557 1558#define FORMAT_REPLACE(what, withwhat) \ 1559 case PIPE_FORMAT_##what: *format = PIPE_FORMAT_##withwhat; break 1560 1561static void* r300_create_vertex_elements_state(struct pipe_context* pipe, 1562 unsigned count, 1563 const struct pipe_vertex_element* attribs) 1564{ 1565 struct r300_vertex_element_state *velems; 1566 unsigned i; 1567 enum pipe_format *format; 1568 1569 assert(count <= PIPE_MAX_ATTRIBS); 1570 velems = CALLOC_STRUCT(r300_vertex_element_state); 1571 if (velems != NULL) { 1572 velems->count = count; 1573 memcpy(velems->velem, attribs, sizeof(struct pipe_vertex_element) * count); 1574 1575 if (r300_screen(pipe->screen)->caps.has_tcl) { 1576 /* Set the best hw format in case the original format is not 1577 * supported by hw. */ 1578 for (i = 0; i < count; i++) { 1579 velems->hw_format[i] = velems->velem[i].src_format; 1580 format = &velems->hw_format[i]; 1581 1582 /* This is basically the list of unsupported formats. 1583 * For now we don't care about the alignment, that's going to 1584 * be sorted out after the PSC setup. */ 1585 switch (*format) { 1586 FORMAT_REPLACE(R64_FLOAT, R32_FLOAT); 1587 FORMAT_REPLACE(R64G64_FLOAT, R32G32_FLOAT); 1588 FORMAT_REPLACE(R64G64B64_FLOAT, R32G32B32_FLOAT); 1589 FORMAT_REPLACE(R64G64B64A64_FLOAT, R32G32B32A32_FLOAT); 1590 1591 FORMAT_REPLACE(R32_UNORM, R32_FLOAT); 1592 FORMAT_REPLACE(R32G32_UNORM, R32G32_FLOAT); 1593 FORMAT_REPLACE(R32G32B32_UNORM, R32G32B32_FLOAT); 1594 FORMAT_REPLACE(R32G32B32A32_UNORM, R32G32B32A32_FLOAT); 1595 1596 FORMAT_REPLACE(R32_USCALED, R32_FLOAT); 1597 FORMAT_REPLACE(R32G32_USCALED, R32G32_FLOAT); 1598 FORMAT_REPLACE(R32G32B32_USCALED, R32G32B32_FLOAT); 1599 FORMAT_REPLACE(R32G32B32A32_USCALED,R32G32B32A32_FLOAT); 1600 1601 FORMAT_REPLACE(R32_SNORM, R32_FLOAT); 1602 FORMAT_REPLACE(R32G32_SNORM, R32G32_FLOAT); 1603 FORMAT_REPLACE(R32G32B32_SNORM, R32G32B32_FLOAT); 1604 FORMAT_REPLACE(R32G32B32A32_SNORM, R32G32B32A32_FLOAT); 1605 1606 FORMAT_REPLACE(R32_SSCALED, R32_FLOAT); 1607 FORMAT_REPLACE(R32G32_SSCALED, R32G32_FLOAT); 1608 FORMAT_REPLACE(R32G32B32_SSCALED, R32G32B32_FLOAT); 1609 FORMAT_REPLACE(R32G32B32A32_SSCALED,R32G32B32A32_FLOAT); 1610 1611 FORMAT_REPLACE(R32_FIXED, R32_FLOAT); 1612 FORMAT_REPLACE(R32G32_FIXED, R32G32_FLOAT); 1613 FORMAT_REPLACE(R32G32B32_FIXED, R32G32B32_FLOAT); 1614 FORMAT_REPLACE(R32G32B32A32_FIXED, R32G32B32A32_FLOAT); 1615 1616 default:; 1617 } 1618 1619 velems->incompatible_layout = 1620 velems->incompatible_layout || 1621 velems->velem[i].src_format != velems->hw_format[i] || 1622 velems->velem[i].src_offset % 4 != 0; 1623 } 1624 1625 /* Now setup PSC. 1626 * The unused components will be replaced by (..., 0, 1). */ 1627 r300_vertex_psc(velems); 1628 1629 /* Align the formats to the size of DWORD. 1630 * We only care about the blocksizes of the formats since 1631 * swizzles are already set up. 1632 * Also compute the vertex size. */ 1633 for (i = 0; i < count; i++) { 1634 /* This is OK because we check for aligned strides too. */ 1635 velems->hw_format_size[i] = 1636 align(util_format_get_blocksize(velems->hw_format[i]), 4); 1637 velems->vertex_size_dwords += velems->hw_format_size[i] / 4; 1638 } 1639 } 1640 } 1641 return velems; 1642} 1643 1644static void r300_bind_vertex_elements_state(struct pipe_context *pipe, 1645 void *state) 1646{ 1647 struct r300_context *r300 = r300_context(pipe); 1648 struct r300_vertex_element_state *velems = state; 1649 1650 if (velems == NULL) { 1651 return; 1652 } 1653 1654 r300->velems = velems; 1655 1656 if (r300->draw) { 1657 draw_flush(r300->draw); 1658 draw_set_vertex_elements(r300->draw, velems->count, velems->velem); 1659 return; 1660 } 1661 1662 UPDATE_STATE(&velems->vertex_stream, r300->vertex_stream_state); 1663 r300->vertex_stream_state.size = (1 + velems->vertex_stream.count) * 2; 1664} 1665 1666static void r300_delete_vertex_elements_state(struct pipe_context *pipe, void *state) 1667{ 1668 FREE(state); 1669} 1670 1671static void* r300_create_vs_state(struct pipe_context* pipe, 1672 const struct pipe_shader_state* shader) 1673{ 1674 struct r300_context* r300 = r300_context(pipe); 1675 struct r300_vertex_shader* vs = CALLOC_STRUCT(r300_vertex_shader); 1676 1677 /* Copy state directly into shader. */ 1678 vs->state = *shader; 1679 vs->state.tokens = tgsi_dup_tokens(shader->tokens); 1680 1681 if (r300->screen->caps.has_tcl) { 1682 r300_init_vs_outputs(vs); 1683 r300_translate_vertex_shader(r300, vs); 1684 } else { 1685 r300_draw_init_vertex_shader(r300->draw, vs); 1686 } 1687 1688 return vs; 1689} 1690 1691static void r300_bind_vs_state(struct pipe_context* pipe, void* shader) 1692{ 1693 struct r300_context* r300 = r300_context(pipe); 1694 struct r300_vertex_shader* vs = (struct r300_vertex_shader*)shader; 1695 1696 if (vs == NULL) { 1697 r300->vs_state.state = NULL; 1698 return; 1699 } 1700 if (vs == r300->vs_state.state) { 1701 return; 1702 } 1703 r300->vs_state.state = vs; 1704 1705 /* The majority of the RS block bits is dependent on the vertex shader. */ 1706 r300->rs_block_state.dirty = TRUE; /* Will be updated before the emission. */ 1707 1708 if (r300->screen->caps.has_tcl) { 1709 r300->vs_state.dirty = TRUE; 1710 r300->vs_state.size = 1711 vs->code.length + 9 + 1712 (vs->immediates_count ? vs->immediates_count * 4 + 3 : 0); 1713 1714 if (vs->externals_count) { 1715 r300->vs_constants.dirty = TRUE; 1716 r300->vs_constants.size = vs->externals_count * 4 + 3; 1717 } else { 1718 r300->vs_constants.size = 0; 1719 } 1720 1721 r300->pvs_flush.dirty = TRUE; 1722 } else { 1723 draw_flush(r300->draw); 1724 draw_bind_vertex_shader(r300->draw, 1725 (struct draw_vertex_shader*)vs->draw_vs); 1726 } 1727} 1728 1729static void r300_delete_vs_state(struct pipe_context* pipe, void* shader) 1730{ 1731 struct r300_context* r300 = r300_context(pipe); 1732 struct r300_vertex_shader* vs = (struct r300_vertex_shader*)shader; 1733 1734 if (r300->screen->caps.has_tcl) { 1735 rc_constants_destroy(&vs->code.constants); 1736 } else { 1737 draw_delete_vertex_shader(r300->draw, 1738 (struct draw_vertex_shader*)vs->draw_vs); 1739 } 1740 1741 FREE((void*)vs->state.tokens); 1742 FREE(shader); 1743} 1744 1745static void r300_set_constant_buffer(struct pipe_context *pipe, 1746 uint shader, uint index, 1747 struct pipe_resource *buf) 1748{ 1749 struct r300_context* r300 = r300_context(pipe); 1750 struct r300_constant_buffer *cbuf; 1751 uint32_t *mapped = r300_buffer(buf)->user_buffer; 1752 int max_size = 0, max_size_bytes = 0, clamped_size = 0; 1753 1754 switch (shader) { 1755 case PIPE_SHADER_VERTEX: 1756 cbuf = (struct r300_constant_buffer*)r300->vs_constants.state; 1757 max_size = 256; 1758 break; 1759 case PIPE_SHADER_FRAGMENT: 1760 cbuf = (struct r300_constant_buffer*)r300->fs_constants.state; 1761 if (r300->screen->caps.is_r500) { 1762 max_size = 256; 1763 } else { 1764 max_size = 32; 1765 } 1766 break; 1767 default: 1768 assert(0); 1769 return; 1770 } 1771 max_size_bytes = max_size * 4 * sizeof(float); 1772 1773 if (buf == NULL || buf->width0 == 0 || 1774 (mapped = r300_buffer(buf)->constant_buffer) == NULL) { 1775 cbuf->count = 0; 1776 return; 1777 } 1778 1779 if (shader == PIPE_SHADER_FRAGMENT || 1780 (shader == PIPE_SHADER_VERTEX && r300->screen->caps.has_tcl)) { 1781 assert((buf->width0 % (4 * sizeof(float))) == 0); 1782 1783 /* Check the size of the constant buffer. */ 1784 /* XXX Subtract immediates and RC_STATE_* variables. */ 1785 if (buf->width0 > max_size_bytes) { 1786 fprintf(stderr, "r300: Max size of the constant buffer is " 1787 "%i*4 floats.\n", max_size); 1788 } 1789 1790 clamped_size = MIN2(buf->width0, max_size_bytes); 1791 cbuf->count = clamped_size / (4 * sizeof(float)); 1792 cbuf->ptr = mapped; 1793 } 1794 1795 if (shader == PIPE_SHADER_VERTEX) { 1796 if (r300->screen->caps.has_tcl) { 1797 if (r300->vs_constants.size) { 1798 r300->vs_constants.dirty = TRUE; 1799 } 1800 r300->pvs_flush.dirty = TRUE; 1801 } else if (r300->draw) { 1802 draw_set_mapped_constant_buffer(r300->draw, PIPE_SHADER_VERTEX, 1803 0, mapped, buf->width0); 1804 } 1805 } else if (shader == PIPE_SHADER_FRAGMENT) { 1806 r300->fs_constants.dirty = TRUE; 1807 } 1808} 1809 1810void r300_init_state_functions(struct r300_context* r300) 1811{ 1812 r300->context.create_blend_state = r300_create_blend_state; 1813 r300->context.bind_blend_state = r300_bind_blend_state; 1814 r300->context.delete_blend_state = r300_delete_blend_state; 1815 1816 r300->context.set_blend_color = r300_set_blend_color; 1817 1818 r300->context.set_clip_state = r300_set_clip_state; 1819 r300->context.set_sample_mask = r300_set_sample_mask; 1820 1821 r300->context.set_constant_buffer = r300_set_constant_buffer; 1822 1823 r300->context.create_depth_stencil_alpha_state = r300_create_dsa_state; 1824 r300->context.bind_depth_stencil_alpha_state = r300_bind_dsa_state; 1825 r300->context.delete_depth_stencil_alpha_state = r300_delete_dsa_state; 1826 1827 r300->context.set_stencil_ref = r300_set_stencil_ref; 1828 1829 r300->context.set_framebuffer_state = r300_set_framebuffer_state; 1830 1831 r300->context.create_fs_state = r300_create_fs_state; 1832 r300->context.bind_fs_state = r300_bind_fs_state; 1833 r300->context.delete_fs_state = r300_delete_fs_state; 1834 1835 r300->context.set_polygon_stipple = r300_set_polygon_stipple; 1836 1837 r300->context.create_rasterizer_state = r300_create_rs_state; 1838 r300->context.bind_rasterizer_state = r300_bind_rs_state; 1839 r300->context.delete_rasterizer_state = r300_delete_rs_state; 1840 1841 r300->context.create_sampler_state = r300_create_sampler_state; 1842 r300->context.bind_fragment_sampler_states = r300_bind_sampler_states; 1843 r300->context.bind_vertex_sampler_states = r300_lacks_vertex_textures; 1844 r300->context.delete_sampler_state = r300_delete_sampler_state; 1845 1846 r300->context.set_fragment_sampler_views = r300_set_fragment_sampler_views; 1847 r300->context.create_sampler_view = r300_create_sampler_view; 1848 r300->context.sampler_view_destroy = r300_sampler_view_destroy; 1849 1850 r300->context.set_scissor_state = r300_set_scissor_state; 1851 1852 r300->context.set_viewport_state = r300_set_viewport_state; 1853 1854 r300->context.set_vertex_buffers = r300_set_vertex_buffers; 1855 1856 r300->context.create_vertex_elements_state = r300_create_vertex_elements_state; 1857 r300->context.bind_vertex_elements_state = r300_bind_vertex_elements_state; 1858 r300->context.delete_vertex_elements_state = r300_delete_vertex_elements_state; 1859 1860 r300->context.create_vs_state = r300_create_vs_state; 1861 r300->context.bind_vs_state = r300_bind_vs_state; 1862 r300->context.delete_vs_state = r300_delete_vs_state; 1863} 1864