r300_state.c revision fd8d4b32ede6ebeae332539b71d38c36420e2654
1/* 2 * Copyright 2008 Corbin Simpson <MostAwesomeDude@gmail.com> 3 * Copyright 2009 Marek Olšák <maraeo@gmail.com> 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * on the rights to use, copy, modify, merge, publish, distribute, sub 9 * license, and/or sell copies of the Software, and to permit persons to whom 10 * the Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, 20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 22 * USE OR OTHER DEALINGS IN THE SOFTWARE. */ 23 24#include "draw/draw_context.h" 25 26#include "util/u_framebuffer.h" 27#include "util/u_math.h" 28#include "util/u_mm.h" 29#include "util/u_memory.h" 30#include "util/u_pack_color.h" 31#include "util/u_transfer.h" 32 33#include "tgsi/tgsi_parse.h" 34 35#include "pipe/p_config.h" 36 37#include "r300_cb.h" 38#include "r300_context.h" 39#include "r300_emit.h" 40#include "r300_reg.h" 41#include "r300_screen.h" 42#include "r300_screen_buffer.h" 43#include "r300_state_inlines.h" 44#include "r300_fs.h" 45#include "r300_texture.h" 46#include "r300_vs.h" 47#include "r300_winsys.h" 48#include "r300_hyperz.h" 49 50/* r300_state: Functions used to intialize state context by translating 51 * Gallium state objects into semi-native r300 state objects. */ 52 53#define UPDATE_STATE(cso, atom) \ 54 if (cso != atom.state) { \ 55 atom.state = cso; \ 56 r300_mark_atom_dirty(r300, &(atom)); \ 57 } 58 59static boolean blend_discard_if_src_alpha_0(unsigned srcRGB, unsigned srcA, 60 unsigned dstRGB, unsigned dstA) 61{ 62 /* If the blend equation is ADD or REVERSE_SUBTRACT, 63 * SRC_ALPHA == 0, and the following state is set, the colorbuffer 64 * will not be changed. 65 * Notice that the dst factors are the src factors inverted. */ 66 return (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA || 67 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE || 68 srcRGB == PIPE_BLENDFACTOR_ZERO) && 69 (srcA == PIPE_BLENDFACTOR_SRC_COLOR || 70 srcA == PIPE_BLENDFACTOR_SRC_ALPHA || 71 srcA == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE || 72 srcA == PIPE_BLENDFACTOR_ZERO) && 73 (dstRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA || 74 dstRGB == PIPE_BLENDFACTOR_ONE) && 75 (dstA == PIPE_BLENDFACTOR_INV_SRC_COLOR || 76 dstA == PIPE_BLENDFACTOR_INV_SRC_ALPHA || 77 dstA == PIPE_BLENDFACTOR_ONE); 78} 79 80static boolean blend_discard_if_src_alpha_1(unsigned srcRGB, unsigned srcA, 81 unsigned dstRGB, unsigned dstA) 82{ 83 /* If the blend equation is ADD or REVERSE_SUBTRACT, 84 * SRC_ALPHA == 1, and the following state is set, the colorbuffer 85 * will not be changed. 86 * Notice that the dst factors are the src factors inverted. */ 87 return (srcRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA || 88 srcRGB == PIPE_BLENDFACTOR_ZERO) && 89 (srcA == PIPE_BLENDFACTOR_INV_SRC_COLOR || 90 srcA == PIPE_BLENDFACTOR_INV_SRC_ALPHA || 91 srcA == PIPE_BLENDFACTOR_ZERO) && 92 (dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA || 93 dstRGB == PIPE_BLENDFACTOR_ONE) && 94 (dstA == PIPE_BLENDFACTOR_SRC_COLOR || 95 dstA == PIPE_BLENDFACTOR_SRC_ALPHA || 96 dstA == PIPE_BLENDFACTOR_ONE); 97} 98 99static boolean blend_discard_if_src_color_0(unsigned srcRGB, unsigned srcA, 100 unsigned dstRGB, unsigned dstA) 101{ 102 /* If the blend equation is ADD or REVERSE_SUBTRACT, 103 * SRC_COLOR == (0,0,0), and the following state is set, the colorbuffer 104 * will not be changed. 105 * Notice that the dst factors are the src factors inverted. */ 106 return (srcRGB == PIPE_BLENDFACTOR_SRC_COLOR || 107 srcRGB == PIPE_BLENDFACTOR_ZERO) && 108 (srcA == PIPE_BLENDFACTOR_ZERO) && 109 (dstRGB == PIPE_BLENDFACTOR_INV_SRC_COLOR || 110 dstRGB == PIPE_BLENDFACTOR_ONE) && 111 (dstA == PIPE_BLENDFACTOR_ONE); 112} 113 114static boolean blend_discard_if_src_color_1(unsigned srcRGB, unsigned srcA, 115 unsigned dstRGB, unsigned dstA) 116{ 117 /* If the blend equation is ADD or REVERSE_SUBTRACT, 118 * SRC_COLOR == (1,1,1), and the following state is set, the colorbuffer 119 * will not be changed. 120 * Notice that the dst factors are the src factors inverted. */ 121 return (srcRGB == PIPE_BLENDFACTOR_INV_SRC_COLOR || 122 srcRGB == PIPE_BLENDFACTOR_ZERO) && 123 (srcA == PIPE_BLENDFACTOR_ZERO) && 124 (dstRGB == PIPE_BLENDFACTOR_SRC_COLOR || 125 dstRGB == PIPE_BLENDFACTOR_ONE) && 126 (dstA == PIPE_BLENDFACTOR_ONE); 127} 128 129static boolean blend_discard_if_src_alpha_color_0(unsigned srcRGB, unsigned srcA, 130 unsigned dstRGB, unsigned dstA) 131{ 132 /* If the blend equation is ADD or REVERSE_SUBTRACT, 133 * SRC_ALPHA_COLOR == (0,0,0,0), and the following state is set, 134 * the colorbuffer will not be changed. 135 * Notice that the dst factors are the src factors inverted. */ 136 return (srcRGB == PIPE_BLENDFACTOR_SRC_COLOR || 137 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA || 138 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE || 139 srcRGB == PIPE_BLENDFACTOR_ZERO) && 140 (srcA == PIPE_BLENDFACTOR_SRC_COLOR || 141 srcA == PIPE_BLENDFACTOR_SRC_ALPHA || 142 srcA == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE || 143 srcA == PIPE_BLENDFACTOR_ZERO) && 144 (dstRGB == PIPE_BLENDFACTOR_INV_SRC_COLOR || 145 dstRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA || 146 dstRGB == PIPE_BLENDFACTOR_ONE) && 147 (dstA == PIPE_BLENDFACTOR_INV_SRC_COLOR || 148 dstA == PIPE_BLENDFACTOR_INV_SRC_ALPHA || 149 dstA == PIPE_BLENDFACTOR_ONE); 150} 151 152static boolean blend_discard_if_src_alpha_color_1(unsigned srcRGB, unsigned srcA, 153 unsigned dstRGB, unsigned dstA) 154{ 155 /* If the blend equation is ADD or REVERSE_SUBTRACT, 156 * SRC_ALPHA_COLOR == (1,1,1,1), and the following state is set, 157 * the colorbuffer will not be changed. 158 * Notice that the dst factors are the src factors inverted. */ 159 return (srcRGB == PIPE_BLENDFACTOR_INV_SRC_COLOR || 160 srcRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA || 161 srcRGB == PIPE_BLENDFACTOR_ZERO) && 162 (srcA == PIPE_BLENDFACTOR_INV_SRC_COLOR || 163 srcA == PIPE_BLENDFACTOR_INV_SRC_ALPHA || 164 srcA == PIPE_BLENDFACTOR_ZERO) && 165 (dstRGB == PIPE_BLENDFACTOR_SRC_COLOR || 166 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA || 167 dstRGB == PIPE_BLENDFACTOR_ONE) && 168 (dstA == PIPE_BLENDFACTOR_SRC_COLOR || 169 dstA == PIPE_BLENDFACTOR_SRC_ALPHA || 170 dstA == PIPE_BLENDFACTOR_ONE); 171} 172 173static unsigned bgra_cmask(unsigned mask) 174{ 175 /* Gallium uses RGBA color ordering while R300 expects BGRA. */ 176 177 return ((mask & PIPE_MASK_R) << 2) | 178 ((mask & PIPE_MASK_B) >> 2) | 179 (mask & (PIPE_MASK_G | PIPE_MASK_A)); 180} 181 182/* Create a new blend state based on the CSO blend state. 183 * 184 * This encompasses alpha blending, logic/raster ops, and blend dithering. */ 185static void* r300_create_blend_state(struct pipe_context* pipe, 186 const struct pipe_blend_state* state) 187{ 188 struct r300_screen* r300screen = r300_screen(pipe->screen); 189 struct r300_blend_state* blend = CALLOC_STRUCT(r300_blend_state); 190 uint32_t blend_control = 0; /* R300_RB3D_CBLEND: 0x4e04 */ 191 uint32_t alpha_blend_control = 0; /* R300_RB3D_ABLEND: 0x4e08 */ 192 uint32_t color_channel_mask = 0; /* R300_RB3D_COLOR_CHANNEL_MASK: 0x4e0c */ 193 uint32_t rop = 0; /* R300_RB3D_ROPCNTL: 0x4e18 */ 194 uint32_t dither = 0; /* R300_RB3D_DITHER_CTL: 0x4e50 */ 195 CB_LOCALS; 196 197 if (state->rt[0].blend_enable) 198 { 199 unsigned eqRGB = state->rt[0].rgb_func; 200 unsigned srcRGB = state->rt[0].rgb_src_factor; 201 unsigned dstRGB = state->rt[0].rgb_dst_factor; 202 203 unsigned eqA = state->rt[0].alpha_func; 204 unsigned srcA = state->rt[0].alpha_src_factor; 205 unsigned dstA = state->rt[0].alpha_dst_factor; 206 207 /* despite the name, ALPHA_BLEND_ENABLE has nothing to do with alpha, 208 * this is just the crappy D3D naming */ 209 blend_control = R300_ALPHA_BLEND_ENABLE | 210 r300_translate_blend_function(eqRGB) | 211 ( r300_translate_blend_factor(srcRGB) << R300_SRC_BLEND_SHIFT) | 212 ( r300_translate_blend_factor(dstRGB) << R300_DST_BLEND_SHIFT); 213 214 /* Optimization: some operations do not require the destination color. 215 * 216 * When SRC_ALPHA_SATURATE is used, colorbuffer reads must be enabled, 217 * otherwise blending gives incorrect results. It seems to be 218 * a hardware bug. */ 219 if (eqRGB == PIPE_BLEND_MIN || eqA == PIPE_BLEND_MIN || 220 eqRGB == PIPE_BLEND_MAX || eqA == PIPE_BLEND_MAX || 221 dstRGB != PIPE_BLENDFACTOR_ZERO || 222 dstA != PIPE_BLENDFACTOR_ZERO || 223 srcRGB == PIPE_BLENDFACTOR_DST_COLOR || 224 srcRGB == PIPE_BLENDFACTOR_DST_ALPHA || 225 srcRGB == PIPE_BLENDFACTOR_INV_DST_COLOR || 226 srcRGB == PIPE_BLENDFACTOR_INV_DST_ALPHA || 227 srcA == PIPE_BLENDFACTOR_DST_COLOR || 228 srcA == PIPE_BLENDFACTOR_DST_ALPHA || 229 srcA == PIPE_BLENDFACTOR_INV_DST_COLOR || 230 srcA == PIPE_BLENDFACTOR_INV_DST_ALPHA || 231 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE) { 232 /* Enable reading from the colorbuffer. */ 233 blend_control |= R300_READ_ENABLE; 234 235 if (r300screen->caps.is_r500) { 236 /* Optimization: Depending on incoming pixels, we can 237 * conditionally disable the reading in hardware... */ 238 if (eqRGB != PIPE_BLEND_MIN && eqA != PIPE_BLEND_MIN && 239 eqRGB != PIPE_BLEND_MAX && eqA != PIPE_BLEND_MAX) { 240 /* Disable reading if SRC_ALPHA == 0. */ 241 if ((dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA || 242 dstRGB == PIPE_BLENDFACTOR_ZERO) && 243 (dstA == PIPE_BLENDFACTOR_SRC_COLOR || 244 dstA == PIPE_BLENDFACTOR_SRC_ALPHA || 245 dstA == PIPE_BLENDFACTOR_ZERO)) { 246 blend_control |= R500_SRC_ALPHA_0_NO_READ; 247 } 248 249 /* Disable reading if SRC_ALPHA == 1. */ 250 if ((dstRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA || 251 dstRGB == PIPE_BLENDFACTOR_ZERO) && 252 (dstA == PIPE_BLENDFACTOR_INV_SRC_COLOR || 253 dstA == PIPE_BLENDFACTOR_INV_SRC_ALPHA || 254 dstA == PIPE_BLENDFACTOR_ZERO)) { 255 blend_control |= R500_SRC_ALPHA_1_NO_READ; 256 } 257 } 258 } 259 } 260 261 /* Optimization: discard pixels which don't change the colorbuffer. 262 * 263 * The code below is non-trivial and some math is involved. 264 * 265 * Discarding pixels must be disabled when FP16 AA is enabled. 266 * This is a hardware bug. Also, this implementation wouldn't work 267 * with FP blending enabled and equation clamping disabled. 268 * 269 * Equations other than ADD are rarely used and therefore won't be 270 * optimized. */ 271 if ((eqRGB == PIPE_BLEND_ADD || eqRGB == PIPE_BLEND_REVERSE_SUBTRACT) && 272 (eqA == PIPE_BLEND_ADD || eqA == PIPE_BLEND_REVERSE_SUBTRACT)) { 273 /* ADD: X+Y 274 * REVERSE_SUBTRACT: Y-X 275 * 276 * The idea is: 277 * If X = src*srcFactor = 0 and Y = dst*dstFactor = 1, 278 * then CB will not be changed. 279 * 280 * Given the srcFactor and dstFactor variables, we can derive 281 * what src and dst should be equal to and discard appropriate 282 * pixels. 283 */ 284 if (blend_discard_if_src_alpha_0(srcRGB, srcA, dstRGB, dstA)) { 285 blend_control |= R300_DISCARD_SRC_PIXELS_SRC_ALPHA_0; 286 } else if (blend_discard_if_src_alpha_1(srcRGB, srcA, 287 dstRGB, dstA)) { 288 blend_control |= R300_DISCARD_SRC_PIXELS_SRC_ALPHA_1; 289 } else if (blend_discard_if_src_color_0(srcRGB, srcA, 290 dstRGB, dstA)) { 291 blend_control |= R300_DISCARD_SRC_PIXELS_SRC_COLOR_0; 292 } else if (blend_discard_if_src_color_1(srcRGB, srcA, 293 dstRGB, dstA)) { 294 blend_control |= R300_DISCARD_SRC_PIXELS_SRC_COLOR_1; 295 } else if (blend_discard_if_src_alpha_color_0(srcRGB, srcA, 296 dstRGB, dstA)) { 297 blend_control |= 298 R300_DISCARD_SRC_PIXELS_SRC_ALPHA_COLOR_0; 299 } else if (blend_discard_if_src_alpha_color_1(srcRGB, srcA, 300 dstRGB, dstA)) { 301 blend_control |= 302 R300_DISCARD_SRC_PIXELS_SRC_ALPHA_COLOR_1; 303 } 304 } 305 306 /* separate alpha */ 307 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) { 308 blend_control |= R300_SEPARATE_ALPHA_ENABLE; 309 alpha_blend_control = 310 r300_translate_blend_function(eqA) | 311 (r300_translate_blend_factor(srcA) << R300_SRC_BLEND_SHIFT) | 312 (r300_translate_blend_factor(dstA) << R300_DST_BLEND_SHIFT); 313 } 314 } 315 316 /* PIPE_LOGICOP_* don't need to be translated, fortunately. */ 317 if (state->logicop_enable) { 318 rop = R300_RB3D_ROPCNTL_ROP_ENABLE | 319 (state->logicop_func) << R300_RB3D_ROPCNTL_ROP_SHIFT; 320 } 321 322 /* Color channel masks for all MRTs. */ 323 color_channel_mask = bgra_cmask(state->rt[0].colormask); 324 if (r300screen->caps.is_r500 && state->independent_blend_enable) { 325 if (state->rt[1].blend_enable) { 326 color_channel_mask |= bgra_cmask(state->rt[1].colormask) << 4; 327 } 328 if (state->rt[2].blend_enable) { 329 color_channel_mask |= bgra_cmask(state->rt[2].colormask) << 8; 330 } 331 if (state->rt[3].blend_enable) { 332 color_channel_mask |= bgra_cmask(state->rt[3].colormask) << 12; 333 } 334 } 335 336 /* Neither fglrx nor classic r300 ever set this, regardless of dithering 337 * state. Since it's an optional implementation detail, we can leave it 338 * out and never dither. 339 * 340 * This could be revisited if we ever get quality or conformance hints. 341 * 342 if (state->dither) { 343 dither = R300_RB3D_DITHER_CTL_DITHER_MODE_LUT | 344 R300_RB3D_DITHER_CTL_ALPHA_DITHER_MODE_LUT; 345 } 346 */ 347 348 /* Build a command buffer. */ 349 BEGIN_CB(blend->cb, 8); 350 OUT_CB_REG(R300_RB3D_ROPCNTL, rop); 351 OUT_CB_REG_SEQ(R300_RB3D_CBLEND, 3); 352 OUT_CB(blend_control); 353 OUT_CB(alpha_blend_control); 354 OUT_CB(color_channel_mask); 355 OUT_CB_REG(R300_RB3D_DITHER_CTL, dither); 356 END_CB; 357 358 /* The same as above, but with no colorbuffer reads and writes. */ 359 BEGIN_CB(blend->cb_no_readwrite, 8); 360 OUT_CB_REG(R300_RB3D_ROPCNTL, rop); 361 OUT_CB_REG_SEQ(R300_RB3D_CBLEND, 3); 362 OUT_CB(0); 363 OUT_CB(0); 364 OUT_CB(0); 365 OUT_CB_REG(R300_RB3D_DITHER_CTL, dither); 366 END_CB; 367 368 return (void*)blend; 369} 370 371/* Bind blend state. */ 372static void r300_bind_blend_state(struct pipe_context* pipe, 373 void* state) 374{ 375 struct r300_context* r300 = r300_context(pipe); 376 377 UPDATE_STATE(state, r300->blend_state); 378} 379 380/* Free blend state. */ 381static void r300_delete_blend_state(struct pipe_context* pipe, 382 void* state) 383{ 384 FREE(state); 385} 386 387/* Convert float to 10bit integer */ 388static unsigned float_to_fixed10(float f) 389{ 390 return CLAMP((unsigned)(f * 1023.9f), 0, 1023); 391} 392 393/* Set blend color. 394 * Setup both R300 and R500 registers, figure out later which one to write. */ 395static void r300_set_blend_color(struct pipe_context* pipe, 396 const struct pipe_blend_color* color) 397{ 398 struct r300_context* r300 = r300_context(pipe); 399 struct r300_blend_color_state* state = 400 (struct r300_blend_color_state*)r300->blend_color_state.state; 401 CB_LOCALS; 402 403 if (r300->screen->caps.is_r500) { 404 /* XXX if FP16 blending is enabled, we should use the FP16 format */ 405 BEGIN_CB(state->cb, 3); 406 OUT_CB_REG_SEQ(R500_RB3D_CONSTANT_COLOR_AR, 2); 407 OUT_CB(float_to_fixed10(color->color[0]) | 408 (float_to_fixed10(color->color[3]) << 16)); 409 OUT_CB(float_to_fixed10(color->color[2]) | 410 (float_to_fixed10(color->color[1]) << 16)); 411 END_CB; 412 } else { 413 union util_color uc; 414 util_pack_color(color->color, PIPE_FORMAT_B8G8R8A8_UNORM, &uc); 415 416 BEGIN_CB(state->cb, 2); 417 OUT_CB_REG(R300_RB3D_BLEND_COLOR, uc.ui); 418 END_CB; 419 } 420 421 r300_mark_atom_dirty(r300, &r300->blend_color_state); 422} 423 424static void r300_set_clip_state(struct pipe_context* pipe, 425 const struct pipe_clip_state* state) 426{ 427 struct r300_context* r300 = r300_context(pipe); 428 struct r300_clip_state *clip = 429 (struct r300_clip_state*)r300->clip_state.state; 430 CB_LOCALS; 431 432 clip->clip = *state; 433 434 if (r300->screen->caps.has_tcl) { 435 r300->clip_state.size = 2 + !!state->nr * 3 + state->nr * 4; 436 437 BEGIN_CB(clip->cb, r300->clip_state.size); 438 if (state->nr) { 439 OUT_CB_REG(R300_VAP_PVS_VECTOR_INDX_REG, 440 (r300->screen->caps.is_r500 ? 441 R500_PVS_UCP_START : R300_PVS_UCP_START)); 442 OUT_CB_ONE_REG(R300_VAP_PVS_UPLOAD_DATA, state->nr * 4); 443 OUT_CB_TABLE(state->ucp, state->nr * 4); 444 } 445 OUT_CB_REG(R300_VAP_CLIP_CNTL, ((1 << state->nr) - 1) | 446 R300_PS_UCP_MODE_CLIP_AS_TRIFAN); 447 END_CB; 448 449 r300_mark_atom_dirty(r300, &r300->clip_state); 450 } else { 451 draw_set_clip_state(r300->draw, state); 452 } 453} 454 455static void 456r300_set_sample_mask(struct pipe_context *pipe, 457 unsigned sample_mask) 458{ 459} 460 461 462/* Create a new depth, stencil, and alpha state based on the CSO dsa state. 463 * 464 * This contains the depth buffer, stencil buffer, alpha test, and such. 465 * On the Radeon, depth and stencil buffer setup are intertwined, which is 466 * the reason for some of the strange-looking assignments across registers. */ 467static void* 468 r300_create_dsa_state(struct pipe_context* pipe, 469 const struct pipe_depth_stencil_alpha_state* state) 470{ 471 struct r300_capabilities *caps = &r300_screen(pipe->screen)->caps; 472 struct r300_dsa_state* dsa = CALLOC_STRUCT(r300_dsa_state); 473 CB_LOCALS; 474 475 dsa->dsa = *state; 476 477 /* Depth test setup. - separate write mask depth for decomp flush */ 478 if (state->depth.writemask) { 479 dsa->z_buffer_control |= R300_Z_WRITE_ENABLE; 480 } 481 482 if (state->depth.enabled) { 483 dsa->z_buffer_control |= R300_Z_ENABLE; 484 485 dsa->z_stencil_control |= 486 (r300_translate_depth_stencil_function(state->depth.func) << 487 R300_Z_FUNC_SHIFT); 488 } 489 490 /* Stencil buffer setup. */ 491 if (state->stencil[0].enabled) { 492 dsa->z_buffer_control |= R300_STENCIL_ENABLE; 493 dsa->z_stencil_control |= 494 (r300_translate_depth_stencil_function(state->stencil[0].func) << 495 R300_S_FRONT_FUNC_SHIFT) | 496 (r300_translate_stencil_op(state->stencil[0].fail_op) << 497 R300_S_FRONT_SFAIL_OP_SHIFT) | 498 (r300_translate_stencil_op(state->stencil[0].zpass_op) << 499 R300_S_FRONT_ZPASS_OP_SHIFT) | 500 (r300_translate_stencil_op(state->stencil[0].zfail_op) << 501 R300_S_FRONT_ZFAIL_OP_SHIFT); 502 503 dsa->stencil_ref_mask = 504 (state->stencil[0].valuemask << R300_STENCILMASK_SHIFT) | 505 (state->stencil[0].writemask << R300_STENCILWRITEMASK_SHIFT); 506 507 if (state->stencil[1].enabled) { 508 dsa->two_sided = TRUE; 509 510 dsa->z_buffer_control |= R300_STENCIL_FRONT_BACK; 511 dsa->z_stencil_control |= 512 (r300_translate_depth_stencil_function(state->stencil[1].func) << 513 R300_S_BACK_FUNC_SHIFT) | 514 (r300_translate_stencil_op(state->stencil[1].fail_op) << 515 R300_S_BACK_SFAIL_OP_SHIFT) | 516 (r300_translate_stencil_op(state->stencil[1].zpass_op) << 517 R300_S_BACK_ZPASS_OP_SHIFT) | 518 (r300_translate_stencil_op(state->stencil[1].zfail_op) << 519 R300_S_BACK_ZFAIL_OP_SHIFT); 520 521 dsa->stencil_ref_bf = 522 (state->stencil[1].valuemask << R300_STENCILMASK_SHIFT) | 523 (state->stencil[1].writemask << R300_STENCILWRITEMASK_SHIFT); 524 525 if (caps->is_r500) { 526 dsa->z_buffer_control |= R500_STENCIL_REFMASK_FRONT_BACK; 527 } else { 528 dsa->two_sided_stencil_ref = 529 (state->stencil[0].valuemask != state->stencil[1].valuemask || 530 state->stencil[0].writemask != state->stencil[1].writemask); 531 } 532 } 533 } 534 535 /* Alpha test setup. */ 536 if (state->alpha.enabled) { 537 dsa->alpha_function = 538 r300_translate_alpha_function(state->alpha.func) | 539 R300_FG_ALPHA_FUNC_ENABLE; 540 541 /* We could use 10bit alpha ref but who needs that? */ 542 dsa->alpha_function |= float_to_ubyte(state->alpha.ref_value); 543 544 if (caps->is_r500) 545 dsa->alpha_function |= R500_FG_ALPHA_FUNC_8BIT; 546 } 547 548 BEGIN_CB(&dsa->cb_begin, 8); 549 OUT_CB_REG(R300_FG_ALPHA_FUNC, dsa->alpha_function); 550 OUT_CB_REG_SEQ(R300_ZB_CNTL, 3); 551 OUT_CB(dsa->z_buffer_control); 552 OUT_CB(dsa->z_stencil_control); 553 OUT_CB(dsa->stencil_ref_mask); 554 OUT_CB_REG(R500_ZB_STENCILREFMASK_BF, dsa->stencil_ref_bf); 555 END_CB; 556 557 BEGIN_CB(dsa->cb_no_readwrite, 8); 558 OUT_CB_REG(R300_FG_ALPHA_FUNC, dsa->alpha_function); 559 OUT_CB_REG_SEQ(R300_ZB_CNTL, 3); 560 OUT_CB(0); 561 OUT_CB(0); 562 OUT_CB(0); 563 OUT_CB_REG(R500_ZB_STENCILREFMASK_BF, 0); 564 END_CB; 565 566 return (void*)dsa; 567} 568 569static void r300_dsa_inject_stencilref(struct r300_context *r300) 570{ 571 struct r300_dsa_state *dsa = 572 (struct r300_dsa_state*)r300->dsa_state.state; 573 574 if (!dsa) 575 return; 576 577 dsa->stencil_ref_mask = 578 (dsa->stencil_ref_mask & ~R300_STENCILREF_MASK) | 579 r300->stencil_ref.ref_value[0]; 580 dsa->stencil_ref_bf = 581 (dsa->stencil_ref_bf & ~R300_STENCILREF_MASK) | 582 r300->stencil_ref.ref_value[1]; 583} 584 585/* Bind DSA state. */ 586static void r300_bind_dsa_state(struct pipe_context* pipe, 587 void* state) 588{ 589 struct r300_context* r300 = r300_context(pipe); 590 591 if (!state) { 592 return; 593 } 594 595 UPDATE_STATE(state, r300->dsa_state); 596 597 r300_mark_atom_dirty(r300, &r300->hyperz_state); /* Will be updated before the emission. */ 598 r300_dsa_inject_stencilref(r300); 599} 600 601/* Free DSA state. */ 602static void r300_delete_dsa_state(struct pipe_context* pipe, 603 void* state) 604{ 605 FREE(state); 606} 607 608static void r300_set_stencil_ref(struct pipe_context* pipe, 609 const struct pipe_stencil_ref* sr) 610{ 611 struct r300_context* r300 = r300_context(pipe); 612 613 r300->stencil_ref = *sr; 614 615 r300_dsa_inject_stencilref(r300); 616 r300_mark_atom_dirty(r300, &r300->dsa_state); 617} 618 619static void r300_tex_set_tiling_flags(struct r300_context *r300, 620 struct r300_resource *tex, 621 unsigned level) 622{ 623 /* Check if the macrotile flag needs to be changed. 624 * Skip changing the flags otherwise. */ 625 if (tex->tex.macrotile[tex->surface_level] != 626 tex->tex.macrotile[level]) { 627 r300->rws->buffer_set_tiling(tex->buf, r300->cs, 628 tex->tex.microtile, tex->tex.macrotile[level], 629 tex->tex.stride_in_bytes[0]); 630 631 tex->surface_level = level; 632 } 633} 634 635/* This switcheroo is needed just because of goddamned MACRO_SWITCH. */ 636static void r300_fb_set_tiling_flags(struct r300_context *r300, 637 const struct pipe_framebuffer_state *state) 638{ 639 unsigned i; 640 641 /* Set tiling flags for new surfaces. */ 642 for (i = 0; i < state->nr_cbufs; i++) { 643 r300_tex_set_tiling_flags(r300, 644 r300_resource(state->cbufs[i]->texture), 645 state->cbufs[i]->u.tex.level); 646 } 647 if (state->zsbuf) { 648 r300_tex_set_tiling_flags(r300, 649 r300_resource(state->zsbuf->texture), 650 state->zsbuf->u.tex.level); 651 } 652} 653 654static void r300_print_fb_surf_info(struct pipe_surface *surf, unsigned index, 655 const char *binding) 656{ 657 struct pipe_resource *tex = surf->texture; 658 struct r300_resource *rtex = r300_resource(tex); 659 660 fprintf(stderr, 661 "r300: %s[%i] Dim: %ix%i, Firstlayer: %i, " 662 "Lastlayer: %i, Level: %i, Format: %s\n" 663 664 "r300: TEX: Macro: %s, Micro: %s, Pitch: %i, " 665 "Dim: %ix%ix%i, LastLevel: %i, Format: %s\n", 666 667 binding, index, surf->width, surf->height, 668 surf->u.tex.first_layer, surf->u.tex.last_layer, surf->u.tex.level, 669 util_format_short_name(surf->format), 670 671 rtex->tex.macrotile[0] ? "YES" : " NO", 672 rtex->tex.microtile ? "YES" : " NO", 673 rtex->tex.stride_in_pixels[0], 674 tex->width0, tex->height0, tex->depth0, 675 tex->last_level, util_format_short_name(tex->format)); 676} 677 678void r300_mark_fb_state_dirty(struct r300_context *r300, 679 enum r300_fb_state_change change) 680{ 681 struct pipe_framebuffer_state *state = r300->fb_state.state; 682 boolean can_hyperz = r300->rws->get_value(r300->rws, R300_CAN_HYPERZ); 683 684 r300_mark_atom_dirty(r300, &r300->gpu_flush); 685 r300_mark_atom_dirty(r300, &r300->fb_state); 686 687 /* What is marked as dirty depends on the enum r300_fb_state_change. */ 688 if (change == R300_CHANGED_FB_STATE) { 689 r300_mark_atom_dirty(r300, &r300->aa_state); 690 } 691 692 if (change == R300_CHANGED_FB_STATE || 693 change == R300_CHANGED_HYPERZ_FLAG) { 694 r300_mark_atom_dirty(r300, &r300->hyperz_state); 695 } 696 697 if (change == R300_CHANGED_FB_STATE || 698 change == R300_CHANGED_MULTIWRITE) { 699 r300_mark_atom_dirty(r300, &r300->fb_state_pipelined); 700 } 701 702 /* Now compute the fb_state atom size. */ 703 r300->fb_state.size = 2 + (8 * state->nr_cbufs); 704 705 if (r300->cbzb_clear) 706 r300->fb_state.size += 10; 707 else if (state->zsbuf) { 708 r300->fb_state.size += 10; 709 if (can_hyperz) 710 r300->fb_state.size += r300->screen->caps.hiz_ram ? 8 : 4; 711 } 712 713 /* The size of the rest of atoms stays the same. */ 714} 715 716static void 717r300_set_framebuffer_state(struct pipe_context* pipe, 718 const struct pipe_framebuffer_state* state) 719{ 720 struct r300_context* r300 = r300_context(pipe); 721 struct r300_aa_state *aa = (struct r300_aa_state*)r300->aa_state.state; 722 struct pipe_framebuffer_state *old_state = r300->fb_state.state; 723 boolean can_hyperz = r300->rws->get_value(r300->rws, R300_CAN_HYPERZ); 724 unsigned max_width, max_height, i; 725 uint32_t zbuffer_bpp = 0; 726 727 if (r300->screen->caps.is_r500) { 728 max_width = max_height = 4096; 729 } else if (r300->screen->caps.is_r400) { 730 max_width = max_height = 4021; 731 } else { 732 max_width = max_height = 2560; 733 } 734 735 if (state->width > max_width || state->height > max_height) { 736 fprintf(stderr, "r300: Implementation error: Render targets are too " 737 "big in %s, refusing to bind framebuffer state!\n", __FUNCTION__); 738 return; 739 } 740 741 if (old_state->zsbuf && r300->zmask_in_use && !r300->zmask_locked) { 742 /* There is a zmask in use, what are we gonna do? */ 743 if (state->zsbuf) { 744 if (!pipe_surface_equal(old_state->zsbuf, state->zsbuf)) { 745 /* Decompress the currently bound zbuffer before we bind another one. */ 746 r300_decompress_zmask(r300); 747 } 748 } else { 749 /* We don't bind another zbuffer, so lock the current one. */ 750 r300->zmask_locked = TRUE; 751 pipe_surface_reference(&r300->locked_zbuffer, old_state->zsbuf); 752 } 753 } else if (r300->zmask_locked && r300->locked_zbuffer) { 754 /* We have a locked zbuffer now, what are we gonna do? */ 755 if (state->zsbuf) { 756 if (!pipe_surface_equal(r300->locked_zbuffer, state->zsbuf)) { 757 /* We are binding some other zbuffer, so decompress the locked one, 758 * it gets unlocked automatically. */ 759 r300_decompress_zmask_locked_unsafe(r300); 760 } else { 761 /* We are binding the locked zbuffer again, so unlock it. */ 762 r300->zmask_locked = FALSE; 763 } 764 } 765 } 766 767 /* If nr_cbufs is changed from zero to non-zero or vice versa... */ 768 if (!!old_state->nr_cbufs != !!state->nr_cbufs) { 769 r300_mark_atom_dirty(r300, &r300->blend_state); 770 } 771 /* If zsbuf is set from NULL to non-NULL or vice versa.. */ 772 if (!!old_state->zsbuf != !!state->zsbuf) { 773 r300_mark_atom_dirty(r300, &r300->dsa_state); 774 } 775 776 /* The tiling flags are dependent on the surface miplevel, unfortunately. */ 777 r300_fb_set_tiling_flags(r300, state); 778 779 util_copy_framebuffer_state(r300->fb_state.state, state); 780 781 if (!r300->zmask_locked) { 782 pipe_surface_reference(&r300->locked_zbuffer, NULL); 783 } 784 785 r300_mark_fb_state_dirty(r300, R300_CHANGED_FB_STATE); 786 787 if (state->zsbuf) { 788 switch (util_format_get_blocksize(state->zsbuf->texture->format)) { 789 case 2: 790 zbuffer_bpp = 16; 791 break; 792 case 4: 793 zbuffer_bpp = 24; 794 break; 795 } 796 797 /* Setup Hyper-Z. */ 798 if (can_hyperz) { 799 struct r300_surface *zs_surf = r300_surface(state->zsbuf); 800 struct r300_resource *tex = r300_resource(zs_surf->base.texture); 801 int level = zs_surf->base.u.tex.level; 802 803 /* work out whether we can support hiz on this buffer */ 804 r300_hiz_alloc_block(r300, zs_surf); 805 806 DBG(r300, DBG_HYPERZ, 807 "hyper-z features: hiz: %d @ %08x\n", tex->hiz_mem[level] ? 1 : 0, 808 tex->hiz_mem[level] ? tex->hiz_mem[level]->ofs : 0xdeadbeef); 809 } 810 811 /* Polygon offset depends on the zbuffer bit depth. */ 812 if (r300->zbuffer_bpp != zbuffer_bpp) { 813 r300->zbuffer_bpp = zbuffer_bpp; 814 815 if (r300->polygon_offset_enabled) 816 r300_mark_atom_dirty(r300, &r300->rs_state); 817 } 818 } 819 820 /* Set up AA config. */ 821 if (r300->rws->get_value(r300->rws, R300_VID_DRM_2_3_0)) { 822 if (state->nr_cbufs && state->cbufs[0]->texture->nr_samples > 1) { 823 aa->aa_config = R300_GB_AA_CONFIG_AA_ENABLE; 824 825 switch (state->cbufs[0]->texture->nr_samples) { 826 case 2: 827 aa->aa_config |= R300_GB_AA_CONFIG_NUM_AA_SUBSAMPLES_2; 828 break; 829 case 3: 830 aa->aa_config |= R300_GB_AA_CONFIG_NUM_AA_SUBSAMPLES_3; 831 break; 832 case 4: 833 aa->aa_config |= R300_GB_AA_CONFIG_NUM_AA_SUBSAMPLES_4; 834 break; 835 case 6: 836 aa->aa_config |= R300_GB_AA_CONFIG_NUM_AA_SUBSAMPLES_6; 837 break; 838 } 839 } else { 840 aa->aa_config = 0; 841 } 842 } 843 844 if (DBG_ON(r300, DBG_FB)) { 845 fprintf(stderr, "r300: set_framebuffer_state:\n"); 846 for (i = 0; i < state->nr_cbufs; i++) { 847 r300_print_fb_surf_info(state->cbufs[i], i, "CB"); 848 } 849 if (state->zsbuf) { 850 r300_print_fb_surf_info(state->zsbuf, 0, "ZB"); 851 } 852 } 853} 854 855/* Create fragment shader state. */ 856static void* r300_create_fs_state(struct pipe_context* pipe, 857 const struct pipe_shader_state* shader) 858{ 859 struct r300_fragment_shader* fs = NULL; 860 861 fs = (struct r300_fragment_shader*)CALLOC_STRUCT(r300_fragment_shader); 862 863 /* Copy state directly into shader. */ 864 fs->state = *shader; 865 fs->state.tokens = tgsi_dup_tokens(shader->tokens); 866 867 return (void*)fs; 868} 869 870void r300_mark_fs_code_dirty(struct r300_context *r300) 871{ 872 struct r300_fragment_shader* fs = r300_fs(r300); 873 874 r300_mark_atom_dirty(r300, &r300->fs); 875 r300_mark_atom_dirty(r300, &r300->fs_rc_constant_state); 876 r300_mark_atom_dirty(r300, &r300->fs_constants); 877 r300->fs.size = fs->shader->cb_code_size; 878 879 if (r300->screen->caps.is_r500) { 880 r300->fs_rc_constant_state.size = fs->shader->rc_state_count * 7; 881 r300->fs_constants.size = fs->shader->externals_count * 4 + 3; 882 } else { 883 r300->fs_rc_constant_state.size = fs->shader->rc_state_count * 5; 884 r300->fs_constants.size = fs->shader->externals_count * 4 + 1; 885 } 886 887 ((struct r300_constant_buffer*)r300->fs_constants.state)->remap_table = 888 fs->shader->code.constants_remap_table; 889} 890 891/* Bind fragment shader state. */ 892static void r300_bind_fs_state(struct pipe_context* pipe, void* shader) 893{ 894 struct r300_context* r300 = r300_context(pipe); 895 struct r300_fragment_shader* fs = (struct r300_fragment_shader*)shader; 896 struct pipe_framebuffer_state *fb = r300->fb_state.state; 897 boolean last_multi_write; 898 899 if (fs == NULL) { 900 r300->fs.state = NULL; 901 return; 902 } 903 904 last_multi_write = r300_fragment_shader_writes_all(r300_fs(r300)); 905 906 r300->fs.state = fs; 907 r300_pick_fragment_shader(r300); 908 r300_mark_fs_code_dirty(r300); 909 910 if (fb->nr_cbufs > 1 && 911 last_multi_write != r300_fragment_shader_writes_all(fs)) { 912 r300_mark_fb_state_dirty(r300, R300_CHANGED_MULTIWRITE); 913 } 914 915 r300_mark_atom_dirty(r300, &r300->rs_block_state); /* Will be updated before the emission. */ 916} 917 918/* Delete fragment shader state. */ 919static void r300_delete_fs_state(struct pipe_context* pipe, void* shader) 920{ 921 struct r300_fragment_shader* fs = (struct r300_fragment_shader*)shader; 922 struct r300_fragment_shader_code *tmp, *ptr = fs->first; 923 924 while (ptr) { 925 tmp = ptr; 926 ptr = ptr->next; 927 rc_constants_destroy(&tmp->code.constants); 928 FREE(tmp->cb_code); 929 FREE(tmp); 930 } 931 FREE((void*)fs->state.tokens); 932 FREE(shader); 933} 934 935static void r300_set_polygon_stipple(struct pipe_context* pipe, 936 const struct pipe_poly_stipple* state) 937{ 938 /* XXX no idea how to set this up, but not terribly important */ 939} 940 941/* Create a new rasterizer state based on the CSO rasterizer state. 942 * 943 * This is a very large chunk of state, and covers most of the graphics 944 * backend (GB), geometry assembly (GA), and setup unit (SU) blocks. 945 * 946 * In a not entirely unironic sidenote, this state has nearly nothing to do 947 * with the actual block on the Radeon called the rasterizer (RS). */ 948static void* r300_create_rs_state(struct pipe_context* pipe, 949 const struct pipe_rasterizer_state* state) 950{ 951 struct r300_rs_state* rs = CALLOC_STRUCT(r300_rs_state); 952 float psiz; 953 uint32_t vap_control_status; /* R300_VAP_CNTL_STATUS: 0x2140 */ 954 uint32_t point_size; /* R300_GA_POINT_SIZE: 0x421c */ 955 uint32_t point_minmax; /* R300_GA_POINT_MINMAX: 0x4230 */ 956 uint32_t line_control; /* R300_GA_LINE_CNTL: 0x4234 */ 957 uint32_t polygon_offset_enable; /* R300_SU_POLY_OFFSET_ENABLE: 0x42b4 */ 958 uint32_t cull_mode; /* R300_SU_CULL_MODE: 0x42b8 */ 959 uint32_t line_stipple_config; /* R300_GA_LINE_STIPPLE_CONFIG: 0x4328 */ 960 uint32_t line_stipple_value; /* R300_GA_LINE_STIPPLE_VALUE: 0x4260 */ 961 uint32_t polygon_mode; /* R300_GA_POLY_MODE: 0x4288 */ 962 uint32_t clip_rule; /* R300_SC_CLIP_RULE: 0x43D0 */ 963 964 /* Point sprites texture coordinates, 0: lower left, 1: upper right */ 965 float point_texcoord_left = 0; /* R300_GA_POINT_S0: 0x4200 */ 966 float point_texcoord_bottom = 0;/* R300_GA_POINT_T0: 0x4204 */ 967 float point_texcoord_right = 1; /* R300_GA_POINT_S1: 0x4208 */ 968 float point_texcoord_top = 0; /* R300_GA_POINT_T1: 0x420c */ 969 CB_LOCALS; 970 971 /* Copy rasterizer state. */ 972 rs->rs = *state; 973 rs->rs_draw = *state; 974 975 rs->rs.sprite_coord_enable = state->point_quad_rasterization * 976 state->sprite_coord_enable; 977 978 /* Override some states for Draw. */ 979 rs->rs_draw.sprite_coord_enable = 0; /* We can do this in HW. */ 980 981#ifdef PIPE_ARCH_LITTLE_ENDIAN 982 vap_control_status = R300_VC_NO_SWAP; 983#else 984 vap_control_status = R300_VC_32BIT_SWAP; 985#endif 986 987 /* If no TCL engine is present, turn off the HW TCL. */ 988 if (!r300_screen(pipe->screen)->caps.has_tcl) { 989 vap_control_status |= R300_VAP_TCL_BYPASS; 990 } 991 992 /* Point size width and height. */ 993 point_size = 994 pack_float_16_6x(state->point_size) | 995 (pack_float_16_6x(state->point_size) << R300_POINTSIZE_X_SHIFT); 996 997 /* Point size clamping. */ 998 if (state->point_size_per_vertex) { 999 /* Per-vertex point size. 1000 * Clamp to [0, max FB size] */ 1001 psiz = pipe->screen->get_paramf(pipe->screen, 1002 PIPE_CAP_MAX_POINT_WIDTH); 1003 point_minmax = 1004 pack_float_16_6x(psiz) << R300_GA_POINT_MINMAX_MAX_SHIFT; 1005 } else { 1006 /* We cannot disable the point-size vertex output, 1007 * so clamp it. */ 1008 psiz = state->point_size; 1009 point_minmax = 1010 (pack_float_16_6x(psiz) << R300_GA_POINT_MINMAX_MIN_SHIFT) | 1011 (pack_float_16_6x(psiz) << R300_GA_POINT_MINMAX_MAX_SHIFT); 1012 } 1013 1014 /* Line control. */ 1015 line_control = pack_float_16_6x(state->line_width) | 1016 R300_GA_LINE_CNTL_END_TYPE_COMP; 1017 1018 /* Enable polygon mode */ 1019 polygon_mode = 0; 1020 if (state->fill_front != PIPE_POLYGON_MODE_FILL || 1021 state->fill_back != PIPE_POLYGON_MODE_FILL) { 1022 polygon_mode = R300_GA_POLY_MODE_DUAL; 1023 } 1024 1025 /* Front face */ 1026 if (state->front_ccw) 1027 cull_mode = R300_FRONT_FACE_CCW; 1028 else 1029 cull_mode = R300_FRONT_FACE_CW; 1030 1031 /* Polygon offset */ 1032 polygon_offset_enable = 0; 1033 if (util_get_offset(state, state->fill_front)) { 1034 polygon_offset_enable |= R300_FRONT_ENABLE; 1035 } 1036 if (util_get_offset(state, state->fill_back)) { 1037 polygon_offset_enable |= R300_BACK_ENABLE; 1038 } 1039 1040 rs->polygon_offset_enable = polygon_offset_enable != 0; 1041 1042 /* Polygon mode */ 1043 if (polygon_mode) { 1044 polygon_mode |= 1045 r300_translate_polygon_mode_front(state->fill_front); 1046 polygon_mode |= 1047 r300_translate_polygon_mode_back(state->fill_back); 1048 } 1049 1050 if (state->cull_face & PIPE_FACE_FRONT) { 1051 cull_mode |= R300_CULL_FRONT; 1052 } 1053 if (state->cull_face & PIPE_FACE_BACK) { 1054 cull_mode |= R300_CULL_BACK; 1055 } 1056 1057 if (state->line_stipple_enable) { 1058 line_stipple_config = 1059 R300_GA_LINE_STIPPLE_CONFIG_LINE_RESET_LINE | 1060 (fui((float)state->line_stipple_factor) & 1061 R300_GA_LINE_STIPPLE_CONFIG_STIPPLE_SCALE_MASK); 1062 /* XXX this might need to be scaled up */ 1063 line_stipple_value = state->line_stipple_pattern; 1064 } else { 1065 line_stipple_config = 0; 1066 line_stipple_value = 0; 1067 } 1068 1069 if (state->flatshade) { 1070 rs->color_control = R300_SHADE_MODEL_FLAT; 1071 } else { 1072 rs->color_control = R300_SHADE_MODEL_SMOOTH; 1073 } 1074 1075 clip_rule = state->scissor ? 0xAAAA : 0xFFFF; 1076 1077 /* Point sprites coord mode */ 1078 if (rs->rs.sprite_coord_enable) { 1079 switch (state->sprite_coord_mode) { 1080 case PIPE_SPRITE_COORD_UPPER_LEFT: 1081 point_texcoord_top = 0.0f; 1082 point_texcoord_bottom = 1.0f; 1083 break; 1084 case PIPE_SPRITE_COORD_LOWER_LEFT: 1085 point_texcoord_top = 1.0f; 1086 point_texcoord_bottom = 0.0f; 1087 break; 1088 } 1089 } 1090 1091 /* Build the main command buffer. */ 1092 BEGIN_CB(rs->cb_main, RS_STATE_MAIN_SIZE); 1093 OUT_CB_REG(R300_VAP_CNTL_STATUS, vap_control_status); 1094 OUT_CB_REG(R300_GA_POINT_SIZE, point_size); 1095 OUT_CB_REG_SEQ(R300_GA_POINT_MINMAX, 2); 1096 OUT_CB(point_minmax); 1097 OUT_CB(line_control); 1098 OUT_CB_REG_SEQ(R300_SU_POLY_OFFSET_ENABLE, 2); 1099 OUT_CB(polygon_offset_enable); 1100 rs->cull_mode_index = 9; 1101 OUT_CB(cull_mode); 1102 OUT_CB_REG(R300_GA_LINE_STIPPLE_CONFIG, line_stipple_config); 1103 OUT_CB_REG(R300_GA_LINE_STIPPLE_VALUE, line_stipple_value); 1104 OUT_CB_REG(R300_GA_POLY_MODE, polygon_mode); 1105 OUT_CB_REG(R300_SC_CLIP_RULE, clip_rule); 1106 OUT_CB_REG_SEQ(R300_GA_POINT_S0, 4); 1107 OUT_CB_32F(point_texcoord_left); 1108 OUT_CB_32F(point_texcoord_bottom); 1109 OUT_CB_32F(point_texcoord_right); 1110 OUT_CB_32F(point_texcoord_top); 1111 END_CB; 1112 1113 /* Build the two command buffers for polygon offset setup. */ 1114 if (polygon_offset_enable) { 1115 float scale = state->offset_scale * 12; 1116 float offset = state->offset_units * 4; 1117 1118 BEGIN_CB(rs->cb_poly_offset_zb16, 5); 1119 OUT_CB_REG_SEQ(R300_SU_POLY_OFFSET_FRONT_SCALE, 4); 1120 OUT_CB_32F(scale); 1121 OUT_CB_32F(offset); 1122 OUT_CB_32F(scale); 1123 OUT_CB_32F(offset); 1124 END_CB; 1125 1126 offset = state->offset_units * 2; 1127 1128 BEGIN_CB(rs->cb_poly_offset_zb24, 5); 1129 OUT_CB_REG_SEQ(R300_SU_POLY_OFFSET_FRONT_SCALE, 4); 1130 OUT_CB_32F(scale); 1131 OUT_CB_32F(offset); 1132 OUT_CB_32F(scale); 1133 OUT_CB_32F(offset); 1134 END_CB; 1135 } 1136 1137 return (void*)rs; 1138} 1139 1140/* Bind rasterizer state. */ 1141static void r300_bind_rs_state(struct pipe_context* pipe, void* state) 1142{ 1143 struct r300_context* r300 = r300_context(pipe); 1144 struct r300_rs_state* rs = (struct r300_rs_state*)state; 1145 int last_sprite_coord_enable = r300->sprite_coord_enable; 1146 boolean last_two_sided_color = r300->two_sided_color; 1147 1148 if (r300->draw && rs) { 1149 draw_set_rasterizer_state(r300->draw, &rs->rs_draw, state); 1150 } 1151 1152 if (rs) { 1153 r300->polygon_offset_enabled = rs->polygon_offset_enable; 1154 r300->sprite_coord_enable = rs->rs.sprite_coord_enable; 1155 r300->two_sided_color = rs->rs.light_twoside; 1156 } else { 1157 r300->polygon_offset_enabled = FALSE; 1158 r300->sprite_coord_enable = 0; 1159 r300->two_sided_color = FALSE; 1160 } 1161 1162 UPDATE_STATE(state, r300->rs_state); 1163 r300->rs_state.size = RS_STATE_MAIN_SIZE + (r300->polygon_offset_enabled ? 5 : 0); 1164 1165 if (last_sprite_coord_enable != r300->sprite_coord_enable || 1166 last_two_sided_color != r300->two_sided_color) { 1167 r300_mark_atom_dirty(r300, &r300->rs_block_state); 1168 } 1169} 1170 1171/* Free rasterizer state. */ 1172static void r300_delete_rs_state(struct pipe_context* pipe, void* state) 1173{ 1174 FREE(state); 1175} 1176 1177static void* 1178 r300_create_sampler_state(struct pipe_context* pipe, 1179 const struct pipe_sampler_state* state) 1180{ 1181 struct r300_context* r300 = r300_context(pipe); 1182 struct r300_sampler_state* sampler = CALLOC_STRUCT(r300_sampler_state); 1183 boolean is_r500 = r300->screen->caps.is_r500; 1184 int lod_bias; 1185 1186 sampler->state = *state; 1187 1188 /* r300 doesn't handle CLAMP and MIRROR_CLAMP correctly when either MAG 1189 * or MIN filter is NEAREST. Since texwrap produces same results 1190 * for CLAMP and CLAMP_TO_EDGE, we use them instead. */ 1191 if (sampler->state.min_img_filter == PIPE_TEX_FILTER_NEAREST || 1192 sampler->state.mag_img_filter == PIPE_TEX_FILTER_NEAREST) { 1193 /* Wrap S. */ 1194 if (sampler->state.wrap_s == PIPE_TEX_WRAP_CLAMP) 1195 sampler->state.wrap_s = PIPE_TEX_WRAP_CLAMP_TO_EDGE; 1196 else if (sampler->state.wrap_s == PIPE_TEX_WRAP_MIRROR_CLAMP) 1197 sampler->state.wrap_s = PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE; 1198 1199 /* Wrap T. */ 1200 if (sampler->state.wrap_t == PIPE_TEX_WRAP_CLAMP) 1201 sampler->state.wrap_t = PIPE_TEX_WRAP_CLAMP_TO_EDGE; 1202 else if (sampler->state.wrap_t == PIPE_TEX_WRAP_MIRROR_CLAMP) 1203 sampler->state.wrap_t = PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE; 1204 1205 /* Wrap R. */ 1206 if (sampler->state.wrap_r == PIPE_TEX_WRAP_CLAMP) 1207 sampler->state.wrap_r = PIPE_TEX_WRAP_CLAMP_TO_EDGE; 1208 else if (sampler->state.wrap_r == PIPE_TEX_WRAP_MIRROR_CLAMP) 1209 sampler->state.wrap_r = PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE; 1210 } 1211 1212 sampler->filter0 |= 1213 (r300_translate_wrap(sampler->state.wrap_s) << R300_TX_WRAP_S_SHIFT) | 1214 (r300_translate_wrap(sampler->state.wrap_t) << R300_TX_WRAP_T_SHIFT) | 1215 (r300_translate_wrap(sampler->state.wrap_r) << R300_TX_WRAP_R_SHIFT); 1216 1217 sampler->filter0 |= r300_translate_tex_filters(state->min_img_filter, 1218 state->mag_img_filter, 1219 state->min_mip_filter, 1220 state->max_anisotropy > 0); 1221 1222 sampler->filter0 |= r300_anisotropy(state->max_anisotropy); 1223 1224 /* Unfortunately, r300-r500 don't support floating-point mipmap lods. */ 1225 /* We must pass these to the merge function to clamp them properly. */ 1226 sampler->min_lod = (unsigned)MAX2(state->min_lod, 0); 1227 sampler->max_lod = (unsigned)MAX2(ceilf(state->max_lod), 0); 1228 1229 lod_bias = CLAMP((int)(state->lod_bias * 32 + 1), -(1 << 9), (1 << 9) - 1); 1230 1231 sampler->filter1 |= (lod_bias << R300_LOD_BIAS_SHIFT) & R300_LOD_BIAS_MASK; 1232 1233 /* This is very high quality anisotropic filtering for R5xx. 1234 * It's good for benchmarking the performance of texturing but 1235 * in practice we don't want to slow down the driver because it's 1236 * a pretty good performance killer. Feel free to play with it. */ 1237 if (DBG_ON(r300, DBG_ANISOHQ) && is_r500) { 1238 sampler->filter1 |= r500_anisotropy(state->max_anisotropy); 1239 } 1240 1241 /* R500-specific fixups and optimizations */ 1242 if (r300->screen->caps.is_r500) { 1243 sampler->filter1 |= R500_BORDER_FIX; 1244 } 1245 1246 return (void*)sampler; 1247} 1248 1249static void r300_bind_sampler_states(struct pipe_context* pipe, 1250 unsigned count, 1251 void** states) 1252{ 1253 struct r300_context* r300 = r300_context(pipe); 1254 struct r300_textures_state* state = 1255 (struct r300_textures_state*)r300->textures_state.state; 1256 unsigned tex_units = r300->screen->caps.num_tex_units; 1257 1258 if (count > tex_units) { 1259 return; 1260 } 1261 1262 memcpy(state->sampler_states, states, sizeof(void*) * count); 1263 state->sampler_state_count = count; 1264 1265 r300_mark_atom_dirty(r300, &r300->textures_state); 1266} 1267 1268static void r300_lacks_vertex_textures(struct pipe_context* pipe, 1269 unsigned count, 1270 void** states) 1271{ 1272} 1273 1274static void r300_delete_sampler_state(struct pipe_context* pipe, void* state) 1275{ 1276 FREE(state); 1277} 1278 1279static uint32_t r300_assign_texture_cache_region(unsigned index, unsigned num) 1280{ 1281 /* This looks like a hack, but I believe it's suppose to work like 1282 * that. To illustrate how this works, let's assume you have 5 textures. 1283 * From docs, 5 and the successive numbers are: 1284 * 1285 * FOURTH_1 = 5 1286 * FOURTH_2 = 6 1287 * FOURTH_3 = 7 1288 * EIGHTH_0 = 8 1289 * EIGHTH_1 = 9 1290 * 1291 * First 3 textures will get 3/4 of size of the cache, divived evenly 1292 * between them. The last 1/4 of the cache must be divided between 1293 * the last 2 textures, each will therefore get 1/8 of the cache. 1294 * Why not just to use "5 + texture_index" ? 1295 * 1296 * This simple trick works for all "num" <= 16. 1297 */ 1298 if (num <= 1) 1299 return R300_TX_CACHE(R300_TX_CACHE_WHOLE); 1300 else 1301 return R300_TX_CACHE(num + index); 1302} 1303 1304static void r300_set_fragment_sampler_views(struct pipe_context* pipe, 1305 unsigned count, 1306 struct pipe_sampler_view** views) 1307{ 1308 struct r300_context* r300 = r300_context(pipe); 1309 struct r300_textures_state* state = 1310 (struct r300_textures_state*)r300->textures_state.state; 1311 struct r300_resource *texture; 1312 unsigned i, real_num_views = 0, view_index = 0; 1313 unsigned tex_units = r300->screen->caps.num_tex_units; 1314 boolean dirty_tex = FALSE; 1315 1316 if (count > tex_units) { 1317 return; 1318 } 1319 1320 /* Calculate the real number of views. */ 1321 for (i = 0; i < count; i++) { 1322 if (views[i]) 1323 real_num_views++; 1324 } 1325 1326 for (i = 0; i < count; i++) { 1327 pipe_sampler_view_reference( 1328 (struct pipe_sampler_view**)&state->sampler_views[i], 1329 views[i]); 1330 1331 if (!views[i]) { 1332 continue; 1333 } 1334 1335 /* A new sampler view (= texture)... */ 1336 dirty_tex = TRUE; 1337 1338 /* Set the texrect factor in the fragment shader. 1339 * Needed for RECT and NPOT fallback. */ 1340 texture = r300_resource(views[i]->texture); 1341 if (texture->tex.is_npot) { 1342 r300_mark_atom_dirty(r300, &r300->fs_rc_constant_state); 1343 } 1344 1345 state->sampler_views[i]->texcache_region = 1346 r300_assign_texture_cache_region(view_index, real_num_views); 1347 view_index++; 1348 } 1349 1350 for (i = count; i < tex_units; i++) { 1351 if (state->sampler_views[i]) { 1352 pipe_sampler_view_reference( 1353 (struct pipe_sampler_view**)&state->sampler_views[i], 1354 NULL); 1355 } 1356 } 1357 1358 state->sampler_view_count = count; 1359 1360 r300_mark_atom_dirty(r300, &r300->textures_state); 1361 1362 if (dirty_tex) { 1363 r300_mark_atom_dirty(r300, &r300->texture_cache_inval); 1364 } 1365} 1366 1367static struct pipe_sampler_view * 1368r300_create_sampler_view(struct pipe_context *pipe, 1369 struct pipe_resource *texture, 1370 const struct pipe_sampler_view *templ) 1371{ 1372 struct r300_sampler_view *view = CALLOC_STRUCT(r300_sampler_view); 1373 struct r300_resource *tex = r300_resource(texture); 1374 boolean is_r500 = r300_screen(pipe->screen)->caps.is_r500; 1375 boolean dxtc_swizzle = r300_screen(pipe->screen)->caps.dxtc_swizzle; 1376 1377 if (view) { 1378 view->base = *templ; 1379 view->base.reference.count = 1; 1380 view->base.context = pipe; 1381 view->base.texture = NULL; 1382 pipe_resource_reference(&view->base.texture, texture); 1383 1384 view->swizzle[0] = templ->swizzle_r; 1385 view->swizzle[1] = templ->swizzle_g; 1386 view->swizzle[2] = templ->swizzle_b; 1387 view->swizzle[3] = templ->swizzle_a; 1388 1389 view->format = tex->tx_format; 1390 view->format.format1 |= r300_translate_texformat(templ->format, 1391 view->swizzle, 1392 is_r500, 1393 dxtc_swizzle); 1394 if (is_r500) { 1395 view->format.format2 |= r500_tx_format_msb_bit(templ->format); 1396 } 1397 } 1398 1399 return (struct pipe_sampler_view*)view; 1400} 1401 1402static void 1403r300_sampler_view_destroy(struct pipe_context *pipe, 1404 struct pipe_sampler_view *view) 1405{ 1406 pipe_resource_reference(&view->texture, NULL); 1407 FREE(view); 1408} 1409 1410static void r300_set_scissor_state(struct pipe_context* pipe, 1411 const struct pipe_scissor_state* state) 1412{ 1413 struct r300_context* r300 = r300_context(pipe); 1414 1415 memcpy(r300->scissor_state.state, state, 1416 sizeof(struct pipe_scissor_state)); 1417 1418 r300_mark_atom_dirty(r300, &r300->scissor_state); 1419} 1420 1421static void r300_set_viewport_state(struct pipe_context* pipe, 1422 const struct pipe_viewport_state* state) 1423{ 1424 struct r300_context* r300 = r300_context(pipe); 1425 struct r300_viewport_state* viewport = 1426 (struct r300_viewport_state*)r300->viewport_state.state; 1427 1428 r300->viewport = *state; 1429 1430 if (r300->draw) { 1431 draw_set_viewport_state(r300->draw, state); 1432 viewport->vte_control = R300_VTX_XY_FMT | R300_VTX_Z_FMT; 1433 return; 1434 } 1435 1436 /* Do the transform in HW. */ 1437 viewport->vte_control = R300_VTX_W0_FMT; 1438 1439 if (state->scale[0] != 1.0f) { 1440 viewport->xscale = state->scale[0]; 1441 viewport->vte_control |= R300_VPORT_X_SCALE_ENA; 1442 } 1443 if (state->scale[1] != 1.0f) { 1444 viewport->yscale = state->scale[1]; 1445 viewport->vte_control |= R300_VPORT_Y_SCALE_ENA; 1446 } 1447 if (state->scale[2] != 1.0f) { 1448 viewport->zscale = state->scale[2]; 1449 viewport->vte_control |= R300_VPORT_Z_SCALE_ENA; 1450 } 1451 if (state->translate[0] != 0.0f) { 1452 viewport->xoffset = state->translate[0]; 1453 viewport->vte_control |= R300_VPORT_X_OFFSET_ENA; 1454 } 1455 if (state->translate[1] != 0.0f) { 1456 viewport->yoffset = state->translate[1]; 1457 viewport->vte_control |= R300_VPORT_Y_OFFSET_ENA; 1458 } 1459 if (state->translate[2] != 0.0f) { 1460 viewport->zoffset = state->translate[2]; 1461 viewport->vte_control |= R300_VPORT_Z_OFFSET_ENA; 1462 } 1463 1464 r300_mark_atom_dirty(r300, &r300->viewport_state); 1465 if (r300->fs.state && r300_fs(r300)->shader->inputs.wpos != ATTR_UNUSED) { 1466 r300_mark_atom_dirty(r300, &r300->fs_rc_constant_state); 1467 } 1468} 1469 1470static void r300_set_vertex_buffers(struct pipe_context* pipe, 1471 unsigned count, 1472 const struct pipe_vertex_buffer* buffers) 1473{ 1474 struct r300_context* r300 = r300_context(pipe); 1475 unsigned i; 1476 struct pipe_vertex_buffer dummy_vb = {0}; 1477 1478 /* There must be at least one vertex buffer set, otherwise it locks up. */ 1479 if (!count) { 1480 dummy_vb.buffer = r300->dummy_vb; 1481 buffers = &dummy_vb; 1482 count = 1; 1483 } 1484 1485 u_vbuf_mgr_set_vertex_buffers(r300->vbuf_mgr, count, buffers); 1486 1487 if (r300->screen->caps.has_tcl) { 1488 /* HW TCL. */ 1489 for (i = 0; i < count; i++) { 1490 if (buffers[i].buffer && 1491 !r300_resource(buffers[i].buffer)->b.user_ptr) { 1492 } 1493 } 1494 r300->vertex_arrays_dirty = TRUE; 1495 } else { 1496 /* SW TCL. */ 1497 draw_set_vertex_buffers(r300->draw, count, buffers); 1498 } 1499} 1500 1501static void r300_set_index_buffer(struct pipe_context* pipe, 1502 const struct pipe_index_buffer *ib) 1503{ 1504 struct r300_context* r300 = r300_context(pipe); 1505 1506 if (ib && ib->buffer) { 1507 assert(ib->offset % ib->index_size == 0); 1508 1509 pipe_resource_reference(&r300->index_buffer.buffer, ib->buffer); 1510 memcpy(&r300->index_buffer, ib, sizeof(r300->index_buffer)); 1511 r300->index_buffer.offset /= r300->index_buffer.index_size; 1512 } 1513 else { 1514 pipe_resource_reference(&r300->index_buffer.buffer, NULL); 1515 memset(&r300->index_buffer, 0, sizeof(r300->index_buffer)); 1516 } 1517 1518 if (!r300->screen->caps.has_tcl) { 1519 draw_set_index_buffer(r300->draw, ib); 1520 } 1521} 1522 1523/* Initialize the PSC tables. */ 1524static void r300_vertex_psc(struct r300_vertex_element_state *velems) 1525{ 1526 struct r300_vertex_stream_state *vstream = &velems->vertex_stream; 1527 uint16_t type, swizzle; 1528 enum pipe_format format; 1529 unsigned i; 1530 1531 if (velems->count > 16) { 1532 fprintf(stderr, "r300: More than 16 vertex elements are not supported," 1533 " requested %i, using 16.\n", velems->count); 1534 velems->count = 16; 1535 } 1536 1537 /* Vertex shaders have no semantics on their inputs, 1538 * so PSC should just route stuff based on the vertex elements, 1539 * and not on attrib information. */ 1540 for (i = 0; i < velems->count; i++) { 1541 format = velems->velem[i].src_format; 1542 1543 type = r300_translate_vertex_data_type(format); 1544 if (type == R300_INVALID_FORMAT) { 1545 fprintf(stderr, "r300: Bad vertex format %s.\n", 1546 util_format_short_name(format)); 1547 assert(0); 1548 abort(); 1549 } 1550 1551 type |= i << R300_DST_VEC_LOC_SHIFT; 1552 swizzle = r300_translate_vertex_data_swizzle(format); 1553 1554 if (i & 1) { 1555 vstream->vap_prog_stream_cntl[i >> 1] |= type << 16; 1556 vstream->vap_prog_stream_cntl_ext[i >> 1] |= swizzle << 16; 1557 } else { 1558 vstream->vap_prog_stream_cntl[i >> 1] |= type; 1559 vstream->vap_prog_stream_cntl_ext[i >> 1] |= swizzle; 1560 } 1561 } 1562 1563 /* Set the last vector in the PSC. */ 1564 if (i) { 1565 i -= 1; 1566 } 1567 vstream->vap_prog_stream_cntl[i >> 1] |= 1568 (R300_LAST_VEC << (i & 1 ? 16 : 0)); 1569 1570 vstream->count = (i >> 1) + 1; 1571} 1572 1573static void* r300_create_vertex_elements_state(struct pipe_context* pipe, 1574 unsigned count, 1575 const struct pipe_vertex_element* attribs) 1576{ 1577 struct r300_context *r300 = r300_context(pipe); 1578 struct r300_vertex_element_state *velems; 1579 unsigned i; 1580 struct pipe_vertex_element dummy_attrib = {0}; 1581 1582 /* R300 Programmable Stream Control (PSC) doesn't support 0 vertex elements. */ 1583 if (!count) { 1584 dummy_attrib.src_format = PIPE_FORMAT_R8G8B8A8_UNORM; 1585 attribs = &dummy_attrib; 1586 count = 1; 1587 } 1588 1589 assert(count <= PIPE_MAX_ATTRIBS); 1590 velems = CALLOC_STRUCT(r300_vertex_element_state); 1591 if (!velems) 1592 return NULL; 1593 1594 velems->count = count; 1595 velems->vmgr_elements = 1596 u_vbuf_mgr_create_vertex_elements(r300->vbuf_mgr, count, attribs, 1597 velems->velem); 1598 1599 if (r300_screen(pipe->screen)->caps.has_tcl) { 1600 /* Setup PSC. 1601 * The unused components will be replaced by (..., 0, 1). */ 1602 r300_vertex_psc(velems); 1603 1604 for (i = 0; i < count; i++) { 1605 velems->format_size[i] = 1606 align(util_format_get_blocksize(velems->velem[i].src_format), 4); 1607 velems->vertex_size_dwords += velems->format_size[i] / 4; 1608 } 1609 } 1610 1611 return velems; 1612} 1613 1614static void r300_bind_vertex_elements_state(struct pipe_context *pipe, 1615 void *state) 1616{ 1617 struct r300_context *r300 = r300_context(pipe); 1618 struct r300_vertex_element_state *velems = state; 1619 1620 if (velems == NULL) { 1621 return; 1622 } 1623 1624 r300->velems = velems; 1625 1626 u_vbuf_mgr_bind_vertex_elements(r300->vbuf_mgr, state, velems->vmgr_elements); 1627 1628 if (r300->draw) { 1629 draw_set_vertex_elements(r300->draw, velems->count, velems->velem); 1630 return; 1631 } 1632 1633 UPDATE_STATE(&velems->vertex_stream, r300->vertex_stream_state); 1634 r300->vertex_stream_state.size = (1 + velems->vertex_stream.count) * 2; 1635 r300->vertex_arrays_dirty = TRUE; 1636} 1637 1638static void r300_delete_vertex_elements_state(struct pipe_context *pipe, void *state) 1639{ 1640 struct r300_context *r300 = r300_context(pipe); 1641 struct r300_vertex_element_state *velems = state; 1642 1643 u_vbuf_mgr_destroy_vertex_elements(r300->vbuf_mgr, velems->vmgr_elements); 1644 FREE(state); 1645} 1646 1647static void* r300_create_vs_state(struct pipe_context* pipe, 1648 const struct pipe_shader_state* shader) 1649{ 1650 struct r300_context* r300 = r300_context(pipe); 1651 struct r300_vertex_shader* vs = CALLOC_STRUCT(r300_vertex_shader); 1652 1653 /* Copy state directly into shader. */ 1654 vs->state = *shader; 1655 vs->state.tokens = tgsi_dup_tokens(shader->tokens); 1656 1657 if (r300->screen->caps.has_tcl) { 1658 r300_init_vs_outputs(vs); 1659 r300_translate_vertex_shader(r300, vs); 1660 } else { 1661 r300_draw_init_vertex_shader(r300->draw, vs); 1662 } 1663 1664 return vs; 1665} 1666 1667static void r300_bind_vs_state(struct pipe_context* pipe, void* shader) 1668{ 1669 struct r300_context* r300 = r300_context(pipe); 1670 struct r300_vertex_shader* vs = (struct r300_vertex_shader*)shader; 1671 1672 if (vs == NULL) { 1673 r300->vs_state.state = NULL; 1674 return; 1675 } 1676 if (vs == r300->vs_state.state) { 1677 return; 1678 } 1679 r300->vs_state.state = vs; 1680 1681 /* The majority of the RS block bits is dependent on the vertex shader. */ 1682 r300_mark_atom_dirty(r300, &r300->rs_block_state); /* Will be updated before the emission. */ 1683 1684 if (r300->screen->caps.has_tcl) { 1685 unsigned fc_op_dwords = r300->screen->caps.is_r500 ? 3 : 2; 1686 r300_mark_atom_dirty(r300, &r300->vs_state); 1687 r300->vs_state.size = 1688 vs->code.length + 9 + 1689 (vs->code.num_fc_ops ? vs->code.num_fc_ops * fc_op_dwords + 4 : 0); 1690 1691 r300_mark_atom_dirty(r300, &r300->vs_constants); 1692 r300->vs_constants.size = 1693 2 + 1694 (vs->externals_count ? vs->externals_count * 4 + 3 : 0) + 1695 (vs->immediates_count ? vs->immediates_count * 4 + 3 : 0); 1696 1697 ((struct r300_constant_buffer*)r300->vs_constants.state)->remap_table = 1698 vs->code.constants_remap_table; 1699 1700 r300_mark_atom_dirty(r300, &r300->pvs_flush); 1701 } else { 1702 draw_bind_vertex_shader(r300->draw, 1703 (struct draw_vertex_shader*)vs->draw_vs); 1704 } 1705} 1706 1707static void r300_delete_vs_state(struct pipe_context* pipe, void* shader) 1708{ 1709 struct r300_context* r300 = r300_context(pipe); 1710 struct r300_vertex_shader* vs = (struct r300_vertex_shader*)shader; 1711 1712 if (r300->screen->caps.has_tcl) { 1713 rc_constants_destroy(&vs->code.constants); 1714 if (vs->code.constants_remap_table) 1715 FREE(vs->code.constants_remap_table); 1716 } else { 1717 draw_delete_vertex_shader(r300->draw, 1718 (struct draw_vertex_shader*)vs->draw_vs); 1719 } 1720 1721 FREE((void*)vs->state.tokens); 1722 FREE(shader); 1723} 1724 1725static void r300_set_constant_buffer(struct pipe_context *pipe, 1726 uint shader, uint index, 1727 struct pipe_resource *buf) 1728{ 1729 struct r300_context* r300 = r300_context(pipe); 1730 struct r300_constant_buffer *cbuf; 1731 struct r300_resource *rbuf = r300_resource(buf); 1732 uint32_t *mapped; 1733 1734 switch (shader) { 1735 case PIPE_SHADER_VERTEX: 1736 cbuf = (struct r300_constant_buffer*)r300->vs_constants.state; 1737 break; 1738 case PIPE_SHADER_FRAGMENT: 1739 cbuf = (struct r300_constant_buffer*)r300->fs_constants.state; 1740 break; 1741 default: 1742 return; 1743 } 1744 1745 if (buf == NULL || buf->width0 == 0) 1746 return; 1747 1748 if (rbuf->b.user_ptr) 1749 mapped = (uint32_t*)rbuf->b.user_ptr; 1750 else if (rbuf->constant_buffer) 1751 mapped = (uint32_t*)rbuf->constant_buffer; 1752 else 1753 return; 1754 1755 if (shader == PIPE_SHADER_FRAGMENT || 1756 (shader == PIPE_SHADER_VERTEX && r300->screen->caps.has_tcl)) { 1757 cbuf->ptr = mapped; 1758 } 1759 1760 if (shader == PIPE_SHADER_VERTEX) { 1761 if (r300->screen->caps.has_tcl) { 1762 struct r300_vertex_shader *vs = 1763 (struct r300_vertex_shader*)r300->vs_state.state; 1764 1765 if (!vs) { 1766 cbuf->buffer_base = 0; 1767 return; 1768 } 1769 1770 cbuf->buffer_base = r300->vs_const_base; 1771 r300->vs_const_base += vs->code.constants.Count; 1772 if (r300->vs_const_base > R500_MAX_PVS_CONST_VECS) { 1773 r300->vs_const_base = vs->code.constants.Count; 1774 cbuf->buffer_base = 0; 1775 r300_mark_atom_dirty(r300, &r300->pvs_flush); 1776 } 1777 r300_mark_atom_dirty(r300, &r300->vs_constants); 1778 } else if (r300->draw) { 1779 draw_set_mapped_constant_buffer(r300->draw, PIPE_SHADER_VERTEX, 1780 0, mapped, buf->width0); 1781 } 1782 } else if (shader == PIPE_SHADER_FRAGMENT) { 1783 r300_mark_atom_dirty(r300, &r300->fs_constants); 1784 } 1785} 1786 1787void r300_init_state_functions(struct r300_context* r300) 1788{ 1789 r300->context.create_blend_state = r300_create_blend_state; 1790 r300->context.bind_blend_state = r300_bind_blend_state; 1791 r300->context.delete_blend_state = r300_delete_blend_state; 1792 1793 r300->context.set_blend_color = r300_set_blend_color; 1794 1795 r300->context.set_clip_state = r300_set_clip_state; 1796 r300->context.set_sample_mask = r300_set_sample_mask; 1797 1798 r300->context.set_constant_buffer = r300_set_constant_buffer; 1799 1800 r300->context.create_depth_stencil_alpha_state = r300_create_dsa_state; 1801 r300->context.bind_depth_stencil_alpha_state = r300_bind_dsa_state; 1802 r300->context.delete_depth_stencil_alpha_state = r300_delete_dsa_state; 1803 1804 r300->context.set_stencil_ref = r300_set_stencil_ref; 1805 1806 r300->context.set_framebuffer_state = r300_set_framebuffer_state; 1807 1808 r300->context.create_fs_state = r300_create_fs_state; 1809 r300->context.bind_fs_state = r300_bind_fs_state; 1810 r300->context.delete_fs_state = r300_delete_fs_state; 1811 1812 r300->context.set_polygon_stipple = r300_set_polygon_stipple; 1813 1814 r300->context.create_rasterizer_state = r300_create_rs_state; 1815 r300->context.bind_rasterizer_state = r300_bind_rs_state; 1816 r300->context.delete_rasterizer_state = r300_delete_rs_state; 1817 1818 r300->context.create_sampler_state = r300_create_sampler_state; 1819 r300->context.bind_fragment_sampler_states = r300_bind_sampler_states; 1820 r300->context.bind_vertex_sampler_states = r300_lacks_vertex_textures; 1821 r300->context.delete_sampler_state = r300_delete_sampler_state; 1822 1823 r300->context.set_fragment_sampler_views = r300_set_fragment_sampler_views; 1824 r300->context.create_sampler_view = r300_create_sampler_view; 1825 r300->context.sampler_view_destroy = r300_sampler_view_destroy; 1826 1827 r300->context.set_scissor_state = r300_set_scissor_state; 1828 1829 r300->context.set_viewport_state = r300_set_viewport_state; 1830 1831 r300->context.set_vertex_buffers = r300_set_vertex_buffers; 1832 r300->context.set_index_buffer = r300_set_index_buffer; 1833 r300->context.redefine_user_buffer = u_default_redefine_user_buffer; 1834 1835 r300->context.create_vertex_elements_state = r300_create_vertex_elements_state; 1836 r300->context.bind_vertex_elements_state = r300_bind_vertex_elements_state; 1837 r300->context.delete_vertex_elements_state = r300_delete_vertex_elements_state; 1838 1839 r300->context.create_vs_state = r300_create_vs_state; 1840 r300->context.bind_vs_state = r300_bind_vs_state; 1841 r300->context.delete_vs_state = r300_delete_vs_state; 1842} 1843