i830_vtbl.c revision 3541cc0d40f86d8ea63a876b7215831335ec677d 
1/**************************************************************************
2 *
3 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 **************************************************************************/
27
28#include "i830_context.h"
29#include "i830_reg.h"
30#include "intel_batchbuffer.h"
31#include "intel_regions.h"
32#include "intel_tris.h"
33#include "intel_fbo.h"
34#include "tnl/tnl.h"
35#include "tnl/t_context.h"
36#include "tnl/t_vertex.h"
37#include "swrast_setup/swrast_setup.h"
38
39#define FILE_DEBUG_FLAG DEBUG_STATE
40
41static GLboolean i830_check_vertex_size(struct intel_context *intel,
42                                        GLuint expected);
43
44#define SZ_TO_HW(sz)  ((sz-2)&0x3)
45#define EMIT_SZ(sz)   (EMIT_1F + (sz) - 1)
46#define EMIT_ATTR( ATTR, STYLE, V0 )					\
47do {									\
48   intel->vertex_attrs[intel->vertex_attr_count].attrib = (ATTR);	\
49   intel->vertex_attrs[intel->vertex_attr_count].format = (STYLE);	\
50   intel->vertex_attr_count++;						\
51   v0 |= V0;								\
52} while (0)
53
54#define EMIT_PAD( N )							\
55do {									\
56   intel->vertex_attrs[intel->vertex_attr_count].attrib = 0;		\
57   intel->vertex_attrs[intel->vertex_attr_count].format = EMIT_PAD;	\
58   intel->vertex_attrs[intel->vertex_attr_count].offset = (N);		\
59   intel->vertex_attr_count++;						\
60} while (0)
61
62
63#define VRTX_TEX_SET_FMT(n, x)          ((x)<<((n)*2))
64#define TEXBIND_SET(n, x) 		((x)<<((n)*4))
65
66static void
67i830_render_prevalidate(struct intel_context *intel)
68{
69}
70
71static void
72i830_render_start(struct intel_context *intel)
73{
74   struct gl_context *ctx = &intel->ctx;
75   struct i830_context *i830 = i830_context(ctx);
76   TNLcontext *tnl = TNL_CONTEXT(ctx);
77   struct vertex_buffer *VB = &tnl->vb;
78   DECLARE_RENDERINPUTS(index_bitset);
79   GLuint v0 = _3DSTATE_VFT0_CMD;
80   GLuint v2 = _3DSTATE_VFT1_CMD;
81   GLuint mcsb1 = 0;
82
83   RENDERINPUTS_COPY(index_bitset, tnl->render_inputs_bitset);
84
85   /* Important:
86    */
87   VB->AttribPtr[VERT_ATTRIB_POS] = VB->NdcPtr;
88   intel->vertex_attr_count = 0;
89
90   /* EMIT_ATTR's must be in order as they tell t_vertex.c how to
91    * build up a hardware vertex.
92    */
93   if (RENDERINPUTS_TEST_RANGE(index_bitset, _TNL_FIRST_TEX, _TNL_LAST_TEX)) {
94      EMIT_ATTR(_TNL_ATTRIB_POS, EMIT_4F_VIEWPORT, VFT0_XYZW);
95      intel->coloroffset = 4;
96   }
97   else {
98      EMIT_ATTR(_TNL_ATTRIB_POS, EMIT_3F_VIEWPORT, VFT0_XYZ);
99      intel->coloroffset = 3;
100   }
101
102   if (RENDERINPUTS_TEST(index_bitset, _TNL_ATTRIB_POINTSIZE)) {
103      EMIT_ATTR(_TNL_ATTRIB_POINTSIZE, EMIT_1F, VFT0_POINT_WIDTH);
104   }
105
106   EMIT_ATTR(_TNL_ATTRIB_COLOR0, EMIT_4UB_4F_BGRA, VFT0_DIFFUSE);
107
108   intel->specoffset = 0;
109   if (RENDERINPUTS_TEST(index_bitset, _TNL_ATTRIB_COLOR1) ||
110       RENDERINPUTS_TEST(index_bitset, _TNL_ATTRIB_FOG)) {
111      if (RENDERINPUTS_TEST(index_bitset, _TNL_ATTRIB_COLOR1)) {
112         intel->specoffset = intel->coloroffset + 1;
113         EMIT_ATTR(_TNL_ATTRIB_COLOR1, EMIT_3UB_3F_BGR, VFT0_SPEC);
114      }
115      else
116         EMIT_PAD(3);
117
118      if (RENDERINPUTS_TEST(index_bitset, _TNL_ATTRIB_FOG))
119         EMIT_ATTR(_TNL_ATTRIB_FOG, EMIT_1UB_1F, VFT0_SPEC);
120      else
121         EMIT_PAD(1);
122   }
123
124   if (RENDERINPUTS_TEST_RANGE(index_bitset, _TNL_FIRST_TEX, _TNL_LAST_TEX)) {
125      int i, count = 0;
126
127      for (i = 0; i < I830_TEX_UNITS; i++) {
128         if (RENDERINPUTS_TEST(index_bitset, _TNL_ATTRIB_TEX(i))) {
129            GLuint sz = VB->AttribPtr[_TNL_ATTRIB_TEX0 + i]->size;
130            GLuint emit;
131            GLuint mcs = (i830->state.Tex[i][I830_TEXREG_MCS] &
132                          ~TEXCOORDTYPE_MASK);
133
134            switch (sz) {
135            case 1:
136            case 2:
137               emit = EMIT_2F;
138               sz = 2;
139               mcs |= TEXCOORDTYPE_CARTESIAN;
140               break;
141            case 3:
142               emit = EMIT_3F;
143               sz = 3;
144               mcs |= TEXCOORDTYPE_VECTOR;
145               break;
146            case 4:
147               emit = EMIT_3F_XYW;
148               sz = 3;
149               mcs |= TEXCOORDTYPE_HOMOGENEOUS;
150               break;
151            default:
152               continue;
153            };
154
155
156            EMIT_ATTR(_TNL_ATTRIB_TEX0 + i, emit, 0);
157            v2 |= VRTX_TEX_SET_FMT(count, SZ_TO_HW(sz));
158            mcsb1 |= (count + 8) << (i * 4);
159
160            if (mcs != i830->state.Tex[i][I830_TEXREG_MCS]) {
161               I830_STATECHANGE(i830, I830_UPLOAD_TEX(i));
162               i830->state.Tex[i][I830_TEXREG_MCS] = mcs;
163            }
164
165            count++;
166         }
167      }
168
169      v0 |= VFT0_TEX_COUNT(count);
170   }
171
172   /* Only need to change the vertex emit code if there has been a
173    * statechange to a new hardware vertex format:
174    */
175   if (v0 != i830->state.Ctx[I830_CTXREG_VF] ||
176       v2 != i830->state.Ctx[I830_CTXREG_VF2] ||
177       mcsb1 != i830->state.Ctx[I830_CTXREG_MCSB1] ||
178       !RENDERINPUTS_EQUAL(index_bitset, i830->last_index_bitset)) {
179      int k;
180
181      I830_STATECHANGE(i830, I830_UPLOAD_CTX);
182
183      /* Must do this *after* statechange, so as not to affect
184       * buffered vertices reliant on the old state:
185       */
186      intel->vertex_size =
187         _tnl_install_attrs(ctx,
188                            intel->vertex_attrs,
189                            intel->vertex_attr_count,
190                            intel->ViewportMatrix.m, 0);
191
192      intel->vertex_size >>= 2;
193
194      i830->state.Ctx[I830_CTXREG_VF] = v0;
195      i830->state.Ctx[I830_CTXREG_VF2] = v2;
196      i830->state.Ctx[I830_CTXREG_MCSB1] = mcsb1;
197      RENDERINPUTS_COPY(i830->last_index_bitset, index_bitset);
198
199      k = i830_check_vertex_size(intel, intel->vertex_size);
200      assert(k);
201   }
202}
203
204static void
205i830_reduced_primitive_state(struct intel_context *intel, GLenum rprim)
206{
207   struct i830_context *i830 = i830_context(&intel->ctx);
208   GLuint st1 = i830->state.Stipple[I830_STPREG_ST1];
209
210   st1 &= ~ST1_ENABLE;
211
212   switch (rprim) {
213   case GL_TRIANGLES:
214      if (intel->ctx.Polygon.StippleFlag && intel->hw_stipple)
215         st1 |= ST1_ENABLE;
216      break;
217   case GL_LINES:
218   case GL_POINTS:
219   default:
220      break;
221   }
222
223   i830->intel.reduced_primitive = rprim;
224
225   if (st1 != i830->state.Stipple[I830_STPREG_ST1]) {
226      INTEL_FIREVERTICES(intel);
227
228      I830_STATECHANGE(i830, I830_UPLOAD_STIPPLE);
229      i830->state.Stipple[I830_STPREG_ST1] = st1;
230   }
231}
232
233/* Pull apart the vertex format registers and figure out how large a
234 * vertex is supposed to be.
235 */
236static GLboolean
237i830_check_vertex_size(struct intel_context *intel, GLuint expected)
238{
239   struct i830_context *i830 = i830_context(&intel->ctx);
240   int vft0 = i830->state.Ctx[I830_CTXREG_VF];
241   int vft1 = i830->state.Ctx[I830_CTXREG_VF2];
242   int nrtex = (vft0 & VFT0_TEX_COUNT_MASK) >> VFT0_TEX_COUNT_SHIFT;
243   int i, sz = 0;
244
245   switch (vft0 & VFT0_XYZW_MASK) {
246   case VFT0_XY:
247      sz = 2;
248      break;
249   case VFT0_XYZ:
250      sz = 3;
251      break;
252   case VFT0_XYW:
253      sz = 3;
254      break;
255   case VFT0_XYZW:
256      sz = 4;
257      break;
258   default:
259      fprintf(stderr, "no xyzw specified\n");
260      return 0;
261   }
262
263   if (vft0 & VFT0_SPEC)
264      sz++;
265   if (vft0 & VFT0_DIFFUSE)
266      sz++;
267   if (vft0 & VFT0_DEPTH_OFFSET)
268      sz++;
269   if (vft0 & VFT0_POINT_WIDTH)
270      sz++;
271
272   for (i = 0; i < nrtex; i++) {
273      switch (vft1 & VFT1_TEX0_MASK) {
274      case TEXCOORDFMT_2D:
275         sz += 2;
276         break;
277      case TEXCOORDFMT_3D:
278         sz += 3;
279         break;
280      case TEXCOORDFMT_4D:
281         sz += 4;
282         break;
283      case TEXCOORDFMT_1D:
284         sz += 1;
285         break;
286      }
287      vft1 >>= VFT1_TEX1_SHIFT;
288   }
289
290   if (sz != expected)
291      fprintf(stderr, "vertex size mismatch %d/%d\n", sz, expected);
292
293   return sz == expected;
294}
295
296static void
297i830_emit_invarient_state(struct intel_context *intel)
298{
299   BATCH_LOCALS;
300
301   BEGIN_BATCH(29);
302
303   OUT_BATCH(_3DSTATE_DFLT_DIFFUSE_CMD);
304   OUT_BATCH(0);
305
306   OUT_BATCH(_3DSTATE_DFLT_SPEC_CMD);
307   OUT_BATCH(0);
308
309   OUT_BATCH(_3DSTATE_DFLT_Z_CMD);
310   OUT_BATCH(0);
311
312   OUT_BATCH(_3DSTATE_FOG_MODE_CMD);
313   OUT_BATCH(FOGFUNC_ENABLE |
314             FOG_LINEAR_CONST | FOGSRC_INDEX_Z | ENABLE_FOG_DENSITY);
315   OUT_BATCH(0);
316   OUT_BATCH(0);
317
318
319   OUT_BATCH(_3DSTATE_MAP_TEX_STREAM_CMD |
320             MAP_UNIT(0) |
321             DISABLE_TEX_STREAM_BUMP |
322             ENABLE_TEX_STREAM_COORD_SET |
323             TEX_STREAM_COORD_SET(0) |
324             ENABLE_TEX_STREAM_MAP_IDX | TEX_STREAM_MAP_IDX(0));
325   OUT_BATCH(_3DSTATE_MAP_TEX_STREAM_CMD |
326             MAP_UNIT(1) |
327             DISABLE_TEX_STREAM_BUMP |
328             ENABLE_TEX_STREAM_COORD_SET |
329             TEX_STREAM_COORD_SET(1) |
330             ENABLE_TEX_STREAM_MAP_IDX | TEX_STREAM_MAP_IDX(1));
331   OUT_BATCH(_3DSTATE_MAP_TEX_STREAM_CMD |
332             MAP_UNIT(2) |
333             DISABLE_TEX_STREAM_BUMP |
334             ENABLE_TEX_STREAM_COORD_SET |
335             TEX_STREAM_COORD_SET(2) |
336             ENABLE_TEX_STREAM_MAP_IDX | TEX_STREAM_MAP_IDX(2));
337   OUT_BATCH(_3DSTATE_MAP_TEX_STREAM_CMD |
338             MAP_UNIT(3) |
339             DISABLE_TEX_STREAM_BUMP |
340             ENABLE_TEX_STREAM_COORD_SET |
341             TEX_STREAM_COORD_SET(3) |
342             ENABLE_TEX_STREAM_MAP_IDX | TEX_STREAM_MAP_IDX(3));
343
344   OUT_BATCH(_3DSTATE_MAP_COORD_TRANSFORM);
345   OUT_BATCH(DISABLE_TEX_TRANSFORM | TEXTURE_SET(0));
346   OUT_BATCH(_3DSTATE_MAP_COORD_TRANSFORM);
347   OUT_BATCH(DISABLE_TEX_TRANSFORM | TEXTURE_SET(1));
348   OUT_BATCH(_3DSTATE_MAP_COORD_TRANSFORM);
349   OUT_BATCH(DISABLE_TEX_TRANSFORM | TEXTURE_SET(2));
350   OUT_BATCH(_3DSTATE_MAP_COORD_TRANSFORM);
351   OUT_BATCH(DISABLE_TEX_TRANSFORM | TEXTURE_SET(3));
352
353   OUT_BATCH(_3DSTATE_VERTEX_TRANSFORM);
354   OUT_BATCH(DISABLE_VIEWPORT_TRANSFORM | DISABLE_PERSPECTIVE_DIVIDE);
355
356   OUT_BATCH(_3DSTATE_W_STATE_CMD);
357   OUT_BATCH(MAGIC_W_STATE_DWORD1);
358   OUT_BATCH(0x3f800000 /* 1.0 in IEEE float */ );
359
360
361   OUT_BATCH(_3DSTATE_COLOR_FACTOR_CMD);
362   OUT_BATCH(0x80808080);       /* .5 required in alpha for GL_DOT3_RGBA_EXT */
363
364   ADVANCE_BATCH();
365}
366
367
368#define emit( intel, state, size )			\
369   intel_batchbuffer_data(intel, state, size, false)
370
371static GLuint
372get_dirty(struct i830_hw_state *state)
373{
374   return state->active & ~state->emitted;
375}
376
377static GLuint
378get_state_size(struct i830_hw_state *state)
379{
380   GLuint dirty = get_dirty(state);
381   GLuint sz = 0;
382   GLuint i;
383
384   if (dirty & I830_UPLOAD_INVARIENT)
385      sz += 40 * sizeof(int);
386
387   if (dirty & I830_UPLOAD_RASTER_RULES)
388      sz += sizeof(state->RasterRules);
389
390   if (dirty & I830_UPLOAD_CTX)
391      sz += sizeof(state->Ctx);
392
393   if (dirty & I830_UPLOAD_BUFFERS)
394      sz += sizeof(state->Buffer);
395
396   if (dirty & I830_UPLOAD_STIPPLE)
397      sz += sizeof(state->Stipple);
398
399   for (i = 0; i < I830_TEX_UNITS; i++) {
400      if ((dirty & I830_UPLOAD_TEX(i)))
401         sz += sizeof(state->Tex[i]);
402
403      if (dirty & I830_UPLOAD_TEXBLEND(i))
404         sz += state->TexBlendWordsUsed[i] * 4;
405   }
406
407   return sz;
408}
409
410
411/* Push the state into the sarea and/or texture memory.
412 */
413static void
414i830_emit_state(struct intel_context *intel)
415{
416   struct i830_context *i830 = i830_context(&intel->ctx);
417   struct i830_hw_state *state = &i830->state;
418   int i, count;
419   GLuint dirty;
420   drm_intel_bo *aper_array[3 + I830_TEX_UNITS];
421   int aper_count;
422   GET_CURRENT_CONTEXT(ctx);
423   BATCH_LOCALS;
424
425   /* We don't hold the lock at this point, so want to make sure that
426    * there won't be a buffer wrap between the state emits and the primitive
427    * emit header.
428    *
429    * It might be better to talk about explicit places where
430    * scheduling is allowed, rather than assume that it is whenever a
431    * batchbuffer fills up.
432    */
433   intel_batchbuffer_require_space(intel,
434				   get_state_size(state) + INTEL_PRIM_EMIT_SIZE,
435				   false);
436   count = 0;
437 again:
438   aper_count = 0;
439   dirty = get_dirty(state);
440
441   aper_array[aper_count++] = intel->batch.bo;
442   if (dirty & I830_UPLOAD_BUFFERS) {
443      aper_array[aper_count++] = state->draw_region->buffer;
444      if (state->depth_region)
445         aper_array[aper_count++] = state->depth_region->buffer;
446   }
447
448   for (i = 0; i < I830_TEX_UNITS; i++)
449     if (dirty & I830_UPLOAD_TEX(i)) {
450	if (state->tex_buffer[i]) {
451	   aper_array[aper_count++] = state->tex_buffer[i];
452	}
453     }
454
455   if (dri_bufmgr_check_aperture_space(aper_array, aper_count)) {
456       if (count == 0) {
457	   count++;
458	   intel_batchbuffer_flush(intel);
459	   goto again;
460       } else {
461	   _mesa_error(ctx, GL_OUT_OF_MEMORY, "i830 emit state");
462	   assert(0);
463       }
464   }
465
466
467   /* Do this here as we may have flushed the batchbuffer above,
468    * causing more state to be dirty!
469    */
470   dirty = get_dirty(state);
471   state->emitted |= dirty;
472   assert(get_dirty(state) == 0);
473
474   if (dirty & I830_UPLOAD_INVARIENT) {
475      DBG("I830_UPLOAD_INVARIENT:\n");
476      i830_emit_invarient_state(intel);
477   }
478
479   if (dirty & I830_UPLOAD_RASTER_RULES) {
480      DBG("I830_UPLOAD_RASTER_RULES:\n");
481      emit(intel, state->RasterRules, sizeof(state->RasterRules));
482   }
483
484   if (dirty & I830_UPLOAD_CTX) {
485      DBG("I830_UPLOAD_CTX:\n");
486      emit(intel, state->Ctx, sizeof(state->Ctx));
487
488   }
489
490   if (dirty & I830_UPLOAD_BUFFERS) {
491      GLuint count = 15;
492
493      DBG("I830_UPLOAD_BUFFERS:\n");
494
495      if (state->depth_region)
496          count += 3;
497
498      BEGIN_BATCH(count);
499      OUT_BATCH(state->Buffer[I830_DESTREG_CBUFADDR0]);
500      OUT_BATCH(state->Buffer[I830_DESTREG_CBUFADDR1]);
501      OUT_RELOC(state->draw_region->buffer,
502		I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
503
504      if (state->depth_region) {
505         OUT_BATCH(state->Buffer[I830_DESTREG_DBUFADDR0]);
506         OUT_BATCH(state->Buffer[I830_DESTREG_DBUFADDR1]);
507         OUT_RELOC(state->depth_region->buffer,
508		   I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
509      }
510
511      OUT_BATCH(state->Buffer[I830_DESTREG_DV0]);
512      OUT_BATCH(state->Buffer[I830_DESTREG_DV1]);
513      OUT_BATCH(state->Buffer[I830_DESTREG_SENABLE]);
514      OUT_BATCH(state->Buffer[I830_DESTREG_SR0]);
515      OUT_BATCH(state->Buffer[I830_DESTREG_SR1]);
516      OUT_BATCH(state->Buffer[I830_DESTREG_SR2]);
517
518      assert(state->Buffer[I830_DESTREG_DRAWRECT0] != MI_NOOP);
519      OUT_BATCH(state->Buffer[I830_DESTREG_DRAWRECT0]);
520      OUT_BATCH(state->Buffer[I830_DESTREG_DRAWRECT1]);
521      OUT_BATCH(state->Buffer[I830_DESTREG_DRAWRECT2]);
522      OUT_BATCH(state->Buffer[I830_DESTREG_DRAWRECT3]);
523      OUT_BATCH(state->Buffer[I830_DESTREG_DRAWRECT4]);
524      OUT_BATCH(state->Buffer[I830_DESTREG_DRAWRECT5]);
525      ADVANCE_BATCH();
526   }
527
528   if (dirty & I830_UPLOAD_STIPPLE) {
529      DBG("I830_UPLOAD_STIPPLE:\n");
530      emit(intel, state->Stipple, sizeof(state->Stipple));
531   }
532
533   for (i = 0; i < I830_TEX_UNITS; i++) {
534      if ((dirty & I830_UPLOAD_TEX(i))) {
535         DBG("I830_UPLOAD_TEX(%d):\n", i);
536
537         BEGIN_BATCH(I830_TEX_SETUP_SIZE + 1);
538         OUT_BATCH(state->Tex[i][I830_TEXREG_TM0LI]);
539
540	 OUT_RELOC(state->tex_buffer[i],
541		   I915_GEM_DOMAIN_SAMPLER, 0,
542		   state->tex_offset[i]);
543
544         OUT_BATCH(state->Tex[i][I830_TEXREG_TM0S1]);
545         OUT_BATCH(state->Tex[i][I830_TEXREG_TM0S2]);
546         OUT_BATCH(state->Tex[i][I830_TEXREG_TM0S3]);
547         OUT_BATCH(state->Tex[i][I830_TEXREG_TM0S4]);
548         OUT_BATCH(state->Tex[i][I830_TEXREG_MCS]);
549         OUT_BATCH(state->Tex[i][I830_TEXREG_CUBE]);
550
551         ADVANCE_BATCH();
552      }
553
554      if (dirty & I830_UPLOAD_TEXBLEND(i)) {
555         DBG("I830_UPLOAD_TEXBLEND(%d): %d words\n", i,
556             state->TexBlendWordsUsed[i]);
557         emit(intel, state->TexBlend[i], state->TexBlendWordsUsed[i] * 4);
558      }
559   }
560
561   assert(get_dirty(state) == 0);
562}
563
564static void
565i830_destroy_context(struct intel_context *intel)
566{
567   GLuint i;
568   struct i830_context *i830 = i830_context(&intel->ctx);
569
570   intel_region_release(&i830->state.draw_region);
571   intel_region_release(&i830->state.depth_region);
572
573   for (i = 0; i < I830_TEX_UNITS; i++) {
574      if (i830->state.tex_buffer[i] != NULL) {
575	 drm_intel_bo_unreference(i830->state.tex_buffer[i]);
576	 i830->state.tex_buffer[i] = NULL;
577      }
578   }
579
580   _tnl_free_vertices(&intel->ctx);
581}
582
583static uint32_t i830_render_target_format_for_mesa_format[MESA_FORMAT_COUNT] =
584{
585   [MESA_FORMAT_ARGB8888] = DV_PF_8888,
586   [MESA_FORMAT_XRGB8888] = DV_PF_8888,
587   [MESA_FORMAT_RGB565] = DV_PF_565,
588   [MESA_FORMAT_ARGB1555] = DV_PF_1555,
589   [MESA_FORMAT_ARGB4444] = DV_PF_4444,
590};
591
592static bool
593i830_render_target_supported(gl_format format)
594{
595   if (format == MESA_FORMAT_S8_Z24 ||
596       format == MESA_FORMAT_X8_Z24 ||
597       format == MESA_FORMAT_Z16) {
598      return true;
599   }
600
601   return i830_render_target_format_for_mesa_format[format] != 0;
602}
603
604static void
605i830_set_draw_region(struct intel_context *intel,
606                     struct intel_region *color_regions[],
607                     struct intel_region *depth_region,
608		     GLuint num_regions)
609{
610   struct i830_context *i830 = i830_context(&intel->ctx);
611   struct gl_context *ctx = &intel->ctx;
612   struct gl_renderbuffer *rb = ctx->DrawBuffer->_ColorDrawBuffers[0];
613   struct intel_renderbuffer *irb = intel_renderbuffer(rb);
614   struct gl_renderbuffer *drb;
615   struct intel_renderbuffer *idrb = NULL;
616   GLuint value;
617   struct i830_hw_state *state = &i830->state;
618   uint32_t draw_x, draw_y;
619
620   if (state->draw_region != color_regions[0]) {
621      intel_region_release(&state->draw_region);
622      intel_region_reference(&state->draw_region, color_regions[0]);
623   }
624   if (state->depth_region != depth_region) {
625      intel_region_release(&state->depth_region);
626      intel_region_reference(&state->depth_region, depth_region);
627   }
628
629   /*
630    * Set stride/cpp values
631    */
632   i915_set_buf_info_for_region(&state->Buffer[I830_DESTREG_CBUFADDR0],
633				color_regions[0], BUF_3D_ID_COLOR_BACK);
634
635   i915_set_buf_info_for_region(&state->Buffer[I830_DESTREG_DBUFADDR0],
636				depth_region, BUF_3D_ID_DEPTH);
637
638   /*
639    * Compute/set I830_DESTREG_DV1 value
640    */
641   value = (DSTORG_HORT_BIAS(0x8) |     /* .5 */
642            DSTORG_VERT_BIAS(0x8) | DEPTH_IS_Z);    /* .5 */
643
644   if (irb != NULL) {
645      value |= i830_render_target_format_for_mesa_format[irb->Base.Format];
646   }
647
648   if (depth_region && depth_region->cpp == 4) {
649      value |= DEPTH_FRMT_24_FIXED_8_OTHER;
650   }
651   else {
652      value |= DEPTH_FRMT_16_FIXED;
653   }
654   state->Buffer[I830_DESTREG_DV1] = value;
655
656   drb = ctx->DrawBuffer->Attachment[BUFFER_DEPTH].Renderbuffer;
657   if (!drb)
658      drb = ctx->DrawBuffer->Attachment[BUFFER_STENCIL].Renderbuffer;
659
660   if (drb)
661      idrb = intel_renderbuffer(drb);
662
663   /* We set up the drawing rectangle to be offset into the color
664    * region's location in the miptree.  If it doesn't match with
665    * depth's offsets, we can't render to it.
666    *
667    * (Well, not actually true -- the hw grew a bit to let depth's
668    * offset get forced to 0,0.  We may want to use that if people are
669    * hitting that case.  Also, some configurations may be supportable
670    * by tweaking the start offset of the buffers around, which we
671    * can't do in general due to tiling)
672    */
673   FALLBACK(intel, I830_FALLBACK_DRAW_OFFSET,
674	    idrb && irb && (idrb->draw_x != irb->draw_x ||
675			    idrb->draw_y != irb->draw_y));
676
677   if (irb) {
678      draw_x = irb->draw_x;
679      draw_y = irb->draw_y;
680   } else if (idrb) {
681      draw_x = idrb->draw_x;
682      draw_y = idrb->draw_y;
683   } else {
684      draw_x = 0;
685      draw_y = 0;
686   }
687
688   state->Buffer[I830_DESTREG_DRAWRECT0] = _3DSTATE_DRAWRECT_INFO;
689   state->Buffer[I830_DESTREG_DRAWRECT1] = 0;
690   state->Buffer[I830_DESTREG_DRAWRECT2] = (draw_y << 16) | draw_x;
691   state->Buffer[I830_DESTREG_DRAWRECT3] =
692      ((ctx->DrawBuffer->Width + draw_x) & 0xffff) |
693      ((ctx->DrawBuffer->Height + draw_y) << 16);
694   state->Buffer[I830_DESTREG_DRAWRECT4] = (draw_y << 16) | draw_x;
695   state->Buffer[I830_DESTREG_DRAWRECT5] = MI_NOOP;
696
697   I830_STATECHANGE(i830, I830_UPLOAD_BUFFERS);
698}
699
700/* This isn't really handled at the moment.
701 */
702static void
703i830_new_batch(struct intel_context *intel)
704{
705   struct i830_context *i830 = i830_context(&intel->ctx);
706   i830->state.emitted = 0;
707}
708
709static void
710i830_assert_not_dirty( struct intel_context *intel )
711{
712   struct i830_context *i830 = i830_context(&intel->ctx);
713   assert(!get_dirty(&i830->state));
714   (void) i830;
715}
716
717static void
718i830_invalidate_state(struct intel_context *intel, GLuint new_state)
719{
720   struct gl_context *ctx = &intel->ctx;
721
722   _swsetup_InvalidateState(ctx, new_state);
723   _tnl_InvalidateState(ctx, new_state);
724   _tnl_invalidate_vertex_state(ctx, new_state);
725
726   if (new_state & _NEW_LIGHT)
727      i830_update_provoking_vertex(&intel->ctx);
728}
729
730void
731i830InitVtbl(struct i830_context *i830)
732{
733   i830->intel.vtbl.check_vertex_size = i830_check_vertex_size;
734   i830->intel.vtbl.destroy = i830_destroy_context;
735   i830->intel.vtbl.emit_state = i830_emit_state;
736   i830->intel.vtbl.new_batch = i830_new_batch;
737   i830->intel.vtbl.reduced_primitive_state = i830_reduced_primitive_state;
738   i830->intel.vtbl.set_draw_region = i830_set_draw_region;
739   i830->intel.vtbl.update_texture_state = i830UpdateTextureState;
740   i830->intel.vtbl.render_start = i830_render_start;
741   i830->intel.vtbl.render_prevalidate = i830_render_prevalidate;
742   i830->intel.vtbl.assert_not_dirty = i830_assert_not_dirty;
743   i830->intel.vtbl.finish_batch = intel_finish_vb;
744   i830->intel.vtbl.invalidate_state = i830_invalidate_state;
745   i830->intel.vtbl.render_target_supported = i830_render_target_supported;
746}
747