i830_vtbl.c revision b17aab5753a6d14c9e757bedb186963b2dae8823 
1/**************************************************************************
2 *
3 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 **************************************************************************/
27
28#include "i830_context.h"
29#include "i830_reg.h"
30#include "intel_batchbuffer.h"
31#include "intel_regions.h"
32#include "intel_tris.h"
33#include "intel_fbo.h"
34#include "tnl/t_context.h"
35#include "tnl/t_vertex.h"
36
37#define FILE_DEBUG_FLAG DEBUG_STATE
38
39static GLboolean i830_check_vertex_size(struct intel_context *intel,
40                                        GLuint expected);
41
42#define SZ_TO_HW(sz)  ((sz-2)&0x3)
43#define EMIT_SZ(sz)   (EMIT_1F + (sz) - 1)
44#define EMIT_ATTR( ATTR, STYLE, V0 )					\
45do {									\
46   intel->vertex_attrs[intel->vertex_attr_count].attrib = (ATTR);	\
47   intel->vertex_attrs[intel->vertex_attr_count].format = (STYLE);	\
48   intel->vertex_attr_count++;						\
49   v0 |= V0;								\
50} while (0)
51
52#define EMIT_PAD( N )							\
53do {									\
54   intel->vertex_attrs[intel->vertex_attr_count].attrib = 0;		\
55   intel->vertex_attrs[intel->vertex_attr_count].format = EMIT_PAD;	\
56   intel->vertex_attrs[intel->vertex_attr_count].offset = (N);		\
57   intel->vertex_attr_count++;						\
58} while (0)
59
60
61#define VRTX_TEX_SET_FMT(n, x)          ((x)<<((n)*2))
62#define TEXBIND_SET(n, x) 		((x)<<((n)*4))
63
64static void
65i830_render_prevalidate(struct intel_context *intel)
66{
67}
68
69static void
70i830_render_start(struct intel_context *intel)
71{
72   struct gl_context *ctx = &intel->ctx;
73   struct i830_context *i830 = i830_context(ctx);
74   TNLcontext *tnl = TNL_CONTEXT(ctx);
75   struct vertex_buffer *VB = &tnl->vb;
76   DECLARE_RENDERINPUTS(index_bitset);
77   GLuint v0 = _3DSTATE_VFT0_CMD;
78   GLuint v2 = _3DSTATE_VFT1_CMD;
79   GLuint mcsb1 = 0;
80
81   RENDERINPUTS_COPY(index_bitset, tnl->render_inputs_bitset);
82
83   /* Important:
84    */
85   VB->AttribPtr[VERT_ATTRIB_POS] = VB->NdcPtr;
86   intel->vertex_attr_count = 0;
87
88   /* EMIT_ATTR's must be in order as they tell t_vertex.c how to
89    * build up a hardware vertex.
90    */
91   if (RENDERINPUTS_TEST_RANGE(index_bitset, _TNL_FIRST_TEX, _TNL_LAST_TEX)) {
92      EMIT_ATTR(_TNL_ATTRIB_POS, EMIT_4F_VIEWPORT, VFT0_XYZW);
93      intel->coloroffset = 4;
94   }
95   else {
96      EMIT_ATTR(_TNL_ATTRIB_POS, EMIT_3F_VIEWPORT, VFT0_XYZ);
97      intel->coloroffset = 3;
98   }
99
100   if (RENDERINPUTS_TEST(index_bitset, _TNL_ATTRIB_POINTSIZE)) {
101      EMIT_ATTR(_TNL_ATTRIB_POINTSIZE, EMIT_1F, VFT0_POINT_WIDTH);
102   }
103
104   EMIT_ATTR(_TNL_ATTRIB_COLOR0, EMIT_4UB_4F_BGRA, VFT0_DIFFUSE);
105
106   intel->specoffset = 0;
107   if (RENDERINPUTS_TEST(index_bitset, _TNL_ATTRIB_COLOR1) ||
108       RENDERINPUTS_TEST(index_bitset, _TNL_ATTRIB_FOG)) {
109      if (RENDERINPUTS_TEST(index_bitset, _TNL_ATTRIB_COLOR1)) {
110         intel->specoffset = intel->coloroffset + 1;
111         EMIT_ATTR(_TNL_ATTRIB_COLOR1, EMIT_3UB_3F_BGR, VFT0_SPEC);
112      }
113      else
114         EMIT_PAD(3);
115
116      if (RENDERINPUTS_TEST(index_bitset, _TNL_ATTRIB_FOG))
117         EMIT_ATTR(_TNL_ATTRIB_FOG, EMIT_1UB_1F, VFT0_SPEC);
118      else
119         EMIT_PAD(1);
120   }
121
122   if (RENDERINPUTS_TEST_RANGE(index_bitset, _TNL_FIRST_TEX, _TNL_LAST_TEX)) {
123      int i, count = 0;
124
125      for (i = 0; i < I830_TEX_UNITS; i++) {
126         if (RENDERINPUTS_TEST(index_bitset, _TNL_ATTRIB_TEX(i))) {
127            GLuint sz = VB->AttribPtr[_TNL_ATTRIB_TEX0 + i]->size;
128            GLuint emit;
129            GLuint mcs = (i830->state.Tex[i][I830_TEXREG_MCS] &
130                          ~TEXCOORDTYPE_MASK);
131
132            switch (sz) {
133            case 1:
134            case 2:
135               emit = EMIT_2F;
136               sz = 2;
137               mcs |= TEXCOORDTYPE_CARTESIAN;
138               break;
139            case 3:
140               emit = EMIT_3F;
141               sz = 3;
142               mcs |= TEXCOORDTYPE_VECTOR;
143               break;
144            case 4:
145               emit = EMIT_3F_XYW;
146               sz = 3;
147               mcs |= TEXCOORDTYPE_HOMOGENEOUS;
148               break;
149            default:
150               continue;
151            };
152
153
154            EMIT_ATTR(_TNL_ATTRIB_TEX0 + i, emit, 0);
155            v2 |= VRTX_TEX_SET_FMT(count, SZ_TO_HW(sz));
156            mcsb1 |= (count + 8) << (i * 4);
157
158            if (mcs != i830->state.Tex[i][I830_TEXREG_MCS]) {
159               I830_STATECHANGE(i830, I830_UPLOAD_TEX(i));
160               i830->state.Tex[i][I830_TEXREG_MCS] = mcs;
161            }
162
163            count++;
164         }
165      }
166
167      v0 |= VFT0_TEX_COUNT(count);
168   }
169
170   /* Only need to change the vertex emit code if there has been a
171    * statechange to a new hardware vertex format:
172    */
173   if (v0 != i830->state.Ctx[I830_CTXREG_VF] ||
174       v2 != i830->state.Ctx[I830_CTXREG_VF2] ||
175       mcsb1 != i830->state.Ctx[I830_CTXREG_MCSB1] ||
176       !RENDERINPUTS_EQUAL(index_bitset, i830->last_index_bitset)) {
177      int k;
178
179      I830_STATECHANGE(i830, I830_UPLOAD_CTX);
180
181      /* Must do this *after* statechange, so as not to affect
182       * buffered vertices reliant on the old state:
183       */
184      intel->vertex_size =
185         _tnl_install_attrs(ctx,
186                            intel->vertex_attrs,
187                            intel->vertex_attr_count,
188                            intel->ViewportMatrix.m, 0);
189
190      intel->vertex_size >>= 2;
191
192      i830->state.Ctx[I830_CTXREG_VF] = v0;
193      i830->state.Ctx[I830_CTXREG_VF2] = v2;
194      i830->state.Ctx[I830_CTXREG_MCSB1] = mcsb1;
195      RENDERINPUTS_COPY(i830->last_index_bitset, index_bitset);
196
197      k = i830_check_vertex_size(intel, intel->vertex_size);
198      assert(k);
199   }
200}
201
202static void
203i830_reduced_primitive_state(struct intel_context *intel, GLenum rprim)
204{
205   struct i830_context *i830 = i830_context(&intel->ctx);
206   GLuint st1 = i830->state.Stipple[I830_STPREG_ST1];
207
208   st1 &= ~ST1_ENABLE;
209
210   switch (rprim) {
211   case GL_TRIANGLES:
212      if (intel->ctx.Polygon.StippleFlag && intel->hw_stipple)
213         st1 |= ST1_ENABLE;
214      break;
215   case GL_LINES:
216   case GL_POINTS:
217   default:
218      break;
219   }
220
221   i830->intel.reduced_primitive = rprim;
222
223   if (st1 != i830->state.Stipple[I830_STPREG_ST1]) {
224      INTEL_FIREVERTICES(intel);
225
226      I830_STATECHANGE(i830, I830_UPLOAD_STIPPLE);
227      i830->state.Stipple[I830_STPREG_ST1] = st1;
228   }
229}
230
231/* Pull apart the vertex format registers and figure out how large a
232 * vertex is supposed to be.
233 */
234static GLboolean
235i830_check_vertex_size(struct intel_context *intel, GLuint expected)
236{
237   struct i830_context *i830 = i830_context(&intel->ctx);
238   int vft0 = i830->state.Ctx[I830_CTXREG_VF];
239   int vft1 = i830->state.Ctx[I830_CTXREG_VF2];
240   int nrtex = (vft0 & VFT0_TEX_COUNT_MASK) >> VFT0_TEX_COUNT_SHIFT;
241   int i, sz = 0;
242
243   switch (vft0 & VFT0_XYZW_MASK) {
244   case VFT0_XY:
245      sz = 2;
246      break;
247   case VFT0_XYZ:
248      sz = 3;
249      break;
250   case VFT0_XYW:
251      sz = 3;
252      break;
253   case VFT0_XYZW:
254      sz = 4;
255      break;
256   default:
257      fprintf(stderr, "no xyzw specified\n");
258      return 0;
259   }
260
261   if (vft0 & VFT0_SPEC)
262      sz++;
263   if (vft0 & VFT0_DIFFUSE)
264      sz++;
265   if (vft0 & VFT0_DEPTH_OFFSET)
266      sz++;
267   if (vft0 & VFT0_POINT_WIDTH)
268      sz++;
269
270   for (i = 0; i < nrtex; i++) {
271      switch (vft1 & VFT1_TEX0_MASK) {
272      case TEXCOORDFMT_2D:
273         sz += 2;
274         break;
275      case TEXCOORDFMT_3D:
276         sz += 3;
277         break;
278      case TEXCOORDFMT_4D:
279         sz += 4;
280         break;
281      case TEXCOORDFMT_1D:
282         sz += 1;
283         break;
284      }
285      vft1 >>= VFT1_TEX1_SHIFT;
286   }
287
288   if (sz != expected)
289      fprintf(stderr, "vertex size mismatch %d/%d\n", sz, expected);
290
291   return sz == expected;
292}
293
294static void
295i830_emit_invarient_state(struct intel_context *intel)
296{
297   BATCH_LOCALS;
298
299   BEGIN_BATCH(29);
300
301   OUT_BATCH(_3DSTATE_DFLT_DIFFUSE_CMD);
302   OUT_BATCH(0);
303
304   OUT_BATCH(_3DSTATE_DFLT_SPEC_CMD);
305   OUT_BATCH(0);
306
307   OUT_BATCH(_3DSTATE_DFLT_Z_CMD);
308   OUT_BATCH(0);
309
310   OUT_BATCH(_3DSTATE_FOG_MODE_CMD);
311   OUT_BATCH(FOGFUNC_ENABLE |
312             FOG_LINEAR_CONST | FOGSRC_INDEX_Z | ENABLE_FOG_DENSITY);
313   OUT_BATCH(0);
314   OUT_BATCH(0);
315
316
317   OUT_BATCH(_3DSTATE_MAP_TEX_STREAM_CMD |
318             MAP_UNIT(0) |
319             DISABLE_TEX_STREAM_BUMP |
320             ENABLE_TEX_STREAM_COORD_SET |
321             TEX_STREAM_COORD_SET(0) |
322             ENABLE_TEX_STREAM_MAP_IDX | TEX_STREAM_MAP_IDX(0));
323   OUT_BATCH(_3DSTATE_MAP_TEX_STREAM_CMD |
324             MAP_UNIT(1) |
325             DISABLE_TEX_STREAM_BUMP |
326             ENABLE_TEX_STREAM_COORD_SET |
327             TEX_STREAM_COORD_SET(1) |
328             ENABLE_TEX_STREAM_MAP_IDX | TEX_STREAM_MAP_IDX(1));
329   OUT_BATCH(_3DSTATE_MAP_TEX_STREAM_CMD |
330             MAP_UNIT(2) |
331             DISABLE_TEX_STREAM_BUMP |
332             ENABLE_TEX_STREAM_COORD_SET |
333             TEX_STREAM_COORD_SET(2) |
334             ENABLE_TEX_STREAM_MAP_IDX | TEX_STREAM_MAP_IDX(2));
335   OUT_BATCH(_3DSTATE_MAP_TEX_STREAM_CMD |
336             MAP_UNIT(3) |
337             DISABLE_TEX_STREAM_BUMP |
338             ENABLE_TEX_STREAM_COORD_SET |
339             TEX_STREAM_COORD_SET(3) |
340             ENABLE_TEX_STREAM_MAP_IDX | TEX_STREAM_MAP_IDX(3));
341
342   OUT_BATCH(_3DSTATE_MAP_COORD_TRANSFORM);
343   OUT_BATCH(DISABLE_TEX_TRANSFORM | TEXTURE_SET(0));
344   OUT_BATCH(_3DSTATE_MAP_COORD_TRANSFORM);
345   OUT_BATCH(DISABLE_TEX_TRANSFORM | TEXTURE_SET(1));
346   OUT_BATCH(_3DSTATE_MAP_COORD_TRANSFORM);
347   OUT_BATCH(DISABLE_TEX_TRANSFORM | TEXTURE_SET(2));
348   OUT_BATCH(_3DSTATE_MAP_COORD_TRANSFORM);
349   OUT_BATCH(DISABLE_TEX_TRANSFORM | TEXTURE_SET(3));
350
351   OUT_BATCH(_3DSTATE_VERTEX_TRANSFORM);
352   OUT_BATCH(DISABLE_VIEWPORT_TRANSFORM | DISABLE_PERSPECTIVE_DIVIDE);
353
354   OUT_BATCH(_3DSTATE_W_STATE_CMD);
355   OUT_BATCH(MAGIC_W_STATE_DWORD1);
356   OUT_BATCH(0x3f800000 /* 1.0 in IEEE float */ );
357
358
359   OUT_BATCH(_3DSTATE_COLOR_FACTOR_CMD);
360   OUT_BATCH(0x80808080);       /* .5 required in alpha for GL_DOT3_RGBA_EXT */
361
362   ADVANCE_BATCH();
363}
364
365
366#define emit( intel, state, size )			\
367   intel_batchbuffer_data(intel, state, size, false)
368
369static GLuint
370get_dirty(struct i830_hw_state *state)
371{
372   return state->active & ~state->emitted;
373}
374
375static GLuint
376get_state_size(struct i830_hw_state *state)
377{
378   GLuint dirty = get_dirty(state);
379   GLuint sz = 0;
380   GLuint i;
381
382   if (dirty & I830_UPLOAD_INVARIENT)
383      sz += 40 * sizeof(int);
384
385   if (dirty & I830_UPLOAD_RASTER_RULES)
386      sz += sizeof(state->RasterRules);
387
388   if (dirty & I830_UPLOAD_CTX)
389      sz += sizeof(state->Ctx);
390
391   if (dirty & I830_UPLOAD_BUFFERS)
392      sz += sizeof(state->Buffer);
393
394   if (dirty & I830_UPLOAD_STIPPLE)
395      sz += sizeof(state->Stipple);
396
397   for (i = 0; i < I830_TEX_UNITS; i++) {
398      if ((dirty & I830_UPLOAD_TEX(i)))
399         sz += sizeof(state->Tex[i]);
400
401      if (dirty & I830_UPLOAD_TEXBLEND(i))
402         sz += state->TexBlendWordsUsed[i] * 4;
403   }
404
405   return sz;
406}
407
408
409/* Push the state into the sarea and/or texture memory.
410 */
411static void
412i830_emit_state(struct intel_context *intel)
413{
414   struct i830_context *i830 = i830_context(&intel->ctx);
415   struct i830_hw_state *state = &i830->state;
416   int i, count;
417   GLuint dirty;
418   drm_intel_bo *aper_array[3 + I830_TEX_UNITS];
419   int aper_count;
420   GET_CURRENT_CONTEXT(ctx);
421   BATCH_LOCALS;
422
423   /* We don't hold the lock at this point, so want to make sure that
424    * there won't be a buffer wrap between the state emits and the primitive
425    * emit header.
426    *
427    * It might be better to talk about explicit places where
428    * scheduling is allowed, rather than assume that it is whenever a
429    * batchbuffer fills up.
430    */
431   intel_batchbuffer_require_space(intel,
432				   get_state_size(state) + INTEL_PRIM_EMIT_SIZE,
433				   false);
434   count = 0;
435 again:
436   aper_count = 0;
437   dirty = get_dirty(state);
438
439   aper_array[aper_count++] = intel->batch.bo;
440   if (dirty & I830_UPLOAD_BUFFERS) {
441      aper_array[aper_count++] = state->draw_region->buffer;
442      if (state->depth_region)
443         aper_array[aper_count++] = state->depth_region->buffer;
444   }
445
446   for (i = 0; i < I830_TEX_UNITS; i++)
447     if (dirty & I830_UPLOAD_TEX(i)) {
448	if (state->tex_buffer[i]) {
449	   aper_array[aper_count++] = state->tex_buffer[i];
450	}
451     }
452
453   if (dri_bufmgr_check_aperture_space(aper_array, aper_count)) {
454       if (count == 0) {
455	   count++;
456	   intel_batchbuffer_flush(intel);
457	   goto again;
458       } else {
459	   _mesa_error(ctx, GL_OUT_OF_MEMORY, "i830 emit state");
460	   assert(0);
461       }
462   }
463
464
465   /* Do this here as we may have flushed the batchbuffer above,
466    * causing more state to be dirty!
467    */
468   dirty = get_dirty(state);
469   state->emitted |= dirty;
470   assert(get_dirty(state) == 0);
471
472   if (dirty & I830_UPLOAD_INVARIENT) {
473      DBG("I830_UPLOAD_INVARIENT:\n");
474      i830_emit_invarient_state(intel);
475   }
476
477   if (dirty & I830_UPLOAD_RASTER_RULES) {
478      DBG("I830_UPLOAD_RASTER_RULES:\n");
479      emit(intel, state->RasterRules, sizeof(state->RasterRules));
480   }
481
482   if (dirty & I830_UPLOAD_CTX) {
483      DBG("I830_UPLOAD_CTX:\n");
484      emit(intel, state->Ctx, sizeof(state->Ctx));
485
486   }
487
488   if (dirty & I830_UPLOAD_BUFFERS) {
489      GLuint count = 15;
490
491      DBG("I830_UPLOAD_BUFFERS:\n");
492
493      if (state->depth_region)
494          count += 3;
495
496      BEGIN_BATCH(count);
497      OUT_BATCH(state->Buffer[I830_DESTREG_CBUFADDR0]);
498      OUT_BATCH(state->Buffer[I830_DESTREG_CBUFADDR1]);
499      OUT_RELOC(state->draw_region->buffer,
500		I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
501
502      if (state->depth_region) {
503         OUT_BATCH(state->Buffer[I830_DESTREG_DBUFADDR0]);
504         OUT_BATCH(state->Buffer[I830_DESTREG_DBUFADDR1]);
505         OUT_RELOC(state->depth_region->buffer,
506		   I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
507      }
508
509      OUT_BATCH(state->Buffer[I830_DESTREG_DV0]);
510      OUT_BATCH(state->Buffer[I830_DESTREG_DV1]);
511      OUT_BATCH(state->Buffer[I830_DESTREG_SENABLE]);
512      OUT_BATCH(state->Buffer[I830_DESTREG_SR0]);
513      OUT_BATCH(state->Buffer[I830_DESTREG_SR1]);
514      OUT_BATCH(state->Buffer[I830_DESTREG_SR2]);
515
516      assert(state->Buffer[I830_DESTREG_DRAWRECT0] != MI_NOOP);
517      OUT_BATCH(state->Buffer[I830_DESTREG_DRAWRECT0]);
518      OUT_BATCH(state->Buffer[I830_DESTREG_DRAWRECT1]);
519      OUT_BATCH(state->Buffer[I830_DESTREG_DRAWRECT2]);
520      OUT_BATCH(state->Buffer[I830_DESTREG_DRAWRECT3]);
521      OUT_BATCH(state->Buffer[I830_DESTREG_DRAWRECT4]);
522      OUT_BATCH(state->Buffer[I830_DESTREG_DRAWRECT5]);
523      ADVANCE_BATCH();
524   }
525
526   if (dirty & I830_UPLOAD_STIPPLE) {
527      DBG("I830_UPLOAD_STIPPLE:\n");
528      emit(intel, state->Stipple, sizeof(state->Stipple));
529   }
530
531   for (i = 0; i < I830_TEX_UNITS; i++) {
532      if ((dirty & I830_UPLOAD_TEX(i))) {
533         DBG("I830_UPLOAD_TEX(%d):\n", i);
534
535         BEGIN_BATCH(I830_TEX_SETUP_SIZE + 1);
536         OUT_BATCH(state->Tex[i][I830_TEXREG_TM0LI]);
537
538	 OUT_RELOC(state->tex_buffer[i],
539		   I915_GEM_DOMAIN_SAMPLER, 0,
540		   state->tex_offset[i]);
541
542         OUT_BATCH(state->Tex[i][I830_TEXREG_TM0S1]);
543         OUT_BATCH(state->Tex[i][I830_TEXREG_TM0S2]);
544         OUT_BATCH(state->Tex[i][I830_TEXREG_TM0S3]);
545         OUT_BATCH(state->Tex[i][I830_TEXREG_TM0S4]);
546         OUT_BATCH(state->Tex[i][I830_TEXREG_MCS]);
547         OUT_BATCH(state->Tex[i][I830_TEXREG_CUBE]);
548
549         ADVANCE_BATCH();
550      }
551
552      if (dirty & I830_UPLOAD_TEXBLEND(i)) {
553         DBG("I830_UPLOAD_TEXBLEND(%d): %d words\n", i,
554             state->TexBlendWordsUsed[i]);
555         emit(intel, state->TexBlend[i], state->TexBlendWordsUsed[i] * 4);
556      }
557   }
558
559   assert(get_dirty(state) == 0);
560}
561
562static void
563i830_destroy_context(struct intel_context *intel)
564{
565   GLuint i;
566   struct i830_context *i830 = i830_context(&intel->ctx);
567
568   intel_region_release(&i830->state.draw_region);
569   intel_region_release(&i830->state.depth_region);
570
571   for (i = 0; i < I830_TEX_UNITS; i++) {
572      if (i830->state.tex_buffer[i] != NULL) {
573	 drm_intel_bo_unreference(i830->state.tex_buffer[i]);
574	 i830->state.tex_buffer[i] = NULL;
575      }
576   }
577
578   _tnl_free_vertices(&intel->ctx);
579}
580
581static uint32_t i830_render_target_format_for_mesa_format[MESA_FORMAT_COUNT] =
582{
583   [MESA_FORMAT_ARGB8888] = DV_PF_8888,
584   [MESA_FORMAT_XRGB8888] = DV_PF_8888,
585   [MESA_FORMAT_RGB565] = DV_PF_565,
586   [MESA_FORMAT_ARGB1555] = DV_PF_1555,
587   [MESA_FORMAT_ARGB4444] = DV_PF_4444,
588};
589
590static bool
591i830_render_target_supported(gl_format format)
592{
593   if (format == MESA_FORMAT_S8_Z24 ||
594       format == MESA_FORMAT_X8_Z24 ||
595       format == MESA_FORMAT_Z16) {
596      return true;
597   }
598
599   return i830_render_target_format_for_mesa_format[format] != 0;
600}
601
602static void
603i830_set_draw_region(struct intel_context *intel,
604                     struct intel_region *color_regions[],
605                     struct intel_region *depth_region,
606		     GLuint num_regions)
607{
608   struct i830_context *i830 = i830_context(&intel->ctx);
609   struct gl_context *ctx = &intel->ctx;
610   struct gl_renderbuffer *rb = ctx->DrawBuffer->_ColorDrawBuffers[0];
611   struct intel_renderbuffer *irb = intel_renderbuffer(rb);
612   struct gl_renderbuffer *drb;
613   struct intel_renderbuffer *idrb = NULL;
614   GLuint value;
615   struct i830_hw_state *state = &i830->state;
616   uint32_t draw_x, draw_y;
617
618   if (state->draw_region != color_regions[0]) {
619      intel_region_release(&state->draw_region);
620      intel_region_reference(&state->draw_region, color_regions[0]);
621   }
622   if (state->depth_region != depth_region) {
623      intel_region_release(&state->depth_region);
624      intel_region_reference(&state->depth_region, depth_region);
625   }
626
627   /*
628    * Set stride/cpp values
629    */
630   i915_set_buf_info_for_region(&state->Buffer[I830_DESTREG_CBUFADDR0],
631				color_regions[0], BUF_3D_ID_COLOR_BACK);
632
633   i915_set_buf_info_for_region(&state->Buffer[I830_DESTREG_DBUFADDR0],
634				depth_region, BUF_3D_ID_DEPTH);
635
636   /*
637    * Compute/set I830_DESTREG_DV1 value
638    */
639   value = (DSTORG_HORT_BIAS(0x8) |     /* .5 */
640            DSTORG_VERT_BIAS(0x8) | DEPTH_IS_Z);    /* .5 */
641
642   if (irb != NULL) {
643      value |= i830_render_target_format_for_mesa_format[irb->Base.Format];
644   }
645
646   if (depth_region && depth_region->cpp == 4) {
647      value |= DEPTH_FRMT_24_FIXED_8_OTHER;
648   }
649   else {
650      value |= DEPTH_FRMT_16_FIXED;
651   }
652   state->Buffer[I830_DESTREG_DV1] = value;
653
654   drb = ctx->DrawBuffer->Attachment[BUFFER_DEPTH].Renderbuffer;
655   if (!drb)
656      drb = ctx->DrawBuffer->Attachment[BUFFER_STENCIL].Renderbuffer;
657
658   if (drb)
659      idrb = intel_renderbuffer(drb);
660
661   /* We set up the drawing rectangle to be offset into the color
662    * region's location in the miptree.  If it doesn't match with
663    * depth's offsets, we can't render to it.
664    *
665    * (Well, not actually true -- the hw grew a bit to let depth's
666    * offset get forced to 0,0.  We may want to use that if people are
667    * hitting that case.  Also, some configurations may be supportable
668    * by tweaking the start offset of the buffers around, which we
669    * can't do in general due to tiling)
670    */
671   FALLBACK(intel, I830_FALLBACK_DRAW_OFFSET,
672	    idrb && irb && (idrb->draw_x != irb->draw_x ||
673			    idrb->draw_y != irb->draw_y));
674
675   if (irb) {
676      draw_x = irb->draw_x;
677      draw_y = irb->draw_y;
678   } else if (idrb) {
679      draw_x = idrb->draw_x;
680      draw_y = idrb->draw_y;
681   } else {
682      draw_x = 0;
683      draw_y = 0;
684   }
685
686   state->Buffer[I830_DESTREG_DRAWRECT0] = _3DSTATE_DRAWRECT_INFO;
687   state->Buffer[I830_DESTREG_DRAWRECT1] = 0;
688   state->Buffer[I830_DESTREG_DRAWRECT2] = (draw_y << 16) | draw_x;
689   state->Buffer[I830_DESTREG_DRAWRECT3] =
690      ((ctx->DrawBuffer->Width + draw_x) & 0xffff) |
691      ((ctx->DrawBuffer->Height + draw_y) << 16);
692   state->Buffer[I830_DESTREG_DRAWRECT4] = (draw_y << 16) | draw_x;
693   state->Buffer[I830_DESTREG_DRAWRECT5] = MI_NOOP;
694
695   I830_STATECHANGE(i830, I830_UPLOAD_BUFFERS);
696}
697
698/* This isn't really handled at the moment.
699 */
700static void
701i830_new_batch(struct intel_context *intel)
702{
703   struct i830_context *i830 = i830_context(&intel->ctx);
704   i830->state.emitted = 0;
705}
706
707static void
708i830_assert_not_dirty( struct intel_context *intel )
709{
710   struct i830_context *i830 = i830_context(&intel->ctx);
711   assert(!get_dirty(&i830->state));
712   (void) i830;
713}
714
715static void
716i830_invalidate_state(struct intel_context *intel, GLuint new_state)
717{
718   if (new_state & _NEW_LIGHT)
719      i830_update_provoking_vertex(&intel->ctx);
720}
721
722void
723i830InitVtbl(struct i830_context *i830)
724{
725   i830->intel.vtbl.check_vertex_size = i830_check_vertex_size;
726   i830->intel.vtbl.destroy = i830_destroy_context;
727   i830->intel.vtbl.emit_state = i830_emit_state;
728   i830->intel.vtbl.new_batch = i830_new_batch;
729   i830->intel.vtbl.reduced_primitive_state = i830_reduced_primitive_state;
730   i830->intel.vtbl.set_draw_region = i830_set_draw_region;
731   i830->intel.vtbl.update_texture_state = i830UpdateTextureState;
732   i830->intel.vtbl.render_start = i830_render_start;
733   i830->intel.vtbl.render_prevalidate = i830_render_prevalidate;
734   i830->intel.vtbl.assert_not_dirty = i830_assert_not_dirty;
735   i830->intel.vtbl.finish_batch = intel_finish_vb;
736   i830->intel.vtbl.invalidate_state = i830_invalidate_state;
737   i830->intel.vtbl.render_target_supported = i830_render_target_supported;
738}
739