i915_vtbl.c revision b87406e55f029d29594ae76a4b39a4fe1007fe4f
1/************************************************************************** 2 * 3 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 4 * All Rights Reserved. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the 8 * "Software"), to deal in the Software without restriction, including 9 * without limitation the rights to use, copy, modify, merge, publish, 10 * distribute, sub license, and/or sell copies of the Software, and to 11 * permit persons to whom the Software is furnished to do so, subject to 12 * the following conditions: 13 * 14 * The above copyright notice and this permission notice (including the 15 * next paragraph) shall be included in all copies or substantial portions 16 * of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 25 * 26 **************************************************************************/ 27 28 29 30#include "main/glheader.h" 31#include "main/mtypes.h" 32#include "main/imports.h" 33#include "main/macros.h" 34#include "main/colormac.h" 35 36#include "tnl/t_context.h" 37#include "tnl/t_vertex.h" 38 39#include "intel_batchbuffer.h" 40#include "intel_regions.h" 41#include "intel_tris.h" 42#include "intel_fbo.h" 43 44#include "i915_reg.h" 45#include "i915_context.h" 46 47static void 48i915_render_prevalidate(struct intel_context *intel) 49{ 50 struct i915_context *i915 = i915_context(&intel->ctx); 51 52 i915ValidateFragmentProgram(i915); 53} 54 55static void 56i915_render_start(struct intel_context *intel) 57{ 58 intel_prepare_render(intel); 59} 60 61 62static void 63i915_reduced_primitive_state(struct intel_context *intel, GLenum rprim) 64{ 65 struct i915_context *i915 = i915_context(&intel->ctx); 66 GLuint st1 = i915->state.Stipple[I915_STPREG_ST1]; 67 68 st1 &= ~ST1_ENABLE; 69 70 switch (rprim) { 71 case GL_QUADS: /* from RASTERIZE(GL_QUADS) in t_dd_tritemp.h */ 72 case GL_TRIANGLES: 73 if (intel->ctx.Polygon.StippleFlag && intel->hw_stipple) 74 st1 |= ST1_ENABLE; 75 break; 76 case GL_LINES: 77 case GL_POINTS: 78 default: 79 break; 80 } 81 82 i915->intel.reduced_primitive = rprim; 83 84 if (st1 != i915->state.Stipple[I915_STPREG_ST1]) { 85 INTEL_FIREVERTICES(intel); 86 87 I915_STATECHANGE(i915, I915_UPLOAD_STIPPLE); 88 i915->state.Stipple[I915_STPREG_ST1] = st1; 89 } 90} 91 92 93/* Pull apart the vertex format registers and figure out how large a 94 * vertex is supposed to be. 95 */ 96static GLboolean 97i915_check_vertex_size(struct intel_context *intel, GLuint expected) 98{ 99 struct i915_context *i915 = i915_context(&intel->ctx); 100 int lis2 = i915->state.Ctx[I915_CTXREG_LIS2]; 101 int lis4 = i915->state.Ctx[I915_CTXREG_LIS4]; 102 int i, sz = 0; 103 104 switch (lis4 & S4_VFMT_XYZW_MASK) { 105 case S4_VFMT_XY: 106 sz = 2; 107 break; 108 case S4_VFMT_XYZ: 109 sz = 3; 110 break; 111 case S4_VFMT_XYW: 112 sz = 3; 113 break; 114 case S4_VFMT_XYZW: 115 sz = 4; 116 break; 117 default: 118 fprintf(stderr, "no xyzw specified\n"); 119 return 0; 120 } 121 122 if (lis4 & S4_VFMT_SPEC_FOG) 123 sz++; 124 if (lis4 & S4_VFMT_COLOR) 125 sz++; 126 if (lis4 & S4_VFMT_DEPTH_OFFSET) 127 sz++; 128 if (lis4 & S4_VFMT_POINT_WIDTH) 129 sz++; 130 if (lis4 & S4_VFMT_FOG_PARAM) 131 sz++; 132 133 for (i = 0; i < 8; i++) { 134 switch (lis2 & S2_TEXCOORD_FMT0_MASK) { 135 case TEXCOORDFMT_2D: 136 sz += 2; 137 break; 138 case TEXCOORDFMT_3D: 139 sz += 3; 140 break; 141 case TEXCOORDFMT_4D: 142 sz += 4; 143 break; 144 case TEXCOORDFMT_1D: 145 sz += 1; 146 break; 147 case TEXCOORDFMT_2D_16: 148 sz += 1; 149 break; 150 case TEXCOORDFMT_4D_16: 151 sz += 2; 152 break; 153 case TEXCOORDFMT_NOT_PRESENT: 154 break; 155 default: 156 fprintf(stderr, "bad texcoord fmt %d\n", i); 157 return GL_FALSE; 158 } 159 lis2 >>= S2_TEXCOORD_FMT1_SHIFT; 160 } 161 162 if (sz != expected) 163 fprintf(stderr, "vertex size mismatch %d/%d\n", sz, expected); 164 165 return sz == expected; 166} 167 168 169static void 170i915_emit_invarient_state(struct intel_context *intel) 171{ 172 BATCH_LOCALS; 173 174 BEGIN_BATCH(17); 175 176 OUT_BATCH(_3DSTATE_AA_CMD | 177 AA_LINE_ECAAR_WIDTH_ENABLE | 178 AA_LINE_ECAAR_WIDTH_1_0 | 179 AA_LINE_REGION_WIDTH_ENABLE | AA_LINE_REGION_WIDTH_1_0); 180 181 OUT_BATCH(_3DSTATE_DFLT_DIFFUSE_CMD); 182 OUT_BATCH(0); 183 184 OUT_BATCH(_3DSTATE_DFLT_SPEC_CMD); 185 OUT_BATCH(0); 186 187 OUT_BATCH(_3DSTATE_DFLT_Z_CMD); 188 OUT_BATCH(0); 189 190 /* Don't support texture crossbar yet */ 191 OUT_BATCH(_3DSTATE_COORD_SET_BINDINGS | 192 CSB_TCB(0, 0) | 193 CSB_TCB(1, 1) | 194 CSB_TCB(2, 2) | 195 CSB_TCB(3, 3) | 196 CSB_TCB(4, 4) | CSB_TCB(5, 5) | CSB_TCB(6, 6) | CSB_TCB(7, 7)); 197 198 /* Need to initialize this to zero. 199 */ 200 OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_1 | I1_LOAD_S(3) | (0)); 201 OUT_BATCH(0); 202 203 /* XXX: Use this */ 204 OUT_BATCH(_3DSTATE_SCISSOR_ENABLE_CMD | DISABLE_SCISSOR_RECT); 205 206 OUT_BATCH(_3DSTATE_SCISSOR_RECT_0_CMD); 207 OUT_BATCH(0); 208 OUT_BATCH(0); 209 210 OUT_BATCH(_3DSTATE_DEPTH_SUBRECT_DISABLE); 211 212 OUT_BATCH(_3DSTATE_LOAD_INDIRECT | 0); /* disable indirect state */ 213 OUT_BATCH(0); 214 215 ADVANCE_BATCH(); 216} 217 218 219#define emit(intel, state, size ) \ 220 intel_batchbuffer_data(intel->batch, state, size) 221 222static GLuint 223get_dirty(struct i915_hw_state *state) 224{ 225 GLuint dirty; 226 227 /* Workaround the multitex hang - if one texture unit state is 228 * modified, emit all texture units. 229 */ 230 dirty = state->active & ~state->emitted; 231 if (dirty & I915_UPLOAD_TEX_ALL) 232 state->emitted &= ~I915_UPLOAD_TEX_ALL; 233 dirty = state->active & ~state->emitted; 234 return dirty; 235} 236 237 238static GLuint 239get_state_size(struct i915_hw_state *state) 240{ 241 GLuint dirty = get_dirty(state); 242 GLuint i; 243 GLuint sz = 0; 244 245 if (dirty & I915_UPLOAD_INVARIENT) 246 sz += 30 * 4; 247 248 if (dirty & I915_UPLOAD_RASTER_RULES) 249 sz += sizeof(state->RasterRules); 250 251 if (dirty & I915_UPLOAD_CTX) 252 sz += sizeof(state->Ctx); 253 254 if (dirty & I915_UPLOAD_BUFFERS) 255 sz += sizeof(state->Buffer); 256 257 if (dirty & I915_UPLOAD_STIPPLE) 258 sz += sizeof(state->Stipple); 259 260 if (dirty & I915_UPLOAD_FOG) 261 sz += sizeof(state->Fog); 262 263 if (dirty & I915_UPLOAD_TEX_ALL) { 264 int nr = 0; 265 for (i = 0; i < I915_TEX_UNITS; i++) 266 if (dirty & I915_UPLOAD_TEX(i)) 267 nr++; 268 269 sz += (2 + nr * 3) * sizeof(GLuint) * 2; 270 } 271 272 if (dirty & I915_UPLOAD_CONSTANTS) 273 sz += state->ConstantSize * sizeof(GLuint); 274 275 if (dirty & I915_UPLOAD_PROGRAM) 276 sz += state->ProgramSize * sizeof(GLuint); 277 278 return sz; 279} 280 281/* Push the state into the sarea and/or texture memory. 282 */ 283static void 284i915_emit_state(struct intel_context *intel) 285{ 286 struct i915_context *i915 = i915_context(&intel->ctx); 287 struct i915_hw_state *state = &i915->state; 288 int i, count, aper_count; 289 GLuint dirty; 290 dri_bo *aper_array[3 + I915_TEX_UNITS]; 291 GET_CURRENT_CONTEXT(ctx); 292 BATCH_LOCALS; 293 294 /* We don't hold the lock at this point, so want to make sure that 295 * there won't be a buffer wrap between the state emits and the primitive 296 * emit header. 297 * 298 * It might be better to talk about explicit places where 299 * scheduling is allowed, rather than assume that it is whenever a 300 * batchbuffer fills up. 301 */ 302 intel_batchbuffer_require_space(intel->batch, 303 get_state_size(state) + INTEL_PRIM_EMIT_SIZE); 304 count = 0; 305 again: 306 aper_count = 0; 307 dirty = get_dirty(state); 308 309 aper_array[aper_count++] = intel->batch->buf; 310 if (dirty & I915_UPLOAD_BUFFERS) { 311 aper_array[aper_count++] = state->draw_region->buffer; 312 if (state->depth_region) 313 aper_array[aper_count++] = state->depth_region->buffer; 314 } 315 316 if (dirty & I915_UPLOAD_TEX_ALL) { 317 for (i = 0; i < I915_TEX_UNITS; i++) { 318 if (dirty & I915_UPLOAD_TEX(i)) { 319 if (state->tex_buffer[i]) { 320 aper_array[aper_count++] = state->tex_buffer[i]; 321 } 322 } 323 } 324 } 325 326 if (dri_bufmgr_check_aperture_space(aper_array, aper_count)) { 327 if (count == 0) { 328 count++; 329 intel_batchbuffer_flush(intel->batch); 330 goto again; 331 } else { 332 _mesa_error(ctx, GL_OUT_OF_MEMORY, "i915 emit state"); 333 assert(0); 334 } 335 } 336 337 /* work out list of buffers to emit */ 338 339 /* Do this here as we may have flushed the batchbuffer above, 340 * causing more state to be dirty! 341 */ 342 dirty = get_dirty(state); 343 state->emitted |= dirty; 344 assert(get_dirty(state) == 0); 345 346 if (INTEL_DEBUG & DEBUG_STATE) 347 fprintf(stderr, "%s dirty: %x\n", __FUNCTION__, dirty); 348 349 if (dirty & I915_UPLOAD_INVARIENT) { 350 if (INTEL_DEBUG & DEBUG_STATE) 351 fprintf(stderr, "I915_UPLOAD_INVARIENT:\n"); 352 i915_emit_invarient_state(intel); 353 } 354 355 if (dirty & I915_UPLOAD_RASTER_RULES) { 356 if (INTEL_DEBUG & DEBUG_STATE) 357 fprintf(stderr, "I915_UPLOAD_RASTER_RULES:\n"); 358 emit(intel, state->RasterRules, sizeof(state->RasterRules)); 359 } 360 361 if (dirty & I915_UPLOAD_CTX) { 362 if (INTEL_DEBUG & DEBUG_STATE) 363 fprintf(stderr, "I915_UPLOAD_CTX:\n"); 364 365 emit(intel, state->Ctx, sizeof(state->Ctx)); 366 } 367 368 if (dirty & I915_UPLOAD_BUFFERS) { 369 GLuint count = 15; 370 371 if (INTEL_DEBUG & DEBUG_STATE) 372 fprintf(stderr, "I915_UPLOAD_BUFFERS:\n"); 373 374 if (state->depth_region) 375 count += 3; 376 377 BEGIN_BATCH(count); 378 OUT_BATCH(state->Buffer[I915_DESTREG_CBUFADDR0]); 379 OUT_BATCH(state->Buffer[I915_DESTREG_CBUFADDR1]); 380 OUT_RELOC(state->draw_region->buffer, 381 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0); 382 383 if (state->depth_region) { 384 OUT_BATCH(state->Buffer[I915_DESTREG_DBUFADDR0]); 385 OUT_BATCH(state->Buffer[I915_DESTREG_DBUFADDR1]); 386 OUT_RELOC(state->depth_region->buffer, 387 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0); 388 } 389 390 OUT_BATCH(state->Buffer[I915_DESTREG_DV0]); 391 OUT_BATCH(state->Buffer[I915_DESTREG_DV1]); 392 OUT_BATCH(state->Buffer[I915_DESTREG_SENABLE]); 393 OUT_BATCH(state->Buffer[I915_DESTREG_SR0]); 394 OUT_BATCH(state->Buffer[I915_DESTREG_SR1]); 395 OUT_BATCH(state->Buffer[I915_DESTREG_SR2]); 396 397 assert(state->Buffer[I915_DESTREG_DRAWRECT0] != MI_NOOP); 398 OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT0]); 399 OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT1]); 400 OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT2]); 401 OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT3]); 402 OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT4]); 403 OUT_BATCH(state->Buffer[I915_DESTREG_DRAWRECT5]); 404 405 ADVANCE_BATCH(); 406 } 407 408 if (dirty & I915_UPLOAD_STIPPLE) { 409 if (INTEL_DEBUG & DEBUG_STATE) 410 fprintf(stderr, "I915_UPLOAD_STIPPLE:\n"); 411 emit(intel, state->Stipple, sizeof(state->Stipple)); 412 } 413 414 if (dirty & I915_UPLOAD_FOG) { 415 if (INTEL_DEBUG & DEBUG_STATE) 416 fprintf(stderr, "I915_UPLOAD_FOG:\n"); 417 emit(intel, state->Fog, sizeof(state->Fog)); 418 } 419 420 /* Combine all the dirty texture state into a single command to 421 * avoid lockups on I915 hardware. 422 */ 423 if (dirty & I915_UPLOAD_TEX_ALL) { 424 int nr = 0; 425 426 for (i = 0; i < I915_TEX_UNITS; i++) 427 if (dirty & I915_UPLOAD_TEX(i)) 428 nr++; 429 430 BEGIN_BATCH(2 + nr * 3); 431 OUT_BATCH(_3DSTATE_MAP_STATE | (3 * nr)); 432 OUT_BATCH((dirty & I915_UPLOAD_TEX_ALL) >> I915_UPLOAD_TEX_0_SHIFT); 433 for (i = 0; i < I915_TEX_UNITS; i++) 434 if (dirty & I915_UPLOAD_TEX(i)) { 435 436 if (state->tex_buffer[i]) { 437 OUT_RELOC(state->tex_buffer[i], 438 I915_GEM_DOMAIN_SAMPLER, 0, 439 state->tex_offset[i]); 440 } 441 else { 442 OUT_BATCH(state->tex_offset[i]); 443 } 444 445 OUT_BATCH(state->Tex[i][I915_TEXREG_MS3]); 446 OUT_BATCH(state->Tex[i][I915_TEXREG_MS4]); 447 } 448 ADVANCE_BATCH(); 449 450 BEGIN_BATCH(2 + nr * 3); 451 OUT_BATCH(_3DSTATE_SAMPLER_STATE | (3 * nr)); 452 OUT_BATCH((dirty & I915_UPLOAD_TEX_ALL) >> I915_UPLOAD_TEX_0_SHIFT); 453 for (i = 0; i < I915_TEX_UNITS; i++) 454 if (dirty & I915_UPLOAD_TEX(i)) { 455 OUT_BATCH(state->Tex[i][I915_TEXREG_SS2]); 456 OUT_BATCH(state->Tex[i][I915_TEXREG_SS3]); 457 OUT_BATCH(state->Tex[i][I915_TEXREG_SS4]); 458 } 459 ADVANCE_BATCH(); 460 } 461 462 if (dirty & I915_UPLOAD_CONSTANTS) { 463 if (INTEL_DEBUG & DEBUG_STATE) 464 fprintf(stderr, "I915_UPLOAD_CONSTANTS:\n"); 465 emit(intel, state->Constant, state->ConstantSize * sizeof(GLuint)); 466 } 467 468 if (dirty & I915_UPLOAD_PROGRAM) { 469 if (state->ProgramSize) { 470 if (INTEL_DEBUG & DEBUG_STATE) 471 fprintf(stderr, "I915_UPLOAD_PROGRAM:\n"); 472 473 assert((state->Program[0] & 0x1ff) + 2 == state->ProgramSize); 474 475 emit(intel, state->Program, state->ProgramSize * sizeof(GLuint)); 476 if (INTEL_DEBUG & DEBUG_STATE) 477 i915_disassemble_program(state->Program, state->ProgramSize); 478 } 479 } 480 481 intel->batch->dirty_state &= ~dirty; 482 assert(get_dirty(state) == 0); 483 assert((intel->batch->dirty_state & (1<<1)) == 0); 484} 485 486static void 487i915_destroy_context(struct intel_context *intel) 488{ 489 GLuint i; 490 struct i915_context *i915 = i915_context(&intel->ctx); 491 492 intel_region_release(&i915->state.draw_region); 493 intel_region_release(&i915->state.depth_region); 494 495 for (i = 0; i < I915_TEX_UNITS; i++) { 496 if (i915->state.tex_buffer[i] != NULL) { 497 dri_bo_unreference(i915->state.tex_buffer[i]); 498 i915->state.tex_buffer[i] = NULL; 499 } 500 } 501 502 _tnl_free_vertices(&intel->ctx); 503} 504 505void 506i915_set_buf_info_for_region(uint32_t *state, struct intel_region *region, 507 uint32_t buffer_id) 508{ 509 state[0] = _3DSTATE_BUF_INFO_CMD; 510 state[1] = buffer_id; 511 512 if (region != NULL) { 513 state[1] |= BUF_3D_PITCH(region->pitch * region->cpp); 514 515 if (region->tiling != I915_TILING_NONE) { 516 state[1] |= BUF_3D_TILED_SURFACE; 517 if (region->tiling == I915_TILING_Y) 518 state[1] |= BUF_3D_TILE_WALK_Y; 519 } 520 } 521} 522 523static void 524i915_set_draw_region(struct intel_context *intel, 525 struct intel_region *color_regions[], 526 struct intel_region *depth_region, 527 GLuint num_regions) 528{ 529 struct i915_context *i915 = i915_context(&intel->ctx); 530 GLcontext *ctx = &intel->ctx; 531 struct gl_renderbuffer *rb = ctx->DrawBuffer->_ColorDrawBuffers[0]; 532 struct intel_renderbuffer *irb = intel_renderbuffer(rb); 533 GLuint value; 534 struct i915_hw_state *state = &i915->state; 535 uint32_t draw_x, draw_y; 536 537 if (state->draw_region != color_regions[0]) { 538 intel_region_release(&state->draw_region); 539 intel_region_reference(&state->draw_region, color_regions[0]); 540 } 541 if (state->depth_region != depth_region) { 542 intel_region_release(&state->depth_region); 543 intel_region_reference(&state->depth_region, depth_region); 544 } 545 546 /* 547 * Set stride/cpp values 548 */ 549 i915_set_buf_info_for_region(&state->Buffer[I915_DESTREG_CBUFADDR0], 550 color_regions[0], BUF_3D_ID_COLOR_BACK); 551 552 i915_set_buf_info_for_region(&state->Buffer[I915_DESTREG_DBUFADDR0], 553 depth_region, BUF_3D_ID_DEPTH); 554 555 /* 556 * Compute/set I915_DESTREG_DV1 value 557 */ 558 value = (DSTORG_HORT_BIAS(0x8) | /* .5 */ 559 DSTORG_VERT_BIAS(0x8) | /* .5 */ 560 LOD_PRECLAMP_OGL | TEX_DEFAULT_COLOR_OGL); 561 if (irb != NULL) { 562 switch (irb->Base.Format) { 563 case MESA_FORMAT_ARGB8888: 564 case MESA_FORMAT_XRGB8888: 565 value |= DV_PF_8888; 566 break; 567 case MESA_FORMAT_RGB565: 568 value |= DV_PF_565 | DITHER_FULL_ALWAYS; 569 break; 570 case MESA_FORMAT_ARGB1555: 571 value |= DV_PF_1555 | DITHER_FULL_ALWAYS; 572 break; 573 case MESA_FORMAT_ARGB4444: 574 value |= DV_PF_4444 | DITHER_FULL_ALWAYS; 575 break; 576 default: 577 _mesa_problem(ctx, "Bad renderbuffer format: %d\n", 578 irb->Base.Format); 579 } 580 } 581 582 /* This isn't quite safe, thus being hidden behind an option. When changing 583 * the value of this bit, the pipeline needs to be MI_FLUSHed. And it 584 * can only be set when a depth buffer is already defined. 585 */ 586 if (intel->is_945 && intel->use_early_z && 587 depth_region->tiling != I915_TILING_NONE) 588 value |= CLASSIC_EARLY_DEPTH; 589 590 if (depth_region && depth_region->cpp == 4) { 591 value |= DEPTH_FRMT_24_FIXED_8_OTHER; 592 } 593 else { 594 value |= DEPTH_FRMT_16_FIXED; 595 } 596 state->Buffer[I915_DESTREG_DV1] = value; 597 598 /* We set up the drawing rectangle to be offset into the color 599 * region's location in the miptree. If it doesn't match with 600 * depth's offsets, we can't render to it. 601 * 602 * (Well, not actually true -- the hw grew a bit to let depth's 603 * offset get forced to 0,0. We may want to use that if people are 604 * hitting that case. Also, some configurations may be supportable 605 * by tweaking the start offset of the buffers around, which we 606 * can't do in general due to tiling) 607 */ 608 FALLBACK(intel, I915_FALLBACK_DRAW_OFFSET, 609 (depth_region && color_regions[0]) && 610 (depth_region->draw_x != color_regions[0]->draw_x || 611 depth_region->draw_y != color_regions[0]->draw_y)); 612 613 if (color_regions[0]) { 614 draw_x = color_regions[0]->draw_x; 615 draw_y = color_regions[0]->draw_y; 616 } else if (depth_region) { 617 draw_x = depth_region->draw_x; 618 draw_y = depth_region->draw_y; 619 } else { 620 draw_x = 0; 621 draw_y = 0; 622 } 623 624 /* When changing drawing rectangle offset, an MI_FLUSH is first required. */ 625 state->Buffer[I915_DESTREG_DRAWRECT0] = MI_FLUSH; 626 state->Buffer[I915_DESTREG_DRAWRECT1] = _3DSTATE_DRAWRECT_INFO; 627 state->Buffer[I915_DESTREG_DRAWRECT2] = 0; 628 state->Buffer[I915_DESTREG_DRAWRECT3] = (draw_y << 16) | draw_x; 629 state->Buffer[I915_DESTREG_DRAWRECT4] = 630 ((ctx->DrawBuffer->Width + draw_x) & 0xffff) | 631 ((ctx->DrawBuffer->Height + draw_y) << 16); 632 state->Buffer[I915_DESTREG_DRAWRECT5] = (draw_y << 16) | draw_x; 633 634 I915_STATECHANGE(i915, I915_UPLOAD_BUFFERS); 635} 636 637 638 639static void 640i915_new_batch(struct intel_context *intel) 641{ 642 struct i915_context *i915 = i915_context(&intel->ctx); 643 644 /* Mark all state as needing to be emitted when starting a new batchbuffer. 645 * Using hardware contexts would be an alternative, but they have some 646 * difficulties associated with them (physical address requirements). 647 */ 648 i915->state.emitted = 0; 649} 650 651static void 652i915_assert_not_dirty( struct intel_context *intel ) 653{ 654 struct i915_context *i915 = i915_context(&intel->ctx); 655 GLuint dirty = get_dirty(&i915->state); 656 assert(!dirty); 657} 658 659void 660i915InitVtbl(struct i915_context *i915) 661{ 662 i915->intel.vtbl.check_vertex_size = i915_check_vertex_size; 663 i915->intel.vtbl.destroy = i915_destroy_context; 664 i915->intel.vtbl.emit_state = i915_emit_state; 665 i915->intel.vtbl.new_batch = i915_new_batch; 666 i915->intel.vtbl.reduced_primitive_state = i915_reduced_primitive_state; 667 i915->intel.vtbl.render_start = i915_render_start; 668 i915->intel.vtbl.render_prevalidate = i915_render_prevalidate; 669 i915->intel.vtbl.set_draw_region = i915_set_draw_region; 670 i915->intel.vtbl.update_texture_state = i915UpdateTextureState; 671 i915->intel.vtbl.assert_not_dirty = i915_assert_not_dirty; 672 i915->intel.vtbl.finish_batch = intel_finish_vb; 673} 674