intel_blit.c revision 1593a1bb3435728806f66fff72a90e72a9616083
1/************************************************************************** 2 * 3 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 4 * All Rights Reserved. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the 8 * "Software"), to deal in the Software without restriction, including 9 * without limitation the rights to use, copy, modify, merge, publish, 10 * distribute, sub license, and/or sell copies of the Software, and to 11 * permit persons to whom the Software is furnished to do so, subject to 12 * the following conditions: 13 * 14 * The above copyright notice and this permission notice (including the 15 * next paragraph) shall be included in all copies or substantial portions 16 * of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 25 * 26 **************************************************************************/ 27 28 29#include <stdio.h> 30#include <errno.h> 31 32#include "main/mtypes.h" 33#include "main/context.h" 34#include "main/enums.h" 35#include "main/texformat.h" 36#include "main/colormac.h" 37 38#include "intel_blit.h" 39#include "intel_buffers.h" 40#include "intel_context.h" 41#include "intel_fbo.h" 42#include "intel_reg.h" 43#include "intel_regions.h" 44#include "intel_batchbuffer.h" 45#include "intel_chipset.h" 46 47#define FILE_DEBUG_FLAG DEBUG_BLIT 48 49/** 50 * Copy the back color buffer to the front color buffer. 51 * Used for SwapBuffers(). 52 */ 53void 54intelCopyBuffer(const __DRIdrawablePrivate * dPriv, 55 const drm_clip_rect_t * rect) 56{ 57 58 struct intel_context *intel; 59 const intelScreenPrivate *intelScreen; 60 61 DBG("%s\n", __FUNCTION__); 62 63 assert(dPriv); 64 65 intel = intelScreenContext(dPriv->driScreenPriv->private); 66 if (!intel) 67 return; 68 69 intelScreen = intel->intelScreen; 70 71 /* The LOCK_HARDWARE is required for the cliprects. Buffer offsets 72 * should work regardless. 73 */ 74 LOCK_HARDWARE(intel); 75 76 if (dPriv && dPriv->numClipRects) { 77 struct intel_framebuffer *intel_fb = dPriv->driverPrivate; 78 struct intel_region *src, *dst; 79 int nbox = dPriv->numClipRects; 80 drm_clip_rect_t *pbox = dPriv->pClipRects; 81 int cpp; 82 int src_pitch, dst_pitch; 83 unsigned short src_x, src_y; 84 int BR13, CMD; 85 int i; 86 dri_bo *aper_array[3]; 87 88 src = intel_get_rb_region(&intel_fb->Base, BUFFER_BACK_LEFT); 89 dst = intel_get_rb_region(&intel_fb->Base, BUFFER_FRONT_LEFT); 90 91 src_pitch = src->pitch * src->cpp; 92 dst_pitch = dst->pitch * dst->cpp; 93 94 cpp = src->cpp; 95 96 ASSERT(intel_fb); 97 ASSERT(intel_fb->Base.Name == 0); /* Not a user-created FBO */ 98 ASSERT(src); 99 ASSERT(dst); 100 ASSERT(src->cpp == dst->cpp); 101 102 if (cpp == 2) { 103 BR13 = (0xCC << 16) | BR13_565; 104 CMD = XY_SRC_COPY_BLT_CMD; 105 } 106 else { 107 BR13 = (0xCC << 16) | BR13_8888; 108 CMD = XY_SRC_COPY_BLT_CMD | XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB; 109 } 110 111 assert(src->tiling != I915_TILING_Y); 112 assert(dst->tiling != I915_TILING_Y); 113#ifndef I915 114 if (src->tiling != I915_TILING_NONE) { 115 CMD |= XY_SRC_TILED; 116 src_pitch /= 4; 117 } 118 if (dst->tiling != I915_TILING_NONE) { 119 CMD |= XY_DST_TILED; 120 dst_pitch /= 4; 121 } 122#endif 123 /* do space/cliprects check before going any further */ 124 intel_batchbuffer_require_space(intel->batch, 8 * 4, 125 REFERENCES_CLIPRECTS); 126 again: 127 aper_array[0] = intel->batch->buf; 128 aper_array[1] = dst->buffer; 129 aper_array[2] = src->buffer; 130 131 if (dri_bufmgr_check_aperture_space(aper_array, 3) != 0) { 132 intel_batchbuffer_flush(intel->batch); 133 goto again; 134 } 135 136 for (i = 0; i < nbox; i++, pbox++) { 137 drm_clip_rect_t box = *pbox; 138 139 if (rect) { 140 if (!intel_intersect_cliprects(&box, &box, rect)) 141 continue; 142 } 143 144 if (box.x1 >= box.x2 || 145 box.y1 >= box.y2) 146 continue; 147 148 assert(box.x1 < box.x2); 149 assert(box.y1 < box.y2); 150 src_x = box.x1 - dPriv->x + dPriv->backX; 151 src_y = box.y1 - dPriv->y + dPriv->backY; 152 153 BEGIN_BATCH(8, REFERENCES_CLIPRECTS); 154 OUT_BATCH(CMD); 155 OUT_BATCH(BR13 | dst_pitch); 156 OUT_BATCH((box.y1 << 16) | box.x1); 157 OUT_BATCH((box.y2 << 16) | box.x2); 158 159 OUT_RELOC(dst->buffer, 160 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 161 0); 162 OUT_BATCH((src_y << 16) | src_x); 163 OUT_BATCH(src_pitch); 164 OUT_RELOC(src->buffer, 165 I915_GEM_DOMAIN_RENDER, 0, 166 0); 167 ADVANCE_BATCH(); 168 } 169 170 /* Flush the rendering and the batch so that the results all land on the 171 * screen in a timely fashion. 172 */ 173 intel_batchbuffer_emit_mi_flush(intel->batch); 174 intel_batchbuffer_flush(intel->batch); 175 } 176 177 UNLOCK_HARDWARE(intel); 178} 179 180static GLuint translate_raster_op(GLenum logicop) 181{ 182 switch(logicop) { 183 case GL_CLEAR: return 0x00; 184 case GL_AND: return 0x88; 185 case GL_AND_REVERSE: return 0x44; 186 case GL_COPY: return 0xCC; 187 case GL_AND_INVERTED: return 0x22; 188 case GL_NOOP: return 0xAA; 189 case GL_XOR: return 0x66; 190 case GL_OR: return 0xEE; 191 case GL_NOR: return 0x11; 192 case GL_EQUIV: return 0x99; 193 case GL_INVERT: return 0x55; 194 case GL_OR_REVERSE: return 0xDD; 195 case GL_COPY_INVERTED: return 0x33; 196 case GL_OR_INVERTED: return 0xBB; 197 case GL_NAND: return 0x77; 198 case GL_SET: return 0xFF; 199 default: return 0; 200 } 201} 202 203 204/* Copy BitBlt 205 */ 206GLboolean 207intelEmitCopyBlit(struct intel_context *intel, 208 GLuint cpp, 209 GLshort src_pitch, 210 dri_bo *src_buffer, 211 GLuint src_offset, 212 uint32_t src_tiling, 213 GLshort dst_pitch, 214 dri_bo *dst_buffer, 215 GLuint dst_offset, 216 uint32_t dst_tiling, 217 GLshort src_x, GLshort src_y, 218 GLshort dst_x, GLshort dst_y, 219 GLshort w, GLshort h, 220 GLenum logic_op) 221{ 222 GLuint CMD, BR13, pass = 0; 223 int dst_y2 = dst_y + h; 224 int dst_x2 = dst_x + w; 225 dri_bo *aper_array[3]; 226 BATCH_LOCALS; 227 228 if (dst_tiling != I915_TILING_NONE) { 229 if (dst_offset & 4095) 230 return GL_FALSE; 231 if (dst_tiling == I915_TILING_Y) 232 return GL_FALSE; 233 } 234 if (src_tiling != I915_TILING_NONE) { 235 if (src_offset & 4095) 236 return GL_FALSE; 237 if (src_tiling == I915_TILING_Y) 238 return GL_FALSE; 239 } 240 241 /* do space/cliprects check before going any further */ 242 do { 243 aper_array[0] = intel->batch->buf; 244 aper_array[1] = dst_buffer; 245 aper_array[2] = src_buffer; 246 247 if (dri_bufmgr_check_aperture_space(aper_array, 3) != 0) { 248 intel_batchbuffer_flush(intel->batch); 249 pass++; 250 } else 251 break; 252 } while (pass < 2); 253 254 if (pass >= 2) { 255 GLboolean locked = GL_FALSE; 256 if (!intel->locked) { 257 LOCK_HARDWARE(intel); 258 locked = GL_TRUE; 259 } 260 261 dri_bo_map(dst_buffer, GL_TRUE); 262 dri_bo_map(src_buffer, GL_FALSE); 263 _mesa_copy_rect((GLubyte *)dst_buffer->virtual + dst_offset, 264 cpp, 265 dst_pitch, 266 dst_x, dst_y, 267 w, h, 268 (GLubyte *)src_buffer->virtual + src_offset, 269 src_pitch, 270 src_x, src_y); 271 272 dri_bo_unmap(src_buffer); 273 dri_bo_unmap(dst_buffer); 274 275 if (locked) 276 UNLOCK_HARDWARE(intel); 277 278 return GL_TRUE; 279 } 280 281 intel_batchbuffer_require_space(intel->batch, 8 * 4, NO_LOOP_CLIPRECTS); 282 DBG("%s src:buf(%p)/%d+%d %d,%d dst:buf(%p)/%d+%d %d,%d sz:%dx%d\n", 283 __FUNCTION__, 284 src_buffer, src_pitch, src_offset, src_x, src_y, 285 dst_buffer, dst_pitch, dst_offset, dst_x, dst_y, w, h); 286 287 src_pitch *= cpp; 288 dst_pitch *= cpp; 289 290 BR13 = translate_raster_op(logic_op) << 16; 291 292 switch (cpp) { 293 case 1: 294 CMD = XY_SRC_COPY_BLT_CMD; 295 break; 296 case 2: 297 BR13 |= BR13_565; 298 CMD = XY_SRC_COPY_BLT_CMD; 299 break; 300 case 4: 301 BR13 |= BR13_8888; 302 CMD = XY_SRC_COPY_BLT_CMD | XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB; 303 break; 304 default: 305 return GL_FALSE; 306 } 307 308#ifndef I915 309 if (dst_tiling != I915_TILING_NONE) { 310 CMD |= XY_DST_TILED; 311 dst_pitch /= 4; 312 } 313 if (src_tiling != I915_TILING_NONE) { 314 CMD |= XY_SRC_TILED; 315 src_pitch /= 4; 316 } 317#endif 318 319 if (dst_y2 <= dst_y || dst_x2 <= dst_x) { 320 return GL_TRUE; 321 } 322 323 assert(dst_x < dst_x2); 324 assert(dst_y < dst_y2); 325 326 BEGIN_BATCH(8, NO_LOOP_CLIPRECTS); 327 OUT_BATCH(CMD); 328 OUT_BATCH(BR13 | (uint16_t)dst_pitch); 329 OUT_BATCH((dst_y << 16) | dst_x); 330 OUT_BATCH((dst_y2 << 16) | dst_x2); 331 OUT_RELOC(dst_buffer, 332 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 333 dst_offset); 334 OUT_BATCH((src_y << 16) | src_x); 335 OUT_BATCH((uint16_t)src_pitch); 336 OUT_RELOC(src_buffer, 337 I915_GEM_DOMAIN_RENDER, 0, 338 src_offset); 339 ADVANCE_BATCH(); 340 341 intel_batchbuffer_emit_mi_flush(intel->batch); 342 343 return GL_TRUE; 344} 345 346 347/** 348 * Use blitting to clear the renderbuffers named by 'flags'. 349 * Note: we can't use the ctx->DrawBuffer->_ColorDrawBufferIndexes field 350 * since that might include software renderbuffers or renderbuffers 351 * which we're clearing with triangles. 352 * \param mask bitmask of BUFFER_BIT_* values indicating buffers to clear 353 */ 354void 355intelClearWithBlit(GLcontext *ctx, GLbitfield mask) 356{ 357 struct intel_context *intel = intel_context(ctx); 358 struct gl_framebuffer *fb = ctx->DrawBuffer; 359 GLuint clear_depth; 360 GLbitfield skipBuffers = 0; 361 unsigned int num_cliprects; 362 struct drm_clip_rect *cliprects; 363 int x_off, y_off; 364 BATCH_LOCALS; 365 366 /* 367 * Compute values for clearing the buffers. 368 */ 369 clear_depth = 0; 370 if (mask & BUFFER_BIT_DEPTH) { 371 clear_depth = (GLuint) (fb->_DepthMax * ctx->Depth.Clear); 372 } 373 if (mask & BUFFER_BIT_STENCIL) { 374 clear_depth |= (ctx->Stencil.Clear & 0xff) << 24; 375 } 376 377 /* If clearing both depth and stencil, skip BUFFER_BIT_STENCIL in 378 * the loop below. 379 */ 380 if ((mask & BUFFER_BIT_DEPTH) && (mask & BUFFER_BIT_STENCIL)) { 381 skipBuffers = BUFFER_BIT_STENCIL; 382 } 383 384 /* XXX Move this flush/lock into the following conditional? */ 385 intelFlush(&intel->ctx); 386 LOCK_HARDWARE(intel); 387 388 intel_get_cliprects(intel, &cliprects, &num_cliprects, &x_off, &y_off); 389 if (num_cliprects) { 390 GLint cx, cy, cw, ch; 391 drm_clip_rect_t clear; 392 int i; 393 394 /* Get clear bounds after locking */ 395 cx = fb->_Xmin; 396 cy = fb->_Ymin; 397 cw = fb->_Xmax - cx; 398 ch = fb->_Ymax - cy; 399 400 if (fb->Name == 0) { 401 /* clearing a window */ 402 403 /* flip top to bottom */ 404 clear.x1 = cx + x_off; 405 clear.y1 = intel->driDrawable->y + intel->driDrawable->h - cy - ch; 406 clear.x2 = clear.x1 + cw; 407 clear.y2 = clear.y1 + ch; 408 } 409 else { 410 /* clearing FBO */ 411 assert(num_cliprects == 1); 412 assert(cliprects == &intel->fboRect); 413 clear.x1 = cx; 414 clear.y1 = cy; 415 clear.x2 = clear.x1 + cw; 416 clear.y2 = clear.y1 + ch; 417 /* no change to mask */ 418 } 419 420 for (i = 0; i < num_cliprects; i++) { 421 const drm_clip_rect_t *box = &cliprects[i]; 422 drm_clip_rect_t b; 423 GLuint buf; 424 GLuint clearMask = mask; /* use copy, since we modify it below */ 425 GLboolean all = (cw == fb->Width && ch == fb->Height); 426 427 if (!all) { 428 intel_intersect_cliprects(&b, &clear, box); 429 } 430 else { 431 b = *box; 432 } 433 434 if (b.x1 >= b.x2 || b.y1 >= b.y2) 435 continue; 436 437 if (0) 438 _mesa_printf("clear %d,%d..%d,%d, mask %x\n", 439 b.x1, b.y1, b.x2, b.y2, mask); 440 441 /* Loop over all renderbuffers */ 442 for (buf = 0; buf < BUFFER_COUNT && clearMask; buf++) { 443 const GLbitfield bufBit = 1 << buf; 444 if ((clearMask & bufBit) && !(bufBit & skipBuffers)) { 445 /* OK, clear this renderbuffer */ 446 struct intel_renderbuffer *irb = intel_get_renderbuffer(fb, buf); 447 dri_bo *write_buffer = 448 intel_region_buffer(intel, irb->region, 449 all ? INTEL_WRITE_FULL : 450 INTEL_WRITE_PART); 451 452 GLuint clearVal; 453 GLint pitch, cpp; 454 GLuint BR13, CMD; 455 456 pitch = irb->region->pitch; 457 cpp = irb->region->cpp; 458 459 DBG("%s dst:buf(%p)/%d+%d %d,%d sz:%dx%d\n", 460 __FUNCTION__, 461 irb->region->buffer, (pitch * cpp), 462 irb->region->draw_offset, 463 b.x1, b.y1, b.x2 - b.x1, b.y2 - b.y1); 464 465 BR13 = 0xf0 << 16; 466 CMD = XY_COLOR_BLT_CMD; 467 468 /* Setup the blit command */ 469 if (cpp == 4) { 470 BR13 |= BR13_8888; 471 if (buf == BUFFER_DEPTH || buf == BUFFER_STENCIL) { 472 if (clearMask & BUFFER_BIT_DEPTH) 473 CMD |= XY_BLT_WRITE_RGB; 474 if (clearMask & BUFFER_BIT_STENCIL) 475 CMD |= XY_BLT_WRITE_ALPHA; 476 } 477 else { 478 /* clearing RGBA */ 479 CMD |= XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB; 480 } 481 } 482 else { 483 ASSERT(cpp == 2); 484 BR13 |= BR13_565; 485 } 486 487#ifndef I915 488 if (irb->region->tiling != I915_TILING_NONE) { 489 CMD |= XY_DST_TILED; 490 pitch /= 4; 491 } 492#endif 493 BR13 |= (pitch * cpp); 494 495 if (buf == BUFFER_DEPTH || buf == BUFFER_STENCIL) { 496 clearVal = clear_depth; 497 } 498 else { 499 uint8_t clear[4]; 500 GLclampf *color = ctx->Color.ClearColor; 501 502 CLAMPED_FLOAT_TO_UBYTE(clear[0], color[0]); 503 CLAMPED_FLOAT_TO_UBYTE(clear[1], color[1]); 504 CLAMPED_FLOAT_TO_UBYTE(clear[2], color[2]); 505 CLAMPED_FLOAT_TO_UBYTE(clear[3], color[3]); 506 507 switch (irb->texformat->MesaFormat) { 508 case MESA_FORMAT_ARGB8888: 509 clearVal = intel->ClearColor8888; 510 break; 511 case MESA_FORMAT_RGB565: 512 clearVal = intel->ClearColor565; 513 break; 514 case MESA_FORMAT_ARGB4444: 515 clearVal = PACK_COLOR_4444(clear[3], clear[0], 516 clear[1], clear[2]); 517 break; 518 case MESA_FORMAT_ARGB1555: 519 clearVal = PACK_COLOR_1555(clear[3], clear[0], 520 clear[1], clear[2]); 521 break; 522 default: 523 _mesa_problem(ctx, "Unexpected renderbuffer format: %d\n", 524 irb->texformat->MesaFormat); 525 clearVal = 0; 526 } 527 } 528 529 /* 530 _mesa_debug(ctx, "hardware blit clear buf %d rb id %d\n", 531 buf, irb->Base.Name); 532 */ 533 534 assert(b.x1 < b.x2); 535 assert(b.y1 < b.y2); 536 537 BEGIN_BATCH(6, REFERENCES_CLIPRECTS); 538 OUT_BATCH(CMD); 539 OUT_BATCH(BR13); 540 OUT_BATCH((b.y1 << 16) | b.x1); 541 OUT_BATCH((b.y2 << 16) | b.x2); 542 OUT_RELOC(write_buffer, 543 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 544 irb->region->draw_offset); 545 OUT_BATCH(clearVal); 546 ADVANCE_BATCH(); 547 clearMask &= ~bufBit; /* turn off bit, for faster loop exit */ 548 } 549 } 550 } 551 } 552 553 UNLOCK_HARDWARE(intel); 554} 555 556GLboolean 557intelEmitImmediateColorExpandBlit(struct intel_context *intel, 558 GLuint cpp, 559 GLubyte *src_bits, GLuint src_size, 560 GLuint fg_color, 561 GLshort dst_pitch, 562 dri_bo *dst_buffer, 563 GLuint dst_offset, 564 uint32_t dst_tiling, 565 GLshort x, GLshort y, 566 GLshort w, GLshort h, 567 GLenum logic_op) 568{ 569 int dwords = ALIGN(src_size, 8) / 4; 570 uint32_t opcode, br13, blit_cmd; 571 572 if (dst_tiling != I915_TILING_NONE) { 573 if (dst_offset & 4095) 574 return GL_FALSE; 575 if (dst_tiling == I915_TILING_Y) 576 return GL_FALSE; 577 } 578 579 assert( logic_op - GL_CLEAR >= 0 ); 580 assert( logic_op - GL_CLEAR < 0x10 ); 581 582 if (w < 0 || h < 0) 583 return GL_TRUE; 584 585 dst_pitch *= cpp; 586 587 DBG("%s dst:buf(%p)/%d+%d %d,%d sz:%dx%d, %d bytes %d dwords\n", 588 __FUNCTION__, 589 dst_buffer, dst_pitch, dst_offset, x, y, w, h, src_size, dwords); 590 591 intel_batchbuffer_require_space( intel->batch, 592 (8 * 4) + 593 (3 * 4) + 594 dwords * 4, 595 REFERENCES_CLIPRECTS ); 596 597 opcode = XY_SETUP_BLT_CMD; 598 if (cpp == 4) 599 opcode |= XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB; 600#ifndef I915 601 if (dst_tiling != I915_TILING_NONE) { 602 opcode |= XY_DST_TILED; 603 dst_pitch /= 4; 604 } 605#endif 606 607 br13 = dst_pitch | (translate_raster_op(logic_op) << 16) | (1 << 29); 608 if (cpp == 2) 609 br13 |= BR13_565; 610 else 611 br13 |= BR13_8888; 612 613 blit_cmd = XY_TEXT_IMMEDIATE_BLIT_CMD | XY_TEXT_BYTE_PACKED; /* packing? */ 614 if (dst_tiling != I915_TILING_NONE) 615 blit_cmd |= XY_DST_TILED; 616 617 BEGIN_BATCH(8 + 3, REFERENCES_CLIPRECTS); 618 OUT_BATCH(opcode); 619 OUT_BATCH(br13); 620 OUT_BATCH((0 << 16) | 0); /* clip x1, y1 */ 621 OUT_BATCH((100 << 16) | 100); /* clip x2, y2 */ 622 OUT_RELOC(dst_buffer, 623 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 624 dst_offset); 625 OUT_BATCH(0); /* bg */ 626 OUT_BATCH(fg_color); /* fg */ 627 OUT_BATCH(0); /* pattern base addr */ 628 629 OUT_BATCH(blit_cmd | ((3 - 2) + dwords)); 630 OUT_BATCH((y << 16) | x); 631 OUT_BATCH(((y + h) << 16) | (x + w)); 632 ADVANCE_BATCH(); 633 634 intel_batchbuffer_data( intel->batch, 635 src_bits, 636 dwords * 4, 637 REFERENCES_CLIPRECTS ); 638 639 intel_batchbuffer_emit_mi_flush(intel->batch); 640 641 return GL_TRUE; 642} 643