intel_blit.c revision 8f81a6468fdbc7320800ea497791e3e1b8f782ca
1/************************************************************************** 2 * 3 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 4 * All Rights Reserved. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the 8 * "Software"), to deal in the Software without restriction, including 9 * without limitation the rights to use, copy, modify, merge, publish, 10 * distribute, sub license, and/or sell copies of the Software, and to 11 * permit persons to whom the Software is furnished to do so, subject to 12 * the following conditions: 13 * 14 * The above copyright notice and this permission notice (including the 15 * next paragraph) shall be included in all copies or substantial portions 16 * of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 25 * 26 **************************************************************************/ 27 28 29#include <stdio.h> 30#include <errno.h> 31 32#include "main/mtypes.h" 33#include "main/context.h" 34#include "main/enums.h" 35#include "main/texformat.h" 36#include "main/colormac.h" 37 38#include "intel_blit.h" 39#include "intel_buffers.h" 40#include "intel_context.h" 41#include "intel_fbo.h" 42#include "intel_reg.h" 43#include "intel_regions.h" 44#include "intel_batchbuffer.h" 45#include "intel_chipset.h" 46 47#define FILE_DEBUG_FLAG DEBUG_BLIT 48 49/** 50 * Copy the back color buffer to the front color buffer. 51 * Used for SwapBuffers(). 52 */ 53void 54intelCopyBuffer(const __DRIdrawablePrivate * dPriv, 55 const drm_clip_rect_t * rect) 56{ 57 58 struct intel_context *intel; 59 const intelScreenPrivate *intelScreen; 60 61 DBG("%s\n", __FUNCTION__); 62 63 assert(dPriv); 64 65 intel = intelScreenContext(dPriv->driScreenPriv->private); 66 if (!intel) 67 return; 68 69 intelScreen = intel->intelScreen; 70 71 /* The LOCK_HARDWARE is required for the cliprects. Buffer offsets 72 * should work regardless. 73 */ 74 LOCK_HARDWARE(intel); 75 76 if (dPriv && dPriv->numClipRects) { 77 struct intel_framebuffer *intel_fb = dPriv->driverPrivate; 78 struct intel_region *src, *dst; 79 int nbox = dPriv->numClipRects; 80 drm_clip_rect_t *pbox = dPriv->pClipRects; 81 int cpp; 82 int src_pitch, dst_pitch; 83 unsigned short src_x, src_y; 84 int BR13, CMD; 85 int i; 86 dri_bo *aper_array[3]; 87 88 src = intel_get_rb_region(&intel_fb->Base, BUFFER_BACK_LEFT); 89 dst = intel_get_rb_region(&intel_fb->Base, BUFFER_FRONT_LEFT); 90 91 src_pitch = src->pitch * src->cpp; 92 dst_pitch = dst->pitch * dst->cpp; 93 94 cpp = src->cpp; 95 96 ASSERT(intel_fb); 97 ASSERT(intel_fb->Base.Name == 0); /* Not a user-created FBO */ 98 ASSERT(src); 99 ASSERT(dst); 100 ASSERT(src->cpp == dst->cpp); 101 102 if (cpp == 2) { 103 BR13 = (0xCC << 16) | BR13_565; 104 CMD = XY_SRC_COPY_BLT_CMD; 105 } 106 else { 107 BR13 = (0xCC << 16) | BR13_8888; 108 CMD = XY_SRC_COPY_BLT_CMD | XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB; 109 } 110 111 assert(src->tiling != I915_TILING_Y); 112 assert(dst->tiling != I915_TILING_Y); 113#ifndef I915 114 if (src->tiling != I915_TILING_NONE) { 115 CMD |= XY_SRC_TILED; 116 src_pitch /= 4; 117 } 118 if (dst->tiling != I915_TILING_NONE) { 119 CMD |= XY_DST_TILED; 120 dst_pitch /= 4; 121 } 122#endif 123 /* do space/cliprects check before going any further */ 124 intel_batchbuffer_require_space(intel->batch, 8 * 4, 125 REFERENCES_CLIPRECTS); 126 again: 127 aper_array[0] = intel->batch->buf; 128 aper_array[1] = dst->buffer; 129 aper_array[2] = src->buffer; 130 131 if (dri_bufmgr_check_aperture_space(aper_array, 3) != 0) { 132 intel_batchbuffer_flush(intel->batch); 133 goto again; 134 } 135 136 for (i = 0; i < nbox; i++, pbox++) { 137 drm_clip_rect_t box = *pbox; 138 139 if (rect) { 140 if (!intel_intersect_cliprects(&box, &box, rect)) 141 continue; 142 } 143 144 if (box.x1 >= box.x2 || 145 box.y1 >= box.y2) 146 continue; 147 148 assert(box.x1 < box.x2); 149 assert(box.y1 < box.y2); 150 src_x = box.x1 - dPriv->x + dPriv->backX; 151 src_y = box.y1 - dPriv->y + dPriv->backY; 152 153 BEGIN_BATCH(8, REFERENCES_CLIPRECTS); 154 OUT_BATCH(CMD); 155 OUT_BATCH(BR13 | dst_pitch); 156 OUT_BATCH((box.y1 << 16) | box.x1); 157 OUT_BATCH((box.y2 << 16) | box.x2); 158 159 OUT_RELOC(dst->buffer, 160 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 161 0); 162 OUT_BATCH((src_y << 16) | src_x); 163 OUT_BATCH(src_pitch); 164 OUT_RELOC(src->buffer, 165 I915_GEM_DOMAIN_RENDER, 0, 166 0); 167 ADVANCE_BATCH(); 168 } 169 170 /* Flush the rendering and the batch so that the results all land on the 171 * screen in a timely fashion. 172 */ 173 intel_batchbuffer_emit_mi_flush(intel->batch); 174 intel_batchbuffer_flush(intel->batch); 175 } 176 177 UNLOCK_HARDWARE(intel); 178} 179 180static GLuint translate_raster_op(GLenum logicop) 181{ 182 switch(logicop) { 183 case GL_CLEAR: return 0x00; 184 case GL_AND: return 0x88; 185 case GL_AND_REVERSE: return 0x44; 186 case GL_COPY: return 0xCC; 187 case GL_AND_INVERTED: return 0x22; 188 case GL_NOOP: return 0xAA; 189 case GL_XOR: return 0x66; 190 case GL_OR: return 0xEE; 191 case GL_NOR: return 0x11; 192 case GL_EQUIV: return 0x99; 193 case GL_INVERT: return 0x55; 194 case GL_OR_REVERSE: return 0xDD; 195 case GL_COPY_INVERTED: return 0x33; 196 case GL_OR_INVERTED: return 0xBB; 197 case GL_NAND: return 0x77; 198 case GL_SET: return 0xFF; 199 default: return 0; 200 } 201} 202 203 204/* Copy BitBlt 205 */ 206GLboolean 207intelEmitCopyBlit(struct intel_context *intel, 208 GLuint cpp, 209 GLshort src_pitch, 210 dri_bo *src_buffer, 211 GLuint src_offset, 212 uint32_t src_tiling, 213 GLshort dst_pitch, 214 dri_bo *dst_buffer, 215 GLuint dst_offset, 216 uint32_t dst_tiling, 217 GLshort src_x, GLshort src_y, 218 GLshort dst_x, GLshort dst_y, 219 GLshort w, GLshort h, 220 GLenum logic_op) 221{ 222 GLuint CMD, BR13, pass = 0; 223 int dst_y2 = dst_y + h; 224 int dst_x2 = dst_x + w; 225 dri_bo *aper_array[3]; 226 BATCH_LOCALS; 227 228 if (dst_tiling == I915_TILING_Y) 229 return GL_FALSE; 230 if (src_tiling == I915_TILING_Y) 231 return GL_FALSE; 232 233 /* do space/cliprects check before going any further */ 234 do { 235 aper_array[0] = intel->batch->buf; 236 aper_array[1] = dst_buffer; 237 aper_array[2] = src_buffer; 238 239 if (dri_bufmgr_check_aperture_space(aper_array, 3) != 0) { 240 intel_batchbuffer_flush(intel->batch); 241 pass++; 242 } else 243 break; 244 } while (pass < 2); 245 246 if (pass >= 2) { 247 GLboolean locked = GL_FALSE; 248 if (!intel->locked) { 249 LOCK_HARDWARE(intel); 250 locked = GL_TRUE; 251 } 252 253 dri_bo_map(dst_buffer, GL_TRUE); 254 dri_bo_map(src_buffer, GL_FALSE); 255 _mesa_copy_rect((GLubyte *)dst_buffer->virtual + dst_offset, 256 cpp, 257 dst_pitch, 258 dst_x, dst_y, 259 w, h, 260 (GLubyte *)src_buffer->virtual + src_offset, 261 src_pitch, 262 src_x, src_y); 263 264 dri_bo_unmap(src_buffer); 265 dri_bo_unmap(dst_buffer); 266 267 if (locked) 268 UNLOCK_HARDWARE(intel); 269 270 return GL_TRUE; 271 } 272 273 intel_batchbuffer_require_space(intel->batch, 8 * 4, NO_LOOP_CLIPRECTS); 274 DBG("%s src:buf(%p)/%d+%d %d,%d dst:buf(%p)/%d+%d %d,%d sz:%dx%d\n", 275 __FUNCTION__, 276 src_buffer, src_pitch, src_offset, src_x, src_y, 277 dst_buffer, dst_pitch, dst_offset, dst_x, dst_y, w, h); 278 279 src_pitch *= cpp; 280 dst_pitch *= cpp; 281 282 BR13 = translate_raster_op(logic_op) << 16; 283 284 switch (cpp) { 285 case 1: 286 CMD = XY_SRC_COPY_BLT_CMD; 287 break; 288 case 2: 289 BR13 |= BR13_565; 290 CMD = XY_SRC_COPY_BLT_CMD; 291 break; 292 case 4: 293 BR13 |= BR13_8888; 294 CMD = XY_SRC_COPY_BLT_CMD | XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB; 295 break; 296 default: 297 return GL_FALSE; 298 } 299 300#ifndef I915 301 if (dst_tiling != I915_TILING_NONE) { 302 CMD |= XY_DST_TILED; 303 dst_pitch /= 4; 304 } 305 if (src_tiling != I915_TILING_NONE) { 306 CMD |= XY_SRC_TILED; 307 src_pitch /= 4; 308 } 309#endif 310 311 if (dst_y2 <= dst_y || dst_x2 <= dst_x) { 312 return GL_TRUE; 313 } 314 315 assert(dst_x < dst_x2); 316 assert(dst_y < dst_y2); 317 318 BEGIN_BATCH(8, NO_LOOP_CLIPRECTS); 319 OUT_BATCH(CMD); 320 OUT_BATCH(BR13 | (uint16_t)dst_pitch); 321 OUT_BATCH((dst_y << 16) | dst_x); 322 OUT_BATCH((dst_y2 << 16) | dst_x2); 323 OUT_RELOC(dst_buffer, 324 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 325 dst_offset); 326 OUT_BATCH((src_y << 16) | src_x); 327 OUT_BATCH((uint16_t)src_pitch); 328 OUT_RELOC(src_buffer, 329 I915_GEM_DOMAIN_RENDER, 0, 330 src_offset); 331 ADVANCE_BATCH(); 332 333 intel_batchbuffer_emit_mi_flush(intel->batch); 334 335 return GL_TRUE; 336} 337 338 339/** 340 * Use blitting to clear the renderbuffers named by 'flags'. 341 * Note: we can't use the ctx->DrawBuffer->_ColorDrawBufferIndexes field 342 * since that might include software renderbuffers or renderbuffers 343 * which we're clearing with triangles. 344 * \param mask bitmask of BUFFER_BIT_* values indicating buffers to clear 345 */ 346void 347intelClearWithBlit(GLcontext *ctx, GLbitfield mask) 348{ 349 struct intel_context *intel = intel_context(ctx); 350 struct gl_framebuffer *fb = ctx->DrawBuffer; 351 GLuint clear_depth; 352 GLbitfield skipBuffers = 0; 353 unsigned int num_cliprects; 354 struct drm_clip_rect *cliprects; 355 int x_off, y_off; 356 BATCH_LOCALS; 357 358 /* 359 * Compute values for clearing the buffers. 360 */ 361 clear_depth = 0; 362 if (mask & BUFFER_BIT_DEPTH) { 363 clear_depth = (GLuint) (fb->_DepthMax * ctx->Depth.Clear); 364 } 365 if (mask & BUFFER_BIT_STENCIL) { 366 clear_depth |= (ctx->Stencil.Clear & 0xff) << 24; 367 } 368 369 /* If clearing both depth and stencil, skip BUFFER_BIT_STENCIL in 370 * the loop below. 371 */ 372 if ((mask & BUFFER_BIT_DEPTH) && (mask & BUFFER_BIT_STENCIL)) { 373 skipBuffers = BUFFER_BIT_STENCIL; 374 } 375 376 /* XXX Move this flush/lock into the following conditional? */ 377 intelFlush(&intel->ctx); 378 LOCK_HARDWARE(intel); 379 380 intel_get_cliprects(intel, &cliprects, &num_cliprects, &x_off, &y_off); 381 if (num_cliprects) { 382 GLint cx, cy, cw, ch; 383 drm_clip_rect_t clear; 384 int i; 385 386 /* Get clear bounds after locking */ 387 cx = fb->_Xmin; 388 cy = fb->_Ymin; 389 cw = fb->_Xmax - cx; 390 ch = fb->_Ymax - cy; 391 392 if (fb->Name == 0) { 393 /* clearing a window */ 394 395 /* flip top to bottom */ 396 clear.x1 = cx + x_off; 397 clear.y1 = intel->driDrawable->y + intel->driDrawable->h - cy - ch; 398 clear.x2 = clear.x1 + cw; 399 clear.y2 = clear.y1 + ch; 400 } 401 else { 402 /* clearing FBO */ 403 assert(num_cliprects == 1); 404 assert(cliprects == &intel->fboRect); 405 clear.x1 = cx; 406 clear.y1 = cy; 407 clear.x2 = clear.x1 + cw; 408 clear.y2 = clear.y1 + ch; 409 /* no change to mask */ 410 } 411 412 for (i = 0; i < num_cliprects; i++) { 413 const drm_clip_rect_t *box = &cliprects[i]; 414 drm_clip_rect_t b; 415 GLuint buf; 416 GLuint clearMask = mask; /* use copy, since we modify it below */ 417 GLboolean all = (cw == fb->Width && ch == fb->Height); 418 419 if (!all) { 420 intel_intersect_cliprects(&b, &clear, box); 421 } 422 else { 423 b = *box; 424 } 425 426 if (b.x1 >= b.x2 || b.y1 >= b.y2) 427 continue; 428 429 if (0) 430 _mesa_printf("clear %d,%d..%d,%d, mask %x\n", 431 b.x1, b.y1, b.x2, b.y2, mask); 432 433 /* Loop over all renderbuffers */ 434 for (buf = 0; buf < BUFFER_COUNT && clearMask; buf++) { 435 const GLbitfield bufBit = 1 << buf; 436 if ((clearMask & bufBit) && !(bufBit & skipBuffers)) { 437 /* OK, clear this renderbuffer */ 438 struct intel_renderbuffer *irb = intel_get_renderbuffer(fb, buf); 439 dri_bo *write_buffer = 440 intel_region_buffer(intel, irb->region, 441 all ? INTEL_WRITE_FULL : 442 INTEL_WRITE_PART); 443 444 GLuint clearVal; 445 GLint pitch, cpp; 446 GLuint BR13, CMD; 447 448 pitch = irb->region->pitch; 449 cpp = irb->region->cpp; 450 451 DBG("%s dst:buf(%p)/%d+%d %d,%d sz:%dx%d\n", 452 __FUNCTION__, 453 irb->region->buffer, (pitch * cpp), 454 irb->region->draw_offset, 455 b.x1, b.y1, b.x2 - b.x1, b.y2 - b.y1); 456 457 BR13 = 0xf0 << 16; 458 CMD = XY_COLOR_BLT_CMD; 459 460 /* Setup the blit command */ 461 if (cpp == 4) { 462 BR13 |= BR13_8888; 463 if (buf == BUFFER_DEPTH || buf == BUFFER_STENCIL) { 464 if (clearMask & BUFFER_BIT_DEPTH) 465 CMD |= XY_BLT_WRITE_RGB; 466 if (clearMask & BUFFER_BIT_STENCIL) 467 CMD |= XY_BLT_WRITE_ALPHA; 468 } 469 else { 470 /* clearing RGBA */ 471 CMD |= XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB; 472 } 473 } 474 else { 475 ASSERT(cpp == 2); 476 BR13 |= BR13_565; 477 } 478 479#ifndef I915 480 if (irb->region->tiling != I915_TILING_NONE) { 481 CMD |= XY_DST_TILED; 482 pitch /= 4; 483 } 484#endif 485 BR13 |= (pitch * cpp); 486 487 if (buf == BUFFER_DEPTH || buf == BUFFER_STENCIL) { 488 clearVal = clear_depth; 489 } 490 else { 491 uint8_t clear[4]; 492 GLclampf *color = ctx->Color.ClearColor; 493 494 CLAMPED_FLOAT_TO_UBYTE(clear[0], color[0]); 495 CLAMPED_FLOAT_TO_UBYTE(clear[1], color[1]); 496 CLAMPED_FLOAT_TO_UBYTE(clear[2], color[2]); 497 CLAMPED_FLOAT_TO_UBYTE(clear[3], color[3]); 498 499 switch (irb->texformat->MesaFormat) { 500 case MESA_FORMAT_ARGB8888: 501 clearVal = intel->ClearColor8888; 502 break; 503 case MESA_FORMAT_RGB565: 504 clearVal = intel->ClearColor565; 505 break; 506 case MESA_FORMAT_ARGB4444: 507 clearVal = PACK_COLOR_4444(clear[3], clear[0], 508 clear[1], clear[2]); 509 break; 510 case MESA_FORMAT_ARGB1555: 511 clearVal = PACK_COLOR_1555(clear[3], clear[0], 512 clear[1], clear[2]); 513 break; 514 default: 515 _mesa_problem(ctx, "Unexpected renderbuffer format: %d\n", 516 irb->texformat->MesaFormat); 517 clearVal = 0; 518 } 519 } 520 521 /* 522 _mesa_debug(ctx, "hardware blit clear buf %d rb id %d\n", 523 buf, irb->Base.Name); 524 */ 525 526 assert(b.x1 < b.x2); 527 assert(b.y1 < b.y2); 528 529 BEGIN_BATCH(6, REFERENCES_CLIPRECTS); 530 OUT_BATCH(CMD); 531 OUT_BATCH(BR13); 532 OUT_BATCH((b.y1 << 16) | b.x1); 533 OUT_BATCH((b.y2 << 16) | b.x2); 534 OUT_RELOC(write_buffer, 535 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 536 irb->region->draw_offset); 537 OUT_BATCH(clearVal); 538 ADVANCE_BATCH(); 539 clearMask &= ~bufBit; /* turn off bit, for faster loop exit */ 540 } 541 } 542 } 543 } 544 545 UNLOCK_HARDWARE(intel); 546} 547 548GLboolean 549intelEmitImmediateColorExpandBlit(struct intel_context *intel, 550 GLuint cpp, 551 GLubyte *src_bits, GLuint src_size, 552 GLuint fg_color, 553 GLshort dst_pitch, 554 dri_bo *dst_buffer, 555 GLuint dst_offset, 556 uint32_t dst_tiling, 557 GLshort x, GLshort y, 558 GLshort w, GLshort h, 559 GLenum logic_op) 560{ 561 int dwords = ALIGN(src_size, 8) / 4; 562 uint32_t opcode, br13, blit_cmd; 563 564 if (dst_tiling == I915_TILING_Y) 565 return GL_FALSE; 566 567 assert( logic_op - GL_CLEAR >= 0 ); 568 assert( logic_op - GL_CLEAR < 0x10 ); 569 570 if (w < 0 || h < 0) 571 return GL_TRUE; 572 573 dst_pitch *= cpp; 574 575 DBG("%s dst:buf(%p)/%d+%d %d,%d sz:%dx%d, %d bytes %d dwords\n", 576 __FUNCTION__, 577 dst_buffer, dst_pitch, dst_offset, x, y, w, h, src_size, dwords); 578 579 intel_batchbuffer_require_space( intel->batch, 580 (8 * 4) + 581 (3 * 4) + 582 dwords * 4, 583 REFERENCES_CLIPRECTS ); 584 585 opcode = XY_SETUP_BLT_CMD; 586 if (cpp == 4) 587 opcode |= XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB; 588#ifndef I915 589 if (dst_tiling != I915_TILING_NONE) { 590 opcode |= XY_DST_TILED; 591 dst_pitch /= 4; 592 } 593#endif 594 595 br13 = dst_pitch | (translate_raster_op(logic_op) << 16) | (1 << 29); 596 if (cpp == 2) 597 br13 |= BR13_565; 598 else 599 br13 |= BR13_8888; 600 601 blit_cmd = XY_TEXT_IMMEDIATE_BLIT_CMD | XY_TEXT_BYTE_PACKED; /* packing? */ 602 if (dst_tiling != I915_TILING_NONE) 603 blit_cmd |= XY_DST_TILED; 604 605 BEGIN_BATCH(8 + 3, REFERENCES_CLIPRECTS); 606 OUT_BATCH(opcode); 607 OUT_BATCH(br13); 608 OUT_BATCH((0 << 16) | 0); /* clip x1, y1 */ 609 OUT_BATCH((100 << 16) | 100); /* clip x2, y2 */ 610 OUT_RELOC(dst_buffer, 611 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 612 dst_offset); 613 OUT_BATCH(0); /* bg */ 614 OUT_BATCH(fg_color); /* fg */ 615 OUT_BATCH(0); /* pattern base addr */ 616 617 OUT_BATCH(blit_cmd | ((3 - 2) + dwords)); 618 OUT_BATCH((y << 16) | x); 619 OUT_BATCH(((y + h) << 16) | (x + w)); 620 ADVANCE_BATCH(); 621 622 intel_batchbuffer_data( intel->batch, 623 src_bits, 624 dwords * 4, 625 REFERENCES_CLIPRECTS ); 626 627 intel_batchbuffer_emit_mi_flush(intel->batch); 628 629 return GL_TRUE; 630} 631