intel_blit.c revision 0cade4de4f74f6b0e86fb6622e2fc370c73fd840
1/************************************************************************** 2 * 3 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 4 * All Rights Reserved. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the 8 * "Software"), to deal in the Software without restriction, including 9 * without limitation the rights to use, copy, modify, merge, publish, 10 * distribute, sub license, and/or sell copies of the Software, and to 11 * permit persons to whom the Software is furnished to do so, subject to 12 * the following conditions: 13 * 14 * The above copyright notice and this permission notice (including the 15 * next paragraph) shall be included in all copies or substantial portions 16 * of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 25 * 26 **************************************************************************/ 27 28 29#include <stdio.h> 30#include <errno.h> 31 32#include "main/mtypes.h" 33#include "main/context.h" 34#include "main/enums.h" 35 36#include "intel_blit.h" 37#include "intel_buffers.h" 38#include "intel_context.h" 39#include "intel_fbo.h" 40#include "intel_reg.h" 41#include "intel_regions.h" 42#include "intel_batchbuffer.h" 43 44#define FILE_DEBUG_FLAG DEBUG_BLIT 45 46/** 47 * Copy the back color buffer to the front color buffer. 48 * Used for SwapBuffers(). 49 */ 50void 51intelCopyBuffer(const __DRIdrawablePrivate * dPriv, 52 const drm_clip_rect_t * rect) 53{ 54 55 struct intel_context *intel; 56 const intelScreenPrivate *intelScreen; 57 58 DBG("%s\n", __FUNCTION__); 59 60 assert(dPriv); 61 62 intel = intelScreenContext(dPriv->driScreenPriv->private); 63 if (!intel) 64 return; 65 66 intelScreen = intel->intelScreen; 67 68 /* The LOCK_HARDWARE is required for the cliprects. Buffer offsets 69 * should work regardless. 70 */ 71 LOCK_HARDWARE(intel); 72 73 if (dPriv && dPriv->numClipRects) { 74 struct intel_framebuffer *intel_fb = dPriv->driverPrivate; 75 struct intel_region *src, *dst; 76 int nbox = dPriv->numClipRects; 77 drm_clip_rect_t *pbox = dPriv->pClipRects; 78 int cpp; 79 int src_pitch, dst_pitch; 80 unsigned short src_x, src_y; 81 int BR13, CMD; 82 int i; 83 dri_bo *aper_array[3]; 84 85 src = intel_get_rb_region(&intel_fb->Base, BUFFER_BACK_LEFT); 86 dst = intel_get_rb_region(&intel_fb->Base, BUFFER_FRONT_LEFT); 87 88 src_pitch = src->pitch * src->cpp; 89 dst_pitch = dst->pitch * dst->cpp; 90 91 cpp = src->cpp; 92 93 ASSERT(intel_fb); 94 ASSERT(intel_fb->Base.Name == 0); /* Not a user-created FBO */ 95 ASSERT(src); 96 ASSERT(dst); 97 ASSERT(src->cpp == dst->cpp); 98 99 if (cpp == 2) { 100 BR13 = (0xCC << 16) | (1 << 24); 101 CMD = XY_SRC_COPY_BLT_CMD; 102 } 103 else { 104 BR13 = (0xCC << 16) | (1 << 24) | (1 << 25); 105 CMD = XY_SRC_COPY_BLT_CMD | XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB; 106 } 107 108#ifndef I915 109 if (src->tiling != I915_TILING_NONE) { 110 CMD |= XY_SRC_TILED; 111 src_pitch /= 4; 112 } 113 if (dst->tiling != I915_TILING_NONE) { 114 CMD |= XY_DST_TILED; 115 dst_pitch /= 4; 116 } 117#endif 118 /* do space/cliprects check before going any further */ 119 intel_batchbuffer_require_space(intel->batch, 8 * 4, 120 REFERENCES_CLIPRECTS); 121 again: 122 aper_array[0] = intel->batch->buf; 123 aper_array[1] = dst->buffer; 124 aper_array[2] = src->buffer; 125 126 if (dri_bufmgr_check_aperture_space(aper_array, 3) != 0) { 127 intel_batchbuffer_flush(intel->batch); 128 goto again; 129 } 130 131 for (i = 0; i < nbox; i++, pbox++) { 132 drm_clip_rect_t box = *pbox; 133 134 if (rect) { 135 if (!intel_intersect_cliprects(&box, &box, rect)) 136 continue; 137 } 138 139 if (box.x1 >= box.x2 || 140 box.y1 >= box.y2) 141 continue; 142 143 assert(box.x1 < box.x2); 144 assert(box.y1 < box.y2); 145 src_x = box.x1 - dPriv->x + dPriv->backX; 146 src_y = box.y1 - dPriv->y + dPriv->backY; 147 148 BEGIN_BATCH(8, REFERENCES_CLIPRECTS); 149 OUT_BATCH(CMD); 150 OUT_BATCH(BR13 | dst_pitch); 151 OUT_BATCH((box.y1 << 16) | box.x1); 152 OUT_BATCH((box.y2 << 16) | box.x2); 153 154 OUT_RELOC(dst->buffer, 155 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 156 0); 157 OUT_BATCH((src_y << 16) | src_x); 158 OUT_BATCH(src_pitch); 159 OUT_RELOC(src->buffer, 160 I915_GEM_DOMAIN_RENDER, 0, 161 0); 162 ADVANCE_BATCH(); 163 } 164 165 /* Flush the rendering and the batch so that the results all land on the 166 * screen in a timely fashion. 167 */ 168 intel_batchbuffer_emit_mi_flush(intel->batch); 169 intel_batchbuffer_flush(intel->batch); 170 } 171 172 UNLOCK_HARDWARE(intel); 173} 174 175 176 177 178void 179intelEmitFillBlit(struct intel_context *intel, 180 GLuint cpp, 181 GLshort dst_pitch, 182 dri_bo *dst_buffer, 183 GLuint dst_offset, 184 uint32_t dst_tiling, 185 GLshort x, GLshort y, 186 GLshort w, GLshort h, 187 GLuint color) 188{ 189 GLuint BR13, CMD; 190 BATCH_LOCALS; 191 192 dst_pitch *= cpp; 193 194 switch (cpp) { 195 case 1: 196 case 2: 197 case 3: 198 BR13 = (0xF0 << 16) | (1 << 24); 199 CMD = XY_COLOR_BLT_CMD; 200 break; 201 case 4: 202 BR13 = (0xF0 << 16) | (1 << 24) | (1 << 25); 203 CMD = XY_COLOR_BLT_CMD | XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB; 204 break; 205 default: 206 return; 207 } 208#ifndef I915 209 if (dst_tiling != I915_TILING_NONE) { 210 CMD |= XY_DST_TILED; 211 dst_pitch /= 4; 212 } 213#endif 214 215 DBG("%s dst:buf(%p)/%d+%d %d,%d sz:%dx%d\n", 216 __FUNCTION__, dst_buffer, dst_pitch, dst_offset, x, y, w, h); 217 218 assert(w > 0); 219 assert(h > 0); 220 221 BEGIN_BATCH(6, NO_LOOP_CLIPRECTS); 222 OUT_BATCH(CMD); 223 OUT_BATCH(BR13 | dst_pitch); 224 OUT_BATCH((y << 16) | x); 225 OUT_BATCH(((y + h) << 16) | (x + w)); 226 OUT_RELOC(dst_buffer, 227 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 228 dst_offset); 229 OUT_BATCH(color); 230 ADVANCE_BATCH(); 231} 232 233static GLuint translate_raster_op(GLenum logicop) 234{ 235 switch(logicop) { 236 case GL_CLEAR: return 0x00; 237 case GL_AND: return 0x88; 238 case GL_AND_REVERSE: return 0x44; 239 case GL_COPY: return 0xCC; 240 case GL_AND_INVERTED: return 0x22; 241 case GL_NOOP: return 0xAA; 242 case GL_XOR: return 0x66; 243 case GL_OR: return 0xEE; 244 case GL_NOR: return 0x11; 245 case GL_EQUIV: return 0x99; 246 case GL_INVERT: return 0x55; 247 case GL_OR_REVERSE: return 0xDD; 248 case GL_COPY_INVERTED: return 0x33; 249 case GL_OR_INVERTED: return 0xBB; 250 case GL_NAND: return 0x77; 251 case GL_SET: return 0xFF; 252 default: return 0; 253 } 254} 255 256 257/* Copy BitBlt 258 */ 259void 260intelEmitCopyBlit(struct intel_context *intel, 261 GLuint cpp, 262 GLshort src_pitch, 263 dri_bo *src_buffer, 264 GLuint src_offset, 265 uint32_t src_tiling, 266 GLshort dst_pitch, 267 dri_bo *dst_buffer, 268 GLuint dst_offset, 269 uint32_t dst_tiling, 270 GLshort src_x, GLshort src_y, 271 GLshort dst_x, GLshort dst_y, 272 GLshort w, GLshort h, 273 GLenum logic_op) 274{ 275 GLuint CMD, BR13, pass = 0; 276 int dst_y2 = dst_y + h; 277 int dst_x2 = dst_x + w; 278 dri_bo *aper_array[3]; 279 BATCH_LOCALS; 280 281 /* do space/cliprects check before going any further */ 282 do { 283 aper_array[0] = intel->batch->buf; 284 aper_array[1] = dst_buffer; 285 aper_array[2] = src_buffer; 286 287 if (dri_bufmgr_check_aperture_space(aper_array, 3) != 0) { 288 intel_batchbuffer_flush(intel->batch); 289 pass++; 290 } else 291 break; 292 } while (pass < 2); 293 294 if (pass >= 2) { 295 GLboolean locked = GL_FALSE; 296 if (!intel->locked) { 297 LOCK_HARDWARE(intel); 298 locked = GL_TRUE; 299 } 300 301 dri_bo_map(dst_buffer, GL_TRUE); 302 dri_bo_map(src_buffer, GL_FALSE); 303 _mesa_copy_rect((GLubyte *)dst_buffer->virtual + dst_offset, 304 cpp, 305 dst_pitch, 306 dst_x, dst_y, 307 w, h, 308 (GLubyte *)src_buffer->virtual + src_offset, 309 src_pitch, 310 src_x, src_y); 311 312 dri_bo_unmap(src_buffer); 313 dri_bo_unmap(dst_buffer); 314 315 if (locked) 316 UNLOCK_HARDWARE(intel); 317 318 return; 319 } 320 321 intel_batchbuffer_require_space(intel->batch, 8 * 4, NO_LOOP_CLIPRECTS); 322 DBG("%s src:buf(%p)/%d+%d %d,%d dst:buf(%p)/%d+%d %d,%d sz:%dx%d\n", 323 __FUNCTION__, 324 src_buffer, src_pitch, src_offset, src_x, src_y, 325 dst_buffer, dst_pitch, dst_offset, dst_x, dst_y, w, h); 326 327 src_pitch *= cpp; 328 dst_pitch *= cpp; 329 330 BR13 = translate_raster_op(logic_op) << 16; 331 332 switch (cpp) { 333 case 1: 334 case 2: 335 case 3: 336 BR13 |= (1 << 24); 337 CMD = XY_SRC_COPY_BLT_CMD; 338 break; 339 case 4: 340 BR13 |= (1 << 24) | (1 << 25); 341 CMD = XY_SRC_COPY_BLT_CMD | XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB; 342 break; 343 default: 344 return; 345 } 346 347#ifndef I915 348 if (dst_tiling != I915_TILING_NONE) { 349 CMD |= XY_DST_TILED; 350 dst_pitch /= 4; 351 } 352 if (src_tiling != I915_TILING_NONE) { 353 CMD |= XY_SRC_TILED; 354 src_pitch /= 4; 355 } 356#endif 357 358 if (dst_y2 <= dst_y || dst_x2 <= dst_x) { 359 return; 360 } 361 362 /* Initial y values don't seem to work with negative pitches. If 363 * we adjust the offsets manually (below), it seems to work fine. 364 * 365 * On the other hand, if we always adjust, the hardware doesn't 366 * know which blit directions to use, so overlapping copypixels get 367 * the wrong result. 368 */ 369 if (dst_pitch > 0 && src_pitch > 0) { 370 assert(dst_x < dst_x2); 371 assert(dst_y < dst_y2); 372 373 BEGIN_BATCH(8, NO_LOOP_CLIPRECTS); 374 OUT_BATCH(CMD); 375 OUT_BATCH(BR13 | dst_pitch); 376 OUT_BATCH((dst_y << 16) | dst_x); 377 OUT_BATCH((dst_y2 << 16) | dst_x2); 378 OUT_RELOC(dst_buffer, 379 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 380 dst_offset); 381 OUT_BATCH((src_y << 16) | src_x); 382 OUT_BATCH(src_pitch); 383 OUT_RELOC(src_buffer, 384 I915_GEM_DOMAIN_RENDER, 0, 385 src_offset); 386 ADVANCE_BATCH(); 387 } 388 else { 389 assert(dst_x < dst_x2); 390 assert(h > 0); 391 392 BEGIN_BATCH(8, NO_LOOP_CLIPRECTS); 393 OUT_BATCH(CMD); 394 OUT_BATCH(BR13 | ((uint16_t)dst_pitch)); 395 OUT_BATCH((0 << 16) | dst_x); 396 OUT_BATCH((h << 16) | dst_x2); 397 OUT_RELOC(dst_buffer, 398 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 399 dst_offset + dst_y * dst_pitch); 400 OUT_BATCH((0 << 16) | src_x); 401 OUT_BATCH(src_pitch); 402 OUT_RELOC(src_buffer, 403 I915_GEM_DOMAIN_RENDER, 0, 404 src_offset + src_y * src_pitch); 405 ADVANCE_BATCH(); 406 } 407 intel_batchbuffer_emit_mi_flush(intel->batch); 408} 409 410 411/** 412 * Use blitting to clear the renderbuffers named by 'flags'. 413 * Note: we can't use the ctx->DrawBuffer->_ColorDrawBufferIndexes field 414 * since that might include software renderbuffers or renderbuffers 415 * which we're clearing with triangles. 416 * \param mask bitmask of BUFFER_BIT_* values indicating buffers to clear 417 */ 418void 419intelClearWithBlit(GLcontext *ctx, GLbitfield mask) 420{ 421 struct intel_context *intel = intel_context(ctx); 422 struct gl_framebuffer *fb = ctx->DrawBuffer; 423 GLuint clear_depth; 424 GLbitfield skipBuffers = 0; 425 unsigned int num_cliprects; 426 struct drm_clip_rect *cliprects; 427 int x_off, y_off; 428 BATCH_LOCALS; 429 430 /* 431 * Compute values for clearing the buffers. 432 */ 433 clear_depth = 0; 434 if (mask & BUFFER_BIT_DEPTH) { 435 clear_depth = (GLuint) (fb->_DepthMax * ctx->Depth.Clear); 436 } 437 if (mask & BUFFER_BIT_STENCIL) { 438 clear_depth |= (ctx->Stencil.Clear & 0xff) << 24; 439 } 440 441 /* If clearing both depth and stencil, skip BUFFER_BIT_STENCIL in 442 * the loop below. 443 */ 444 if ((mask & BUFFER_BIT_DEPTH) && (mask & BUFFER_BIT_STENCIL)) { 445 skipBuffers = BUFFER_BIT_STENCIL; 446 } 447 448 /* XXX Move this flush/lock into the following conditional? */ 449 intelFlush(&intel->ctx); 450 LOCK_HARDWARE(intel); 451 452 intel_get_cliprects(intel, &cliprects, &num_cliprects, &x_off, &y_off); 453 if (num_cliprects) { 454 GLint cx, cy, cw, ch; 455 drm_clip_rect_t clear; 456 int i; 457 458 /* Get clear bounds after locking */ 459 cx = fb->_Xmin; 460 cy = fb->_Ymin; 461 cw = fb->_Xmax - cx; 462 ch = fb->_Ymax - cy; 463 464 if (fb->Name == 0) { 465 /* clearing a window */ 466 467 /* flip top to bottom */ 468 clear.x1 = cx + x_off; 469 clear.y1 = intel->driDrawable->y + intel->driDrawable->h - cy - ch; 470 clear.x2 = clear.x1 + cw; 471 clear.y2 = clear.y1 + ch; 472 } 473 else { 474 /* clearing FBO */ 475 assert(num_cliprects == 1); 476 assert(cliprects == &intel->fboRect); 477 clear.x1 = cx; 478 clear.y1 = cy; 479 clear.x2 = clear.x1 + cw; 480 clear.y2 = clear.y1 + ch; 481 /* no change to mask */ 482 } 483 484 for (i = 0; i < num_cliprects; i++) { 485 const drm_clip_rect_t *box = &cliprects[i]; 486 drm_clip_rect_t b; 487 GLuint buf; 488 GLuint clearMask = mask; /* use copy, since we modify it below */ 489 GLboolean all = (cw == fb->Width && ch == fb->Height); 490 491 if (!all) { 492 intel_intersect_cliprects(&b, &clear, box); 493 } 494 else { 495 b = *box; 496 } 497 498 if (b.x1 >= b.x2 || b.y1 >= b.y2) 499 continue; 500 501 if (0) 502 _mesa_printf("clear %d,%d..%d,%d, mask %x\n", 503 b.x1, b.y1, b.x2, b.y2, mask); 504 505 /* Loop over all renderbuffers */ 506 for (buf = 0; buf < BUFFER_COUNT && clearMask; buf++) { 507 const GLbitfield bufBit = 1 << buf; 508 if ((clearMask & bufBit) && !(bufBit & skipBuffers)) { 509 /* OK, clear this renderbuffer */ 510 struct intel_region *irb_region = 511 intel_get_rb_region(fb, buf); 512 dri_bo *write_buffer = 513 intel_region_buffer(intel, irb_region, 514 all ? INTEL_WRITE_FULL : 515 INTEL_WRITE_PART); 516 517 GLuint clearVal; 518 GLint pitch, cpp; 519 GLuint BR13, CMD; 520 521 ASSERT(irb_region); 522 523 pitch = irb_region->pitch; 524 cpp = irb_region->cpp; 525 526 DBG("%s dst:buf(%p)/%d+%d %d,%d sz:%dx%d\n", 527 __FUNCTION__, 528 irb_region->buffer, (pitch * cpp), 529 irb_region->draw_offset, 530 b.x1, b.y1, b.x2 - b.x1, b.y2 - b.y1); 531 532 BR13 = 0xf0 << 16; 533 CMD = XY_COLOR_BLT_CMD; 534 535 /* Setup the blit command */ 536 if (cpp == 4) { 537 BR13 |= (1 << 24) | (1 << 25); 538 if (buf == BUFFER_DEPTH || buf == BUFFER_STENCIL) { 539 if (clearMask & BUFFER_BIT_DEPTH) 540 CMD |= XY_BLT_WRITE_RGB; 541 if (clearMask & BUFFER_BIT_STENCIL) 542 CMD |= XY_BLT_WRITE_ALPHA; 543 } 544 else { 545 /* clearing RGBA */ 546 CMD |= XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB; 547 } 548 } 549 else { 550 ASSERT(cpp == 2 || cpp == 0); 551 BR13 |= (1 << 24); 552 } 553 554#ifndef I915 555 if (irb_region->tiling != I915_TILING_NONE) { 556 CMD |= XY_DST_TILED; 557 pitch /= 4; 558 } 559#endif 560 BR13 |= (pitch * cpp); 561 562 if (buf == BUFFER_DEPTH || buf == BUFFER_STENCIL) { 563 clearVal = clear_depth; 564 } 565 else { 566 clearVal = (cpp == 4) 567 ? intel->ClearColor8888 : intel->ClearColor565; 568 } 569 /* 570 _mesa_debug(ctx, "hardware blit clear buf %d rb id %d\n", 571 buf, irb->Base.Name); 572 */ 573 intel_wait_flips(intel); 574 575 assert(b.x1 < b.x2); 576 assert(b.y1 < b.y2); 577 578 BEGIN_BATCH(6, REFERENCES_CLIPRECTS); 579 OUT_BATCH(CMD); 580 OUT_BATCH(BR13); 581 OUT_BATCH((b.y1 << 16) | b.x1); 582 OUT_BATCH((b.y2 << 16) | b.x2); 583 OUT_RELOC(write_buffer, 584 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 585 irb_region->draw_offset); 586 OUT_BATCH(clearVal); 587 ADVANCE_BATCH(); 588 clearMask &= ~bufBit; /* turn off bit, for faster loop exit */ 589 } 590 } 591 } 592 intel_batchbuffer_emit_mi_flush(intel->batch); 593 } 594 595 UNLOCK_HARDWARE(intel); 596} 597 598void 599intelEmitImmediateColorExpandBlit(struct intel_context *intel, 600 GLuint cpp, 601 GLubyte *src_bits, GLuint src_size, 602 GLuint fg_color, 603 GLshort dst_pitch, 604 dri_bo *dst_buffer, 605 GLuint dst_offset, 606 uint32_t dst_tiling, 607 GLshort x, GLshort y, 608 GLshort w, GLshort h, 609 GLenum logic_op) 610{ 611 int dwords = ALIGN(src_size, 8) / 4; 612 uint32_t opcode, br13, blit_cmd; 613 614 assert( logic_op - GL_CLEAR >= 0 ); 615 assert( logic_op - GL_CLEAR < 0x10 ); 616 617 if (w < 0 || h < 0) 618 return; 619 620 dst_pitch *= cpp; 621 622 DBG("%s dst:buf(%p)/%d+%d %d,%d sz:%dx%d, %d bytes %d dwords\n", 623 __FUNCTION__, 624 dst_buffer, dst_pitch, dst_offset, x, y, w, h, src_size, dwords); 625 626 intel_batchbuffer_require_space( intel->batch, 627 (8 * 4) + 628 (3 * 4) + 629 dwords, 630 REFERENCES_CLIPRECTS ); 631 632 opcode = XY_SETUP_BLT_CMD; 633 if (cpp == 4) 634 opcode |= XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB; 635#ifndef I915 636 if (dst_tiling != I915_TILING_NONE) { 637 opcode |= XY_DST_TILED; 638 dst_pitch /= 4; 639 } 640#endif 641 642 br13 = dst_pitch | (translate_raster_op(logic_op) << 16) | (1 << 29); 643 if (cpp == 2) 644 br13 |= BR13_565; 645 else 646 br13 |= BR13_8888; 647 648 blit_cmd = XY_TEXT_IMMEDIATE_BLIT_CMD | XY_TEXT_BYTE_PACKED; /* packing? */ 649 if (dst_tiling != I915_TILING_NONE) 650 blit_cmd |= XY_DST_TILED; 651 652 BEGIN_BATCH(8 + 3, REFERENCES_CLIPRECTS); 653 OUT_BATCH(opcode); 654 OUT_BATCH(br13); 655 OUT_BATCH((0 << 16) | 0); /* clip x1, y1 */ 656 OUT_BATCH((100 << 16) | 100); /* clip x2, y2 */ 657 OUT_RELOC(dst_buffer, 658 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 659 dst_offset); 660 OUT_BATCH(0); /* bg */ 661 OUT_BATCH(fg_color); /* fg */ 662 OUT_BATCH(0); /* pattern base addr */ 663 664 OUT_BATCH(blit_cmd | ((3 - 2) + dwords)); 665 OUT_BATCH((y << 16) | x); 666 OUT_BATCH(((y + h) << 16) | (x + w)); 667 ADVANCE_BATCH(); 668 669 intel_batchbuffer_data( intel->batch, 670 src_bits, 671 dwords * 4, 672 REFERENCES_CLIPRECTS ); 673 674 intel_batchbuffer_emit_mi_flush(intel->batch); 675} 676