1//===- EDEmitter.cpp - Generate instruction descriptions for ED -*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This tablegen backend is responsible for emitting a description of each
11// instruction in a format that the enhanced disassembler can use to tokenize
12// and parse instructions.
13//
14//===----------------------------------------------------------------------===//
15
16#include "EDEmitter.h"
17
18#include "AsmWriterInst.h"
19#include "CodeGenTarget.h"
20
21#include "llvm/TableGen/Record.h"
22#include "llvm/MC/EDInstInfo.h"
23#include "llvm/Support/ErrorHandling.h"
24#include "llvm/Support/Format.h"
25#include "llvm/Support/raw_ostream.h"
26
27#include <string>
28#include <vector>
29
30using namespace llvm;
31
32///////////////////////////////////////////////////////////
33// Support classes for emitting nested C data structures //
34///////////////////////////////////////////////////////////
35
36namespace {
37
38  class EnumEmitter {
39  private:
40    std::string Name;
41    std::vector<std::string> Entries;
42  public:
43    EnumEmitter(const char *N) : Name(N) {
44    }
45    int addEntry(const char *e) {
46      Entries.push_back(std::string(e));
47      return Entries.size() - 1;
48    }
49    void emit(raw_ostream &o, unsigned int &i) {
50      o.indent(i) << "enum " << Name.c_str() << " {" << "\n";
51      i += 2;
52
53      unsigned int index = 0;
54      unsigned int numEntries = Entries.size();
55      for (index = 0; index < numEntries; ++index) {
56        o.indent(i) << Entries[index];
57        if (index < (numEntries - 1))
58          o << ",";
59        o << "\n";
60      }
61
62      i -= 2;
63      o.indent(i) << "};" << "\n";
64    }
65
66    void emitAsFlags(raw_ostream &o, unsigned int &i) {
67      o.indent(i) << "enum " << Name.c_str() << " {" << "\n";
68      i += 2;
69
70      unsigned int index = 0;
71      unsigned int numEntries = Entries.size();
72      unsigned int flag = 1;
73      for (index = 0; index < numEntries; ++index) {
74        o.indent(i) << Entries[index] << " = " << format("0x%x", flag);
75        if (index < (numEntries - 1))
76          o << ",";
77        o << "\n";
78        flag <<= 1;
79      }
80
81      i -= 2;
82      o.indent(i) << "};" << "\n";
83    }
84  };
85
86  class ConstantEmitter {
87  public:
88    virtual ~ConstantEmitter() { }
89    virtual void emit(raw_ostream &o, unsigned int &i) = 0;
90  };
91
92  class LiteralConstantEmitter : public ConstantEmitter {
93  private:
94    bool IsNumber;
95    union {
96      int Number;
97      const char* String;
98    };
99  public:
100    LiteralConstantEmitter(int number = 0) :
101      IsNumber(true),
102      Number(number) {
103    }
104    void set(const char *string) {
105      IsNumber = false;
106      Number = 0;
107      String = string;
108    }
109    bool is(const char *string) {
110      return !strcmp(String, string);
111    }
112    void emit(raw_ostream &o, unsigned int &i) {
113      if (IsNumber)
114        o << Number;
115      else
116        o << String;
117    }
118  };
119
120  class CompoundConstantEmitter : public ConstantEmitter {
121  private:
122    unsigned int Padding;
123    std::vector<ConstantEmitter *> Entries;
124  public:
125    CompoundConstantEmitter(unsigned int padding = 0) : Padding(padding) {
126    }
127    CompoundConstantEmitter &addEntry(ConstantEmitter *e) {
128      Entries.push_back(e);
129
130      return *this;
131    }
132    ~CompoundConstantEmitter() {
133      while (Entries.size()) {
134        ConstantEmitter *entry = Entries.back();
135        Entries.pop_back();
136        delete entry;
137      }
138    }
139    void emit(raw_ostream &o, unsigned int &i) {
140      o << "{" << "\n";
141      i += 2;
142
143      unsigned int index;
144      unsigned int numEntries = Entries.size();
145
146      unsigned int numToPrint;
147
148      if (Padding) {
149        if (numEntries > Padding) {
150          fprintf(stderr, "%u entries but %u padding\n", numEntries, Padding);
151          llvm_unreachable("More entries than padding");
152        }
153        numToPrint = Padding;
154      } else {
155        numToPrint = numEntries;
156      }
157
158      for (index = 0; index < numToPrint; ++index) {
159        o.indent(i);
160        if (index < numEntries)
161          Entries[index]->emit(o, i);
162        else
163          o << "-1";
164
165        if (index < (numToPrint - 1))
166          o << ",";
167        o << "\n";
168      }
169
170      i -= 2;
171      o.indent(i) << "}";
172    }
173  };
174
175  class FlagsConstantEmitter : public ConstantEmitter {
176  private:
177    std::vector<std::string> Flags;
178  public:
179    FlagsConstantEmitter() {
180    }
181    FlagsConstantEmitter &addEntry(const char *f) {
182      Flags.push_back(std::string(f));
183      return *this;
184    }
185    void emit(raw_ostream &o, unsigned int &i) {
186      unsigned int index;
187      unsigned int numFlags = Flags.size();
188      if (numFlags == 0)
189        o << "0";
190
191      for (index = 0; index < numFlags; ++index) {
192        o << Flags[index].c_str();
193        if (index < (numFlags - 1))
194          o << " | ";
195      }
196    }
197  };
198}
199
200EDEmitter::EDEmitter(RecordKeeper &R) : Records(R) {
201}
202
203/// populateOperandOrder - Accepts a CodeGenInstruction and generates its
204///   AsmWriterInst for the desired assembly syntax, giving an ordered list of
205///   operands in the order they appear in the printed instruction.  Then, for
206///   each entry in that list, determines the index of the same operand in the
207///   CodeGenInstruction, and emits the resulting mapping into an array, filling
208///   in unused slots with -1.
209///
210/// @arg operandOrder - The array that will be populated with the operand
211///                     mapping.  Each entry will contain -1 (invalid index
212///                     into the operands present in the AsmString) or a number
213///                     representing an index in the operand descriptor array.
214/// @arg inst         - The instruction to use when looking up the operands
215/// @arg syntax       - The syntax to use, according to LLVM's enumeration
216void populateOperandOrder(CompoundConstantEmitter *operandOrder,
217                          const CodeGenInstruction &inst,
218                          unsigned syntax) {
219  unsigned int numArgs = 0;
220
221  AsmWriterInst awInst(inst, syntax, -1, -1);
222
223  std::vector<AsmWriterOperand>::iterator operandIterator;
224
225  for (operandIterator = awInst.Operands.begin();
226       operandIterator != awInst.Operands.end();
227       ++operandIterator) {
228    if (operandIterator->OperandType ==
229        AsmWriterOperand::isMachineInstrOperand) {
230      operandOrder->addEntry(
231        new LiteralConstantEmitter(operandIterator->CGIOpNo));
232      numArgs++;
233    }
234  }
235}
236
237/////////////////////////////////////////////////////
238// Support functions for handling X86 instructions //
239/////////////////////////////////////////////////////
240
241#define SET(flag) { type->set(flag); return 0; }
242
243#define REG(str) if (name == str) SET("kOperandTypeRegister");
244#define MEM(str) if (name == str) SET("kOperandTypeX86Memory");
245#define LEA(str) if (name == str) SET("kOperandTypeX86EffectiveAddress");
246#define IMM(str) if (name == str) SET("kOperandTypeImmediate");
247#define PCR(str) if (name == str) SET("kOperandTypeX86PCRelative");
248
249/// X86TypeFromOpName - Processes the name of a single X86 operand (which is
250///   actually its type) and translates it into an operand type
251///
252/// @arg flags    - The type object to set
253/// @arg name     - The name of the operand
254static int X86TypeFromOpName(LiteralConstantEmitter *type,
255                             const std::string &name) {
256  REG("GR8");
257  REG("GR8_NOREX");
258  REG("GR16");
259  REG("GR16_NOAX");
260  REG("GR32");
261  REG("GR32_NOAX");
262  REG("GR32_NOREX");
263  REG("GR32_TC");
264  REG("FR32");
265  REG("RFP32");
266  REG("GR64");
267  REG("GR64_NOAX");
268  REG("GR64_TC");
269  REG("FR64");
270  REG("VR64");
271  REG("RFP64");
272  REG("RFP80");
273  REG("VR128");
274  REG("VR256");
275  REG("RST");
276  REG("SEGMENT_REG");
277  REG("DEBUG_REG");
278  REG("CONTROL_REG");
279
280  IMM("i8imm");
281  IMM("i16imm");
282  IMM("i16i8imm");
283  IMM("i32imm");
284  IMM("i32i8imm");
285  IMM("u32u8imm");
286  IMM("i64imm");
287  IMM("i64i8imm");
288  IMM("i64i32imm");
289  IMM("SSECC");
290
291  // all R, I, R, I, R
292  MEM("i8mem");
293  MEM("i8mem_NOREX");
294  MEM("i16mem");
295  MEM("i32mem");
296  MEM("i32mem_TC");
297  MEM("f32mem");
298  MEM("ssmem");
299  MEM("opaque32mem");
300  MEM("opaque48mem");
301  MEM("i64mem");
302  MEM("i64mem_TC");
303  MEM("f64mem");
304  MEM("sdmem");
305  MEM("f80mem");
306  MEM("opaque80mem");
307  MEM("i128mem");
308  MEM("i256mem");
309  MEM("f128mem");
310  MEM("f256mem");
311  MEM("opaque512mem");
312
313  // all R, I, R, I
314  LEA("lea32mem");
315  LEA("lea64_32mem");
316  LEA("lea64mem");
317
318  // all I
319  PCR("i16imm_pcrel");
320  PCR("i32imm_pcrel");
321  PCR("i64i32imm_pcrel");
322  PCR("brtarget8");
323  PCR("offset8");
324  PCR("offset16");
325  PCR("offset32");
326  PCR("offset64");
327  PCR("brtarget");
328  PCR("uncondbrtarget");
329  PCR("bltarget");
330
331  // all I, ARM mode only, conditional/unconditional
332  PCR("br_target");
333  PCR("bl_target");
334  return 1;
335}
336
337#undef REG
338#undef MEM
339#undef LEA
340#undef IMM
341#undef PCR
342
343#undef SET
344
345/// X86PopulateOperands - Handles all the operands in an X86 instruction, adding
346///   the appropriate flags to their descriptors
347///
348/// @operandFlags - A reference the array of operand flag objects
349/// @inst         - The instruction to use as a source of information
350static void X86PopulateOperands(
351  LiteralConstantEmitter *(&operandTypes)[EDIS_MAX_OPERANDS],
352  const CodeGenInstruction &inst) {
353  if (!inst.TheDef->isSubClassOf("X86Inst"))
354    return;
355
356  unsigned int index;
357  unsigned int numOperands = inst.Operands.size();
358
359  for (index = 0; index < numOperands; ++index) {
360    const CGIOperandList::OperandInfo &operandInfo = inst.Operands[index];
361    Record &rec = *operandInfo.Rec;
362
363    if (X86TypeFromOpName(operandTypes[index], rec.getName()) &&
364        !rec.isSubClassOf("PointerLikeRegClass")) {
365      errs() << "Operand type: " << rec.getName().c_str() << "\n";
366      errs() << "Operand name: " << operandInfo.Name.c_str() << "\n";
367      errs() << "Instruction name: " << inst.TheDef->getName().c_str() << "\n";
368      llvm_unreachable("Unhandled type");
369    }
370  }
371}
372
373/// decorate1 - Decorates a named operand with a new flag
374///
375/// @operandFlags - The array of operand flag objects, which don't have names
376/// @inst         - The CodeGenInstruction, which provides a way to translate
377///                 between names and operand indices
378/// @opName       - The name of the operand
379/// @flag         - The name of the flag to add
380static inline void decorate1(
381  FlagsConstantEmitter *(&operandFlags)[EDIS_MAX_OPERANDS],
382  const CodeGenInstruction &inst,
383  const char *opName,
384  const char *opFlag) {
385  unsigned opIndex;
386
387  opIndex = inst.Operands.getOperandNamed(std::string(opName));
388
389  operandFlags[opIndex]->addEntry(opFlag);
390}
391
392#define DECORATE1(opName, opFlag) decorate1(operandFlags, inst, opName, opFlag)
393
394#define MOV(source, target) {               \
395  instType.set("kInstructionTypeMove");     \
396  DECORATE1(source, "kOperandFlagSource");  \
397  DECORATE1(target, "kOperandFlagTarget");  \
398}
399
400#define BRANCH(target) {                    \
401  instType.set("kInstructionTypeBranch");   \
402  DECORATE1(target, "kOperandFlagTarget");  \
403}
404
405#define PUSH(source) {                      \
406  instType.set("kInstructionTypePush");     \
407  DECORATE1(source, "kOperandFlagSource");  \
408}
409
410#define POP(target) {                       \
411  instType.set("kInstructionTypePop");      \
412  DECORATE1(target, "kOperandFlagTarget");  \
413}
414
415#define CALL(target) {                      \
416  instType.set("kInstructionTypeCall");     \
417  DECORATE1(target, "kOperandFlagTarget");  \
418}
419
420#define RETURN() {                          \
421  instType.set("kInstructionTypeReturn");   \
422}
423
424/// X86ExtractSemantics - Performs various checks on the name of an X86
425///   instruction to determine what sort of an instruction it is and then adds
426///   the appropriate flags to the instruction and its operands
427///
428/// @arg instType     - A reference to the type for the instruction as a whole
429/// @arg operandFlags - A reference to the array of operand flag object pointers
430/// @arg inst         - A reference to the original instruction
431static void X86ExtractSemantics(
432  LiteralConstantEmitter &instType,
433  FlagsConstantEmitter *(&operandFlags)[EDIS_MAX_OPERANDS],
434  const CodeGenInstruction &inst) {
435  const std::string &name = inst.TheDef->getName();
436
437  if (name.find("MOV") != name.npos) {
438    if (name.find("MOV_V") != name.npos) {
439      // ignore (this is a pseudoinstruction)
440    } else if (name.find("MASK") != name.npos) {
441      // ignore (this is a masking move)
442    } else if (name.find("r0") != name.npos) {
443      // ignore (this is a pseudoinstruction)
444    } else if (name.find("PS") != name.npos ||
445             name.find("PD") != name.npos) {
446      // ignore (this is a shuffling move)
447    } else if (name.find("MOVS") != name.npos) {
448      // ignore (this is a string move)
449    } else if (name.find("_F") != name.npos) {
450      // TODO handle _F moves to ST(0)
451    } else if (name.find("a") != name.npos) {
452      // TODO handle moves to/from %ax
453    } else if (name.find("CMOV") != name.npos) {
454      MOV("src2", "dst");
455    } else if (name.find("PC") != name.npos) {
456      MOV("label", "reg")
457    } else {
458      MOV("src", "dst");
459    }
460  }
461
462  if (name.find("JMP") != name.npos ||
463      name.find("J") == 0) {
464    if (name.find("FAR") != name.npos && name.find("i") != name.npos) {
465      BRANCH("off");
466    } else {
467      BRANCH("dst");
468    }
469  }
470
471  if (name.find("PUSH") != name.npos) {
472    if (name.find("CS") != name.npos ||
473        name.find("DS") != name.npos ||
474        name.find("ES") != name.npos ||
475        name.find("FS") != name.npos ||
476        name.find("GS") != name.npos ||
477        name.find("SS") != name.npos) {
478      instType.set("kInstructionTypePush");
479      // TODO add support for fixed operands
480    } else if (name.find("F") != name.npos) {
481      // ignore (this pushes onto the FP stack)
482    } else if (name.find("A") != name.npos) {
483      // ignore (pushes all GP registoers onto the stack)
484    } else if (name[name.length() - 1] == 'm') {
485      PUSH("src");
486    } else if (name.find("i") != name.npos) {
487      PUSH("imm");
488    } else {
489      PUSH("reg");
490    }
491  }
492
493  if (name.find("POP") != name.npos) {
494    if (name.find("POPCNT") != name.npos) {
495      // ignore (not a real pop)
496    } else if (name.find("CS") != name.npos ||
497               name.find("DS") != name.npos ||
498               name.find("ES") != name.npos ||
499               name.find("FS") != name.npos ||
500               name.find("GS") != name.npos ||
501               name.find("SS") != name.npos) {
502      instType.set("kInstructionTypePop");
503      // TODO add support for fixed operands
504    } else if (name.find("F") != name.npos) {
505      // ignore (this pops from the FP stack)
506    } else if (name.find("A") != name.npos) {
507      // ignore (pushes all GP registoers onto the stack)
508    } else if (name[name.length() - 1] == 'm') {
509      POP("dst");
510    } else {
511      POP("reg");
512    }
513  }
514
515  if (name.find("CALL") != name.npos) {
516    if (name.find("ADJ") != name.npos) {
517      // ignore (not a call)
518    } else if (name.find("SYSCALL") != name.npos) {
519      // ignore (doesn't go anywhere we know about)
520    } else if (name.find("VMCALL") != name.npos) {
521      // ignore (rather different semantics than a regular call)
522    } else if (name.find("FAR") != name.npos && name.find("i") != name.npos) {
523      CALL("off");
524    } else {
525      CALL("dst");
526    }
527  }
528
529  if (name.find("RET") != name.npos) {
530    RETURN();
531  }
532}
533
534#undef MOV
535#undef BRANCH
536#undef PUSH
537#undef POP
538#undef CALL
539#undef RETURN
540
541/////////////////////////////////////////////////////
542// Support functions for handling ARM instructions //
543/////////////////////////////////////////////////////
544
545#define SET(flag) { type->set(flag); return 0; }
546
547#define REG(str)    if (name == str) SET("kOperandTypeRegister");
548#define IMM(str)    if (name == str) SET("kOperandTypeImmediate");
549
550#define MISC(str, type)   if (name == str) SET(type);
551
552/// ARMFlagFromOpName - Processes the name of a single ARM operand (which is
553///   actually its type) and translates it into an operand type
554///
555/// @arg type     - The type object to set
556/// @arg name     - The name of the operand
557static int ARMFlagFromOpName(LiteralConstantEmitter *type,
558                             const std::string &name) {
559  REG("GPR");
560  REG("rGPR");
561  REG("GPRnopc");
562  REG("GPRsp");
563  REG("tcGPR");
564  REG("cc_out");
565  REG("s_cc_out");
566  REG("tGPR");
567  REG("DPR");
568  REG("DPR_VFP2");
569  REG("DPR_8");
570  REG("SPR");
571  REG("QPR");
572  REG("QQPR");
573  REG("QQQQPR");
574
575  IMM("i32imm");
576  IMM("i32imm_hilo16");
577  IMM("bf_inv_mask_imm");
578  IMM("lsb_pos_imm");
579  IMM("width_imm");
580  IMM("jtblock_operand");
581  IMM("nohash_imm");
582  IMM("p_imm");
583  IMM("c_imm");
584  IMM("coproc_option_imm");
585  IMM("imod_op");
586  IMM("iflags_op");
587  IMM("cpinst_operand");
588  IMM("setend_op");
589  IMM("cps_opt");
590  IMM("vfp_f64imm");
591  IMM("vfp_f32imm");
592  IMM("memb_opt");
593  IMM("msr_mask");
594  IMM("neg_zero");
595  IMM("imm0_31");
596  IMM("imm0_31_m1");
597  IMM("imm1_16");
598  IMM("imm1_32");
599  IMM("nModImm");
600  IMM("imm0_7");
601  IMM("imm0_15");
602  IMM("imm0_255");
603  IMM("imm0_4095");
604  IMM("imm0_65535");
605  IMM("imm0_65535_expr");
606  IMM("imm24b");
607  IMM("pkh_lsl_amt");
608  IMM("pkh_asr_amt");
609  IMM("jt2block_operand");
610  IMM("t_imm0_1020s4");
611  IMM("t_imm0_508s4");
612  IMM("pclabel");
613  IMM("adrlabel");
614  IMM("t_adrlabel");
615  IMM("t2adrlabel");
616  IMM("shift_imm");
617  IMM("t2_shift_imm");
618  IMM("neon_vcvt_imm32");
619  IMM("shr_imm8");
620  IMM("shr_imm16");
621  IMM("shr_imm32");
622  IMM("shr_imm64");
623  IMM("t2ldrlabel");
624  IMM("postidx_imm8");
625  IMM("postidx_imm8s4");
626  IMM("imm_sr");
627  IMM("imm1_31");
628  IMM("VectorIndex8");
629  IMM("VectorIndex16");
630  IMM("VectorIndex32");
631
632  MISC("brtarget", "kOperandTypeARMBranchTarget");                // ?
633  MISC("uncondbrtarget", "kOperandTypeARMBranchTarget");           // ?
634  MISC("t_brtarget", "kOperandTypeARMBranchTarget");              // ?
635  MISC("t_bcctarget", "kOperandTypeARMBranchTarget");             // ?
636  MISC("t_cbtarget", "kOperandTypeARMBranchTarget");              // ?
637  MISC("bltarget", "kOperandTypeARMBranchTarget");                // ?
638
639  MISC("br_target", "kOperandTypeARMBranchTarget");                // ?
640  MISC("bl_target", "kOperandTypeARMBranchTarget");                // ?
641  MISC("blx_target", "kOperandTypeARMBranchTarget");                // ?
642
643  MISC("t_bltarget", "kOperandTypeARMBranchTarget");              // ?
644  MISC("t_blxtarget", "kOperandTypeARMBranchTarget");             // ?
645  MISC("so_reg_imm", "kOperandTypeARMSoRegReg");                         // R, R, I
646  MISC("so_reg_reg", "kOperandTypeARMSoRegImm");                         // R, R, I
647  MISC("shift_so_reg_reg", "kOperandTypeARMSoRegReg");                   // R, R, I
648  MISC("shift_so_reg_imm", "kOperandTypeARMSoRegImm");                   // R, R, I
649  MISC("t2_so_reg", "kOperandTypeThumb2SoReg");                   // R, I
650  MISC("so_imm", "kOperandTypeARMSoImm");                         // I
651  MISC("rot_imm", "kOperandTypeARMRotImm");                       // I
652  MISC("t2_so_imm", "kOperandTypeThumb2SoImm");                   // I
653  MISC("so_imm2part", "kOperandTypeARMSoImm2Part");               // I
654  MISC("pred", "kOperandTypeARMPredicate");                       // I, R
655  MISC("it_pred", "kOperandTypeARMPredicate");                    // I
656  MISC("addrmode_imm12", "kOperandTypeAddrModeImm12");            // R, I
657  MISC("ldst_so_reg", "kOperandTypeLdStSOReg");                   // R, R, I
658  MISC("postidx_reg", "kOperandTypeARMAddrMode3Offset");          // R, I
659  MISC("addrmode2", "kOperandTypeARMAddrMode2");                  // R, R, I
660  MISC("am2offset_reg", "kOperandTypeARMAddrMode2Offset");        // R, I
661  MISC("am2offset_imm", "kOperandTypeARMAddrMode2Offset");        // R, I
662  MISC("addrmode3", "kOperandTypeARMAddrMode3");                  // R, R, I
663  MISC("am3offset", "kOperandTypeARMAddrMode3Offset");            // R, I
664  MISC("ldstm_mode", "kOperandTypeARMLdStmMode");                 // I
665  MISC("addrmode5", "kOperandTypeARMAddrMode5");                  // R, I
666  MISC("addrmode6", "kOperandTypeARMAddrMode6");                  // R, R, I, I
667  MISC("am6offset", "kOperandTypeARMAddrMode6Offset");            // R, I, I
668  MISC("addrmode6dup", "kOperandTypeARMAddrMode6");               // R, R, I, I
669  MISC("addrmode6oneL32", "kOperandTypeARMAddrMode6");            // R, R, I, I
670  MISC("addrmodepc", "kOperandTypeARMAddrModePC");                // R, I
671  MISC("addr_offset_none", "kOperandTypeARMAddrMode7");           // R
672  MISC("reglist", "kOperandTypeARMRegisterList");                 // I, R, ...
673  MISC("dpr_reglist", "kOperandTypeARMDPRRegisterList");          // I, R, ...
674  MISC("spr_reglist", "kOperandTypeARMSPRRegisterList");          // I, R, ...
675  MISC("it_mask", "kOperandTypeThumbITMask");                     // I
676  MISC("t2addrmode_reg", "kOperandTypeThumb2AddrModeReg");        // R
677  MISC("t2addrmode_posimm8", "kOperandTypeThumb2AddrModeImm8");   // R, I
678  MISC("t2addrmode_negimm8", "kOperandTypeThumb2AddrModeImm8");   // R, I
679  MISC("t2addrmode_imm8", "kOperandTypeThumb2AddrModeImm8");      // R, I
680  MISC("t2am_imm8_offset", "kOperandTypeThumb2AddrModeImm8Offset");//I
681  MISC("t2addrmode_imm12", "kOperandTypeThumb2AddrModeImm12");    // R, I
682  MISC("t2addrmode_so_reg", "kOperandTypeThumb2AddrModeSoReg");   // R, R, I
683  MISC("t2addrmode_imm8s4", "kOperandTypeThumb2AddrModeImm8s4");  // R, I
684  MISC("t2addrmode_imm0_1020s4", "kOperandTypeThumb2AddrModeImm8s4");  // R, I
685  MISC("t2am_imm8s4_offset", "kOperandTypeThumb2AddrModeImm8s4Offset");
686                                                                  // R, I
687  MISC("tb_addrmode", "kOperandTypeARMTBAddrMode");               // I
688  MISC("t_addrmode_rrs1", "kOperandTypeThumbAddrModeRegS1");      // R, R
689  MISC("t_addrmode_rrs2", "kOperandTypeThumbAddrModeRegS2");      // R, R
690  MISC("t_addrmode_rrs4", "kOperandTypeThumbAddrModeRegS4");      // R, R
691  MISC("t_addrmode_is1", "kOperandTypeThumbAddrModeImmS1");       // R, I
692  MISC("t_addrmode_is2", "kOperandTypeThumbAddrModeImmS2");       // R, I
693  MISC("t_addrmode_is4", "kOperandTypeThumbAddrModeImmS4");       // R, I
694  MISC("t_addrmode_rr", "kOperandTypeThumbAddrModeRR");           // R, R
695  MISC("t_addrmode_sp", "kOperandTypeThumbAddrModeSP");           // R, I
696  MISC("t_addrmode_pc", "kOperandTypeThumbAddrModePC");           // R, I
697  MISC("addrmode_tbb", "kOperandTypeThumbAddrModeRR");            // R, R
698  MISC("addrmode_tbh", "kOperandTypeThumbAddrModeRR");            // R, R
699
700  return 1;
701}
702
703#undef REG
704#undef MEM
705#undef MISC
706
707#undef SET
708
709/// ARMPopulateOperands - Handles all the operands in an ARM instruction, adding
710///   the appropriate flags to their descriptors
711///
712/// @operandFlags - A reference the array of operand flag objects
713/// @inst         - The instruction to use as a source of information
714static void ARMPopulateOperands(
715  LiteralConstantEmitter *(&operandTypes)[EDIS_MAX_OPERANDS],
716  const CodeGenInstruction &inst) {
717  if (!inst.TheDef->isSubClassOf("InstARM") &&
718      !inst.TheDef->isSubClassOf("InstThumb"))
719    return;
720
721  unsigned int index;
722  unsigned int numOperands = inst.Operands.size();
723
724  if (numOperands > EDIS_MAX_OPERANDS) {
725    errs() << "numOperands == " << numOperands << " > " <<
726      EDIS_MAX_OPERANDS << '\n';
727    llvm_unreachable("Too many operands");
728  }
729
730  for (index = 0; index < numOperands; ++index) {
731    const CGIOperandList::OperandInfo &operandInfo = inst.Operands[index];
732    Record &rec = *operandInfo.Rec;
733
734    if (ARMFlagFromOpName(operandTypes[index], rec.getName())) {
735      errs() << "Operand type: " << rec.getName() << '\n';
736      errs() << "Operand name: " << operandInfo.Name << '\n';
737      errs() << "Instruction name: " << inst.TheDef->getName() << '\n';
738      llvm_unreachable("Unhandled type");
739    }
740  }
741}
742
743#define BRANCH(target) {                    \
744  instType.set("kInstructionTypeBranch");   \
745  DECORATE1(target, "kOperandFlagTarget");  \
746}
747
748/// ARMExtractSemantics - Performs various checks on the name of an ARM
749///   instruction to determine what sort of an instruction it is and then adds
750///   the appropriate flags to the instruction and its operands
751///
752/// @arg instType     - A reference to the type for the instruction as a whole
753/// @arg operandTypes - A reference to the array of operand type object pointers
754/// @arg operandFlags - A reference to the array of operand flag object pointers
755/// @arg inst         - A reference to the original instruction
756static void ARMExtractSemantics(
757  LiteralConstantEmitter &instType,
758  LiteralConstantEmitter *(&operandTypes)[EDIS_MAX_OPERANDS],
759  FlagsConstantEmitter *(&operandFlags)[EDIS_MAX_OPERANDS],
760  const CodeGenInstruction &inst) {
761  const std::string &name = inst.TheDef->getName();
762
763  if (name == "tBcc"   ||
764      name == "tB"     ||
765      name == "t2Bcc"  ||
766      name == "Bcc"    ||
767      name == "tCBZ"   ||
768      name == "tCBNZ") {
769    BRANCH("target");
770  }
771
772  if (name == "tBLr9"      ||
773      name == "BLr9_pred"  ||
774      name == "tBLXi_r9"   ||
775      name == "tBLXr_r9"   ||
776      name == "BLXr9"      ||
777      name == "t2BXJ"      ||
778      name == "BXJ") {
779    BRANCH("func");
780
781    unsigned opIndex;
782    opIndex = inst.Operands.getOperandNamed("func");
783    if (operandTypes[opIndex]->is("kOperandTypeImmediate"))
784      operandTypes[opIndex]->set("kOperandTypeARMBranchTarget");
785  }
786}
787
788#undef BRANCH
789
790/// populateInstInfo - Fills an array of InstInfos with information about each
791///   instruction in a target
792///
793/// @arg infoArray  - The array of InstInfo objects to populate
794/// @arg target     - The CodeGenTarget to use as a source of instructions
795static void populateInstInfo(CompoundConstantEmitter &infoArray,
796                             CodeGenTarget &target) {
797  const std::vector<const CodeGenInstruction*> &numberedInstructions =
798    target.getInstructionsByEnumValue();
799
800  unsigned int index;
801  unsigned int numInstructions = numberedInstructions.size();
802
803  for (index = 0; index < numInstructions; ++index) {
804    const CodeGenInstruction& inst = *numberedInstructions[index];
805
806    CompoundConstantEmitter *infoStruct = new CompoundConstantEmitter;
807    infoArray.addEntry(infoStruct);
808
809    LiteralConstantEmitter *instType = new LiteralConstantEmitter;
810    infoStruct->addEntry(instType);
811
812    LiteralConstantEmitter *numOperandsEmitter =
813      new LiteralConstantEmitter(inst.Operands.size());
814    infoStruct->addEntry(numOperandsEmitter);
815
816    CompoundConstantEmitter *operandTypeArray = new CompoundConstantEmitter;
817    infoStruct->addEntry(operandTypeArray);
818
819    LiteralConstantEmitter *operandTypes[EDIS_MAX_OPERANDS];
820
821    CompoundConstantEmitter *operandFlagArray = new CompoundConstantEmitter;
822    infoStruct->addEntry(operandFlagArray);
823
824    FlagsConstantEmitter *operandFlags[EDIS_MAX_OPERANDS];
825
826    for (unsigned operandIndex = 0;
827         operandIndex < EDIS_MAX_OPERANDS;
828         ++operandIndex) {
829      operandTypes[operandIndex] = new LiteralConstantEmitter;
830      operandTypeArray->addEntry(operandTypes[operandIndex]);
831
832      operandFlags[operandIndex] = new FlagsConstantEmitter;
833      operandFlagArray->addEntry(operandFlags[operandIndex]);
834    }
835
836    unsigned numSyntaxes = 0;
837
838    // We don't need to do anything for pseudo-instructions, as we'll never
839    // see them here. We'll only see real instructions.
840    // We still need to emit null initializers for everything.
841    if (!inst.isPseudo) {
842      if (target.getName() == "X86") {
843        X86PopulateOperands(operandTypes, inst);
844        X86ExtractSemantics(*instType, operandFlags, inst);
845        numSyntaxes = 2;
846      }
847      else if (target.getName() == "ARM") {
848        ARMPopulateOperands(operandTypes, inst);
849        ARMExtractSemantics(*instType, operandTypes, operandFlags, inst);
850        numSyntaxes = 1;
851      }
852    }
853
854    CompoundConstantEmitter *operandOrderArray = new CompoundConstantEmitter;
855
856    infoStruct->addEntry(operandOrderArray);
857
858    for (unsigned syntaxIndex = 0;
859         syntaxIndex < EDIS_MAX_SYNTAXES;
860         ++syntaxIndex) {
861      CompoundConstantEmitter *operandOrder =
862        new CompoundConstantEmitter(EDIS_MAX_OPERANDS);
863
864      operandOrderArray->addEntry(operandOrder);
865
866      if (syntaxIndex < numSyntaxes) {
867        populateOperandOrder(operandOrder, inst, syntaxIndex);
868      }
869    }
870
871    infoStruct = NULL;
872  }
873}
874
875static void emitCommonEnums(raw_ostream &o, unsigned int &i) {
876  EnumEmitter operandTypes("OperandTypes");
877  operandTypes.addEntry("kOperandTypeNone");
878  operandTypes.addEntry("kOperandTypeImmediate");
879  operandTypes.addEntry("kOperandTypeRegister");
880  operandTypes.addEntry("kOperandTypeX86Memory");
881  operandTypes.addEntry("kOperandTypeX86EffectiveAddress");
882  operandTypes.addEntry("kOperandTypeX86PCRelative");
883  operandTypes.addEntry("kOperandTypeARMBranchTarget");
884  operandTypes.addEntry("kOperandTypeARMSoRegReg");
885  operandTypes.addEntry("kOperandTypeARMSoRegImm");
886  operandTypes.addEntry("kOperandTypeARMSoImm");
887  operandTypes.addEntry("kOperandTypeARMRotImm");
888  operandTypes.addEntry("kOperandTypeARMSoImm2Part");
889  operandTypes.addEntry("kOperandTypeARMPredicate");
890  operandTypes.addEntry("kOperandTypeAddrModeImm12");
891  operandTypes.addEntry("kOperandTypeLdStSOReg");
892  operandTypes.addEntry("kOperandTypeARMAddrMode2");
893  operandTypes.addEntry("kOperandTypeARMAddrMode2Offset");
894  operandTypes.addEntry("kOperandTypeARMAddrMode3");
895  operandTypes.addEntry("kOperandTypeARMAddrMode3Offset");
896  operandTypes.addEntry("kOperandTypeARMLdStmMode");
897  operandTypes.addEntry("kOperandTypeARMAddrMode5");
898  operandTypes.addEntry("kOperandTypeARMAddrMode6");
899  operandTypes.addEntry("kOperandTypeARMAddrMode6Offset");
900  operandTypes.addEntry("kOperandTypeARMAddrMode7");
901  operandTypes.addEntry("kOperandTypeARMAddrModePC");
902  operandTypes.addEntry("kOperandTypeARMRegisterList");
903  operandTypes.addEntry("kOperandTypeARMDPRRegisterList");
904  operandTypes.addEntry("kOperandTypeARMSPRRegisterList");
905  operandTypes.addEntry("kOperandTypeARMTBAddrMode");
906  operandTypes.addEntry("kOperandTypeThumbITMask");
907  operandTypes.addEntry("kOperandTypeThumbAddrModeImmS1");
908  operandTypes.addEntry("kOperandTypeThumbAddrModeImmS2");
909  operandTypes.addEntry("kOperandTypeThumbAddrModeImmS4");
910  operandTypes.addEntry("kOperandTypeThumbAddrModeRegS1");
911  operandTypes.addEntry("kOperandTypeThumbAddrModeRegS2");
912  operandTypes.addEntry("kOperandTypeThumbAddrModeRegS4");
913  operandTypes.addEntry("kOperandTypeThumbAddrModeRR");
914  operandTypes.addEntry("kOperandTypeThumbAddrModeSP");
915  operandTypes.addEntry("kOperandTypeThumbAddrModePC");
916  operandTypes.addEntry("kOperandTypeThumb2AddrModeReg");
917  operandTypes.addEntry("kOperandTypeThumb2SoReg");
918  operandTypes.addEntry("kOperandTypeThumb2SoImm");
919  operandTypes.addEntry("kOperandTypeThumb2AddrModeImm8");
920  operandTypes.addEntry("kOperandTypeThumb2AddrModeImm8Offset");
921  operandTypes.addEntry("kOperandTypeThumb2AddrModeImm12");
922  operandTypes.addEntry("kOperandTypeThumb2AddrModeSoReg");
923  operandTypes.addEntry("kOperandTypeThumb2AddrModeImm8s4");
924  operandTypes.addEntry("kOperandTypeThumb2AddrModeImm8s4Offset");
925  operandTypes.emit(o, i);
926
927  o << "\n";
928
929  EnumEmitter operandFlags("OperandFlags");
930  operandFlags.addEntry("kOperandFlagSource");
931  operandFlags.addEntry("kOperandFlagTarget");
932  operandFlags.emitAsFlags(o, i);
933
934  o << "\n";
935
936  EnumEmitter instructionTypes("InstructionTypes");
937  instructionTypes.addEntry("kInstructionTypeNone");
938  instructionTypes.addEntry("kInstructionTypeMove");
939  instructionTypes.addEntry("kInstructionTypeBranch");
940  instructionTypes.addEntry("kInstructionTypePush");
941  instructionTypes.addEntry("kInstructionTypePop");
942  instructionTypes.addEntry("kInstructionTypeCall");
943  instructionTypes.addEntry("kInstructionTypeReturn");
944  instructionTypes.emit(o, i);
945
946  o << "\n";
947}
948
949void EDEmitter::run(raw_ostream &o) {
950  unsigned int i = 0;
951
952  CompoundConstantEmitter infoArray;
953  CodeGenTarget target(Records);
954
955  populateInstInfo(infoArray, target);
956
957  emitCommonEnums(o, i);
958
959  o << "namespace {\n";
960
961  o << "llvm::EDInstInfo instInfo" << target.getName().c_str() << "[] = ";
962  infoArray.emit(o, i);
963  o << ";" << "\n";
964
965  o << "}\n";
966}
967