176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* 276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * Definitions for RTL818x hardware 376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * 476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * Copyright 2007 Michael Wu <flamingice@sourmilk.net> 576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * Copyright 2007 Andrea Merello <andreamrl@tiscali.it> 676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * 776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * Modified for gPXE, June 2009, by Joshua Oreman <oremanj@rwcr.net> 876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * 976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * Based on the r8187 driver, which is: 1076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * Copyright 2005 Andrea Merello <andreamrl@tiscali.it>, et al. 1176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * 1276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * This program is free software; you can redistribute it and/or modify 1376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * it under the terms of the GNU General Public License version 2 as 1476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman * published by the Free Software Foundation. 1576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman */ 1676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 1776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#ifndef RTL818X_H 1876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define RTL818X_H 1976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 2076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#include <gpxe/spi_bit.h> 2176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#include <gpxe/tables.h> 2276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 2376d05dc695b06c4e987bb8078f78032441e1430cGreg HartmanFILE_LICENCE(GPL2_ONLY); 2476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 2576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct rtl818x_csr { 2676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman u8 MAC[6]; 2776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman u8 reserved_0[2]; 2876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman u32 MAR[2]; 2976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman u8 RX_FIFO_COUNT; 3076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman u8 reserved_1; 3176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman u8 TX_FIFO_COUNT; 3276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman u8 BQREQ; 3376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman u8 reserved_2[4]; 3476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman u32 TSFT[2]; 3576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman u32 TLPDA; 3676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman u32 TNPDA; 3776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman u32 THPDA; 3876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman u16 BRSR; 3976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman u8 BSSID[6]; 4076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman u8 RESP_RATE; 4176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman u8 EIFS; 4276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman u8 reserved_3[1]; 4376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman u8 CMD; 4476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define RTL818X_CMD_TX_ENABLE (1 << 2) 4576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define RTL818X_CMD_RX_ENABLE (1 << 3) 4676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define RTL818X_CMD_RESET (1 << 4) 4776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman u8 reserved_4[4]; 4876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman u16 INT_MASK; 4976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman u16 INT_STATUS; 5076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define RTL818X_INT_RX_OK (1 << 0) 5176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define RTL818X_INT_RX_ERR (1 << 1) 5276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define RTL818X_INT_TXL_OK (1 << 2) 5376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define RTL818X_INT_TXL_ERR (1 << 3) 5476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define RTL818X_INT_RX_DU (1 << 4) 5576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define RTL818X_INT_RX_FO (1 << 5) 5676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define RTL818X_INT_TXN_OK (1 << 6) 5776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define RTL818X_INT_TXN_ERR (1 << 7) 5876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define RTL818X_INT_TXH_OK (1 << 8) 5976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define RTL818X_INT_TXH_ERR (1 << 9) 6076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define RTL818X_INT_TXB_OK (1 << 10) 6176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define RTL818X_INT_TXB_ERR (1 << 11) 6276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define RTL818X_INT_ATIM (1 << 12) 6376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define RTL818X_INT_BEACON (1 << 13) 6476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define RTL818X_INT_TIME_OUT (1 << 14) 6576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define RTL818X_INT_TX_FO (1 << 15) 6676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman u32 TX_CONF; 6776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define RTL818X_TX_CONF_LOOPBACK_MAC (1 << 17) 6876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define RTL818X_TX_CONF_LOOPBACK_CONT (3 << 17) 6976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define RTL818X_TX_CONF_NO_ICV (1 << 19) 7076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define RTL818X_TX_CONF_DISCW (1 << 20) 7176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define RTL818X_TX_CONF_SAT_HWPLCP (1 << 24) 7276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define RTL818X_TX_CONF_R8180_ABCD (2 << 25) 7376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define RTL818X_TX_CONF_R8180_F (3 << 25) 7476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define RTL818X_TX_CONF_R8185_ABC (4 << 25) 7576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define RTL818X_TX_CONF_R8185_D (5 << 25) 7676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define RTL818X_TX_CONF_R8187vD (5 << 25) 7776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define RTL818X_TX_CONF_R8187vD_B (6 << 25) 7876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define RTL818X_TX_CONF_HWVER_MASK (7 << 25) 7976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define RTL818X_TX_CONF_DISREQQSIZE (1 << 28) 8076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define RTL818X_TX_CONF_PROBE_DTS (1 << 29) 8176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define RTL818X_TX_CONF_HW_SEQNUM (1 << 30) 8276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define RTL818X_TX_CONF_CW_MIN (1 << 31) 8376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman u32 RX_CONF; 8476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define RTL818X_RX_CONF_MONITOR (1 << 0) 8576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define RTL818X_RX_CONF_NICMAC (1 << 1) 8676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define RTL818X_RX_CONF_MULTICAST (1 << 2) 8776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define RTL818X_RX_CONF_BROADCAST (1 << 3) 8876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define RTL818X_RX_CONF_FCS (1 << 5) 8976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define RTL818X_RX_CONF_DATA (1 << 18) 9076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define RTL818X_RX_CONF_CTRL (1 << 19) 9176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define RTL818X_RX_CONF_MGMT (1 << 20) 9276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define RTL818X_RX_CONF_ADDR3 (1 << 21) 9376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define RTL818X_RX_CONF_PM (1 << 22) 9476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define RTL818X_RX_CONF_BSSID (1 << 23) 9576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define RTL818X_RX_CONF_RX_AUTORESETPHY (1 << 28) 9676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define RTL818X_RX_CONF_CSDM1 (1 << 29) 9776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define RTL818X_RX_CONF_CSDM2 (1 << 30) 9876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define RTL818X_RX_CONF_ONLYERLPKT (1 << 31) 9976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman u32 INT_TIMEOUT; 10076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman u32 TBDA; 10176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman u8 EEPROM_CMD; 10276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define RTL818X_EEPROM_CMD_READ (1 << 0) 10376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define RTL818X_EEPROM_CMD_WRITE (1 << 1) 10476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define RTL818X_EEPROM_CMD_CK (1 << 2) 10576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define RTL818X_EEPROM_CMD_CS (1 << 3) 10676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define RTL818X_EEPROM_CMD_NORMAL (0 << 6) 10776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define RTL818X_EEPROM_CMD_LOAD (1 << 6) 10876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define RTL818X_EEPROM_CMD_PROGRAM (2 << 6) 10976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define RTL818X_EEPROM_CMD_CONFIG (3 << 6) 11076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman u8 CONFIG0; 11176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman u8 CONFIG1; 11276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman u8 CONFIG2; 11376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define RTL818X_CONFIG2_ANTENNA_DIV (1 << 6) 11476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman u32 ANAPARAM; 11576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman u8 MSR; 11676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define RTL818X_MSR_NO_LINK (0 << 2) 11776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define RTL818X_MSR_ADHOC (1 << 2) 11876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define RTL818X_MSR_INFRA (2 << 2) 11976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define RTL818X_MSR_MASTER (3 << 2) 12076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define RTL818X_MSR_ENEDCA (4 << 2) 12176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman u8 CONFIG3; 12276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define RTL818X_CONFIG3_ANAPARAM_WRITE (1 << 6) 12376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define RTL818X_CONFIG3_GNT_SELECT (1 << 7) 12476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman u8 CONFIG4; 12576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define RTL818X_CONFIG4_POWEROFF (1 << 6) 12676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define RTL818X_CONFIG4_VCOOFF (1 << 7) 12776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman u8 TESTR; 12876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman u8 reserved_9[2]; 12976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman u8 PGSELECT; 13076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman u8 SECURITY; 13176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman u32 ANAPARAM2; 13276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman u8 reserved_10[12]; 13376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman u16 BEACON_INTERVAL; 13476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman u16 ATIM_WND; 13576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman u16 BEACON_INTERVAL_TIME; 13676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman u16 ATIMTR_INTERVAL; 13776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman u8 PHY_DELAY; 13876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman u8 CARRIER_SENSE_COUNTER; 13976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman u8 reserved_11[2]; 14076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman u8 PHY[4]; 14176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman u16 RFPinsOutput; 14276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman u16 RFPinsEnable; 14376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman u16 RFPinsSelect; 14476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman u16 RFPinsInput; 14576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman u32 RF_PARA; 14676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman u32 RF_TIMING; 14776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman u8 GP_ENABLE; 14876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman u8 GPIO; 14976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman u8 reserved_12[2]; 15076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman u32 HSSI_PARA; 15176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman u8 reserved_13[4]; 15276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman u8 TX_AGC_CTL; 15376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define RTL818X_TX_AGC_CTL_PERPACKET_GAIN_SHIFT (1 << 0) 15476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define RTL818X_TX_AGC_CTL_PERPACKET_ANTSEL_SHIFT (1 << 1) 15576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define RTL818X_TX_AGC_CTL_FEEDBACK_ANT (1 << 2) 15676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman u8 TX_GAIN_CCK; 15776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman u8 TX_GAIN_OFDM; 15876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman u8 TX_ANTENNA; 15976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman u8 reserved_14[16]; 16076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman u8 WPA_CONF; 16176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman u8 reserved_15[3]; 16276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman u8 SIFS; 16376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman u8 DIFS; 16476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman u8 SLOT; 16576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman u8 reserved_16[5]; 16676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman u8 CW_CONF; 16776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define RTL818X_CW_CONF_PERPACKET_CW_SHIFT (1 << 0) 16876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define RTL818X_CW_CONF_PERPACKET_RETRY_SHIFT (1 << 1) 16976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman u8 CW_VAL; 17076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman u8 RATE_FALLBACK; 17176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define RTL818X_RATE_FALLBACK_ENABLE (1 << 7) 17276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman u8 ACM_CONTROL; 17376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman u8 reserved_17[24]; 17476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman u8 CONFIG5; 17576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman u8 TX_DMA_POLLING; 17676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman u8 reserved_18[2]; 17776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman u16 CWR; 17876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman u8 RETRY_CTR; 17976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman u8 reserved_19[3]; 18076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman u16 INT_MIG; 18176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman/* RTL818X_R8187B_*: magic numbers from ioregisters */ 18276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define RTL818X_R8187B_B 0 18376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define RTL818X_R8187B_D 1 18476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define RTL818X_R8187B_E 2 18576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman u32 RDSAR; 18676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman u16 TID_AC_MAP; 18776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman u8 reserved_20[4]; 18876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman u8 ANAPARAM3; 18976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman u8 reserved_21[5]; 19076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman u16 FEMR; 19176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman u8 reserved_22[4]; 19276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman u16 TALLY_CNT; 19376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman u8 TALLY_SEL; 19476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman} __attribute__((packed)); 19576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 19676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define MAX_RX_SIZE IEEE80211_MAX_FRAME_LEN 19776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 19876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define RF_PARAM_ANALOGPHY (1 << 0) 19976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define RF_PARAM_ANTBDEFAULT (1 << 1) 20076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define RF_PARAM_CARRIERSENSE1 (1 << 2) 20176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define RF_PARAM_CARRIERSENSE2 (1 << 3) 20276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 20376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define BB_ANTATTEN_CHAN14 0x0C 20476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define BB_ANTENNA_B 0x40 20576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 20676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define BB_HOST_BANG (1 << 30) 20776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define BB_HOST_BANG_EN (1 << 2) 20876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define BB_HOST_BANG_CLK (1 << 1) 20976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define BB_HOST_BANG_DATA 1 21076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 21176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define ANAPARAM_TXDACOFF_SHIFT 27 21276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define ANAPARAM_PWR0_SHIFT 28 21376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define ANAPARAM_PWR0_MASK (0x07 << ANAPARAM_PWR0_SHIFT) 21476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define ANAPARAM_PWR1_SHIFT 20 21576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define ANAPARAM_PWR1_MASK (0x7F << ANAPARAM_PWR1_SHIFT) 21676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 21776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define RTL818X_RX_RING_SIZE 8 /* doesn't have to be a power of 2 */ 21876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define RTL818X_TX_RING_SIZE 8 /* nor this [but 2^n is very slightly faster] */ 21976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define RTL818X_RING_ALIGN 256 22076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 22176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define RTL818X_MAX_RETRIES 4 22276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 22376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanenum rtl818x_tx_desc_flags { 22476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman RTL818X_TX_DESC_FLAG_NO_ENC = (1 << 15), 22576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman RTL818X_TX_DESC_FLAG_TX_OK = (1 << 15), 22676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman RTL818X_TX_DESC_FLAG_SPLCP = (1 << 16), 22776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman RTL818X_TX_DESC_FLAG_RX_UNDER = (1 << 16), 22876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman RTL818X_TX_DESC_FLAG_MOREFRAG = (1 << 17), 22976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman RTL818X_TX_DESC_FLAG_CTS = (1 << 18), 23076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman RTL818X_TX_DESC_FLAG_RTS = (1 << 23), 23176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman RTL818X_TX_DESC_FLAG_LS = (1 << 28), 23276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman RTL818X_TX_DESC_FLAG_FS = (1 << 29), 23376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman RTL818X_TX_DESC_FLAG_DMA = (1 << 30), 23476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman RTL818X_TX_DESC_FLAG_OWN = (1 << 31) 23576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 23676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 23776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct rtl818x_tx_desc { 23876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman u32 flags; 23976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman u16 rts_duration; 24076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman u16 plcp_len; 24176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman u32 tx_buf; 24276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman u32 frame_len; 24376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman u32 next_tx_desc; 24476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman u8 cw; 24576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman u8 retry_limit; 24676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman u8 agc; 24776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman u8 flags2; 24876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman u32 reserved[2]; 24976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman} __attribute__ ((packed)); 25076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 25176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanenum rtl818x_rx_desc_flags { 25276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman RTL818X_RX_DESC_FLAG_ICV_ERR = (1 << 12), 25376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman RTL818X_RX_DESC_FLAG_CRC32_ERR = (1 << 13), 25476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman RTL818X_RX_DESC_FLAG_PM = (1 << 14), 25576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman RTL818X_RX_DESC_FLAG_RX_ERR = (1 << 15), 25676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman RTL818X_RX_DESC_FLAG_BCAST = (1 << 16), 25776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman RTL818X_RX_DESC_FLAG_PAM = (1 << 17), 25876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman RTL818X_RX_DESC_FLAG_MCAST = (1 << 18), 25976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman RTL818X_RX_DESC_FLAG_QOS = (1 << 19), /* RTL8187(B) only */ 26076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman RTL818X_RX_DESC_FLAG_TRSW = (1 << 24), /* RTL8187(B) only */ 26176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman RTL818X_RX_DESC_FLAG_SPLCP = (1 << 25), 26276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman RTL818X_RX_DESC_FLAG_FOF = (1 << 26), 26376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman RTL818X_RX_DESC_FLAG_DMA_FAIL = (1 << 27), 26476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman RTL818X_RX_DESC_FLAG_LS = (1 << 28), 26576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman RTL818X_RX_DESC_FLAG_FS = (1 << 29), 26676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman RTL818X_RX_DESC_FLAG_EOR = (1 << 30), 26776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman RTL818X_RX_DESC_FLAG_OWN = (1 << 31) 26876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 26976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 27076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct rtl818x_rx_desc { 27176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman u32 flags; 27276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman u32 flags2; 27376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman union { 27476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman u32 rx_buf; 27576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman u64 tsft; 27676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman }; 27776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman} __attribute__ ((packed)); 27876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 27976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct rtl818x_priv { 28076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct rtl818x_csr *map; 28176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman const struct rtl818x_rf_ops *rf; 28276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman int rf_flag; /* whatever RF driver wishes to use it for */ 28376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman int hw_rate; 28476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman int hw_rtscts_rate; 28576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 28676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct spi_bit_basher spibit; 28776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct spi_device eeprom; 28876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 28976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct rtl818x_rx_desc *rx_ring; 29076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman u32 rx_ring_dma; 29176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman unsigned int rx_idx; /* next desc to be filled by card */ 29276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct io_buffer *rx_buf[RTL818X_RX_RING_SIZE]; 29376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 29476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct rtl818x_tx_desc *tx_ring; 29576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman u32 tx_ring_dma; 29676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman unsigned int tx_cons; /* next desc to be filled by card */ 29776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman unsigned int tx_prod; /* next desc to be filled by driver */ 29876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct io_buffer *tx_buf[RTL818X_TX_RING_SIZE]; 29976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 30076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman struct pci_device *pdev; 30176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman u32 rx_conf; 30276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 30376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman u16 txpower[14]; 30476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 30576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman int r8185; 30676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman u32 anaparam; 30776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman u16 rfparam; 30876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman u8 csthreshold; 30976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 31076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 31176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanvoid rtl818x_write_phy(struct net80211_device *dev, u8 addr, u32 data); 31276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanvoid rtl818x_set_anaparam(struct rtl818x_priv *priv, u32 anaparam); 31376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 31476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstatic inline u8 rtl818x_ioread8(struct rtl818x_priv *priv __unused, u8 *addr) 31576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman{ 31676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman return inb(addr); 31776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman} 31876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 31976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstatic inline u16 rtl818x_ioread16(struct rtl818x_priv *priv __unused, u16 *addr) 32076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman{ 32176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman return inw(addr); 32276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman} 32376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 32476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstatic inline u32 rtl818x_ioread32(struct rtl818x_priv *priv __unused, u32 *addr) 32576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman{ 32676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman return inl(addr); 32776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman} 32876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 32976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstatic inline void rtl818x_iowrite8(struct rtl818x_priv *priv __unused, 33076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman u8 *addr, u8 val) 33176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman{ 33276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman outb(val, addr); 33376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman} 33476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 33576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstatic inline void rtl818x_iowrite16(struct rtl818x_priv *priv __unused, 33676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman u16 *addr, u16 val) 33776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman{ 33876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman outw(val, addr); 33976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman} 34076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 34176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstatic inline void rtl818x_iowrite32(struct rtl818x_priv *priv __unused, 34276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman u32 *addr, u32 val) 34376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman{ 34476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman outl(val, addr); 34576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman} 34676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 34776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define RTL818X_RF_DRIVERS __table(struct rtl818x_rf_ops, "rtl818x_rf_drivers") 34876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#define __rtl818x_rf_driver __table_entry(RTL818X_RF_DRIVERS, 01) 34976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 35076d05dc695b06c4e987bb8078f78032441e1430cGreg Hartmanstruct rtl818x_rf_ops { 35176d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman char *name; 35276d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman u8 id; /* as identified in EEPROM */ 35376d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman void (*init)(struct net80211_device *dev); 35476d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman void (*stop)(struct net80211_device *dev); 35576d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman void (*set_chan)(struct net80211_device *dev, struct net80211_channel *chan); 35676d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman void (*conf_erp)(struct net80211_device *dev); /* set based on dev->erp_flags */ 35776d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman}; 35876d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman 35976d05dc695b06c4e987bb8078f78032441e1430cGreg Hartman#endif /* RTL818X_H */ 360