assembler-mips-inl.h revision 958fae7ec3f466955f8e5b50fa5b8d38b9e91675
1 2// Copyright (c) 1994-2006 Sun Microsystems Inc. 3// All Rights Reserved. 4// 5// Redistribution and use in source and binary forms, with or without 6// modification, are permitted provided that the following conditions are 7// met: 8// 9// - Redistributions of source code must retain the above copyright notice, 10// this list of conditions and the following disclaimer. 11// 12// - Redistribution in binary form must reproduce the above copyright 13// notice, this list of conditions and the following disclaimer in the 14// documentation and/or other materials provided with the distribution. 15// 16// - Neither the name of Sun Microsystems or the names of contributors may 17// be used to endorse or promote products derived from this software without 18// specific prior written permission. 19// 20// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS 21// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 22// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 24// CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 25// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 26// PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 27// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 28// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 29// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 30// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 32// The original source code covered by the above license above has been 33// modified significantly by Google Inc. 34// Copyright 2012 the V8 project authors. All rights reserved. 35 36 37#ifndef V8_MIPS_ASSEMBLER_MIPS_INL_H_ 38#define V8_MIPS_ASSEMBLER_MIPS_INL_H_ 39 40#include "src/mips/assembler-mips.h" 41 42#include "src/assembler.h" 43#include "src/debug.h" 44 45 46namespace v8 { 47namespace internal { 48 49 50bool CpuFeatures::SupportsCrankshaft() { return IsSupported(FPU); } 51 52 53// ----------------------------------------------------------------------------- 54// Operand and MemOperand. 55 56Operand::Operand(int32_t immediate, RelocInfo::Mode rmode) { 57 rm_ = no_reg; 58 imm32_ = immediate; 59 rmode_ = rmode; 60} 61 62 63Operand::Operand(const ExternalReference& f) { 64 rm_ = no_reg; 65 imm32_ = reinterpret_cast<int32_t>(f.address()); 66 rmode_ = RelocInfo::EXTERNAL_REFERENCE; 67} 68 69 70Operand::Operand(Smi* value) { 71 rm_ = no_reg; 72 imm32_ = reinterpret_cast<intptr_t>(value); 73 rmode_ = RelocInfo::NONE32; 74} 75 76 77Operand::Operand(Register rm) { 78 rm_ = rm; 79} 80 81 82bool Operand::is_reg() const { 83 return rm_.is_valid(); 84} 85 86 87int Register::NumAllocatableRegisters() { 88 return kMaxNumAllocatableRegisters; 89} 90 91 92int DoubleRegister::NumRegisters() { 93 return FPURegister::kMaxNumRegisters; 94} 95 96 97int DoubleRegister::NumAllocatableRegisters() { 98 return FPURegister::kMaxNumAllocatableRegisters; 99} 100 101 102int DoubleRegister::NumAllocatableAliasedRegisters() { 103 return NumAllocatableRegisters(); 104} 105 106 107int FPURegister::ToAllocationIndex(FPURegister reg) { 108 DCHECK(reg.code() % 2 == 0); 109 DCHECK(reg.code() / 2 < kMaxNumAllocatableRegisters); 110 DCHECK(reg.is_valid()); 111 DCHECK(!reg.is(kDoubleRegZero)); 112 DCHECK(!reg.is(kLithiumScratchDouble)); 113 return (reg.code() / 2); 114} 115 116 117// ----------------------------------------------------------------------------- 118// RelocInfo. 119 120void RelocInfo::apply(intptr_t delta, ICacheFlushMode icache_flush_mode) { 121 if (IsCodeTarget(rmode_)) { 122 uint32_t scope1 = (uint32_t) target_address() & ~kImm28Mask; 123 uint32_t scope2 = reinterpret_cast<uint32_t>(pc_) & ~kImm28Mask; 124 125 if (scope1 != scope2) { 126 Assembler::JumpLabelToJumpRegister(pc_); 127 } 128 } 129 if (IsInternalReference(rmode_)) { 130 // Absolute code pointer inside code object moves with the code object. 131 byte* p = reinterpret_cast<byte*>(pc_); 132 int count = Assembler::RelocateInternalReference(p, delta); 133 CpuFeatures::FlushICache(p, count * sizeof(uint32_t)); 134 } 135} 136 137 138Address RelocInfo::target_address() { 139 DCHECK(IsCodeTarget(rmode_) || IsRuntimeEntry(rmode_)); 140 return Assembler::target_address_at(pc_, host_); 141} 142 143 144Address RelocInfo::target_address_address() { 145 DCHECK(IsCodeTarget(rmode_) || 146 IsRuntimeEntry(rmode_) || 147 rmode_ == EMBEDDED_OBJECT || 148 rmode_ == EXTERNAL_REFERENCE); 149 // Read the address of the word containing the target_address in an 150 // instruction stream. 151 // The only architecture-independent user of this function is the serializer. 152 // The serializer uses it to find out how many raw bytes of instruction to 153 // output before the next target. 154 // For an instruction like LUI/ORI where the target bits are mixed into the 155 // instruction bits, the size of the target will be zero, indicating that the 156 // serializer should not step forward in memory after a target is resolved 157 // and written. In this case the target_address_address function should 158 // return the end of the instructions to be patched, allowing the 159 // deserializer to deserialize the instructions as raw bytes and put them in 160 // place, ready to be patched with the target. After jump optimization, 161 // that is the address of the instruction that follows J/JAL/JR/JALR 162 // instruction. 163 return reinterpret_cast<Address>( 164 pc_ + Assembler::kInstructionsFor32BitConstant * Assembler::kInstrSize); 165} 166 167 168Address RelocInfo::constant_pool_entry_address() { 169 UNREACHABLE(); 170 return NULL; 171} 172 173 174int RelocInfo::target_address_size() { 175 return Assembler::kSpecialTargetSize; 176} 177 178 179void RelocInfo::set_target_address(Address target, 180 WriteBarrierMode write_barrier_mode, 181 ICacheFlushMode icache_flush_mode) { 182 DCHECK(IsCodeTarget(rmode_) || IsRuntimeEntry(rmode_)); 183 Assembler::set_target_address_at(pc_, host_, target, icache_flush_mode); 184 if (write_barrier_mode == UPDATE_WRITE_BARRIER && 185 host() != NULL && IsCodeTarget(rmode_)) { 186 Object* target_code = Code::GetCodeFromTargetAddress(target); 187 host()->GetHeap()->incremental_marking()->RecordWriteIntoCode( 188 host(), this, HeapObject::cast(target_code)); 189 } 190} 191 192 193Address Assembler::target_address_from_return_address(Address pc) { 194 return pc - kCallTargetAddressOffset; 195} 196 197 198Address Assembler::break_address_from_return_address(Address pc) { 199 return pc - Assembler::kPatchDebugBreakSlotReturnOffset; 200} 201 202 203Object* RelocInfo::target_object() { 204 DCHECK(IsCodeTarget(rmode_) || rmode_ == EMBEDDED_OBJECT); 205 return reinterpret_cast<Object*>(Assembler::target_address_at(pc_, host_)); 206} 207 208 209Handle<Object> RelocInfo::target_object_handle(Assembler* origin) { 210 DCHECK(IsCodeTarget(rmode_) || rmode_ == EMBEDDED_OBJECT); 211 return Handle<Object>(reinterpret_cast<Object**>( 212 Assembler::target_address_at(pc_, host_))); 213} 214 215 216void RelocInfo::set_target_object(Object* target, 217 WriteBarrierMode write_barrier_mode, 218 ICacheFlushMode icache_flush_mode) { 219 DCHECK(IsCodeTarget(rmode_) || rmode_ == EMBEDDED_OBJECT); 220 Assembler::set_target_address_at(pc_, host_, 221 reinterpret_cast<Address>(target), 222 icache_flush_mode); 223 if (write_barrier_mode == UPDATE_WRITE_BARRIER && 224 host() != NULL && 225 target->IsHeapObject()) { 226 host()->GetHeap()->incremental_marking()->RecordWrite( 227 host(), &Memory::Object_at(pc_), HeapObject::cast(target)); 228 } 229} 230 231 232Address RelocInfo::target_reference() { 233 DCHECK(rmode_ == EXTERNAL_REFERENCE); 234 return Assembler::target_address_at(pc_, host_); 235} 236 237 238Address RelocInfo::target_runtime_entry(Assembler* origin) { 239 DCHECK(IsRuntimeEntry(rmode_)); 240 return target_address(); 241} 242 243 244void RelocInfo::set_target_runtime_entry(Address target, 245 WriteBarrierMode write_barrier_mode, 246 ICacheFlushMode icache_flush_mode) { 247 DCHECK(IsRuntimeEntry(rmode_)); 248 if (target_address() != target) 249 set_target_address(target, write_barrier_mode, icache_flush_mode); 250} 251 252 253Handle<Cell> RelocInfo::target_cell_handle() { 254 DCHECK(rmode_ == RelocInfo::CELL); 255 Address address = Memory::Address_at(pc_); 256 return Handle<Cell>(reinterpret_cast<Cell**>(address)); 257} 258 259 260Cell* RelocInfo::target_cell() { 261 DCHECK(rmode_ == RelocInfo::CELL); 262 return Cell::FromValueAddress(Memory::Address_at(pc_)); 263} 264 265 266void RelocInfo::set_target_cell(Cell* cell, 267 WriteBarrierMode write_barrier_mode, 268 ICacheFlushMode icache_flush_mode) { 269 DCHECK(rmode_ == RelocInfo::CELL); 270 Address address = cell->address() + Cell::kValueOffset; 271 Memory::Address_at(pc_) = address; 272 if (write_barrier_mode == UPDATE_WRITE_BARRIER && host() != NULL) { 273 // TODO(1550) We are passing NULL as a slot because cell can never be on 274 // evacuation candidate. 275 host()->GetHeap()->incremental_marking()->RecordWrite( 276 host(), NULL, cell); 277 } 278} 279 280 281static const int kNoCodeAgeSequenceLength = 7 * Assembler::kInstrSize; 282 283 284Handle<Object> RelocInfo::code_age_stub_handle(Assembler* origin) { 285 UNREACHABLE(); // This should never be reached on Arm. 286 return Handle<Object>(); 287} 288 289 290Code* RelocInfo::code_age_stub() { 291 DCHECK(rmode_ == RelocInfo::CODE_AGE_SEQUENCE); 292 return Code::GetCodeFromTargetAddress( 293 Assembler::target_address_at(pc_ + Assembler::kInstrSize, host_)); 294} 295 296 297void RelocInfo::set_code_age_stub(Code* stub, 298 ICacheFlushMode icache_flush_mode) { 299 DCHECK(rmode_ == RelocInfo::CODE_AGE_SEQUENCE); 300 Assembler::set_target_address_at(pc_ + Assembler::kInstrSize, 301 host_, 302 stub->instruction_start()); 303} 304 305 306Address RelocInfo::call_address() { 307 DCHECK((IsJSReturn(rmode()) && IsPatchedReturnSequence()) || 308 (IsDebugBreakSlot(rmode()) && IsPatchedDebugBreakSlotSequence())); 309 // The pc_ offset of 0 assumes mips patched return sequence per 310 // debug-mips.cc BreakLocationIterator::SetDebugBreakAtReturn(), or 311 // debug break slot per BreakLocationIterator::SetDebugBreakAtSlot(). 312 return Assembler::target_address_at(pc_, host_); 313} 314 315 316void RelocInfo::set_call_address(Address target) { 317 DCHECK((IsJSReturn(rmode()) && IsPatchedReturnSequence()) || 318 (IsDebugBreakSlot(rmode()) && IsPatchedDebugBreakSlotSequence())); 319 // The pc_ offset of 0 assumes mips patched return sequence per 320 // debug-mips.cc BreakLocationIterator::SetDebugBreakAtReturn(), or 321 // debug break slot per BreakLocationIterator::SetDebugBreakAtSlot(). 322 Assembler::set_target_address_at(pc_, host_, target); 323 if (host() != NULL) { 324 Object* target_code = Code::GetCodeFromTargetAddress(target); 325 host()->GetHeap()->incremental_marking()->RecordWriteIntoCode( 326 host(), this, HeapObject::cast(target_code)); 327 } 328} 329 330 331Object* RelocInfo::call_object() { 332 return *call_object_address(); 333} 334 335 336Object** RelocInfo::call_object_address() { 337 DCHECK((IsJSReturn(rmode()) && IsPatchedReturnSequence()) || 338 (IsDebugBreakSlot(rmode()) && IsPatchedDebugBreakSlotSequence())); 339 return reinterpret_cast<Object**>(pc_ + 2 * Assembler::kInstrSize); 340} 341 342 343void RelocInfo::set_call_object(Object* target) { 344 *call_object_address() = target; 345} 346 347 348void RelocInfo::WipeOut() { 349 DCHECK(IsEmbeddedObject(rmode_) || 350 IsCodeTarget(rmode_) || 351 IsRuntimeEntry(rmode_) || 352 IsExternalReference(rmode_)); 353 Assembler::set_target_address_at(pc_, host_, NULL); 354} 355 356 357bool RelocInfo::IsPatchedReturnSequence() { 358 Instr instr0 = Assembler::instr_at(pc_); 359 Instr instr1 = Assembler::instr_at(pc_ + 1 * Assembler::kInstrSize); 360 Instr instr2 = Assembler::instr_at(pc_ + 2 * Assembler::kInstrSize); 361 bool patched_return = ((instr0 & kOpcodeMask) == LUI && 362 (instr1 & kOpcodeMask) == ORI && 363 ((instr2 & kOpcodeMask) == JAL || 364 ((instr2 & kOpcodeMask) == SPECIAL && 365 (instr2 & kFunctionFieldMask) == JALR))); 366 return patched_return; 367} 368 369 370bool RelocInfo::IsPatchedDebugBreakSlotSequence() { 371 Instr current_instr = Assembler::instr_at(pc_); 372 return !Assembler::IsNop(current_instr, Assembler::DEBUG_BREAK_NOP); 373} 374 375 376void RelocInfo::Visit(Isolate* isolate, ObjectVisitor* visitor) { 377 RelocInfo::Mode mode = rmode(); 378 if (mode == RelocInfo::EMBEDDED_OBJECT) { 379 visitor->VisitEmbeddedPointer(this); 380 } else if (RelocInfo::IsCodeTarget(mode)) { 381 visitor->VisitCodeTarget(this); 382 } else if (mode == RelocInfo::CELL) { 383 visitor->VisitCell(this); 384 } else if (mode == RelocInfo::EXTERNAL_REFERENCE) { 385 visitor->VisitExternalReference(this); 386 } else if (RelocInfo::IsCodeAgeSequence(mode)) { 387 visitor->VisitCodeAgeSequence(this); 388 } else if (((RelocInfo::IsJSReturn(mode) && 389 IsPatchedReturnSequence()) || 390 (RelocInfo::IsDebugBreakSlot(mode) && 391 IsPatchedDebugBreakSlotSequence())) && 392 isolate->debug()->has_break_points()) { 393 visitor->VisitDebugTarget(this); 394 } else if (RelocInfo::IsRuntimeEntry(mode)) { 395 visitor->VisitRuntimeEntry(this); 396 } 397} 398 399 400template<typename StaticVisitor> 401void RelocInfo::Visit(Heap* heap) { 402 RelocInfo::Mode mode = rmode(); 403 if (mode == RelocInfo::EMBEDDED_OBJECT) { 404 StaticVisitor::VisitEmbeddedPointer(heap, this); 405 } else if (RelocInfo::IsCodeTarget(mode)) { 406 StaticVisitor::VisitCodeTarget(heap, this); 407 } else if (mode == RelocInfo::CELL) { 408 StaticVisitor::VisitCell(heap, this); 409 } else if (mode == RelocInfo::EXTERNAL_REFERENCE) { 410 StaticVisitor::VisitExternalReference(this); 411 } else if (RelocInfo::IsCodeAgeSequence(mode)) { 412 StaticVisitor::VisitCodeAgeSequence(heap, this); 413 } else if (heap->isolate()->debug()->has_break_points() && 414 ((RelocInfo::IsJSReturn(mode) && 415 IsPatchedReturnSequence()) || 416 (RelocInfo::IsDebugBreakSlot(mode) && 417 IsPatchedDebugBreakSlotSequence()))) { 418 StaticVisitor::VisitDebugTarget(heap, this); 419 } else if (RelocInfo::IsRuntimeEntry(mode)) { 420 StaticVisitor::VisitRuntimeEntry(this); 421 } 422} 423 424 425// ----------------------------------------------------------------------------- 426// Assembler. 427 428 429void Assembler::CheckBuffer() { 430 if (buffer_space() <= kGap) { 431 GrowBuffer(); 432 } 433} 434 435 436void Assembler::CheckTrampolinePoolQuick() { 437 if (pc_offset() >= next_buffer_check_) { 438 CheckTrampolinePool(); 439 } 440} 441 442 443void Assembler::emit(Instr x) { 444 if (!is_buffer_growth_blocked()) { 445 CheckBuffer(); 446 } 447 *reinterpret_cast<Instr*>(pc_) = x; 448 pc_ += kInstrSize; 449 CheckTrampolinePoolQuick(); 450} 451 452 453} } // namespace v8::internal 454 455#endif // V8_MIPS_ASSEMBLER_MIPS_INL_H_ 456