1
2/*---------------------------------------------------------------*/
3/*--- begin                                  guest_arm_defs.h ---*/
4/*---------------------------------------------------------------*/
5/*
6   This file is part of Valgrind, a dynamic binary instrumentation
7   framework.
8
9   Copyright (C) 2004-2015 OpenWorks LLP
10      info@open-works.net
11
12   This program is free software; you can redistribute it and/or
13   modify it under the terms of the GNU General Public License as
14   published by the Free Software Foundation; either version 2 of the
15   License, or (at your option) any later version.
16
17   This program is distributed in the hope that it will be useful, but
18   WITHOUT ANY WARRANTY; without even the implied warranty of
19   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
20   General Public License for more details.
21
22   You should have received a copy of the GNU General Public License
23   along with this program; if not, write to the Free Software
24   Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
25   02110-1301, USA.
26
27   The GNU General Public License is contained in the file COPYING.
28*/
29
30/* Only to be used within the guest-arm directory. */
31
32#ifndef __VEX_GUEST_ARM_DEFS_H
33#define __VEX_GUEST_ARM_DEFS_H
34
35#include "libvex_basictypes.h"
36#include "guest_generic_bb_to_IR.h"     // DisResult
37
38/*---------------------------------------------------------*/
39/*--- arm to IR conversion                              ---*/
40/*---------------------------------------------------------*/
41
42/* Convert one ARM insn to IR.  See the type DisOneInstrFn in
43   bb_to_IR.h. */
44extern
45DisResult disInstr_ARM ( IRSB*        irbb,
46                         Bool         (*resteerOkFn) ( void*, Addr ),
47                         Bool         resteerCisOk,
48                         void*        callback_opaque,
49                         const UChar* guest_code,
50                         Long         delta,
51                         Addr         guest_IP,
52                         VexArch      guest_arch,
53                         const VexArchInfo* archinfo,
54                         const VexAbiInfo*  abiinfo,
55                         VexEndness   host_endness,
56                         Bool         sigill_diag );
57
58/* Used by the optimiser to specialise calls to helpers. */
59extern
60IRExpr* guest_arm_spechelper ( const HChar* function_name,
61                               IRExpr** args,
62                               IRStmt** precedingStmts,
63                               Int      n_precedingStmts );
64
65/* Describes to the optimser which part of the guest state require
66   precise memory exceptions.  This is logically part of the guest
67   state description. */
68extern
69Bool guest_arm_state_requires_precise_mem_exns ( Int, Int,
70                                                 VexRegisterUpdates );
71
72extern
73VexGuestLayout armGuest_layout;
74
75
76/*---------------------------------------------------------*/
77/*--- arm guest helpers                                 ---*/
78/*---------------------------------------------------------*/
79
80/* --- CLEAN HELPERS --- */
81
82/* Calculate NZCV from the supplied thunk components, in the positions
83   they appear in the CPSR, viz bits 31:28 for N Z V C respectively.
84   Returned bits 27:0 are zero. */
85extern
86UInt armg_calculate_flags_nzcv ( UInt cc_op, UInt cc_dep1,
87                                 UInt cc_dep2, UInt cc_dep3 );
88
89/* Calculate the C flag from the thunk components, in the lowest bit
90   of the word (bit 0). */
91extern
92UInt armg_calculate_flag_c ( UInt cc_op, UInt cc_dep1,
93                             UInt cc_dep2, UInt cc_dep3 );
94
95/* Calculate the V flag from the thunk components, in the lowest bit
96   of the word (bit 0). */
97extern
98UInt armg_calculate_flag_v ( UInt cc_op, UInt cc_dep1,
99                             UInt cc_dep2, UInt cc_dep3 );
100
101/* Calculate the specified condition from the thunk components, in the
102   lowest bit of the word (bit 0). */
103extern
104UInt armg_calculate_condition ( UInt cond_n_op /* ARMCondcode << 4 | cc_op */,
105                                UInt cc_dep1,
106                                UInt cc_dep2, UInt cc_dep3 );
107
108/* Calculate the QC flag from the thunk components, in the lowest bit
109   of the word (bit 0). */
110extern
111UInt armg_calculate_flag_qc ( UInt resL1, UInt resL2,
112                              UInt resR1, UInt resR2 );
113
114
115/*---------------------------------------------------------*/
116/*--- Condition code stuff                              ---*/
117/*---------------------------------------------------------*/
118
119/* Flags masks.  Defines positions of flags bits in the CPSR. */
120#define ARMG_CC_SHIFT_N  31
121#define ARMG_CC_SHIFT_Z  30
122#define ARMG_CC_SHIFT_C  29
123#define ARMG_CC_SHIFT_V  28
124#define ARMG_CC_SHIFT_Q  27
125
126#define ARMG_CC_MASK_N    (1 << ARMG_CC_SHIFT_N)
127#define ARMG_CC_MASK_Z    (1 << ARMG_CC_SHIFT_Z)
128#define ARMG_CC_MASK_C    (1 << ARMG_CC_SHIFT_C)
129#define ARMG_CC_MASK_V    (1 << ARMG_CC_SHIFT_V)
130#define ARMG_CC_MASK_Q    (1 << ARMG_CC_SHIFT_Q)
131
132/* Flag thunk descriptors.  A four-word thunk is used to record
133   details of the most recent flag-setting operation, so NZCV can
134   be computed later if needed.
135
136   The four words are:
137
138      CC_OP, which describes the operation.
139
140      CC_DEP1, CC_DEP2, CC_DEP3.  These are arguments to the
141         operation.  We want set up the mcx_masks in flag helper calls
142         involving these fields so that Memcheck "believes" that the
143         resulting flags are data-dependent on both CC_DEP1 and
144         CC_DEP2.  Hence the name DEP.
145
146   When building the thunk, it is always necessary to write words into
147   CC_DEP1/2/3, even if those args are not used given the
148   CC_OP field.  This is important because otherwise Memcheck could
149   give false positives as it does not understand the relationship
150   between the CC_OP field and CC_DEP1/2/3, and so believes
151   that the definedness of the stored flags always depends on
152   all 3 DEP values.
153
154   Fields carrying only 1 or 2 bits of useful information (old_C,
155   shifter_co, old_V, oldC:oldV) must have their top 31 or 30 bits
156   (respectively) zero.  The text "31x0:" or "30x0:" denotes this.
157
158   A summary of the field usages is:
159
160   OP                DEP1              DEP2              DEP3
161   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
162
163   OP_COPY           curr_NZCV:28x0    unused            unused
164   OP_ADD            argL              argR              unused
165   OP_SUB            argL              argR              unused
166   OP_ADC            argL              argR              31x0:old_C
167   OP_SBB            argL              argR              31x0:old_C
168   OP_LOGIC          result            31x0:shifter_co   31x0:old_V
169   OP_MUL            result            unused            30x0:old_C:old_V
170   OP_MULL           resLO32           resHI32           30x0:old_C:old_V
171*/
172
173enum {
174   ARMG_CC_OP_COPY=0,  /* DEP1 = NZCV in 31:28, DEP2 = 0, DEP3 = 0
175                          just copy DEP1 to output */
176
177   ARMG_CC_OP_ADD,     /* DEP1 = argL (Rn), DEP2 = argR (shifter_op),
178                          DEP3 = 0 */
179
180   ARMG_CC_OP_SUB,     /* DEP1 = argL (Rn), DEP2 = argR (shifter_op),
181                          DEP3 = 0 */
182
183   ARMG_CC_OP_ADC,     /* DEP1 = argL (Rn), DEP2 = arg2 (shifter_op),
184                          DEP3 = oldC (in LSB) */
185
186   ARMG_CC_OP_SBB,     /* DEP1 = argL (Rn), DEP2 = arg2 (shifter_op),
187                          DEP3 = oldC (in LSB) */
188
189   ARMG_CC_OP_LOGIC,   /* DEP1 = result, DEP2 = shifter_carry_out (in LSB),
190                          DEP3 = old V flag (in LSB) */
191
192   ARMG_CC_OP_MUL,     /* DEP1 = result, DEP2 = 0, DEP3 = oldC:old_V
193                          (in bits 1:0) */
194
195   ARMG_CC_OP_MULL,    /* DEP1 = resLO32, DEP2 = resHI32, DEP3 = oldC:old_V
196                          (in bits 1:0) */
197
198   ARMG_CC_OP_NUMBER
199};
200
201/* XXXX because of the calling conventions for
202   armg_calculate_condition, all this OP values MUST be in the range
203   0 .. 15 only (viz, 4-bits). */
204
205
206
207/* Defines conditions which we can ask for (ARM ARM 2e page A3-6) */
208
209typedef
210   enum {
211      ARMCondEQ     = 0,  /* equal                         : Z=1 */
212      ARMCondNE     = 1,  /* not equal                     : Z=0 */
213
214      ARMCondHS     = 2,  /* >=u (higher or same)          : C=1 */
215      ARMCondLO     = 3,  /* <u  (lower)                   : C=0 */
216
217      ARMCondMI     = 4,  /* minus (negative)              : N=1 */
218      ARMCondPL     = 5,  /* plus (zero or +ve)            : N=0 */
219
220      ARMCondVS     = 6,  /* overflow                      : V=1 */
221      ARMCondVC     = 7,  /* no overflow                   : V=0 */
222
223      ARMCondHI     = 8,  /* >u   (higher)                 : C=1 && Z=0 */
224      ARMCondLS     = 9,  /* <=u  (lower or same)          : C=0 || Z=1 */
225
226      ARMCondGE     = 10, /* >=s (signed greater or equal) : N=V */
227      ARMCondLT     = 11, /* <s  (signed less than)        : N!=V */
228
229      ARMCondGT     = 12, /* >s  (signed greater)          : Z=0 && N=V */
230      ARMCondLE     = 13, /* <=s (signed less or equal)    : Z=1 || N!=V */
231
232      ARMCondAL     = 14, /* always (unconditional)        : 1 */
233      ARMCondNV     = 15  /* never (unconditional):        : 0 */
234      /* NB: ARM have deprecated the use of the NV condition code.
235         You are now supposed to use MOV R0,R0 as a noop rather than
236         MOVNV R0,R0 as was previously recommended.  Future processors
237         may have the NV condition code reused to do other things.  */
238   }
239   ARMCondcode;
240
241#endif /* ndef __VEX_GUEST_ARM_DEFS_H */
242
243/*---------------------------------------------------------------*/
244/*--- end                                    guest_arm_defs.h ---*/
245/*---------------------------------------------------------------*/
246